An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Scala 2.4k 932
An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast
Python 111 32
Berkeley's Spatial Array Generator
Scala 1.5k 302
Hammer: Highly Agile Masks Made Effortlessly from RTL
Python 329 81
A Heterogeneous GPU Platform for AI and Neural Graphics
Scala 70 7
Chisel RISC-V Vector 1.0 Implementation
Assembly 159 42
Gemmini (& Variants) MLIR dialect
MLIR-in as a compiler stack for ucb-bar
Blast your models
Gemmini extensions for Spike
MLIR dialect for Atlas.
A simple FPGA SoC generation framework with Chisel and Mill.
Any model in Torch or JAX format to MLIR frontend dialects.
Statically scheduled Neural Processing Unit