distributed: guard x86 cache-flush intrinsics for aarch64#43940
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blozano-tt wants to merge 3 commits intomainfrom
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distributed: guard x86 cache-flush intrinsics for aarch64#43940blozano-tt wants to merge 3 commits intomainfrom
blozano-tt wants to merge 3 commits intomainfrom
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d2h_socket.cpp unconditionally included <immintrin.h> and called _mm_clflush/_mm_lfence, which are x86-only. This breaks builds on Linux/aarch64 (introduced in #42905). Replace the bare x86 intrinsics with inline host_clflush/host_lfence helpers that dispatch to the correct ISA: - x86/x86-64: _mm_clflush + _mm_lfence (unchanged semantics) - aarch64: DC CIVAC (clean+invalidate to PoC) + DSB ISH - other: #error to catch future ports early Also rename k_x86_clflush_line_bytes -> k_host_clflush_line_bytes since cache lines are 64 B on both supported arches.
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Pull request overview
This PR fixes tt_metal/distributed/d2h_socket.cpp failing to compile on Linux/aarch64 by guarding x86-only cache flush intrinsics and providing architecture-specific inline helpers for cache line flush + read-serialization in the hugepage fallback path.
Changes:
- Replaces unconditional
<immintrin.h>usage and direct_mm_clflush/_mm_lfencecalls withhost_clflush()/host_lfence()wrappers selected per-architecture. - Adds an aarch64 implementation using
dc civac(cache line clean+invalidate) anddsb ish(barrier). - Renames the cache-line stride constant to
k_host_clflush_line_bytesand uses it for flush loops.
| // DSB ISH: data synchronisation barrier, inner-shareable domain. | ||
| asm volatile("dsb ish" ::: "memory"); | ||
| } | ||
| constexpr uint32_t k_host_clflush_line_bytes = 64; // typical ARM64 D-cache line |
…nsics d2h_socket.cpp unconditionally included <immintrin.h> and used _mm_clflush/_mm_lfence, which are x86-only. This broke aarch64 builds (introduced in #42905). The hugepage D2H path (using_hugepage_ == true) requires explicit cache-line eviction because WH device PCIe writes may be non-snooped. Correct handling of WB + no-snoop DMA is inherently x86-specific and fragile; attempting to replicate it on other architectures would be unsound. Fix: - Guard #include <immintrin.h> with __x86_64__ / __i386__ - On other arches, provide stubs that TT_THROW so the translation unit compiles but the unreachable paths remain loud if ever hit - TT_FATAL at the top of init_host_buffer_hugepage() on non-x86, because WH (the only arch that sets using_hugepage_) is x86-only The x86 _mm_clflush / _mm_lfence code is left untouched.
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Problem
d2h_socket.cppunconditionally includes<immintrin.h>and calls_mm_clflush/_mm_lfence, which are x86-only intrinsics. This breaksLinux/aarch64builds with a wall of errors from clang-20:Introduced in #42905.
Fix
Replace the bare x86 intrinsics with thin inline helpers (
host_clflush/host_lfence) that dispatch to the correct ISA:_mm_clflush_mm_lfenceDC CIVAC(clean+invalidate to PoC)DSB ISH#errorAlso renames
k_x86_clflush_line_bytes→k_host_clflush_line_bytes(cache lines are 64 B on both supported arches, so the value is unchanged).Notes for reviewers
DC CIVAC+DSB ISHis the standard aarch64 equivalent of clflush+lfence for observing device DMA writes through host-mapped memory. Same semantics.using_hugepage_path (which contains all these calls) is only reachable whencan_use_pinned_memoryis false — not expected on aarch64 production hardware, but the code must at least compile.--without-distributeddoes not skip compiling this file (it only gates MPI linking); that is a separate issue.🧠 Fixed by BrAIn — my neurons fired on all architectures for once.
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