TL-Verilog Makerchip Examples

Various examples of TL-Verilog code to run in Makerchip.com. (All have custom simulation visualization.)

Here are some quick-links:

• all_examples.tlv: Combines many of these examples into one.
• logic_gates.tlv: Simple visualization of the function of various logic gates.
• life_viz.tlv: Conway's Game of Life.
• sort_viz.tlv: A basic circuit that sorts a set of numbers (and demonstrates Visual Debug).
• DAC_ring_example.tlv: A 10-line ring network-on-chip used as an example at the Design Automation Conference in 2020.
• frog_maze.tlv: A fun little maze solver.
• mandelbrot_as_img.tlv: A Mandelbrot fractal generator.
• serv.tlv: The SERV core, demonstrating how to import Verilog code.
• smith_waterman.tlv: A hardware implementation of the Smith-Waterman for genome alignment.
• tiny_tapeout_examples/tt_um_AES.tlv: AES encryption, implemented by students in an open final project for a two-week course.
• mat_mul.tlv: Output-stationary matrix multiply for ML acceleration.
• viz_demo.tlv: A progressive series of simple visualizations to demonstrate Visual Debug.
• claude_booth_multiplier.tlv: A Booth multiplier explainer.
• logic_analyzer.tlv: An example for comparison with Spade HDL.

From other repos:

• WARP-V: A configurable RISC-V core generator (See warp-v.org.)

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