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Merged
mr-c merged 1 commit into from
Sep 16, 2026
Merged

arm/neon: add LSX implementations #1447

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2 changes: 2 additions & 0 deletions simde/arm/neon/abs.h
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Expand Up @@ -431,6 +431,8 @@ simde_vabsq_s16(simde_int16x8_t a) {
r_.v128 = wasm_i16x8_abs(a_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmax_vv_i16m1(a_.sv128 , __riscv_vneg_v_i16m1(a_.sv128 , 8) , 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vsigncov_h(a_.m128i, a_.m128i);
#elif (SIMDE_NATURAL_VECTOR_SIZE > 0) && defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
__typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT16_C(0));
r_.values = (-a_.values & m) | (a_.values & ~m);
Expand Down
26 changes: 26 additions & 0 deletions simde/arm/neon/add.h
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Expand Up @@ -182,6 +182,8 @@ simde_vadd_s8(simde_int8x8_t a, simde_int8x8_t b) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vadd_vv_i8m1(a_.sv64, b_.sv64, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_x_lsx_store64(&r_.values, __lsx_vadd_b(simde_x_lsx_load64(&a_.values), simde_x_lsx_load64(&b_.values)));
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#elif defined(SIMDE_X86_MMX_NATIVE)
Expand Down Expand Up @@ -214,6 +216,8 @@ simde_vadd_s16(simde_int16x4_t a, simde_int16x4_t b) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vadd_vv_i16m1(a_.sv64, b_.sv64, 4);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_x_lsx_store64(&r_.values, __lsx_vadd_h(simde_x_lsx_load64(&a_.values), simde_x_lsx_load64(&b_.values)));
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#elif defined(SIMDE_X86_MMX_NATIVE)
Expand Down Expand Up @@ -246,6 +250,8 @@ simde_vadd_s32(simde_int32x2_t a, simde_int32x2_t b) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vadd_vv_i32m1(a_.sv64, b_.sv64, 2);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_x_lsx_store64(&r_.values, __lsx_vadd_w(simde_x_lsx_load64(&a_.values), simde_x_lsx_load64(&b_.values)));
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#elif defined(SIMDE_X86_MMX_NATIVE)
Expand Down Expand Up @@ -278,6 +284,8 @@ simde_vadd_s64(simde_int64x1_t a, simde_int64x1_t b) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vadd_vv_i64m1(a_.sv64, b_.sv64, 1);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_x_lsx_store64(&r_.values, __lsx_vadd_d(simde_x_lsx_load64(&a_.values), simde_x_lsx_load64(&b_.values)));
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#else
Expand Down Expand Up @@ -308,6 +316,8 @@ simde_vadd_u8(simde_uint8x8_t a, simde_uint8x8_t b) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vadd_vv_u8m1(a_.sv64, b_.sv64, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_x_lsx_store64(&r_.values, __lsx_vadd_b(simde_x_lsx_load64(&a_.values), simde_x_lsx_load64(&b_.values)));
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#else
Expand Down Expand Up @@ -339,6 +349,8 @@ simde_vadd_u16(simde_uint16x4_t a, simde_uint16x4_t b) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vadd_vv_u16m1(a_.sv64, b_.sv64, 4);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_x_lsx_store64(&r_.values, __lsx_vadd_h(simde_x_lsx_load64(&a_.values), simde_x_lsx_load64(&b_.values)));
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#else
Expand Down Expand Up @@ -369,6 +381,8 @@ simde_vadd_u32(simde_uint32x2_t a, simde_uint32x2_t b) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vadd_vv_u32m1(a_.sv64, b_.sv64, 2);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_x_lsx_store64(&r_.values, __lsx_vadd_w(simde_x_lsx_load64(&a_.values), simde_x_lsx_load64(&b_.values)));
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#else
Expand Down Expand Up @@ -399,6 +413,8 @@ simde_vadd_u64(simde_uint64x1_t a, simde_uint64x1_t b) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vadd_vv_u64m1(a_.sv64, b_.sv64, 1);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_x_lsx_store64(&r_.values, __lsx_vadd_d(simde_x_lsx_load64(&a_.values), simde_x_lsx_load64(&b_.values)));
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#else
Expand Down Expand Up @@ -540,6 +556,8 @@ simde_vaddq_s8(simde_int8x16_t a, simde_int8x16_t b) {
r_.v128 = wasm_i8x16_add(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vadd_vv_i8m1(a_.sv128, b_.sv128, 16);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vadd_b(a_.m128i, b_.m128i);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#else
Expand Down Expand Up @@ -576,6 +594,8 @@ simde_vaddq_s16(simde_int16x8_t a, simde_int16x8_t b) {
r_.v128 = wasm_i16x8_add(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vadd_vv_i16m1(a_.sv128, b_.sv128, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vadd_h(a_.m128i, b_.m128i);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#else
Expand Down Expand Up @@ -612,6 +632,8 @@ simde_vaddq_s32(simde_int32x4_t a, simde_int32x4_t b) {
r_.v128 = wasm_i32x4_add(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vadd_vv_i32m1(a_.sv128, b_.sv128, 4);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vadd_w(a_.m128i, b_.m128i);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#else
Expand Down Expand Up @@ -680,6 +702,8 @@ simde_vaddq_u8(simde_uint8x16_t a, simde_uint8x16_t b) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vadd_vv_u8m1(a_.sv128, b_.sv128, 16);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vadd_b(a_.m128i, b_.m128i);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#else
Expand Down Expand Up @@ -712,6 +736,8 @@ simde_vaddq_u16(simde_uint16x8_t a, simde_uint16x8_t b) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vadd_vv_u16m1(a_.sv128, b_.sv128, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vadd_h(a_.m128i, b_.m128i);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values + b_.values;
#else
Expand Down
16 changes: 16 additions & 0 deletions simde/arm/neon/addhn.h
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Expand Up @@ -84,6 +84,14 @@ simde_vaddhn_s32(simde_int32x4_t a, simde_int32x4_t b) {
r_.values = __builtin_shufflevector(tmp_.values, tmp_.values, 0, 2, 4, 6);
#endif
return simde_int16x4_from_private(r_);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_int32x4_private
a_ = simde_int32x4_to_private(a),
b_ = simde_int32x4_to_private(b);
simde_int16x4_private r_;
__m128i sum = __lsx_vadd_w(a_.m128i, b_.m128i);
simde_x_lsx_store64(&r_.values, __lsx_vssrani_h_w(sum, sum, 16));
return simde_int16x4_from_private(r_);
#else
return simde_vmovn_s32(simde_vshrq_n_s32(simde_vaddq_s32(a, b), 16));
#endif
Expand All @@ -98,6 +106,14 @@ simde_int32x2_t
simde_vaddhn_s64(simde_int64x2_t a, simde_int64x2_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vaddhn_s64(a, b);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_int64x2_private
a_ = simde_int64x2_to_private(a),
b_ = simde_int64x2_to_private(b);
simde_int32x2_private r_;
__m128i sum = __lsx_vadd_d(a_.m128i, b_.m128i);
simde_x_lsx_store64(&r_.values, __lsx_vssrani_w_d(sum, sum, 32));
return simde_int32x2_from_private(r_);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_NO_SHUFFLE_VECTOR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
simde_int32x2_private r_;
simde_int32x4_private tmp_ =
Expand Down
5 changes: 5 additions & 0 deletions simde/arm/neon/addv.h
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Expand Up @@ -168,6 +168,11 @@ simde_vaddv_u8(simde_uint8x8_t a) {
vuint8m1_t zero = __riscv_vmv_v_x_u8m1(0 , 1);
vuint8m1_t sum = __riscv_vredsum_vs_u8m1_u8m1(a_.sv64 , zero , 8);
r = __riscv_vmv_x_s_u8m1_u8 (sum);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
__m128i tmp = __lsx_vhaddw_hu_bu(simde_x_lsx_load64(&a_.values), simde_x_lsx_load64(&a_.values));
tmp = __lsx_vhaddw_wu_hu(tmp, tmp);
tmp = __lsx_vhaddw_du_wu(tmp, tmp);
r = HEDLEY_STATIC_CAST(uint8_t, __lsx_vpickve2gr_b(tmp, 0));
#else
r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r)
Expand Down
6 changes: 6 additions & 0 deletions simde/arm/neon/addw.h
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Expand Up @@ -141,6 +141,12 @@ simde_uint16x8_t
simde_vaddw_u8(simde_uint16x8_t a, simde_uint8x8_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vaddw_u8(a, b);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_uint16x8_private r_;
simde_uint16x8_private a_ = simde_uint16x8_to_private(a);
simde_uint8x8_private b_ = simde_uint8x8_to_private(b);
r_.m128i = __lsx_vadd_h(a_.m128i, __lsx_vsllwil_hu_bu(simde_x_lsx_load64(&b_.values), 0));
return simde_uint16x8_from_private(r_);
#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddq_u16(a, simde_vmovl_u8(b));
#else
Expand Down
2 changes: 2 additions & 0 deletions simde/arm/neon/and.h
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Expand Up @@ -453,6 +453,8 @@ simde_vandq_u8(simde_uint8x16_t a, simde_uint8x16_t b) {
r_.v128 = wasm_v128_and(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vand_vv_u8m1(a_.sv128, b_.sv128, 16);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vand_v(a_.m128i, b_.m128i);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down
10 changes: 7 additions & 3 deletions simde/arm/neon/clz.h
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Expand Up @@ -315,9 +315,13 @@ simde_vclzq_s16(simde_int16x8_t a) {
a_ = simde_int16x8_to_private(a),
r_;

for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = simde_x_vclzh_s16(a_.values[i]);
}
#if defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vclz_h(a_.m128i);
#else
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = simde_x_vclzh_s16(a_.values[i]);
}
#endif

return simde_int16x8_from_private(r_);
#endif
Expand Down
12 changes: 8 additions & 4 deletions simde/arm/neon/cnt.h
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Expand Up @@ -93,10 +93,14 @@ simde_vcnt_u8(simde_uint8x8_t a) {
r_,
a_ = simde_uint8x8_to_private(a);

SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = simde_x_arm_neon_cntb(a_.values[i]);
}
#if defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_x_lsx_store64(&r_.values, __lsx_vpcnt_b(simde_x_lsx_load64(&a_.values)));
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = simde_x_arm_neon_cntb(a_.values[i]);
}
#endif

return simde_uint8x8_from_private(r_);
#endif
Expand Down
8 changes: 8 additions & 0 deletions simde/arm/neon/combine.h
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Expand Up @@ -145,6 +145,8 @@ simde_vcombine_s8(simde_int8x8_t low, simde_int8x8_t high) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vslideup_vx_i8m1(low_.sv64, high_.sv64, 8, 16);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vilvl_d(simde_x_lsx_load64(&high_.values), simde_x_lsx_load64(&low_.values));
#elif defined(SIMDE_VECTOR_SUBSCRIPT) && !defined(SIMDE_NO_SHUFFLE_VECTOR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(low_.values, high_.values, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
#else
Expand Down Expand Up @@ -177,6 +179,8 @@ simde_vcombine_s16(simde_int16x4_t low, simde_int16x4_t high) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vslideup_vx_i16m1(low_.sv64, high_.sv64, 4, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vilvl_d(simde_x_lsx_load64(&high_.values), simde_x_lsx_load64(&low_.values));
#elif defined(SIMDE_VECTOR_SUBSCRIPT) && !defined(SIMDE_NO_SHUFFLE_VECTOR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(low_.values, high_.values, 0, 1, 2, 3, 4, 5, 6, 7);
#else
Expand Down Expand Up @@ -273,6 +277,8 @@ simde_vcombine_u8(simde_uint8x8_t low, simde_uint8x8_t high) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vslideup_vx_u8m1(low_.sv64, high_.sv64, 8, 16);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vilvl_d(simde_x_lsx_load64(&high_.values), simde_x_lsx_load64(&low_.values));
#elif defined(SIMDE_VECTOR_SUBSCRIPT) && !defined(SIMDE_NO_SHUFFLE_VECTOR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(low_.values, high_.values, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
#else
Expand Down Expand Up @@ -305,6 +311,8 @@ simde_vcombine_u16(simde_uint16x4_t low, simde_uint16x4_t high) {

#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vslideup_vx_u16m1(low_.sv64, high_.sv64, 4, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vilvl_d(simde_x_lsx_load64(&high_.values), simde_x_lsx_load64(&low_.values));
#elif defined(SIMDE_VECTOR_SUBSCRIPT) && !defined(SIMDE_NO_SHUFFLE_VECTOR) && HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(low_.values, high_.values, 0, 1, 2, 3, 4, 5, 6, 7);
#else
Expand Down
12 changes: 12 additions & 0 deletions simde/arm/neon/dup_n.h
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Expand Up @@ -244,6 +244,8 @@ simde_vdup_n_u8(uint8_t value) {
r_.m64 = _mm_set1_pi8(HEDLEY_STATIC_CAST(int8_t, value));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vmv_v_x_u8m1(value, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
simde_x_lsx_store64(&r_.values, __lsx_vreplgr2vr_b(HEDLEY_STATIC_CAST(int8_t, value)));
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
Expand Down Expand Up @@ -495,6 +497,8 @@ simde_vdupq_n_s16(int16_t value) {
r_.v128 = wasm_i16x8_splat(value);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmv_v_x_i16m1(value, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vreplgr2vr_h(value);
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
Expand Down Expand Up @@ -597,6 +601,8 @@ simde_vdupq_n_u8(uint8_t value) {
r_.v128 = wasm_i8x16_splat(HEDLEY_STATIC_CAST(int8_t, value));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmv_v_x_u8m1(value, 16);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vreplgr2vr_b(HEDLEY_STATIC_CAST(int8_t, value));
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
Expand Down Expand Up @@ -631,6 +637,8 @@ simde_vdupq_n_u16(uint16_t value) {
r_.v128 = wasm_i16x8_splat(HEDLEY_STATIC_CAST(int16_t, value));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmv_v_x_u16m1(value, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vreplgr2vr_h(HEDLEY_STATIC_CAST(int16_t, value));
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
Expand Down Expand Up @@ -665,6 +673,8 @@ simde_vdupq_n_u32(uint32_t value) {
r_.v128 = wasm_i32x4_splat(HEDLEY_STATIC_CAST(int32_t, value));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmv_v_x_u32m1(value, 4);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vreplgr2vr_w(value);
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
Expand Down Expand Up @@ -699,6 +709,8 @@ simde_vdupq_n_u64(uint64_t value) {
r_.v128 = wasm_i64x2_splat(HEDLEY_STATIC_CAST(int64_t, value));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmv_v_x_u64m1(value, 2);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vreplgr2vr_d(value);
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
Expand Down
4 changes: 4 additions & 0 deletions simde/arm/neon/eor.h
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Expand Up @@ -348,6 +348,8 @@ simde_veorq_s16(simde_int16x8_t a, simde_int16x8_t b) {
r_.v128 = wasm_v128_xor(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vxor_vv_i16m1(a_.sv128, b_.sv128, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vxor_v(a_.m128i, b_.m128i);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values ^ b_.values;
#else
Expand Down Expand Up @@ -492,6 +494,8 @@ simde_veorq_u16(simde_uint16x8_t a, simde_uint16x8_t b) {
r_.v128 = wasm_v128_xor(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vxor_vv_u16m1(a_.sv128, b_.sv128, 8);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.m128i = __lsx_vxor_v(a_.m128i, b_.m128i);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values ^ b_.values;
#else
Expand Down
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