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Instruction memory uses LC #13
Description
I believe that in https://github.com/physical-computation/RV32I_iCE40/blob/master/verilog/instruction_mem.v#L13:
assign out = instruction_memory[addr >> 2];Is not getting synthesised as BRAM. To fix this I think this line may need to be moved into an always block.
Activity
rjlv2 commentedon May 5, 2019
The instruction memory is written as combinational logic (and is not clocked, BRAM requires a clock). The limited amount of BRAM available is used in the general purpose registers and data memory.
Making instruction memory work using BRAM can be a future improvement.