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Fix verilog_reader importing NOR and XNOR assignments as constant zero - #713
vera-rubin wants to merge 4 commits into
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lorina dispatches `assign y = ~( a | b );` and `assign y = ~( a ^ b );` to `on_nor` and `on_xnor`, but `verilog_reader` did not override them, so the inherited empty callbacks left the left-hand side undefined and the outputs were later created as constant 0. Add `on_nor` and `on_xnor` following `on_nand`. They negate `create_or` and `create_xor`, since not every network implements `create_nor` or `create_xnor` (e.g. `klut_network`, `mig_network`).
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## master #713 +/- ##
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- Coverage 84.10% 84.08% -0.02%
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Files 191 191
Lines 29579 29608 +29
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+ Hits 24876 24895 +19
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Thank you for the PR. Why don't we use create_nor and create_xnor? Probably we don't need the function description comment for this file. |
mig_network has no create_xnor and klut_network has neither, so fall back to create_not of create_or/create_xor when has_create_nor_v / has_create_xnor_v is false.
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Thanks! Done: it now uses |
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If we support those network types then probably we should also add a fallback for the earlier create_nand. It would be also nicer if test covers other network types (klut and perhaps aig) to check both regular and fallback paths. |
Use create_nand when available, otherwise negate create_and in the same style as the NOR and XNOR callbacks. Run the assignment regression on AIG, XAG, MIG, k-LUT, XMG and MuxIG, plus a test-only k-LUT variant without create_nand to exercise the fallback.
The reader's missing NOR and XNOR callbacks imported these assignments as constant zero. We add the callbacks and use native NAND, NOR and XNOR creation when available, with equivalent fallbacks otherwise. Tests cover native and fallback paths in AIG, k-LUT, MIG and the other reader networks, and the full suite passes before and after.
Fixes #712
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