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Enable D4XX frame-sync updates, ISX031 exposure controls/fixes, and supporting documentation refresh - #54

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khaiwenng merged 6 commits into
intel:mainfrom
vunnyso:vs-external-port-20260910
Sep 10, 2026
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Enable D4XX frame-sync updates, ISX031 exposure controls/fixes, and supporting documentation refresh#54
khaiwenng merged 6 commits into
intel:mainfrom
vunnyso:vs-external-port-20260910

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@vunnyso vunnyso commented Sep 10, 2026

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Description of changes

  1. Add ISX031 auto/manual exposure controls
  2. Fix ISX031 multi-byte register endianness handling
  3. Add D4XX frame-sync MFP1 configuration for RGB sync input
  4. Document kernel dependency expectations for ACPI kernelspace flow
  5. Refresh validated sensor symbols/status in project documentation
  6. Apply minor D4XX documentation table fixes

khaiwenng and others added 6 commits September 10, 2026 15:45
RGB is using MFP1 as frame sync input.

Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
Fix table structure.

Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
Update the sensor list to match current supported configuration.

Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
SSDT ASL method has dependency on I2C_ATR module.
Add the section to specify the need to rebuild kernel
if the kernel module is missing.

Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
Expose V4L2 controls to switch between automatic and manual exposure on
ISX031 and to program the manual exposure time.

- add V4L2_CID_EXPOSURE_AUTO to select AEMODE (auto vs. FULL_ME)
- add V4L2_CID_EXPOSURE to program the shutter value (SP1 + SP2) in
  microseconds when in manual mode
- activate/deactivate the exposure control based on the selected AE
  mode and reject AEMODE changes while streaming
- read AEMODE and SHTVAL back from the sensor so cached V4L2 values
  reflect the hardware state

Signed-off-by: Sodhi, Vunny <vunny.sodhi@intel.com>
The isx031_write_reg() and isx031_read_reg() helpers serialized
multi-byte values in big-endian order, but the ISX031 sensor uses
little-endian layout for its multi-byte registers (LSB at the lower
address). This is confirmed by the D3 reference driver, which
configures its 16-bit and 32-bit regmaps with
val_format_endian = REGMAP_ENDIAN_LITTLE, and by this driver's own
mode init tables (e.g. H size 1920 written as 0x8AAA=0x80,
0x8AAB=0x07).

As a result, every 2- and 4-byte control write reached the sensor
with swapped bytes. The most visible symptom was manual exposure:
writing 120000 us to FME_SHTVAL (0xABEC, 32-bit) landed as
0xC0D40100, which the sensor clamped to its VMAX-extended maximum
of ~266547 us, pinning the frame rate at 3.75 fps regardless of
the requested value. Analog/digital gain and white balance gain
writes were similarly corrupted but produced changes that could be
mistaken for a working path.

Switch the transport helpers to little-endian using
put_unaligned_le32() and get_unaligned_le32(). This fixes exposure,
analog gain, digital gain, WB gains, AE limits, and all multi-byte
readbacks in one place.

Verified on hardware:

  exposure=8000     -> 30.00 fps
  exposure=120000   ->  7.50 fps
  exposure=260000   ->  3.75 fps

Signed-off-by: Sodhi, Vunny <vunny.sodhi@intel.com>
@khaiwenng
khaiwenng merged commit 64b666b into intel:main Sep 10, 2026
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3 participants