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media: Add IPU8 8-camera AR0234 and D457 external frame-sync support - #50

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khaiwenng merged 9 commits into
intel:mainfrom
vunnyso:vs-external-port-20260804
Sep 4, 2026
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media: Add IPU8 8-camera AR0234 and D457 external frame-sync support#50
khaiwenng merged 9 commits into
intel:mainfrom
vunnyso:vs-external-port-20260804

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@vunnyso vunnyso commented Sep 4, 2026

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Description of changes

  • Expand the IPU8 D3 AR0234 ACPI topology from two to eight GMSL cameras.
  • Add matching IPU8 AR0234 sensor entries, virtual-channel settings, and I2C addresses.
  • Regenerate IPU75XA AR0234 GCSS files with unpacked RAW support and corrected preview/video links.
  • Add external frame-sync support to the D4xx driver and D457 ACPI configuration.
  • Add frame-sync and reset GPIO definitions to the common ACPI camera definitions.
  • Enable LGE Robinson D457 frame synchronization.
  • Fix LINK_FREQ macro expansion and default handling in the IPU7 MAX96724 ACPI include.
  • Remove the obsolete DESCH_SER_EXTRA_GPIO_PIN definition from the IPU7 configuration.

gohweikh and others added 9 commits September 4, 2026 10:23
Add DES1, a second MAX96724 deserializer on I2C2/MIPI port 2, with
four GMSL channels (CH00..CH03) each carrying a D3 AR0234 camera
through a MAX9295A serializer, mirroring the existing DES0 layout.

This expands the D3 AR0234 GMSL configuration from one deserializer
with two cameras to two deserializers with eight cameras total.
Bump the DefinitionBlock OEM revision and update the file header and
channel comments to match.

Signed-off-by: Goh, Wei Khang1 <wei.khang1.goh@intel.com>
Extend ar0234.json from two sensor entries to eight
(ar0234_acpi-1..8) to match the 8x D3 AR0234 GMSL topology.

Bump vcCount from 2 to 4 for all entries and update the I2C addresses
in each VIDEO_PIXEL_ARRAY videonode to match the new per-channel
sensor addressing.

Signed-off-by: Goh, Wei Khang1 <wei.khang1.goh@intel.com>
Regenerate AR0234.IPU75XA.xml/.bin with systool 26.31.3.0
(tag 20260406_1900_297):

- Switch the raw-only setting's isys output link from packed
  SINGLE_PL_10_P to unpacked SINGLE_PL_10 to enable unpacked RAW.
- Add the missing isys:output -> lbff_Bayer main data input link
  for the preview/video settings.

Signed-off-by: Goh, Wei Khang1 <wei.khang1.goh@intel.com>
Add fwnode property read-back from ASL, and perform
register write to D457 FW.

Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
D457 is using MFP0 for external sync, and getting external
sync signal from MFP7 of MAX96724.

Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
Remove reset-gpios for d457. RS MIPI driver does not use it.
MFP0 was used for Frame Sync instead.
Add gmsl-frame-sync-enable into ASL to be read-back by driver.

Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
Add DESCH_SER_RESET_GPIO for Reset GPIO.
Add DESCH_SER_FSIN_GPIO for Fsin GPIO.

Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
The LINK_FREQ_VAL indirection added in 898a6a065e ("ipu7: acpi:
isx031 max linq freq") does not work: iasl's preprocessor expands
LINK_FREQ_VAL to the token LINK_FREQ but does not recursively expand
LINK_FREQ further, so the literal identifier ends up in the AML source
and iasl fails with a syntax error, e.g.:

    ./script/gen_ssdt.sh acpi/ipu7/max96724_d3_isx031.asl
    ...
    Package () { "mipi-img-link-frequencies", Package() { LINK_FREQ } },
    Error 6126 - syntax error

Drop the LINK_FREQ_VAL alias and use LINK_FREQ directly, matching the
pattern already used by acpi/ipu6/_des_common_max96724.asl. Callers keep
the same interface ("#define LINK_FREQ <value>" before include,
"#undef LINK_FREQ" after).

When the includer does not provide LINK_FREQ, only default it for the
duration of this include and undef it on the way out, so the default
does not leak to subsequent includes or block a later "#define LINK_FREQ"
in the same translation unit. A LINK_FREQ_DEFAULTED sentinel tracks
whether this include is the one that installed the default.

Signed-off-by: Sodhi, Vunny <vunny.sodhi@intel.com>
Align with robinson bay implementation.

Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
@khaiwenng
khaiwenng merged commit 5a7af81 into intel:main Sep 4, 2026
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3 participants