Add OV13B10 direct-MIPI support and D4xx suspend/resume plus mc-setup robustness updates

acpi/ipu7/_mipi_cam_common_ov13b10.asl

@@ -0,0 +1,132 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (c) 2026 Intel Corporation.
+ *
+ * Description: Common template for a direct MIPI CSI-2 OV13B10 camera device.
+ *              This include provides the body of a CAMx device for native MIPI.
+ *
+ * CAM-level defines expected by caller:
+ *   CAM_I2C_BUS       - Camera I2C bus path (e.g. "\\_SB.PC00.I2C1")
+ *   CAM_I2C_ADDR      - Camera I2C slave address (e.g. 0x0010)
+ *   CAM_TO_MIPI_PORT  - Connected IPU MIPI port index (e.g. 0, 1, 2)
+ *   CAM_LANES         - Number of MIPI data lanes (e.g. 2, 4)
+ *   CAM_RESET_GPIO_CTLR - GPIO controller path for RESET (e.g. "\\_SB.GPI1")
+ *   CAM_POWER_GPIO_CTLR - GPIO controller path for POWER_EN (e.g. "\\_SB.GPI0")
+ *   CAM_RESET_PIN     - GPIO pin number for RESET
+ *   CAM_POWER_PIN     - GPIO pin number for POWER_EN
+ *   CAM_RESET_GPIORSC - GPIO resource index used by reset-gpios:
+ *                       0 = first GpioIo (_CRS RESET), 1 = second GpioIo (_CRS POWER_EN)
+ *   CAM_RESET_ACTIVE_LOW - RESET GPIO polarity (1: active low, 0: active high)
+ *   CAM_IPU_PATH      - IPU path string (e.g. "\\_SB.PC00.IPU0")
+ *   CAM_IPU_REF       - IPU namespace reference (e.g. \_SB.PC00.IPU0)
+ *   CAM_GPIO_REF      - Device self-reference for reset-gpios (e.g. ^CAM0)
+ */
+Method (_STA, 0, NotSerialized) // _STA: Status
+{
+    Return (0x0F)
+}
+
+Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+{
+    Return ("OVTI13B1")         // OV13B10
+}
+
+Name (_DEP, Package (0x01)       // _DEP: Dependencies
+{
+    CAM_IPU_REF
+})
+
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+{
+    /*
+     * mipi-disco-img.c will use the information in CSI2Bus to create fwnode.
+     * CAMx Local Port -> IPU Remote Port
+     * CAMx PRT0 -> IPU PRTx (selected by CAM_TO_MIPI_PORT)
+     */
+    CSI2Bus(
+        DeviceInitiated,        // SlaveMode
+        1,                      // PhyType (1 for DPHY)
+        0,                      // LocalPort (sensor local port)
+        CAM_IPU_PATH,           // ResourceSource (Path to IPU)
+        CAM_TO_MIPI_PORT,       // ResourceSourceIndex (IPU PRTx)
+        ,                       // ResourceUsage
+        ,                       // DescriptorName
+        )                       // VendorData
+
+    I2cSerialBusV2 (
+        CAM_I2C_ADDR,           // SlaveAddress
+        ControllerInitiated,    // SlaveMode
+        400000,                 // I2C ConnectionSpeed
+        AddressingMode7Bit,     // AddressingMode
+        CAM_I2C_BUS,            // ResourceSource
+        0x00,                   // ResourceSourceIndex
+        ResourceConsumer,       // ResourceUsage
+        ,                       // DescriptorName
+        Exclusive,              // Shared
+        )                       // VendorData
+
+    /* GPIO for sensor RESET (directly from SoC GPIO controller) */
+    GpioIo (
+        Exclusive,              // Shared (Not shared)
+        PullNone,               // PinConfig (No need for pulls)
+        0,                      // DebounceTimeout
+        0,                      // DriveStrength
+        IoRestrictionOutputOnly,// IoRestriction (Only used as output)
+        CAM_RESET_GPIO_CTLR,    // ResourceSource (GPIO controller)
+        0)                      // ResourceSourceIndex (Must be 0)
+    {
+        CAM_RESET_PIN           // Pin number
+    }
+
+    /* GPIO for sensor POWER_EN (optional rail control) */
+    GpioIo (
+        Exclusive,
+        PullNone,
+        0,
+        0,
+        IoRestrictionOutputOnly,
+        CAM_POWER_GPIO_CTLR,
+        0)
+    {
+        CAM_POWER_PIN           // Pin number
+    }
+})
+
+Name (_DSD, Package ()           // _DSD: Device-Specific Data
+{
+    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
+    Package ()
+    {
+        Package () { "mipi-img-clock-frequency", 19200000 }, // 19.2 MHz
+        /*
+         * reset-gpios: used by ov13b10.c driver via
+         * devm_gpiod_get_optional(dev, "reset", ...)
+         * Format: { <gpio_ref>, <resource_index>, <pin_index>, <active_low> }
+         * resource_index maps to _CRS GpioIo order: 0=RESET, 1=POWER_EN.
+         */
+        Package () { "reset-gpios", Package () { CAM_GPIO_REF, CAM_RESET_GPIORSC, 0, CAM_RESET_ACTIVE_LOW } },
+    },
+    ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), // Hierarchical Data Extension
+    Package ()
+    {
+        /* mipi-img-port here is local camera port used by mipi-disco-img.c. */
+        Package () { "mipi-img-port-0", "PRT0" },
+    },
+})
+
+Name (PRT0, Package ()
+{
+    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
+    Package ()
+    {
+        Package () { "mipi-img-clock-lane", 0 },
+#if CAM_LANES == 4
+        Package () { "mipi-img-data-lanes", Package () { 1, 2, 3, 4 } },
+#elif CAM_LANES == 2
+        Package () { "mipi-img-data-lanes", Package () { 1, 2 } },
+#else
+        Package () { "mipi-img-data-lanes", Package () { 1, 2, 3, 4 } },
+#endif
+        Package () { "mipi-img-link-frequencies", Package () { 560000000 } },
+    },
+})

acpi/ipu7/mipi_ov13b10.asl

@@ -0,0 +1,110 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (c) 2026 Intel Corporation.
+ *
+ * SSDT overlay: Direct MIPI CSI-2 OV13B10 camera configuration on PTL platform.
+ *
+ * This overlay describes a native MIPI-connected OV13B10 sensor (no GMSL SERDES).
+ * Adjust the CAM_* defines below to match your hardware wiring.
+ *
+ * CAM-level defines (set per CAMx, see _mipi_cam_common_ov13b10.asl):
+ *   CAM_I2C_BUS       - Camera I2C bus path (e.g. "\\_SB.PC00.I2C1")
+ *   CAM_I2C_ADDR      - Camera I2C slave address (0x0010 for OV13B10)
+ *   CAM_TO_MIPI_PORT  - Connected IPU0 MIPI port (e.g. 0/1/2)
+ *   CAM_LANES         - Number of MIPI data lanes (e.g. 2, 4)
+ *   CAM_RESET_GPIO_CTLR - GPIO controller path for RESET (e.g. "\\_SB.GPI1")
+ *   CAM_POWER_GPIO_CTLR - GPIO controller path for POWER_EN (e.g. "\\_SB.GPI0")
+ *   CAM_RESET_PIN     - GPIO pin number for RESET (community-relative)
+ *   CAM_POWER_PIN     - GPIO pin number for POWER_EN (community-relative)
+ *   CAM_RESET_GPIORSC - GPIO resource index used by reset-gpios:
+ *                       0 = RESET GpioIo resource, 1 = POWER_EN GpioIo resource
+ *   CAM_RESET_ACTIVE_LOW - RESET GPIO polarity (1: active low, 0: active high)
+ *   CAM_IPU_PATH      - IPU path string (e.g. "\\_SB.PC00.IPU0")
+ *   CAM_IPU_REF       - IPU namespace reference (e.g. \_SB.PC00.IPU0)
+ *   CAM_GPIO_REF      - Device self-reference for reset-gpios (e.g. ^CAM0)
+ *
+ * Default configuration (from BIOS table for OV13B10 on IPU75XA):
+ *   CAM0: I2C1, MIPI port 0, 4 lanes, RESET COM1 C_D_E_H pad 10 (GPI1 pin 27),
+ *         POWER_EN COM0 C_D_E_H pad 5 (GPI0 pin 29)
+ *   CAM1: I2C2, MIPI port 2, 2 lanes, RESET COM1 C_D_E_H pad 1 (GPI1 pin 36),
+ *         POWER_EN COM0 C_D_E_H pad 8 (GPI0 pin 32)
+ */
+
+DefinitionBlock ("", "SSDT", 2, "", "IMG_IPU", 0x20260827)
+{
+    External (_SB.PC00, DeviceObj)
+    External (_SB.PC00.IPU0, DeviceObj)
+    External (_SB.GPI1, DeviceObj)          // GPIO controller COM1 for RESET
+    External (_SB.GPI0, DeviceObj)          // GPIO controller COM0 for POWER_EN
+
+    Include ("_ipu.asl")
+
+    Scope (\_SB.PC00)
+    {
+        Device (CAM0)
+        {
+            #define CAM_I2C_BUS "\\_SB.PC00.I2C1"
+            #define CAM_I2C_ADDR 0x0010
+            #define CAM_TO_MIPI_PORT 0
+            #define CAM_LANES 4
+            #define CAM_RESET_GPIO_CTLR "\\_SB.GPI1"
+            #define CAM_POWER_GPIO_CTLR "\\_SB.GPI0"
+            #define CAM_RESET_PIN 27        // COM1 C_D_E_H pad 10
+            #define CAM_POWER_PIN 29        // COM0 C_D_E_H pad 5 (Power_En)
+            // Use POWER_EN GPIO resource for probe-time toggling.
+            #define CAM_RESET_GPIORSC 1
+            // Logical low maps to physical high (enable rail).
+            #define CAM_RESET_ACTIVE_LOW 1
+            #define CAM_IPU_PATH "\\_SB.PC00.IPU0"
+            #define CAM_IPU_REF \_SB.PC00.IPU0
+            #define CAM_GPIO_REF ^CAM0
+            #include "_mipi_cam_common_ov13b10.asl"
+            #undef CAM_I2C_BUS
+            #undef CAM_I2C_ADDR
+            #undef CAM_TO_MIPI_PORT
+            #undef CAM_LANES
+            #undef CAM_RESET_GPIO_CTLR
+            #undef CAM_POWER_GPIO_CTLR
+            #undef CAM_RESET_PIN
+            #undef CAM_POWER_PIN
+            #undef CAM_RESET_GPIORSC
+            #undef CAM_RESET_ACTIVE_LOW
+            #undef CAM_IPU_PATH
+            #undef CAM_IPU_REF
+            #undef CAM_GPIO_REF
+        }
+
+        Device (CAM1)
+        {
+            #define CAM_I2C_BUS "\\_SB.PC00.I2C2"
+            #define CAM_I2C_ADDR 0x0010
+            #define CAM_TO_MIPI_PORT 2
+            #define CAM_LANES 2
+            #define CAM_RESET_GPIO_CTLR "\\_SB.GPI1"
+            #define CAM_POWER_GPIO_CTLR "\\_SB.GPI0"
+            #define CAM_RESET_PIN 36        // COM1 C_D_E_H pad 1
+            #define CAM_POWER_PIN 32        // COM0 C_D_E_H pad 8 (Power_En)
+            // Use POWER_EN GPIO resource for probe-time toggling.
+            #define CAM_RESET_GPIORSC 1
+            // Logical low maps to physical high (enable rail).
+            #define CAM_RESET_ACTIVE_LOW 1
+            #define CAM_IPU_PATH "\\_SB.PC00.IPU0"
+            #define CAM_IPU_REF \_SB.PC00.IPU0
+            #define CAM_GPIO_REF ^CAM1
+            #include "_mipi_cam_common_ov13b10.asl"
+            #undef CAM_I2C_BUS
+            #undef CAM_I2C_ADDR
+            #undef CAM_TO_MIPI_PORT
+            #undef CAM_LANES
+            #undef CAM_RESET_GPIO_CTLR
+            #undef CAM_POWER_GPIO_CTLR
+            #undef CAM_RESET_PIN
+            #undef CAM_POWER_PIN
+            #undef CAM_RESET_GPIORSC
+            #undef CAM_RESET_ACTIVE_LOW
+            #undef CAM_IPU_PATH
+            #undef CAM_IPU_REF
+            #undef CAM_GPIO_REF
+        }
+    }
+}

acpi/ipu7/robinson_bay/3_d3_isx031_1_d457_frame_sync.asl

@@ -64,8 +64,8 @@
  * Make sure DESCH_CH, DESCH_SER, DESCH_CAM, DESCH_CH_PATH, DESCH_SER_PATH,
  * DESCH_SER_REF, DESCH_SER_GPIOREF are all updated if connection changed.
  *
- * 3x D3 ISX031 on MIPI-0 (0, 90, 270),   --> DES0, channel 0,1,3 : frame sync enabled
- * 1x RealSense on MIPI-2 (180)           --> DES1, channel 2     : frame sync disabled
+ * 3x D3 ISX031 on MIPI-0 (90, 180, 270),   --> DES0, channel 1,2,3 : frame sync enabled
+ * 1x RealSense on MIPI-2 (90)              --> DES1, channel 1     : frame sync disabled
  *
  */
 
@@ -94,22 +94,21 @@ DefinitionBlock ("", "SSDT", 2, "", "IMG_ROB", 0x20260827)
             #define DES_FSIN_GPIO_PIN 7
             #include "_des_common_max96724.asl"
 
-            // Channel 0 (D3 MFP8 fsync)
-            #define DESCH_LINK_NUM 0
-            #define DESCH_CH CH00
-            #define DESCH_SER SER0
-            #define DESCH_CAM CAM0
+            // Channel 1/acpi 2 (D3 MFP8 fsync)
+            #define DESCH_CH CH01
+            #define DESCH_SER SER1
+            #define DESCH_CAM CAM1
+            #define DESCH_CH_PATH "\\_SB.PC00.DES0.CH01"
+            #define DESCH_SER_PATH "\\_SB.PC00.DES0.CH01.SER1"
+            #define DESCH_SER_REF \_SB.PC00.DES0.CH01.SER1
+            #define DESCH_LINK_NUM 1
             #define DESCH_SER_I2C 0x40
-            #define DESCH_CH_PATH "\\_SB.PC00.DES0.CH00"
-            #define DESCH_SER_PATH "\\_SB.PC00.DES0.CH00.SER0"
-            #define DESCH_SER_REF \_SB.PC00.DES0.CH00.SER0
-            #define DESCH_SER_GPIOREF ^^SER0
-            #define CAM_ALIAS 0x54
-            #define CAM_LANES 4
+            #define DESCH_SER_GPIOREF ^^SER1
             #define DESCH_SER_EXTRA_GPIO_PIN 8
             #define DESCH_SER_FSYNC_RX_ID 7
+            #define CAM_ALIAS 0x55
+            #define CAM_LANES 4
             #include "_des_ch_common_isx031.asl"
-
             #undef DESCH_CH
             #undef DESCH_SER
             #undef DESCH_CAM
@@ -128,19 +127,19 @@ DefinitionBlock ("", "SSDT", 2, "", "IMG_ROB", 0x20260827)
             #undef CAM_ALIAS
             #undef CAM_LANES
 
-            // Channel 1 (D3 MFP8 fsync)
-            #define DESCH_CH CH01
-            #define DESCH_SER SER1
-            #define DESCH_CAM CAM1
-            #define DESCH_CH_PATH "\\_SB.PC00.DES0.CH01"
-            #define DESCH_SER_PATH "\\_SB.PC00.DES0.CH01.SER1"
-            #define DESCH_SER_REF \_SB.PC00.DES0.CH01.SER1
-            #define DESCH_LINK_NUM 1
+            // Channel 2/acpi 3 (D3 MFP8 fsync)
+            #define DESCH_CH CH02
+            #define DESCH_SER SER2
+            #define DESCH_CAM CAM2
+            #define DESCH_CH_PATH "\\_SB.PC00.DES0.CH02"
+            #define DESCH_SER_PATH "\\_SB.PC00.DES0.CH02.SER2"
+            #define DESCH_SER_REF \_SB.PC00.DES0.CH02.SER2
+            #define DESCH_LINK_NUM 2
             #define DESCH_SER_I2C 0x40
-            #define DESCH_SER_GPIOREF ^^SER1
+            #define DESCH_SER_GPIOREF ^^SER2
             #define DESCH_SER_EXTRA_GPIO_PIN 8
             #define DESCH_SER_FSYNC_RX_ID 7
-            #define CAM_ALIAS 0x55
+            #define CAM_ALIAS 0x56
             #define CAM_LANES 4
             #include "_des_ch_common_isx031.asl"
             #undef DESCH_CH
@@ -161,19 +160,19 @@ DefinitionBlock ("", "SSDT", 2, "", "IMG_ROB", 0x20260827)
             #undef CAM_ALIAS
             #undef CAM_LANES
 
-            // Channel 3 (D3 MFP8 fsync)
+            // Channel 3/acpi 4 (D3 MFP8 fsync)
             #define DESCH_CH CH03
             #define DESCH_SER SER3
             #define DESCH_CAM CAM3
             #define DESCH_CH_PATH "\\_SB.PC00.DES0.CH03"
             #define DESCH_SER_PATH "\\_SB.PC00.DES0.CH03.SER3"
             #define DESCH_SER_REF \_SB.PC00.DES0.CH03.SER3
-            #define DESCH_SER_EXTRA_GPIO_PIN 8
-            #define DESCH_SER_FSYNC_RX_ID 7
             #define DESCH_LINK_NUM 3
             #define DESCH_SER_I2C 0x40
             #define DESCH_SER_GPIOREF ^^SER3
-            #define CAM_ALIAS 0x56
+            #define DESCH_SER_EXTRA_GPIO_PIN 8
+            #define DESCH_SER_FSYNC_RX_ID 7
+            #define CAM_ALIAS 0x57
             #define CAM_LANES 4
             #include "_des_ch_common_isx031.asl"
             #undef DESCH_CH
@@ -229,22 +228,22 @@ DefinitionBlock ("", "SSDT", 2, "", "IMG_ROB", 0x20260827)
 //            #define DES_FSIN_GPIO_PIN 7
             #include "_des_common_max96724.asl"
 
-            // Channel 2 (D457 MFP0 fsync)
-            #define DESCH_LINK_NUM 2
-            #define DESCH_CH CH02
-            #define DESCH_SER SER2
-            #define DESCH_CAM CAM2
+            // Channel 1 (D457 MFP0 fsync)
+            #define DESCH_LINK_NUM 1
+            #define DESCH_CH CH01
+            #define DESCH_SER SER1
+            #define DESCH_CAM CAM1
             #define DESCH_SER_I2C 0x40
-            #define DESCH_CH_PATH "\\_SB.PC00.DES1.CH02"
-            #define DESCH_SER_PATH "\\_SB.PC00.DES1.CH02.SER2"
-            #define DESCH_SER_REF \_SB.PC00.DES1.CH02.SER2
-            #define DESCH_SER_GPIOREF ^^SER2
+            #define DESCH_CH_PATH "\\_SB.PC00.DES1.CH01"
+            #define DESCH_SER_PATH "\\_SB.PC00.DES1.CH01.SER1"
+            #define DESCH_SER_REF \_SB.PC00.DES1.CH01.SER1
+            #define DESCH_SER_GPIOREF ^^SER1
             #define DESCH_SER_X_VC Package () { 0 }
             #define DESCH_SER_Y_VC Package () { 1 }
             #define DESCH_SER_Z_VC Package () { 2 }
             #define DESCH_SER_U_VC Package () { 3 }
 //            #define DESCH_SER_FSYNC_RX_ID 0
-            #define CAM_ALIAS 0x54
+            #define CAM_ALIAS 0x55
             #define CAM_LANES 2
             #include "_des_ch_common_d457.asl"
             #undef DESCH_CH