docs: design dual-output TEXTRACT support - #1289
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| 4. 任一 TSTORE source static range 与任一 partial destination range 相交即拒绝。TSTORE source | ||
| 是 block argument/call operand 派生值而无法解析为唯一 static absolute range 时也保守拒绝； | ||
| 首版不为此建立 argument-effect/range summary fixed point。 |
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Restrict this range-intersection check to sources in the same address space as the partial destination. TStoreOp accepts VEC, MAT, and ACC sources, and those local memories can legitimately reuse the same numeric offsets; therefore a component containing a partial VEC destination at address 0 and an unrelated MAT/ACC TSTORE source at address 0 would be rejected even though that store cannot expose the UB destination. The helper should carry the address space with each range and only report an alias when both the space and byte intervals overlap.
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| 该 helper 使用 `getBufferBitSize(alloc.getResult())` 填 `allocateSize`，从 tile memory space 填 | ||
| `addressSpace`，把静态 byte `addr` 乘 `kBitsToByte` 后作为唯一 `addresses` 元素，并记录 | ||
| `parentLoop`。地址不可折叠时写入 `ShapedType::kDynamic`，在同 address space 中保持保守冲突， |
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Require checked multiplication when converting the byte address to GraphSync's bit units. Existing AllocTileOp verification only enforces non-negativity and alignment, so a level-3 constant greater than INT64_MAX / 8 can reach GraphSync; because GraphSync runs before the proposed post-planning helper, addr * kBitsToByte then overflows signed int64_t before the later range validation can reject it, potentially producing incorrect hazard decisions or undefined behavior. Reject the address or conservatively mark it dynamic when the conversion is not representable.
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| indexRow_k + dst_k.validRows <= src.physicalRows | ||
| indexCol_k + dst_k.validCols <= src.physicalCols |
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When src.valid_shape is smaller than its physical shape, these checks accept a window entirely outside the valid region—for example, a physical 64x128 source with valid 16x16 and indexRow=32. The proposed A2/A3 scalar lowering and A5 template then read those padding elements and expose them through dst.valid_shape, producing undefined or stale output. Either require a full-valid source or check each window against src.validRows/src.validCols rather than its allocation extent.
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A3 板测失败
失败用例
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Design PR hw-native-sys#1289 sections 5.1 items 11-13 and 5.3.1: - validateTExtractNd2xNzInputProvenance: runs after generic verification and before any planning pass; rejects runtime-bound tile provenance (DeclareTileOp/TAssignOp/TPop-derived and their views), allows only AllocTileOp roots and non-RowPlusOne alloc_multi_tile slots. - validateTExtractNd2xNzPostPlanningSafety: runs after PTOResolveBufferSelect and before PTOInlineBackendHelpersPass; address-space-aware physical-range comparison rejects alias generic TSTORE of partial-valid destinations inside the same closed direct-call component; compile-unit-wide call-surface closure rejects call_indirect / external / unresolved / opaque calls while any partial producer exists. - compilePTOASModule: main pipeline is split into two actually-run pass managers (pre-inline planning through resolve-buffer-select, then the post-validation backend-helper pass); both helper calls and the shared checkpoint are on the ordinary codegen and --emit-pto-ir paths. - lit: provenance negative and partial-store-alias negative.
…odel (stage 3) Design PR hw-native-sys#1289 sections 6.3, 6.3.1 and 7: - getSemanticNoAliasPairs: the dual-output form reports (src,dst0), (src,dst1) and (dst0,dst1) so legacy/modern PlanMemory and the semantic no-alias verifier treat all three pairs as disjoint. - GraphSync MemInfo: ordinary pto.alloc_tile gets a single-address model (static byte addr * bits-to-byte as the sole address; dynamic entry when the addr is not foldable so the allocation stays conservative inside its address space instead of looking disjoint); getMemInfo(Value) dispatches AllocTileOp explicitly. - TExtractOp SyncMacroModel: dual-output form declares one external PIPE_V phase plus an internal PIPE_S phase covering source read and both destination writes, with bidirectional hidden V<->S events reserved before event-id allocation (design 6.3.1). The model is shape-selected: A2/A3 scalar lowering and the A5 1x1 scalar path opt in; the ordinary A5 vector template stays a pure PIPE_V op.
…assembly, EmitC) Extend the existing pto.textract TExtractOp to carry the PTO-ISA ND-to-2xNZ dual-output overload on the same operation (design PR hw-native-sys#1289): - ODS: indexRow/indexCol/dst become Variadic indices/dsts ranges with the fixed five-segment schema [src, indices, dsts, fp, preQuantScalar]; custom assembly keeps the single-output canonical text character-for-character. - classifyForm(): typed-property schema inference (SingleOutput vs NdTo2xNz); legacy getIndexRow/getIndexCol/getDst accessors restored as wrappers. - verifier: form dispatch; verifyNdTo2xNzForm covers the IR/shape/layout items 1-10 (incl. source valid/physical double bounds, A5 partial-valid physicalRows==align16(validRows) gate, RowPlusOne rejection). - getEffects: dual-output Read(src)+Write(dst0)+Write(dst1); Invalid schema falls back to conservative Read+Write on all raw memory operands. - EmitC: dual-output emits the public seven-operand TEXTRACT(dst0,dst1,src, row0,col0,row1,col1) exactly once; single-output path reads ranges. - PTOBC v0: dual-output forced through the generic v0 record, legacy four/five-operand opcodes unchanged. - lit: parse/emit roundtrip, undefined-padding negative, and seven-arg EmitC checks. Compiled locally against LLVM 19-compatible APIs; full regressions run on the main-branch LLVM 19 CI.
Design PR hw-native-sys#1289 sections 5.1 items 11-13 and 5.3.1: - validateTExtractNd2xNzInputProvenance: runs after generic verification and before any planning pass; rejects runtime-bound tile provenance (DeclareTileOp/TAssignOp/TPop-derived and their views), allows only AllocTileOp roots and non-RowPlusOne alloc_multi_tile slots. - validateTExtractNd2xNzPostPlanningSafety: runs after PTOResolveBufferSelect and before PTOInlineBackendHelpersPass; address-space-aware physical-range comparison rejects alias generic TSTORE of partial-valid destinations inside the same closed direct-call component; compile-unit-wide call-surface closure rejects call_indirect / external / unresolved / opaque calls while any partial producer exists. - compilePTOASModule: main pipeline is split into two actually-run pass managers (pre-inline planning through resolve-buffer-select, then the post-validation backend-helper pass); both helper calls and the shared checkpoint are on the ordinary codegen and --emit-pto-ir paths. - lit: provenance negative and partial-store-alias negative.
…odel (stage 3) Design PR hw-native-sys#1289 sections 6.3, 6.3.1 and 7: - getSemanticNoAliasPairs: the dual-output form reports (src,dst0), (src,dst1) and (dst0,dst1) so legacy/modern PlanMemory and the semantic no-alias verifier treat all three pairs as disjoint. - GraphSync MemInfo: ordinary pto.alloc_tile gets a single-address model (static byte addr * bits-to-byte as the sole address; dynamic entry when the addr is not foldable so the allocation stays conservative inside its address space instead of looking disjoint); getMemInfo(Value) dispatches AllocTileOp explicitly. - TExtractOp SyncMacroModel: dual-output form declares one external PIPE_V phase plus an internal PIPE_S phase covering source read and both destination writes, with bidirectional hidden V<->S events reserved before event-id allocation (design 6.3.1). The model is shape-selected: A2/A3 scalar lowering and the A5 1x1 scalar path opt in; the ordinary A5 vector template stays a pure PIPE_V op.
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Summary
这是一个 docs-only 设计 PR，目标是让 PTOAS 在现有
pto.textract/TExtractOp上承载 PTO-ISA 的 ND -> 2xNZ 双输出 overload。本 PR 不实现代码，不新增 MLIR op、dotted mnemonic、driver 参数或构建配置。
设计范围
pto.textract，通过完整 operand segment schema 和 tile layout 推断单输出/双输出 form。LowerPTOToUBufOps内展开为两路 scalar pointer loop 和 V/S 内部同步，不能残留 pointer-formpto.textract。1x1只作为 UB-only TEXTRACT 覆盖，禁止通过同址 alias generic TSTORE 导出未定义 NZ padding。不在本 PR
TExtractNd2xNzOp、第二个 IR mnemonic或 backend TEXTRACT op。--pto-isa-include-root、codegen environment 属性、compile probe 或其他 capability discovery 机制。Review focus
请重点评审：现有 op 的 operand/schema 兼容性、A2/A3 VPTO lowering、双输出的内存与同步语义、partial-valid 的 TSTORE 安全边界、跨函数/跨 child 调用闭包、A5 physical layout 与 gap 观测边界，以及后续实现拆分和回归覆盖。
Scope
本分支只新增：
docs/designs/textract-nd-to-2xnz-design.md没有代码、测试或依赖变更。