Pinned Loading

1. riscv-single-cycle riscv-single-cycle Public

   A single-cycle RV32I CPU core with machine-mode traps, verified with RISC-V Formal and Spike lockstep co-simulation, booting FreeRTOS and running CoreMark on a Basys 3 FPGA.

   SystemVerilog 1

2. tinytapeout-uart tinytapeout-uart Public

   A FIFO-buffered UART with an APB register block, verified with self-checking testbenches and taped out on the Tiny Tapeout TTSKY26c shuttle.

   Python

3. uart uart Public

   A UART transceiver with a 16x-oversampling receiver, self-checking testbenches, formally verified RX/TX, and Basys 3 FPGA loopback validation.

   SystemVerilog

4. fifo fifo Public

   A configurable synchronous and asynchronous FIFO with Gray-code clock-domain crossing, verified with an unbounded SymbiYosys formal proof and self-checking testbenches.

   SystemVerilog