TeamYogaBlade2 Linux 7.1 Release#60
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PowerVR SGX544 on MediaTek MT6589 is rev 115, MP1 Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
…pers Extend __mtk_clk_simple_probe() and __mtk_clk_simple_remove() to support cpumux clocks. This reduces boilerplate code in drivers for SoCs that require cpumux registration, such as mt6795-infracfg. Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Some of MT6589 PLLs don't have this register. Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
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fixed diff --git a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c
index 653d25bfface..36176338beb0 100644
--- a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c
@@ -94,7 +94,7 @@ static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_MMPLL, "mmpll", MMPLL_CON0, VOID_REG, 0xf0000001,
HAVE_RST_BAR, 7, MMPLL_CON0, 6, MMPLL_CON0, 8, 1430000000),
PLL(CLK_APMIXED_ISPPLL, "isppll", ISPPLL_CON0, VOID_REG, 0x80000001,
- 0, 7, ISPPLL_CON0, 7, ISPPLL_CON0, 8, 1664000000),
+ 0, 7, ISPPLL_CON0, 6, ISPPLL_CON0, 8, 1664000000),
};
static int clk_mt6589_apmixed_probe(struct platform_device *pdev) |
MT6589 has 2bit postdiv register Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Add entries for Lenovo YOGA Tablet 8/10 tablet board. They belongs to Lenovo's "blade" product family, a codename found in the stock Android "ro.product.board" property (e.g., "blade10_row_wifi" for B8000-F and "blade8_row_3gdata" for B6000-H). The "blade" family includes several variants with different screen sizes and connectivity: YOGA Tablet 8 (8-inch display) B6000-F : Wi-Fi B6000-H : Wi-Fi + 3G (Data only) B6000-HV : Wi-Fi + 3G (Voice) YOGA Tablet 10 (10-inch display) B8000-F : Wi-Fi B8000-H : Wi-Fi + 3G (Data only) These devices feature 1GB of RAM and powered by MediaTek MT8125 or MT8389 SoC. Since these SoCs are tablet-oriented variants of MT6589, they are grouped under the "mediatek,mt6589" compatible string. Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Some MediaTek SoCs split their I2C APDMA into two physically separate channels per bus, each with its own register block using TX-side offsets regardless of direction. mt6572 is one such SoC. The existing driver assumes a single unified APDMA channel where RX and TX live at RX_*/TX_* offsets within the same block, which is correct for the SoCs already in mainline but cannot reach the RX channel on dual-channel SoCs. Add a per-SoC compatible flag dma_separate_rx plus a second ioremap pointer pdmabase_rx for the RX channel. When the flag is clear (every currently supported SoC), pdmabase_rx aliases pdmabase and the RX-direction offsets collapse back to OFFSET_RX_MEM_ADDR / OFFSET_RX_LEN / OFFSET_RX_4G_MODE — byte-for-byte identical writes to the pre-patch code path. No behaviour change for unified-DMA SoCs. When the flag is set, the driver ioremaps the third reg entry as the RX channel and routes RX writes through that block using OFFSET_TX_* offsets (the RX channel uses the same TX-style register layout in its own block). DMA_START_EN is issued on the RX channel for read transfers; the TX channel still starts WR/WRRD paths as before. No SoC opts into this layout in this commit. Co-developed-by: rva3 <rva333@protonmail.com> [rva3: fix DMA enable for WRRD] Signed-off-by: rva3 <rva333@protonmail.com> Signed-off-by: Custom Firmware <gabin278@gmail.com>
MediaTek mt65xx family SoCs have no auto restart, however, they still support the WRRD mode in the hardware. Because auto_restart is set to 0, the WRRD mode will be never enabled, leading to read errors using i2cget with explicit register. Fix this by removing auto_restart check from the WRRD enable path. Signed-off-by: rva3 <rva333@protonmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
The MediaTek SoCs often released under the same marketing name but with different suffix for the speedbin. The standard way to handle different OPP entries is 'opp-supported-hw' property. Add support for the NVMEM cell parsing and using OPP config based on the actual hardware speedbin. Signed-off-by: rva3 <rva333@protonmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Implement reset GPIO handling logic for the rmi_i2c driver. This logic is required for some mobile devices to successfully initialize the touch controller. As there are no datasheets available, the timings were taken from the GPLv2+ licensed synaptics-dsx-v2.1 vendor driver release. Tested-On: Motorola G5 Plus (Potter / XT1685) Signed-off-by: Felix Kaechele <felix@kaechele.ca>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Assisted-by: DeepSeek:deepseek-v4-pro Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
[ 5.205562] cpu cpu0: error -ERANGE: cpu0: failed to get intermediate opp [ 5.208093] mtk-cpufreq mtk-cpufreq: probe with driver mtk-cpufreq failed with error -34 impl TOP_CKDIV1 Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
When building with CONFIG_THUMB2_KERNEL=y and Clang, secondary CPUs fail to come online with "CPU1: failed to come online". The address written to the jump register has bit 0 set, causing the secondary CPU to start in Thumb mode. secondary_startup_arm is ARM-mode code (.arm) and, on a Thumb-2 kernel, expects to be entered in ARM mode in order to switch to Thumb via the standard sequence at that label. Starting in Thumb mode causes the CPU to execute ARM instructions as Thumb, resulting in an immediate crash. Clear bit 0 of the entry address so the CPU always starts in ARM mode. Tested on Lenovo YOGA Tablet 10 (Wi-Fi). Fixes: 0cda070 ("ARM: mediatek: add smp bringup code") Assisted-by: DeepSeek:deepseek-v4-pro Cc: stable@vger.kernel.org Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Link: https://github.com/bq/aquaris-5/blob/bc1d0d0e35c969670e2d869001be944ad0c9c5e5/mediatek/platform/mt6589/kernel/core/mt_ptp.c Link: https://github.com/bq/aquaris-5/blob/bc1d0d0e35c969670e2d869001be944ad0c9c5e5/mediatek/platform/mt6589/kernel/core/mt_cpufreq.c Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
… Clang" This reverts commit 3f87e1f.
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
MMPLL/2 means mmpll_d2
normal config:
```
~ # time sh -c 'dd if=/dev/zero bs=1M count=500 2>/dev/null | md5sum'
d8b61b2c0025919d5321461045c8226f -
real 0m 5.59s
user 0m 4.82s
sys 0m 2.11s
```
hack for testing:
```c
static const char * const infra_mux1_parents[] = {
"clk26m",
"rtc_clk",
"rtc_clk",
"mmpll", /* MMPLL/2 */
};
```
```dts
&infracfg {
assigned-clocks = <&infracfg CLK_INFRA_MUX1>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_MMPLL>;
};
```
result ->
```
[ 1.192318] cpufreq: cpufreq_policy_online: CPU0: Running at unlisted initial frequency: 1430000 kHz, changing to: 1209000 kHz
~ # time sh -c 'dd if=/dev/zero bs=1M count=500 2>/dev/null | md5sum'
d8b61b2c0025919d5321461045c8226f -
real 0m 8.99s
user 0m 8.22s
sys 0m 2.40s
~ #
~ # time sh -c 'dd if=/dev/zero bs=1M count=500 2>/dev/null | md5sum'
d8b61b2c0025919d5321461045c8226f -
real 0m 8.98s
user 0m 8.21s
sys 0m 2.41s
```
Assisted-by: DeepSeek:deepseek-v4-pro
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
failed log: [ 0.004423] smp: Bringing up secondary CPUs ... [ 1.040269] CPU1: failed to come online [ 2.080544] CPU2: failed to come online [ 3.120823] CPU3: failed to come online [ 3.120898] smp: Brought up 1 node, 1 CPU [ 3.120920] SMP: Total of 1 processors activated (26.00 BogoMIPS). succeed log: [ 0.004443] smp: Bringing up secondary CPUs ... [ 0.005139] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.006037] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002 [ 0.006873] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003 [ 0.007085] smp: Brought up 1 node, 4 CPUs [ 0.007140] SMP: Total of 4 processors activated (104.00 BogoMIPS). Link: https://lore.kernel.org/all/CAKwvOdnbPKoTy72EvfpKtT9Ne-r+O0j99KFX8OvjGk8ZxsuEGw@mail.gmail.com/ Link: llvm/llvm-project#211376 Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Currently the driver assumes eint mapping is linear and never repeated for any other GPIO. However, this is false on mt6572 SoC. For example, both GPIO30 and GPIO135 have EINT0 in their modes. When devicetree requests interrupt on EINT0, the driver would pick GPIO30, regardless of the actual pinmux value. To fix this, add hardware mode lookup, which checks pinmux. If the devicetree selects GPIO135 in consumer's pinctrl state, now the driver will correctly pick GPIO135 over GPIO30 for EINT0. If the pinmux is not defined, the driver will fallback to searching first pin with desired EINT. While here, also replace while loop with for, to improve readability. This change doesn't affect most SoCs with linear mapping, where GPIO0 corresponds to EINT0, GPIO1 to EINT1, and so on, such as mt6595 or mt67xx series. On SoCs with non-linear mapping, like mt6572, leftover or invalid bootloader pinmux states should be cleared using pinctrl configuration, such as pinctrl-0 = <&...>, in the devicetree to ensure correct mapping. Signed-off-by: Roman Vivchar <rva333@protonmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
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