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WIP: Minor simulation missing#274

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padeken wants to merge 5 commits into
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minor_simulation_missing
Open

WIP: Minor simulation missing#274
padeken wants to merge 5 commits into
masterfrom
minor_simulation_missing

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@padeken

@padeken padeken commented May 27, 2026

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Hi I would like to have these sim stand-ins in basil. I think they are useful for more projects.

@cbespin

cbespin commented May 28, 2026

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Funnily enough, part of it (at least the PLL one) is included in #272 that is about to be merged the next days. I would wait until this one is done and then check again. The RAM block will probably still be needed as I don't think it is included in #272, but I would have to check (it is quite a big one..)

@kcaisley

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Actually, after chatting with @awalsemann I actually removed the PLL block. Since my version was also just a black box, we couldn't think of a good reason to keep it. But I'll chat with @padeken, since if he wants it there's obviously a use case!

@padeken

padeken commented May 28, 2026

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Hi Ned,
yes then we move it to your merge. I just need a dummy for simulation and I just used the input as output, because it worked for my simplified simulation.

@cbespin

cbespin commented May 28, 2026

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Well, if you need some sort of PLL in a simulation with more than one clock output, maybe we can make a more flexible simulation solution with instantiating clock dividers in the PLL replacement module?

@padeken

padeken commented May 28, 2026

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Yes, and writing this I can also provide the not sim module for the RAM, which should be more efificent, but I need to test this first

@cbespin

cbespin commented May 28, 2026

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So you need the RAM simulation module to work on a more advanced PLL one? Then we could split this and merge the RAM first.
Do you instantiate the RAM module at some point or do you use an inferred version? In this case, one would not need the simulation module, no? Just wondering, because I did not run into this issue yet with designs that infer the primitive, but that might be on my end.

@padeken

padeken commented May 28, 2026

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I think I will talk to Ned and we will make a better PLL sim and the RAM maybe I will test first and then put it here.

@padeken padeken changed the title Minor simulation missing WIP: Minor simulation missing May 28, 2026
@awalsemann

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I belive if you need a more advanced model for a PLL, just use an encrypted model from AMD or use one of the exitsing open models available, like this one: https://github.com/nmi-leipzig/sim-x-pll
I will not stop you from developing such models on your own, but I don't see the point in us reinventing the wheel.

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4 participants