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Name		Name	Last commit message	Last commit date
analysis.v		analysis.v
bcd.v		bcd.v
components.v		components.v
components_tb.v		components_tb.v
div.v		div.v
div_bb.v		div_bb.v
mul.v		mul.v
mul_bb.v		mul_bb.v
proc.v		proc.v
proc_extension.v		proc_extension.v
proc_extension_tb.v		proc_extension_tb.v
proc_tb.v		proc_tb.v
readme.md		readme.md

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Simulated CPU

Instructions

Open Quartus 18.1
Start a new project
Add all verilog files in this repo to the project
Compile the project, with proc_extension as the top level module
Open Modelsim, and open proc_tb to see testbench demonstration of CPU functionality.

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