[XPU] Support checkpoint-engine weight update on Intel XPU - #96
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[XPU] Support checkpoint-engine weight update on Intel XPU#96siju-samuel wants to merge 1 commit into
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Add Intel XPU as a first-class device backend alongside CUDA and NPU. Device abstraction (device_utils.py): detect xpu, map to the xccl distributed backend, and gate capabilities per backend -- in-place host pinning (cudaHostRegister) and Mooncake device P2P stay CUDA/NPU-only, while cross-process device-tensor IPC is supported on XPU via a native extension. Weight transport (transport.py): the broadcast path shares a device buffer with the colocated inference worker. PyTorch has no XPU tensor IPC (reduce_tensor raises '_share_fd_: only available on CPU'), so a WeightTransport seam selects the CUDA/NPU reduce_tensor path or a native XPU implementation. XPU IPC (xpu_ipc/): implemented on SYCL ext::oneapi::experimental::ipc_memory, which torch's own libsycl (oneAPI >= 2026.0, libsycl.so.9) exports. A SYCL IPC handle is a self-contained, portable byte blob -- verified cross-process on Arc B60 -- so it needs no out-of-band dma-buf fd transfer and no sub-allocation offset handling: the whole handle rides the existing ZMQ channel exactly like CUDA's reduce_tensor tuple. The -fsycl extension coexists with torch's single SYCL runtime in-process. Only the broadcast update method is supported on XPU; P2P is rejected with a clear error (Mooncake has no Level Zero backend for XPU device memory). Robustness: the exported IPC handle is released in an outer try/finally so an early failure (export, ZMQ bind, or first send) can no longer leak it, while the collective barrier stays in the inner finally to avoid deadlocking peers on an asymmetric failure. The P2P store is skipped entirely on backends that do not support device P2P (e.g. XPU) instead of being eagerly initialized and only guarded against ImportError. icpx discovery falls back to PATH (via shutil.which) for oneAPI layouts outside /opt or a sourced setvars.sh that does not export CMPLR_ROOT. Tests: CPU-only coverage for device dispatch, the transport seam, the P2P guard, and the XPU parity paths (portable-handle contract, xccl backend selection, in-place-pin disable, detach-on-early-failure, icpx PATH fallback); hardware-gated tests for the SYCL IPC roundtrip, interior-pointer offset, and the full cross-process broadcast.
Author
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@kip-cxj @specture724 @weixiao-huang @ppwwyyxx |
| ``reduce_tensor`` tuple -- see ``XpuIpcWeightTransport``. | ||
| """ | ||
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| from __future__ import annotations |
Collaborator
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It is unnecessary to import this line. I thinks we can use double quote in type
| def ipc_collect(self) -> None: | ||
| """Reclaim memory held by stale IPC handles where the backend supports it (no-op otherwise).""" | ||
| fn = getattr(self.device_module, "ipc_collect", None) | ||
| if callable(fn): |
Collaborator
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If not callable, mayeb it should raise
| socket.recv() | ||
| gidx = 0 | ||
| ret_code = torch.zeros((), device=self.device_manager.device_type, dtype=torch.int64) | ||
| try: |
Collaborator
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Why there need additinal try and finally?
HubertZhang
reviewed
Jul 28, 2026
| @@ -0,0 +1,124 @@ | |||
| """Pluggable device-buffer handoff between the ParameterServer and the worker. | |||
Collaborator
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What about renaming WeightTransport to IPCHandler? This object transports nothing; it just hands an IPC handle for a device buffer across processes.
| #include <unordered_map> | ||
| #include <vector> | ||
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| namespace ipc = sycl::ext::oneapi::experimental::ipc_memory; |
Collaborator
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It seems ipc_memory namespace is deprecated upstream and should migrate to ipc::memory?
| sources=[str(src)], | ||
| extra_cflags=["-fsycl", "-O2", *sycl_include_flags], | ||
| extra_ldflags=["-fsycl"], | ||
| verbose=False, |
Collaborator
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Would this file be simplified if we set with_sycl=True here?
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Motivation
This PR adds Intel XPU as a first-class device backend behind device abstraction, and fills the IPC gap with a native SYCL ipc_memory transport, which is the XPU counterpart of CUDA IPC
The CUDA and NPU paths are unchanged, XPU-specific code is reached only when the device type is xpu.
This unblocks checkpoint-engine's fast weight-update path on Intel GPUs, which is needed for SGLang's XPU for RL rollout weight sync.
Modifications
Device abstraction
device_utils.py: detectxpuand map it to thexcclcollective backend; addsupports_device_ipc()/supports_device_p2p()capability gates so XPU enables broadcast IPC but not P2P.distributed/base.py: reject custom distributed backends on XPU and fall back to the defaultxcclTorchBackend.**Weight transport **
transport.py: add aWeightTransportseam —IpcWeightTransport(CUDA/NPU, unchanged) andXpuIpcWeightTransport(XPU) — withbuild_transport()selecting by device type.xpu_ipc/sycl_ipc.cpp+xpu_ipc/__init__.py: native SYCLipc_memoryextension (get/open/close), JIT-compiled at runtime with-fsycl, providing the cross-process device-buffer IPC that PyTorch lacks on XPU.Parameter server & worker
ps.py: route the broadcast throughbuild_transport(), prebuild the SYCL extension at startup, and fail loudly with clear errors when device IPC/P2P is unavailable on XPU.worker.py: derive theGPU-<uuid>handshake key fromtorch.xpuon XPU, matching the ParameterServer's_get_physical_gpu_id.Packaging
pyproject.toml: ship the SYCL.cppsource as package data (JIT-compiled on XPU hosts; inert on CUDA).Tests
test_device_manager.py,test_transport.py,test_xpu_parity.py,test_p2p_guard.py— device dispatch, transport seam, portable-handle contract,xcclselection, P2P rejection.test_xpu_ipc.py— SYCL IPC roundtrip, interior-offset, full cross-process broadcast.Accuracy Test / Verified
Device-UUID handshake verified on Intel Arc Pro B60: the worker emits the exact
GPU-<uuid>key the ParameterServer expects. 5 CPU unit tests pass.Environment
Check list
pytest tests/ -m "not gpu")pytest tests/test_xpu_ipc.py)xpu)CC: @@kip-cxj @specture724 @weixiao-huang @ppwwyyxxc Could you please run the CI and review. TIA