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Ariana, Andrew, Jonah Submission - #16

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arianaolson419 wants to merge 217 commits into

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arianaolson419:master

Commits on Nov 6, 2017

Create work plan
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dba9873
Createe work plan with correct file name
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c8c8083

Commits on Nov 8, 2017

Create module encompassing ALU, RegFile, and Memory
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fc81680
Create makefile to build modules
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2cb2fb0
Ignore compiled binaries and gtkwave files
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74292b0
Create test bench for core module
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79cde4c
Add alu files
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1cff180
Add inputs and outputs to module definition
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0e9e79f
Merge branch 'master' of https://github.com/arianaolson419/Lab3 into core_module
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cae0a5b
Build core testbenches
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26b8f1d
Add register file related modules
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3883fa8
Add build rules for regfile modules
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c81349d
Add memory files
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a7e4eeb
Add build rules for memory
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ae05540
Add module for 4 input mux
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ea4c132
Add tests for 4 input module
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bbb2399
Add new module for four input multiplexer
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1375826
Parametize 4 input mux for code reuse
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37e0474
modified gitignore to ignore extra output files
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d0991be
Added definition of Core module
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b6fbcd3
Add Instruction Parser Shell
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efcc999
Added PC_Calc
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2bb1396

Commits on Nov 9, 2017

Top-level module is done.
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410bc2a
Add zero flag
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e1f828a
Add new modules
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80343e8
Change address size
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10ff9b9
Add signextend module
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0c356cf
Change mem and addr size
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c902bef
Change address size
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43fb3ac
Add initial Instruction_Parser parts, no tests
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98c4dbc
work on pc calculator
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f458d8e
Change width of regfile addresses
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82192b8
Tests passing
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3bafadb
Increase spacing from 2 to 4
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1736bd3
Add controller
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52dd89f
Add alu control outs
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60a1ede
Move core module files to subfolder
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1a7a36c

Commits on Nov 10, 2017

Initialize memory
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fae67a3
Add test cases
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e08bfe0
Create file of initialized memory
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e5df628
Connect Da wire
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217e071
Implement tests for addi, lw, sw
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7a4587c
Update module references
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f69ea41
update file paths
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98ab8f7
Update file paths
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a04ebb6
Move files to subfolder
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849f316
Merge branch 'master' of https://github.com/arianaolson419/Lab3 into core_module
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56fa176

Commits on Nov 11, 2017

Implement module
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e81590e
Update Core instantiation
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a9e1ce5
Update file references
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3a0bf3c
Remove old files that have been replaced
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4fa129f

Commits on Nov 12, 2017

Change address size in test
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9116483
Change size of 2d array to correct width
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88c839b
Add build rules for new modules
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d15b6aa
Add remaining tests
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8be9889
Instruction_Parser now compiles
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07e7375
Change AddCtrl to be 1 bit because of difference in JAL
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2c51318
Added initial tests, found bug in jump
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93debdd
Finish Tests, update Controller xs to be full # of bits
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859087d
Add program runner, add barebones for testing memory
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ec03d24
Instruction Parser only runs when it is executed from right directory now
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65544d5
First memory test runs
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3e98160
Finish memory Tests
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e9ded79
Add InstructionParser test
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9f0ede7
Create module encompassing ALU, RegFile, and Memory

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5d88194
Create makefile to build modules

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d69f56c
Create test bench for core module

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fc38651
Add alu files

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f83bd5a
Add inputs and outputs to module definition

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9461de9
Build core testbenches

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ed5486c
Add register file related modules

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1c69c4e
Add build rules for regfile modules

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55b480a
Add memory files

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6bdb2e3
Add build rules for memory

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c5a29b6
Add module for 4 input mux

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dff2583
Add tests for 4 input module

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8f3e391
Add new module for four input multiplexer

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fa6048c
Parametize 4 input mux for code reuse

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e7ae586
Add zero flag

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02f0983
Add new modules

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e7cd21f
Change address size

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fdae91f
Add signextend module

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9a7420b
Change mem and addr size

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18a87f2
Change address size

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bebf55b
Change width of regfile addresses

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ccd5b91
Move core module files to subfolder

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753b8b9
Initialize memory

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c40951b
Add test cases

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1a51e26
Create file of initialized memory

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3faa596
Connect Da wire

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17c141a
Implement tests for addi, lw, sw

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authored and
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8d1c6ea
Update module references

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authored and
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e8d8325
update file paths

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authored and
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76a4b82
Update file paths

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f3d270f
Move files to subfolder

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1425420
work on pc calculator

apan64
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ae079f4
Implement module

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a274de0
Update Core instantiation

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authored and
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5089cb6
Update file references

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authored and
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2844250
Remove old files that have been replaced

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authored and
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committed
2a1963a
Change address size in test

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authored and
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committed
fa00d5b
Change size of 2d array to correct width

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authored and
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committed
f1a4d56
Add build rules for new modules

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authored and
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3b91494
Add remaining tests

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8947a7f
Merge branch 'Instruction_Parser' of https://github.com/arianaolson419/Lab3
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97cfde6
Add absolute position of modules
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9045aca
Merge branch 'master' of github.com:arianaolson419/Lab3
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d91c261
Merge branch 'master' of github.com:arianaolson419/Lab3
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a6570d4
Merge branch 'master' of github.com:arianaolson419/Lab3
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ae62c42
Make it so mem does not reference backwards
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ac5ec57

Commits on Nov 13, 2017

Make top level directory run (sort of)
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94d7a19
pc calc and test
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9e88935
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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c457870
removed merge heads
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7b0b78f
moved mux to submodules
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8996686
fixed mux overlap
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6c90c51
Register no longer give warning
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b8e0478
Add fibonacci program
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24d1c33
Update with new modules
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6297e26
Add test module
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652dcc9
Fix typo
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3cb495c
Connect missing registers
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91b3edf
Start writing testbench
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7ce4790
Add missing ports to Core instantiation
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e23c325
Move all wires to top of module
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9809fa2
Change reference memory file
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caa2954
add CPU build target to all target
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297d129
Move to more local location for Core use only
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a635a72
Ignore mem.dat
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6d98b24
Write assmebly to use as test expressions
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de9792c
Instantiate instruction memory
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d4b5112

Commits on Nov 14, 2017

make stuff compile
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91ba871
Make gtkwave file
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9ffa298
switch inputs to DFF
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92f769e
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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af019e9
got 0s at first
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b9844a9
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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0eb5c19
Remove debugging statement
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17c8bf0
Change PC to be divided by 4
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4a20766
Fix error where PC was updating after one timestep
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cd79cc2
Run tests without ./run_program
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2460bab
Specify dump vars
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a66e041
Add longer enable delay
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9e61113
Remove print statement
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57662c4
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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39c9df2
removed some output wires that I forgot about
apan64
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9fd6005
Add first unit tests
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9e2369b
Merge branch 'master' of github.com:arianaolson419/Lab3
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e26c0ab
Change immediate for easier differentiation
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caf925e

Commits on Nov 15, 2017

fixed the wiring for core and pc_calc
apan64
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fbc482c
Merge branch 'master' of https://github.com/arianaolson419/Lab3
apan64
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b43acbc
Make tests work
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eec285f
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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5d5bd8a
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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7f3e283
Merge branch 'master' of github.com:arianaolson419/Lab3
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9be9a5f
Add another test
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6da68cf
Fix bug where PC would be xs after LW/SW
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bce1b2d
Change test instructions for diagnostics
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f4d10b9
Diasble memory overwrite and add clock cycles
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9f882b6
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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282c12a
created xori test
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fca980a
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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6776bdc

Commits on Nov 16, 2017

Fix the slt command number
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a2517b6
Correct the size of the 4input mux
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b9d425a
Run the 4input mux test with the test harness
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990c21b
run tests from memory dumped from assembly program
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e00a6cf
Dump new progeam from assembly
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13143af
Remove unused file
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4c7baf7
Create small unit test programs in assembly
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ded7550
Create memory file to write to mem.dat
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4bbbc22
Modify test strategy
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e60a622
Finish running through unit tests
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6eedb46
Partway done with README.md
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6edc04f
fixed load word timing issue
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efd0912
Add clock cycles to run to program end
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a0f6b2f
set CPU.t.v back to unit tests
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24a9525
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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f13f0aa
Start adding lw tests
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a4244e9
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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168f4b1
Add Control Signal Table to Readme
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7fb5c61

Commits on Nov 17, 2017

added cpu fib test
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25a6aff
Merge branch 'master' of https://github.com/arianaolson419/Lab3
apan64
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64837ba
Finish unit tests
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fa10da0
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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da14659
Uncomment and unhardcode reg29
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f48258d
added a fib test to make
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08422fc
Change size of memory
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8288225
Initialize smaller sp
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6368ed2
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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fdfb750
Add static images
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3612a7e
Add images to README
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554df32
added to design section
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1b194d1
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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ab66134
added to testing section
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eec21d1
added work plan section
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29c1293
Delete extra stuff in README
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6adab28
reused components section added to design
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Merge branch 'master' of https://github.com/arianaolson419/Lab3
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5fcb768
added commands for tests
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81ec16d
Modify for CPU constraints
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fcafe0f
hopefully fixed md formatting
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79d3af6
Split file into several testbenches
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0001e9b
typo
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Create testbench for each program
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e787bdc
Update build targets
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b2cad1b
Initialize entire memory with 0s
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1fcb2d7
Remove automatically generated file
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1c355ad
Create bash script to run tests
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Merge branch 'master' of https://github.com/arianaolson419/Lab3
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73a89e9
Add sentence to beginning of readme
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80e952f
Fix broken test
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Dump memory to core tests
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5ba9371
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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f4e0bec
Fix file ref
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48319d5
Fix test
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0072f21
test case only displays on fail
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1ee2cac
Merge branch 'master' of https://github.com/arianaolson419/Lab3
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