diff --git a/.github/workflows/go-ci.yml b/.github/workflows/go-ci.yml index 39dd98fc..8a33ad03 100644 --- a/.github/workflows/go-ci.yml +++ b/.github/workflows/go-ci.yml @@ -75,6 +75,43 @@ jobs: - name: ARM64 Plan 9 reference corpus run: scripts/check-arm64-plan9-corpus.sh + benchmark: + name: compile benchmark (Go 1.27, LLVM 22) + runs-on: ${{ github.repository_owner == 'xgo-dev' && fromJSON('["qiniu", "ubuntu-24.04-large"]') || 'ubuntu-24.04' }} + timeout-minutes: 20 + + steps: + - name: Checkout + uses: actions/checkout@v7 + + - name: Install LLVM 22 + run: | + echo "deb http://apt.llvm.org/$(lsb_release -cs)/ llvm-toolchain-$(lsb_release -cs)-22 main" | sudo tee /etc/apt/sources.list.d/llvm.list + wget -qO- https://apt.llvm.org/llvm-snapshot.gpg.key | sudo tee /etc/apt/trusted.gpg.d/llvm-snapshot.asc >/dev/null + sudo apt-get update + sudo apt-get install -y llvm-22-dev clang-22 libclang-22-dev lld-22 libunwind-22-dev libc++-22-dev + echo "PATH=/usr/lib/llvm-22/bin:$PATH" >> "$GITHUB_ENV" + + - name: Setup Go + uses: ./.github/actions/setup-go + with: + go-version: '1.27.x' + cache: true + + - name: Translate and compile standard-library assembly + env: + PLAN9ASM_BENCHMARK_MAX_TARGET_SECONDS: '300' + PLAN9ASM_BENCHMARK_MAX_TOTAL_SECONDS: '900' + run: scripts/benchmark-compile.sh + + - name: Upload benchmark report + if: always() + uses: actions/upload-artifact@v6 + with: + name: compile-benchmark + path: _out/compile-benchmark + if-no-files-found: error + reported_library_list: name: Third-party corpus matrix runs-on: ${{ github.repository_owner == 'xgo-dev' && fromJSON('["qiniu", "ubuntu-24.04-large"]') || 'ubuntu-24.04' }} @@ -128,6 +165,67 @@ jobs: REPORTED_LIBRARY: ${{ matrix.library }} run: scripts/check-reported-library-corpus.sh "$REPORTED_LIBRARY" + discovered_library_corpus: + name: discovered-corpus (shard ${{ matrix.shard }}/32) + runs-on: ${{ github.repository_owner == 'xgo-dev' && fromJSON('["qiniu", "ubuntu-24.04-large"]') || 'ubuntu-24.04' }} + strategy: + fail-fast: false + matrix: + shard: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31] + + steps: + - name: Checkout + uses: actions/checkout@v7 + + - name: Install LLVM 22 + run: | + echo "deb http://apt.llvm.org/$(lsb_release -cs)/ llvm-toolchain-$(lsb_release -cs)-22 main" | sudo tee /etc/apt/sources.list.d/llvm.list + wget -qO- https://apt.llvm.org/llvm-snapshot.gpg.key | sudo tee /etc/apt/trusted.gpg.d/llvm-snapshot.asc >/dev/null + sudo apt-get update + sudo apt-get install -y llvm-22-dev clang-22 libclang-22-dev lld-22 libunwind-22-dev libc++-22-dev + echo "PATH=/usr/lib/llvm-22/bin:$PATH" >> "$GITHUB_ENV" + + - name: Setup Go + uses: ./.github/actions/setup-go + with: + go-version: '1.27.x' + cache: true + + - name: Translate and compile discovered assembly + run: scripts/check-discovered-library-corpus.sh "${{ matrix.shard }}" 32 + + - name: Upload shard report + if: always() + uses: actions/upload-artifact@v6 + with: + name: discovered-corpus-shard-${{ matrix.shard }} + path: _out/discovered-library-corpus/shard-${{ matrix.shard }}.json + if-no-files-found: error + + discovered_library_corpus_verify: + name: discovered-corpus aggregate verification + needs: discovered_library_corpus + runs-on: ${{ github.repository_owner == 'xgo-dev' && fromJSON('["qiniu", "ubuntu-24.04-large"]') || 'ubuntu-24.04' }} + steps: + - name: Checkout + uses: actions/checkout@v7 + + - name: Setup Go + uses: ./.github/actions/setup-go + with: + go-version: '1.27.x' + cache: true + + - name: Download shard reports + uses: actions/download-artifact@v8 + with: + pattern: discovered-corpus-shard-* + path: _out/discovered-library-corpus + merge-multiple: true + + - name: Verify complete ledger coverage + run: scripts/verify-discovered-library-corpus.sh + stdlib-corpus: name: stdlib-corpus (${{ matrix.os }}, Go ${{ matrix.go-version }}) runs-on: ${{ github.repository_owner == 'xgo-dev' && matrix.runner || matrix.os }} @@ -428,7 +526,7 @@ jobs: echo "PATH=/usr/lib/llvm-22/bin:$PATH" >> "$GITHUB_ENV" - name: Go test (race) - run: go test -race ./... + run: go test -race -timeout=20m ./... coverage: runs-on: ${{ github.repository_owner == 'xgo-dev' && fromJSON('["qiniu", "ubuntu-24.04-large"]') || 'ubuntu-24.04' }} diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..bbe7e64e --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +/_out/ diff --git a/AGENTS.md b/AGENTS.md new file mode 100644 index 00000000..41e54d39 --- /dev/null +++ b/AGENTS.md @@ -0,0 +1,1860 @@ +# plan9asm development guide + +This repository translates Go Plan 9 assembly to LLVM IR. Changes are complete +only when the accepted operand forms match the Go assembler, the generated IR +is accepted by LLVM 22, and the relevant runtime semantics are tested. + +## Active work checkpoint + +The current ecosystem-coverage work lives in the worktree +`/private/tmp/plan9asm-pr40-current.eJNnNq`, branch +`codex/expand-ecosystem-corpus-20260913`, and draft PR +`https://github.com/xgo-dev/plan9asm/pull/40`. Preserve the worktree and inspect +it with `git status --short` before editing. The contribution history is based +directly on `xgo-dev/main`; obsolete per-run ledgers and compressed reports must +not reappear in any commit when the branch is updated. + +The current ledger checkpoint uses newest-to-oldest discovery. It contains +257,098 precisely ranged Go index entries, 98,276 successfully inspected exact +module versions, 98,525 unique module paths, 848 assembly-bearing exact +versions containing 10,456 assembly files, and 4,205 failures retained for +retry. Its derived history cursor is `2026-09-13T09:56:42.949703Z`; its derived +incremental cursor is `2026-09-15T16:56:51.924668Z`. Both come from +`testdata/discovery/ledger/manifest.json#index_ranges`, not separately stored +cursor fields. The former 320,400-entry aggregate +mixed two non-contiguous forward windows and is no longer counted as coverage. +The old multi-run ledger is consolidated into the single `records/` layout, +including in the rewritten contribution history. + +The metrics in this opening checkpoint are authoritative. The later per-shard +narrative is retained as implementation history and TDD evidence; its older +intermediate candidate counts must not be used for the PR funnel. + +Local work has added broad x86/ARM/wasm instruction coverage. In addition to +the x86 binary-floating and horizontal-floating work, the complete Go 1.27 x87 +move, arithmetic, comparison, constant, transcendental, environment, and +control families now translate and compile with LLVM 22. ARM has complete +scalar `MOVF`/`MOVD`, float unary/conversion, integer `DIV`/`DIVU`/`MOD`/`MODU`, +and `SLL`/`SRL`/`SRA` families, including FP-addressed classic stack slots. +Shard 3 added the whole ARM AADDF-derived scalar arithmetic family (F/D, +two-/three-register, negative, accumulate, fused, and negative-fused forms), +all `MOVWF`/`MOVWD`/`MOVFW`/`MOVDW` signed/unsigned register conversions, and +the complete `PLD C_SOREG` form. It also added `CMPF`/`CMPD`, decoded raw +`VCMP`/`VCMPE` plus `VMRS APSR_nzcv,FPSCR` sequences (including split S-register +D/M bits), and completed `MOVW` general/F-register bit transfers. ARM now +always uses the architecture-aware CFG lowerer in both translation entry +points; do not restore the old straight-line fallback because it silently +accepted forms absent from the Go tables. Wasm has the complete F32/F64 unary +family and accepts Go metadata directives. Legacy `TEXT name+0(SB)` +normalization, safe `GOROOT/pkg/include` expansion, Go TLS pseudo-register +parsing, and arithmetic constant displacements such as `0+(1*16)(BP)` are also +present. + +Shard 2 exposed and now has focused red/green coverage for all four legacy x86 +prefetch hints and the Plan 9 x86 `MOVD` alias. Go's x86 frontend maps `MOVD` +to `AMOVQ`; do not lower its XMM memory forms as Intel's 32-bit MOVD. Shard 3 +also completed the legacy integer-to-float conversion family, scalar +`VBROADCASTSS`/`VBROADCASTSD`, and signed/unsigned dword-to-qword multiply +families. Their accepted 386 and amd64 operand classes are validated separately +against Go 1.27 and both triples are compiled by LLVM 22. `PMULULQ`'s MMX form +is amd64-only even though its XMM form is valid on 386. Shard 3 also completed +ARM64's eight signed/unsigned 32-/64-bit integer-to-float S/D conversions and +all eighteen scalar floating binary S/D operations, including correct +NaN-propagating `FMAX`/`FMIN` versus number-selecting `FMAXNM`/`FMINNM` +intrinsics. Those families compile for Darwin, Linux, and Windows ARM64 with +LLVM 22. + +Shard 4 completed three more mechanisms. ARM64 tailcalls now adapt the full +`i1`/`i8`/`i16`/`i32`/`i64` return-width matrix with `trunc`/`zext`, plus +`ptr`/`i64`; keep the matrix test rather than special-casing `bool`. X86 now +implements the complete Go `yin`/`ynone` port-I/O families: `INB`/`INW`/`INL` +and `OUTB`/`OUTW`/`OUTL` with no operand or one 32-bit immediate, and +`INSB`/`INSW`/`INSL` plus `OUTSB`/`OUTSW`/`OUTSL` with no operands. Their +fixed-register effects, memory clobbers, updated string index/count registers, +and `REP`/`REPN` forms are expressed with constrained inline assembly and +compiled for 386 and amd64 by LLVM 22. The related ordinary string families +`MOVS`/`STOS`/`SCAS` are now complete for B/W/L on 386 and B/W/L/Q on amd64, +including bare, `REP`, `REPN`, forward, and backward forms. Do not restore the +old amd64 behavior that silently discarded `REP` and executed `MOVSB` once. + +The parser accepts both Go-supported global declaration grammars, +`GLOBL sym(SB), $size` and `GLOBL sym(SB), flags, $size`; Go 1.27 assembler +acceptance of the historical two-operand form was verified against +`github.com/tonnerre/golang-go.crypto`. `FrameSlot.Name` preserves source-level +Go result names. On 386, a unique named result can correct a stale numeric FP +offset in legacy assembly; anonymous results and aggregate results with several +physical slots retain strict numeric-offset matching. This is required by +`github.com/sigma/vmw-guestinfo` and must not be weakened into accepting +arbitrary unknown frame writes. + +Discovery now proves package applicability with an exact-package current-Go +build and applies `go vet -asmdecl` only to concrete FP/argument ABI +mismatches; generic vet diagnostics must still reach the translator. The +`plan9asmll` Go-package driver selects `WASMABIGo` for `GOARCH=wasm`, because +Go package assembly uses the resumable linear-memory stack ABI rather than the +direct LLGo ABI. ARM and ARM64 tailcalls adapt all integer result widths with LLVM +`trunc`/`zext`; this is needed when a local assembly helper has only a fallback +signature but the public Go declaration returns `bool`. + +The current 848-candidate checkpoint has all 32 canonical reports green: 692 +passing candidates, 156 structured source N/A candidates, zero failures, 11,790 +LLVM 22 translations, and 50 target-level N/A translations. These values come +from `_out/discovered-library-corpus/shard-{0..31}.json`; ignore historical +files with suffixes such as `-fixed` or `-dev`. A targeted `linux/arm64` replay also +proved the saved-path query path: it selected 316 of the then-current assembly-bearing +versions without reading the module index or revisiting no-assembly records. +The candidate deadline covers download, current-Go build and asmdecl checks, +and every applicable target translation for that exact version. Keep it at 60 +minutes by default: shared Linux runners exhausted the former 15-minute budget +while making forward progress through large generated candidates such as +`github.com/goplus/reflectx@v1.7.9` and +`github.com/goccy/llamawasm2go@v0.4.1`. A deadline remains a hard shard failure, +never N/A or success; override it only through +`PLAN9ASM_DISCOVERY_CANDIDATE_TIMEOUT` when diagnosing. Commit `03ecbd9` makes +`go_asm.h` layout expansion inspect +only referenced concrete structs, so the generic types in +`github.laiyagushi.com/richardwilkes/canvas@v0.3.1` no longer panic `go/types`. +Canvas now passes four applicable assembly files across five target +configurations (10 translations). +Shard 18 itself was green with 22 passing +candidates, 2 source N/A candidates, 492 translations, and 26 target-level N/A +translations. It independently exposed and now passes extended amd64 byte +register aliases in `github.com/bronze1man/AesCtr` and +`github.com/issuj/gofaster`, all `JCXZW/JCXZL/JCXZQ` counter-zero branches in +`github.com/clmul/checksum`, and the complete PALIGNR/VPALIGNR, +PCLMULQDQ/VPCLMULQDQ, and PSLLO/PSLLDQ/PSRLO/PSRLDQ/VPSLLDQ/VPSRLDQ families +needed by `github.com/nspcc-dev/tzhash`. Those families have Go 1.27 +positive/negative form tests, all applicable x86 platform object tests, LLVM +22 semantic runtime tests, and supported-op extraction assertions. + +Discovery records can also contain `_test_.s` files. When an exact file +set contains test assembly, `plan9asmll` loads Go package test variants and +prefers their type scope for translation; otherwise declarations that exist +only in `_test.go` incorrectly degrade to the integer fallback ABI. Keep +`cmd/plan9asmll/testdata/testsignature` as the regression for a `float32` +result written by `MOVSS`. Do not fix this class of failure by accepting an +`i64`/float frame mismatch. + +Shard 19 is green with 15 passing candidates, 5 source N/A candidates, 138 +translations, and 21 target-level N/A translations. TDD failures independently +exposed `RCLQ/RCRQ` memory forms in `github.com/kilic/fp256`, `PSHUFLW` in +`github.com/ledao/arrgo`, and `VAESENC` in `github.com/mengzhuo/nabhash`. The +fixes cover the complete Go 1.27 RCL/RCR B/W/L/Q family, the legacy/VEX/EVEX +PSHUFHW/PSHUFLW family, and the AES/VAES round, inverse-mix-column, and +keygen-assist family. Its report remains useful as the per-family TDD evidence; +the aggregate checkpoint immediately above now also includes shard 20. + +Shard 20 is green with 12 passing candidates, 9 source N/A candidates, 122 +translations, and no target-level N/A translations. Its only initial failure +was a module requiring Go 1.27.1 while the scanner runs Go 1.27.0 with +`GOTOOLCHAIN=local`: `go mod download -json` had already cached a verified ZIP +but returned nonzero without a module directory. The corpus runner now parses +metadata even on nonzero exit and safely materializes an available module ZIP; +the later Go build version rejection is retained as explicit per-target source +N/A evidence. + +Shards 21 through 23 are green. Together they add 43 passing candidates, 12 +source N/A candidates, 360 translations, and no target-level N/A translations; +none exposed a new opcode or form gap. Shard 24 is green with 17 passing +candidates, 4 source N/A candidates, 735 translations, and 46 target-level N/A +translations. Its TDD failure in `github.com/chewxy/math32` exposed +`CVTSS2SL`; the fix covers the complete Go 1.27 scalar float-to-integer family: +eight legacy signed forms, eight VEX/EVEX signed forms, and eight EVEX unsigned +forms, including memory sources and the register-only embedded rounding/SAE +forms. Shard 25 is green with 22 passing candidates, 1 source N/A candidate, +242 translations, no target-level N/A translations, and no new form gap. +Shard 26 is green with 10 passing candidates, 4 source N/A candidates, 177 +translations, no target-level N/A translations, and no new form gap. It also +proves that the generic ledger/discovery path independently selects and passes +`github.com/vmware/vmw-guestinfo`; it is not a hard-coded issue fixture. +Shard 27 is green with 12 passing candidates, 5 source N/A candidates, 100 +translations, no target-level N/A translations, and no new form gap. Shard 28 +is green with 18 passing candidates, 5 source N/A candidates, 422 translations, +and 35 target-level N/A translations. TDD failures independently exposed +`ROUNDSD` in `github.com/mdempsky/go` and `BOUNDL` in `rsc.io/tmp`; the fixes +cover the complete Go 1.27 legacy/VEX ROUND family and the 386-only BOUNDW/L +family. ROUND has a five-platform form matrix and LLVM runtime semantics for +all rounding modes plus scalar upper-lane preservation. BOUND is emitted as +the exact 62 /r encoding with fixed AX/CX constraints because LLVM 22 rejects +the mnemonic itself. Shard 29 is green with 18 passing candidates, 10 source +N/A candidates, 166 translations, 12 target-level N/A translations, and no new +form gap. Shard 30 is green with 17 passing candidates, 3 source N/A candidates, 292 +translations, 23 target-level N/A translations, and no new form gap. Shard 0 +and shard 31 have both been regenerated from this worktree. + +Shard 31 is green with 22 passing candidates, 4 source N/A candidates, 423 +translations, and 27 target-level N/A translations. `github.com/cloudflare/circl` +independently exposed the complete x86 CLC/STC/CMC carry-control family, the +complete ADC/SBB B/W/L/Q family and its memory destinations, and ARM64's +NEG/NEGW/NEGS/NEGSW plus NGC/NGCW/NGCS/NGCSW families. Their legal operand +rows come from Go 1.27, all applicable OS/architecture targets compile with +LLVM 22, and runtime tests cover carry/borrow, overflow, and NZCV semantics. +`github.com/notti/nocgo` exposed a signature-inference gap: a declaration-free +direct tail-forwarding TEXT now inherits the complete ABI only when all of its +external tail targets have declared, identical signatures. This fixes 386 C-ABI +trampolines without changing the conservative fallback for genuine undeclared +register-return assembly. + +Go 1.27.1 made `github.com/usbarmory/tamago@v1.27.1` applicable where Go +1.27.0 had correctly classified it as source N/A. Its KVM clock helper exposed +the raw AMD system-management opcode `0F 01 D9`. Keep the complete fixed +`0F 01 D8-DF` family together: `VMRUN`, `VMMCALL`, `VMLOAD`, `VMSAVE`, `STGI`, +`CLGI`, `SKINIT`, and `INVLPGA`. The decoder, implicit-register lowering, +negative operand tests, supported-op extraction, and LLVM 22 object tests cover +both 386 and amd64 across all five x86 target triples. Discovery must run with +the latest Go 1.27 patch in PATH; setting only `GOTOOLCHAIN=go1.27.1` is +insufficient because the corpus deliberately forces subprocesses to +`GOTOOLCHAIN=local`. + +Shard 5 added two x86 mechanisms. Scalar `MOVL` may store either a GP register +or immediate into an FP result slot but rejects memory-to-memory forms. The +complete Go 1.27 `ydivb`, `ydivl`, `yimul`, and `yimul3` families now cover +`MUL`/`IMUL`/`DIV`/`IDIV` B/W/L/Q and `IMUL3` W/L/Q, with implicit AX or DX:AX +results, all GP/memory sources, IMUL immediate/register/memory forms, correct +386 Q-width rejection, multiply CF/OF behavior, and LLVM 22 object compilation +on both i386 and x86_64. Keep the full opcode switch in +`amd64_lower_muldiv_scalar.go`: both supported-op extractors rely on literal +case labels and must not silently omit a lowerable opcode. This fixes all +`github.com/bjwbell/gensimd` failures; one of its nine files is a structured +target N/A because its explicit TEXT arg size disagrees with the Go declaration. + +Shard 6 hardened applicability evidence. An `unexpected EOF` accompanied by a +local `.s` diagnostic and `asm: assembly of ... failed` is deterministic source +rejection, not a transient proxy EOF. Also, old package tests can fail type +checking before `go vet -asmdecl` analyzes otherwise buildable production +assembly. On a generic vet failure, Discovery now copies the owning module out +of `GOMODCACHE`, replaces its test files with empty same-package files via a +temporary modfile, and reruns asmdecl. This is necessary because the Go command +forbids overlays under `GOMODCACHE`. The mechanism gives +`github.com/neclepsio/qml` concrete invalid-FP-offset evidence, while +`github.com/v2pro/plz` excludes only its truncated 386/ARM sources and still +translates its valid amd64/ARM64 files. Keep the focused tests in +`cmd/plan9asmcorpus/discovery_test.go`; do not collapse local assembler EOFs +back into infrastructure retry records. + +Use final JSON aggregation for the PR funnel rather than recomputing this +prose. All 32 discovery shards were verified for the current 848 matched versions +before the upstream integration described below. +The committed official Go form baselines cover Go 1.20 through Go 1.27 for +386, amd64, ARM, ARM64, and wasm. The Go 1.27 official corpus now has zero +unsupported forms and zero parse errors on all five architectures. Its final +supported/context/unsupported counts are: 386 `50/7/0`, amd64 `6734/6/0`, ARM +`455/44/0`, ARM64 `1980/68/0`, and wasm `0/120/0`. The coverage fingerprints +are respectively `a761cab88cc51f2073bb6215c65316cdda26c801e10ca41a346f3f39b18d9b3d`, +`786c884a97756aff577826e58042c0f83ed97d42e7d754eb9d0aa1731205718c`, +`e4b40628c50da969e06d93552884a0c27e276a361d45cb221ccfc5c82c5a11bc`, +`375e6ad3881b96ec7b98f566f3a04060569b35687790c8700a4aec1e27bd5f25`, +and `4e31258d9b2a04e72dafc936139407050163282fb04b79e9a0b7c3afe0b6a22f`. +The latest ARM64 report is +`_out/official-coverage-100/arm64-complete.json`; it has 2,048 unique forms, +zero parse errors, all 26 normalized `ZLDFF1*` forms supported, and all 85 +normalized ordinary `ZLD1*`/`ZST1*` forms supported. All 60 normalized +structured `ZLD2/3/4*`/`ZST2/3/4*` forms are supported, including the SVE2.1 +Q-granule forms. All 16 Go encoder forms (seven normalized corpus forms) in the +non-faulting `ZLDNF1*` family are supported as well. The complete replicate-load +family contributes another 32 Go encoder forms +(23 normalized corpus forms): `ZLD1R*`, `ZLD1RO*`, and `ZLD1RQ*`. LLVM 22 +requires `+f64mm` specifically for `ZLD1RO*`; `ZLD1RQ*` requires only SVE. The +four `CTERMEQ`/`CTERMNE` X/W forms are emitted as exact side-effecting LLVM +inline assembly under `+sve`, preserving their architectural behavior. The +complete 16-opcode SVE integer-reduction family is also supported: ordinary +`ZANDV*`/`ZEORV*`/`ZORV*` forms retain Go's generic-source size-bit OR behavior, +while `ZADDQV`/`ZANDQV`/`ZEORQV`/`ZORQV` require matching full-width SIMD +destinations and `+sve2p1`. The nine-opcode add-reduction family is complete as +well: `ZFADDA*`/`ZFADDV*`, `ZFADDQV`, and `ZSADDVD`/`ZUADDVD` cover all 28 Go +encoder combinations, including destructive scalar accumulation and the +signed/unsigned integer source-width distinction. The 27-opcode SVE2 +widening/narrowing add/subtract family covers all 81 B/H/S/D width combinations: +signed and unsigned long/wide operations plus high-half, rounded-high-half, and +top-merge narrowing. The `*HNT` lowering preserves the old destination through +LLVM's merged narrowing intrinsic. The complete 14-opcode signed/unsigned +absolute-difference family covers all 46 Go forms: predicated `SABD/UABD`, +same-width `SABA/UABA`, widening bottom/top difference and accumulate, and +predicated pairwise long accumulate. All 32 Go forms in the signed/unsigned, +rounded/non-rounded halving add/subtract family are supported as well, +including the distinct reverse-subtract intrinsics. The signed/unsigned SVE +integer divide and reverse-divide family covers every Go S/D form under +`+sve`. The six destructive D-width SVE2 ternary bitwise operations +`BCAX`/`BSL`/`BSL1N`/`BSL2N`/`EOR3`/`NBSL` are complete with hardware operand +order preserved. The complete SVE2 bit-permutation family covers all 12 Go +encoder forms of `BDEP`/`BEXT`/`BGRP` across B/H/S/D widths and explicitly +requires LLVM 22's `+sve-bitperm` feature in addition to SVE2. The complete +SVE2 long carry/borrow family covers all eight S/D encoder forms of +`ADCLB`/`ADCLT`/`SBCLB`/`SBCLT`; lowering preserves the destructive `Zda` +accumulator and LLVM's architectural `Zda, Zn, Zm` operand order. The complete +SVE clamp family covers all 12 integer, IEEE floating-point, and +BF16 Go encoder forms. BF16 is lowered as LLVM `bfloat` under +`+sve-b16b16`; integer and IEEE forms require `+sve2p1`. The signed and +unsigned SVE unpack-high/unpack-low family covers all 12 B-to-H, H-to-S, and +S-to-D widening forms under `+sve`. The complete six-opcode SVE2 saturating +narrow family covers all 18 H-to-B, S-to-H, and D-to-S forms; every top-half +form merges the old narrow destination through LLVM's merged intrinsic. The +four-opcode SVE2 right-shift narrowing family covers rounded/non-rounded and +bottom/top forms, including every legal immediate boundary. Go 1.27 also +accepts shifts above the architectural destination-width limit; those forms +are rejected explicitly because LLVM 22 cannot select them and otherwise +aborts. The complete 12-opcode SVE2 saturating right-shift narrowing family +covers signed, unsigned, signed-to-unsigned, rounded/non-rounded, and +bottom/top variants across all three width pairs and legal immediate +boundaries, with the same explicit guard against Go's over-wide immediate +acceptance. The complete SVE2 variable rounding/saturating shift family adds +all 40 forms of `SQRSHL[R]`, `UQRSHL[R]`, `SQSHLR`, `UQSHLR`, `SRSHL[R]`, +and `URSHL[R]`. Reverse forms swap LLVM data/shift inputs and explicitly merge +the old destructive destination for inactive lanes. The complete SVE +`MAD`/`MSB` family covers all eight B/H/S/D encoder forms under `+sve`; its +lowering preserves the destructive `Zdn` input and maps Go's `Za, Zm, Pg/M, +Zdn` syntax to LLVM's predicate, destination, multiplier, addend/subtrahend +operand order. Both Go 1.27 `BFDOT` encoder forms are supported as well: the +H-vector and indexed H-lane variants accumulate into S elements under +`+bf16,+sve`, with the indexed source constrained to `Z0..Z7.H[0..3]`. The +complete signed, unsigned, and mixed-sign integer dot family covers all 17 Go +encoder forms of `SDOT`, `UDOT`, `SUDOT`, and `USDOT`, including B-to-H and +H-to-S two-way products, ordinary B-to-S and H-to-D products, and every indexed +register/lane boundary. Mixed-sign forms require `+i8mm`; B-to-H requires +`+sve2p3`. LLVM 22 declares but cannot select the B-to-H x2 intrinsic, so only +that width uses typed tied-output SVE inline assembly; every other width uses +the corresponding LLVM intrinsic. The destructive B-element SVE AES +MixColumns pair `AESIMC`/`AESMC` is complete as well and uses LLVM 22's +dedicated `+sve2-aes` feature rather than the insufficient `+sve2,+aes` +combination. The `EORBT`/`EORTB` bottom/top-interleaving family covers all +eight B/H/S/D Go forms under SVE2 while preserving the implicit old destination +operand. Both Q-element `REVD` forms are covered: `/M` preserves the old +destination under `+sve2p1`, while `/Z` supplies an explicit inactive zero and +requires `+sve2p2`. The SVE2.1 Q-granule permutation family `ZIPQ1/2` and +`UZPQ1/2` covers all 16 B/H/S/D forms; do not confuse its Q-granule operation +with the separate F64MM `.Q` element forms of ordinary `ZIP/UZP`. The adjacent +table extension family covers all 12 B/H/S/D forms of `TBLQ`, `TBX`, and +`TBXQ`; both TBX variants pass the old destination to LLVM as the out-of-range +fallback, and TBLQ requires exactly one table-list register. The complete +same-width polynomial multiply family currently consists of Go 1.27's single +`ZPMUL Zm.B, Zn.B, Zd.B` encoder form; it lowers through LLVM 22's SVE PMUL +intrinsic under `+sve,+sve2`. The complete widening bottom/top polynomial +multiply family covers both Go encoders for each of `ZPMULLB/T`: B-to-H, +S-to-D, and D-to-Q. The Q-granule pair form is represented as `nxv2i64` and +requires `+sve2-aes`; ordinary widening forms use SVE2. Keep the multi-vector +`PMULL/PMLAL` family separate because it has paired destinations and +destructive-accumulate semantics. That multi-vector family is now complete as +well: both D-source/Q-pair encoder forms require an even-odd destination range +and `+sve-aes2`, and PMLAL passes both old destinations to LLVM as accumulators. +`Operand.RegListRange` retains the source distinction between Go's accepted +`[Z4.Q-Z5.Q]` and rejected comma-list spelling, which otherwise parse to the +same registers. The complete SVE AES round family covers single-vector +`ZAESD/ZAESE` under `+sve2-aes` and every aligned x2/x4 lane form of +`ZAESD/ZAESDIMC/ZAESE/ZAESEMC` under `+sve,+sve-aes2`. Multi-vector forms +preserve all destructive destinations, accept key lane 0 through 3, and require +the repeated source/destination ranges to match exactly. The optional SVE2 +crypto family also covers the sole Go forms of `ZRAX1`, `ZSM4E`, and +`ZSM4EKEY`; they use LLVM 22's dedicated `+sve2-sha3` and `+sve2-sm4` +features, with SM4E preserving its repeated destructive destination. The +complete extra SVE shift family covers 52 concrete B/H/S/D forms across 13 +normalized opcodes: `ASRD`, reverse `ASR`/`LSL`/`LSR`, and the SVE2 immediate +insert, rounding, saturating, and accumulating shifts. Go 1.27's named +assembler accepts immediate values below (but not equal to) the element width; +the lowerer enforces those exact boundaries. Reverse shifts compute with an +all-true predicate and then select the old destructive destination for inactive +lanes, because directly using the governing merge predicate would preserve the +wrong LLVM operand. The complete 12-opcode SVE2 multiply-long family now +generalizes the earlier `UMULLB` mechanism across signed/unsigned bottom/top, +saturating doubling, and saturating doubling accumulate/subtract forms. Its 56 +concrete Go forms include all B/H/S vector widening and every H/S indexed-lane +boundary; `SQDMLALBT`/`SQDMLSLBT` correctly remain vector-only. The same table +drives named lowering, raw `WORD` decoding, target features, LLVM declarations, +and supported-op extraction. The complete five-opcode SVE matrix-multiply family +covers all 11 Go 1.27 forms: signed/unsigned/mixed I8MM, widening and +non-widening BF16, FP8-to-F16/F32, non-widening F16, widening F16-to-F32, and +F32/F64. LLVM 22 cannot select its declared BF16-H, FP8, and non-widening F16 +intrinsics when their results are used, so those forms use typed tied-output +inline assembly; all other forms use selectable intrinsics. Every feature set +was object-compiled on Darwin, Linux, and Windows ARM64, including +`+sve-b16mm`, `+sve2,+f8f16mm/+f8f32mm`, and `+sve2p2,+f16mm`. The +pairwise/tail add-subtract family covers all four B/H/S/D predicated +`ZADDP` forms and both predicated-destructive and unpredicated D-width forms of +`ZADDPT`/`ZSUBPT`. `ZADDP` uses LLVM's SVE2 intrinsic; the CPA tail operations +use typed inline assembly under `+cpa,+sve`. Predicate inline-asm operands use +LLVM's encoded `@3Upl` constraint and the full `nxv16i1` svbool value; plain +`Upl` is parsed as a memory constraint by LLVM 22. The complete vector +predicate increment/decrement family covers all 18 Go 1.27 +H/S/D forms of `ZDECP`/`ZINCP`/`ZSQDECP`/`ZSQINCP`/`ZUQDECP`/`ZUQINCP`. +The operand table deliberately excludes B elements. Ordinary forms lower from +`CNTP` through a per-element count splat and vector add/subtract; saturating +forms use LLVM's SVE intrinsics. All six require `+sve` and object-compile for +Darwin, Linux, and Windows ARM64. The complete widening shift-left-long family +covers all 12 B-to-H, H-to-S, and S-to-D forms of +`ZSSHLLB`/`ZSSHLLT`/`ZUSHLLB`/`ZUSHLLT`. Tests exercise both ends of each +Go 1.27 immediate range (`0..7`, `0..15`, and `0..31`) and reject the first +out-of-range value. The LLVM SVE2 intrinsics object-compile for Darwin, Linux, +and Windows ARM64. The floating reciprocal-step family covers all six H/S/D +forms of `ZFRECPS` and `ZFRSQRTS`, using LLVM's unpredicated SVE intrinsics +under `+sve`; B/Q, mismatched-width, and suffixed forms are rejected in lockstep +with the Go 1.27 assembler. The predicated floating pairwise family covers all +12 destructive H/S/D forms of `ZFABD`/`ZFADDP`/`ZFAMAX`/`ZFAMIN`, including +inactive-lane preservation. LLVM 22 requires the dedicated `+faminmax` feature +alongside `+sve2` for absolute min/max; every form object-compiles for Darwin, +Linux, and Windows ARM64. The SVE2 character-match family covers all four B/H +forms of `ZMATCH`/`ZNMATCH`, including zeroing P0..P7 governing predicates and +matching B/H result-predicate arrangements; Go-rejected S/D and mismatched +forms remain rejected. The complete SVE2 histogram family covers both S/D +zeroing-predicate `ZHISTCNT` forms and the sole B-vector `ZHISTSEG` form, with +all other widths and predicate modes rejected by both the Go oracle and the +translator. The complete CPA multiply-add-tail family covers the sole D-width +forms of `ZMADPT` and `ZMLAPT`; tied-output inline assembly preserves the old +destination and maps Go's reversed sources to architectural order under +`+cpa,+sve`. The complete SVE2 complex-add family covers all 16 B/H/S/D forms +of `ZCADD`/`ZSQCADD` at the only legal rotations, 90 and 270 degrees; lowering +preserves the repeated destructive destination through LLVM's indexed +intrinsics. `ZXAR` covers all B/H/S/D widths and the exact Go-accepted immediate +ranges `1..7`, `1..15`, `1..31`, and `1..63`; TDD confirms that both zero and +the element width itself are illegal despite the generated table's broader +range comment. `ZEXPAND` covers all four B/H/S/D forms with a bare P0..P7 +predicate; LLVM 22 requires `+sve2p2`, while merge/zero predicate spellings and +mismatched widths remain rejected. The floating exponent helper family covers +all three H/S/D `ZFEXPA` forms and all six H/S/D merge/zero `ZFLOGB` forms. +Lowering preserves the integer-to-float and float-to-integer vector type +directions, including old-destination passthrough for `/M` and explicit zero +for `/Z`. The floating-immediate family covers all H/S/D `ZFCPY` and `ZFDUP` +forms and the complete 256-value ARM floating-immediate domain. `ZFCPY` accepts +the actual Go/encoding-table predicate range P0..P15, not the P0..P7 range used +by most destructive SVE operations, and preserves inactive destination lanes. +The floating divide/scale family covers all H/S/D destructive `ZFDIV`, +`ZFDIVR`, and `ZFSCALE` forms with P0..P7/M. It uses LLVM 22's predicated SVE +intrinsics, explicitly preserves inactive destination lanes, and loads +`ZFSCALE`'s exponent operand as the required same-width integer vector. +The mixed-sign saturating add family covers all B/H/S/D destructive +`ZSUQADD`/`ZUSQADD` forms and preserves inactive lanes. LLVM 22 requires +`+sve,+sve2`; the focused object test must retain all Darwin, Linux, and +Windows triples because bare `+sve` aborts during instruction selection. +The SVE2 floating complex-add family covers all H/S/D `ZFCADD` forms at both +legal rotations, $90 and $270, with destructive P0..P7/M semantics and +inactive-lane preservation. +`ZDUPW` covers all B/H/S/D scalar GPR/SP broadcast forms by reusing the +width-sensitive general-register duplicate lowering. Keep `ZDUPM` and `ZDUPQ` +separate: they are logical-bitmask and indexed 128-bit-segment mechanisms, not +aliases of this GPR broadcast. +`ZDUPQ` now independently covers all B/H/S/D per-128-bit-segment lane +duplications, including the exact 0..15/0..7/0..3/0..1 index boundaries. It +uses the typed LLVM 22 `dupq.lane` intrinsic under `+sve,+sve2p1`; it must not +be replaced with an ordinary whole-vector splat. +`ZDUPM` independently covers B/H/S/D logical-bitmask splats. It reuses the +exhaustively tested SVE imm13 decoder/validator, rejects zero and all-ones +patterns exactly as Go does, and masks the emitted constant to the destination +element width. +`ZFDOT` covers all six Go encoder formats: FP8 B-to-H 2-way and B-to-S 4-way +dot products plus FP16 H-to-S 2-way dot products, each in vector and indexed +forms. Indexed Zm is limited to Z0..Z7 with exact lane maxima 7/3/3. Feature +inference is per instruction (`ssve-fp8dot2`, `ssve-fp8dot4`, or `f16f32dot`) +and LLVM 22 object generation passes on all three ARM64 triples. The official +report normalizes those six encoder forms into one operand-kind form, so the +supported/unsupported delta is one rather than six. +`ZCDOT` covers all four Go format classes: ordinary and indexed B-to-S and +H-to-D complex dot products, all rotations 0/90/180/270, and the exact indexed +register/lane limits Z0..Z7/0..3 and Z0..Z15/0..1. LLVM 22's lane intrinsic +receives `(lane, rotation)` in that order. The report likewise normalizes the +three encoder-table entries into one operand-kind form. +The lookup-table family covers all five Go encoder formats: `ZLUTI2` B/H +single-table and `ZLUTI4` B/H single-table plus H two-table forms. Tests cover +the exact lane maxima 3/7/1/3, matching widths, and Go's consecutive table-pair +rule including the legal Z31-to-Z0 wrap. LLVM 22 uses the typed `luti2.lane`, +`luti4.lane`, and `luti4.lane.x2` intrinsics under `+lut,+sve,+sve2`. The +official report normalizes the five encoder formats into two operand-kind +forms, hence this family's supported/unsupported delta is two. +The widening floating multiply-accumulate family covers all 20 Go encoder +formats across `ZFMLALB/T`, `ZFMLSLB/T`, and `ZFMLALLBB/BT/TB/TT`. The FP16 +H-to-S add/sub forms use ordinary and indexed SVE2 intrinsics; the FP8 B-to-H +and B-to-S add forms use LLVM 22's dedicated `sve.fp8` intrinsics under +`+fp8,+ssve-fp8fma,+sve,+sve2,+sve2p2`. Indexed sources are exactly Z0..Z7, +with H lanes 0..7 and B lanes 0..15. All 20 encoder forms normalize to eight +operand-kind forms, all now supported. +The SVE2.1 multi-vector narrowing family covers all nine Go encoder formats +(six normalized operand-kind forms) of `ZSQCVTN`, `ZSQCVTUN`, `ZUQCVTN`, +`ZSQRSHRN`, `ZSQRSHRUN`, and `ZUQRSHRN`. Sources must be a range-spelled pair +whose first register is even and whose second is the following odd register. +Conversion forms narrow S-to-H; shift forms cover H-to-B at shifts 1..8 and +S-to-H at shifts 1..16. LLVM 22 selects the target x2 intrinsics for S-to-H, +but aborts on all three declared H-to-B shift intrinsics. Those H-to-B forms +therefore use target-independent widening, rounding, saturation, truncation, +and `llvm.vector.interleave2` while still being object-compiled on Darwin, +Linux, and Windows ARM64; no form or missing tool is skipped. +The complete SVE floating narrowing-conversion family adds all 20 Go encoder +formats (15 normalized operand-kind forms) across `ZBF1CVT`, `ZBF1CVTLT`, +`ZBF2CVT`, `ZBF2CVTLT`, `ZF1CVT`, `ZF1CVTLT`, `ZF2CVT`, `ZF2CVTLT`, +`ZBFCVT`, `ZBFCVTN`, `ZBFCVTNT`, `ZFCVTN`, `ZFCVTNB`, and `ZFCVTNT`. +It covers FP8-to-F16/BF16 conversion, predicated F32-to-F16/BF16 and +F64-to-F32 top narrowing, and exact even/odd x2 range narrowing to FP8. +Tests require calls rather than declarations for every LLVM 22 intrinsic and +object-compile the union of `+bf16,+fp8,+sve,+sve2,+sve2p2` on Darwin, Linux, +and Windows ARM64. Independent feature-class tests are required as well: +predicated `ZFCVTNT ... P/M` needs `+sve2`, while its `P/Z` form requires +`+sve2p2`; the LLVM intrinsic declarations do not make that format-level +difference obvious, and the full-family feature union can otherwise hide it. +The complete basic BF16 arithmetic family covers all 12 Go encoder formats +(11 normalized operand-kind forms) of `ZBFADD`, `ZBFSUB`, `ZBFMUL`, +`ZBFMAX`, `ZBFMAXNM`, `ZBFMIN`, `ZBFMINNM`, and `ZBFSCALE`. It includes +destructive P0..P7/M forms, unpredicated add/subtract/multiply, and the exact +`Z0..Z7.H[0..7]` indexed multiply domain. Ordinary BF16 arithmetic uses +`+sve-b16b16`; BFScale independently uses `+sve-bfscale`. Both feature classes +are object-compiled separately on Darwin, Linux, and Windows ARM64 so their +union cannot mask an inference error. +The complete BF16 multiply-accumulate family covers all 12 Go encoder formats +(eight normalized operand-kind forms) of `ZBFMLA`, `ZBFMLS`, `ZBFMLALB/T`, +and `ZBFMLSLB/T`, including every vector form and the exact +`Z0..Z7.H[0..7]` indexed domain. Non-widening BF16 FMA uses +`+sve-b16b16`, widening add uses `+bf16,+sve`, and widening subtract uses +`+bf16,+sve,+sve2p1`; all three feature classes are object-compiled +independently on Darwin, Linux, and Windows ARM64. This family brings the +current Go 1.27 ARM64 official report to zero unsupported forms and zero parse +errors. +The amd64 cleanup now includes the complete Go 1.27 `XADDB/W/L/Q` family from +the `yrb_mb` and `yrl_ml` tables. Register and atomic-memory destinations, +symbol memory, 386 register restrictions, partial B/W writes, L zero extension, +Q full-width writes, source/destination exchange semantics, and all arithmetic +flags are covered. Its five-target LLVM 22 object matrix and Rosetta/native +runtime test reduced amd64 unsupported forms from 869 to 859; the current +report is `_out/official-coverage-100/amd64-xadd.json`, with fingerprint +`428088a8fc41184e481587899cdbf1a7abd5981e6879d3139c4785f85b7b1401`. +The complete `XCHGB/W/L/Q` family follows Go's two-way `yml_mb` byte table and +all four `yxchg` rows, including memory on either side, register-register forms, +symbol memory, and the 386 Q-width restriction. Sized writeback preserves B/W +upper bits, zero-extends L, and leaves flags unchanged; native/Rosetta runtime +coverage checks overlapping byte aliases, every width, reverse memory order, +and flag preservation. The amd64 official count is now 857 unsupported forms; +`_out/official-coverage-100/amd64-xchg.json` has zero parse errors and +fingerprint `5be662229ab70f480695b2f95ae2c45cd1a1c24dea0cf140650c314610b2a20f`. +The complete `NEGB/W/L/Q` `yscond(Ymb)` family now shares one sized lowering +for registers, ordinary/segment/frame/symbol memory, and rejects amd64-only +registers and Q width on 386. It preserves B/W upper bits, zero-extends L, and +sets CF/OF/ZF/SF/PF exactly as `0 - operand`. Five-target object compilation +and native/Rosetta runtime semantics cover zero, signed-minimum overflow, +partial-register writes, memory, and all modeled flags. The official amd64 +count is `5885/6/849`; `_out/official-coverage-100/amd64-neg.json` has zero +parse errors and fingerprint +`87753e6c449ed80937b9eb58d889ac58f2be6e889e762711e7955b11ca1f69ea`. +The complete BMI2 variable-shift family (`SARXL/Q`, `SHLXL/Q`, and `SHRXL/Q`) +now follows its sole Go 1.27 `_ybextrl` row: register count, register/memory +source, and register destination. Both widths remain accepted on 386 because +that is what the Go table and assembler specify, while extended registers are +rejected there. Count masking, signed/logical direction, dword zero extension, +operand aliasing, memory sources, and flag preservation have runtime coverage; +all five x86 triples compile with LLVM 22 and infer exactly `+bmi2`. The amd64 +official count is `5895/6/839`; report +`_out/official-coverage-100/amd64-bmi2-shift.json` has zero parse errors and +fingerprint `01e76c53611de84e55afdc8eb9eb2d185bbc9dcba60ea0c7250e8a2734751db9`. +The complete `LZCNTW/L/Q` `yml_rl` family now accepts register, ordinary +memory, and symbol sources, preserves 16-bit destination upper bits, zeroes +32-bit destination upper bits, and supports legal 386 SP destinations while +rejecting Q width there. It adds the missing `llvm.ctlz.i16` declaration and +infers `+lzcnt`. Runtime coverage checks zero input, top-bit input, memory, +CF/ZF, and all writeback widths; LLVM 22 compiles all five x86 triples. The +amd64 official count is `5901/6/833`; report +`_out/official-coverage-100/amd64-lzcnt.json` has zero parse errors and +fingerprint `7c2f91e2030de596e923453640880a964ebca080c985286452194ee2234857c1`. +The complete ADX carry-chain family (`ADCXL/Q` and `ADOXL/Q`) now follows its +sole Go 1.27 `yml_rl` row: register/memory source and register destination, +with Q width rejected on 386. ADCX consumes and updates only CF; ADOX consumes +and updates only OF. Runtime coverage checks both independent chains, preserved +flags, memory sources, and L-width zero extension. All five x86 triples compile +with LLVM 22 and infer exactly `+adx`. The amd64 official count is +`5905/6/829`; report `_out/official-coverage-100/amd64-adx.json` has zero parse +errors and fingerprint +`856d8a2276e02030de25d44a90c1f29742aaefed72369965835d48d6877de5d1`. +The complete `BEXTRL/Q` family now follows the Go 1.27 `_ybextrl` row on both +386 and amd64: register control, register/memory source, and register +destination. It validates all three operand classes, uses the correct `+bmi` +feature instead of `+bmi2`, zero-extends L destinations, and updates the +defined ZF/CF/OF flags. Runtime coverage checks out-of-range starts, lengths +that cross the operand boundary, memory sources, and destination/control +aliasing. All five x86 triples compile with LLVM 22. The amd64 official count +is `5907/6/827`; report `_out/official-coverage-100/amd64-bextr.json` has zero +parse errors and fingerprint +`1ebcafca3a6d7175002f54077bf6d3c56b13c654ab7456957737c8ea0a4f9cc9`. +The complete BMI2 `BZHIL/Q` family now follows the same Go 1.27 `_ybextrl` +operand row on 386 and amd64. It validates register index, register/memory +source, and register destination; uses only the index's low byte; zero-extends +L destinations; sets CF for an out-of-range index; clears OF; and updates +ZF/SF. Runtime coverage includes the zero boundary, operand-width boundary, +ignored high index bits, memory sources, and destination/index aliasing. All +five x86 triples compile with LLVM 22 under `+bmi2`. The amd64 official count +is `5909/6/825`; report `_out/official-coverage-100/amd64-bzhi.json` has zero +parse errors and fingerprint +`d82f203bb2ce079d28ab95bac80712a064b0f1bd40dca151c5c4d091575cfc41`. +The complete x86 `CRC32B/W/L/Q` family now follows Go 1.27's `ycrc32b` and +`ycrc32l` tables. B/W/L cover 386 and amd64; Q is amd64-only. Register, +ordinary-memory, symbol-memory, byte-alias, extended-register, and legal 386 +SP-destination forms are validated against the Go assembler. Runtime coverage +compares all four widths with an independent software CRC32C implementation, +checks dword-result zero extension, and proves flags are preserved. All five +x86 triples compile with LLVM 22 under `+crc32,+sse4.2`. The amd64 official +count is `5914/6/820`; report `_out/official-coverage-100/amd64-crc32.json` has +zero parse errors and fingerprint +`84f242de99b0e4c75cb9e44ba8c5a52e90211945b78bd833137831f0f2e42a3f`. +The complete x86 `CMPSB/W/L/Q` string-compare family now supports Go 1.27's +operand-free forms, with Q rejected on 386, plus the assembler's `REP` and +`REPN` prefixes. Its typed helper models forward/backward SI/DI movement, +remaining CX, early termination, zero-count flag preservation, and the full +CF/ZF/SF/OF/PF result of the final comparison. Runtime coverage exercises +equal/mismatching repetitions, both repeat conditions, DF reversal, every +width, and pointer/count results. All five x86 triples compile with LLVM 22. +The amd64 official count is `5918/6/816`; report +`_out/official-coverage-100/amd64-cmps.json` has zero parse errors and +fingerprint `c1633e1333335a4b32e64a6202406ca305493872c562a3ae35dd3b16aa9dcd5f`. +The complete `LODSB/W/L/Q` string-load family now supports Go 1.27's +operand-free forms, with Q rejected on 386, plus `REP`/`REPN` and DF reversal. +Its typed helper preserves AX on a zero-count repeat, applies B/W partial writes, +L zero extension, and Q full-width writes, and returns the exact final SI/CX. +Runtime coverage exercises every width, both repeat spellings, and forward and +backward traversal. All five x86 triples compile with LLVM 22. The amd64 +official count is `5922/6/812`; report +`_out/official-coverage-100/amd64-lods.json` has zero parse errors and +fingerprint `10f523dd946354e935486a05b09e4570300235cdac1273ed3f8caac0cea5c1a3`. +The complete sized-NOP family (`NOPW` and `NOPL`) now follows Go 1.27's sole +`ydivl(Yml)` row: exactly one general register or memory operand. Register, +SP, ordinary-memory, symbol-memory, extended-register, and 386 restrictions +are covered across all five x86 triples. Runtime coverage proves register and +flag preservation and that a memory-form NOP does not access its nominal +address. The amd64 official count is `5926/6/808`; report +`_out/official-coverage-100/amd64-sized-nop.json` has zero parse errors and +fingerprint `dcd94ba6d625e5e0074b582033bee69cbbb6c561b9e9f302557a36327eb09b31`. +The complete `MOVBEW/L/Q` endian-move family now implements both Go 1.27 +`ymovbe` rows: memory-to-register and register-to-memory. W/L cover 386 and +amd64; Q is amd64-only. Ordinary, symbol, and extended-register addressing is +validated across all five x86 triples under `+movbe`. Runtime coverage checks +both directions, W partial-register preservation, L zero extension, Q +full-width results, byte ordering, and flag preservation. Store forms do not +perform a spurious read of write-only destination memory. The amd64 official +count is `5932/6/802`; report `_out/official-coverage-100/amd64-movbe.json` has +zero parse errors and fingerprint +`cd91b597e226ebdb954200e523d8709fc830fbcbc099a101eeca035bbfc38d9f`. +The complete scalar non-temporal integer-store family now implements Go +1.27's shared `yrl_ml` row for `MOVNTIL/Q`: L is supported on 386 and amd64, +and Q is amd64-only. Ordinary, symbol, FP, extended-register, and five-platform +object forms carry LLVM `!nontemporal` metadata under `+sse2`; tests inspect +LLVM 22 backend assembly to prove the hint becomes `movnti`, and native/Rosetta +execution verifies L/Q values plus flag preservation. Go's Yml compatibility +closure also accepts a register destination even though Intel defines only a +memory destination; that exact Go-accepted form lowers to `ud2` and +`unreachable` instead of silently becoming a register move. The amd64 official +count is `5934/6/800`; report +`_out/official-coverage-100/amd64-movnti.json` has zero parse errors and +fingerprint +`14ce5adfb103edf3e6f9cee70dbd6908736825546e5e15c8aa52485001decbed`. +The complete implicit-accumulator sign-extension family now shares one +width-aware lowering: `CBW`/`CWDE`/`CDQE` extend into AX/EAX/RAX, while +`CWD`/`CDQ`/`CQO` produce the sign half in DX/EDX/RDX. All six use Go 1.27's +zero-operand `ynone` table; CDQE/CQO are rejected on 386. Five-platform tests +cover the complete form set, and native/Rosetta runtime coverage checks partial +16-bit writes, 32-bit zero-extension, 64-bit sign-extension, and flag +preservation. This also closes the old bug where the standalone CQO lowerer +accepted 386 input. The amd64 official count is `5939/6/795`; report +`_out/official-coverage-100/amd64-accumulator-sign-extend.json` has zero parse +errors and fingerprint +`a3d9831c51bb354d77c863ffa396914f3a49390d35b1e6fbfc58e2cb1f4819f3`. +The complete Go 1.27 x87 conditional-move family is now supported. This means +all eight base conditions `FCMOVB/BE/E/NB/NBE/NE/NU/U` plus the six Go aliases +`FCMOVCC/CS/EQ/HI/LS/UN`, not merely the opcodes observed in the official +corpus. Every instruction accepts the complete `Yrf,F0` row (F0-F7 source, +exact F0 destination) on 386 and amd64. Five-platform object tests cover the +full table and native/Rosetta semantics exercise true and false CF/ZF/PF +conditions without modifying the x87 stack shape. The amd64 official count is +`5947/6/787`; report +`_out/official-coverage-100/amd64-x87-conditional-move.json` has zero parse +errors and fingerprint +`13ba46c5edfbf9aed8e3249d3042b3e9e36079354de8438c3eb662a8cd1f0788`. +The complete `LEAW/LEAL/LEAQ` address-generation family now follows the sole +Go 1.27 `ym_rl` row with shared validation. W preserves the destination's upper +bits, L zero-extends the computed 32-bit address, and Q writes the full address; +none modify flags. Tests cover base/index/scale/displacement, symbols, SP, +extended registers, all five x86 triples, and native/Rosetta semantics. The +same mechanism rejects XMM destinations, 386 high address/destination +registers, and 386 LEAQ, closing permissive behavior in the old L/Q lowerer. +The amd64 official count is `5948/6/786`; report +`_out/official-coverage-100/amd64-lea.json` has zero parse errors and +fingerprint +`0f64b672587decc15f563008b9d5333bb2331443c8d948340a9f1e4a0df197e3`. +The complete scalar SSE reciprocal-estimate family now covers Go 1.27's +legacy `RCPSS/RSQRTSS` `Yxm,Yxr` table and VEX `VRCPSS/VRSQRTSS` +`Yxm,Yxr,Yxr` table. Register, ordinary memory, symbol, FP, absolute-memory, +extended-register, and all five x86 target forms are checked against the Go +assembler and compiled by LLVM 22. Keep the explicit 386 distinction: legacy +forms reject high X/address registers, while Go's VEX compatibility classes +accept X8-X15 and high address registers even in 32-bit mode. Native/Rosetta +execution verifies reciprocal estimates, legacy and VEX upper-lane selection, +and flag preservation. The amd64 official count is `5956/6/778`; report +`_out/official-coverage-100/amd64-scalar-reciprocal.json` has zero parse errors +and fingerprint +`e96c3568e631bf1daf8ab2dbd4fd407b8b72021821e3fe3d960524571fac1f5f`. +The complete mask-unpack family now supports `KUNPCKBW/WD/DQ` with Go +1.27's shared `K,K,K` table on 386 and amd64. Lowering follows the encoded +Plan 9 operand order: the first source supplies the low half and the second +source supplies the high half; source/destination aliases are safe because +both inputs are loaded before the destination write. Five-platform object +tests and native/Rosetta runtime coverage verify all three widths, aliasing, +and flag preservation. The amd64 official count is `5959/6/775`; report +`_out/official-coverage-100/amd64-mask-unpack.json` has zero parse errors and +fingerprint +`089446aeec9f6d77cb2666facb480651ed12c0b93d1de1fc7b98cfc0718257fe`. +The complete legacy packed integer logical family now covers all MMX/m64 and +XMM/m128 forms of `PAND/PANDN/POR/PXOR`. MMX is amd64-only according to the +Go 1.27 assembler's mode checks even though the opcodes share an `ymm` table; +386 retains only XMM forms and strictly rejects X8-X15 and high address +registers. Five-platform tests also reject suffixes and mixed register classes; +native/Rosetta execution checks every Boolean operation, MMX memory movement, +and flags. The amd64 official count is `5965/6/769`; report +`_out/official-coverage-100/amd64-legacy-packed-logical.json` has zero parse +errors and fingerprint +`8d5fd1e1e89f719f34f07c8d751882ba9f232bfbde496bad80460815403ab3b8`. +Go's explicit `PADDD` spelling now follows its `arch.go` alias mapping to +`APADDL`, including the complete `PADDL` MMX/m64 and XMM/m128 operand table. +The entire 17-spelling packed-add family is described by one typed grammar: +canonical aliases, Go `ymm`/`yxm`/`_yvandnpd` form class, lane width, +wrapping/saturation semantics, and D/Q broadcast capability. The shared +validator now enforces that MMX rows are amd64-only and that legacy X/address +registers stay within the 386 range. Five-platform object tests compare both +spellings, the grammar test locks every family member and property, and +native/Rosetta execution verifies per-dword wrapping, alias behavior, and flag +preservation. The amd64 official count is `5966/6/768`; report +`_out/official-coverage-100/amd64-paddd-alias.json` has zero parse errors and +fingerprint +`b01612c1a927e5004b622cae04ff83108937db34b4f6f5e8382cc95fc4d95524`. +The complete floating dot-product family (`DPPD`/`DPPS` and +`VDPPD`/`VDPPS`) is modeled by one typed grammar covering Go's `yxshuf`, +`_yvdppd`, and `_yvblendpd` tables. It records lane type, legacy/VEX operand +shape, X/Y width availability, and the Go 386 frontend's four-operand limit. +Lowering uses LLVM 22's matching SSE4.1/AVX intrinsics so immediate selection, +reduction rounding, and NaN behavior remain architectural. Five-platform +object tests cover all ten official forms; native/Rosetta execution verifies +the immediate masks, result lanes, and flag preservation. The amd64 official +count is `5976/6/758`; report +`_out/official-coverage-100/amd64-floating-dot.json` has zero parse errors and +fingerprint +`dd311e9865a6cb6745e14f9dfbdcd062fe8bee8539da8da8dd919170694ec0db`. +The byte sum-of-absolute-differences area now has one typed grammar for +`PSADBW`/`VPSADBW` and `MPSADBW`/`VMPSADBW`. It distinguishes fixed eight-byte +block sums from immediate-selected sliding four-byte sums, and records the +legacy X, VEX X/Y, and EVEX X/Y/Z form surfaces. Go's 386 frontend rejection +of four-operand VMPSADBW is explicit. LLVM 22 SSE4.1/AVX2 intrinsics preserve +the immediate-dependent window semantics; five-platform object tests and +native/Rosetta execution cover all six newly supported official forms, Yu8 +boundaries, flags, and output lanes. All 17 official SAD forms are supported. +The amd64 official count is `5982/6/752`; report +`_out/official-coverage-100/amd64-packed-sad.json` has zero parse errors and +fingerprint +`9e7df85e18206eb062f414ec5387ff101dfb976930951aa9263c5a506aff123b`. +The complete half-vector move family now shares one typed grammar across +`MOVHPS`/`MOVLPS`/`MOVHPD`/`MOVLPD` and their V-prefixed spellings. It records +the selected 64-bit lane and separates legacy register aliases from Go's +strict `_yvmovhpd` memory-store and `memory, X, X` load rows. EVEX X0-X31 and +the narrower 386 surface are covered by Go-oracle tests. Five-platform LLVM 22 +object compilation covers every load/store direction, while native/Rosetta +execution verifies high/low lane preservation and flags. All 31 official +forms are supported. The amd64 official count is `6005/6/729`; report +`_out/official-coverage-100/amd64-move-half.json` has zero parse errors and +fingerprint +`c9f1dfeb3add36e39854bb77855d054e47dfa722561f927994c812c27e13faaa`. +The complete unaligned-load family (`LDDQU`/`VLDDQU`) is described by one +load-only schema: legacy X/m128 and VEX X/m128 plus Y/m256. Tests preserve the +Go 1.27 frontend's exact 386 distinction: legacy X8/R9 forms are rejected, +while the VEX table accepts `VLDDQU 4(R9), Y8`; the latter is translated and +compiled for both i386 LLVM 22 targets rather than skipped. Five-platform +object tests and native/Rosetta unaligned execution cover all three official +forms and flag preservation. The amd64 official count is `6008/6/726`; report +`_out/official-coverage-100/amd64-lddqu.json` has zero parse errors and +fingerprint +`4d09674ad3b890b2244b643d4f6d72aa3f2e23f0f74e7f56db0933b5d01d62e6`. +The complete K-register broadcast family (`VPBROADCASTMB2Q` and +`VPBROADCASTMW2D`) shares one typed schema recording K source width and output +lane width. Lowering truncates the K value to its low byte/word, zero-extends +it to qword/dword, and broadcasts across X/Y/Z. Go-oracle tests cover K0-K7, +EVEX register ranges, suffix/operand rejection, and all five x86 targets; +native/Rosetta execution verifies exact zero extension, lane replication, and +flags. All six official forms are supported. The amd64 official count is +`6014/6/720`; report +`_out/official-coverage-100/amd64-mask-broadcast.json` has zero parse errors +and fingerprint +`2067f51d635ace0365584e75a3493fa78ac25eb138e7b928462d7ba03c165fa5`. +The complete vector flags-test family now shares one typed grammar across +legacy `PTEST` and VEX `VPTEST`/`VTESTPD`/`VTESTPS`. It models Go 1.27's +`yxm_q4` and `_yvptest` rows, including X/m128 and Y/m256 register-or-memory +forms, legacy versus VEX register limits, and the Go 386 frontend's acceptance +of X/Y8-X15 plus extended VEX address registers. Lowering computes both ZF and +CF with Plan 9 operand order, distinguishes all-bit integer tests from PS/PD +per-lane sign-bit tests, and clears SF/PF/OF. LLVM 22 aborts on some otherwise +valid 256-bit vector bitcasts for i386, so the implementation reduces bytes +directly; both i386 targets are compiled rather than skipped. Five-platform +Go-oracle/object tests and native/Rosetta semantics cover all seven official +grammar rows. All eleven previously unsupported normalized forms are now +supported. The amd64 official count is `6025/6/709`; report +`_out/official-coverage-100/amd64-vector-test.json` has zero parse errors and +fingerprint +`ac0802710ceaca45bf63f2ebe63f7fcff7452bba49fd14f94536b68c42d93305`. +The complete packed conflict-detection family (`VPCONFLICTD/Q`) shares one +typed `_yvexpandpd` grammar for D/Q lane widths. It covers X/Y/Z register and +memory sources, scalar-memory broadcast, K1-K7 merge masking, and `.Z`, while +preserving Go 386's X/Y0-X/Y31 and extended-address acceptance plus its Z0-Z7 +limit. Lowering builds each result lane as the bit mask of equal source lanes +with lower indices; destination aliases are safe because all source lanes are +loaded first. Five-platform Go-oracle/LLVM 22 object tests cover all six table +rows per opcode, and native/Rosetta execution verifies ordinary, broadcast, +merge, zero-mask, D/Q, alias, and flag-preservation semantics. All 15 +previously unsupported normalized forms (76 corpus hits) are now supported. +The amd64 official count is `6040/6/694`; report +`_out/official-coverage-100/amd64-packed-conflict.json` has zero parse errors +and fingerprint +`ec5fc71a54a6d142439970d12b650863f61a997ed98405b108bb4020c6dc7cfc`. +The complete packed expand family (`VEXPANDPD/PS` and +`VPEXPANDB/W/D/Q`) now uses one typed `_yvexpandpd` grammar. It covers all +36 Go encoder rows: X/Y/Z register and memory sources plus K1-K7 merge and +`.Z` forms, including Go 386's broad X/Y register surface and Z0-Z7 limit. +Masked memory lowering uses `llvm.masked.expandload`, so disabled lanes do not +read past the compact source array; register lowering computes each compact +source index from the lower mask bits and remains safe when source and +destination alias. Five-platform Go-oracle/LLVM 22 object tests and +native/Rosetta semantics cover B/W/D/Q, PS/PD bit patterns, merge, zeroing, +aliasing, flag preservation, and a zero-mask null source. All 49 previously +unsupported normalized forms are now supported. The amd64 official count is +`6089/6/645`; report +`_out/official-coverage-100/amd64-packed-expand.json` has zero parse errors and +fingerprint +`5f3b67bd1403a34bb4dd9018142414a0ec009872a0f3d38c5cd083d1d2efd496`. +The packed bit-count area now uses one typed grammar across existing +`VPOPCNTB/W/D/Q` and the complete `VPLZCNTD/Q` family. The grammar records +population versus leading-zero semantics, lane width, and scalar-broadcast +availability while sharing the full `_yvexpandpd` X/Y/Z, memory, K1-K7 merge, +and `.Z` validation. Leading-zero count returns the element width for zero, +preserves flags, and covers D/Q broadcast. Five-platform Go-oracle/LLVM 22 +object tests and native/Rosetta semantics cover every row while retaining the +older popcount regressions. All 14 previously unsupported normalized LZCNT +forms are now supported. The amd64 official count is `6103/6/631`; report +`_out/official-coverage-100/amd64-packed-lzcnt.json` has zero parse errors and +fingerprint +`0af808d292d71086075d83685798563de3752f93e16dc0352e97c57f22a68533`. +The shared mask-blend grammar now covers floating `VBLENDMPS/PD` together +with existing integer `VPBLENDMB/W/D/Q`. It records lane width and broadcast +availability explicitly instead of inferring capability from width, and +implements every `_yvblendmpd` X/Y/Z register/memory, K1-K7, `.Z`, and legal +scalar-broadcast form. Five-platform Go positive/negative oracles and LLVM 22 +objects retain Go 386's three-operand frontend limit; native/Rosetta runtime +coverage checks PS/PD bit patterns, broadcast, merge/zero selection, and flag +preservation. All 18 previously unsupported normalized floating mask-blend +forms are now supported. The amd64 official count is `6121/6/613`; report +`_out/official-coverage-100/amd64-mask-blend.json` has zero parse errors and +fingerprint +`8f1f803fba1f21767a1811f84da3d34ed1111a7183135304565b11df1a2a2c88`. +The complete GFNI family now shares one typed grammar across `VGF2P8MULB`, +`VGF2P8AFFINEQB`, and `VGF2P8AFFINEINVQB`. It covers all eight Go encoder +rows for each instruction: X/Y/Z register or memory first sources, K1-K7 merge +and `.Z`, plus legal qword matrix broadcast on the two affine operations. The +386 frontend can express the multiply family's unmasked three-operand rows but +cannot express either affine instruction's four-operand minimum; tests verify +that distinction with the Go 1.27 assembler rather than silently skipping it. +Target-independent GF(2^8) IR implements multiplication modulo `0x11b`, +multiplicative inverse, and the affine matrix transform, so runtime semantics +do not depend on host GFNI support. Five-platform Go-oracle/LLVM 22 object +tests and native/Rosetta semantics cover immediate handling, register/memory +sources, broadcast, merge/zero masking, aliasing, and flag preservation. This +also replaces the old `VGF2P8AFFINEQB` placeholder that merely copied its data +source. All 26 previously unsupported normalized GFNI forms are now supported. +The amd64 official count is `6147/6/587`; report +`_out/official-coverage-100/amd64-gfni.json` has zero parse errors and +fingerprint +`99312244b4ccbadefe2e8d1a8f97b8d8402096e807b1fdcf871c52ab761b120f`. +The indexed-permute area now uses one typed grammar for single-table +`VPERMB/W`, insert-index `VPERMI2{B,W,D,Q,PS,PD}`, and table-index +`VPERMT2{B,W,D,Q,PS,PD}`. Its spec records lane width, semantic mode, and +broadcast availability; one validator covers all X/Y/Z, register/memory, +K1-K7 merge, `.Z`, legal scalar-broadcast, and Go 386 frontend forms. The +shared emitters explicitly model each instruction's table/index sources: +single-table forms take indices from the second Plan 9 source, I2 takes them +from the old destination, and T2 takes them from the second source while using +the old destination as table zero. This replaces the old Z-only `VPERMB` and +`VPERMI2B` copy placeholders. Five-platform Go-oracle/LLVM 22 tests and +native/Rosetta semantics cover B/W/D/Q selection, both two-table directions, +broadcast, mask merge/zero, destination-as-input behavior, and flag +preservation. All 61 previously unsupported normalized forms are now +supported. The amd64 official count is `6208/6/526`; report +`_out/official-coverage-100/amd64-indexed-permute.json` has zero parse errors +and fingerprint +`5b6e5d5435c4335a2d7e3d5b5a967a5827ad8bfacdf3f3f3bdf4db80c6ce458a`. +The qword bit-lookup grammar now groups `VPMULTISHIFTQB` and +`VPSHUFBITQMB`. Both interpret each byte control's low six bits inside the +corresponding qword data lane; the typed output mode selects either the low +eight rotated bits for a vector result or the low bit packed into a K mask. +The shared validator covers X/Y/Z, register/memory sources, K1-K7 byte-mask +merge/zero, legal qword broadcast for multishift, the mask instruction's +always-zero writemask semantics, K0-K7 destinations, and Go 386's operand +limit. The target-independent rotate/lookup IR avoids depending on host +AVX-512 VBMI/BITALG support. Five-platform Go-oracle/LLVM 22 tests and +native/Rosetta semantics cover rotation wraparound including counts zero and +63, per-qword isolation, broadcast, vector merge/zero, packed mask bit order, +mask zeroing, and flag preservation. All 17 previously unsupported normalized +forms are now supported. The amd64 official count is `6225/6/509`; report +`_out/official-coverage-100/amd64-qword-bit-lookup.json` has zero parse errors +and fingerprint +`1f43d40e10487b31bc2df38c3716df8f4a07d5c16bf64d98d78a8e1cb6b549f7`. +The floating range grammar now covers `VRANGEPS/PD/SS/SD` through a four-entry +typed spec recording lane width and packed/scalar shape. The immediate remains +orthogonal data: its comparison field selects min, max, min-absolute, or +max-absolute, while its sign field selects source-one, comparison-result, +clear, or set. Shared target-independent IR preserves NaN payload selection, +quiets signaling NaNs, and handles opposite-signed zero and equal-magnitude +opposite-sign ties before applying writemasks. Go 1.27 accepts the complete +X/Y/Z register/memory, broadcast, K1-K7 merge/zero, and legal SAE forms on +amd64; its 386 frontend rejects even the unmasked four-operand form, which the +negative oracle records explicitly instead of skipping. Three amd64 target +objects and native/Rosetta f32/f64 packed/scalar semantics cover all 16 +immediate modes, masks, broadcast, upper-lane preservation, NaNs, flags, and +signed-zero cases. All 20 previously unsupported normalized forms are now +supported. The amd64 official count is `6245/6/489`; report +`_out/official-coverage-100/amd64-range.json` has zero parse errors and +fingerprint +`f6ea117b66042829c48c2b114e342daaf7de3125e68d82d1e37c64986db13cad`. +The explicit vector mask-move grammar now groups floating `VMASKMOVPS/PD` +with integer `VPMASKMOVD/Q`; a four-entry typed spec records only the 32- or +64-bit lane width because all four opcodes share `_yvmaskmovpd`. One validator +covers X/Y loads and stores, matching mask/data widths, all five x86 target +triples, and Go's accepted X0-X15/Y0-Y15 VEX register range even in 386 mode. +Lowering derives predicates from each mask lane's sign bit and uses LLVM 22 +masked load/store intrinsics, preserving zeroed load lanes, untouched store +lanes, and fault suppression instead of eagerly touching masked-off memory. +Native/Rosetta runtime tests cover all four spellings, both lane widths, load, +store, mixed masks, and flag preservation. All 16 previously unsupported +normalized forms are now supported. The amd64 official count is +`6261/6/473`; report +`_out/official-coverage-100/amd64-explicit-mask-move.json` has zero parse +errors and fingerprint +`1bb538ecbc3cb8681c9a6f328c17bd7a6d957542e288648515d98855b87e7bce`. +The FPCLASS grammar now covers all eight Go width-specialized opcode names: +`VFPCLASSPD{X,Y,Z}`, `VFPCLASSPS{X,Y,Z}`, `VFPCLASSSD`, and `VFPCLASSSS`. +Its typed spec records lane width, exact vector width, and scalar shape; one +validator covers unsigned-byte immediates, register/full-memory/broadcast +sources, optional K1-K7 input masks, and K0-K7 results. Go 386 accepts X/Y +EVEX sources through register 31 but Z sources only through 7, while its +four-operand input-mask form is source-inexpressible; positive and negative +Go-oracle tests preserve those boundaries. Integer-bit classification covers +qNaN, both zeros, both infinities, denormal, negative finite, and sNaN without +raising host floating exceptions. It reads MXCSR dynamically so DAZ correctly +reclassifies denormals as signed zero. Five-target LLVM 22 objects and +native/Rosetta runtime tests cover every class bit, packed/scalar widths, +broadcast, input-mask zeroing, DAZ on/off, and flag preservation. All 23 +previously unsupported normalized forms are now supported. The amd64 official +count is `6284/6/450`; report +`_out/official-coverage-100/amd64-fpclass.json` has zero parse errors and +fingerprint +`e704c30b111e01cb96f7c78b7c8dfb68fe446059284c2954b9883932d34889b3`. +The GETEXP grammar now groups `VGETEXPPS/PD/SS/SD` with typed lane width and +packed/scalar shape. One validator covers X/Y/Z register/full-memory sources, +scalar-memory broadcast, legal Z/scalar SAE, K1-K7 merge and `.Z`, scalar +pass-through lanes, and the exact Go 386 X/Y/Z and operand-count boundaries. +The shared integer-bit emitter extracts unbiased normal exponents, normalizes +denormals with `ctlz`, converts the signed exponent back to the source floating +type, returns `-Inf` for zero, `+Inf` for either infinity, and quiets NaNs while +preserving payload/sign. A shared MXCSR reader makes DAZ turn denormals into +zero at runtime. Five-target LLVM 22 object tests and native/Rosetta semantics +cover f32/f64 normal and subnormal boundaries, signed values, zeros, +infinities, qNaN/sNaN, DAZ on/off, broadcast, merge/zero masks, scalar upper +lanes, and flags. All 21 previously unsupported normalized forms are now +supported. The amd64 official count is `6305/6/429`; report +`_out/official-coverage-100/amd64-getexp.json` has zero parse errors and +fingerprint +`b4f80d2350a281a2c77a9f52ed29e8f08c2c6c9bcb8d9c25c282d264a361073e`. +The GETMANT grammar now groups `VGETMANTPS/PD/SS/SD` with typed lane width +and packed/scalar shape. One validator covers the complete Go 1.27 optabs: +X/Y/Z register and full-memory sources, scalar-memory broadcast, legal Z or +scalar SAE, K1-K7 merge and `.Z`, scalar pass-through lanes, unsigned-byte +immediates, and the exact 386 register and three-operand frontend boundaries. +The integer-bit emitter implements all four normalization intervals and four +sign-control encodings, normalizes denormals with `ctlz`, reads MXCSR.DAZ, +quiets NaNs while preserving payload/sign, and handles signed zero, infinity, +and negative finite indefinite results without host floating operations. Five +x86 target object tests and native/Rosetta semantics cover all 16 effective +immediate encodings, f32/f64 normal and denormal values, zeros, infinities, +qNaN/sNaN, DAZ on/off, broadcast, merge/zero masks, scalar upper lanes, and +flags. All 21 previously unsupported normalized forms are now supported. The +amd64 official count is `6326/6/408`; report +`_out/official-coverage-100/amd64-getmant.json` has zero parse errors and +fingerprint +`51b42533d23a53d02f0303e5443d583e23b305ce30988dbb03b82d1298172055`. +The shared unary-immediate floating grammar now models Go's `_yvgetmantpd` +and `_yvfixupimmsd` shapes once for GETMANT, VREDUCE, and VRNDSCALE. A typed +shape records only lane width and packed/scalar form; the common parser owns +unsigned-byte immediates, X/Y/Z and memory widths, BCST, legal Z/scalar SAE, +K1-K7 merge/zeroing, scalar pass-through, and 386 frontend constraints. +VREDUCE and VRNDSCALE add a semantic mode to that shape rather than duplicating +operand combinations. Their integer-bit rounding engine covers all 16 scale +values, all four immediate rounding modes, dynamic MXCSR.RC selection, DAZ, +ties-to-even, directed rounding, signed zero, infinities, and quieted NaNs; +VREDUCE computes the exact residual and applies Intel's result-zero sign rule. +Five x86 target object tests and native/Rosetta semantics cover the complete +Go optabs, 64 scale/rounding combinations per precision, dynamic RC, DAZ, +packed masks, zeroing, broadcast, scalar upper lanes, and flags. All 44 +previously unsupported normalized forms are now supported. The amd64 official +count is `6370/6/364`; report +`_out/official-coverage-100/amd64-scaled-round.json` has zero parse errors and +fingerprint +`72111c7f5ce20b3083f8b0cf814e5183cf36bdab590b8cc0c2414d40cbb103de`. +The typed binary-floating grammar now also models the complete +`VSCALEFPS/PD/SS/SD` family with `mode=scale`; the four opcode entries reuse +one parser for X/Y/Z and scalar shapes, full-memory and scalar-broadcast +sources, K1-K7 merge/zeroing, legal Z/scalar embedded rounding, and the exact +386 register/operand-count limits. A target-independent integer-bit emitter +implements `SRC1 * 2^floor(SRC2)` without requiring AVX-512 hardware or +libm calls. It handles dynamic MXCSR.RC and explicit RN/RD/RU/RZ, DAZ and FTZ, +normal/subnormal normalization, exact and inexact underflow, directed +overflow, signed zero, and Intel's qNaN/sNaN/infinity special-case table. +Five-target LLVM 22 object tests and native/Rosetta semantics cover the full +Go optabs, rounding modes, DAZ, packed masks, zeroing, broadcast, scalar upper +lanes, and flags. All 22 previously unsupported normalized forms are now +supported. The amd64 official count is `6392/6/342`; report +`_out/official-coverage-100/amd64-scalef.json` has zero parse errors and +fingerprint +`0c0c9fd335e7908270c8ed9230f9b30de91f5013b2a3e36eb963bf72636af947`. +The typed packed numeric-conversion grammar now covers 26 EVEX opcodes by +declaring source/destination kind (floating, signed, or unsigned), element +width, truncation/explicit-rounding mode, and physical width/lane shapes. One +parser combines those semantic axes with X/Y/Z register or memory sources, +scalar broadcast, K1-K7 merge/zeroing, legal maximum-width embedded +rounding/SAE, and 386 register limits. Do not expand this family into separate +per-mnemonic/per-width lowerers. Integer-to-floating conversion constructs +IEEE-754 bits directly and reads MXCSR.RC for dynamic rounding: LLVM 22 ignores +fixed rounding metadata when lowering constrained integer-to-floating +intrinsics, so restoring those intrinsics silently breaks RD/RU/RZ SAE forms. +Five-target LLVM 22 object tests and native/Rosetta semantics cover all four +dynamic and fixed rounding modes, signed/unsigned boundaries, invalid +floating-to-integer results, truncate/round conversion, broadcast, masks, +zeroing, narrow-result padding, and flags. All 146 previously unsupported +normalized forms are now supported. The amd64 official count is +`6538/6/196`; report +`_out/official-coverage-100/amd64-packed-numeric-conversion.json` has zero +parse errors and fingerprint +`4e7e215deb80f5a805109524aad8c5081952cc0b7852d8e357ad9290bd12c6c2`. +The typed byte-SAD grammar now also includes the complete `VDBPSADBW` family. +Its EVEX form reuses the existing SAD family dispatch while one validator owns +X/Y/Z source/destination widths, register/full-memory SRC2, optional K1-K7 +merge masking, `.Z`, and imm8. Go 1.27's 386 frontend cannot represent its +four- or five-operand forms, which is an explicit negative oracle rather than +an unsupported-form skip. The target-independent integer emitter follows the +Intel lane grammar: imm8 selects four dwords independently inside each +128-bit SRC2 lane, then every 64-bit block produces four word-sized sliding +SAD results against two stationary SRC1 dwords. Three amd64 target object tests +and native/Rosetta semantics cover all widths, register/memory sources, +unmasked/merge/zero forms, cross-lane control isolation, and flags. All 8 +previously unsupported normalized forms are now supported. The amd64 official +count is `6546/6/188`; report +`_out/official-coverage-100/amd64-vdbpsadbw.json` has zero parse errors and +fingerprint +`992bb926d206bf2c5cc5392e8fdba13c73d0552fa841b1187aee62dd1f2b8ca1`. +The typed unary-immediate floating grammar now has a `twoSource` axis and +covers the complete `VFIXUPIMMPS/PD/SS/SD` family without duplicating X/Y/Z, +memory/broadcast, SAE, K1-K7 merge/zero, scalar pass-through, or 386 frontend +validation. Go 1.27 rejects every 386 FIXUPIMM spelling because the frontend +cannot represent its four- and five-operand forms; keep the explicit negative +oracle. A target-independent integer emitter classifies qNaN, sNaN, zero, +positive one, both infinities, and negative/positive finite inputs after +MXCSR.DAZ, selects the corresponding nibble from each table lane, and +implements all 16 response encodings. The immediate controls floating exception +reporting only; the current software lowering does not expose that exception +state. Three amd64 target object tests and native/Rosetta semantics cover all +response encodings, token classes, DAZ states, response-0 destination +preservation, packed masks/zeroing, and scalar upper-lane copying from SRC1. +All 21 previously unsupported normalized forms are now supported. The amd64 +official count is `6567/6/167`; report +`_out/official-coverage-100/amd64-fixupimm.json` has zero parse errors and +fingerprint +`32efbc7afdeea181b47744676421529bdec8a3bc41464a1b8ce7b14e2fb5f0ee`. +The typed approximate-math grammar now covers the complete AVX512ER +`VEXP2PS/PD`, `VRCP28PS/PD/SS/SD`, and `VRSQRT28PS/PD/SS/SD` family. Its +declarative axes are operation, 32/64-bit lane, and packed/scalar shape; one +parser derives the Z-only packed or X scalar width, register/full-memory +source, scalar-memory broadcast, SAE, K1-K7 merge/zero, and 386 operand-count +rules. LLVM 22 removed the `avx512er` feature flag and target intrinsics, but +its integrated x86 assembler still emits the architectural instructions. The +emitter therefore uses exact side-effecting inline assembly under `+avx512f`, +including a clobbered temporary k1 for true writemasking, instead of silently +substituting exact division, square root, or a library exp2 call for the +specified approximation. Go 1.27 syntax oracles and LLVM 22 object compilation +cover Darwin/Linux/Windows amd64 and Linux/Windows 386; 386 supports masked +packed forms but its frontend rejects the four-operand masked scalar forms. +All 25 previously unsupported normalized forms are now supported. The amd64 +official count is `6592/6/142`; report +`_out/official-coverage-100/amd64-approximate-math.json` has zero parse errors +and fingerprint +`6eb7debae01aa295696454b5b813897b4b1dc46c077986714e8a00a7442ac8b1`. +The typed SSE4.2 packed-string grammar replaces the old +`PCMPESTRI $0x0c, memory, X` special case and covers all eight +`PCMP{E,I}STR{I,M}` and `VPCMP{E,I}STR{I,M}` opcodes. Three axes select +explicit/implicit lengths, index/mask result, and legacy/VEX encoding while +one validator owns X/m128 operands and the immediate domain. The immediate +domain is intentionally encoding-dependent: legacy `yxshuf` accepts `0..255`, +while VEX `_yvaeskeygenassist` also accepts `-128..-1`. LLVM 22's SSE4.2 +intrinsics produce the architectural index or mask plus CF/ZF/SF/OF; the +lowerer stores SF xor OF in plan9asm's signed-less flag slot and clears PF. +Five-target object compilation and native/Rosetta execution against C SSE4.2 +intrinsics cover explicit and implicit lengths, index and mask outputs, all +modeled flags, memory/register sources, and immediate boundaries. All 16 +previously unsupported normalized forms are now supported. The amd64 official +count is `6608/6/126`; report +`_out/official-coverage-100/amd64-packed-string-compare.json` has zero parse +errors and fingerprint +`5e9710e4b0cc862dc98f4d0e9ff5dff412a128c7c39e9bdb009e292d968030af`. +The typed x86 stack-width grammar covers `PUSH`/`POP` for W/L/Q and +`PUSHF`/`POPF` for W/L/Q. Its table separates width from value/flags and +push/pop mode; one validator owns register, memory, immediate, arity, and +386-versus-amd64 availability. This replaces the duplicated PUSHL/POPL, +PUSHFL/POPFL, PUSHQ/POPQ, and PUSHFQ/POPFQ switches, adds the shared W forms +and POPQ memory destinations, and rejects the old false positives for vector +register destinations and cross-architecture L/Q spellings. Five-target Go +syntax-oracle and LLVM 22 object tests plus native/Rosetta value-and-flags +execution cover the family. All six previously unsupported normalized forms +are now supported. The amd64 official count is `6614/6/120`; report +`_out/official-coverage-100/amd64-stack-width.json` has zero parse errors and +fingerprint +`f342d7a180af3aa247551de0f06fb37c39782b122310fd11a61cbe0e01ab7bc9`. +The typed four-source grammar covers the complete AVX512_4FMAPS +`V4FMADDPS/SS` and `V4FNMADDPS/SS` family together with AVX512_4VNNIW +`VP4DPWSSD/VP4DPWSSDS`. Its axes distinguish floating versus signed-word dot +product, packed versus scalar, positive versus negative FMA, and wrapping +versus stepwise signed-saturating accumulation. One parser owns the mandatory +16-byte memory operand, consecutive four-register range, optional K1-K7 +merge/zero mask, and the 386 four-operand frontend limit. Preserve the +architectural source-block rule: the encoded first register's low two bits are +ignored, so a Go-accepted spelling such as `[Z10-Z13]` reads Z8-Z11. Masked +loads also preserve the ISA's whole-m128 fault suppression when every relevant +mask bit is zero. Five-target Go syntax-oracle and LLVM 22 object tests plus +native/Rosetta execution cover sequential FMA, mask behavior, scalar upper +lanes, source-block alignment, wrapping/saturating dot products, and null +memory with a zero mask. All 11 previously unsupported normalized forms are +now supported. The amd64 official count is `6625/6/109`; report +`_out/official-coverage-100/amd64-four-source.json` has zero parse errors and +fingerprint +`4b4cb483f7534cf194151d597a269e76f1dae01c770381a8ce5a6ef817ee7bfe`. +The typed packed scalar-extract grammar now covers all ten legacy/vector +`EXTRACTPS`/`VEXTRACTPS` and `PEXTRB/W/D/Q`/`VPEXTRB/W/D/Q` opcodes in one +table. The spec records result width, legacy versus VEX/EVEX immediate domain, +and the legacy encoded-MMX destination quirk; shared validation owns source and +destination register classes for both 386 and amd64. In particular, legacy +`EXTRACTPS` accepts only immediates 0..3, while VEX forms have their wider +signed/unsigned imm8 rows. Preserve the Go 1.27 compatibility distinction that +386 rejects legacy `PEXTRQ` but accepts `VPEXTRQ`. Five-target object tests, +Go positive/negative syntax oracles, and native/Rosetta bit-exact execution +cover register and memory extraction. Both previously unsupported normalized +`EXTRACTPS` forms are now supported. The amd64 official count is +`6627/6/107`; report +`_out/official-coverage-100/amd64-scalar-extract.json` has zero parse errors +and fingerprint +`deedd039f714165e8171c7278f757035ecbd2c85e69a25c1292570598baf0002`. +The typed segment-query grammar now covers the complete `LARW/L/Q`, +`LSLW/L/Q`, and `VERR/VERW` family. Its axes select access-rights, +segment-limit, readable, or writable validation plus the optional 16/32/64-bit +destination width; one parser owns the shared Yml selector (GP register or +16-bit memory) and optional Yrl destination classes. The exact inline assembly +lowering ties the old LAR/LSL destination to the result because Intel leaves it +unchanged when descriptor validation fails, captures ZF with `SETE`, and +preserves every other modeled flag for all four query kinds. Go 1.27 positive/negative syntax oracles +and LLVM 22 object compilation cover Darwin/Linux/Windows amd64 and +Linux/Windows 386, including 386 SP destinations and Q-width rejection. The +native-amd64 runtime test covers LAR/LSL/VERR success through the current CS +selector, VERW rejection of CS, null-selector failure, and non-ZF flag +preservation; Rosetta raises SIGILL for these instructions and is not treated +as semantic execution. All 16 previously unsupported normalized forms are now +supported. The amd64 official count is `6643/6/91`; report +`_out/official-coverage-100/amd64-segment-validation.json` has zero parse +errors and fingerprint +`7538145e64c36a897b45b3258af91d55c0882cf3f790792e48b67c7f9164fb0e`. +The typed far-pointer grammar covers every Go 1.27 `LFSW/L/Q`, `LGSW/L/Q`, +and `LSSW/L/Q` form through segment and offset-width axes. One parser enforces +the shared far-pointer-memory to Yrl shape, 4/6/10-byte memory widths, 386 +register bounds, and Q-width availability. Exact side-effecting inline +assembly preserves descriptor checks and segment-register state, and LLVM 22 +object compilation covers all five x86 targets. The stack-width family shares +typed segment-selector load/store helpers with ordinary MOVW segment moves. +Its complete Go `ymovtab` grammar is expressed as width, push/pop direction, +allowed-segment set, and fixed-versus-native stack width: W push accepts +CS/SS/DS/ES/FS/GS, W pop accepts all except CS, L has the same sets with native +stack width, and Q accepts FS/GS in both directions with native stack width. +Go accepts these movtab compatibility rows in both 386 and amd64 modes; do not +reapply the ordinary-register L/Q mode restriction to them. These +state-changing segment loads are compile-tested rather than executed in-process +because changing FS/GS/SS can corrupt TLS or the active stack. All 11 +previously unsupported normalized forms are now supported. The historical +amd64 checkpoint was `6654/6/80`; report +`_out/official-coverage-100/amd64-segment-state.json` has zero parse errors and +fingerprint +`bbf5c66c5a7c84fe53887c109534ffd9d684d1cbe48307ddafb0aabcaf2890e5`. +The complete 16-opcode FXSAVE/XSAVE/XRSTOR extended-state family is expressed +as one typed grammar over family, save/restore direction, 64-bit encoding, and +implicit EDX:EAX mask use. One parser enforces Go's single `Ym` operand and the +amd64-only `*64` restriction; one exact inline-assembly emitter covers all +variants with explicit LLVM 22 `fxsr`, `xsave`, `xsaveopt`, `xsavec`, and +`xsaves` features. Positive and negative Go 1.27 oracles, all five x86 object +targets, supported-op extraction, and safe FXSAVE/FXRSTOR runtime semantics are +covered. The amd64 official count is `6670/6/64`; report +`_out/official-coverage-100/amd64-xstate.json` has zero parse errors and +fingerprint +`5852adef83b8bc6719e6926dde97c6482135e7c7db3b289a5356b188df40405d`. +The complete eight-opcode FSGSBASE family is one typed grammar over segment, +read/write direction, and L/Q width. Go 1.27 accepts all L forms on both 386 +and amd64 even though Intel defines the instruction only in 64-bit mode and +LLVM 22 consequently rejects its mnemonic for i386. The 386 lowering therefore +emits Go's exact F3 0F AE EAX encodings with fixed-register constraints; they +are object-compiled but intentionally not executed. Q forms remain amd64-only, +and FS/GS writes are not runtime-tested because they can corrupt process TLS. +All five x86 object targets, positive and negative Go oracles, target-feature +inference, and supported-op extraction pass. The amd64 official count is +`6678/6/56`; report `_out/official-coverage-100/amd64-segment-base.json` has +zero parse errors and fingerprint +`d74cffcc8dda444400f40c5cfd0240f34f169fb4f337fff6147d4cb8029f12a2`. +The VSIB-prefetch grammar now covers all eight gather-prefetch and all eight +scatter-prefetch opcodes through typed direction, PF0/PF1 hint, element width, +index-element width, and Go operand-vector width. One validator enforces K1-K7, +the Y-index DPD row, the Z-index remaining rows, VSIB addressing, scale, and +386 register limits; the hints intentionally have no observable IR effect. +Positive and negative Go 1.27 oracles plus LLVM 22 object compilation cover all +five x86 targets. The eight new scatter opcodes remove 12 normalized forms. +The amd64 official count is `6690/6/44`; report +`_out/official-coverage-100/amd64-vsib-prefetch.json` has zero parse errors and +fingerprint +`c21dd668b34f16f93c39ab53fc71b7a8c6750bca348f05098b993d43fec039e3`. +The legacy MMX/SSE grammar now covers signed-imm8 `PSHUFW` register/memory +rows, every `MOVQOZX` MMX/XMM/memory source row, `MOVDQ2Q`, and the `MOVNTQ` / +`MOVNTDQ` non-temporal stores. Typed operand-class specs share validation and +the non-temporal vector mechanism now emits LLVM metadata with a guaranteed +module metadata node. Five-target Go/LLVM form tests and an amd64 runtime +fixture verify word-lane order, low-qword transfer, XMM high-qword zeroing, and +both store widths. All six previously unsupported normalized forms are now +supported. The amd64 official count is `6696/6/38`; report +`_out/official-coverage-100/amd64-legacy-mmx.json` has zero parse errors and +fingerprint +`4bcde880d720cb16aef3e1cea9f8df0be09fc455f7fbfaafe7362d2de1f1e40c`. +The typed system-address grammar covers `INVLPG`, `INVPCID`, and `CLDEMOTE`, +including Go's GP-register compatibility closures for the first two. Invalid +ModRM register encodings become explicit `UD2` traps. Go also accepts memory +`INVPCID` on 386 despite the instruction being 64-bit-mode-only, so that path +emits Go's exact bytes with fixed EAX/EBX value/address constraints and is +object-compiled rather than executed. All five x86 targets, feature inference, +positive/negative Go oracles, and supported-op extraction pass. The amd64 +official count is `6699/6/35`; report +`_out/official-coverage-100/amd64-system-address.json` has zero parse errors and +fingerprint +`85f2e060cf40b556571bd9438c8173d83d563cb169c228b64e978b89f77c0973`. +The typed implicit-system grammar covers `MONITOR`, `MWAIT`, `RDPMC`, +`RDPKRU`, `WRPKRU`, `XSETBV`, `UMONITOR`, `UMWAIT`, and `TPAUSE` as one +explicit-operand shape plus typed AX/CX/DX input/output sets. Register liveness +and emission consume the same specification, read instructions write their +architectural AX/DX results back, and `UMWAIT`/`TPAUSE` preserve CF through an +inline `SETC`. Go positive/negative oracles and LLVM 22 object compilation pass +on all five x86 targets. The amd64 official count is `6708/6/26`; report +`_out/official-coverage-100/amd64-implicit-system.json` has zero parse errors +and fingerprint +`7cb619254f6792d391587dde90537696f6f1c181b5f3aedcaeb080fe6cd890d1`. +The typed RTM grammar covers the complete Go 1.27 optab family: +`XBEGIN`, `XABORT`, `XEND`, and `XTEST`. This intentionally includes the +accepted label and PC-relative `XBEGIN` forms even though Go's positive encoder +corpus leaves its examples commented as TODOs. LLVM's RTM intrinsics preserve +the successful/fallback CFG, EAX abort status, Yu8 immediate domain, and XTEST +flag state; the feature is not modeled as a no-op. Go positive/negative oracles +and LLVM 22 objects pass for all five x86 targets. The amd64 official count is +`6711/6/23`; report `_out/official-coverage-100/amd64-rtm.json` has zero parse +errors and fingerprint +`6ce5749aa14a5ac815a382d5cf456e144db26305e8295e344810a49aedb52e2e`. +The typed fixed-system grammar covers the complete operand-free +`CLAC`/`CLI`/`CLTS`/`ENDBR64`/`ICEBP`/`INVD`/`RSM`/`STAC`/`STI`/`SWAPGS`/ +`UD1`/`WBINVD` family. Its specification stores Go's exact bytes and separates +ordinary fallthrough, architectural traps, and non-returning control transfer. +This preserves Go's 386 compatibility rows for 64-bit-only spellings without +letting LLVM silently select a different mode-specific instruction. Go +positive/negative oracles and LLVM 22 objects pass on all five x86 targets. +The amd64 official count is `6723/6/11`; report +`_out/official-coverage-100/amd64-fixed-system.json` has zero parse errors and +fingerprint +`a04a7fa19725cce4ca83d2a39566b5b4be231bc5e2f1c15ff918479c23715393`. +The typed far-return grammar covers all Go 1.27 `IRETW/L/Q` and +`RETFW/L/Q` rows, including both operand-free and Yi32-immediate RETF forms. +It preserves Go's imm16 truncation (including 386's classify-after-int32 +compatibility), rejects Q-width forms on 386, emits exact encodings, and marks +all forms as control-flow terminators. Block splitting retains any following +unreachable instructions instead of silently dropping them. Go +positive/negative oracles and LLVM 22 objects pass on all five x86 targets. +The amd64 official count is `6727/6/7`; report +`_out/official-coverage-100/amd64-far-return.json` has zero parse errors and +fingerprint +`5e64d4ff8c67ec797efe15a3a63d821f138489ed5245b911ea4c05e0bdca645c`. +The typed system-transfer grammar covers all Go 1.27 `SYSENTER`, +`SYSENTER64`, `SYSEXIT`, `SYSEXIT64`, and `SYSRET` rows. Exact encodings are +paired with the architectural CX/DX and amd64 CX/R11 inputs so translated +assembly receives real implicit-register state rather than bytes alone. The +typed mode rejects 64-bit spellings on 386; entry forms can fall through while +exit/return forms terminate and split following blocks. Go positive/negative +oracles and LLVM 22 objects pass on all five x86 targets. The amd64 official +count is `6732/6/2`; report +`_out/official-coverage-100/amd64-system-transfer.json` has zero parse errors +and fingerprint +`75112eac5e72e24645081e543d78516fdef3b572bab04a3242d6ca2e63f42ada`. +The final implicit legacy batch models `LEAVEW/L/Q` as one width table and +`XLAT` as its AX/BX implicit-register form. LEAVE implements `SP = BP; POP BP` +with 386 address wrapping; XLAT preserves upper AX bits while loading +`byte[BX+AL]`. Go positive/negative oracles, all five x86 LLVM 22 targets, and +native/Rosetta semantics pass. The same batch completed the segment-stack +matrix above and brought the final official reports to 386 `50/7/0` and amd64 +`6734/6/0`; the amd64 fingerprint is +`786c884a97756aff577826e58042c0f83ed97d42e7d754eb9d0aa1731205718c`. +The root module, nested +command modules, format/build gates, standard-library matrix, +ARM64 x/arch corpus, curated reported-library corpus, and native AMD64/ARM64 +conformance pass locally. The official coverage baseline is intentionally not +updated until all five reports have zero unsupported forms; the Go 1.27 entries +are now updated from those final reports. The strict compile benchmark passes +184/184 files with zero N/A in 18 target-seconds. Go 1.20 also passes the full +root-module suite. Go 1.22 +passes source compilation and root tests locally, but its old linker emits a +test binary rejected by the current macOS dyld for missing `LC_UUID`; use the +Linux CI result rather than treating that host-tool failure as a code failure. + +The last portability failures are fixed in `f44f406` and `6f9c4b6`. +Unbound generic detection uses the `TypeParams`/`TypeArgs` method interface so +it compiles on Go 1.20 through 1.27, the Windows hosted-toolcache GOROOT link +has a narrowly scoped existing-path fallback, and the DIT standard-library +fixture is selected with the `go1.27` release tag instead of failing older Go +versions. Focused tests pass on Go 1.20.14, 1.22.12, and 1.27.1. The PR body is +updated with the 838-candidate funnel and current official coverage table. + +The latest 20,000-entry backfill exposed three real regressions and their +focused tests failed before fixes. `rust2go` needs the architecture-specific +`g` register alias (amd64 R14, ARM R10, ARM64 R28; wasm remains G), including +bare, memory-base/index, effective-address and indirect operands. Keep symbol +names such as `g(SB)` intact. `foundation` needs the entire NEG/NOT +`yscond(Ymb)` grammar, shared by lowering, liveness and modeled 386 SP writes. +Wide byte-register spellings use raw ModRM numbering; AH/CH/DH/BH select +SP/BP/SI/DI, and BPB/SIB/DIB/R8B-R15B select full GP registers. The 78-case +native/Rosetta semantic test caught a real BPB truncation bug after object +compilation was already green. `gomlx/compute` has Go declarations gated by +`goexperiment.simd` while some assembly remains selected without that tag. +Pure tail stubs now inherit their destination's FP ABI, including chains, +through `internal/asmsig` shared by both command drivers. Unknown cycles, +register-changing bodies, indirect/offset transfers and declared signatures +are protected by negative tests. + +The full root suite passed in 399.311 seconds after these changes; both command +modules, builds, formatting, all five current-Go official coverage checks, +ARM64 x/arch checks and the strict benchmark passed. The benchmark compiled +184/184 files with no N/A in 25 target-seconds. Shards 1, 10 and 11 were replayed +after the fixes and the 32-report verifier proved the exact 848-match ledger. +Rerun the full corpus after upstream integration to validate the combined tree. + +All Go 1.20-1.27 coverage baselines were refreshed after reviewing the complete +40-report matrix: supported forms never decreased and unsupported forms never +increased. Go 1.21-1.27 have zero unsupported forms. Go 1.20 retains one +historical `VADDPD.Z X30, X1, X0` row: its assembler accepts it, but Go 1.27 +correctly requires a mask for `.Z`. Do not silently classify it as supported +or context. The full x/arch decoder corpus is now 752 supported, 76 context, +280 unsupported, with zero parse errors; its native-Go-accepted required +family subset remains 146 supported plus 38 context and zero unsupported. + +Current main (`d896d4b`, including PR 41's foreign-ABI ARM64 object support) is +integrated locally in merge commit `b50d32d`. The dependency merge preserves +`phuslu/log v1.0.133` and `pierrec/lz4/v4 v4.1.30`. Post-merge root tests passed +in 545.075 seconds, and both nested command modules, all builds, gofmt and diff +checks passed. The complete 32-shard replay is in progress. Keep the ledger +read-only until it finishes; its canonical report directory is partial while +that command is running, not a completed aggregate. + +The next agent should: + +1. Finish the post-merge corpus replay and check the current contribution's CI, + review and coverage. Push only to the `cpunion` fork. The PR body must report + the 848-candidate checkpoint and current official coverage table, and label + incomplete validation accurately. Do not report old CI or Codecov results as + current-head success. +2. Resume contiguous Module Index history discovery from the ledger-derived + cursor toward 2019-04-10, using the automatic reverse mode and one atomic + writer. Retry retained failures, validate the ledger, and commit checkpoints + promptly. +3. Rerun all 32 corpus shards after each committed Discovery checkpoint, then + check CI, Codecov, and review. Keep PR 40 draft until every gate is green and + update it only through the `cpunion` fork. Never merge the upstream PR. + +This checkpoint is temporary handoff state. Update or remove it when the work is +finished; the remaining sections are durable repository procedure. + +## Repository and contribution safety + +- `xgo-dev/plan9asm` is upstream and is outside the direct-push authority + boundary. Never push to `origin` or `xgo-dev`, and never merge the upstream + PR. Push the contribution branch only to the allowed `cpunion` fork. +- Fetch upstream before final validation and inspect divergence. Do not rebase + or rewrite while tests are running, and do not discard unrelated dirty-tree + changes. +- Use `apply_patch` for source edits. Use `gofmt` for mechanical formatting. +- Generated reports belong under `_out/` or a temporary directory. Only the + normalized Discovery ledger is committed; never commit ZIPs, module caches, + object files, raw run directories, or compressed reports. + +## Sources of truth + +- Use the supported Go toolchain's assembler tables under + `$(go env GOROOT)/src/cmd/internal/obj/` as the authority for opcode, + operand, register, suffix, masking, broadcast, and rounding forms. +- For x86 AVX/EVEX instructions, inspect both the referenced `ytab` and every + opcode attribute in `avx_optabs.go`. A shared `ytab` does not imply that + rounding, SAE, broadcast, or zeroing flags are identical. +- Confirm uncertain forms with the Go assembler. Do not infer a form solely + from Intel syntax or from a third-party source file. +- Treat `386`, `amd64`, `arm`, `arm64`, and `wasm` as supported architectures. + A form must not be classified as unsupported merely because the host has a + different architecture. + +## Instruction-family workflow + +Use test-driven development for every instruction change: + +1. Reproduce the unsupported instruction or incorrect operand-form behavior in + a focused test and run it to observe the expected failure. +2. Before implementing the opcode, enumerate its complete family and all forms + in the current Go assembler tables. Add positive and negative form tests. +3. Implement a coherent instruction family, not only the single spelling that + exposed the gap. Cover every X/Y/Z width, register and memory source, + architecture restriction, mask/zero form, broadcast form, and rounding/SAE + form present in the Go tables. +4. Compile generated IR with LLVM 22 for every affected target. Add runtime + conformance when an instruction's lane preservation, operand order, flags, + masking, NaN behavior, or memory effects are not established by compilation. +5. Rerun the discovering external-library shard or official corpus that exposed + the problem. One fixed mnemonic must not hide another form from the same + family. + +Prefer typed, table-driven grammars over mnemonic-specific branches. Separate +orthogonal axes such as operation, lane/stack width, operand class, encoding +generation, architecture mode, masks/broadcast/rounding, implicit registers, +and semantic effect. The parser/validator, register-liveness scan, lowering, +supported-op extraction, and completeness test should consume the same spec +where practical. A completeness test must compare the whole spec table with +the current Go encoder family so adding one observed spelling cannot leave +sibling forms unmodeled. + +For a newly discovered instruction, update all four layers before calling it +complete: the family-specific lowerer, positive/negative Go-table form tests, +LLVM 22 object compilation for every affected supported architecture, and the +architecture's supported-op extraction test in `cmd/plan9asmll/main_test.go`. +The external corpus uses that extraction result in its diagnostics, so omitting +the last layer can make a supported instruction look unsupported. + +A typical x86 investigation starts with the Go 1.27 tables and an assembler +probe: + +```sh +goroot=$(go env GOROOT) +rg -n 'A?VADDPS|yvaddps' "$goroot/src/cmd/internal/obj/x86" +sed -n ',p' "$goroot/src/cmd/internal/obj/x86/avx_optabs.go" +GOOS=linux GOARCH=amd64 go tool asm -o /tmp/form.o /tmp/form_amd64.s +GOOS=linux GOARCH=386 go tool asm -o /tmp/form.o /tmp/form_386.s +``` + +Record the initial failure in test output before adding the lowering. Focused +form tests normally belong in `amd64_ecosystem_test.go`, +`amd64_operand_forms_test.go`, or the corresponding ARM file. Add the opcode to +`TestExtractSupportedOpsFindsCompleteAddedInstructionFamilies` so external +corpus diagnostics recognize it. Semantic fixtures live under +`testdata/conformance/` and must be checked against both native Go and the +LLVM runtime oracle where supported. + +The main implementation entry points are: + +- x86/386/amd64: `amd64_blocks.go`, `amd64_needed.go`, `amd64_translate.go`, + then the family-specific `amd64_lower_*.go` file; +- ARM: `arm_blocks.go`, `arm_needed.go`, `arm_translate_cfg.go`, then + `arm_lower_*.go` and frame/register handling in `arm_eval.go`; +- ARM64: `arm64_translate.go`, `arm64_eval.go`, and `arm64_lower_*.go`; +- wasm: opcode families in `wasm_ops.go`, lowering in `wasm_translate.go`, and + intrinsic declarations in `translate_prelude.go`; +- command-side package signature, ABI, include, and target handling: + `cmd/plan9asmll/main.go` with tests in its nested module. + +Supported-opcode reporting scans opcode-keyed package maps as well as explicit +switches. Every newly introduced opcode map must have an architecture-specific +extraction regression in `cmd/plan9asmll/main_test.go`; otherwise a real +translator failure can be misreported as an unknown instruction. + +For x86 form tests, cover at least these targets: + +- `darwin/amd64` — `x86_64-apple-darwin` +- `linux/amd64` — `x86_64-unknown-linux-gnu` +- `windows/amd64` — `x86_64-pc-windows-msvc` +- `linux/386` — `i386-unknown-linux-gnu` +- `windows/386` — `i686-pc-windows-msvc` + +Do not add an `unsupported_forms` skip for a supported target. Context-dependent +forms may be classified separately only when translation genuinely requires +information unavailable to the scanner. + +## Toolchain requirements + +- Use Go 1.27 for new instruction development, Discovery, and external-library + corpus validation. The official standard-library/toolchain corpus separately + retains the Go 1.20 through Go 1.27 compatibility matrix. +- Run new instruction tests with the host Go toolchain while llgo's test runner + is incomplete, but do not add a `//go:build !llgo` exclusion to those tests. + They must remain discoverable so llgo can execute the same regression suite + once its testing and subprocess support is ready. +- Use LLVM 22 exactly. Never fall back to LLVM 23 or another installed release; + compatibility with another release does not prove LLVM 22 compatibility. +- LLVM compilation and runtime-oracle tests must fail when their required LLVM + 22 tools or supported target backend are unavailable. Never use `t.Skip` to + turn a missing `llc`, `clang`, linker, or supported triple into a green test. + A runtime test may skip only when the current host cannot execute that target; + its separate cross-runtime CI job must remain required. +- `scripts/llvm22.sh` accepts `llc-22`, an unversioned `llc` reporting version + 22, or `LLVM_CONFIG` pointing to LLVM 22. On macOS, Homebrew LLVM can be + selected with `LLVM_CONFIG="$(brew --prefix llvm@22)/bin/llvm-config"`. +- Prefer repository scripts because they validate the Go and LLVM versions + before running a corpus. + +Check the active tools before a substantial validation run: + +```sh +go version +source scripts/llvm22.sh +llc_cmd=$(find_llvm22_llc) +"$llc_cmd" --version +``` + +## Test and validation commands + +Run focused red/green tests while developing, then run all applicable gates. + +```sh +# Root module and the two nested command modules. +go test ./... -count=1 +(cd cmd/plan9asm && go test ./... -count=1) +(cd cmd/plan9asmll && go test ./... -count=1) + +# Formatting and build checks. +test -z "$(gofmt -l .)" +go build ./... +(cd cmd/plan9asm && go build ./...) +(cd cmd/plan9asmll && go build ./...) + +# Semantic runtime checks. Cross execution requires the CI cross compilers and +# QEMU; native checks should still be run locally when applicable. +go test . -run '^(TestAMD64ConformanceNativeGo|TestAMD64ConformanceLLVMRuntime)$' -count=1 -v +PLAN9ASM_CROSS_EXEC=1 go test . -run '^(TestCrossLinuxRuntimeMatrix|TestARM64Conformance)' -count=1 -v + +# Official Go assembler and standard-library corpora. +scripts/check-go-asm-coverage.sh +scripts/check-stdlib-corpus.sh +scripts/check-arm64-plan9-corpus.sh + +# Go 1.27 standard-library translate + LLVM 22 object-compile benchmark. +scripts/benchmark-compile.sh + +# Curated issue/reported libraries and all discovered assembly candidates. +scripts/check-reported-library-corpus.sh all +for shard in $(seq 0 31); do + scripts/check-discovered-library-corpus.sh "$shard" 32 +done +``` + +The official corpus gate requires every form to be classified, no parse errors, +and no unsupported forms. Inspect form-level reports before intentionally +updating `testdata/coverage/go-asm-baseline.json`; never update a fingerprint +merely to make CI green. + +`scripts/benchmark-compile.sh` is the fast, strict compilation/performance +gate for `linux/{386,amd64,arm,arm64}` and `js/wasm`. It requires Go 1.27, +requires LLVM 22, builds `cmd/plan9asmll`, translates every applicable standard +library assembly file, and compiles every generated module with `llc-22`. A +failed, skipped, or N/A file fails the job; success must equal the complete file +count. The current Go 1.27 inventory is 184 files (33/55/30/47/19) and normally +finishes in well under the default budgets of 300 seconds per target and 900 +seconds total. Detailed per-target logs use GitHub Actions groups, while +`_out/compile-benchmark/{summary.json,summary.md}` and the per-target JSON files +retain timings and counts. Override only for focused local diagnosis with +`PLAN9ASM_BENCHMARK_TARGETS`, `PLAN9ASM_BENCHMARK_MAX_TARGET_SECONDS`, +`PLAN9ASM_BENCHMARK_MAX_TOTAL_SECONDS`, or `PLAN9ASM_BENCHMARK_REPORT_DIR`. + +## External-library discovery + +Discovery reads the official Go module index from the current time backwards to +2019-04-10, resolves each selected module as `module@latest`, and inspects that +exact ZIP. It +must independently rediscover libraries mentioned in issues; the curated +manifest is an additional regression suite, not an input whitelist for +Discovery. + +The committed checkpoint is one diff-friendly ledger: + +```text +testdata/discovery/ledger/ + manifest.json + records/00.jsonl ... records/ff.jsonl +``` + +- Select a shard with the first byte of `sha256(module path)`. +- Keep every record for a module in the same shard. +- Sort each shard by module path, Go semantic version, then record kind. +- Select one logical module family by module-path major first, then Go semantic + version. An older history window can upgrade `/v2` to `/v3`; after that, + further `/v2` and `/v1` records are skipped. A future incremental `/v4` or + higher current-major semver must still cross the checkpoint. +- Resolve `@latest` after a family crosses that checkpoint. A newly resolved + higher-priority exact version replaces all older scanned, matched, and + exact-failure records for that family. If resolving + `@latest` itself fails, retain the last exact result alongside the retry. +- Record completed exact versions even when they contain no assembly so later + scans do not download them again. +- Matched records retain every discovered `.s` relative path, including files + for architectures plan9asm does not support yet. Their `architectures` field + is rebuilt from all GOARCH filename suffixes known to the current Go toolchain, + not only architectures plan9asm already supports. When adding a platform, + select exact `module@version` candidates from these paths and rerun only + applicability/translation for that target; never rescan all index entries or + all no-assembly modules. Source build constraints and declarations are + reevaluated after fetching only those matched exact versions. +- Retain transient failures for retry; a successful retry removes the failure + record for that exact version. +- Keep only `manifest.json` and `records/*.jsonl`. Do not commit run directories, + recursive ledgers, generated archives, or `.gz` files. + +Continue a reverse scan by updating the ledger in place: + +```sh +go run ./cmd/plan9asmdiscover \ + -limit 20000 \ + -workers 64 \ + -traffic-report _out/discovery-traffic.json \ + -out-dir testdata/discovery/ledger +``` + +`plan9asmdiscover` is the only normal writer for committed records. With +`-out-dir` it first reads and validates the existing ledger, derives the +history upper bound from the earliest covered range, selects modules in that +reverse index window by +`(module-path major, Go semver)`, resolves only checkpoint upgrades through +`module@latest`, avoids downloading an exact version already recorded, replaces +obsolete versions, removes a same-version failure after success, deduplicates +exact module versions and assembly paths, sorts Go +versions with `golang.org/x/mod/semver`, rewrites all 256 hash shards in a +temporary directory, and replaces the ledger atomically. It records successful +versions even when no assembly exists. Do not hand-append JSONL lines. + +The official index exposes only an ascending `since` feed. Reverse discovery +therefore brackets a time window small enough to read completely, takes its +newest records, and retains the earliest timestamp group whole. A batch may +slightly exceed `-limit`; this is required so the next derived history cursor +cannot skip records sharing a timestamp. Every selected `[since,before)` +window and exact count is saved in `manifest.json#index_ranges`. Ranges are +ordered by parsed RFC3339 time and every adjacent pair must share an identical +endpoint. The reader/writer rejects gaps, overlaps, and conflicting repeated +ranges instead of guessing coverage. Empty ledgers start at the current time +with a zero-width anchor. + +Run an incremental head scan whenever needed, independently of history progress: + +```sh +go run ./cmd/plan9asmdiscover \ + -scan-mode incremental \ + -workers 64 \ + -out-dir testdata/discovery/ledger +``` + +Incremental mode derives its lower bound from the greatest committed range +upper bound and always consumes the complete interval up to the captured +current-time upper bound. `-limit` is ignored, so a new high-water mark cannot +hide an unfinished interval. Empty head intervals are recorded with a zero +count. History and incremental scans therefore extend opposite ends of one +continuous range set without hand-copied cursors. + +Retry retained failures without reading the index or changing its coverage +ranges: + +```sh +go run ./cmd/plan9asmdiscover \ + -scan-mode retry \ + -workers 64 \ + -out-dir testdata/discovery/ledger +``` + +Retry mode selects the highest `(module-path major, Go semver)` failed exact +version in each family. A successful retry replaces that failure with the +canonical scanned/matched record; unresolved failures remain in the ledger. + +Discovery parallelism is internal to one process: `-workers` concurrently +resolves metadata and inspects ZIP ranges, then one writer merges and replaces +the ledger. The writer holds a sibling `.ledger.writer-lock` directory and a +second writer fails rather than risking a lost update. Do not launch multiple +processes that write the same ledger, and do not update the ledger while corpus +shards are reading it. Corpus shards may run in parallel after discovery has +finished because they only read the ledger and each writes a distinct report. + +ZIP inspection is also two-stage. Every selected module must resolve +`@latest`; a completed exact version is reused before any ZIP request. A new +exact version is inspected through HTTP HEAD/range reads of its ZIP directory +and candidate `.s` contents. Only `matched` versions are later materialized as +complete modules by the corpus runner for source applicability, translation, +and LLVM compilation. The Go module cache prevents redundant network downloads +between corpus runs, while translation and compilation intentionally rerun. +ZIPs no larger than 64 KiB are fetched whole. Larger ZIPs start with the +22-byte EOCD, fetch the exact central-directory range, and use 64 KiB read-ahead +only for missing directory/source blocks. The 65,557-byte maximum EOCD search +is a fallback for comments and ZIP64. Changing these thresholds requires a +measured traffic/latency justification and updated range-reader tests. + +Pass `-traffic-report ` for per-module HTTP accounting. The sorted JSON +separates `@latest`, ZIP HEAD, ZIP range, and whole-small-ZIP requests and bytes, +plus global index traffic. Its byte count is the response entity body read with +`Accept-Encoding: identity`, excluding headers and TLS/IP overhead. Each module +entry includes indexed and resolved versions, outcome, request totals, payload +totals, and advertised full ZIP size. Outcomes are `scanned`, `matched`, +`failure`, `reused_scanned`, and `reused_matched`. Modules omitted from the +traffic report made no proxy request. Keep this generated report under `_out/`; +do not commit it. Find the largest modules in a batch with: + +```sh +jq -r '.modules[] | [.total_body_bytes, .total_requests, .module, + .resolved_version, .outcome] | @tsv' _out/discovery-traffic.json | + sort -nr | head -20 +``` + +Successful GitHub pseudo-version ZIP inspections are reused by commit across +case aliases of the repository owner/name, both from the committed ledger and +through an in-process singleflight. Do not fold semantic tags or the +case-sensitive module subdirectory after `github.com/owner/repo`. + +The writer is deliberately idempotent. Running the same index window again +does not duplicate modules, versions, assembly paths, or failures; it rewrites +the canonical shards in the same order. There is no manual sorting step and no +separate per-run directory to merge. If writer behavior changes, add a fixture +to `cmd/plan9asmdiscover/main_test.go` that runs the merge twice and compares +the resulting files byte-for-byte. + +The three record kinds are: + +- `scanned`: exact `module@version` inspected successfully, with or without + assembly; +- `matched`: the same exact version has assembly, plus normalized architecture + hints and module-relative `.s` paths; +- `failure`: the exact version, or `@latest` if resolution failed, must be + retried and is not considered scanned. + +Validate record integrity and summarize the checkpoint after every update: + +```sh +go test ./cmd/plan9asmdiscover ./cmd/plan9asmcorpus -count=1 +go run ./cmd/plan9asmdiscover -status \ + -out-dir testdata/discovery/ledger +test "$(find testdata/discovery/ledger/records -type f -name '*.jsonl' | wc -l | tr -d ' ')" = 256 +find testdata/discovery -type f \( -name '*.gz' -o -name '*.zip' \) -print +``` + +The last command must print nothing. `go test` re-reads every shard and rejects +wrong hashes, duplicates, unsafe paths, invalid successful semvers, unexpected +files, or module/string-version/kind ordering. A legacy report can be imported +once with `-convert-report -out-dir testdata/discovery/ledger`; do not +create another `runs/` hierarchy. Import normalization keeps only the greatest +`(module-path major, Go semver)` for each logical family; normal discovery +applies the same monotonic rule to the exact version returned by the current +`@latest` resolution. + +Discovery corpus sharding uses `sha256(module@version) % 32`, independently of +the ledger file shard. Run and retain one auditable report per shard: + +```sh +PLAN9ASM_DISCOVERY_PARALLELISM=4 \ + scripts/check-discovered-library-corpus.sh all 32 + +jq -s '{ + index_shards: length, + selected: (map(.selected) | add), + passed: (map(.passed) | add), + not_applicable: (map(.not_applicable) | add), + failed: (map(.failed) | add), + translations: (map(.translations) | add), + not_applicable_translations: (map(.not_applicable_translations) | add) +}' _out/discovered-library-corpus/shard-*.json +``` + +The `all` form removes stale shard reports, runs all read-only shards in +parallel, and then requires `scripts/verify-discovered-library-corpus.sh` to +prove that every current ledger match appears exactly once, in the correct +shard, with the exact saved assembly inventory and a passing or evidence-backed +not-applicable result. CI performs the same aggregate gate after downloading +all 32 shard artifacts. + +When implementing a new supported platform, replay only records whose saved +assembly paths may match it. The filename filter excludes only paths that +conclusively name another GOOS or GOARCH; unsuffixed files and unknown/custom +suffixes remain eligible and are checked after the exact version is fetched: + +```sh +# After linux/riscv64 has been added to plan9asm's supported-target validation: +for shard in $(seq 0 31); do + PLAN9ASM_DISCOVERY_TARGETS=linux/riscv64 \ + scripts/check-discovered-library-corpus.sh "$shard" 32 \ + "_out/discovered-library-corpus/riscv64-shard-$shard.json" +done +``` + +This command reads only `records/*.jsonl`, downloads the recorded matched exact +versions, derives package paths from the saved `.s` paths, and performs current +Go applicability, translation, and LLVM 22 compilation for the requested +target. It does not read the Go module index or revisit scanned no-assembly +versions. The report records both the full ledger candidate count and the +target-eligible count so the filter is auditable. + +Every report must satisfy `selected = passed + not_applicable + failed`, every +target must satisfy `total_asm = success + not_applicable + failed`, and final +`failed` must be zero. A candidate with at least one successful target is +`passed`; a candidate is globally `not_applicable` only when no selected source +can be translated on any supported target. + +Source applicability must follow Go's rules: use file-name GOOS/GOARCH suffixes +and `go/build.Context.MatchFile` for constraints. For unsuffixed assembly whose +source is architecture-specific, probe it with the Go assembler for the target +matrix. Every applicable discovered `.s` file must enter translation and LLVM +22 compilation, or the candidate fails; do not silently skip an applicable file. + +For each target/tag/package group, Discovery then runs `go build` against that +exact package path, never `package/...`. A compiler rejection on Go 1.27 is +structured source N/A evidence for that package/target only; it does not exclude +another package, target, or retained version. Network, proxy, timeout, process, +and filesystem failures are infrastructure failures and must fail the shard for +retry, never become N/A. A package that builds must proceed to `go vet -asmdecl`, +translation, and LLVM 22 compilation. Only asmdecl's wrong argument size, +invalid FP offset, or invalid FP-width diagnostics are ABI N/A evidence; unknown +variables, missing declarations, dependency errors, unsupported instructions, +parse errors, and LLVM errors are not. + +An unsuffixed file may still encode one architecture's ABI in its `TEXT` +argument size. Classify a file/target pair as not applicable when its explicit +`TEXT $frame-args` size disagrees with the size derived from that target's +current Go declaration (the same condition reported by `go vet -asmdecl`). Do +not treat an omitted `-args` suffix as zero: current, valid packages use that +form. Emit the structured symbol, declared size, expected size, and target in +the corpus report. +Unsupported instructions, parse failures, LLVM failures, and generic source +errors are never valid not-applicable evidence. +If the current Go assembler conclusively rejects an unsuffixed source for every +target selected by Go's file/build constraints, retain a structured source-level +N/A item containing the file, attempted targets, and rejection kind. This is +appropriate for historical toolchain fixtures or generated invalid test input; +it must not be used when even one supported target accepts the source. + +The final report validator requires every source N/A item to name an allowed +kind, one or more discovered assembly files, attempted `GOOS/GOARCH` targets, +and a nonempty diagnostic. `applicable_asm_files` is a unique file set even when +the same file is exercised on several targets; `translations` carries the +per-target count. + +## Pull-request completion + +- Keep broad corpus work as a draft until local tests, CI, review, and coverage + checks pass. +- The PR body must report a funnel with index entries, exact module versions, + unique module paths, assembly-bearing versions, retry failures, candidates + passing/N/A/failing, and newly covered instruction families/forms. +- Calculate funnel values from the committed ledger manifest and the 32 saved + shard reports, not from terminal recollection. Include a Markdown table in + the PR body only; do not duplicate transient counts in the Discovery README. +- Verify that libraries named by user-reported issues occur in the Discovery + ledger independently of the curated manifest, and state their exact versions + and shard outcomes in the PR body. +- When replacing an obsolete generated ledger layout, rewrite the contribution + branch before publishing so deleted run files and compressed artifacts do not + remain in the PR's commit history. Use `--force-with-lease`, never overwrite + an unrelated remote update. diff --git a/amd64_abi.go b/amd64_abi.go new file mode 100644 index 00000000..5c31d111 --- /dev/null +++ b/amd64_abi.go @@ -0,0 +1,92 @@ +package plan9asm + +import "fmt" + +func (c *amd64Ctx) abi0CallStackPtr(off int64) (string, error) { + sp, err := c.loadReg(SP) + if err != nil { + return "", fmt.Errorf("ABI0 call stack: %w", err) + } + addr := sp + if off != 0 { + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %d\n", next, sp, off) + addr = "%" + next + } + ptr := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", ptr, addr) + return "%" + ptr, nil +} + +func (c *amd64Ctx) abi0CallArgs(callee string, sig FuncSig) ([]string, error) { + slotsByArg := make([][]FrameSlot, len(sig.Args)) + for _, slot := range sig.Frame.Params { + if slot.Index < 0 || slot.Index >= len(sig.Args) { + return nil, fmt.Errorf("amd64 call %q: ABI0 parameter at +%d has invalid argument index %d", callee, slot.Offset, slot.Index) + } + slotsByArg[slot.Index] = append(slotsByArg[slot.Index], slot) + } + args := make([]string, 0, len(sig.Args)) + for argIndex, argType := range sig.Args { + slots := slotsByArg[argIndex] + if len(slots) == 0 { + return nil, fmt.Errorf("amd64 call %q: ABI0 argument %d has no frame slot", callee, argIndex) + } + if len(slots) == 1 && len(frameSlotFields(slots[0])) == 0 { + if slots[0].Type != argType { + return nil, fmt.Errorf("amd64 call %q: ABI0 argument %d frame type %s does not match %s", callee, argIndex, slots[0].Type, argType) + } + ptr, err := c.abi0CallStackPtr(slots[0].Offset) + if err != nil { + return nil, err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", value, argType, ptr) + args = append(args, fmt.Sprintf("%s %%%s", argType, value)) + continue + } + aggregate := "undef" + for _, slot := range slots { + if len(frameSlotFields(slot)) == 0 { + return nil, fmt.Errorf("amd64 call %q: ABI0 aggregate argument %d has a scalar frame slot", callee, argIndex) + } + ptr, err := c.abi0CallStackPtr(slot.Offset) + if err != nil { + return nil, err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", value, slot.Type, ptr) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertvalue %s %s, %s %%%s%s\n", inserted, argType, aggregate, slot.Type, value, frameSlotExtractSuffix(slot)) + aggregate = "%" + inserted + } + args = append(args, fmt.Sprintf("%s %s", argType, aggregate)) + } + return args, nil +} + +func (c *amd64Ctx) storeABI0CallResult(callee string, sig FuncSig, result string) error { + if len(sig.Frame.Results) == 0 { + return fmt.Errorf("amd64 call %q: ABI0 result %s has no frame slot", callee, sig.Ret) + } + fields, aggregate := parseLiteralStructFields(sig.Ret) + for _, slot := range sig.Frame.Results { + value := result + if aggregate { + if slot.Index < 0 || slot.Index >= len(fields) || fields[slot.Index] != slot.Type { + return fmt.Errorf("amd64 call %q: ABI0 result slot %d does not match %s", callee, slot.Index, sig.Ret) + } + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", extracted, sig.Ret, result, slot.Index) + value = "%" + extracted + } else if slot.Index != 0 || slot.Type != sig.Ret { + return fmt.Errorf("amd64 call %q: ABI0 scalar result frame does not match %s", callee, sig.Ret) + } + ptr, err := c.abi0CallStackPtr(slot.Offset) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, ptr %s, align 1\n", slot.Type, value, ptr) + } + return nil +} diff --git a/amd64_blocks.go b/amd64_blocks.go index 19e9cba4..b516e752 100644 --- a/amd64_blocks.go +++ b/amd64_blocks.go @@ -10,6 +10,30 @@ type amd64Block struct { instrs []Instr } +func isAMD64ConditionalBranch(op Op) bool { + switch Op(strings.ToUpper(string(op))) { + case "JCXZW", "JCXZL", "JCXZQ": + return true + case "JE", "JEQ", "JZ", "JNE", "JNZ", + "JL", "JLT", "JNGE", "JLE", "JNG", "JG", "JGT", "JNLE", "JGE", "JNL", "JS", "JMI", "JNS", "JPL", + "JA", "JHI", "JNBE", "JAE", "JHS", "JNB", "JB", "JLO", "JNAE", "JBE", "JLS", "JNA", + "JC", "JCS", "JNC", "JCC", + "JO", "JOS", "JNO", "JOC", "JP", "JPE", "JPS", "JNP", "JPO", "JPC": + return true + default: + return false + } +} + +func isAMD64CounterZeroBranch(op Op) bool { + switch Op(strings.ToUpper(string(op))) { + case "JCXZW", "JCXZL", "JCXZQ": + return true + default: + return false + } +} + func amd64SplitBlocks(fn Func) []amd64Block { blocks := []amd64Block{{name: "entry"}} cur := 0 @@ -17,22 +41,20 @@ func amd64SplitBlocks(fn Func) []amd64Block { isPCRelTarget := func(ins Instr) (off int64, ok bool) { op := strings.ToUpper(string(ins.Op)) - switch Op(op) { - case "JMP", - "JE", "JEQ", "JZ", "JNE", "JNZ", - "JL", "JLT", "JLE", "JG", "JGT", "JGE", "JS", "JNS", - "JB", "JLO", "JBE", "JA", "JHI", "JAE", "JHS", "JLS", "JNA", - "JNC", "JC", "JCC": - default: + if op != "JMP" && op != "LOOP" && op != "XBEGIN" && !isAMD64ConditionalBranch(Op(op)) { return 0, false } - if len(ins.Args) != 1 || ins.Args[0].Kind != OpMem { + args := ins.Args + if op != "JMP" && len(args) == 2 && args[0].Kind == OpImm { + args = args[1:] + } + if len(args) != 1 || args[0].Kind != OpMem { return 0, false } - if !strings.EqualFold(string(ins.Args[0].Mem.Base), "PC") { + if !strings.EqualFold(string(args[0].Mem.Base), "PC") { return 0, false } - return ins.Args[0].Mem.Off, true + return args[0].Mem.Off, true } startAnon := func() { @@ -46,16 +68,16 @@ func amd64SplitBlocks(fn Func) []amd64Block { return true } op := strings.ToUpper(string(ins.Op)) - switch Op(op) { - case "JMP", - "JE", "JEQ", "JZ", "JNE", "JNZ", - "JL", "JLT", "JLE", "JG", "JGT", "JGE", "JS", "JNS", - "JB", "JLO", "JBE", "JA", "JHI", "JAE", "JHS", "JLS", "JNA", - "JNC", "JC", "JCC": + if _, ok := amd64FarReturnSpecs[Op(op)]; ok { + return true + } + if spec, ok := amd64SystemTransferSpecs[Op(op)]; ok && spec.terminates() { + return true + } + if op == "JMP" || op == "LOOP" || op == "XBEGIN" || isAMD64ConditionalBranch(Op(op)) { return true - default: - return false } + return false } linear := make([]Instr, 0, len(fn.Instrs)) diff --git a/amd64_byte_alias_test.go b/amd64_byte_alias_test.go new file mode 100644 index 00000000..5a5a21f7 --- /dev/null +++ b/amd64_byte_alias_test.go @@ -0,0 +1,102 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +// Go 1.27's amd64 Yrb class contains BPB/SIB/DIB and R8B..R15B in +// addition to the four low and four high legacy byte-register spellings. +// REG_SPB is deliberately not classified as Yrb by cmd/internal/obj/x86. +func TestTranslateAMD64ExtendedByteRegisterCompleteGoAssemblerClass(t *testing.T) { + aliases := []string{"BPB", "SIB", "DIB", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B"} + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT extendedbyteforms(SB),NOSPLIT,$0-0\n") + for _, alias := range aliases { + fmt.Fprintf(&source, "\tMOVB %s, (AX)\n", alias) + fmt.Fprintf(&source, "\tMOVB (AX), %s\n", alias) + fmt.Fprintf(&source, "\tMOVBQZX %s, CX\n", alias) + fmt.Fprintf(&source, "\tMOVBQSX %s, DX\n", alias) + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "extendedbyteforms": {Name: "extendedbyteforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "extended-byte-"+target.name+".ll", "extended-byte-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86ExtendedByteRegisterRejectsFormsOutsideGoAssemblerClass(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + aliases := []string{"SPB"} + if target.goarch == "386" { + aliases = append(aliases, "BPB", "SIB", "DIB", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B") + } + for _, alias := range aliases { + instruction := "MOVB " + alias + ", (AX)" + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's byte-register class for %s", instruction, target.goarch) + } + } + }) + } +} + +func TestAMD64ExtendedByteRegisterAliasesShareFullRegisterStorage(t *testing.T) { + for _, test := range []struct { + alias Reg + base Reg + }{ + {BPB, BP}, {SIB, SI}, {DIB, DI}, + {R8B, Reg("R8")}, {R9B, Reg("R9")}, {R10B, Reg("R10")}, {R11B, Reg("R11")}, + {R12B, Reg("R12")}, {R13B, Reg("R13")}, {R14B, Reg("R14")}, {R15B, Reg("R15")}, + } { + base, shift, ok := amd64ByteAlias(test.alias) + if !ok || base != test.base || shift != 0 { + t.Errorf("amd64ByteAlias(%s) = (%s, %d, %v), want (%s, 0, true)", test.alias, base, shift, ok, test.base) + } + } +} diff --git a/amd64_conformance_test.go b/amd64_conformance_test.go index f481eb5d..f2ab56de 100644 --- a/amd64_conformance_test.go +++ b/amd64_conformance_test.go @@ -15,9 +15,9 @@ func TestAMD64ConformanceNativeGo(t *testing.T) { if runtime.GOARCH != "amd64" && !(runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable()) { t.Skip("native Go assembler oracle requires an amd64 host") } - cmd := exec.Command("go", "test", "./testdata/conformance/amd64") + cmd := exec.Command("go", "test", "-count=1", "./testdata/conformance/amd64") if runtime.GOARCH != "amd64" { - cmd.Env = append(os.Environ(), "GOARCH=amd64") + cmd.Env = append(os.Environ(), "GOARCH=amd64", "PLAN9ASM_ROSETTA=1") } if out, err := cmd.CombinedOutput(); err != nil { t.Fatalf("native Go conformance failed: %v\n%s", err, out) @@ -31,7 +31,7 @@ func TestAMD64ConformanceLLVMRuntime(t *testing.T) { } llc, clang, ok := findLlcAndClang(t) if !ok { - t.Skip("llc/clang not found") + t.Fatal("llc/clang not found") } src, err := os.ReadFile(filepath.Join("testdata", "conformance", "amd64", "conformance_amd64.s")) @@ -133,6 +133,238 @@ func TestAMD64ConformanceLLVMRuntime(t *testing.T) { {Offset: 24, Type: I64, Index: 3, Field: -1}, }}, }, + "scalarShiftRotateSemantics": { + Name: "scalarShiftRotateSemantics", + Args: []LLVMType{Ptr, I64, I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }, + "incDecSemantics": { + Name: "incDecSemantics", + Args: []LLVMType{Ptr, I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + }}, + }, + "scalarAddSubSemantics": { + Name: "scalarAddSubSemantics", + Args: []LLVMType{Ptr, I64, I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }, + "compareExchangeScalarSemantics": { + Name: "compareExchangeScalarSemantics", + Args: []LLVMType{Ptr, Ptr, I64, I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + {Offset: 24, Type: I64, Index: 3, Field: -1}, + }}, + }, + "compareExchangePairSemantics": { + Name: "compareExchangePairSemantics", + Args: []LLVMType{Ptr, Ptr, I64, I64, I64, I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + {Offset: 24, Type: I64, Index: 3, Field: -1}, + {Offset: 32, Type: I64, Index: 4, Field: -1}, + {Offset: 40, Type: I64, Index: 5, Field: -1}, + }}, + }, + "parallelBitSemantics": { + Name: "parallelBitSemantics", + Args: []LLVMType{Ptr, I64, I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }, + "bitTestRegisterSemantics": { + Name: "bitTestRegisterSemantics", + Args: []LLVMType{Ptr, I64, I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }, + "bitTestMemorySemantics": { + Name: "bitTestMemorySemantics", + Args: []LLVMType{Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + "packedWordMultiplyAddSemantics": { + Name: "packedWordMultiplyAddSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "packedUnsignedSignedByteMultiplyAddSemantics": { + Name: "packedUnsignedSignedByteMultiplyAddSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "packedDotProductSemantics": { + Name: "packedDotProductSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + }}, + }, + "packedIntegerMinMaxSemantics": { + Name: "packedIntegerMinMaxSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "packedWordMultiplySemantics": { + Name: "packedWordMultiplySemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "packedFloatShuffleSemantics": { + Name: "packedFloatShuffleSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "inLaneFloatingPermuteSemantics": { + Name: "inLaneFloatingPermuteSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "immediatePackedBlendSemantics": { + Name: "immediatePackedBlendSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "packedUnpackSemantics": { + Name: "packedUnpackSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "qwordPermuteSemantics": { + Name: "qwordPermuteSemantics", + Args: []LLVMType{Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + "qwordVariablePermuteSemantics": { + Name: "qwordVariablePermuteSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "packedFloatMoveVEXSemantics": { + Name: "packedFloatMoveVEXSemantics", + Args: []LLVMType{Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + "packedFloatMoveMaskSemantics": { + Name: "packedFloatMoveMaskSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "packedSignExtendMoveVEXSemantics": { + Name: "packedSignExtendMoveVEXSemantics", + Args: []LLVMType{Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + "packedSignExtendMoveMaskSemantics": { + Name: "packedSignExtendMoveMaskSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, "goHexVectorOps": { Name: "goHexVectorOps", Args: []LLVMType{Ptr, Ptr, Ptr}, @@ -161,6 +393,121 @@ func TestAMD64ConformanceLLVMRuntime(t *testing.T) { Ret: Void, Frame: ptrParams, }, + "packedSubtractSemantics": { + Name: "packedSubtractSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "expandedEcosystemVectors": { + Name: "expandedEcosystemVectors", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "parityBranches": { + Name: "parityBranches", + Args: []LLVMType{I8}, + Ret: I64, + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: I8, Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 8, Type: I64, Index: 0, Field: -1}}, + }, + }, + "unorderedBranch": { + Name: "unorderedBranch", + Args: []LLVMType{LLVMType("double")}, + Ret: I64, + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: LLVMType("double"), Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 8, Type: I64, Index: 0, Field: -1}}, + }, + }, + "packedFloatToDwordModes": { + Name: "packedFloatToDwordModes", + Args: []LLVMType{Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + "sameWidthPackedConversionSemantics": { + Name: "sameWidthPackedConversionSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + }}, + }, + "packedSingleToDouble": { + Name: "packedSingleToDouble", + Args: []LLVMType{Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + "conditionalMoveCodes": { + Name: "conditionalMoveCodes", + Args: []LLVMType{Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + "fma3Semantics": { + Name: "fma3Semantics", + Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + {Offset: 48, Type: Ptr, Index: 6, Field: -1}, + }}, + }, + "binaryFloatingSemantics": { + Name: "binaryFloatingSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + }}, + }, + "horizontalFloatingSemantics": { + Name: "horizontalFloatingSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + }}, + }, }, }) if err != nil { @@ -176,9 +523,61 @@ extern uint32_t shiftLegacyThreeOperand(uint32_t src, uint32_t dst, uint32_t amo extern uint64_t clearTopBit(uint64_t value); extern void doubleShift32(uint32_t *out, uint32_t src, uint32_t dst, uint32_t amount); extern void doubleShift64(uint64_t *out, uint64_t src, uint64_t dst, uint64_t amount); +extern void scalarShiftRotateSemantics(uint64_t *out, uint64_t value, uint64_t count); +extern void incDecSemantics(uint64_t *out, uint64_t value); +extern void scalarAddSubSemantics(uint64_t *out, uint64_t value, uint64_t source); +extern void compareExchangeScalarSemantics(uint64_t *out, uint64_t *memory, uint64_t expected, uint64_t desired); +extern void compareExchangePairSemantics(uint64_t *out, uint64_t *memory, uint64_t expected_low, uint64_t expected_high, uint64_t desired_low, uint64_t desired_high); +extern void parallelBitSemantics(uint64_t *out, uint64_t mask, uint64_t source); +extern void bitTestRegisterSemantics(uint64_t *out, uint64_t value, uint64_t index); +extern void bitTestMemorySemantics(uint8_t *out, uint64_t *data); +extern void packedWordMultiplyAddSemantics(int32_t *out, int16_t *a, int16_t *b); +extern void packedUnsignedSignedByteMultiplyAddSemantics(int16_t *out, int8_t *signed_input, uint8_t *unsigned_input); +extern void packedDotProductSemantics(int32_t *out, int8_t *signed_bytes, uint8_t *unsigned_bytes, int16_t *words_a, int16_t *words_b, int32_t *accumulator); +extern void packedIntegerMinMaxSemantics(uint8_t *out, uint8_t *a, uint8_t *b); +extern void packedWordMultiplySemantics(uint16_t *out, int16_t *a, int16_t *b); +extern void packedFloatShuffleSemantics(uint8_t *out, uint8_t *a, uint8_t *b); +extern void inLaneFloatingPermuteSemantics(uint8_t *out, uint8_t *data, uint8_t *control); +extern void immediatePackedBlendSemantics(uint8_t *out, uint8_t *a, uint8_t *b); +extern void packedUnpackSemantics(uint8_t *out, uint8_t *a, uint8_t *b); +extern void qwordPermuteSemantics(uint64_t *out, uint64_t *data); +extern void qwordVariablePermuteSemantics(uint64_t *out, uint64_t *data, uint64_t *control); +extern void packedFloatMoveVEXSemantics(uint8_t *out, uint8_t *src); +extern void packedFloatMoveMaskSemantics(uint8_t *out, uint8_t *src, uint8_t *old); +extern void packedSignExtendMoveVEXSemantics(uint8_t *out, uint8_t *src); +extern void packedSignExtendMoveMaskSemantics(uint8_t *out, uint8_t *src, uint8_t *old); extern void goHexVectorOps(uint8_t *out, uint8_t *a, uint8_t *b); extern uint64_t goHexWordOps(uint64_t value, uint64_t count); extern void packedArithmeticShift32(int32_t *out, int32_t *src); +extern void packedSubtractSemantics(uint8_t *out, uint8_t *a, uint8_t *b); +extern void expandedEcosystemVectors(uint8_t *out, uint8_t *a, uint8_t *b); +extern uint64_t parityBranches(uint8_t value); +extern uint64_t unorderedBranch(double value); +extern void packedFloatToDwordModes(int32_t *out, float *src); +extern void sameWidthPackedConversionSemantics(uint8_t *out, int32_t *ints, float *floats, float *squares32, double *squares64); +extern void packedSingleToDouble(double *out, float *src); +extern void conditionalMoveCodes(uint64_t *out, uint64_t *src); +extern void fma3Semantics(uint8_t *out, double *a64, double *b64, double *c64, float *a32, float *b32, float *c32); +extern void binaryFloatingSemantics(uint8_t *out, double *a64, double *b64, float *a32, float *b32); +extern void horizontalFloatingSemantics(uint8_t *out, float *a32, float *b32, double *a64, double *b64); + +static uint16_t load16(const uint8_t *p) { + return (uint16_t)p[0] | (uint16_t)p[1] << 8; +} +static uint32_t load32(const uint8_t *p) { + return (uint32_t)load16(p) | (uint32_t)load16(p + 2) << 16; +} +static uint64_t load64(const uint8_t *p) { + return (uint64_t)load32(p) | (uint64_t)load32(p + 4) << 32; +} +static float loadf32(const uint8_t *p) { + union { uint32_t bits; float value; } converted = {load32(p)}; + return converted.value; +} +static double loadf64(const uint8_t *p) { + union { uint64_t bits; double value; } converted = {load64(p)}; + return converted.value; +} static uint32_t shld32(uint32_t src, uint32_t dst, uint32_t count) { count &= 31; @@ -196,6 +595,77 @@ static uint64_t shrd64(uint64_t src, uint64_t dst, uint64_t count) { count &= 63; return count == 0 ? dst : (dst >> count) | (src << (64 - count)); } +static uint64_t rol(uint64_t value, unsigned bits, uint64_t count) { + uint64_t mask = bits == 64 ? UINT64_MAX : (UINT64_C(1) << bits) - 1; + count %= bits; + value &= mask; + return count == 0 ? value : ((value << count) | (value >> (bits - count))) & mask; +} +static uint64_t ror(uint64_t value, unsigned bits, uint64_t count) { + return rol(value, bits, bits - count % bits); +} +static uint64_t replace_low(uint64_t value, uint64_t low, unsigned bits) { + uint64_t mask = (UINT64_C(1) << bits) - 1; + return (value & ~mask) | (low & mask); +} + +static uint64_t reference_scalar_add_sub(int add, unsigned bits, uint64_t value, uint64_t source, + int register_destination, uint64_t *flags) { + uint64_t mask = bits == 64 ? UINT64_MAX : (UINT64_C(1) << bits) - 1; + uint64_t destination_low = value & mask, source_low = source & mask; + uint64_t result_low = add ? (destination_low + source_low) & mask : (destination_low - source_low) & mask; + uint64_t carry = add ? result_low < destination_low : destination_low < source_low; + uint64_t sign_bit = UINT64_C(1) << (bits - 1); + uint64_t overflow = add + ? ((~(destination_low ^ source_low) & (destination_low ^ result_low) & sign_bit) != 0) + : (((destination_low ^ source_low) & (destination_low ^ result_low) & sign_bit) != 0); + uint8_t low_byte = (uint8_t)result_low; + uint64_t parity = 1; + while (low_byte != 0) { + parity ^= 1; + low_byte &= low_byte - 1; + } + *flags = carry | overflow << 8 | (result_low == 0) << 16 | + ((result_low & sign_bit) != 0) << 24 | parity << 32; + if (bits == 64 || (register_destination && bits == 32)) return result_low; + return (value & ~mask) | result_low; +} + +static uint64_t reference_pdep(uint64_t mask, uint64_t source) { + uint64_t result = 0; + while (mask != 0) { + uint64_t lowest = mask & (0 - mask); + if (source & 1) result |= lowest; + source >>= 1; + mask &= mask - 1; + } + return result; +} + +static uint64_t reference_pext(uint64_t mask, uint64_t source) { + uint64_t result = 0, output_bit = 1; + while (mask != 0) { + uint64_t lowest = mask & (0 - mask); + if (source & lowest) result |= output_bit; + output_bit <<= 1; + mask &= mask - 1; + } + return result; +} + +static uint64_t reference_bit_test_register(int operation, unsigned bits, uint64_t value, uint64_t index, uint64_t *carry) { + uint64_t bit = index & (bits - 1); + *carry = (value >> bit) & 1; + if (operation == 0) return value; + uint64_t mask = UINT64_C(1) << bit; + uint64_t low = value; + if (operation == 1) low ^= mask; + if (operation == 2) low &= ~mask; + if (operation == 3) low |= mask; + if (bits == 16) return (value & ~UINT64_C(0xffff)) | (low & UINT64_C(0xffff)); + if (bits == 32) return (uint32_t)low; + return low; +} int main(void) { uint8_t bytes[4] = {0x10, 0xf0, 0x5a, 0xa0}; @@ -265,6 +735,526 @@ int main(void) { return 50 + i; } } + const uint64_t scalar_value = UINT64_C(0x8123456789abcdef); + const uint64_t word_dst = UINT64_C(0xfedcba9876543210); + for (uint64_t count = 0; count < 16; count++) { + uint64_t out[14] = {0}, want[14] = {0}; + scalarShiftRotateSemantics(out, scalar_value, count); + uint64_t hardware_count = count & 31; + uint64_t byte_logical = hardware_count < 8 ? (uint8_t)scalar_value >> hardware_count : 0; + uint64_t byte_arithmetic = hardware_count < 8 ? (uint8_t)((int8_t)scalar_value >> hardware_count) : UINT8_MAX; + uint64_t word_count = count & 15; + uint16_t shldw = (uint16_t)word_dst, shrdw = (uint16_t)word_dst; + if (word_count != 0) { + shldw = (uint16_t)(((uint16_t)word_dst << word_count) | ((uint16_t)scalar_value >> (16 - word_count))); + shrdw = (uint16_t)(((uint16_t)word_dst >> word_count) | ((uint16_t)scalar_value << (16 - word_count))); + } + want[0] = replace_low(scalar_value, rol(scalar_value, 8, count), 8); + want[1] = replace_low(scalar_value, ror(scalar_value, 8, count), 8); + want[2] = replace_low(scalar_value, byte_arithmetic, 8); + want[3] = replace_low(scalar_value, byte_logical, 8); + want[4] = replace_low(scalar_value, rol(scalar_value, 16, count), 16); + want[5] = replace_low(scalar_value, (uint16_t)((int16_t)scalar_value >> hardware_count), 16); + want[6] = (uint32_t)scalar_value << hardware_count; + want[7] = ror(scalar_value, 64, count); + want[8] = replace_low(scalar_value, byte_logical, 8); + want[9] = replace_low(scalar_value, rol(scalar_value, 16, count), 16); + want[10] = replace_low(word_dst, shldw, 16); + want[11] = replace_low(word_dst, shrdw, 16); + want[12] = replace_low(scalar_value, (uint8_t)scalar_value << 3, 8); + want[13] = (uint32_t)((int32_t)scalar_value >> 3); + for (int i = 0; i < 14; i++) + if (out[i] != want[i]) return 196 + i; + } + const uint64_t inc_values[] = {0, 1, 0x7f, 0xff, 0xffff, 0xffffffff, UINT64_C(0x8123456789abcdef)}; + for (unsigned v = 0; v < sizeof(inc_values) / sizeof(inc_values[0]); v++) { + uint64_t value = inc_values[v], out[12] = {0}; + incDecSemantics(out, value); + uint64_t want[12] = { + replace_low(value, (uint8_t)value + 1, 8), + replace_low(value, (uint8_t)value - 1, 8), + replace_low(value, (uint16_t)value + 1, 16), + replace_low(value, (uint16_t)value - 1, 16), + (uint32_t)value + 1, (uint32_t)value - 1, value + 1, value - 1, + replace_low(value, (uint8_t)value + 1, 8), + replace_low(value, (uint16_t)value - 1, 16), + UINT64_C(0x0000000000010101), UINT64_C(0x0000000101000001), + }; + for (int i = 0; i < 12; i++) + if (out[i] != want[i]) return 220 + i; + } + const uint64_t scalar_add_sub_cases[][2] = { + {0, 0}, {UINT64_MAX, 1}, {0x7f, 1}, {0x7fff, 1}, + {0x7fffffff, 1}, {UINT64_C(0x7fffffffffffffff), 1}, + {UINT64_C(0x8123456789abcdef), UINT64_C(0xfedcba9876543210)}, + }; + const unsigned scalar_add_sub_widths[] = {8, 16, 32, 64}; + for (unsigned v = 0; v < sizeof(scalar_add_sub_cases) / sizeof(scalar_add_sub_cases[0]); v++) { + uint64_t value = scalar_add_sub_cases[v][0], source = scalar_add_sub_cases[v][1]; + uint64_t out[16] = {0}, want[16] = {0}; + scalarAddSubSemantics(out, value, source); + for (unsigned width_index = 0; width_index < 4; width_index++) { + unsigned bits = scalar_add_sub_widths[width_index]; + want[width_index * 4] = reference_scalar_add_sub(1, bits, value, source, 1, &want[width_index * 4 + 1]); + want[width_index * 4 + 2] = reference_scalar_add_sub(0, bits, value, UINT64_MAX, 0, &want[width_index * 4 + 3]); + } + for (int i = 0; i < 16; i++) + if (out[i] != want[i]) return 232 + i; + } + const uint64_t cmpxchg_expected_values[] = { + 0, UINT64_MAX, 0x7f, 0x7fff, 0x7fffffff, + UINT64_C(0x7fffffffffffffff), UINT64_C(0x8123456789abcdef), + }; + const uint64_t cmpxchg_desired = UINT64_C(0xfedcba9876543210); + for (unsigned v = 0; v < sizeof(cmpxchg_expected_values) / sizeof(cmpxchg_expected_values[0]); v++) { + uint64_t expected = cmpxchg_expected_values[v], memory[8] = {0}, initial[8] = {0}; + uint64_t out[24] = {0}, want[24] = {0}; + for (unsigned width_index = 0; width_index < 4; width_index++) { + unsigned bits = scalar_add_sub_widths[width_index]; + uint64_t mask = bits == 64 ? UINT64_MAX : (UINT64_C(1) << bits) - 1; + uint64_t base = UINT64_C(0xa5a5a5a5a5a5a5a5) & ~mask; + memory[width_index * 2] = base | (expected & mask); + memory[width_index * 2 + 1] = base | ((expected ^ (UINT64_C(1) << (bits - 1))) & mask); + initial[width_index * 2] = memory[width_index * 2]; + initial[width_index * 2 + 1] = memory[width_index * 2 + 1]; + } + compareExchangeScalarSemantics(out, memory, expected, cmpxchg_desired); + for (unsigned width_index = 0; width_index < 4; width_index++) { + unsigned bits = scalar_add_sub_widths[width_index]; + uint64_t mask = bits == 64 ? UINT64_MAX : (UINT64_C(1) << bits) - 1; + uint64_t success_initial = initial[width_index * 2]; + uint64_t failure_initial = initial[width_index * 2 + 1]; + unsigned output_index = width_index * 6; + want[output_index] = (success_initial & ~mask) | (cmpxchg_desired & mask); + want[output_index + 1] = expected; + reference_scalar_add_sub(0, bits, success_initial, expected, 1, &want[output_index + 2]); + want[output_index + 3] = failure_initial; + if (bits == 8 || bits == 16) want[output_index + 4] = (expected & ~mask) | (failure_initial & mask); + if (bits == 32) want[output_index + 4] = (uint32_t)failure_initial; + if (bits == 64) want[output_index + 4] = failure_initial; + reference_scalar_add_sub(0, bits, expected, failure_initial, 1, &want[output_index + 5]); + } + for (int i = 0; i < 24; i++) + if (out[i] != want[i]) return 248 + i; + } + const uint64_t cmpxchg_expected_low = UINT64_C(0xaaaaaaaa11223344); + const uint64_t cmpxchg_expected_high = UINT64_C(0xbbbbbbbb55667788); + const uint64_t cmpxchg_desired_low = UINT64_C(0x0123456789abcdef); + const uint64_t cmpxchg_desired_high = UINT64_C(0xfedcba9876543210); + for (int success = 0; success <= 1; success++) { + _Alignas(16) uint64_t memory[4] = {0}, out[9] = {0}, want[9] = {0}; + if (success) { + memory[0] = cmpxchg_expected_low; + memory[1] = cmpxchg_expected_high; + memory[2] = (cmpxchg_expected_low & UINT32_MAX) | (cmpxchg_expected_high & UINT32_MAX) << 32; + } else { + memory[0] = UINT64_C(0x1020304050607080); + memory[1] = UINT64_C(0x90a0b0c0d0e0f001); + memory[2] = UINT64_C(0x8877665544332211); + } + uint64_t old16_low = memory[0], old16_high = memory[1], old8 = memory[2]; + compareExchangePairSemantics(out, memory, cmpxchg_expected_low, cmpxchg_expected_high, + cmpxchg_desired_low, cmpxchg_desired_high); + if (success) { + want[0] = (cmpxchg_desired_low & UINT32_MAX) | (cmpxchg_desired_high & UINT32_MAX) << 32; + want[1] = cmpxchg_expected_low; + want[2] = cmpxchg_expected_high; + want[3] = 1; + want[4] = cmpxchg_desired_low; + want[5] = cmpxchg_desired_high; + want[6] = cmpxchg_expected_low; + want[7] = cmpxchg_expected_high; + want[8] = 1; + } else { + want[0] = old8; + want[1] = (uint32_t)old8; + want[2] = (uint32_t)(old8 >> 32); + want[4] = old16_low; + want[5] = old16_high; + want[6] = old16_low; + want[7] = old16_high; + } + for (int i = 0; i < 9; i++) + if (out[i] != want[i]) return 272 + i; + } + const uint64_t parallel_cases[][2] = { + {0, UINT64_C(0x0123456789abcdef)}, + {UINT64_MAX, UINT64_C(0x0123456789abcdef)}, + {UINT64_C(0xaaaaaaaaaaaaaaaa), UINT64_C(0x0123456789abcdef)}, + {UINT64_C(0x8040201008040201), UINT64_C(0xfedcba9876543210)}, + {UINT64_C(0x8000000100000081), UINT64_MAX}, + }; + for (unsigned v = 0; v < sizeof(parallel_cases) / sizeof(parallel_cases[0]); v++) { + uint64_t mask = parallel_cases[v][0], source = parallel_cases[v][1], out[8] = {0}; + parallelBitSemantics(out, mask, source); + uint64_t mask32 = (uint32_t)mask, source32 = (uint32_t)source; + uint64_t want[8] = { + reference_pdep(mask, source), reference_pdep(mask, source), + reference_pext(mask, source), reference_pext(mask, source), + reference_pdep(mask32, source32), reference_pdep(mask32, source32), + reference_pext(mask32, source32), reference_pext(mask32, source32), + }; + for (int i = 0; i < 8; i++) + if (out[i] != want[i]) return 124; + } + const uint64_t bit_test_value = UINT64_C(0xfedcba9876543210); + const uint64_t bit_test_index = 21; + uint64_t bit_test_out[24] = {0}; + bitTestRegisterSemantics(bit_test_out, bit_test_value, bit_test_index); + const unsigned bit_test_widths[3] = {16, 32, 64}; + for (int width_index = 0; width_index < 3; width_index++) { + unsigned bits = bit_test_widths[width_index]; + for (int operation = 0; operation < 4; operation++) { + uint64_t operand_index = bit_test_index; + if (operation == 0) operand_index = bits - 1; + if (operation == 2) operand_index = 4; + uint64_t carry = 0; + uint64_t result = reference_bit_test_register(operation, bits, bit_test_value, operand_index, &carry); + int output_index = 2 * (width_index * 4 + operation); + if (bit_test_out[output_index] != result || bit_test_out[output_index + 1] != carry) return 125; + } + } + uint64_t bit_test_data[9] = { + UINT64_MAX, UINT64_C(1) << 17, 0, + UINT64_MAX, UINT64_C(1) << 33, 0, + UINT64_MAX, 0, UINT64_C(1) << 1, + }; + uint8_t bit_test_carry[12] = {0}; + bitTestMemorySemantics(bit_test_carry, bit_test_data); + const uint8_t bit_test_want_carry[12] = {1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0}; + const uint64_t bit_test_want_data[9] = { + UINT64_C(0x7fffffffffffffff), 1, 0, + UINT64_C(0x7fffffffffffffff), 1, 0, + UINT64_C(0x7fffffffffffffff), 1, 0, + }; + for (int i = 0; i < 12; i++) + if (bit_test_carry[i] != bit_test_want_carry[i]) return 126; + for (int i = 0; i < 9; i++) + if (bit_test_data[i] != bit_test_want_data[i]) return 127; + int16_t word_madd_a[16] = { + INT16_MIN, INT16_MIN, -30000, -1, 0, 1, 12345, INT16_MAX, + 7, -11, 1000, -2000, 22222, -12345, INT16_MAX, INT16_MAX, + }; + int16_t word_madd_b[16] = { + INT16_MIN, INT16_MIN, -23456, INT16_MAX, -1, INT16_MAX, -2345, INT16_MAX, + -9, 13, -3000, 4000, -11111, 23456, INT16_MAX, INT16_MAX, + }; + int32_t word_madd_out[18] = {0}, word_madd_reference[8] = {0}, word_madd_want[18] = {0}; + for (int i = 0; i < 8; i++) { + int64_t sum = (int64_t)word_madd_a[2*i] * word_madd_b[2*i] + + (int64_t)word_madd_a[2*i+1] * word_madd_b[2*i+1]; + word_madd_reference[i] = (int32_t)(uint32_t)sum; + } + for (int i = 0; i < 2; i++) word_madd_want[i] = word_madd_reference[i]; + for (int i = 0; i < 4; i++) { + word_madd_want[2+i] = word_madd_reference[i]; + word_madd_want[6+i] = word_madd_reference[i]; + } + for (int i = 0; i < 8; i++) word_madd_want[10+i] = word_madd_reference[i]; + packedWordMultiplyAddSemantics(word_madd_out, word_madd_a, word_madd_b); + for (int i = 0; i < 18; i++) + if (word_madd_out[i] != word_madd_want[i]) return 128; + int8_t byte_madd_signed[32] = { + 127, 127, -128, -128, 100, -100, 1, -1, + 64, -64, 11, 12, -13, 14, 15, -16, + 31, -32, 33, -34, 35, -36, 37, -38, + 39, -40, 41, -42, 43, -44, 45, -46, + }; + uint8_t byte_madd_unsigned[32] = { + 255, 255, 255, 255, 200, 3, 255, 128, + 250, 249, 17, 19, 23, 29, 31, 37, + 41, 43, 47, 53, 59, 61, 67, 71, + 73, 79, 83, 89, 97, 101, 103, 107, + }; + int16_t byte_madd_out[32] = {0}, byte_madd_reference[16] = {0}, byte_madd_want[32] = {0}; + for (int i = 0; i < 16; i++) { + int32_t sum = (int32_t)byte_madd_signed[2*i] * byte_madd_unsigned[2*i] + + (int32_t)byte_madd_signed[2*i+1] * byte_madd_unsigned[2*i+1]; + if (sum > INT16_MAX) sum = INT16_MAX; + if (sum < INT16_MIN) sum = INT16_MIN; + byte_madd_reference[i] = (int16_t)sum; + } + for (int i = 0; i < 8; i++) { + byte_madd_want[i] = byte_madd_reference[i]; + byte_madd_want[8+i] = byte_madd_reference[i]; + } + for (int i = 0; i < 16; i++) byte_madd_want[16+i] = byte_madd_reference[i]; + packedUnsignedSignedByteMultiplyAddSemantics(byte_madd_out, byte_madd_signed, byte_madd_unsigned); + for (int i = 0; i < 32; i++) + if (byte_madd_out[i] != byte_madd_want[i]) return 129; + int8_t dot_signed_bytes[64]; + uint8_t dot_unsigned_bytes[64]; + int16_t dot_words_a[32], dot_words_b[32]; + int32_t dot_accumulator[16], dot_out[64] = {0}; + for (int i = 0; i < 64; i++) { + dot_signed_bytes[i] = (i / 4) & 1 ? -128 : 127; + dot_unsigned_bytes[i] = (uint8_t)(255 - (i & 3)); + } + for (int i = 0; i < 32; i++) { + dot_words_a[i] = (i / 2) & 1 ? INT16_MIN : INT16_MAX; + dot_words_b[i] = (i & 1) ? INT16_MAX : INT16_MIN; + } + for (int i = 0; i < 16; i++) { + switch (i & 3) { + case 0: dot_accumulator[i] = INT32_MAX - 10; break; + case 1: dot_accumulator[i] = INT32_MIN + 10; break; + case 2: dot_accumulator[i] = 123456789; break; + default: dot_accumulator[i] = -987654321; break; + } + } + packedDotProductSemantics(dot_out, dot_signed_bytes, dot_unsigned_bytes, dot_words_a, dot_words_b, dot_accumulator); + for (int lane = 0; lane < 16; lane++) { + int64_t byte_sum = dot_accumulator[lane]; + for (int item = 0; item < 4; item++) byte_sum += (int64_t)dot_signed_bytes[4*lane+item] * dot_unsigned_bytes[4*lane+item]; + int64_t byte_sat = byte_sum; + if (byte_sat > INT32_MAX) byte_sat = INT32_MAX; + if (byte_sat < INT32_MIN) byte_sat = INT32_MIN; + int64_t word_sum = dot_accumulator[lane]; + for (int item = 0; item < 2; item++) word_sum += (int64_t)dot_words_a[2*lane+item] * dot_words_b[2*lane+item]; + int64_t word_sat = word_sum; + if (word_sat > INT32_MAX) word_sat = INT32_MAX; + if (word_sat < INT32_MIN) word_sat = INT32_MIN; + if ((uint32_t)dot_out[lane] != (uint32_t)byte_sum) return 930 + lane; + if (dot_out[16+lane] != (int32_t)byte_sat) return 950 + lane; + if ((uint32_t)dot_out[32+lane] != (uint32_t)word_sum) return 970 + lane; + if (dot_out[48+lane] != (int32_t)word_sat) return 990 + lane; + } + uint8_t minmax_a[64], minmax_b[64], minmax_out[1024] = {0}; + for (int i = 0; i < 64; i++) { + minmax_a[i] = (uint8_t)(0x80 + 73*i); + minmax_b[i] = (uint8_t)(0xff - 29*i); + } + packedIntegerMinMaxSemantics(minmax_out, minmax_a, minmax_b); + for (int lane = 0; lane < 64; lane++) { + int8_t a = (int8_t)minmax_a[lane], b = (int8_t)minmax_b[lane]; + if ((int8_t)minmax_out[lane] != (a < b ? a : b)) return 1010 + lane; + if (minmax_out[64+lane] != (minmax_a[lane] < minmax_b[lane] ? minmax_a[lane] : minmax_b[lane])) return 1080 + lane; + if ((int8_t)minmax_out[128+lane] != (a > b ? a : b)) return 1150 + lane; + if (minmax_out[192+lane] != (minmax_a[lane] > minmax_b[lane] ? minmax_a[lane] : minmax_b[lane])) return 1220 + lane; + } + for (int lane = 0; lane < 32; lane++) { + uint16_t au = load16(minmax_a + 2*lane), bu = load16(minmax_b + 2*lane); + int16_t as = (int16_t)au, bs = (int16_t)bu; + if ((int16_t)load16(minmax_out + 256 + 2*lane) != (as < bs ? as : bs)) return 1290 + lane; + if (load16(minmax_out + 320 + 2*lane) != (au < bu ? au : bu)) return 1330 + lane; + if ((int16_t)load16(minmax_out + 384 + 2*lane) != (as > bs ? as : bs)) return 1370 + lane; + if (load16(minmax_out + 448 + 2*lane) != (au > bu ? au : bu)) return 1410 + lane; + } + for (int lane = 0; lane < 16; lane++) { + uint32_t au = load32(minmax_a + 4*lane), bu = load32(minmax_b + 4*lane); + int32_t as = (int32_t)au, bs = (int32_t)bu; + if ((int32_t)load32(minmax_out + 512 + 4*lane) != (as < bs ? as : bs)) return 1450 + lane; + if (load32(minmax_out + 576 + 4*lane) != (au < bu ? au : bu)) return 1470 + lane; + if ((int32_t)load32(minmax_out + 640 + 4*lane) != (as > bs ? as : bs)) return 1490 + lane; + if (load32(minmax_out + 704 + 4*lane) != (au > bu ? au : bu)) return 1510 + lane; + } + for (int lane = 0; lane < 8; lane++) { + uint64_t au = load64(minmax_a + 8*lane), bu = load64(minmax_b + 8*lane); + int64_t as = (int64_t)au, bs = (int64_t)bu; + if ((int64_t)load64(minmax_out + 768 + 8*lane) != (as < bs ? as : bs)) return 1530 + lane; + if (load64(minmax_out + 832 + 8*lane) != (au < bu ? au : bu)) return 1540 + lane; + if ((int64_t)load64(minmax_out + 896 + 8*lane) != (as > bs ? as : bs)) return 1550 + lane; + if (load64(minmax_out + 960 + 8*lane) != (au > bu ? au : bu)) return 1560 + lane; + } + int16_t word_a[8] = {INT16_MIN, INT16_MIN, -30000, -1, 0, 1, 12345, INT16_MAX}; + int16_t word_b[8] = {INT16_MIN, INT16_MAX, -23456, INT16_MAX, -1, INT16_MAX, -2345, INT16_MAX}; + uint16_t word_mul_out[64] = {0}, word_mul_want[64] = {0}; + packedWordMultiplySemantics(word_mul_out, word_a, word_b); + for (int i = 0; i < 8; i++) { + int32_t product = (int32_t)word_a[i] * (int32_t)word_b[i]; + uint32_t unsigned_product = (uint32_t)(uint16_t)word_a[i] * (uint32_t)(uint16_t)word_b[i]; + int32_t rounded = (product + 0x4000) >> 15; + uint16_t values[4] = {(uint16_t)product, (uint16_t)(product >> 16), (uint16_t)(unsigned_product >> 16), (uint16_t)rounded}; + for (int mode = 0; mode < 4; mode++) { + word_mul_want[mode*8+i] = values[mode]; + word_mul_want[(mode+4)*8+i] = values[mode]; + } + } + for (int i = 0; i < 64; i++) + if (word_mul_out[i] != word_mul_want[i]) return 240 + i; + uint32_t shuffle_a[8], shuffle_b[8]; + uint8_t shuffle_out[96] = {0}; + for (int i = 0; i < 8; i++) { + shuffle_a[i] = 0xa0 + i; + shuffle_b[i] = 0xb0 + i; + } + packedFloatShuffleSemantics(shuffle_out, (uint8_t *)shuffle_a, (uint8_t *)shuffle_b); + const uint32_t shuffle_ps[12] = { + 0xb3, 0xb2, 0xa1, 0xa0, + 0xb3, 0xb2, 0xa1, 0xa0, + 0xb7, 0xb6, 0xa5, 0xa4, + }; + for (int i = 0; i < 4; i++) + if (load32(shuffle_out + 4*i) != shuffle_ps[i]) return 310 + i; + if (load64(shuffle_out + 16) != UINT64_C(0x000000b1000000b0) || + load64(shuffle_out + 24) != UINT64_C(0x000000a3000000a2)) return 314; + for (int i = 0; i < 8; i++) + if (load32(shuffle_out + 32 + 4*i) != shuffle_ps[4+i]) return 315 + i; + const uint64_t shuffle_pd[4] = { + UINT64_C(0x000000b1000000b0), UINT64_C(0x000000a3000000a2), + UINT64_C(0x000000b5000000b4), UINT64_C(0x000000a7000000a6), + }; + for (int i = 0; i < 4; i++) + if (load64(shuffle_out + 64 + 8*i) != shuffle_pd[i]) return 323 + i; + uint32_t in_lane_data[8] = {0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107}; + uint32_t in_lane_control[8] = {3, 2, 1, 0, 4, 5, 6, 7}; + uint8_t in_lane_out[144] = {0}; + inLaneFloatingPermuteSemantics(in_lane_out, (uint8_t *)in_lane_data, (uint8_t *)in_lane_control); + for (int lane = 0; lane < 4; lane++) + if (load32(in_lane_out + 4*lane) != in_lane_data[3-lane]) return 324; + for (int lane = 0; lane < 8; lane++) { + uint32_t immediate_value = in_lane_data[(lane/4)*4 + 3-(lane%4)]; + uint32_t variable_value = in_lane_data[(lane/4)*4 + (in_lane_control[lane]&3)]; + if (load32(in_lane_out + 16 + 4*lane) != immediate_value) return 325; + if (load32(in_lane_out + 48 + 4*lane) != variable_value) return 326; + } + for (int lane = 0; lane < 4; lane++) { + uint64_t data_q[4], control_q[4]; + for (int i = 0; i < 4; i++) { + data_q[i] = (uint64_t)in_lane_data[2*i] | (uint64_t)in_lane_data[2*i+1] << 32; + control_q[i] = (uint64_t)in_lane_control[2*i] | (uint64_t)in_lane_control[2*i+1] << 32; + } + uint64_t immediate_value = data_q[(lane/2)*2 + ((0x05 >> lane)&1)]; + uint64_t variable_value = data_q[(lane/2)*2 + ((control_q[lane] >> 1)&1)]; + if (load64(in_lane_out + 80 + 8*lane) != immediate_value) return 327; + if (load64(in_lane_out + 112 + 8*lane) != variable_value) return 328; + } + uint8_t blend_a[32], blend_b[32], blend_out[240] = {0}; + for (int i = 0; i < 32; i++) { + blend_a[i] = (uint8_t)(0x20 + i); + blend_b[i] = (uint8_t)(0xc0 + i); + } + immediatePackedBlendSemantics(blend_out, blend_a, blend_b); + const int blend_offsets[11] = {0, 16, 32, 48, 64, 96, 112, 144, 160, 192, 208}; + const int blend_widths[11] = {16, 16, 16, 16, 32, 16, 32, 16, 32, 16, 32}; + const int blend_lane_bytes[11] = {2, 4, 8, 2, 2, 4, 4, 4, 4, 8, 8}; + for (int block = 0; block < 11; block++) { + for (int i = 0; i < blend_widths[block]; i++) { + int bit = (i / blend_lane_bytes[block]) % 8; + uint8_t want = (0xa5 & (1 << bit)) ? blend_a[i] : blend_b[i]; + if (blend_out[blend_offsets[block] + i] != want) return 327 + block; + } + } + uint8_t unpack_out[384] = {0}; + packedUnpackSemantics(unpack_out, blend_a, blend_b); + const int unpack_offsets[16] = {0,16,32,48,64,80,96,112,128,160,192,224,256,288,320,352}; + const int unpack_widths[16] = {16,16,16,16,16,16,16,16,32,32,32,32,32,32,32,32}; + const int unpack_lane_bytes[16] = {1,1,2,2,4,4,8,8,1,1,2,2,4,4,8,8}; + for (int block = 0; block < 16; block++) { + int output = unpack_offsets[block]; + int high = block & 1; + for (int group = 0; group < unpack_widths[block]; group += 16) { + int lanes_per_group = 16 / unpack_lane_bytes[block]; + int start = high ? lanes_per_group / 2 : 0; + for (int lane = start; lane < start + lanes_per_group / 2; lane++) { + int input = group + lane * unpack_lane_bytes[block]; + for (int byte = 0; byte < unpack_lane_bytes[block]; byte++) { + if (unpack_out[output++] != blend_b[input + byte]) return 338 + block; + } + for (int byte = 0; byte < unpack_lane_bytes[block]; byte++) { + if (unpack_out[output++] != blend_a[input + byte]) return 354 + block; + } + } + } + } + uint64_t permute_data[4] = {0x10, 0x21, 0x32, 0x43}; + uint64_t permute_control[4] = {3, 0, 5, 2}; + uint64_t permute_out[8] = {0}, variable_permute_out[8] = {0}; + const uint64_t permute_immediate[4] = {0x10, 0x32, 0x21, 0x43}; + const uint64_t permute_variable[4] = {0x43, 0x10, 0x21, 0x32}; + qwordPermuteSemantics(permute_out, permute_data); + qwordVariablePermuteSemantics(variable_permute_out, permute_data, permute_control); + for (int block = 0; block < 2; block++) { + for (int lane = 0; lane < 4; lane++) + if (permute_out[4*block+lane] != permute_immediate[lane]) return 370 + block; + } + for (int block = 0; block < 2; block++) { + for (int lane = 0; lane < 4; lane++) + if (variable_permute_out[4*block+lane] != permute_variable[lane]) return 372 + block; + } + uint8_t move_src[64], move_old[64], move_vex_out[128] = {0}, move_mask_out[688] = {0}; + for (int i = 0; i < 64; i++) { + move_src[i] = (uint8_t)(3 + 17*i); + move_old[i] = (uint8_t)(0xf0 - 3*i); + } + packedFloatMoveVEXSemantics(move_vex_out, move_src); + for (int block = 0; block < 4; block++) + for (int i = 0; i < 32; i++) + if (move_vex_out[32*block+i] != move_src[i]) return 374 + block; + packedFloatMoveMaskSemantics(move_mask_out, move_src, move_old); + const int move_offsets[14] = {0,16,32,48,64,80,96,112,144,176,208,240,272,304}; + const int move_widths[14] = {16,16,16,16,16,16,16,32,32,32,32,32,32,64}; + const int move_lane_bytes[14] = {4,4,4,4,8,8,8,4,4,4,8,8,8,4}; + const int move_zero[14] = {0,1,0,0,0,1,0,0,1,0,0,1,0,0}; + for (int block = 0; block < 14; block++) { + for (int i = 0; i < move_widths[block]; i++) { + int active = (0xa55a >> (i / move_lane_bytes[block])) & 1; + uint8_t want = active ? move_src[i] : (move_zero[block] ? 0 : move_old[i]); + if (move_mask_out[move_offsets[block]+i] != want) return 378 + block; + } + } + const int move_z_offsets[5] = {368,432,496,560,624}; + const int move_z_lane_bytes[5] = {4,4,8,8,8}; + const int move_z_zero[5] = {1,0,0,1,0}; + for (int block = 0; block < 5; block++) { + for (int i = 0; i < 64; i++) { + int active = (0xa55a >> (i / move_z_lane_bytes[block])) & 1; + uint8_t want = active ? move_src[i] : (move_z_zero[block] ? 0 : move_old[i]); + if (move_mask_out[move_z_offsets[block]+i] != want) return 392 + block; + } + } + uint8_t extend_src[32] = { + 0x00,0x01,0x7f,0x80,0xff,0x55,0xaa,0x40, + 0xc0,0x11,0xee,0x33,0xcc,0x66,0x99,0x22, + 0xdd,0x44,0xbb,0x77,0x88,0x10,0xf0,0x20, + 0xe0,0x30,0xd0,0x50,0xb0,0x60,0xa0,0x70, + }; + uint8_t extend_vex_out[288] = {0}; + const int extend_input_bits[6] = {8,8,8,16,16,32}; + const int extend_output_bits[6] = {16,32,64,32,64,64}; + packedSignExtendMoveVEXSemantics(extend_vex_out, extend_src); + for (int op = 0; op < 6; op++) { + for (int form = 0; form < 2; form++) { + int width = form ? 32 : 16; + int offset = form ? 96 + 32*op : 16*op; + int lanes = width * 8 / extend_output_bits[op]; + for (int lane = 0; lane < lanes; lane++) { + const uint8_t *p = extend_src + lane * extend_input_bits[op] / 8; + int64_t expected = extend_input_bits[op] == 8 ? (int64_t)(int8_t)p[0] : + extend_input_bits[op] == 16 ? (int64_t)(int16_t)load16(p) : (int64_t)(int32_t)load32(p); + const uint8_t *actual = extend_vex_out + offset + lane * extend_output_bits[op] / 8; + uint64_t actual_bits = extend_output_bits[op] == 16 ? load16(actual) : + extend_output_bits[op] == 32 ? load32(actual) : load64(actual); + uint64_t mask = extend_output_bits[op] == 16 ? UINT64_C(0xffff) : + extend_output_bits[op] == 32 ? UINT64_C(0xffffffff) : UINT64_MAX; + if (actual_bits != ((uint64_t)expected & mask)) return 397 + op; + } + } + } + uint8_t extend_old[64], extend_mask_out[768] = {0}; + for (int i = 0; i < 64; i++) extend_old[i] = (uint8_t)(0xe7 - 5*i); + packedSignExtendMoveMaskSemantics(extend_mask_out, extend_src, extend_old); + for (int op = 0; op < 6; op++) { + int lanes = 512 / extend_output_bits[op]; + for (int zero = 0; zero < 2; zero++) { + int offset = 128*op + 64*zero; + for (int lane = 0; lane < lanes; lane++) { + const uint8_t *input = extend_src + lane * extend_input_bits[op] / 8; + int64_t extended = extend_input_bits[op] == 8 ? (int64_t)(int8_t)input[0] : + extend_input_bits[op] == 16 ? (int64_t)(int16_t)load16(input) : (int64_t)(int32_t)load32(input); + const uint8_t *actual = extend_mask_out + offset + lane * extend_output_bits[op] / 8; + uint64_t actual_bits = extend_output_bits[op] == 16 ? load16(actual) : + extend_output_bits[op] == 32 ? load32(actual) : load64(actual); + const uint8_t *old = extend_old + lane * extend_output_bits[op] / 8; + uint64_t old_bits = extend_output_bits[op] == 16 ? load16(old) : + extend_output_bits[op] == 32 ? load32(old) : load64(old); + uint64_t width_mask = extend_output_bits[op] == 16 ? UINT64_C(0xffff) : + extend_output_bits[op] == 32 ? UINT64_C(0xffffffff) : UINT64_MAX; + uint64_t expected = (UINT64_C(0xa55aa55a) >> lane) & 1 ? (uint64_t)extended & width_mask : (zero ? 0 : old_bits); + if (actual_bits != expected) return 403 + op; + } + } + } uint8_t a[16], b[16], vector_out[160] = {0}; const uint8_t or_mask[16] = { 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, @@ -310,6 +1300,316 @@ int main(void) { packedArithmeticShift32(packed_out, packed_src); for (int i = 0; i < 8; i++) if (packed_out[i] != packed_want[i]) return 80 + i; + + uint8_t subtract_a[16] = {0x7f, 0x80, 0x64, 0x9c, 0x32, 0xce, 0x00, 0x01, 0xff, 0x00, 0x34, 0x12, 0x00, 0x80, 0xff, 0x7f}; + uint8_t subtract_b[16] = {0xff, 0x01, 0x9c, 0x64, 0xce, 0x32, 0x01, 0x00, 0x01, 0xff, 0x78, 0x56, 0xff, 0x7f, 0x01, 0x80}; + uint8_t subtract_out[80] = {0}; + packedSubtractSemantics(subtract_out, subtract_a, subtract_b); + for (int i = 0; i < 16; i++) { + int signed_value = (int)(int8_t)subtract_a[i] - (int)(int8_t)subtract_b[i]; + if (signed_value < -128) signed_value = -128; + if (signed_value > 127) signed_value = 127; + if (subtract_out[i] != (uint8_t)(int8_t)signed_value) return 190; + int unsigned_value = (int)subtract_a[i] - (int)subtract_b[i]; + if (unsigned_value < 0) unsigned_value = 0; + if (subtract_out[32+i] != (uint8_t)unsigned_value) return 191; + } + for (int i = 0; i < 8; i++) { + int signed_value = (int)(int16_t)load16(subtract_a + 2*i) - (int)(int16_t)load16(subtract_b + 2*i); + if (signed_value < -32768) signed_value = -32768; + if (signed_value > 32767) signed_value = 32767; + if (load16(subtract_out + 16 + 2*i) != (uint16_t)(int16_t)signed_value) return 192; + int unsigned_value = (int)load16(subtract_a + 2*i) - (int)load16(subtract_b + 2*i); + if (unsigned_value < 0) unsigned_value = 0; + if (load16(subtract_out + 48 + 2*i) != (uint16_t)unsigned_value) return 193; + } + for (int i = 0; i < 2; i++) + if (load64(subtract_out + 64 + 8*i) != load64(subtract_a + 8*i) - load64(subtract_b + 8*i)) return 194; + + uint8_t ecosystem_a[16] = { + 0x00, 0x7f, 0x80, 0xff, 0x34, 0x12, 0xfe, 0xff, + 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x00, 0x80, + }; + uint8_t ecosystem_b[16] = { + 0xff, 0x80, 0x7f, 0x00, 0x78, 0x56, 0x02, 0x00, + 0xef, 0xcd, 0xab, 0x90, 0xff, 0xff, 0xff, 0x7f, + }; + uint8_t ecosystem_out[816] = {0}; + expandedEcosystemVectors(ecosystem_out, ecosystem_a, ecosystem_b); + for (int i = 0; i < 16; i++) { + uint8_t min_u = ecosystem_a[i] < ecosystem_b[i] ? ecosystem_a[i] : ecosystem_b[i]; + uint8_t max_u = ecosystem_a[i] > ecosystem_b[i] ? ecosystem_a[i] : ecosystem_b[i]; + int8_t as = (int8_t)ecosystem_a[i], bs = (int8_t)ecosystem_b[i]; + if (ecosystem_out[i] != min_u || ecosystem_out[16+i] != (uint8_t)(as < bs ? as : bs)) return 100; + if (ecosystem_out[96+i] != max_u || ecosystem_out[112+i] != (uint8_t)(as > bs ? as : bs)) return 101; + } + for (int i = 0; i < 8; i++) { + uint16_t au = load16(ecosystem_a + 2*i), bu = load16(ecosystem_b + 2*i); + int16_t as = (int16_t)au, bs = (int16_t)bu; + if (load16(ecosystem_out + 32 + 2*i) != (au < bu ? au : bu)) return 102; + if ((int16_t)load16(ecosystem_out + 48 + 2*i) != (as < bs ? as : bs)) return 103; + if (load16(ecosystem_out + 128 + 2*i) != (au > bu ? au : bu)) return 104; + if ((int16_t)load16(ecosystem_out + 144 + 2*i) != (as > bs ? as : bs)) return 105; + } + for (int i = 0; i < 4; i++) { + uint32_t au = load32(ecosystem_a + 4*i), bu = load32(ecosystem_b + 4*i); + int32_t as = (int32_t)au, bs = (int32_t)bu; + if (load32(ecosystem_out + 64 + 4*i) != (au < bu ? au : bu)) return 106; + if ((int32_t)load32(ecosystem_out + 80 + 4*i) != (as < bs ? as : bs)) return 107; + if (load32(ecosystem_out + 160 + 4*i) != (au > bu ? au : bu)) return 108; + if ((int32_t)load32(ecosystem_out + 176 + 4*i) != (as > bs ? as : bs)) return 109; + } + for (int i = 0; i < 2; i++) + if (load64(ecosystem_out + 192 + 8*i) != (load64(ecosystem_a + 8*i) << 13)) return 110; + for (int i = 208; i < 224; i++) + if (ecosystem_out[i] != 0) return 111; + if (load64(ecosystem_out + 224) != 0x0123456789abcdefULL) return 112; + if (load64(ecosystem_out + 232) != 0x0000000089abcdefULL) return 113; + if (load32(ecosystem_out + 240) != 0x89abcdefU) return 119; + for (int i = 244; i < 256; i++) if (ecosystem_out[i] != 0) return 121; + if (load64(ecosystem_out + 256) != load64(ecosystem_a)) return 122; + if (load64(ecosystem_out + 264) != 0) return 123; + for (int i = 0; i < 16; i++) + if (ecosystem_out[272+i] != (uint8_t)(((uint16_t)ecosystem_a[i] + ecosystem_b[i] + 1) >> 1)) return 124; + for (int i = 0; i < 8; i++) + if (load16(ecosystem_out + 288 + 2*i) != (uint16_t)(((uint32_t)load16(ecosystem_a + 2*i) + load16(ecosystem_b + 2*i) + 1) >> 1)) return 125; + for (int i = 0; i < 16; i++) + if (ecosystem_out[304+i] != ((int8_t)ecosystem_a[i] > (int8_t)ecosystem_b[i] ? 0xff : 0)) return 126; + for (int i = 0; i < 8; i++) + if (load16(ecosystem_out + 320 + 2*i) != ((int16_t)load16(ecosystem_a + 2*i) > (int16_t)load16(ecosystem_b + 2*i) ? 0xffff : 0)) return 127; + for (int i = 0; i < 4; i++) + if (load32(ecosystem_out + 336 + 4*i) != ((int32_t)load32(ecosystem_a + 4*i) > (int32_t)load32(ecosystem_b + 4*i) ? 0xffffffffU : 0)) return 128; + for (int i = 0; i < 2; i++) + if (load64(ecosystem_out + 352 + 8*i) != ((int64_t)load64(ecosystem_a + 8*i) > (int64_t)load64(ecosystem_b + 8*i) ? ~0ULL : 0)) return 129; + for (int i = 0; i < 8; i++) { + int16_t value = (int16_t)load16(ecosystem_a + 2*i); + if ((int16_t)load16(ecosystem_out + 368 + 2*i) != (int16_t)(value >> 3)) return 150; + if ((int16_t)load16(ecosystem_out + 384 + 2*i) != (int16_t)(value >> 15)) return 151; + } + for (int i = 0; i < 2; i++) { + if (load32(ecosystem_out + 400 + 8*i) != load32(ecosystem_a + 4*i)) return 152; + if (load32(ecosystem_out + 404 + 8*i) != load32(ecosystem_b + 4*i)) return 153; + if (load32(ecosystem_out + 416 + 8*i) != load32(ecosystem_a + 8 + 4*i)) return 154; + if (load32(ecosystem_out + 420 + 8*i) != load32(ecosystem_b + 8 + 4*i)) return 155; + } + if (load64(ecosystem_out + 432) != load64(ecosystem_a) || load64(ecosystem_out + 440) != load64(ecosystem_b)) return 156; + if (load64(ecosystem_out + 448) != load64(ecosystem_a + 8) || load64(ecosystem_out + 456) != load64(ecosystem_b + 8)) return 157; + for (int i = 0; i < 8; i++) if (load16(ecosystem_out + 464 + 2*i) != ecosystem_a[i]) return 158; + for (int i = 0; i < 4; i++) if (load32(ecosystem_out + 480 + 4*i) != ecosystem_a[i]) return 159; + for (int i = 0; i < 2; i++) if (load64(ecosystem_out + 496 + 8*i) != ecosystem_a[i]) return 160; + for (int i = 0; i < 4; i++) if (load32(ecosystem_out + 512 + 4*i) != load16(ecosystem_a + 2*i)) return 161; + for (int i = 0; i < 2; i++) if (load64(ecosystem_out + 528 + 8*i) != load16(ecosystem_a + 2*i)) return 162; + for (int i = 0; i < 2; i++) if (load64(ecosystem_out + 544 + 8*i) != load32(ecosystem_a + 4*i)) return 163; + for (int i = 0; i < 2; i++) { + if (load32(ecosystem_out + 560 + 4*i) != load32(ecosystem_a + 8*i) + load32(ecosystem_a + 8*i + 4)) return 164; + if (load32(ecosystem_out + 568 + 4*i) != load32(ecosystem_b + 8*i) + load32(ecosystem_b + 8*i + 4)) return 165; + if (load32(ecosystem_out + 608 + 4*i) != load32(ecosystem_a + 8*i) - load32(ecosystem_a + 8*i + 4)) return 166; + if (load32(ecosystem_out + 616 + 4*i) != load32(ecosystem_b + 8*i) - load32(ecosystem_b + 8*i + 4)) return 167; + } + for (int i = 0; i < 4; i++) { + int32_t aa = (int16_t)load16(ecosystem_a + 4*i) + (int16_t)load16(ecosystem_a + 4*i + 2); + int32_t ba = (int16_t)load16(ecosystem_b + 4*i) + (int16_t)load16(ecosystem_b + 4*i + 2); + int32_t as = (int16_t)load16(ecosystem_a + 4*i) - (int16_t)load16(ecosystem_a + 4*i + 2); + int32_t bs = (int16_t)load16(ecosystem_b + 4*i) - (int16_t)load16(ecosystem_b + 4*i + 2); + if (aa < -32768) aa = -32768; if (aa > 32767) aa = 32767; + if (ba < -32768) ba = -32768; if (ba > 32767) ba = 32767; + if (as < -32768) as = -32768; if (as > 32767) as = 32767; + if (bs < -32768) bs = -32768; if (bs > 32767) bs = 32767; + if ((int16_t)load16(ecosystem_out + 576 + 2*i) != (int16_t)aa) return 168; + if ((int16_t)load16(ecosystem_out + 584 + 2*i) != (int16_t)ba) return 169; + if (load16(ecosystem_out + 592 + 2*i) != (uint16_t)(load16(ecosystem_a + 4*i) + load16(ecosystem_a + 4*i + 2))) return 170; + if (load16(ecosystem_out + 600 + 2*i) != (uint16_t)(load16(ecosystem_b + 4*i) + load16(ecosystem_b + 4*i + 2))) return 171; + if ((int16_t)load16(ecosystem_out + 624 + 2*i) != (int16_t)as) return 172; + if ((int16_t)load16(ecosystem_out + 632 + 2*i) != (int16_t)bs) return 173; + if (load16(ecosystem_out + 640 + 2*i) != (uint16_t)(load16(ecosystem_a + 4*i) - load16(ecosystem_a + 4*i + 2))) return 174; + if (load16(ecosystem_out + 648 + 2*i) != (uint16_t)(load16(ecosystem_b + 4*i) - load16(ecosystem_b + 4*i + 2))) return 175; + } + uint16_t minimum = 0xffff, minimum_index = 0; + for (int i = 0; i < 8; i++) { + uint16_t value = load16(ecosystem_a + 2*i); + if (value < minimum) { minimum = value; minimum_index = (uint16_t)i; } + } + if (load16(ecosystem_out + 656) != minimum || load16(ecosystem_out + 658) != minimum_index) return 176; + for (int i = 660; i < 672; i++) if (ecosystem_out[i] != 0) return 177; + for (int block = 0; block < 2; block++) + for (int i = 0; i < 16; i++) { + uint8_t want_masked = (int8_t)ecosystem_b[i] < 0 ? ecosystem_a[i] : ecosystem_b[i]; + if (ecosystem_out[672 + 16*block + i] != want_masked) return 178 + block; + } + for (int i = 0; i < 8; i++) { + if (load16(ecosystem_out + 704 + 2*i) != (uint16_t)(load16(ecosystem_a + 2*i) << 3)) return 180; + if (load16(ecosystem_out + 752 + 2*i) != (uint16_t)(load16(ecosystem_a + 2*i) >> 3)) return 181; + } + for (int i = 0; i < 4; i++) { + if (load32(ecosystem_out + 720 + 4*i) != load32(ecosystem_a + 4*i) << 3) return 182; + if (load32(ecosystem_out + 768 + 4*i) != load32(ecosystem_a + 4*i) >> 3) return 183; + } + for (int i = 0; i < 2; i++) { + if (load64(ecosystem_out + 736 + 8*i) != load64(ecosystem_a + 8*i) << 3) return 184; + if (load64(ecosystem_out + 784 + 8*i) != load64(ecosystem_a + 8*i) >> 3) return 185; + } + if (load64(ecosystem_out + 800) != 3 || load64(ecosystem_out + 808) != 0) return 186; + uint64_t parity0 = parityBranches(0x00); + if (parity0 != 1) return 120 + (int)parity0; + if (parityBranches(0x03) != 1) return 114; + if (parityBranches(0x01) != 2) return 115; + if (parityBranches(0x07) != 2) return 116; + volatile double zero = 0.0; + if (unorderedBranch(1.25) != 0) return 117; + if (unorderedBranch(zero / zero) != 1) return 118; + float conversion_src[4] = {1.5f, -1.5f, 2.75f, -2.75f}; + int32_t conversion_out[20] = {0}; + int32_t conversion_want[20] = { + 2, -2, 3, -3, + 1, -2, 2, -3, + 2, -1, 3, -2, + 1, -1, 2, -2, + 1, -1, 2, -2, + }; + packedFloatToDwordModes(conversion_out, conversion_src); + for (int i = 0; i < 20; i++) + if (conversion_out[i] != conversion_want[i]) return 130 + i; + int32_t same_width_ints[16]; + float same_width_floats[16] = { + 1.5f, -1.5f, 2.75f, -2.75f, 0.5f, -0.5f, 3.25f, -3.25f, + 4.5f, -4.5f, 5.75f, -5.75f, 6.5f, -6.5f, 7.25f, -7.25f, + }; + float same_width_squares32[16]; + double same_width_squares64[8]; + for (int i = 0; i < 16; i++) { + same_width_ints[i] = i - 8; + same_width_squares32[i] = (float)((i + 1) * (i + 1)); + } + for (int i = 0; i < 8; i++) same_width_squares64[i] = (double)((i + 1) * (i + 1)); + int32_t same_width_nearest[16] = {2,-2,3,-3,0,0,3,-3,4,-4,6,-6,6,-6,7,-7}; + int32_t same_width_trunc[16] = {1,-1,2,-2,0,0,3,-3,4,-4,5,-5,6,-6,7,-7}; + int32_t same_width_down[16] = {1,-2,2,-3,0,-1,3,-4,4,-5,5,-6,6,-7,7,-8}; + int32_t same_width_up[16] = {2,-1,3,-2,1,0,4,-3,5,-4,6,-5,7,-6,8,-7}; + uint8_t same_width_out[576] = {0}; + sameWidthPackedConversionSemantics(same_width_out, same_width_ints, same_width_floats, same_width_squares32, same_width_squares64); + for (int i = 0; i < 16; i++) { + if (loadf32(same_width_out + 4*i) != (float)same_width_ints[i]) return 760 + i; + if ((int32_t)load32(same_width_out + 64 + 4*i) != same_width_nearest[i]) return 780 + i; + if ((int32_t)load32(same_width_out + 128 + 4*i) != same_width_trunc[i]) return 800 + i; + if (loadf32(same_width_out + 192 + 4*i) != (float)(i + 1)) return 820 + i; + if ((int32_t)load32(same_width_out + 320 + 4*i) != same_width_nearest[i]) return 840 + i; + if ((int32_t)load32(same_width_out + 384 + 4*i) != same_width_down[i]) return 860 + i; + if ((int32_t)load32(same_width_out + 448 + 4*i) != same_width_up[i]) return 880 + i; + if ((int32_t)load32(same_width_out + 512 + 4*i) != same_width_trunc[i]) return 900 + i; + } + for (int i = 0; i < 8; i++) + if (loadf64(same_width_out + 256 + 8*i) != (double)(i + 1)) return 920 + i; + double widening_out[4] = {0}; + double widening_want[4] = {1.5, -1.5, 2.75, -2.75}; + packedSingleToDouble(widening_out, conversion_src); + for (int i = 0; i < 4; i++) + if (widening_out[i] != widening_want[i]) return 180 + i; + uint64_t cmov_src[16]; + uint64_t cmov_out[16] = {0}; + for (int i = 0; i < 16; i++) cmov_src[i] = 101 + (uint64_t)i; + conditionalMoveCodes(cmov_out, cmov_src); + int cmov_taken[16] = {1, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1}; + for (int i = 0; i < 16; i++) { + uint64_t want = cmov_taken[i] ? cmov_src[i] : UINT64_MAX; + if (cmov_out[i] != want) return 160 + i; + } + double fma_a64[2] = {2, -3}, fma_b64[2] = {5, 7}, fma_c64[2] = {11, -13}; + float fma_a32[4] = {2, -3, 4, -5}; + float fma_b32[4] = {5, 7, -11, -13}; + float fma_c32[4] = {17, -19, 23, -29}; + uint8_t fma_out[288] = {0}; + fma3Semantics(fma_out, fma_a64, fma_b64, fma_c64, fma_a32, fma_b32, fma_c32); + for (int lane = 0; lane < 2; lane++) { + double a = fma_a64[lane], b = fma_b64[lane], c = fma_c64[lane]; + double want[8] = { + c*a+b, b*c+a, b*a+c, c*a-b, -(b*c)+a, -(b*a)-c, + lane % 2 == 0 ? c*a-b : c*a+b, + lane % 2 == 0 ? b*a+c : b*a-c, + }; + for (int block = 0; block < 8; block++) + if (loadf64(fma_out + 16*block + 8*lane) != want[block]) return 500 + 2*block + lane; + } + for (int lane = 0; lane < 4; lane++) { + float a = fma_a32[lane], b = fma_b32[lane], c = fma_c32[lane]; + float want[6] = { + c*a+b, b*c-a, -(b*a)+c, -(c*a)-b, + lane % 2 == 0 ? b*c-a : b*c+a, + lane % 2 == 0 ? b*a+c : b*a-c, + }; + for (int block = 0; block < 6; block++) + if (loadf32(fma_out + 128 + 16*block + 4*lane) != want[block]) return 520 + 4*block + lane; + } + if (loadf64(fma_out + 224) != fma_c64[0]*fma_a64[0]+fma_b64[0] || + loadf64(fma_out + 232) != fma_c64[1]) return 550; + if (loadf64(fma_out + 240) != fma_b64[0]*fma_c64[0]-fma_a64[0] || + loadf64(fma_out + 248) != fma_c64[1]) return 551; + if (loadf32(fma_out + 256) != -(fma_b32[0]*fma_a32[0])+fma_c32[0] || + loadf32(fma_out + 260) != fma_c32[1] || + loadf32(fma_out + 264) != fma_c32[2] || + loadf32(fma_out + 268) != fma_c32[3]) return 552; + if (loadf32(fma_out + 272) != -(fma_c32[0]*fma_a32[0])-fma_b32[0] || + loadf32(fma_out + 276) != fma_c32[1] || + loadf32(fma_out + 280) != fma_c32[2] || + loadf32(fma_out + 284) != fma_c32[3]) return 553; + double binary_a64[2] = {2, -3}, binary_b64[2] = {20, 30}; + float binary_a32[4] = {2, -3, 4, -5}, binary_b32[4] = {20, 30, -40, -50}; + double binary_want64[6][2] = { + {22, 27}, {18, 33}, {40, -90}, {10, -10}, {20, 30}, {2, -3}, + }; + float binary_want32[6][4] = { + {22, 27, -36, -55}, + {18, 33, -44, -45}, + {40, -90, -160, 250}, + {10, -10, -10, 10}, + {20, 30, 4, -5}, + {2, -3, -40, -50}, + }; + uint8_t binary_out[384] = {0}; + binaryFloatingSemantics(binary_out, binary_a64, binary_b64, binary_a32, binary_b32); + for (int operation = 0; operation < 6; operation++) { + for (int lane = 0; lane < 2; lane++) + if (loadf64(binary_out + 16*operation + 8*lane) != binary_want64[operation][lane]) return 600 + 2*operation + lane; + for (int lane = 0; lane < 4; lane++) + if (loadf32(binary_out + 96 + 16*operation + 4*lane) != binary_want32[operation][lane]) return 620 + 4*operation + lane; + for (int lane = 0; lane < 2; lane++) { + double want = lane == 0 ? binary_want64[operation][0] : binary_b64[lane]; + if (loadf64(binary_out + 192 + 16*operation + 8*lane) != want) return 650 + 2*operation + lane; + } + for (int lane = 0; lane < 4; lane++) { + float want = lane == 0 ? binary_want32[operation][0] : binary_b32[lane]; + if (loadf32(binary_out + 288 + 16*operation + 4*lane) != want) return 670 + 4*operation + lane; + } + } + float horizontal_a32[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + float horizontal_b32[8] = {10, 20, 30, 40, 50, 60, 70, 80}; + double horizontal_a64[4] = {1, 2, 3, 4}; + double horizontal_b64[4] = {10, 20, 30, 40}; + float horizontal_want32[4][8] = { + {30, 70, 3, 7, 110, 150, 11, 15}, + {-10, -10, -1, -1, -10, -10, -1, -1}, + {30, 70, 3, 7, 0, 0, 0, 0}, + {-10, -10, -1, -1, 0, 0, 0, 0}, + }; + double horizontal_want64[4][4] = { + {30, 3, 70, 7}, + {-10, -1, -10, -1}, + {30, 3, 0, 0}, + {-10, -1, 0, 0}, + }; + uint8_t horizontal_out[192] = {0}; + horizontalFloatingSemantics(horizontal_out, horizontal_a32, horizontal_b32, horizontal_a64, horizontal_b64); + for (int block = 0; block < 2; block++) + for (int lane = 0; lane < 8; lane++) + if (loadf32(horizontal_out + 32*block + 4*lane) != horizontal_want32[block][lane]) return 700 + 8*block + lane; + for (int block = 0; block < 2; block++) + for (int lane = 0; lane < 4; lane++) + if (loadf64(horizontal_out + 64 + 32*block + 8*lane) != horizontal_want64[block][lane]) return 720 + 4*block + lane; + for (int block = 0; block < 2; block++) + for (int lane = 0; lane < 4; lane++) + if (loadf32(horizontal_out + 128 + 16*block + 4*lane) != horizontal_want32[2+block][lane]) return 740 + 4*block + lane; + for (int block = 0; block < 2; block++) + for (int lane = 0; lane < 2; lane++) + if (loadf64(horizontal_out + 160 + 16*block + 8*lane) != horizontal_want64[2+block][lane]) return 750 + 2*block + lane; return 0; } ` diff --git a/amd64_ctx.go b/amd64_ctx.go index 03abb4ab..e6d2e9ea 100644 --- a/amd64_ctx.go +++ b/amd64_ctx.go @@ -53,6 +53,7 @@ type amd64Ctx struct { flagsZSlot string flagsSltSlot string // signed negative-style bit for J{L,LE,G,GE}-like checks flagsCFSlot string // carry/borrow style bit for J{B,BE,A,AE,NC,C}-like checks + flagsPFSlot string // parity bit for J{P,PE,PS,NP,PO,PC}-like checks flagsOFSlot string // overflow-style bit used by ADOX carry chain modeling flagsIDSlot string // CPUID availability bit preserved by PUSHFL/POPFL flagsWritten bool @@ -67,6 +68,7 @@ type amd64Ctx struct { classicBias int64 fpParams map[int64]FrameSlot // off(FP) -> slot + fpParamAlloca map[int64]string // off(FP) -> mutable parameter shadow fpResults []FrameSlot fpResAllocaOff map[int64]string // off(FP) -> alloca fpResAllocaIdx map[int]string // result index -> alloca @@ -99,6 +101,7 @@ func newX86Ctx(b *strings.Builder, fn Func, sig FuncSig, resolve func(string) st usedKRegs: map[int]bool{}, kRegSlot: map[int]string{}, fpParams: map[int64]FrameSlot{}, + fpParamAlloca: map[int64]string{}, fpResAllocaOff: map[int64]string{}, fpResAllocaIdx: map[int]string{}, fpResWritten: map[int]bool{}, @@ -119,7 +122,7 @@ func newX86Ctx(b *strings.Builder, fn Func, sig FuncSig, resolve func(string) st } func (c *amd64Ctx) useHardwareX87() bool { - return c.goarch == "386" && c.x87Mode != X87Software + return c.x87Mode != X87Software } func (c *amd64Ctx) emitSourceComment(ins Instr) { @@ -207,6 +210,10 @@ func (c *amd64Ctx) scanUsedRegs() { if r == "" { return } + // Byte aliases are read and written through their containing GP slot. + if base, _, ok := amd64ByteAlias(r); ok { + r = base + } if idx, ok := amd64ParseXReg(r); ok { c.usedXRegs[idx] = true return @@ -223,7 +230,7 @@ func (c *amd64Ctx) scanUsedRegs() { c.usedKRegs[idx] = true return } - if _, ok := amd64ParseX87Reg(r); ok && c.goarch == "386" { + if _, ok := amd64ParseX87Reg(r); ok { c.usedX87 = true return } @@ -248,21 +255,80 @@ func (c *amd64Ctx) scanUsedRegs() { for _, blk := range c.blocks { for _, ins := range blk.instrs { op := strings.ToUpper(string(ins.Op)) - if c.goarch == "386" && isX87Op(Op(op)) { + if dot := strings.IndexByte(op, '.'); dot >= 0 { + op = op[:dot] + } + if isX87Op(Op(op)) { c.usedX87 = true if op == "FMOVVP" { c.usesX87Convert = true } } + if op == "LAHF" || op == "SAHF" { + markReg(AX) + } + if spec, ok := amd64ImplicitSystemSpecs[Op(op)]; ok { + registers := spec.inputs | spec.outputs + if registers&amd64ImplicitAX != 0 { + markReg(AX) + } + if registers&amd64ImplicitCX != 0 { + markReg(CX) + } + if registers&amd64ImplicitDX != 0 { + markReg(DX) + } + } + if spec, ok := amd64RTMSpecs[Op(op)]; ok && spec.outputAX { + markReg(AX) + } + if spec, ok := amd64SystemTransferSpecs[Op(op)]; ok { + if spec.inputs&amd64SystemTransferCX != 0 { + markReg(CX) + } + if spec.inputs&amd64SystemTransferDX != 0 { + markReg(DX) + } + if c.goarch != "386" && spec.inputs&amd64SystemTransferR11 != 0 { + markReg(Reg("R11")) + } + } + if _, ok := amd64LeaveSpecs[Op(op)]; ok { + markReg(BP) + markReg(SP) + } + if op == "XLAT" { + markReg(AX) + markReg(BX) + } if c.goarch == "386" { switch op { - case "PUSHL", "POPL", "PUSHFL", "POPFL", "PUSHAL", "POPAL", "ADJSP": + case "PUSHW", "POPW", "PUSHFW", "POPFW", "PUSHL", "POPL", "PUSHFL", "POPFL", "PUSHAL", "POPAL", "ADJSP": markReg(SP) } } for _, arg := range ins.Args { markOp(arg) } + if _, fourSource := amd64FourSourceSpecs[Op(op)]; fourSource && len(ins.Args) >= 2 && ins.Args[1].Kind == OpRegList && len(ins.Args[1].RegList) != 0 { + first := ins.Args[1].RegList[0] + if index, ok := amd64ParseXReg(first); ok { + base := index &^ 3 + for register := base; register < base+4; register++ { + markReg(Reg(fmt.Sprintf("X%d", register))) + } + } else if index, ok := amd64ParseZReg(first); ok { + base := index &^ 3 + for register := base; register < base+4; register++ { + markReg(Reg(fmt.Sprintf("Z%d", register))) + } + } + } + if len(ins.Args) == 1 && ins.Args[0].Kind == OpReg { + if spec, ok := x86UnaryYmbSpecs[Op(op)]; ok { + markReg(amd64YmbEffectiveRegister(ins.Args[0].Reg, spec.bits)) + } + } } } @@ -311,11 +377,15 @@ func (c *amd64Ctx) emitEntryAllocas() error { fmt.Fprintf(c.b, " %s = alloca i64\n", name) fmt.Fprintf(c.b, " store i64 0, ptr %s\n", name) } - if spSlot, ok := c.regSlot[SP]; ok && c.goarch == "386" { + if spSlot, ok := c.regSlot[SP]; ok { minOff, maxOff := c.stackOffsetRange() - movement, err := c.stackMovementBudget() - if err != nil { - return err + var movement int64 + if c.goarch == "386" { + var err error + movement, err = c.stackMovementBudget() + if err != nil { + return err + } } minOff -= movement maxOff += movement @@ -399,13 +469,13 @@ func (c *amd64Ctx) emitEntryAllocas() error { fmt.Fprintf(c.b, " %s = alloca i64\n", c.x87IntegerSlot) } } - c.flagsZSlot = "%flags_z" c.flagsSltSlot = "%flags_slt" c.flagsCFSlot = "%flags_cf" + c.flagsPFSlot = "%flags_pf" c.flagsOFSlot = "%flags_of" + c.directionSlot = "%direction_backward" if c.goarch == "386" { - c.directionSlot = "%direction_backward" c.flagsIDSlot = "%flags_id" } fmt.Fprintf(c.b, " %s = alloca i1\n", c.flagsZSlot) @@ -414,6 +484,8 @@ func (c *amd64Ctx) emitEntryAllocas() error { fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsSltSlot) fmt.Fprintf(c.b, " %s = alloca i1\n", c.flagsCFSlot) fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsCFSlot) + fmt.Fprintf(c.b, " %s = alloca i1\n", c.flagsPFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsPFSlot) fmt.Fprintf(c.b, " %s = alloca i1\n", c.flagsOFSlot) fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) if c.flagsIDSlot != "" { @@ -443,6 +515,25 @@ func (c *amd64Ctx) emitEntryAllocas() error { return err } } else { + // Named FP parameters have mutable frame-slot semantics in Go assembly. + // Keep shadow storage even though LLVM function arguments are SSA values; + // assembly kernels commonly advance slice pointers by writing base+off(FP) + // and reading the updated value in a later loop iteration. + for _, slot := range c.sig.Frame.Params { + if slot.Index < 0 || slot.Index >= len(c.sig.Args) { + return fmt.Errorf("FP frame slot: invalid arg index %d at +%d(FP)", slot.Index, slot.Offset) + } + name := amd64FPParamSlotName(slot.Offset) + c.fpParamAlloca[slot.Offset] = name + value := fmt.Sprintf("%%arg%d", slot.Index) + if fields := frameSlotFields(slot); len(fields) != 0 { + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %s%s\n", extracted, c.sig.Args[slot.Index], value, frameSlotExtractSuffix(slot)) + value = "%" + extracted + } + fmt.Fprintf(c.b, " %s = alloca %s\n", name, slot.Type) + fmt.Fprintf(c.b, " store %s %s, ptr %s\n", slot.Type, value, name) + } for _, r := range c.fpResults { name := fmt.Sprintf("%%fp_ret_%d", r.Index) c.fpResAllocaIdx[r.Index] = name @@ -523,6 +614,13 @@ func (c *amd64Ctx) emitEntryAllocas() error { return nil } +func amd64FPParamSlotName(off int64) string { + if off < 0 { + return fmt.Sprintf("%%fp_arg_n%d", -off) + } + return fmt.Sprintf("%%fp_arg_%d", off) +} + func x86FrameTypeSize(ty LLVMType) int64 { switch ty { case I1, I8: @@ -589,9 +687,9 @@ func (c *amd64Ctx) emit386ClassicFrame() error { return fmt.Errorf("FP frame slot: invalid arg index %d at +%d(FP)", slot.Index, slot.Offset) } value := fmt.Sprintf("%%arg%d", slot.Index) - if slot.Field >= 0 { + if fields := frameSlotFields(slot); len(fields) != 0 { extracted := c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", extracted, c.sig.Args[slot.Index], value, slot.Field) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %s%s\n", extracted, c.sig.Args[slot.Index], value, frameSlotExtractSuffix(slot)) value = "%" + extracted } fmt.Fprintf(c.b, " store %s %s, ptr %s, align 1\n", slot.Type, value, c.classicFramePtr(slot.Offset)) @@ -646,6 +744,10 @@ func (c *amd64Ctx) stackMovementBudget() (int64, error) { if err := add(4, ins); err != nil { return 0, err } + case "PUSHW", "POPW", "PUSHFW", "POPFW": + if err := add(2, ins); err != nil { + return 0, err + } case "PUSHAL", "POPAL": if err := add(32, ins); err != nil { return 0, err @@ -662,6 +764,26 @@ func (c *amd64Ctx) stackMovementBudget() (int64, error) { return 0, err } } + case "INCL", "DECL": + if is386SPDestination(ins) { + if err := add(1, ins); err != nil { + return 0, err + } + } + case "INCW", "DECW": + if is386SPDestination(ins) { + // A low-word wrap can move the modeled SP by as much as 65535. + if err := add(65535, ins); err != nil { + return 0, err + } + } + case "ADDW", "SUBW": + if is386SPDestination(ins) { + // A low-word update can move the modeled SP by up to 65535. + if err := add(65535, ins); err != nil { + return 0, err + } + } case "ANDL": if movement, ok := bounded386SPAndMovement(ins); ok { if err := add(movement, ins); err != nil { @@ -707,15 +829,65 @@ func bounded386SPAndMovement(ins Instr) (int64, bool) { } func models386SPWrite(ins Instr) bool { + op := strings.ToUpper(string(ins.Op)) + if dot := strings.IndexByte(op, '.'); dot >= 0 { + op = op[:dot] + } + if op == "MOVQ" && len(ins.Args) == 2 && ins.Args[1].Kind == OpReg && ins.Args[1].Reg == SP && ins.Args[0].Kind == OpReg { + class, _, special := x86MachineRegister(ins.Args[0].Reg) + return special && (class == "cr" || class == "dr") + } + if len(ins.Args) == 1 && ins.Args[0].Kind == OpReg { + if spec, ok := x86UnaryYmbSpecs[Op(op)]; ok && spec.bits != 64 { + return amd64YmbEffectiveRegister(ins.Args[0].Reg, spec.bits) == SP + } + } if !is386SPDestination(ins) { return false } - switch strings.ToUpper(string(ins.Op)) { - case "MOVL", "ADDL", "SUBL", "LEAL", "POPL": + switch op { + case "MOVL", "ADDW", "SUBW", "ADCW", "SBBW", "ADDL", "SUBL", "ADCL", "SBBL", "ADCXL", "ADOXL", "LEAW", "LEAL", "POPW", "POPL", + "CRC32B", "CRC32W", "CRC32L", + "CMPXCHGW", "CMPXCHGL", + "POPCNTW", "POPCNTL", "TZCNTW", "TZCNTL", "LZCNTW", "LZCNTL", "PMOVMSKB", "VPMOVMSKB", + "BEXTRL", "BEXTRQ", "BZHIL", "BZHIQ", "BLSIL", "BLSIQ", "BLSMSKL", "BLSMSKQ", "BLSRL", "BLSRQ", + "ANDNL", "ANDNQ", + "RORXL", "RORXQ", + "PDEPL", "PDEPQ", "PEXTL", "PEXTQ", + "CVTSS2SL", "CVTSD2SL", "CVTTSS2SL", "CVTTSD2SL", + "VCVTSS2SI", "VCVTSD2SI", "VCVTTSS2SI", "VCVTTSD2SI", + "VCVTSS2USIL", "VCVTSD2USIL", "VCVTTSS2USIL", "VCVTTSD2USIL": // These are the direct SP forms used by the official 386 corpus. MOVL // and non-SP LEAL rebase to an explicitly supplied stack context; // arithmetic and SP-relative LEAL retain the current stack model. return true + case "RDPID": + return len(ins.Args) == 1 && ins.Args[0].Kind == OpReg && ins.Args[0].Reg == SP + case "RCLW", "RCLL", "RCRW", "RCRL", "ROLW", "ROLL", "RORW", "RORL", "SARW", "SARL", + "SALW", "SALL", "SHLW", "SHLL", "SHRW", "SHRL": + return true + case "INCW", "DECW", "INCL", "DECL": + return true + case "BTCW", "BTCL", "BTRW", "BTRL", "BTSW", "BTSL": + return true + case "SLDTW", "SLDTL", "SMSWW", "SMSWL", "STRW", "STRL": + // Go's Yml destination class includes SP in 386 mode. These system + // instructions write their result directly to that destination. + return true + case "LARW", "LARL", "LSLW", "LSLL": + // LAR/LSL use the same Yrl destination class, including SP. + return true + case "LFSW", "LFSL", "LGSW", "LGSL", "LSSW", "LSSL": + // Far-pointer loads also use Yrl, including SP, for their offset. + return true + case "RDFSBASEL", "RDGSBASEL": + // The 386 FSGSBASE read forms use Yrl destinations, including SP. + return true + case "MOVBWSX", "MOVBWZX", "MOVBLSX", "MOVBLZX", + "MOVWLSX", "MOVWLZX", "MOVLQZX", "MOVSWW", "MOVZWW": + return true + case "KMOVB", "KMOVW", "KMOVD", "KMOVQ": + return len(ins.Args) == 2 && amd64IsKOperand(ins.Args[0]) case "ANDL": _, ok := bounded386SPAndMovement(ins) return ok @@ -758,6 +930,37 @@ func (c *amd64Ctx) popI64() string { return "%" + val } +func (c *amd64Ctx) pushI16(v string) error { + sp, err := c.loadReg(SP) + if err != nil { + return err + } + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i64 %s, 2\n", next, sp) + if err := c.storeRegUnchecked(SP, "%"+next); err != nil { + return err + } + p := c.ptrFromAddrI64("%" + next) + fmt.Fprintf(c.b, " store i16 %s, ptr %s, align 1\n", v, p) + return nil +} + +func (c *amd64Ctx) popI16() (string, error) { + sp, err := c.loadReg(SP) + if err != nil { + return "", err + } + p := c.ptrFromAddrI64(sp) + v := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i16, ptr %s, align 1\n", v, p) + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, 2\n", next, sp) + if err := c.storeRegUnchecked(SP, "%"+next); err != nil { + return "", err + } + return "%" + v, nil +} + func (c *amd64Ctx) pushI32(v string) error { sp, err := c.loadReg(SP) if err != nil { @@ -836,6 +1039,28 @@ func amd64ByteAlias(rr Reg) (base Reg, shift uint, ok bool) { return DX, 0, true case DH: return DX, 8, true + case BPB: + return BP, 0, true + case SIB: + return SI, 0, true + case DIB: + return DI, 0, true + case R8B: + return Reg("R8"), 0, true + case R9B: + return Reg("R9"), 0, true + case R10B: + return Reg("R10"), 0, true + case R11B: + return Reg("R11"), 0, true + case R12B: + return Reg("R12"), 0, true + case R13B: + return Reg("R13"), 0, true + case R14B: + return Reg("R14"), 0, true + case R15B: + return Reg("R15"), 0, true default: return "", 0, false } @@ -1119,6 +1344,7 @@ func (c *amd64Ctx) setZSFlagsFromI64(v string) { slt := c.newTmp() fmt.Fprintf(c.b, " %%%s = icmp slt i64 %s, 0\n", slt, v) fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", slt, c.flagsSltSlot) + c.setParityFlagSized(I64, v) } func (c *amd64Ctx) setZSFlagsFromI32(v string) { @@ -1128,6 +1354,33 @@ func (c *amd64Ctx) setZSFlagsFromI32(v string) { slt := c.newTmp() fmt.Fprintf(c.b, " %%%s = icmp slt i32 %s, 0\n", slt, v) fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", slt, c.flagsSltSlot) + c.setParityFlagSized(I32, v) +} + +func (c *amd64Ctx) setParityFlagSized(ty LLVMType, v string) { + low := v + if ty != I8 { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to i8\n", truncated, ty, v) + low = "%" + truncated + } + shift4 := c.newTmp() + fold4 := c.newTmp() + shift2 := c.newTmp() + fold2 := c.newTmp() + shift1 := c.newTmp() + fold1 := c.newTmp() + bit := c.newTmp() + parity := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i8 %s, 4\n", shift4, low) + fmt.Fprintf(c.b, " %%%s = xor i8 %s, %%%s\n", fold4, low, shift4) + fmt.Fprintf(c.b, " %%%s = lshr i8 %%%s, 2\n", shift2, fold4) + fmt.Fprintf(c.b, " %%%s = xor i8 %%%s, %%%s\n", fold2, fold4, shift2) + fmt.Fprintf(c.b, " %%%s = lshr i8 %%%s, 1\n", shift1, fold2) + fmt.Fprintf(c.b, " %%%s = xor i8 %%%s, %%%s\n", fold1, fold2, shift1) + fmt.Fprintf(c.b, " %%%s = and i8 %%%s, 1\n", bit, fold1) + fmt.Fprintf(c.b, " %%%s = icmp eq i8 %%%s, 0\n", parity, bit) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", parity, c.flagsPFSlot) } func (c *amd64Ctx) setCmpFlags(a, b string) { @@ -1142,6 +1395,9 @@ func (c *amd64Ctx) setCmpFlags(a, b string) { ult := c.newTmp() fmt.Fprintf(c.b, " %%%s = icmp ult i64 %s, %s\n", ult, a, b) fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", ult, c.flagsCFSlot) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i64 %s, %s\n", result, a, b) + c.setParityFlagSized(I64, "%"+result) } func (c *amd64Ctx) loadFlag(slot string) string { @@ -1158,6 +1414,29 @@ func (c *amd64Ctx) fpParam(off int64) (slot FrameSlot, ok bool) { return s, true } +func (c *amd64Ctx) loadFPParamValue(slot FrameSlot) (string, error) { + if slot.Index < 0 || slot.Index >= len(c.sig.Args) { + return "", fmt.Errorf("FP read slot: invalid arg index %d at +%d(FP)", slot.Index, slot.Offset) + } + if c.classicFrame != "" { + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", loaded, slot.Type, c.classicFramePtr(slot.Offset)) + return "%" + loaded, nil + } + if shadow := c.fpParamAlloca[slot.Offset]; shadow != "" { + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s\n", loaded, slot.Type, shadow) + return "%" + loaded, nil + } + value := fmt.Sprintf("%%arg%d", slot.Index) + if fields := frameSlotFields(slot); len(fields) != 0 { + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %s%s\n", extracted, c.sig.Args[slot.Index], value, frameSlotExtractSuffix(slot)) + value = "%" + extracted + } + return value, nil +} + func (c *amd64Ctx) fpResultAlloca(off int64) (string, LLVMType, bool) { s, ok := c.fpParams[off] _ = s @@ -1260,24 +1539,10 @@ func (c *amd64Ctx) evalFPToI64(off int64) (string, error) { // inference (common in low-level runtime assembly). return "0", nil } - idx := slot.Index - if idx < 0 || idx >= len(c.sig.Args) { - return "", fmt.Errorf("FP read slot: invalid arg index %d at +%d(FP)", idx, off) - } - arg := fmt.Sprintf("%%arg%d", idx) - - // If this FP slot refers to a field within an aggregate argument (string/slice), - // extract that field first. ty := slot.Type - if c.classicFrame != "" { - loaded := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", loaded, ty, c.classicFramePtr(off)) - arg = "%" + loaded - } else if slot.Field >= 0 { - aggTy := c.sig.Args[idx] - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", t, aggTy, arg, slot.Field) - arg = "%" + t + arg, err := c.loadFPParamValue(slot) + if err != nil { + return "", err } switch ty { case Ptr: @@ -1319,33 +1584,139 @@ func (c *amd64Ctx) evalFPToI64(off int64) (string, error) { } } +func amd64IntegerTypeBits(ty LLVMType) (int, bool) { + switch ty { + case I1: + return 1, true + case I8: + return 8, true + case I16: + return 16, true + case I32: + return 32, true + case I64: + return 64, true + default: + return 0, false + } +} + +func amd64IntegerTypeForBits(bits int) LLVMType { + switch bits { + case 1: + return I1 + case 8: + return I8 + case 16: + return I16 + case 32: + return I32 + case 64: + return I64 + default: + return "" + } +} + +func (c *amd64Ctx) coerceFPStoreValue(from, to LLVMType, value string) (string, error) { + if from == to { + return value, nil + } + pointerBits := 64 + if c.goarch == "386" { + pointerBits = 32 + } + + rawType := from + rawValue := value + switch from { + case Ptr: + rawType = amd64IntegerTypeForBits(pointerBits) + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %s to %s\n", cast, value, rawType) + rawValue = "%" + cast + case LLVMType("float"): + rawType = I32 + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %s to i32\n", cast, value) + rawValue = "%" + cast + case LLVMType("double"): + rawType = I64 + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", cast, value) + rawValue = "%" + cast + default: + if _, ok := amd64IntegerTypeBits(from); !ok { + return "", fmt.Errorf("unsupported FP store source type %s", from) + } + } + + targetBits := 0 + switch to { + case Ptr: + targetBits = pointerBits + case LLVMType("float"): + targetBits = 32 + case LLVMType("double"): + targetBits = 64 + default: + var ok bool + targetBits, ok = amd64IntegerTypeBits(to) + if !ok { + return "", fmt.Errorf("unsupported FP store destination type %s", to) + } + } + + fromBits, _ := amd64IntegerTypeBits(rawType) + targetIntType := amd64IntegerTypeForBits(targetBits) + if fromBits > targetBits { + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", cast, rawType, rawValue, targetIntType) + rawType, rawValue = targetIntType, "%"+cast + } else if fromBits < targetBits { + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", cast, rawType, rawValue, targetIntType) + rawType, rawValue = targetIntType, "%"+cast + } + + switch to { + case Ptr: + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr %s %s to ptr\n", cast, rawType, rawValue) + return "%" + cast, nil + case LLVMType("float"), LLVMType("double"): + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", cast, rawType, rawValue, to) + return "%" + cast, nil + default: + return rawValue, nil + } +} + func (c *amd64Ctx) storeFPResult(off int64, ty LLVMType, v string) error { + return c.storeFPResultWithMetadata(off, ty, v, "") +} + +func (c *amd64Ctx) storeFPResultWithMetadata(off int64, ty LLVMType, v, metadata string) error { align := "" if c.classicFrame != "" { // The 386 ABI frame is a byte array, and FP offsets need not provide // the natural alignment required by the value stored in a slot. align = ", align 1" } - if slot, ok := c.fpParams[off]; ok && c.classicFrame != "" { - // 386 ABIInternal stubs write register arguments back into the - // caller-provided FP argument area before tail-calling an ABI0 - // handler (for example runtime.panicIndex). The classic frame is - // deliberately mutable, unlike an LLVM SSA argument. - value := v - switch { - case ty == slot.Type: - case ty == I32 && slot.Type == Ptr: - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = inttoptr i32 %s to ptr\n", t, v) - value = "%" + t - case ty == Ptr && slot.Type == I32: - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %s to i32\n", t, v) - value = "%" + t - default: - return fmt.Errorf("FP parameter write type mismatch: have %s want %s at +%d(FP)", ty, slot.Type, off) + if slot, ok := c.fpParams[off]; ok { + ptr := c.fpParamAlloca[off] + if c.classicFrame != "" { + ptr = c.classicFramePtr(off) } - fmt.Fprintf(c.b, " store %s %s, ptr %s%s\n", slot.Type, value, c.classicFramePtr(off), align) + if ptr == "" { + return fmt.Errorf("missing mutable FP parameter slot at +%d(FP)", off) + } + value, err := c.coerceFPStoreValue(ty, slot.Type, v) + if err != nil { + return fmt.Errorf("FP parameter write type mismatch: have %s want %s at +%d(FP): %w", ty, slot.Type, off, err) + } + fmt.Fprintf(c.b, " store %s %s, ptr %s%s%s\n", slot.Type, value, ptr, align, metadata) return nil } if c.goarch == "386" && ty == I32 { @@ -1380,9 +1751,9 @@ func (c *amd64Ctx) storeFPResult(off int64, ty LLVMType, v string) error { if slot.Type == LLVMType("double") { cast := c.newTmp() fmt.Fprintf(c.b, " %%%s = bitcast i64 %%%s to double\n", cast, merged) - fmt.Fprintf(c.b, " store double %%%s, ptr %s%s\n", cast, alloca, align) + fmt.Fprintf(c.b, " store double %%%s, ptr %s%s%s\n", cast, alloca, align, metadata) } else { - fmt.Fprintf(c.b, " store i64 %%%s, ptr %s%s\n", merged, alloca, align) + fmt.Fprintf(c.b, " store i64 %%%s, ptr %s%s%s\n", merged, alloca, align, metadata) } c.fpResWritten[slot.Index] = true return nil @@ -1396,7 +1767,21 @@ func (c *amd64Ctx) storeFPResult(off int64, ty LLVMType, v string) error { if c.goarch == "386" && ty == I32 && slotTy == Ptr { p := c.newTmp() fmt.Fprintf(c.b, " %%%s = inttoptr i32 %s to ptr\n", p, v) - fmt.Fprintf(c.b, " store ptr %%%s, ptr %s%s\n", p, alloca, align) + fmt.Fprintf(c.b, " store ptr %%%s, ptr %s%s%s\n", p, alloca, align, metadata) + c.markFPResultWritten(off) + return nil + } + if ty == I32 && slotTy == LLVMType("float") { + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i32 %s to float\n", cast, v) + fmt.Fprintf(c.b, " store float %%%s, ptr %s%s%s\n", cast, alloca, align, metadata) + c.markFPResultWritten(off) + return nil + } + if ty == LLVMType("float") && slotTy == I32 { + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %s to i32\n", cast, v) + fmt.Fprintf(c.b, " store i32 %%%s, ptr %s%s%s\n", cast, alloca, align, metadata) c.markFPResultWritten(off) return nil } @@ -1428,41 +1813,68 @@ func (c *amd64Ctx) storeFPResult(off int64, ty LLVMType, v string) error { fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", t, ty, v, slotTy) cast = "%" + t } - fmt.Fprintf(c.b, " store %s %s, ptr %s%s\n", slotTy, cast, alloca, align) + fmt.Fprintf(c.b, " store %s %s, ptr %s%s%s\n", slotTy, cast, alloca, align, metadata) c.markFPResultWritten(off) return nil } } + if (ty == I64 || ty == LLVMType("double")) && slotTy == LLVMType("float") { + secondAlloca, secondTy, secondOK := c.fpResultAlloca(off + 4) + if !secondOK || secondTy != LLVMType("float") { + return fmt.Errorf("FP write at +%d(FP) cannot split a 64-bit memory operand", off) + } + bits := v + if ty == LLVMType("double") { + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", cast, v) + bits = "%" + cast + } + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", low, bits) + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i64 %s, 32\n", shifted, bits) + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", high, shifted) + lowFloat := c.newTmp() + highFloat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", lowFloat, low) + fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", highFloat, high) + fmt.Fprintf(c.b, " store float %%%s, ptr %s%s%s\n", lowFloat, alloca, align, metadata) + fmt.Fprintf(c.b, " store float %%%s, ptr %s%s%s\n", highFloat, secondAlloca, align, metadata) + c.markFPResultWritten(off) + c.markFPResultWritten(off + 4) + return nil + } // Cast integer sizes when needed (common: i64 reg -> i32 return slot). switch { case ty == I64 && slotTy == I32: t := c.newTmp() fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", t, v) - fmt.Fprintf(c.b, " store i32 %%%s, ptr %s%s\n", t, alloca, align) + fmt.Fprintf(c.b, " store i32 %%%s, ptr %s%s%s\n", t, alloca, align, metadata) c.markFPResultWritten(off) return nil case ty == I64 && slotTy == LLVMType("double"): t := c.newTmp() fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to double\n", t, v) - fmt.Fprintf(c.b, " store double %%%s, ptr %s%s\n", t, alloca, align) + fmt.Fprintf(c.b, " store double %%%s, ptr %s%s%s\n", t, alloca, align, metadata) c.markFPResultWritten(off) return nil case ty == LLVMType("double") && slotTy == I64: t := c.newTmp() fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", t, v) - fmt.Fprintf(c.b, " store i64 %%%s, ptr %s%s\n", t, alloca, align) + fmt.Fprintf(c.b, " store i64 %%%s, ptr %s%s%s\n", t, alloca, align, metadata) c.markFPResultWritten(off) return nil case ty == I64 && slotTy == Ptr: t := c.newTmp() fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", t, v) - fmt.Fprintf(c.b, " store ptr %%%s, ptr %s%s\n", t, alloca, align) + fmt.Fprintf(c.b, " store ptr %%%s, ptr %s%s%s\n", t, alloca, align, metadata) c.markFPResultWritten(off) return nil case ty == Ptr && slotTy == I64: t := c.newTmp() fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %s to i64\n", t, v) - fmt.Fprintf(c.b, " store i64 %%%s, ptr %s%s\n", t, alloca, align) + fmt.Fprintf(c.b, " store i64 %%%s, ptr %s%s%s\n", t, alloca, align, metadata) c.markFPResultWritten(off) return nil case ty == I64 && slotTy == I64: @@ -1471,11 +1883,35 @@ func (c *amd64Ctx) storeFPResult(off int64, ty LLVMType, v string) error { return fmt.Errorf("FP write type mismatch: have %s want %s at +%d(FP)", ty, slotTy, off) } } - fmt.Fprintf(c.b, " store %s %s, ptr %s%s\n", ty, v, alloca, align) + fmt.Fprintf(c.b, " store %s %s, ptr %s%s%s\n", ty, v, alloca, align, metadata) c.markFPResultWritten(off) return nil } +func (c *amd64Ctx) namedFPResultOffset(name string, fallback int64) int64 { + if name == "" { + return fallback + } + match := int64(0) + found := false + for _, slot := range c.fpResults { + if slot.Name != name { + continue + } + if found { + // Aggregate results can have multiple physical FP slots with one Go + // name. Their explicit offsets remain authoritative. + return fallback + } + match = slot.Offset + found = true + } + if found { + return match + } + return fallback +} + func isSplit64FrameType(typ LLVMType) bool { return typ == I64 || typ == LLVMType("double") } diff --git a/amd64_ecosystem_test.go b/amd64_ecosystem_test.go new file mode 100644 index 00000000..a0e7aa03 --- /dev/null +++ b/amd64_ecosystem_test.go @@ -0,0 +1,7809 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateAMD64LegacyDoubleShiftRegisterPair(t *testing.T) { + src := ` +TEXT shiftpair(SB),NOSPLIT,$0-0 + MOVQ $1, SI + MOVQ $2, CX + SHLQ $13, CX:SI + RET +` + translateAMD64EcosystemCase(t, src, "shiftpair") +} + +func TestTranslateX86UD2CompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 assigns UD2 to ynone on both 386 and amd64: its complete + // accepted surface is exactly the no-operand form. + file, err := Parse(ArchAMD64, "TEXT ud2forms(SB),NOSPLIT,$0-0\n\tUD2\n") + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + } { + t.Run(target.goarch, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"ud2forms": {Name: "ud2forms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, "unreachable") { + t.Fatalf("%s UD2 translation is not terminating:\n%s", target.goarch, ll) + } + compileLLVMToObject(t, llc, target.triple, "ud2-"+target.goarch+".ll", "ud2-"+target.goarch+".o", ll) + }) + } +} + +func TestTranslateX86UD2RejectsFormsOutsideGoAssemblerTables(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\tUD2 AX\n") + if err != nil { + return + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + } { + if _, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("%s UD2 with an operand unexpectedly translated", target.goarch) + } + } +} + +func TestTranslateAMD64ScalarShiftRotateCompleteGoAssemblerForms(t *testing.T) { + // ROL/ROR/SAR/SAL/SHL/SHR share yshb/yshl. Each width accepts $1, + // unsigned imm8, CL, and CX counts with a same-width GP-or-memory target. + var src strings.Builder + src.WriteString("TEXT scalarshiftrotateforms(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"ROL", "ROR", "SAR", "SAL", "SHL", "SHR"} { + for _, width := range []string{"B", "W", "L", "Q"} { + op := stem + width + if width == "B" { + fmt.Fprintf(&src, "\t%s $1, AH\n", op) + fmt.Fprintf(&src, "\t%s $255, R11\n", op) + fmt.Fprintf(&src, "\t%s CL, (BX)\n", op) + fmt.Fprintf(&src, "\t%s CX, AL\n", op) + } else { + fmt.Fprintf(&src, "\t%s $1, AX\n", op) + fmt.Fprintf(&src, "\t%s $255, R11\n", op) + fmt.Fprintf(&src, "\t%s CL, (BX)\n", op) + fmt.Fprintf(&src, "\t%s CX, AX\n", op) + } + } + } + // Go's special double-shift table adds signed imm8/CL/CX, GP source, + // GP-or-memory destination rows to SHL/SHR W/L/Q only. + for _, op := range []string{"SHLW", "SHLL", "SHLQ", "SHRW", "SHRL", "SHRQ"} { + fmt.Fprintf(&src, "\t%s $-128, AX, BX\n", op) + fmt.Fprintf(&src, "\t%s $127, R11, (DI)\n", op) + fmt.Fprintf(&src, "\t%s CL, AX, BX\n", op) + fmt.Fprintf(&src, "\t%s CX, R11, (DI)\n", op) + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "scalarshiftrotateforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "scalar-shift-rotate-forms.ll", "scalar-shift-rotate-forms.o", ll) +} + +func TestTranslate386ScalarShiftRotateCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT scalarshiftrotateforms386(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"ROL", "ROR", "SAR", "SAL", "SHL", "SHR"} { + for _, width := range []string{"B", "W", "L"} { + op := stem + width + if width == "B" { + fmt.Fprintf(&src, "\t%s $1, AH\n", op) + fmt.Fprintf(&src, "\t%s $255, DX\n", op) + fmt.Fprintf(&src, "\t%s CL, (BX)\n", op) + fmt.Fprintf(&src, "\t%s CX, AL\n", op) + fmt.Fprintf(&src, "\t%s $1, BP\n", op) + fmt.Fprintf(&src, "\t%s $255, SI\n", op) + fmt.Fprintf(&src, "\t%s CL, DI\n", op) + } else { + fmt.Fprintf(&src, "\t%s $1, AX\n", op) + fmt.Fprintf(&src, "\t%s $255, SI\n", op) + fmt.Fprintf(&src, "\t%s CL, (BX)\n", op) + fmt.Fprintf(&src, "\t%s CX, DI\n", op) + } + } + } + for _, op := range []string{"SHLW", "SHLL", "SHRW", "SHRL"} { + fmt.Fprintf(&src, "\t%s $-128, AX, BX\n", op) + fmt.Fprintf(&src, "\t%s $127, SI, (DI)\n", op) + fmt.Fprintf(&src, "\t%s CL, AX, BX\n", op) + fmt.Fprintf(&src, "\t%s CX, SI, (DI)\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "scalarshiftrotateforms386": {Name: "scalarshiftrotateforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "scalar-shift-rotate-386-forms.ll", "scalar-shift-rotate-386-forms.o", ll) +} + +func TestTranslateX86PortIOCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT portioforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"INB", "INW", "INL", "OUTB", "OUTW", "OUTL"} { + fmt.Fprintf(&src, "\t%s\n", op) + fmt.Fprintf(&src, "\t%s $7\n", op) + } + for _, op := range []string{"INSB", "INSW", "INSL", "OUTSB", "OUTSW", "OUTSL"} { + fmt.Fprintf(&src, "\t%s\n", op) + fmt.Fprintf(&src, "\tCLD; REP; %s\n", op) + fmt.Fprintf(&src, "\tSTD; REPN; %s\n", op) + fmt.Fprintln(&src, "\tCLD") + } + src.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + } { + t.Run(target.goarch, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "portioforms": {Name: "portioforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `asm sideeffect "inb`, `asm sideeffect "inw`, `asm sideeffect "inl`, + `asm sideeffect "outb`, `asm sideeffect "outw`, `asm sideeffect "outl`, + `asm sideeffect "insb`, `asm sideeffect "insw`, `asm sideeffect "insl`, + `asm sideeffect "outsb`, `asm sideeffect "outsw`, `asm sideeffect "outsl`, + `asm sideeffect "rep; insb`, `asm sideeffect "rep; outsb`, + `asm sideeffect "repne; insb`, `asm sideeffect "repne; outsb`, + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s port-I/O translation missing %q:\n%s", target.goarch, want, ll) + } + } + compileLLVMToObject(t, llc, target.triple, "port-io-"+target.goarch+".ll", "port-io-"+target.goarch+".o", ll) + }) + } +} + +func TestTranslateX86PortIORejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + } { + for _, instruction := range []string{ + "INB AX", + "INW $1, AX", + "OUTL AX", + "OUTB $1, AX", + "INSB AX", + "OUTSL (SI)", + "REP; INL", + } { + name := target.goarch + "/" + strings.NewReplacer(" ", "_", ";", "_").Replace(instruction) + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("%s %q unexpectedly translated", target.goarch, instruction) + } + }) + } + } +} + +func TestTranslateX86StringInstructionsCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goarch string + triple string + widths []string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu", widths: []string{"B", "W", "L"}}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", widths: []string{"B", "W", "L", "Q"}}, + } { + t.Run(target.goarch, func(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT stringforms(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"MOVS", "STOS", "SCAS"} { + for _, width := range target.widths { + op := stem + width + fmt.Fprintf(&src, "\t%s\n", op) + fmt.Fprintf(&src, "\tCLD; REP; %s\n", op) + fmt.Fprintf(&src, "\tSTD; REPN; %s\n", op) + fmt.Fprintln(&src, "\tCLD") + } + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"stringforms": {Name: "stringforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, stem := range []string{"movs", "rep_stos", "rep_scas"} { + for _, width := range target.widths { + want := "@__plan9asm_" + stem + strings.ToLower(width) + if !strings.Contains(ll, want) { + t.Fatalf("%s string translation missing %q:\n%s", target.goarch, want, ll) + } + } + } + compileLLVMToObject(t, llc, target.triple, "string-forms-"+target.goarch+".ll", "string-forms-"+target.goarch+".o", ll) + }) + } +} + +func TestTranslate386RejectsQwordStringInstructions(t *testing.T) { + for _, op := range []string{"MOVSQ", "STOSQ", "SCASQ"} { + t.Run(op, func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+op+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("386 %s unexpectedly translated", op) + } + }) + } +} + +func TestTranslate386UsesUniqueFPResultNamesForLegacyOffsets(t *testing.T) { + src := `TEXT legacyresults(SB),NOSPLIT,$0-56 + MOVL AX, retax+28(FP) + MOVL BX, retbx+32(FP) + MOVL CX, retcx+40(FP) + MOVL DX, retdx+44(FP) + MOVL SI, retsi+48(FP) + MOVL DI, retdi+52(FP) + MOVL BP, retbp+56(FP) + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + results := make([]FrameSlot, 0, 7) + names := []string{"retax", "retbx", "retcx", "retdx", "retsi", "retdi", "retbp"} + for i, name := range names { + results = append(results, FrameSlot{Offset: int64(28 + 4*i), Type: I32, Index: i, Field: -1, Name: name}) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "legacyresults": { + Name: "legacyresults", + Args: []LLVMType{I32, I32, I32, I32, I32, I32, I32}, + Ret: LLVMType("{ i32, i32, i32, i32, i32, i32, i32 }"), + Frame: FrameLayout{Results: results}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "legacy-named-results.ll", "legacy-named-results.o", ll) +} + +func TestTranslateX86MOVLScalarResultMemoryForms(t *testing.T) { + file, err := Parse(ArchAMD64, `TEXT movlresults(SB),NOSPLIT,$0-8 + MOVL $-1, first+0(FP) + MOVL AX, second+4(FP) + RET +`) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + } { + t.Run(target.goarch, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"movlresults": { + Name: "movlresults", + Ret: LLVMType("{ i32, i32 }"), + Frame: FrameLayout{Results: []FrameSlot{ + {Offset: 0, Type: I32, Index: 0, Field: -1, Name: "first"}, + {Offset: 4, Type: I32, Index: 1, Field: -1, Name: "second"}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "movl-result-forms-"+target.goarch+".ll", "movl-result-forms-"+target.goarch+".o", ll) + }) + } +} + +func TestTranslateX86MOVLRejectsMemoryToResultMemory(t *testing.T) { + for _, source := range []string{"arg+0(FP)", "(AX)", "global(SB)"} { + t.Run(strings.NewReplacer("(", "_", ")", "_", "+", "_").Replace(source), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-4\n\tMOVL "+source+", result+0(FP)\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": { + Name: "bad", + Ret: I32, + Frame: FrameLayout{Results: []FrameSlot{{Offset: 0, Type: I32, Index: 0, Field: -1, Name: "result"}}}, + }}, + }); err == nil { + t.Fatalf("MOVL %s, result(FP) unexpectedly translated", source) + } + }) + } +} + +func TestTranslateX86ImplicitMultiplyDivideCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's ydivb/ydivl tables give MUL, IMUL, DIV, and IDIV one + // GP-or-memory operand. IMUL W/L/Q additionally uses yimul/yimul3 for + // the two- and three-operand signed multiply forms. + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goarch string + triple string + widths []string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu", widths: []string{"B", "W", "L"}}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", widths: []string{"B", "W", "L", "Q"}}, + } { + t.Run(target.goarch, func(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT muldivforms(SB),NOSPLIT,$0-0\n") + for _, width := range target.widths { + reg := "BX" + for _, stem := range []string{"MUL", "IMUL", "DIV", "IDIV"} { + fmt.Fprintf(&src, "\t%s%s %s\n", stem, width, reg) + fmt.Fprintf(&src, "\t%s%s (SI)\n", stem, width) + } + if width != "B" { + fmt.Fprintf(&src, "\tIMUL%s $-128, CX\n", width) + fmt.Fprintf(&src, "\tIMUL%s $4294967295, DI\n", width) + fmt.Fprintf(&src, "\tIMUL%s BX, CX\n", width) + fmt.Fprintf(&src, "\tIMUL%s (SI), DI\n", width) + fmt.Fprintf(&src, "\tIMUL3%s $-128, BX, CX\n", width) + fmt.Fprintf(&src, "\tIMUL3%s $4294967295, (SI), DI\n", width) + } + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"muldivforms": {Name: "muldivforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "mul-div-forms-"+target.goarch+".ll", "mul-div-forms-"+target.goarch+".o", ll) + }) + } +} + +func TestTranslateX86ImplicitMultiplyDivideRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + common := []string{ + "MULB $1", + "DIVW AX, BX", + "IDIVL AX, BX", + "IMULB AX, BX", + "IMUL3B $1, AX, BX", + "IMULW (AX), (BX)", + "IMUL3W AX, BX, CX", + "IMUL3L $1, AX, (BX)", + "IMULL X0", + } + for _, target := range []struct { + goarch string + triple string + instructions []string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu", instructions: append(append([]string{}, common...), "MULQ AX", "IMULQ AX", "DIVQ AX", "IDIVQ AX", "IMUL3Q $1, AX, BX")}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instructions: append(append([]string{}, common...), "IMULQ $4294967296, AX", "IMUL3Q $-2147483649, AX, BX")}, + } { + for _, instruction := range target.instructions { + name := target.goarch + "/" + strings.NewReplacer(" ", "_", ",", "_", "(", "_", ")", "_").Replace(instruction) + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("%s accepted %q outside Go 1.27's multiply/divide tables", target.goarch, instruction) + } + }) + } + } +} + +func TestTranslateAMD64ScalarShiftRotateRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "SHRB $-1, AL", + "SHLB $256, AL", + "SARW AX, BX", + "SALL (AX), BX", + "ROLL $1, X1", + "RORB $1, X1", + "RORQ.Z $1, AX, AX", + "SHLB $1, AL, BL", + "SARL $1, AX, BX", + "SALW $1, AX, BX", + "ROLQ $1, AX, BX", + "SHLL $128, AX, BX", + "SHRL DX, AX, BX", + "SHLW $1, (AX), BX", + "SHRQ $1, AX, $2", + "SHLB $1, AX, BX", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidscalarshiftrotate(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidscalarshiftrotate": {Name: "invalidscalarshiftrotate", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's shift/rotate tables", instruction) + } + }) + } +} + +func TestTranslate386ScalarShiftRotateRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "SHRQ $1, AX", + "ROLQ CL, (BX)", + "SHRB $1, SP", + "SARL $1, R8", + "SHLL $1, R8, AX", + "SHLQ $1, AX, BX", + "SHRQ CL, AX, (BX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidscalarshiftrotate386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidscalarshiftrotate386": {Name: "invalidscalarshiftrotate386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64IncDecCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT incdecforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"INCB", "DECB"} { + fmt.Fprintf(&src, "\t%s AL\n", op) + fmt.Fprintf(&src, "\t%s AH\n", op) + fmt.Fprintf(&src, "\t%s BPB\n", op) + fmt.Fprintf(&src, "\t%s R15B\n", op) + fmt.Fprintf(&src, "\t%s R11\n", op) + fmt.Fprintf(&src, "\t%s (BX)\n", op) + } + for _, op := range []string{"INCW", "DECW", "INCL", "DECL", "INCQ", "DECQ"} { + fmt.Fprintf(&src, "\t%s AX\n", op) + fmt.Fprintf(&src, "\t%s R11\n", op) + fmt.Fprintf(&src, "\t%s (BX)\n", op) + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "incdecforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "inc-dec-forms.ll", "inc-dec-forms.o", ll) +} + +func TestTranslate386IncDecCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT incdecforms386(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"INCB", "DECB"} { + fmt.Fprintf(&src, "\t%s AL\n", op) + fmt.Fprintf(&src, "\t%s AH\n", op) + fmt.Fprintf(&src, "\t%s DX\n", op) + fmt.Fprintf(&src, "\t%s BP\n", op) + fmt.Fprintf(&src, "\t%s SI\n", op) + fmt.Fprintf(&src, "\t%s DI\n", op) + fmt.Fprintf(&src, "\t%s (BX)\n", op) + } + for _, op := range []string{"INCW", "DECW", "INCL", "DECL"} { + fmt.Fprintf(&src, "\t%s AX\n", op) + fmt.Fprintf(&src, "\t%s SI\n", op) + fmt.Fprintf(&src, "\t%s (BX)\n", op) + fmt.Fprintf(&src, "\t%s SP\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "incdecforms386": {Name: "incdecforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "inc-dec-386-forms.ll", "inc-dec-386-forms.o", ll) +} + +func TestTranslateAMD64IncDecRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "INCB", + "INCW AX, BX", + "DECL $1", + "DECQ X0", + "INCQ.Z AX", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidincdec(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidincdec": {Name: "invalidincdec", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's INC/DEC tables", instruction) + } + }) + } +} + +func TestTranslate386IncDecRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "INCB SP", + "INCW R8", + "DECL R11", + "INCQ AX", + "DECQ (BX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidincdec386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidincdec386": {Name: "invalidincdec386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedWordMultiplyCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT packedwordmulforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PMULLW", "PMULHW", "PMULHUW"} { + fmt.Fprintf(&src, "\t%s M0, M1\n", op) + fmt.Fprintf(&src, "\t%s (AX), M1\n", op) + fmt.Fprintf(&src, "\t%s X0, X1\n", op) + fmt.Fprintf(&src, "\t%s (AX), X1\n", op) + } + src.WriteString("\tPMULHRSW X0, X1\n\tPMULHRSW (AX), X1\n") + for _, op := range []string{"VPMULLW", "VPMULHW", "VPMULHUW", "VPMULHRSW"} { + fmt.Fprintf(&src, "\t%s X0, X1, X2\n", op) + fmt.Fprintf(&src, "\t%s (AX), X1, X2\n", op) + fmt.Fprintf(&src, "\t%s Y0, Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s (AX), Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s Z0, Z1, Z2\n", op) + fmt.Fprintf(&src, "\t%s (AX), Z1, Z2\n", op) + fmt.Fprintf(&src, "\t%s X20, X21, X22\n", op) + fmt.Fprintf(&src, "\t%s X0, X1, K1, X2\n", op) + fmt.Fprintf(&src, "\t%s.Z Y0, Y1, K2, Y2\n", op) + fmt.Fprintf(&src, "\t%s.Z Z0, Z1, K3, Z2\n", op) + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "packedwordmulforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-word-multiply-forms.ll", "packed-word-multiply-forms.o", ll) +} + +func TestTranslate386PackedWordMultiplyCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT packedwordmulforms386(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PMULLW", "PMULHW", "PMULHUW", "PMULHRSW"} { + fmt.Fprintf(&src, "\t%s X0, X1\n", op) + fmt.Fprintf(&src, "\t%s (AX), X1\n", op) + } + for _, op := range []string{"VPMULLW", "VPMULHW", "VPMULHUW", "VPMULHRSW"} { + fmt.Fprintf(&src, "\t%s X0, X1, X2\n", op) + fmt.Fprintf(&src, "\t%s (AX), X1, X2\n", op) + fmt.Fprintf(&src, "\t%s Y0, Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s (AX), Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s X20, X21, X22\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "packedwordmulforms386": {Name: "packedwordmulforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "packed-word-multiply-386-forms.ll", "packed-word-multiply-386-forms.o", ll) +} + +func TestTranslateAMD64PackedWordMultiplyRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PMULLW Y0, Y1", + "PMULHRSW M0, M1", + "PMULHW.Z X0, X1", + "VPMULLW.BCST (AX), X1, X2", + "VPMULHW.SAE X0, X1, X2", + "VPMULHUW.Z X0, X1, X2", + "VPMULLW X0, Y1, Y2", + "VPMULHW X0, X1, K0, X2", + "VPMULHUW X0, X1, AX, X2", + "VPMULHRSW X0, X1, K1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedwordmul(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedwordmul": {Name: "invalidpackedwordmul", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's packed-word multiply tables", instruction) + } + }) + } +} + +func TestTranslate386PackedWordMultiplyRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "PMULLW M0, M1", + "PMULHW (AX), M1", + "PMULHUW X8, X0", + "PMULHRSW X0, X8", + "VPMULLW Z0, Z1, Z2", + "VPMULHW X0, X1, K1, X2", + "VPMULHUW.Z X0, X1, K1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedwordmul386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidpackedwordmul386": {Name: "invalidpackedwordmul386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedWordMultiplyAddCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 uses ymm for PMADDWL and _yvandnpd for VPMADDWD. + src := `TEXT packedwordmaddforms(SB),NOSPLIT,$0-0 + PMADDWL M0, M1 + PMADDWL (AX), M2 + PMADDWL X0, X1 + PMADDWL (AX), X15 + VPMADDWD X0, X1, X2 + VPMADDWD (AX), X1, X2 + VPMADDWD Y0, Y1, Y2 + VPMADDWD (AX), Y1, Y2 + VPMADDWD Z0, Z1, Z2 + VPMADDWD (AX), Z1, Z2 + VPMADDWD X20, X21, X22 + VPMADDWD Y20, Y21, Y22 + VPMADDWD Z20, Z21, Z22 + VPMADDWD X20, X21, K1, X22 + VPMADDWD.Z (AX), X21, K2, X22 + VPMADDWD Y20, Y21, K3, Y22 + VPMADDWD.Z (AX), Y21, K4, Y22 + VPMADDWD Z20, Z21, K5, Z22 + VPMADDWD.Z (AX), Z21, K6, Z22 + RET +` + ll := translateAMD64EcosystemCase(t, src, "packedwordmaddforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-word-multiply-add-forms.ll", "packed-word-multiply-add-forms.o", ll) +} + +func TestTranslate386PackedWordMultiplyAddCompleteGoAssemblerForms(t *testing.T) { + src := `TEXT packedwordmaddforms386(SB),NOSPLIT,$0-0 + PMADDWL X0, X1 + PMADDWL (AX), X7 + VPMADDWD X0, X1, X2 + VPMADDWD (AX), X1, X2 + VPMADDWD Y0, Y1, Y2 + VPMADDWD (AX), Y1, Y2 + VPMADDWD Z0, Z1, Z7 + VPMADDWD (AX), Z6, Z7 + VPMADDWD X20, X21, X22 + VPMADDWD Y20, Y21, Y22 + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "packedwordmaddforms386": {Name: "packedwordmaddforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "packed-word-multiply-add-386-forms.ll", "packed-word-multiply-add-386-forms.o", ll) +} + +func TestTranslateAMD64PackedWordMultiplyAddRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PMADDWL.Z X0, X1", + "PMADDWL X0", + "PMADDWL Y0, Y1", + "PMADDWL X0, M1", + "PMADDWL X16, X1", + "PMADDWL X0, (AX)", + "VPMADDWD X0, X1", + "VPMADDWD M0, M1, M2", + "VPMADDWD X0, Y1, Y2", + "VPMADDWD X0, X1, (AX)", + "VPMADDWD.BCST (AX), X1, X2", + "VPMADDWD.Z X0, X1, X2", + "VPMADDWD X0, X1, K0, X2", + "VPMADDWD X0, X1, AX, X2", + "VPMADDWD X0, X1, K1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT invalidpackedwordmadd(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedwordmadd": {Name: "invalidpackedwordmadd", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's PMADDWL/VPMADDWD tables", instruction) + } + }) + } +} + +func TestTranslate386PackedWordMultiplyAddRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "PMADDWL M0, M1", + "PMADDWL (AX), M1", + "PMADDWL X8, X0", + "PMADDWL X0, X8", + "VPMADDWD Z8, Z1, Z2", + "VPMADDWD Z0, Z1, Z8", + "VPMADDWD X0, X1, K1, X2", + "VPMADDWD.Z X0, X1, K1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT invalidpackedwordmadd386(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidpackedwordmadd386": {Name: "invalidpackedwordmadd386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedFloatShuffleCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT packedfloatshuffleforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"SHUFPS", "SHUFPD"} { + fmt.Fprintf(&src, "\t%s $0, X0, X1\n", op) + fmt.Fprintf(&src, "\t%s $255, (AX), X15\n", op) + } + for _, op := range []string{"VSHUFPS", "VSHUFPD"} { + fmt.Fprintf(&src, "\t%s $0, X0, X1, X2\n", op) + fmt.Fprintf(&src, "\t%s $255, (AX), X1, X2\n", op) + fmt.Fprintf(&src, "\t%s $1, Y0, Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s $2, (AX), Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s $3, Z0, Z1, Z2\n", op) + fmt.Fprintf(&src, "\t%s $4, (AX), Z1, Z2\n", op) + fmt.Fprintf(&src, "\t%s $5, X20, X21, X22\n", op) + fmt.Fprintf(&src, "\t%s $6, X0, X1, K1, X2\n", op) + fmt.Fprintf(&src, "\t%s.Z $7, Y0, Y1, K2, Y2\n", op) + fmt.Fprintf(&src, "\t%s.BCST $8, (AX), Z1, Z2\n", op) + fmt.Fprintf(&src, "\t%s.BCST.Z $9, (AX), Z1, K3, Z2\n", op) + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "packedfloatshuffleforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-float-shuffle-forms.ll", "packed-float-shuffle-forms.o", ll) +} + +func TestTranslate386PackedFloatShuffleCompleteGoAssemblerForms(t *testing.T) { + src := ` +TEXT packedfloatshuffleforms386(SB),NOSPLIT,$0-0 + SHUFPS $0, X0, X1 + SHUFPS $255, (AX), X7 + SHUFPD $0, X0, X1 + SHUFPD $255, (AX), X7 + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "packedfloatshuffleforms386": {Name: "packedfloatshuffleforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "packed-float-shuffle-386-forms.ll", "packed-float-shuffle-386-forms.o", ll) +} + +func TestTranslateAMD64PackedFloatShuffleRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "SHUFPS $-1, X0, X1", + "SHUFPD $256, X0, X1", + "SHUFPS.Z $0, X0, X1", + "VSHUFPS $0, X0, X1", + "VSHUFPD.SAE $0, X0, X1, X2", + "VSHUFPS.Z $0, X0, X1, X2", + "VSHUFPD $0, X0, Y1, Y2", + "VSHUFPS $0, X0, X1, K0, X2", + "VSHUFPD $0, X0, X1, AX, X2", + "VSHUFPS.BCST $0, X0, X1, X2", + "VSHUFPD.BCST $0, (AX), X1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedfloatshuffle(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedfloatshuffle": {Name: "invalidpackedfloatshuffle", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's packed-float shuffle tables", instruction) + } + }) + } +} + +func TestTranslate386PackedFloatShuffleRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "SHUFPS $0, X8, X0", + "SHUFPD $0, X0, X8", + "VSHUFPS $0, X0, X1, X2", + "VSHUFPD $0, Y0, Y1, Y2", + "VSHUFPS.BCST $0, (AX), X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedfloatshuffle386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidpackedfloatshuffle386": {Name: "invalidpackedfloatshuffle386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64ImmediatePackedBlendCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT immediatepackedblendforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PBLENDW", "BLENDPS", "BLENDPD"} { + fmt.Fprintf(&src, "\t%s $0, X0, X1\n", op) + fmt.Fprintf(&src, "\t%s $255, (AX), X15\n", op) + } + for _, op := range []string{"VPBLENDW", "VPBLENDD", "VBLENDPS", "VBLENDPD"} { + fmt.Fprintf(&src, "\t%s $0, X0, X1, X2\n", op) + fmt.Fprintf(&src, "\t%s $255, (AX), X1, X15\n", op) + fmt.Fprintf(&src, "\t%s $1, Y0, Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s $254, (AX), Y1, Y15\n", op) + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "immediatepackedblendforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "immediate-packed-blend-forms.ll", "immediate-packed-blend-forms.o", ll) +} + +func TestTranslate386ImmediatePackedBlendCompleteGoAssemblerForms(t *testing.T) { + src := ` +TEXT immediatepackedblendforms386(SB),NOSPLIT,$0-0 + PBLENDW $0, X0, X1 + PBLENDW $255, (AX), X7 + BLENDPS $0, X0, X1 + BLENDPS $255, (AX), X7 + BLENDPD $0, X0, X1 + BLENDPD $255, (AX), X7 + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "immediatepackedblendforms386": {Name: "immediatepackedblendforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "immediate-packed-blend-386-forms.ll", "immediate-packed-blend-386-forms.o", ll) +} + +func TestTranslateAMD64ImmediatePackedBlendRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PBLENDW $-1, X0, X1", + "BLENDPS $256, X0, X1", + "BLENDPD.Z $0, X0, X1", + "PBLENDW $0, X20, X1", + "BLENDPS $0, X0, X20", + "VPBLENDW $-1, X0, X1, X2", + "VPBLENDD $256, X0, X1, X2", + "VBLENDPS $0, X0, X1", + "VBLENDPD $0, X0, Y1, Y2", + "VPBLENDW $0, X20, X1, X2", + "VPBLENDD $0, Y0, Y20, Y2", + "VBLENDPS $0, Z0, Z1, Z2", + "VBLENDPD.Z $0, X0, X1, X2", + "VPBLENDW.BCST $0, (AX), X1, X2", + "VPBLENDD $0, X0, X1, K1, X2", + "VBLENDPS $0, X0, (AX), X2", + "VBLENDPD $0, X0, X1, (AX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidimmediatepackedblend(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidimmediatepackedblend": {Name: "invalidimmediatepackedblend", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's immediate packed-blend tables", instruction) + } + }) + } +} + +func TestTranslate386ImmediatePackedBlendRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "PBLENDW $0, X8, X0", + "BLENDPS $0, X0, X8", + "BLENDPD.Z $0, X0, X1", + "VPBLENDW $0, X0, X1, X2", + "VPBLENDD $0, Y0, Y1, Y2", + "VBLENDPS $0, X0, X1, X2", + "VBLENDPD $0, Y0, Y1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidimmediatepackedblend386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidimmediatepackedblend386": {Name: "invalidimmediatepackedblend386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedUnpackCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT packedunpackforms(SB),NOSPLIT,$0-0\n") + legacyMMX := []string{"PUNPCKLBW", "PUNPCKHBW", "PUNPCKLWL", "PUNPCKHWL", "PUNPCKLLQ", "PUNPCKHLQ"} + for _, op := range legacyMMX { + fmt.Fprintf(&src, "\t%s M0, M1\n", op) + fmt.Fprintf(&src, "\t%s (AX), M7\n", op) + fmt.Fprintf(&src, "\t%s X0, X1\n", op) + fmt.Fprintf(&src, "\t%s (AX), X15\n", op) + } + for _, op := range []string{"PUNPCKLQDQ", "PUNPCKHQDQ"} { + fmt.Fprintf(&src, "\t%s X0, X1\n", op) + fmt.Fprintf(&src, "\t%s (AX), X15\n", op) + } + vectorOps := []string{ + "VPUNPCKLBW", "VPUNPCKHBW", "VPUNPCKLWD", "VPUNPCKHWD", + "VPUNPCKLDQ", "VPUNPCKHDQ", "VPUNPCKLQDQ", "VPUNPCKHQDQ", + } + for _, op := range vectorOps { + fmt.Fprintf(&src, "\t%s X0, X1, X2\n", op) + fmt.Fprintf(&src, "\t%s (AX), X1, X15\n", op) + fmt.Fprintf(&src, "\t%s Y0, Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s (AX), Y1, Y15\n", op) + fmt.Fprintf(&src, "\t%s Z0, Z1, Z2\n", op) + fmt.Fprintf(&src, "\t%s (AX), Z1, Z31\n", op) + fmt.Fprintf(&src, "\t%s X20, X21, X22\n", op) + fmt.Fprintf(&src, "\t%s Y20, Y21, K1, Y22\n", op) + fmt.Fprintf(&src, "\t%s.Z (AX), Z21, K2, Z22\n", op) + if strings.Contains(op, "DQ") { + fmt.Fprintf(&src, "\t%s.BCST (AX), X21, X22\n", op) + fmt.Fprintf(&src, "\t%s.BCST (AX), Y21, Y22\n", op) + fmt.Fprintf(&src, "\t%s.BCST (AX), Z21, Z22\n", op) + fmt.Fprintf(&src, "\t%s.BCST.Z (AX), Z21, K3, Z22\n", op) + } + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "packedunpackforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-unpack-forms.ll", "packed-unpack-forms.o", ll) +} + +func TestTranslate386PackedUnpackCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT packedunpackforms386(SB),NOSPLIT,$0-0\n") + for _, op := range []string{ + "PUNPCKLBW", "PUNPCKHBW", "PUNPCKLWL", "PUNPCKHWL", + "PUNPCKLLQ", "PUNPCKHLQ", "PUNPCKLQDQ", "PUNPCKHQDQ", + } { + fmt.Fprintf(&src, "\t%s X0, X1\n", op) + fmt.Fprintf(&src, "\t%s (AX), X7\n", op) + } + for _, op := range []string{ + "VPUNPCKLBW", "VPUNPCKHBW", "VPUNPCKLWD", "VPUNPCKHWD", + "VPUNPCKLDQ", "VPUNPCKHDQ", "VPUNPCKLQDQ", "VPUNPCKHQDQ", + } { + fmt.Fprintf(&src, "\t%s X0, X1, X2\n", op) + fmt.Fprintf(&src, "\t%s (AX), Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s X8, X9, X10\n", op) + fmt.Fprintf(&src, "\t%s Z0, Z1, Z2\n", op) + if strings.Contains(op, "DQ") { + fmt.Fprintf(&src, "\t%s.BCST (AX), Y1, Y2\n", op) + } + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "packedunpackforms386": {Name: "packedunpackforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "packed-unpack-386-forms.ll", "packed-unpack-386-forms.o", ll) +} + +func TestTranslateAMD64PackedUnpackRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PUNPCKLBW.Z X0, X1", + "PUNPCKLWL X20, X1", + "PUNPCKHWL X0, X20", + "PUNPCKLLQ M0, X1", + "PUNPCKHLQ X0, M1", + "PUNPCKLQDQ M0, M1", + "PUNPCKHQDQ Y0, X1", + "VPUNPCKLBW X0, X1", + "VPUNPCKHWD X0, Y1, Y2", + "VPUNPCKLDQ X0, (AX), X2", + "VPUNPCKHQDQ X0, X1, (AX)", + "VPUNPCKLBW X32, X1, X2", + "VPUNPCKHWD Z0, Z1, K0, Z2", + "VPUNPCKLWD.Z Z0, Z1, Z2", + "VPUNPCKHBW.BCST (AX), X1, X2", + "VPUNPCKLWD.BCST (AX), Y1, Y2", + "VPUNPCKLDQ.BCST X0, X1, X2", + "VPUNPCKHQDQ.BCST (AX), X1, Y2", + "VPUNPCKHDQ.SAE X0, X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedunpack(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedunpack": {Name: "invalidpackedunpack", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's packed-unpack tables", instruction) + } + }) + } +} + +func TestTranslate386PackedUnpackRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "PUNPCKLBW M0, M1", + "PUNPCKHWL (AX), M1", + "PUNPCKLQDQ M0, M1", + "PUNPCKHBW X8, X0", + "PUNPCKHLQ X0, X8", + "VPUNPCKLWD Z8, Z1, Z2", + "VPUNPCKHWD Z0, Z8, Z2", + "VPUNPCKLDQ Z0, Z1, Z8", + "VPUNPCKLBW X0, X1, K1, X2", + "VPUNPCKLDQ.Z Z0, Z1, K1, Z2", + "VPUNPCKHQDQ.BCST.Z (AX), Y1, K1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedunpack386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidpackedunpack386": {Name: "invalidpackedunpack386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64QwordPermuteCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT qwordpermuteforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VPERMQ", "VPERMPD"} { + fmt.Fprintf(&src, "\t%s $-128, Y0, Y1\n", op) + fmt.Fprintf(&src, "\t%s $255, (AX), Y15\n", op) + fmt.Fprintf(&src, "\t%s $0, Y20, Y21\n", op) + fmt.Fprintf(&src, "\t%s $1, Z20, Z21\n", op) + fmt.Fprintf(&src, "\t%s $2, Y20, K1, Y21\n", op) + fmt.Fprintf(&src, "\t%s.Z $3, Z20, K2, Z21\n", op) + fmt.Fprintf(&src, "\t%s.BCST $4, (AX), Y21\n", op) + fmt.Fprintf(&src, "\t%s.BCST.Z $5, (AX), K3, Z21\n", op) + fmt.Fprintf(&src, "\t%s Y0, Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s (AX), Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s Z0, Z1, Z2\n", op) + fmt.Fprintf(&src, "\t%s Y20, Y21, Y22\n", op) + fmt.Fprintf(&src, "\t%s (AX), Y21, K1, Y22\n", op) + fmt.Fprintf(&src, "\t%s.Z Z20, Z21, K2, Z22\n", op) + fmt.Fprintf(&src, "\t%s.BCST (AX), Y21, Y22\n", op) + fmt.Fprintf(&src, "\t%s.BCST.Z (AX), Z21, K3, Z22\n", op) + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "qwordpermuteforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "qword-permute-forms.ll", "qword-permute-forms.o", ll) +} + +func TestTranslate386QwordPermuteCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT qwordpermuteforms386(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VPERMQ", "VPERMPD"} { + fmt.Fprintf(&src, "\t%s $-128, Y0, Y1\n", op) + fmt.Fprintf(&src, "\t%s $255, (AX), Y7\n", op) + fmt.Fprintf(&src, "\t%s $0, Y20, Y21\n", op) + fmt.Fprintf(&src, "\t%s $1, Z0, Z1\n", op) + fmt.Fprintf(&src, "\t%s.BCST $2, (AX), Y21\n", op) + fmt.Fprintf(&src, "\t%s.BCST $3, (AX), Z7\n", op) + fmt.Fprintf(&src, "\t%s Y0, Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s (AX), Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s Z0, Z1, Z2\n", op) + fmt.Fprintf(&src, "\t%s Y20, Y21, Y22\n", op) + fmt.Fprintf(&src, "\t%s.BCST (AX), Z1, Z7\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "qwordpermuteforms386": {Name: "qwordpermuteforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "qword-permute-386-forms.ll", "qword-permute-386-forms.o", ll) +} + +func TestTranslateAMD64QwordPermuteRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "VPERMQ $-129, Y0, Y1", + "VPERMPD $256, Y0, Y1", + "VPERMQ $-1, Y20, Y21", + "VPERMPD $-1, Z0, Z1", + "VPERMQ.BCST $-1, (AX), Y1", + "VPERMQ $0, X0, X1", + "VPERMPD X0, X1, X2", + "VPERMQ $0, Y0, Z1", + "VPERMPD Y0, Z1, Z2", + "VPERMQ Y0, (AX), Y2", + "VPERMPD Y0, Y1, (AX)", + "VPERMQ $0, Y0, K0, Y1", + "VPERMPD Z0, Z1, K0, Z2", + "VPERMQ.Z $0, Y0, Y1", + "VPERMPD.Z Y0, Y1, Y2", + "VPERMQ.BCST $0, Y0, Y1", + "VPERMPD.BCST Y0, Y1, Y2", + "VPERMQ.SAE $0, Y0, Y1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidqwordpermute(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidqwordpermute": {Name: "invalidqwordpermute", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's _yvpermq table", instruction) + } + }) + } +} + +func TestTranslate386QwordPermuteRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "VPERMQ $-1, Y20, Y21", + "VPERMPD $0, Z8, Z1", + "VPERMQ $0, Z0, Z8", + "VPERMPD Z8, Z1, Z2", + "VPERMQ Z0, Z8, Z2", + "VPERMPD Z0, Z1, Z8", + "VPERMQ $0, Y0, K1, Y1", + "VPERMPD Z0, Z1, K1, Z2", + "VPERMQ.BCST.Z (AX), Z1, K1, Z2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidqwordpermute386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidqwordpermute386": {Name: "invalidqwordpermute386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedFloatMoveCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 assigns VMOVAPD/APS/UPD/UPS the same 16-row _yvmovapd + // table: bidirectional X/Y/Z register-or-memory moves, EVEX high + // registers, and K1-K7 merge/zero masking for every width and direction. + var src strings.Builder + src.WriteString("TEXT packedfloatmoveforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VMOVAPD", "VMOVAPS", "VMOVUPD", "VMOVUPS"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&src, "\t%s %s0, %s1\n", op, width, width) + fmt.Fprintf(&src, "\t%s %s1, (AX)\n", op, width) + fmt.Fprintf(&src, "\t%s (AX), %s2\n", op, width) + fmt.Fprintf(&src, "\t%s %s20, %s21\n", op, width, width) + fmt.Fprintf(&src, "\t%s %s20, (AX)\n", op, width) + fmt.Fprintf(&src, "\t%s (AX), %s21\n", op, width) + } + fmt.Fprintf(&src, "\t%s Z0, Z1\n", op) + fmt.Fprintf(&src, "\t%s Z1, (AX)\n", op) + fmt.Fprintf(&src, "\t%s (AX), Z2\n", op) + fmt.Fprintf(&src, "\t%s Z20, Z21\n", op) + fmt.Fprintf(&src, "\t%s Z20, (AX)\n", op) + fmt.Fprintf(&src, "\t%s (AX), Z21\n", op) + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&src, "\t%s %s1, K1, %s2\n", op, width, width) + fmt.Fprintf(&src, "\t%s %s1, K2, (AX)\n", op, width) + fmt.Fprintf(&src, "\t%s (AX), K3, %s2\n", op, width) + fmt.Fprintf(&src, "\t%s.Z %s1, K4, %s2\n", op, width, width) + // The Go assembler accepts .Z on masked memory stores. The EVEX + // zeroing bit has no effect on inactive memory lanes. + fmt.Fprintf(&src, "\t%s.Z %s1, K5, (AX)\n", op, width) + fmt.Fprintf(&src, "\t%s.Z (AX), K6, %s2\n", op, width) + } + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "packedfloatmoveforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-float-move-forms.ll", "packed-float-move-forms.o", ll) +} + +func TestTranslate386PackedFloatMoveCompleteGoAssemblerForms(t *testing.T) { + // The 386 encoder exposes X/Y registers 0-31, Z registers 0-7, and all + // three-operand mask rows (unlike EVEX families that need four operands). + var src strings.Builder + src.WriteString("TEXT packedfloatmoveforms386(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VMOVAPD", "VMOVAPS", "VMOVUPD", "VMOVUPS"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&src, "\t%s %s0, %s1\n", op, width, width) + fmt.Fprintf(&src, "\t%s %s20, %s21\n", op, width, width) + fmt.Fprintf(&src, "\t%s %s20, (AX)\n", op, width) + fmt.Fprintf(&src, "\t%s (AX), %s21\n", op, width) + fmt.Fprintf(&src, "\t%s %s20, K1, %s21\n", op, width, width) + fmt.Fprintf(&src, "\t%s.Z %s20, K2, (AX)\n", op, width) + fmt.Fprintf(&src, "\t%s.Z (AX), K3, %s21\n", op, width) + } + fmt.Fprintf(&src, "\t%s Z0, Z7\n", op) + fmt.Fprintf(&src, "\t%s Z7, (AX)\n", op) + fmt.Fprintf(&src, "\t%s (AX), Z7\n", op) + fmt.Fprintf(&src, "\t%s Z0, K1, Z7\n", op) + fmt.Fprintf(&src, "\t%s.Z Z0, K2, (AX)\n", op) + fmt.Fprintf(&src, "\t%s.Z (AX), K3, Z7\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "packedfloatmoveforms386": {Name: "packedfloatmoveforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "packed-float-move-386-forms.ll", "packed-float-move-386-forms.o", ll) +} + +func TestTranslateAMD64PackedFloatMoveRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VMOVAPD X1, Y2", + "VMOVAPS Y1, Z2", + "VMOVUPD Z1, X2", + "VMOVUPS (AX), (BX)", + "VMOVAPD K1, X2", + "VMOVAPS X1, K0, X2", + "VMOVUPD (AX), K0, X2", + "VMOVUPS.Z X1, X2", + "VMOVAPD.BCST (AX), X2", + "VMOVAPS.SAE X1, X2", + "VMOVUPD.RN_SAE X1, X2", + "VMOVUPS X1, K1, Y2", + "VMOVAPD X1, X2, K1", + "VMOVAPS X1", + "VMOVUPD X1, K1, X2, X3", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedfloatmove(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedfloatmove": {Name: "invalidpackedfloatmove", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's _yvmovapd table", instruction) + } + }) + } +} + +func TestTranslate386PackedFloatMoveRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "VMOVAPD Z8, Z1", + "VMOVAPS Z0, Z8", + "VMOVUPD Z8, (AX)", + "VMOVUPS (AX), Z8", + "VMOVAPD Z0, K1, Z8", + "VMOVAPS.Z Z8, K1, (AX)", + "VMOVUPD.Z (AX), K1, Z8", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedfloatmove386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidpackedfloatmove386": {Name: "invalidpackedfloatmove386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateX86EVEXPackedIntegerMoveCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 assigns this complete family the same 12-row _yvmovdqa32 + // table. Each opcode accepts bidirectional X/Y/Z register-or-memory + // moves plus K1-K7 merge/zero masking for every width and direction. + for _, target := range []struct { + goarch string + triple string + zregs []int + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu", zregs: []int{0, 7}}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", zregs: []int{0, 21}}, + } { + t.Run(target.goarch, func(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT evexpackedintegermoveforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VMOVDQA32", "VMOVDQA64", "VMOVDQU8", "VMOVDQU16", "VMOVDQU32", "VMOVDQU64"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&src, "\t%s %s0, %s1\n", op, width, width) + fmt.Fprintf(&src, "\t%s %s20, (AX)\n", op, width) + fmt.Fprintf(&src, "\t%s (AX), %s21\n", op, width) + fmt.Fprintf(&src, "\t%s %s1, K1, %s2\n", op, width, width) + fmt.Fprintf(&src, "\t%s %s1, K2, (AX)\n", op, width) + fmt.Fprintf(&src, "\t%s (AX), K3, %s2\n", op, width) + fmt.Fprintf(&src, "\t%s.Z %s1, K4, %s2\n", op, width, width) + fmt.Fprintf(&src, "\t%s.Z %s1, K5, (AX)\n", op, width) + fmt.Fprintf(&src, "\t%s.Z (AX), K6, %s2\n", op, width) + } + fmt.Fprintf(&src, "\t%s Z%d, Z%d\n", op, target.zregs[0], target.zregs[1]) + fmt.Fprintf(&src, "\t%s Z%d, (AX)\n", op, target.zregs[0]) + fmt.Fprintf(&src, "\t%s (AX), Z%d\n", op, target.zregs[1]) + fmt.Fprintf(&src, "\t%s Z%d, K1, Z%d\n", op, target.zregs[0], target.zregs[1]) + fmt.Fprintf(&src, "\t%s.Z Z%d, K2, (AX)\n", op, target.zregs[0]) + fmt.Fprintf(&src, "\t%s.Z (AX), K3, Z%d\n", op, target.zregs[1]) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "evexpackedintegermoveforms": {Name: "evexpackedintegermoveforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "evex-packed-integer-move-"+target.goarch+".ll", "evex-packed-integer-move-"+target.goarch+".o", ll) + }) + } +} + +func TestTranslateX86EVEXPackedIntegerMoveRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VMOVDQA32 X1, Y2", + "VMOVDQA64 Y1, Z2", + "VMOVDQU8 (AX), (BX)", + "VMOVDQU16 X1, K0, X2", + "VMOVDQU32.Z X1, X2", + "VMOVDQU64.BCST (AX), Z2", + "VMOVDQU8.SAE X1, X2", + "VMOVDQU16 X1, K1, Y2", + "VMOVDQU32 X1", + "VMOVDQA64 X1, K1, X2, X3", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's _yvmovdqa32 table", instruction) + } + }) + } + for _, instruction := range []string{ + "VMOVDQA32 Z8, Z0", + "VMOVDQA64 Z0, Z8", + "VMOVDQU8 Z8, (AX)", + "VMOVDQU16 (AX), Z8", + "VMOVDQU32 Z0, K1, Z8", + "VMOVDQU64.Z (AX), K1, Z8", + } { + file, err := Parse(ArchAMD64, "TEXT bad386(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad386": {Name: "bad386", Ret: Void}}, + }); err == nil { + t.Fatalf("386 Translate accepted architecture-restricted %q", instruction) + } + } +} + +func TestTranslateAMD64PackedSignExtendMoveCompleteGoAssemblerForms(t *testing.T) { + // The complete signed widening family consists of six legacy yxm_q4 + // instructions plus six V instructions. BW/WD/DQ use _yvcvtdq2pd + // (X source for X/Y destinations and Y source for Z); BD/BQ/WQ use + // _yvbroadcastss (X source for every destination width). + var src strings.Builder + src.WriteString("TEXT packedsignextendmoveforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PMOVSXBW", "PMOVSXBD", "PMOVSXBQ", "PMOVSXWD", "PMOVSXWQ", "PMOVSXDQ"} { + fmt.Fprintf(&src, "\t%s X0, X1\n", op) + fmt.Fprintf(&src, "\t%s (AX), X2\n", op) + fmt.Fprintf(&src, "\t%s X15, X14\n", op) + } + for _, op := range []string{"VPMOVSXBW", "VPMOVSXWD", "VPMOVSXDQ"} { + fmt.Fprintf(&src, "\t%s X0, X1\n", op) + fmt.Fprintf(&src, "\t%s (AX), X2\n", op) + fmt.Fprintf(&src, "\t%s X0, Y1\n", op) + fmt.Fprintf(&src, "\t%s (AX), Y2\n", op) + fmt.Fprintf(&src, "\t%s Y0, Z1\n", op) + fmt.Fprintf(&src, "\t%s (AX), Z2\n", op) + fmt.Fprintf(&src, "\t%s X20, X21\n", op) + fmt.Fprintf(&src, "\t%s X20, Y21\n", op) + fmt.Fprintf(&src, "\t%s Y20, Z21\n", op) + fmt.Fprintf(&src, "\t%s X20, K1, X21\n", op) + fmt.Fprintf(&src, "\t%s.Z (AX), K2, X21\n", op) + fmt.Fprintf(&src, "\t%s X20, K3, Y21\n", op) + fmt.Fprintf(&src, "\t%s.Z (AX), K4, Y21\n", op) + fmt.Fprintf(&src, "\t%s Y20, K5, Z21\n", op) + fmt.Fprintf(&src, "\t%s.Z (AX), K6, Z21\n", op) + } + for _, op := range []string{"VPMOVSXBD", "VPMOVSXBQ", "VPMOVSXWQ"} { + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&src, "\t%s X0, %s1\n", op, width) + fmt.Fprintf(&src, "\t%s (AX), %s2\n", op, width) + fmt.Fprintf(&src, "\t%s X20, %s21\n", op, width) + fmt.Fprintf(&src, "\t%s X20, K1, %s21\n", op, width) + fmt.Fprintf(&src, "\t%s.Z (AX), K2, %s21\n", op, width) + } + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "packedsignextendmoveforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-sign-extend-move-forms.ll", "packed-sign-extend-move-forms.o", ll) +} + +func TestTranslate386PackedSignExtendMoveCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT packedsignextendmoveforms386(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PMOVSXBW", "PMOVSXBD", "PMOVSXBQ", "PMOVSXWD", "PMOVSXWQ", "PMOVSXDQ"} { + fmt.Fprintf(&src, "\t%s X0, X7\n", op) + fmt.Fprintf(&src, "\t%s (AX), X7\n", op) + } + for _, op := range []string{"VPMOVSXBW", "VPMOVSXWD", "VPMOVSXDQ"} { + fmt.Fprintf(&src, "\t%s X20, X21\n", op) + fmt.Fprintf(&src, "\t%s X20, Y21\n", op) + fmt.Fprintf(&src, "\t%s Y20, Z7\n", op) + fmt.Fprintf(&src, "\t%s X20, K1, Y21\n", op) + fmt.Fprintf(&src, "\t%s.Z (AX), K2, Z7\n", op) + } + for _, op := range []string{"VPMOVSXBD", "VPMOVSXBQ", "VPMOVSXWQ"} { + fmt.Fprintf(&src, "\t%s X20, X21\n", op) + fmt.Fprintf(&src, "\t%s X20, Y21\n", op) + fmt.Fprintf(&src, "\t%s X20, Z7\n", op) + fmt.Fprintf(&src, "\t%s X20, K1, Y21\n", op) + fmt.Fprintf(&src, "\t%s.Z (AX), K2, Z7\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "packedsignextendmoveforms386": {Name: "packedsignextendmoveforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "packed-sign-extend-move-386-forms.ll", "packed-sign-extend-move-386-forms.o", ll) +} + +func TestTranslateAMD64PackedSignExtendMoveRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PMOVSXBW X16, X1", + "PMOVSXBD X1, X16", + "PMOVSXBQ Y1, X2", + "PMOVSXWD X1, Y2", + "PMOVSXWQ X1, (AX)", + "PMOVSXDQ.Z X1, X2", + "PMOVSXBW X1, K1, X2", + "VPMOVSXBW Y1, Y2", + "VPMOVSXWD X1, Z2", + "VPMOVSXDQ Z1, Z2", + "VPMOVSXBD Y1, Z2", + "VPMOVSXBQ Y1, Y2", + "VPMOVSXWQ Z1, X2", + "VPMOVSXBW X1, (AX)", + "VPMOVSXBD (AX), (BX)", + "VPMOVSXBQ X1, K0, Y2", + "VPMOVSXWD.Z X1, Y2", + "VPMOVSXDQ.BCST (AX), Y2", + "VPMOVSXWQ.SAE X1, Z2", + "VPMOVSXBW.RN_SAE X1, Y2", + "VPMOVSXBD X1", + "VPMOVSXBQ X1, K1, Y2, Y3", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedsignextendmove(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedsignextendmove": {Name: "invalidpackedsignextendmove", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's signed-extension move tables", instruction) + } + }) + } +} + +func TestTranslate386PackedSignExtendMoveRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "PMOVSXBW X8, X1", + "PMOVSXBD X1, X8", + "PMOVSXBQ X15, X7", + "VPMOVSXBW Y1, Z8", + "VPMOVSXWD (AX), Z8", + "VPMOVSXDQ Y20, K1, Z8", + "VPMOVSXBD X20, Z8", + "VPMOVSXBQ.Z (AX), K1, Z8", + "VPMOVSXWQ X20, K1, Z8", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedsignextendmove386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidpackedsignextendmove386": {Name: "invalidpackedsignextendmove386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64MOVDFromXRegister(t *testing.T) { + src := ` +TEXT movdfromx(SB),NOSPLIT,$0-0 + PXOR X12, X12 + MOVD X12, DX + RET +` + translateAMD64EcosystemCase(t, src, "movdfromx") +} + +func TestTranslateAMD64MOVDAliasCompleteGo127Forms(t *testing.T) { + // cmd/asm aliases MOVD to AMOVQ on x86. These cover every ymovq operand + // class that the alias can select in 64-bit mode: GP/immediate/memory, + // MMX/memory/GP/XMM, and XMM/memory/GP/XMM. + src := ` +TEXT movdaliasforms(SB),NOSPLIT,$0-0 + MOVD AX, BX + MOVD $1, AX + MOVD AX, 8(BX) + MOVD 8(BX), AX + MOVD (BX), M0 + MOVD M0, 8(BX) + MOVD AX, M1 + MOVD M1, AX + MOVD X0, M2 + MOVD M2, M3 + MOVD AX, X1 + MOVD 24(SP), X9 + MOVD X1, AX + MOVD X9, 32(SP) + MOVD X1, X2 + RET +` + ll := translateAMD64EcosystemCase(t, src, "movdaliasforms") + if !strings.Contains(ll, "load i64") || !strings.Contains(ll, "store i64") { + t.Fatalf("MOVD alias did not preserve MOVQ-width memory semantics:\n%s", ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "movd-alias-forms.ll", "movd-alias-forms.o", ll) +} + +func TestTranslateAMD64MOVDAliasRejectsFormsOutsideGo127Ymovq(t *testing.T) { + for _, instruction := range []string{ + "MOVD $1, X0", + "MOVD M0, X0", + "MOVD X0, X1, X2", + "MOVD.Z X0, X1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT badmovd(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"badmovd": {Name: "badmovd", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's MOVD/ymovq forms", instruction) + } + }) + } +} + +func TestTranslateAMD64LegacyPrefetchFamilyCompleteGo127Forms(t *testing.T) { + src := ` +TEXT prefetchforms(SB),NOSPLIT,$0-0 + PREFETCHNTA (AX) + PREFETCHT0 8(BX) + PREFETCHT1 source(SB) + PREFETCHT2 16(SP) + RET +` + ll := translateAMD64EcosystemCase(t, src, "prefetchforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "prefetch-forms.ll", "prefetch-forms.o", ll) +} + +func TestTranslateAMD64LegacyPrefetchFamilyRejectsNonMemoryForms(t *testing.T) { + for _, instruction := range []string{ + "PREFETCHNTA", + "PREFETCHT0 AX", + "PREFETCHT1 $1", + "PREFETCHT2 (AX), (BX)", + "PREFETCHT0.Z (AX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT badprefetch(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"badprefetch": {Name: "badprefetch", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's yprefetch table", instruction) + } + }) + } +} + +func TestTranslateAMD64ArithmeticDisplacementExpression(t *testing.T) { + ll := translateAMD64EcosystemCase(t, ` +TEXT arithmeticdisplacement(SB),NOSPLIT,$32-0 + ADDQ 0+(1*16)(BP), R10 + MOVQ (-16+8)(SP), AX + RET +`, "arithmeticdisplacement") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "arithmetic-displacement.ll", "arithmetic-displacement.o", ll) +} + +func TestTranslateAMD64GoTLSPseudoRegisterForms(t *testing.T) { + ll := translateAMD64EcosystemCase(t, ` +TEXT tlsforms(SB),NOSPLIT,$0-0 + MOVQ TLS, CX + MOVQ 0(CX)(TLS*1), BX + MOVQ 8(TLS), DX + RET +`, "tlsforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "tls-forms.ll", "tls-forms.o", ll) +} + +func TestTranslateAMD64LegacyIntegerToFloatConversionFamilyCompleteGo127Forms(t *testing.T) { + ll := translateAMD64EcosystemCase(t, ` +TEXT integerfloatconversions(SB),NOSPLIT,$0-0 + CVTSL2SS AX, X0 + CVTSL2SS 4(BX), X1 + CVTSL2SD CX, X2 + CVTSL2SD 8(BX), X3 + CVTSQ2SS SI, X4 + CVTSQ2SS 16(BX), X5 + CVTSQ2SD DI, X6 + CVTSQ2SD 24(BX), X7 + CVTPL2PS X0, X1 + CVTPL2PS 32(BX), X2 + CVTPL2PS M0, X3 + CVTPL2PD X4, X5 + CVTPL2PD 48(BX), X6 + CVTPL2PD M1, X7 + RET +`, "integerfloatconversions") + for _, want := range []string{"sitofp i32", "sitofp i64", "sitofp <4 x i32>", "sitofp <2 x i32>"} { + if !strings.Contains(ll, want) { + t.Fatalf("missing %q in integer-to-float conversion IR:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "integer-float-conversions.ll", "integer-float-conversions.o", ll) +} + +func TestTranslateAMD64LegacyIntegerToFloatConversionFamilyRejectsNonGoForms(t *testing.T) { + for _, instruction := range []string{ + "CVTSL2SS $1, X0", + "CVTSQ2SS X0, X1", + "CVTSQ2SD AX, Y0", + "CVTPL2PS AX, X0", + "CVTPL2PD X0, Y0", + "CVTPL2PS.Z X0, X1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT badconversion(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"badconversion": {Name: "badconversion", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's legacy integer-to-float tables", instruction) + } + }) + } +} + +func TestTranslateAMD64ScalarFloatBroadcastFamilyCompleteGo127Forms(t *testing.T) { + ll := translateAMD64EcosystemCase(t, ` +TEXT scalarfloatbroadcasts(SB),NOSPLIT,$0-0 + VBROADCASTSS X0, X1 + VBROADCASTSS 4(AX), Y1 + VBROADCASTSS X16, Z17 + VBROADCASTSS X16, K1, X17 + VBROADCASTSS.Z 8(AX), K2, Y18 + VBROADCASTSS 12(AX), K3, Z19 + VBROADCASTSD X0, Y1 + VBROADCASTSD 8(AX), Z1 + VBROADCASTSD X16, K1, Y17 + VBROADCASTSD.Z 16(AX), K2, Z18 + RET +`, "scalarfloatbroadcasts") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "scalar-float-broadcasts.ll", "scalar-float-broadcasts.o", ll) +} + +func TestTranslateAMD64ScalarFloatBroadcastFamilyRejectsNonGoForms(t *testing.T) { + for _, instruction := range []string{ + "VBROADCASTSS AX, X0", + "VBROADCASTSD X0, X1", + "VBROADCASTSS.Z X0, Y1", + "VBROADCASTSD X0, K0, Y1", + "VBROADCASTSS.BCST 4(AX), Y1", + "VBROADCASTSD X0, K1, K2, Y1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT badbroadcast(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"badbroadcast": {Name: "badbroadcast", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scalar broadcast tables", instruction) + } + }) + } +} + +func TestTranslateAMD64DwordToQwordMultiplyFamilyCompleteGo127Forms(t *testing.T) { + ll := translateAMD64EcosystemCase(t, ` +TEXT dwordqwordmultiply(SB),NOSPLIT,$0-0 + PMULDQ X0, X1 + PMULDQ 16(AX), X2 + PMULULQ M0, M1 + PMULULQ 24(AX), M2 + PMULULQ X0, X1 + PMULULQ 32(AX), X2 + VPMULDQ X0, X1, X2 + VPMULDQ Y0, Y1, Y2 + VPMULDQ Z0, Z1, Z2 + VPMULDQ Z0, Z1, K1, Z2 + VPMULDQ.Z Z0, Z1, K2, Z2 + VPMULDQ.BCST 40(AX), Z1, Z2 + VPMULDQ.BCST.Z 48(AX), Z1, K3, Z2 + VPMULUDQ X0, X1, X2 + VPMULUDQ Y0, Y1, Y2 + VPMULUDQ Z0, Z1, Z2 + VPMULUDQ Z0, Z1, K1, Z2 + VPMULUDQ.Z Z0, Z1, K2, Z2 + VPMULUDQ.BCST 56(AX), Z1, Z2 + VPMULUDQ.BCST.Z 64(AX), Z1, K3, Z2 + RET +`, "dwordqwordmultiply") + for _, want := range []string{"sext <", "zext <", "mul <2 x i64>", "mul <4 x i64>", "mul <8 x i64>"} { + if !strings.Contains(ll, want) { + t.Fatalf("missing %q in dword-to-qword multiply IR:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "dword-qword-multiply.ll", "dword-qword-multiply.o", ll) +} + +func TestTranslateAMD64DwordToQwordMultiplyFamilyRejectsNonGoForms(t *testing.T) { + for _, instruction := range []string{ + "PMULDQ M0, M1", + "PMULULQ Y0, Y1", + "VPMULUDQ X0, Y1, X2", + "VPMULDQ Z0, Z1, K0, Z2", + "VPMULUDQ.Z Z0, Z1, Z2", + "VPMULDQ.BCST Z0, Z1, Z2", + "VPMULUDQ.Z.BCST 8(AX), Z1, K1, Z2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT badmultiply(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"badmultiply": {Name: "badmultiply", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's dword-to-qword multiply tables", instruction) + } + }) + } +} + +func TestTranslate386NewlyDiscoveredX86FamiliesCompleteGo127Forms(t *testing.T) { + // Keep the 386 matrix explicit: x86 opcode names are shared with amd64, but + // cmd/asm's operand tables and available registers differ in 32-bit mode. + src := ` +TEXT discoveredx86forms386(SB),NOSPLIT,$0-0 + MOVD (AX), X0 + MOVD X0, 8(AX) + MOVD X0, X1 + MOVD 16(AX), M0 + MOVD M0, 24(AX) + MOVD X0, M1 + CVTSL2SS AX, X0 + CVTSL2SS 4(BX), X1 + CVTSL2SD CX, X2 + CVTSL2SD 8(BX), X3 + CVTPL2PS X0, X1 + CVTPL2PS 16(BX), X2 + CVTPL2PS M0, X3 + CVTPL2PD X4, X5 + CVTPL2PD 24(BX), X6 + CVTPL2PD M1, X7 + VBROADCASTSS X0, X1 + VBROADCASTSS 4(AX), Y1 + VBROADCASTSS 8(AX), Z1 + VBROADCASTSD X0, Y2 + VBROADCASTSD 16(AX), Z2 + PMULDQ X0, X1 + PMULDQ 16(AX), X2 + PMULULQ X0, X1 + PMULULQ 24(AX), X2 + VPMULDQ X0, X1, X2 + VPMULDQ Y0, Y1, Y2 + VPMULDQ Z0, Z1, Z2 + VPMULUDQ X0, X1, X2 + VPMULUDQ Y0, Y1, Y2 + VPMULUDQ Z0, Z1, Z2 + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "discoveredx86forms386": {Name: "discoveredx86forms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "discovered-x86-386-forms.ll", "discovered-x86-386-forms.o", ll) +} + +func TestTranslate386NewlyDiscoveredX86FamiliesRejectArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "MOVD AX, BX", + "MOVD M0, M1", + "MOVD M0, X0", + "CVTSQ2SS AX, X0", + "CVTSQ2SD 8(AX), X0", + "PMULULQ M0, M1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad386discovered(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "bad386discovered": {Name: "bad386discovered", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for GOARCH=386", instruction) + } + }) + } +} + +func TestTranslateAMD64MOVQFromXRegisterToFrameResult(t *testing.T) { + src := ` +TEXT vectorret(SB),NOSPLIT,$0-8 + PXOR X0, X0 + MOVQ X0, vectorGlobal<>(SB) + MOVQ X0, ret+0(FP) + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"vectorret": { + Name: "vectorret", + Ret: I64, + Frame: FrameLayout{Results: []FrameSlot{{ + Offset: 0, + Type: I64, + Index: 0, + Field: -1, + }}}, + }}, + }); err != nil { + t.Fatal(err) + } +} + +func TestTranslateAMD64X87Arithmetic(t *testing.T) { + src := ` +TEXT x87amd64(SB),NOSPLIT,$0-0 + FLDZ + FLD1 + FADDD F1, F0 + FSUBD F1, F0 + FLDCW 0(SP) + RET +` + translateAMD64EcosystemCase(t, src, "x87amd64") +} + +func TestTranslateAMD64FuzzerBitTestAndVectorSubtract(t *testing.T) { + src := ` +TEXT fuzzops(SB),NOSPLIT,$0-0 + BTL $16, CX + JCS done + VPSUBB Y0, Y1, Y2 +done: + RET +` + translateAMD64EcosystemCase(t, src, "fuzzops") +} + +func TestTranslateX86DivisionAndFrameArithmetic(t *testing.T) { + amd64Source := ` +TEXT divmod(SB),NOSPLIT,$0-32 + MOVQ $0, DX + MOVQ a+0(FP), AX + DIVQ b+8(FP) + MOVQ AX, quo+16(FP) + MOVQ DX, rem+24(FP) + RET +` + translateX86FrameCase(t, amd64Source, "amd64", "x86_64-unknown-linux-gnu", "divmod") + + x86Source := ` +TEXT mulparts(SB),NOSPLIT,$0-32 + MOVL a+0(FP), AX + MULL b+8(FP) + MOVL AX, hi+16(FP) + ADDL DX, hi+16(FP) + RET +` + translateX86FrameCase(t, x86Source, "386", "i386-unknown-linux-gnu", "mulparts") +} + +func TestTranslateAMD64LegacyBranchHintAndSignedDivision(t *testing.T) { + src := ` +TEXT signeddivmod(SB),NOSPLIT,$0-32 + MOVQ a+0(FP), AX + MOVQ b+8(FP), CX + CMPQ CX, $-1 + JEQ $1, special + CQO + IDIVQ CX + JMP done +special: + NEGQ AX + MOVQ $0, DX +done: + MOVQ AX, quo+16(FP) + MOVQ DX, rem+24(FP) + RET +` + translateX86FrameCase(t, src, "amd64", "x86_64-unknown-linux-gnu", "signeddivmod") +} + +func TestTranslateAMD64LoopBranch(t *testing.T) { + src := ` +TEXT countedloop(SB),NOSPLIT,$0-0 + MOVQ $2, CX +loop: + LOOP loop + RET +` + translateAMD64EcosystemCase(t, src, "countedloop") +} + +func TestTranslateAMD64RawDataDirectives(t *testing.T) { + src := ` +TEXT rawencoding(SB),NOSPLIT,$0-0 + LONG $0xe77da1c4 + QUAD $0x4109048d47d18941 + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawencoding": {Name: "rawencoding", Ret: Void}}}); err == nil || !strings.Contains(err.Error(), "decode raw x86 directive group") { + t.Fatalf("reachable opaque data directives must fail closed, got %v", err) + } +} + +func TestTranslateAMD64HighQuadwordInterleave(t *testing.T) { + src := ` +TEXT highquadword(SB),NOSPLIT,$0-0 + PUNPCKHQDQ X1, X0 + VPUNPCKHQDQ Y0, Y1, Y2 + RET +` + translateAMD64EcosystemCase(t, src, "highquadword") +} + +func TestTranslateAMD64AdditionalAVXUnpackAndBroadcastFamilies(t *testing.T) { + src := ` +TEXT avxunpackbroadcast(SB),NOSPLIT,$0-0 + VPUNPCKLQDQ X0, X1, X2 + VPUNPCKLQDQ Y0, Y1, Y2 + VPUNPCKLDQ X0, X1, X2 + VPUNPCKLDQ Y0, Y1, Y2 + VPUNPCKHDQ X0, X1, X2 + VPUNPCKHDQ Y0, Y1, Y2 + VPBROADCASTD (AX), X3 + VPBROADCASTD (AX), Y3 + VPSHUFD $0x4e, (AX), X4 + VPSHUFD $0x4e, X0, X4 + VPSHUFD $0x4e, (AX), Z4 + VPSLLD $12, X5, X13 + VPSRLD $7, (AX), X13 + VPSLLD $12, Y5, Y13 + VPSLLD $12, Z5, Z13 + RET +` + translateAMD64EcosystemCase(t, src, "avxunpackbroadcast") +} + +func TestTranslateAMD64DwordShuffleCompleteGoAssemblerForms(t *testing.T) { + src := ` +TEXT dwordshuffleforms(SB),NOSPLIT,$0-0 + PSHUFD $1, X1, X2 + PSHUFD $1, (AX), X2 + PSHUFL $1, X1, X2 + VPSHUFD $1, X1, X2 + VPSHUFD $1, (AX), X2 + VPSHUFD $1, Y1, Y2 + VPSHUFD $1, (AX), Y2 + VPSHUFD $1, Z1, Z2 + VPSHUFD $1, (AX), Z2 + VPSHUFD $1, X1, K1, X2 + VPSHUFD.Z $1, (AX), K1, X2 + VPSHUFD $1, Y1, K1, Y2 + VPSHUFD.Z $1, (AX), K1, Y2 + VPSHUFD $1, Z1, K1, Z2 + VPSHUFD.Z $1, (AX), K1, Z2 + RET +` + translateAMD64EcosystemCase(t, src, "dwordshuffleforms") +} + +func TestTranslateAMD64CanonicalPackedByteShiftAliases(t *testing.T) { + src := ` +TEXT packedbyteshifts(SB),NOSPLIT,$0-0 + PSLLO $4, X0 + PSRLO $4, X0 + RET +` + translateAMD64EcosystemCase(t, src, "packedbyteshifts") +} + +func TestTranslateAMD64PackedUniformShiftCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's x86 assembler assigns all of these instructions the same + // _yvpslld operand-format table. Keep this test in lockstep with that + // family instead of adding only the form first observed in a dependency. + for _, op := range []string{ + "VPSLLD", "VPSLLQ", "VPSLLW", + "VPSRAD", "VPSRAW", + "VPSRLD", "VPSRLQ", "VPSRLW", + } { + var src strings.Builder + fmt.Fprintf(&src, "TEXT uniformshift%s(SB),NOSPLIT,$0-0\n", op) + for _, operands := range []string{ + "$3, X1, X2", "$-1, X1, X2", "$3, (AX), X2", + "$3, Y1, Y2", "$-1, Y1, Y2", "$3, (AX), Y2", + "$3, Z1, Z2", "$3, (AX), Z2", + "X0, X1, X2", "(AX), X1, X2", + "X0, Y1, Y2", "(AX), Y1, Y2", + "X0, Z1, Z2", "(AX), Z1, Z2", + "$3, X1, K1, X2", "$3, (AX), K1, X2", + "$3, Y1, K1, Y2", "$3, (AX), K1, Y2", + "$3, Z1, K1, Z2", "$3, (AX), K1, Z2", + "X0, X1, K1, X2", "(AX), X1, K1, X2", + "X0, Y1, K1, Y2", "(AX), Y1, K1, Y2", + "X0, Z1, K1, Z2", "(AX), Z1, K1, Z2", + } { + fmt.Fprintf(&src, "\t%s %s\n", op, operands) + } + for _, operands := range []string{ + "$3, X1, K1, X2", "$3, (AX), K1, X2", + "$3, Y1, K1, Y2", "$3, (AX), K1, Y2", + "$3, Z1, K1, Z2", "$3, (AX), K1, Z2", + "X0, X1, K1, X2", "(AX), X1, K1, X2", + "X0, Y1, K1, Y2", "(AX), Y1, K1, Y2", + "X0, Z1, K1, Z2", "(AX), Z1, K1, Z2", + } { + fmt.Fprintf(&src, "\t%s.Z %s\n", op, operands) + } + src.WriteString("\tRET\n") + translateAMD64EcosystemCase(t, src.String(), "uniformshift"+op) + } +} + +func TestTranslateAMD64PackedIntegerCompareCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 assigns all eight equality/greater-than variants the shared + // _yvpcmpeqb table. VEX writes X/Y vectors; EVEX compares X/Y/Z lanes into + // K registers, optionally masked by K1-K7. D/Q also permit memory broadcast. + ops := []string{ + "VPCMPEQB", "VPCMPEQW", "VPCMPEQD", "VPCMPEQQ", + "VPCMPGTB", "VPCMPGTW", "VPCMPGTD", "VPCMPGTQ", + } + forms := []string{ + "X1, X2, X3", "(AX), X2, X3", + "Y1, Y2, Y3", "(AX), Y2, Y3", + "X1, X2, K3", "(AX), X2, K3", + "X1, X2, K1, K3", "(AX), X2, K1, K3", + "Y1, Y2, K3", "(AX), Y2, K3", + "Y1, Y2, K1, K3", "(AX), Y2, K1, K3", + "Z1, Z2, K3", "(AX), Z2, K3", + "Z1, Z2, K1, K3", "(AX), Z2, K1, K3", + } + var src strings.Builder + src.WriteString("TEXT packedintegercompareforms(SB),NOSPLIT,$0-0\n") + for _, op := range ops { + for _, form := range forms { + fmt.Fprintf(&src, "\t%s %s\n", op, form) + } + if strings.HasSuffix(op, "D") || strings.HasSuffix(op, "Q") { + for _, form := range []string{ + "(AX), X2, K3", "(AX), X2, K1, K3", + "(AX), Y2, K3", "(AX), Y2, K1, K3", + "(AX), Z2, K3", "(AX), Z2, K1, K3", + } { + fmt.Fprintf(&src, "\t%s.BCST %s\n", op, form) + } + } + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "packedintegercompareforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-integer-compare-forms.ll", "packed-integer-compare-forms.o", ll) +} + +func TestTranslateAMD64PackedIntegerCompareRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPCMPEQB Z1, Z2, Z3", + "VPCMPEQW X1, Y2, Y3", + "VPCMPEQD X1, X2, K0, K3", + "VPCMPEQQ.Z X1, X2, K1, K3", + "VPCMPGTB.BCST (AX), X2, K3", + "VPCMPGTW.SAE X1, X2, K3", + "VPCMPGTD.BCST X1, X2, K3", + "VPCMPGTQ.BCST (AX), X2, X3", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedintegercompare(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedintegercompare": {Name: "invalidpackedintegercompare", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's _yvpcmpeqb table", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedAndNotCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 defines the whole AND-NOT family across three operand tables: + // PANDN's ymm table (MMX/XMM), VPANDN's _yvaddsubpd table (X/Y VEX), + // and VPANDND/Q's _yvblendmpd table (X/Y/Z EVEX with optional K1-K7 + // masking and zeroing). Only the D/Q EVEX variants permit memory broadcast. + src := ` +TEXT packedandnotforms(SB),NOSPLIT,$0-0 + PANDN M1, M2 + PANDN (AX), M2 + PANDN X1, X2 + PANDN (AX), X2 + VPANDN X1, X2, X3 + VPANDN (AX), X2, X3 + VPANDN Y1, Y2, Y3 + VPANDN (AX), Y2, Y3 + VPANDND X1, X2, X3 + VPANDND (AX), X2, X3 + VPANDND X1, X2, K1, X3 + VPANDND.Z (AX), X2, K1, X3 + VPANDND Y1, Y2, Y3 + VPANDND (AX), Y2, Y3 + VPANDND Y1, Y2, K1, Y3 + VPANDND.Z (AX), Y2, K1, Y3 + VPANDND Z1, Z2, Z3 + VPANDND (AX), Z2, Z3 + VPANDND Z1, Z2, K1, Z3 + VPANDND.Z (AX), Z2, K1, Z3 + VPANDND.BCST (AX), X2, X3 + VPANDND.BCST (AX), X2, K1, X3 + VPANDND.BCST.Z (AX), X2, K1, X3 + VPANDND.BCST (AX), Y2, Y3 + VPANDND.BCST (AX), Y2, K1, Y3 + VPANDND.BCST.Z (AX), Y2, K1, Y3 + VPANDND.BCST (AX), Z2, Z3 + VPANDND.BCST (AX), Z2, K1, Z3 + VPANDND.BCST.Z (AX), Z2, K1, Z3 + VPANDNQ X1, X2, X3 + VPANDNQ (AX), X2, X3 + VPANDNQ X1, X2, K1, X3 + VPANDNQ.Z (AX), X2, K1, X3 + VPANDNQ Y1, Y2, Y3 + VPANDNQ (AX), Y2, Y3 + VPANDNQ Y1, Y2, K1, Y3 + VPANDNQ.Z (AX), Y2, K1, Y3 + VPANDNQ Z1, Z2, Z3 + VPANDNQ (AX), Z2, Z3 + VPANDNQ Z1, Z2, K1, Z3 + VPANDNQ.Z (AX), Z2, K1, Z3 + VPANDNQ.BCST (AX), X2, X3 + VPANDNQ.BCST (AX), X2, K1, X3 + VPANDNQ.BCST.Z (AX), X2, K1, X3 + VPANDNQ.BCST (AX), Y2, Y3 + VPANDNQ.BCST (AX), Y2, K1, Y3 + VPANDNQ.BCST.Z (AX), Y2, K1, Y3 + VPANDNQ.BCST (AX), Z2, Z3 + VPANDNQ.BCST (AX), Z2, K1, Z3 + VPANDNQ.BCST.Z (AX), Z2, K1, Z3 + RET +` + ll := translateAMD64EcosystemCase(t, src, "packedandnotforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-and-not-forms.ll", "packed-and-not-forms.o", ll) +} + +func TestTranslateAMD64PackedAndNotRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "PANDN Y1, Y2", + "VPANDN Z1, Z2, Z3", + "VPANDN.X Z1, Z2, Z3", + "VPANDND X1, Y2, Y3", + "VPANDND X1, X2, K0, X3", + "VPANDND.Z X1, X2, X3", + "VPANDND.SAE X1, X2, K1, X3", + "VPANDND.BCST X1, X2, X3", + "VPANDNQ.BCST (AX), X2, Y3", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedandnot(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedandnot": {Name: "invalidpackedandnot", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's PANDN/VPANDN operand tables", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedScalarBroadcastCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 assigns VPBROADCASTB/W/D/Q the same _yvpbroadcastb table. + // VEX broadcasts X/m to X/Y; EVEX adds GP and X/m sources, X/Y/Z + // destinations, K1-K7 merge masking, and masked .Z zeroing. + forms := []string{ + "X1, X2", "(AX), X2", "table<>(SB), X2", "0, X2", + "X1, Y2", "(AX), Y2", "table<>(SB), Y2", "0x1234, Y2", + "AX, X2", "AX, Y2", "AX, Z2", + "X1, Z2", "(AX), Z2", + "AX, K1, X2", "X1, K1, X2", "(AX), K1, X2", + "AX, K1, Y2", "X1, K1, Y2", "(AX), K1, Y2", + "AX, K1, Z2", "X1, K1, Z2", "(AX), K1, Z2", + } + zeroForms := []string{ + "AX, K1, X2", "X1, K1, X2", "(AX), K1, X2", + "AX, K1, Y2", "X1, K1, Y2", "(AX), K1, Y2", + "AX, K1, Z2", "X1, K1, Z2", "(AX), K1, Z2", + } + var src strings.Builder + src.WriteString("TEXT packedscalarbroadcastforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VPBROADCASTB", "VPBROADCASTW", "VPBROADCASTD", "VPBROADCASTQ"} { + for _, form := range forms { + fmt.Fprintf(&src, "\t%s %s\n", op, form) + } + for _, form := range zeroForms { + fmt.Fprintf(&src, "\t%s.Z %s\n", op, form) + } + } + src.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, "amd64", strings.Replace(src.String(), ",NOSPLIT", "", 1), true) + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "packedscalarbroadcastforms": {Name: "packedscalarbroadcastforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "packed-scalar-broadcast-forms-"+target.name+".ll", "packed-scalar-broadcast-forms-"+target.name+".o", ll) + }) + } +} + +func TestTranslateAMD64PackedScalarBroadcastRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPBROADCASTB $1, X2", + "VPBROADCASTW Y1, Y2", + "VPBROADCASTD X1, K0, X2", + "VPBROADCASTQ X1, AX", + "VPBROADCASTB.Z X1, X2", + "VPBROADCASTW.BCST (AX), X2", + "VPBROADCASTD.SAE X1, K1, X2", + "VPBROADCASTQ X1, K1, Y2, Z3", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedscalarbroadcast(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedscalarbroadcast": {Name: "invalidpackedscalarbroadcast", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's _yvpbroadcastb table", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedIntegerAddCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's legacy ymm table gives these instructions MMX and XMM forms. + for _, op := range []string{"PADDB", "PADDL", "PADDSB", "PADDSW", "PADDUSB", "PADDUSW", "PADDW"} { + src := fmt.Sprintf(` +TEXT legacy%sforms(SB),NOSPLIT,$0-0 + %s M1, M2 + %s (AX), M2 + %s X1, X2 + %s (AX), X2 + RET +`, op, op, op, op, op) + translateAMD64EcosystemCase(t, src, "legacy"+op+"forms") + } + // PADDQ is deliberately narrower in Go's legacy yxm table: XMM only. + translateAMD64EcosystemCase(t, ` +TEXT legacyPADDQforms(SB),NOSPLIT,$0-0 + PADDQ X1, X2 + PADDQ (AX), X2 + RET +`, "legacyPADDQforms") + + // Every AVX variant shares _yvandnpd: X/Y/Z register-or-memory inputs, + // optional K1-K7 merge/zero masks. D/Q additionally enable broadcast. + commonForms := []string{ + "X1, X2, X3", "(AX), X2, X3", + "X1, X2, K1, X3", "(AX), X2, K1, X3", + "Y1, Y2, Y3", "(AX), Y2, Y3", + "Y1, Y2, K1, Y3", "(AX), Y2, K1, Y3", + "Z1, Z2, Z3", "(AX), Z2, Z3", + "Z1, Z2, K1, Z3", "(AX), Z2, K1, Z3", + } + maskedForms := []string{ + "X1, X2, K1, X3", "(AX), X2, K1, X3", + "Y1, Y2, K1, Y3", "(AX), Y2, K1, Y3", + "Z1, Z2, K1, Z3", "(AX), Z2, K1, Z3", + } + var src strings.Builder + src.WriteString("TEXT packedintegeraddforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{ + "VPADDB", "VPADDW", "VPADDD", "VPADDQ", + "VPADDSB", "VPADDSW", "VPADDUSB", "VPADDUSW", + } { + for _, form := range commonForms { + fmt.Fprintf(&src, "\t%s %s\n", op, form) + } + for _, form := range maskedForms { + fmt.Fprintf(&src, "\t%s.Z %s\n", op, form) + } + if op == "VPADDD" || op == "VPADDQ" { + for _, form := range []string{ + "(AX), X2, X3", "(AX), X2, K1, X3", + "(AX), Y2, Y3", "(AX), Y2, K1, Y3", + "(AX), Z2, Z3", "(AX), Z2, K1, Z3", + } { + fmt.Fprintf(&src, "\t%s.BCST %s\n", op, form) + } + for _, form := range []string{ + "(AX), X2, K1, X3", "(AX), Y2, K1, Y3", "(AX), Z2, K1, Z3", + } { + fmt.Fprintf(&src, "\t%s.BCST.Z %s\n", op, form) + } + } + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "packedintegeraddforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-integer-add-forms.ll", "packed-integer-add-forms.o", ll) +} + +func TestTranslateAMD64PackedIntegerAddRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "PADDQ M1, M2", + "PADDB Y1, Y2", + "VPADDB X1, Y2, Y3", + "VPADDW X1, X2, K0, X3", + "VPADDD.Z X1, X2, X3", + "VPADDQ.BCST X1, X2, X3", + "VPADDSB.BCST (AX), X2, X3", + "VPADDSW.SAE X1, X2, K1, X3", + "VPADDUSB X1, X2, K1, X3, X4", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedintegeradd(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedintegeradd": {Name: "invalidpackedintegeradd", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's packed-add tables", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedIntegerSubtractCompleteGoAssemblerForms(t *testing.T) { + // All eight legacy instructions use yxm: X/m128, X. Unlike the packed-add + // family, none of these legacy subtract spellings has an MMX row. + var src strings.Builder + src.WriteString("TEXT packedintegersubtractforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PSUBB", "PSUBL", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW"} { + fmt.Fprintf(&src, "\t%s X1, X15\n", op) + fmt.Fprintf(&src, "\t%s (AX), X15\n", op) + } + + // All eight V spellings share _yvandnpd. Exercise every VEX/EVEX width, + // both register and memory members of each rm class, high EVEX registers, + // K merge/zero masks, and the D/Q-only broadcast rows. + commonForms := []string{ + "X1, X2, X3", "(AX), X2, X3", + "Y1, Y2, Y3", "(AX), Y2, Y3", + "Z1, Z2, Z3", "(AX), Z2, Z3", + "X20, X21, X22", "Y20, Y21, Y22", "Z20, Z21, Z22", + } + maskedForms := []string{ + "X20, X21, K1, X22", "(AX), X21, K1, X22", + "Y20, Y21, K1, Y22", "(AX), Y21, K1, Y22", + "Z20, Z21, K1, Z22", "(AX), Z21, K1, Z22", + } + for _, op := range []string{ + "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB", + "VPSUBSW", "VPSUBUSB", "VPSUBUSW", "VPSUBW", + } { + for _, form := range commonForms { + fmt.Fprintf(&src, "\t%s %s\n", op, form) + } + for _, form := range maskedForms { + fmt.Fprintf(&src, "\t%s %s\n", op, form) + fmt.Fprintf(&src, "\t%s.Z %s\n", op, form) + } + if op == "VPSUBD" || op == "VPSUBQ" { + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&src, "\t%s.BCST (AX), %s21, %s22\n", op, width, width) + fmt.Fprintf(&src, "\t%s.BCST (AX), %s21, K1, %s22\n", op, width, width) + fmt.Fprintf(&src, "\t%s.BCST.Z (AX), %s21, K1, %s22\n", op, width, width) + } + } + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "packedintegersubtractforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-integer-subtract-forms.ll", "packed-integer-subtract-forms.o", ll) +} + +func TestTranslate386PackedIntegerSubtractCompleteGoAssemblerForms(t *testing.T) { + // In 386 mode the legacy encoder limits X registers to X0-X7. VEX and + // unmasked EVEX X/Y rows remain available (including X/Y16-X/Y31), while + // the assembler frontend rejects Z width and the four-operand mask rows. + var src strings.Builder + src.WriteString("TEXT packedintegersubtractforms386(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PSUBB", "PSUBL", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW"} { + fmt.Fprintf(&src, "\t%s X1, X7\n", op) + fmt.Fprintf(&src, "\t%s (AX), X7\n", op) + } + for _, op := range []string{ + "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB", + "VPSUBSW", "VPSUBUSB", "VPSUBUSW", "VPSUBW", + } { + for _, form := range []string{ + "X1, X2, X3", "(AX), X2, X3", "X20, X21, X22", + "Y1, Y2, Y3", "(AX), Y2, Y3", "Y20, Y21, Y22", + } { + fmt.Fprintf(&src, "\t%s %s\n", op, form) + } + if op == "VPSUBD" || op == "VPSUBQ" { + fmt.Fprintf(&src, "\t%s.BCST (AX), X21, X22\n", op) + fmt.Fprintf(&src, "\t%s.BCST (AX), Y21, Y22\n", op) + } + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "packedintegersubtractforms386": {Name: "packedintegersubtractforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "packed-integer-subtract-386-forms.ll", "packed-integer-subtract-386-forms.o", ll) +} + +func TestTranslateAMD64PackedIntegerSubtractRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "PSUBB M1, M2", + "PSUBQ Y1, Y2", + "VPSUBB X1, Y2, Y3", + "VPSUBW X1, X2, K0, X3", + "VPSUBD.Z X1, X2, X3", + "VPSUBQ.BCST X1, X2, X3", + "VPSUBSB.BCST (AX), X2, X3", + "VPSUBSW.SAE X1, X2, K1, X3", + "VPSUBUSB X1, X2, K1, X3, X4", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedintegersubtract(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedintegersubtract": {Name: "invalidpackedintegersubtract", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's packed-subtract tables", instruction) + } + }) + } +} + +func TestTranslate386PackedIntegerSubtractRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "PSUBB X1, X8", + "VPSUBQ Z1, Z2, Z3", + "VPSUBD X1, X2, K1, X3", + "VPSUBQ.Z X1, X2, K1, X3", + "VPSUBD.BCST.Z (AX), X2, K1, X3", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedintegersubtract386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidpackedintegersubtract386": {Name: "invalidpackedintegersubtract386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedSumAbsoluteDifferencesCompleteGoAssemblerForms(t *testing.T) { + src := ` +TEXT packedsadforms(SB),NOSPLIT,$0-0 + PSADBW X1, X2 + PSADBW (AX), X2 + VPSADBW X1, X2, X3 + VPSADBW (AX), X2, X3 + VPSADBW Y1, Y2, Y3 + VPSADBW (AX), Y2, Y3 + VPSADBW Z1, Z2, Z3 + VPSADBW (AX), Z2, Z3 + RET +` + ll := translateAMD64EcosystemCase(t, src, "packedsadforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-sad-forms.ll", "packed-sad-forms.o", ll) +} + +func TestTranslateAMD64PackedSumAbsoluteDifferencesRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "PSADBW Y1, Y2", + "VPSADBW X1, Y2, Y3", + "VPSADBW X1, X2, K1, X3", + "VPSADBW.Z X1, X2, X3", + "VPSADBW.BCST (AX), X2, X3", + "VPSADBW $1, X2, X3", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedsad(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedsad": {Name: "invalidpackedsad", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's PSADBW/VPSADBW tables", instruction) + } + }) + } +} + +func TestTranslateAMD64VectorLaneExtractCompleteGoAssemblerForms(t *testing.T) { + // VEXTRACTF128/I128 share Go 1.27's _yvextractf128 table. + var src strings.Builder + src.WriteString("TEXT vectorlaneextractforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VEXTRACTF128", "VEXTRACTI128"} { + fmt.Fprintf(&src, "\t%s $1, Y1, X2\n", op) + fmt.Fprintf(&src, "\t%s $-1, Y1, (AX)\n", op) + } + // These four produce 128 bits from either Y or Z and share + // _yvextractf32x4, including masked register/memory destinations. + for _, op := range []string{"VEXTRACTF32X4", "VEXTRACTF64X2", "VEXTRACTI32X4", "VEXTRACTI64X2"} { + for _, form := range []string{ + "$1, Y1, X2", "$1, Y1, (AX)", + "$1, Y1, K1, X2", "$1, Y1, K1, (AX)", + "$3, Z1, X2", "$3, Z1, (AX)", + "$3, Z1, K1, X2", "$3, Z1, K1, (AX)", + } { + fmt.Fprintf(&src, "\t%s %s\n", op, form) + } + fmt.Fprintf(&src, "\t%s.Z $1, Y1, K1, X2\n", op) + fmt.Fprintf(&src, "\t%s.Z $3, Z1, K1, X2\n", op) + } + // These four produce 256 bits from Z and share _yvextractf32x8. + for _, op := range []string{"VEXTRACTF32X8", "VEXTRACTF64X4", "VEXTRACTI32X8", "VEXTRACTI64X4"} { + for _, form := range []string{ + "$1, Z1, Y2", "$1, Z1, (AX)", + "$1, Z1, K1, Y2", "$1, Z1, K1, (AX)", + } { + fmt.Fprintf(&src, "\t%s %s\n", op, form) + } + fmt.Fprintf(&src, "\t%s.Z $1, Z1, K1, Y2\n", op) + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "vectorlaneextractforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "vector-lane-extract-forms.ll", "vector-lane-extract-forms.o", ll) +} + +func TestTranslateAMD64VectorLaneExtractRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VEXTRACTI128 $1, Z1, X2", + "VEXTRACTF128 $1, Y1, K1, X2", + "VEXTRACTI32X4 $1, X1, X2", + "VEXTRACTF64X2 $1, Y1, Y2", + "VEXTRACTI32X8 $1, Y1, Y2", + "VEXTRACTF64X4 $1, Z1, K0, Y2", + "VEXTRACTF32X4.Z $1, Y1, X2", + "VEXTRACTI64X2.Z $1, Z1, K1, (AX)", + "VEXTRACTI64X4.SAE $1, Z1, Y2", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidvectorlaneextract(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidvectorlaneextract": {Name: "invalidvectorlaneextract", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's vector-lane extract tables", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedScalarExtractCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's legacy yextr/yextrw tables accept an unsigned imm8, an + // X0-X15 source, and a GP-or-memory destination. The yextr table used by + // B/D/Q also (unusually) classifies M0-M7 as destinations; those names + // encode the correspondingly numbered GP registers. + var src strings.Builder + src.WriteString("TEXT packedscalarextractforms(SB),NOSPLIT,$0-0\n") + for _, spec := range []struct { + op string + maxIndex int + mmxDst bool + }{ + {op: "PEXTRB", maxIndex: 15, mmxDst: true}, + {op: "PEXTRW", maxIndex: 7}, + {op: "PEXTRD", maxIndex: 3, mmxDst: true}, + {op: "PEXTRQ", maxIndex: 1, mmxDst: true}, + } { + fmt.Fprintf(&src, "\t%s $%d, X15, AX\n", spec.op, spec.maxIndex) + fmt.Fprintf(&src, "\t%s $255, X15, (AX)\n", spec.op) + if spec.mmxDst { + fmt.Fprintf(&src, "\t%s $%d, X15, M2\n", spec.op, spec.maxIndex) + } + } + + // Go 1.27's _yvextractps/_yvpextrw tables add signed-imm8 VEX forms + // for X0-X15 and unsigned-imm8 EVEX forms for X16-X31. They do not add + // mask or instruction-suffix forms. + for _, spec := range []struct { + op string + maxIndex int + }{ + {op: "VPEXTRB", maxIndex: 15}, + {op: "VPEXTRW", maxIndex: 7}, + {op: "VPEXTRD", maxIndex: 3}, + {op: "VPEXTRQ", maxIndex: 1}, + } { + fmt.Fprintf(&src, "\t%s $%d, X1, R8\n", spec.op, spec.maxIndex) + fmt.Fprintf(&src, "\t%s $255, X1, (AX)\n", spec.op) + fmt.Fprintf(&src, "\t%s $-128, X1, R8\n", spec.op) + fmt.Fprintf(&src, "\t%s $%d, X31, R15\n", spec.op, spec.maxIndex) + fmt.Fprintf(&src, "\t%s $255, X31, (AX)\n", spec.op) + } + src.WriteString("\tRET\n") + + ll := translateAMD64EcosystemCase(t, src.String(), "packedscalarextractforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-scalar-extract-forms.ll", "packed-scalar-extract-forms.o", ll) +} + +func TestTranslateAMD64PackedScalarExtractRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "PEXTRB $-1, X1, AX", + "PEXTRD $256, X1, AX", + "PEXTRW $1, X1, M2", + "PEXTRQ $1, X16, AX", + "PEXTRB $1, Y1, AX", + "VPEXTRB $-129, X1, AX", + "VPEXTRW $256, X1, AX", + "VPEXTRD $-1, X20, AX", + "VPEXTRQ $1, X1, M2", + "VPEXTRB $1, X1, K1, AX", + "VPEXTRW.Z $1, X1, AX", + "VPEXTRD.BCST $1, X1, (AX)", + "VPEXTRQ.SAE $1, X1, AX", + "VPEXTRB $1, X1, X2", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedscalarextract(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedscalarextract": {Name: "invalidpackedscalarextract", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's PEXTR/VPEXTR tables", instruction) + } + }) + } +} + +func TestTranslateAMD64MoveHighLowPackedSingleCompleteGoAssemblerForms(t *testing.T) { + // MOVHLPS/MOVLHPS use Go 1.27's yxr table (X0-X15, two operands). + // VMOVHLPS/VMOVLHPS share _yvmovhlps: three X operands, with both the + // X0-X15 VEX entry and the X0-X31 EVEX entry. + src := ` +TEXT movehighlowpackedsingleforms(SB),NOSPLIT,$0-0 + MOVHLPS X1, X2 + MOVLHPS X15, X0 + VMOVHLPS X1, X2, X3 + VMOVLHPS X15, X14, X13 + VMOVHLPS X20, X2, X3 + VMOVHLPS X1, X20, X3 + VMOVLHPS X1, X2, X31 + RET +` + ll := translateAMD64EcosystemCase(t, src, "movehighlowpackedsingleforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "move-high-low-packed-single-forms.ll", "move-high-low-packed-single-forms.o", ll) +} + +func TestTranslateAMD64MoveHighLowPackedSingleRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "MOVHLPS X16, X1", + "MOVLHPS X1, X16", + "MOVHLPS (AX), X1", + "MOVLHPS X1, X2, X3", + "VMOVHLPS X1, X2", + "VMOVLHPS (AX), X2, X3", + "VMOVHLPS Y1, Y2, Y3", + "VMOVLHPS X1, X2, K1, X3", + "VMOVHLPS.Z X1, X2, X3", + "VMOVLHPS.BCST X1, X2, X3", + "VMOVHLPS.SAE X1, X2, X3", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidmovehighlowpackedsingle(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidmovehighlowpackedsingle": {Name: "invalidmovehighlowpackedsingle", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's MOVHLPS/MOVLHPS tables", instruction) + } + }) + } +} + +func TestTranslateAMD64PopulationCountCompleteGoAssemblerForms(t *testing.T) { + // POPCNTW/L/Q all use Go 1.27's yml_rl table: a Yml GP-or-memory + // source followed by a Yrl GP destination. + src := ` +TEXT populationcountforms(SB),NOSPLIT,$0-0 + POPCNTW AX, BX + POPCNTW (AX), R8 + POPCNTW R15, R14 + POPCNTL AX, BX + POPCNTL (AX), R8 + POPCNTL R15, R14 + POPCNTQ AX, BX + POPCNTQ (AX), R8 + POPCNTQ R15, R14 + RET +` + ll := translateAMD64EcosystemCase(t, src, "populationcountforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "population-count-forms.ll", "population-count-forms.o", ll) +} + +func TestTranslate386PopulationCountCompleteGoAssemblerForms(t *testing.T) { + src := ` +TEXT populationcount386forms(SB),NOSPLIT,$0-0 + POPCNTW AX, BX + POPCNTW (AX), CX + POPCNTL AX, BX + POPCNTL (AX), CX + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "populationcount386forms": {Name: "populationcount386forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "population-count-386-forms.ll", "population-count-386-forms.o", ll) + + invalid, err := Parse(ArchAMD64, "TEXT invalidpopulationcount386(SB),NOSPLIT,$0-0\n\tPOPCNTQ AX, BX\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(invalid, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidpopulationcount386": {Name: "invalidpopulationcount386", Ret: Void}, + }, + }); err == nil { + t.Fatal("Translate accepted POPCNTQ for GOARCH=386") + } +} + +func TestTranslateAMD64PopulationCountRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "POPCNTW AL, BX", + "POPCNTL AX, AH", + "POPCNTQ M1, AX", + "POPCNTW X1, AX", + "POPCNTL AX, (BX)", + "POPCNTQ $1, AX", + "POPCNTW.Z AX, BX", + "POPCNTL AX, BX, CX", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpopulationcount(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpopulationcount": {Name: "invalidpopulationcount", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's POPCNT tables", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedMoveMaskCompleteGoAssemblerForms(t *testing.T) { + // PMOVMSKB's ymskb table has X and M source rows. VPMOVMSKB's + // _yvmovmskpd table has X and Y source rows. Every row writes Yrl and + // every vector register is limited to 0-15; neither table has EVEX rows. + src := ` +TEXT packedmovemaskforms(SB),NOSPLIT,$0-0 + PMOVMSKB X0, AX + PMOVMSKB X15, R8 + PMOVMSKB M0, BX + PMOVMSKB M7, R15 + VPMOVMSKB X0, AX + VPMOVMSKB X15, R8 + VPMOVMSKB Y0, BX + VPMOVMSKB Y15, R15 + RET +` + ll := translateAMD64EcosystemCase(t, src, "packedmovemaskforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-move-mask-forms.ll", "packed-move-mask-forms.o", ll) +} + +func TestTranslateAMD64PackedMoveMaskRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "PMOVMSKB Y1, AX", + "PMOVMSKB X16, AX", + "PMOVMSKB (AX), BX", + "PMOVMSKB X1, M2", + "VPMOVMSKB M1, AX", + "VPMOVMSKB X16, AX", + "VPMOVMSKB Y16, AX", + "VPMOVMSKB X1, AL", + "VPMOVMSKB X1, X2", + "VPMOVMSKB X1, K1, AX", + "PMOVMSKB.Z X1, AX", + "VPMOVMSKB.BCST Y1, AX", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedmovemask(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedmovemask": {Name: "invalidpackedmovemask", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's PMOVMSKB/VPMOVMSKB tables", instruction) + } + }) + } +} + +func TestTranslateAMD64BitwiseNotCompleteGoAssemblerForms(t *testing.T) { + // NOTB/W/L/Q all use Go 1.27's yscond table, whose sole row is Ymb. + // Besides memory and full GP spellings, Ymb admits low/high byte register + // spellings; for wider operations Go encodes those spellings by ModRM + // number (for example, NOTW AH encodes NOTW SP). + var src strings.Builder + src.WriteString("TEXT bitwisenotforms(SB),NOSPLIT,$0-0\n") + operands := []string{ + "AX", "BX", "CX", "DX", "SP", "BP", "SI", "DI", + "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", + "AL", "AH", "BL", "BH", "CL", "CH", "DL", "DH", + "BPB", "SIB", "DIB", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B", + "(BX)", + } + for _, op := range []string{"NOTB", "NOTW", "NOTL", "NOTQ"} { + for _, operand := range operands { + fmt.Fprintf(&src, "\t%s %s\n", op, operand) + } + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "bitwisenotforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "bitwise-not-forms.ll", "bitwise-not-forms.o", ll) +} + +func TestTranslate386BitwiseNotCompleteGoAssemblerForms(t *testing.T) { + // In 386 mode Go classifies SP as Yrl32, which does not cover Ymb, but + // accepts BP/SI/DI by synthesizing an equivalent instruction sequence. + // Exercise every accepted GP spelling, both byte aliases, and memory. + var src strings.Builder + src.WriteString("TEXT bitwisenot386forms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"NOTB", "NOTW", "NOTL"} { + for _, operand := range []string{ + "AX", "BX", "CX", "DX", "BP", "SI", "DI", + "AL", "AH", "BL", "BH", "CL", "CH", "DL", "DH", + "(BX)", + } { + fmt.Fprintf(&src, "\t%s %s\n", op, operand) + } + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "bitwisenot386forms": {Name: "bitwisenot386forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "bitwise-not-386-forms.ll", "bitwise-not-386-forms.o", ll) + + for _, instruction := range []string{"NOTB SP", "NOTW SP", "NOTL SP", "NOTQ AX", "NOTB R8"} { + t.Run("reject_"+strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + invalid, err := Parse(ArchAMD64, "TEXT invalidbitwisenot386(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(invalid, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidbitwisenot386": {Name: "invalidbitwisenot386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for GOARCH=386", instruction) + } + }) + } +} + +func TestTranslateAMD64BitwiseNotRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "NOTB M1", + "NOTW X1", + "NOTL K1", + "NOTQ $1", + "NOTB AX, BX", + "NOTW.Z AX", + "NOTL.BCST (AX)", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidbitwisenot(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidbitwisenot": {Name: "invalidbitwisenot", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's NOT tables", instruction) + } + }) + } +} + +func TestTranslateAMD64ParallelBitDepositExtractCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 uses one _yandnl row for the whole family: + // Yml source/mask, Yrl source value, and Yrl destination. This gives each + // L/Q instruction both register and memory first-operand forms. + var src strings.Builder + src.WriteString("TEXT parallelbitforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PDEPL", "PDEPQ", "PEXTL", "PEXTQ"} { + fmt.Fprintf(&src, "\t%s AX, BX, CX\n", op) + fmt.Fprintf(&src, "\t%s (SI), R8, R15\n", op) + fmt.Fprintf(&src, "\t%s parallelBitMask(SB), R9, R10\n", op) + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "parallelbitforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "parallel-bit-forms.ll", "parallel-bit-forms.o", ll) +} + +func TestTranslate386ParallelBitDepositExtractCompleteGoAssemblerForms(t *testing.T) { + // The Go 1.27 assembler accepts the same four instruction names in 386 + // mode. Yml/Yrl admit all eight 386 GP registers, including SP in any + // register position; only the first operand can instead be memory. + var src strings.Builder + src.WriteString("TEXT parallelbitforms386(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PDEPL", "PDEPQ", "PEXTL", "PEXTQ"} { + fmt.Fprintf(&src, "\t%s AX, BX, CX\n", op) + fmt.Fprintf(&src, "\t%s (SI), BP, DI\n", op) + fmt.Fprintf(&src, "\t%s SP, AX, BX\n", op) + fmt.Fprintf(&src, "\t%s AX, SP, BX\n", op) + fmt.Fprintf(&src, "\t%s AX, BX, SP\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "parallelbitforms386": {Name: "parallelbitforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "parallel-bit-386-forms.ll", "parallel-bit-386-forms.o", ll) +} + +func TestTranslateAMD64ParallelBitDepositExtractRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "PDEPL AX, BX", + "PDEPQ AX, (BX), CX", + "PEXTL AX, BX, (CX)", + "PEXTQ $1, AX, BX", + "PDEPL AL, BX, CX", + "PDEPQ AX, X0, BX", + "PEXTL AX, BX, X0", + "PEXTQ.Z AX, BX, CX", + "PDEPL.BCST (AX), BX, CX", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidparallelbit(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidparallelbit": {Name: "invalidparallelbit", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's PDEP/PEXT table", instruction) + } + }) + } +} + +func TestTranslate386ParallelBitDepositExtractRejectsHighRegisters(t *testing.T) { + for _, instruction := range []string{ + "PDEPL R8, AX, BX", + "PDEPQ AX, R8, BX", + "PEXTL AX, BX, R8", + } { + file, err := Parse(ArchAMD64, "TEXT invalidparallelbit386(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidparallelbit386": {Name: "invalidparallelbit386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for GOARCH=386", instruction) + } + } +} + +func TestTranslateAMD64BitTestFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 gives all BT/BTC/BTR/BTS W/L/Q instructions exactly two ybtl + // rows: signed imm8 + Yml and Yrl + Yml. + var src strings.Builder + src.WriteString("TEXT bittestforms(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"BT", "BTC", "BTR", "BTS"} { + for _, width := range []string{"W", "L", "Q"} { + op := stem + width + fmt.Fprintf(&src, "\t%s $-128, AX\n", op) + fmt.Fprintf(&src, "\t%s $127, (BX)\n", op) + fmt.Fprintf(&src, "\t%s CX, R15\n", op) + fmt.Fprintf(&src, "\t%s R8, 8(SI)\n", op) + fmt.Fprintf(&src, "\t%s R9, bitTestGlobal(SB)\n", op) + } + } + src.WriteString("\tRET\n") + ll := translateAMD64EcosystemCase(t, src.String(), "bittestforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "bit-test-forms.ll", "bit-test-forms.o", ll) +} + +func TestTranslate386BitTestFamilyCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT bittestforms386(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"BT", "BTC", "BTR", "BTS"} { + for _, width := range []string{"W", "L"} { + op := stem + width + fmt.Fprintf(&src, "\t%s $-128, AX\n", op) + fmt.Fprintf(&src, "\t%s $127, (BX)\n", op) + fmt.Fprintf(&src, "\t%s CX, DI\n", op) + fmt.Fprintf(&src, "\t%s SP, BP\n", op) + fmt.Fprintf(&src, "\t%s AX, SP\n", op) + } + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "bittestforms386": {Name: "bittestforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "bit-test-386-forms.ll", "bit-test-386-forms.o", ll) +} + +func TestTranslateAMD64BitTestFamilyRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "BTB $1, AX", + "BTRL $128, AX", + "BTSQ $-129, AX", + "BTCW AX", + "BTL (AX), BX", + "BTRQ AL, AX", + "BTSW AX, $1", + "BTQ AX, X0", + "BTCL.Z AX, BX", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT invalidbittest(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidbittest": {Name: "invalidbittest", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's ybtl table", instruction) + } + }) + } +} + +func TestTranslate386BitTestFamilyRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "BTQ $1, AX", + "BTCQ AX, BX", + "BTRQ $1, (BX)", + "BTSQ AX, SP", + "BTL R8, AX", + "BTRW AX, R8", + } { + file, err := Parse(ArchAMD64, "TEXT invalidbittest386(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidbittest386": {Name: "invalidbittest386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for GOARCH=386", instruction) + } + } +} + +func TestTranslateAMD64ScalarAddSubCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT scalaraddsubforms(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"ADD", "SUB"} { + fmt.Fprintf(&src, "\t%sB $-2147483648, AL\n", stem) + fmt.Fprintf(&src, "\t%sB $4294967295, bytearg+0(FP)\n", stem) + fmt.Fprintf(&src, "\t%sB BP, (BX)\n", stem) + fmt.Fprintf(&src, "\t%sB (BX), R15\n", stem) + fmt.Fprintf(&src, "\t%sB bytearg+0(FP), R14\n", stem) + fmt.Fprintf(&src, "\t%sB CL, bytearg+0(FP)\n", stem) + for _, form := range []struct { + width string + fpName string + offset int + }{ + {width: "W", fpName: "wordarg", offset: 8}, + {width: "L", fpName: "longarg", offset: 16}, + {width: "Q", fpName: "quadarg", offset: 24}, + } { + op := stem + form.width + fmt.Fprintf(&src, "\t%s $-2147483648, AX\n", op) + fmt.Fprintf(&src, "\t%s $4294967295, %s+%d(FP)\n", op, form.fpName, form.offset) + fmt.Fprintf(&src, "\t%s R8, (BX)\n", op) + fmt.Fprintf(&src, "\t%s (BX), R15\n", op) + fmt.Fprintf(&src, "\t%s %s+%d(FP), R14\n", op, form.fpName, form.offset) + fmt.Fprintf(&src, "\t%s CX, %s+%d(FP)\n", op, form.fpName, form.offset) + } + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "scalaraddsubforms": { + Name: "scalaraddsubforms", + Args: []LLVMType{I8, I16, I32, I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I8, Index: 0, Field: -1}, + {Offset: 8, Type: I16, Index: 1, Field: -1}, + {Offset: 16, Type: I32, Index: 2, Field: -1}, + {Offset: 24, Type: I64, Index: 3, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "scalar-add-sub-forms.ll", "scalar-add-sub-forms.o", ll) +} + +func TestTranslate386ScalarAddSubCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT scalaraddsubforms386(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"ADD", "SUB"} { + fmt.Fprintf(&src, "\t%sB $4294967296, BP\n", stem) + fmt.Fprintf(&src, "\t%sB $-2147483649, bytearg+0(FP)\n", stem) + fmt.Fprintf(&src, "\t%sB SI, (BX)\n", stem) + fmt.Fprintf(&src, "\t%sB (BX), DI\n", stem) + for _, form := range []struct { + width string + fpName string + offset int + }{ + {width: "W", fpName: "wordarg", offset: 4}, + {width: "L", fpName: "longarg", offset: 8}, + } { + op := stem + form.width + fmt.Fprintf(&src, "\t%s $4294967296, AX\n", op) + fmt.Fprintf(&src, "\t%s $1, SP\n", op) + fmt.Fprintf(&src, "\t%s $-2147483649, %s+%d(FP)\n", op, form.fpName, form.offset) + fmt.Fprintf(&src, "\t%s SI, (BX)\n", op) + fmt.Fprintf(&src, "\t%s (BX), DI\n", op) + } + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "scalaraddsubforms386": { + Name: "scalaraddsubforms386", + Args: []LLVMType{I8, I16, I32}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I8, Index: 0, Field: -1}, + {Offset: 4, Type: I16, Index: 1, Field: -1}, + {Offset: 8, Type: I32, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "scalar-add-sub-386-forms.ll", "scalar-add-sub-386-forms.o", ll) +} + +func TestTranslateAMD64ScalarAddSubRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "ADDB (AX), (BX)", + "SUBW (AX), (BX)", + "ADDL $-2147483649, AX", + "SUBQ $4294967296, AX", + "ADDQ.Z AX, BX", + "SUBQ X0, AX", + "ADDQ AX, X0", + "SUBQ AX, $1", + "ADDB SP, (AX)", + "SUBB (AX), SP", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT invalidscalaraddsub(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidscalaraddsub": {Name: "invalidscalaraddsub", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's ADD/SUB tables", instruction) + } + }) + } +} + +func TestTranslate386ScalarAddSubRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "ADDQ AX, BX", + "SUBQ $1, (BX)", + "ADDL R8, AX", + "SUBW AX, R8", + "ADDB R8, (AX)", + "SUBB (AX), R8", + "ADDB SP, (AX)", + } { + file, err := Parse(ArchAMD64, "TEXT invalidscalaraddsub386(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidscalaraddsub386": {Name: "invalidscalaraddsub386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + } +} + +func TestTranslateAMD64CompareExchangeCompleteGoAssemblerForms(t *testing.T) { + src := ` +DATA cmpxchgdata+0(SB)/8, $0 +DATA cmpxchgdata+8(SB)/8, $0 +GLOBL cmpxchgdata(SB), NOPTR, $16 +TEXT cmpxchgforms(SB),NOSPLIT,$0-16 + CMPXCHGB AH, R11 + CMPXCHGB R11, SP + CMPXCHGB DL, (R12) + CMPXCHGB DL, 0(FS) + CMPXCHGB DL, cmpxchgdata(SB) + CMPXCHGB DL, value+0(FP) + CMPXCHGW DX, R11 + CMPXCHGW R11, (R12) + CMPXCHGW DX, 0(GS) + CMPXCHGW DX, cmpxchgdata(SB) + CMPXCHGW DX, value+0(FP) + CMPXCHGL DX, R11 + CMPXCHGL R11, (R12) + CMPXCHGL DX, 0(FS) + CMPXCHGL DX, cmpxchgdata(SB) + CMPXCHGL DX, value+0(FP) + CMPXCHGQ DX, R11 + CMPXCHGQ R11, (R12) + CMPXCHGQ DX, 0(GS) + CMPXCHGQ DX, cmpxchgdata(SB) + CMPXCHGQ DX, value+0(FP) + CMPXCHG8B R11 + CMPXCHG8B SP + CMPXCHG8B (R12) + CMPXCHG8B 0(FS) + CMPXCHG8B cmpxchgdata(SB) + CMPXCHG8B value+0(FP) + CMPXCHG16B R11 + CMPXCHG16B SP + CMPXCHG16B (R12) + CMPXCHG16B 0(GS) + CMPXCHG16B cmpxchgdata(SB) + CMPXCHG16B value+0(FP) + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "cmpxchgforms": { + Name: "cmpxchgforms", + Args: []LLVMType{LLVMType("i128")}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: LLVMType("i128"), Index: 0, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "cmpxchg-forms.ll", "cmpxchg-forms.o", ll) +} + +func TestTranslate386CompareExchangeCompleteGoAssemblerForms(t *testing.T) { + src := ` +DATA cmpxchgdata386+0(SB)/8, $0 +GLOBL cmpxchgdata386(SB), NOPTR, $8 +TEXT cmpxchgforms386(SB),NOSPLIT,$0-8 + CMPXCHGB BP, (BX) + CMPXCHGB SI, DI + CMPXCHGB DL, 0(FS) + CMPXCHGB DL, cmpxchgdata386(SB) + CMPXCHGB DL, value+0(FP) + CMPXCHGW SI, DI + CMPXCHGW DX, SP + CMPXCHGW DX, (BX) + CMPXCHGW DX, 0(FS) + CMPXCHGW DX, cmpxchgdata386(SB) + CMPXCHGW DX, value+0(FP) + CMPXCHGL SI, DI + CMPXCHGL DX, SP + CMPXCHGL DX, (BX) + CMPXCHGL DX, 0(FS) + CMPXCHGL DX, cmpxchgdata386(SB) + CMPXCHGL DX, value+0(FP) + CMPXCHG8B AX + CMPXCHG8B BP + CMPXCHG8B SI + CMPXCHG8B (BX) + CMPXCHG8B 0(FS) + CMPXCHG8B cmpxchgdata386(SB) + CMPXCHG8B value+0(FP) + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "cmpxchgforms386": { + Name: "cmpxchgforms386", + Args: []LLVMType{I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "cmpxchg-386-forms.ll", "cmpxchg-386-forms.o", ll) +} + +func TestTranslateAMD64CompareExchangeRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "CMPXCHGB (BX), DL", + "CMPXCHGW (BX), DX", + "CMPXCHGL $1, DX", + "CMPXCHGQ DX, $1", + "CMPXCHGB X0, DL", + "CMPXCHGL DX, X0", + "CMPXCHG8B", + "CMPXCHG8B (BX), AX", + "CMPXCHG8B $1", + "CMPXCHG16B", + "CMPXCHG16B (BX), AX", + "CMPXCHG16B.Z (BX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT invalidcmpxchg(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidcmpxchg": {Name: "invalidcmpxchg", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's CMPXCHG tables", instruction) + } + }) + } +} + +func TestTranslate386CompareExchangeRejectsArchitectureRestrictedForms(t *testing.T) { + for _, instruction := range []string{ + "CMPXCHGQ DX, (BX)", + "CMPXCHG16B (BX)", + "CMPXCHGB R8, (BX)", + "CMPXCHGW R8, (BX)", + "CMPXCHGL R8, (BX)", + "CMPXCHGB SP, (BX)", + "CMPXCHGB DL, SP", + "CMPXCHG8B SP", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT invalidcmpxchg386(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidcmpxchg386": {Name: "invalidcmpxchg386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which Go 1.27 rejects for 386", instruction) + } + }) + } +} + +func TestTranslateAMD64TrailingZeroCountCompleteGoAssemblerForms(t *testing.T) { + // TZCNTW/L/Q all use Go 1.27's ycrc32l table: Yml source, Yrl + // destination. The width is selected only by the opcode prefix. + src := ` +TEXT trailingzerocountforms(SB),NOSPLIT,$0-0 + TZCNTW AX, BX + TZCNTW (AX), R8 + TZCNTW R15, R14 + TZCNTL AX, BX + TZCNTL (AX), R8 + TZCNTL R15, R14 + TZCNTQ AX, BX + TZCNTQ (AX), R8 + TZCNTQ R15, R14 + RET +` + ll := translateAMD64EcosystemCase(t, src, "trailingzerocountforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "trailing-zero-count-forms.ll", "trailing-zero-count-forms.o", ll) +} + +func TestTranslate386TrailingZeroCountCompleteGoAssemblerForms(t *testing.T) { + src := ` +TEXT trailingzerocount386forms(SB),NOSPLIT,$0-0 + TZCNTW AX, BX + TZCNTW (AX), CX + TZCNTL AX, BX + TZCNTL (AX), CX + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "trailingzerocount386forms": {Name: "trailingzerocount386forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "trailing-zero-count-386-forms.ll", "trailing-zero-count-386-forms.o", ll) + + invalid, err := Parse(ArchAMD64, "TEXT invalidtrailingzerocount386(SB),NOSPLIT,$0-0\n\tTZCNTQ AX, BX\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(invalid, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidtrailingzerocount386": {Name: "invalidtrailingzerocount386", Ret: Void}, + }, + }); err == nil { + t.Fatal("Translate accepted TZCNTQ for GOARCH=386") + } +} + +func TestTranslateAMD64TrailingZeroCountRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "TZCNTW AL, BX", + "TZCNTL AX, AH", + "TZCNTQ M1, AX", + "TZCNTW X1, AX", + "TZCNTL AX, (BX)", + "TZCNTQ $1, AX", + "TZCNTW.Z AX, BX", + "TZCNTL AX, BX, CX", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidtrailingzerocount(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidtrailingzerocount": {Name: "invalidtrailingzerocount", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's TZCNT tables", instruction) + } + }) + } +} + +func TestTranslateAMD64FloatingCompareCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's legacy yxcmpi table accepts X/m, X0-X15, signed imm8. + // The packed AVX _yvcmppd table adds X/Y vector-result VEX forms and + // X/Y/Z K-result EVEX forms. EVEX memory sources may use .BCST; only + // the Z-register source form may use .SAE. The scalar _yvcmpsd table + // has X vector-result VEX forms and X K-result EVEX forms; only the + // EVEX register-source form may use .SAE. + var src strings.Builder + src.WriteString("TEXT floatingcompareforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"CMPPD", "CMPPS", "CMPSD", "CMPSS"} { + fmt.Fprintf(&src, "\t%s X1, X15, $-128\n", op) + fmt.Fprintf(&src, "\t%s (AX), X15, $127\n", op) + } + for _, op := range []string{"VCMPPD", "VCMPPS"} { + fmt.Fprintf(&src, "\t%s $255, X1, X2, X3\n", op) + fmt.Fprintf(&src, "\t%s $0, (AX), X2, X3\n", op) + fmt.Fprintf(&src, "\t%s $255, Y1, Y2, Y3\n", op) + fmt.Fprintf(&src, "\t%s $0, (AX), Y2, Y3\n", op) + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&src, "\t%s $255, %s20, %s21, K0\n", op, width, width) + fmt.Fprintf(&src, "\t%s $0, (AX), %s21, K1, K7\n", op, width) + fmt.Fprintf(&src, "\t%s.BCST $255, (AX), %s21, K7\n", op, width) + } + fmt.Fprintf(&src, "\t%s.SAE $255, Z20, Z21, K1, K7\n", op) + } + for _, op := range []string{"VCMPSD", "VCMPSS"} { + fmt.Fprintf(&src, "\t%s $255, X1, X2, X3\n", op) + fmt.Fprintf(&src, "\t%s $0, (AX), X2, X3\n", op) + fmt.Fprintf(&src, "\t%s $255, X20, X21, K0\n", op) + fmt.Fprintf(&src, "\t%s $0, (AX), X21, K1, K7\n", op) + fmt.Fprintf(&src, "\t%s.SAE $255, X20, X21, K1, K7\n", op) + } + src.WriteString("\tRET\n") + + ll := translateAMD64EcosystemCase(t, src.String(), "floatingcompareforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "floating-compare-forms.ll", "floating-compare-forms.o", ll) +} + +func TestTranslate386FloatingCompareCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT floatingcompareforms386(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"CMPPD", "CMPPS", "CMPSD", "CMPSS"} { + fmt.Fprintf(&src, "\t%s X1, X7, $-128\n", op) + fmt.Fprintf(&src, "\t%s (AX), X7, $127\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "floatingcompareforms386": {Name: "floatingcompareforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "floating-compare-forms-386.ll", "floating-compare-forms-386.o", ll) +} + +func TestTranslateAMD64FloatingCompareRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "CMPPD X1, X2, $-129", + "CMPPS X1, X2, $128", + "CMPSD X16, X2, $0", + "CMPSS X1, X16, $0", + "CMPPD Y1, X2, $0", + "CMPPS.BCST (AX), X2, $0", + "VCMPPD $-1, X1, X2, X3", + "VCMPPS $256, X1, X2, X3", + "VCMPSD $0, Y1, X2, X3", + "VCMPSS $0, X1, Y2, X3", + "VCMPPD $0, X1, X2, Y3", + "VCMPPS $0, Y1, Y2, X3", + "VCMPPD $0, X20, X21, X22", + "VCMPSD $0, X20, X21, X22", + "VCMPSS $0, X1, X2, K0, K1", + "VCMPPD $0, X1, X2, K0, K1", + "VCMPPS.Z $0, Z1, Z2, K1, K2", + "VCMPPD.BCST $0, Z1, Z2, K1", + "VCMPPS.BCST $0, (AX), X2, X3", + "VCMPSD.BCST $0, (AX), X2, K1", + "VCMPSS.BCST $0, (AX), X2, K1", + "VCMPPD.SAE $0, X1, X2, K1", + "VCMPPS.SAE $0, Y1, Y2, K1", + "VCMPPD.SAE $0, (AX), Z2, K1", + "VCMPSD.SAE $0, (AX), X2, K1", + "VCMPSS.SAE $0, X1, X2, X3", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidfloatingcompare(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidfloatingcompare": {Name: "invalidfloatingcompare", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's CMP/VCMP floating-point tables", instruction) + } + }) + } +} + +func TestTranslate386FloatingCompareRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "CMPPD X8, X1, $0", + "CMPSD X1, X8, $0", + "VCMPPD $0, X1, X2, X3", + "VCMPSD $0, X1, X2, X3", + } { + src := "TEXT invalidfloatingcompare386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidfloatingcompare386": {Name: "invalidfloatingcompare386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q for GOARCH=386", instruction) + } + } +} + +func TestTranslateAMD64PackedSaturatingNarrowCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 names the legacy signed dword-to-word instruction PACKSSLW. + // PACKSSLW/PACKSSWB/PACKUSWB use ymm (MMX/m64 and X/m128 forms), while + // PACKUSDW uses yxm_q4 (X/m128 only). All four V instructions share + // _yvandnpd: X/Y VEX plus X/Y/Z EVEX, optional K1-K7 and .Z. Only the + // dword-to-word forms enable EVEX 32-bit memory broadcast. + var src strings.Builder + src.WriteString("TEXT packedsaturatingnarrowforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PACKSSLW", "PACKSSWB", "PACKUSWB"} { + fmt.Fprintf(&src, "\t%s M1, M7\n", op) + fmt.Fprintf(&src, "\t%s (AX), M7\n", op) + fmt.Fprintf(&src, "\t%s X1, X15\n", op) + fmt.Fprintf(&src, "\t%s (AX), X15\n", op) + } + src.WriteString("\tPACKUSDW X1, X15\n\tPACKUSDW (AX), X15\n") + for _, op := range []string{"VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB"} { + fmt.Fprintf(&src, "\t%s X1, X2, X3\n", op) + fmt.Fprintf(&src, "\t%s (AX), X2, X3\n", op) + fmt.Fprintf(&src, "\t%s Y1, Y2, Y3\n", op) + fmt.Fprintf(&src, "\t%s (AX), Y2, Y3\n", op) + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&src, "\t%s %s20, %s21, %s22\n", op, width, width, width) + fmt.Fprintf(&src, "\t%s (AX), %s21, K1, %s22\n", op, width, width) + fmt.Fprintf(&src, "\t%s.Z %s20, %s21, K7, %s22\n", op, width, width, width) + } + } + for _, op := range []string{"VPACKSSDW", "VPACKUSDW"} { + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&src, "\t%s.BCST (AX), %s21, %s22\n", op, width, width) + fmt.Fprintf(&src, "\t%s.BCST (AX), %s21, K1, %s22\n", op, width, width) + fmt.Fprintf(&src, "\t%s.BCST.Z (AX), %s21, K7, %s22\n", op, width, width) + } + } + src.WriteString("\tRET\n") + + ll := translateAMD64EcosystemCase(t, src.String(), "packedsaturatingnarrowforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-saturating-narrow-forms.ll", "packed-saturating-narrow-forms.o", ll) +} + +func TestTranslate386PackedSaturatingNarrowCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT packedsaturatingnarrowforms386(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PACKSSLW", "PACKSSWB", "PACKUSWB"} { + fmt.Fprintf(&src, "\t%s M1, M7\n", op) + fmt.Fprintf(&src, "\t%s (AX), M7\n", op) + fmt.Fprintf(&src, "\t%s X1, X7\n", op) + fmt.Fprintf(&src, "\t%s (AX), X7\n", op) + } + src.WriteString("\tPACKUSDW X1, X7\n\tPACKUSDW (AX), X7\n\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "packedsaturatingnarrowforms386": {Name: "packedsaturatingnarrowforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "packed-saturating-narrow-forms-386.ll", "packed-saturating-narrow-forms-386.o", ll) +} + +func TestTranslateAMD64PackedSaturatingNarrowRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "PACKSSLW M1, X2", + "PACKSSWB X1, M2", + "PACKUSDW M1, M2", + "PACKUSWB X16, X1", + "PACKSSLW X1, X16", + "PACKSSWB.Z X1, X2", + "PACKUSWB X1, X2, X3", + "VPACKSSDW X1, X2", + "VPACKSSWB X1, Y2, Y3", + "VPACKUSDW Y1, Y2, X3", + "VPACKUSWB Z1, Z2, Y3", + "VPACKSSDW X1, X2, K0, X3", + "VPACKSSWB.Z X1, X2, X3", + "VPACKUSDW.BCST X1, X2, X3", + "VPACKUSWB.BCST (AX), X2, X3", + "VPACKSSWB.BCST.Z (AX), X2, K1, X3", + "VPACKSSDW.SAE X1, X2, X3", + "VPACKUSWB X1, X2, K1", + "VPACKUSDW X1, (AX), X3", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidpackedsaturatingnarrow(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedsaturatingnarrow": {Name: "invalidpackedsaturatingnarrow", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's PACK/VPACK tables", instruction) + } + }) + } +} + +func TestTranslate386PackedSaturatingNarrowRejectsVectorForms(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT invalidpackedsaturatingnarrow386(SB),NOSPLIT,$0-0\n\tVPACKSSDW X1, X2, X3\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidpackedsaturatingnarrow386": {Name: "invalidpackedsaturatingnarrow386", Ret: Void}, + }, + }); err == nil { + t.Fatal("Translate accepted VPACKSSDW for GOARCH=386") + } +} + +func TestTranslateAMD64VariableDwordPermuteCompleteGoAssemblerForms(t *testing.T) { + // VPERMD and VPERMPS share Go 1.27's _yvpermd table: Y-only VEX, + // Y/Z EVEX, optional K1-K7 and .Z, plus 32-bit memory broadcast. + var src strings.Builder + src.WriteString("TEXT variabledwordpermuteforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VPERMD", "VPERMPS"} { + fmt.Fprintf(&src, "\t%s Y1, Y2, Y3\n", op) + fmt.Fprintf(&src, "\t%s (AX), Y2, Y3\n", op) + for _, width := range []string{"Y", "Z"} { + fmt.Fprintf(&src, "\t%s %s20, %s21, %s22\n", op, width, width, width) + fmt.Fprintf(&src, "\t%s (AX), %s21, K1, %s22\n", op, width, width) + fmt.Fprintf(&src, "\t%s.Z %s20, %s21, K7, %s22\n", op, width, width, width) + fmt.Fprintf(&src, "\t%s.BCST (AX), %s21, %s22\n", op, width, width) + fmt.Fprintf(&src, "\t%s.BCST.Z (AX), %s21, K7, %s22\n", op, width, width) + } + } + src.WriteString("\tRET\n") + + ll := translateAMD64EcosystemCase(t, src.String(), "variabledwordpermuteforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "variable-dword-permute-forms.ll", "variable-dword-permute-forms.o", ll) +} + +func TestTranslateAMD64VariableDwordPermuteRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPERMD X1, X2, X3", + "VPERMPS Y1, Z2, Z3", + "VPERMD Z1, Z2, Y3", + "VPERMPS Y1, (AX), Y3", + "VPERMD Y1, Y2, K0, Y3", + "VPERMPS.Z Y1, Y2, Y3", + "VPERMD.BCST Y1, Y2, Y3", + "VPERMPS.BCST.Z (AX), Z2, Z3", + "VPERMD.SAE Y1, Y2, Y3", + "VPERMPS Y1, Y2, K1", + "VPERMD Y1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidvariabledwordpermute(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidvariabledwordpermute": {Name: "invalidvariabledwordpermute", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's VPERMD/VPERMPS table", instruction) + } + }) + } +} + +func TestTranslate386VariableDwordPermuteCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT variabledwordpermuteforms386(SB),$0-0\n") + for _, op := range []string{"VPERMD", "VPERMPS"} { + fmt.Fprintf(&source, "\t%s Y1, Y2, Y3\n", op) + fmt.Fprintf(&source, "\t%s (AX), Y2, Y3\n", op) + fmt.Fprintf(&source, "\t%s Y31, Y30, Y29\n", op) + fmt.Fprintf(&source, "\t%s Z7, Z6, Z5\n", op) + fmt.Fprintf(&source, "\t%s.BCST (AX), Y30, Y29\n", op) + fmt.Fprintf(&source, "\t%s.BCST (AX), Z6, Z5\n", op) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, "386", source.String(), true) + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + triple string + }{ + {name: "linux", triple: "i386-unknown-linux-gnu"}, + {name: "windows", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "386", + Sigs: map[string]FuncSig{ + "variabledwordpermuteforms386": {Name: "variabledwordpermuteforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "variable-dword-permute-forms-386-"+target.name+".ll", "variable-dword-permute-forms-386-"+target.name+".o", ll) + }) + } +} + +func TestTranslate386VariableDwordPermuteRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPERMD Z8, Z0, Z1", + "VPERMPS Z0, Z8, Z1", + "VPERMD Z0, Z1, Z8", + "VPERMD Y1, Y2, K1, Y3", + "VPERMPS.Z Y1, Y2, K1, Y3", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "386", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's 386 VPERMD/VPERMPS table", instruction) + } + }) + } +} + +func TestTranslateAMD64ConditionalSetCompleteGoAssemblerForms(t *testing.T) { + conditions := []string{"CC", "CS", "EQ", "GE", "GT", "HI", "LE", "LS", "LT", "MI", "NE", "OC", "OS", "PC", "PL", "PS"} + var src strings.Builder + src.WriteString("TEXT conditionalsetforms(SB),NOSPLIT,$0-1\n") + for _, condition := range conditions { + op := "SET" + condition + fmt.Fprintf(&src, "\t%s R15\n", op) + fmt.Fprintf(&src, "\t%s AH\n", op) + fmt.Fprintf(&src, "\t%s BPB\n", op) + fmt.Fprintf(&src, "\t%s R15B\n", op) + fmt.Fprintf(&src, "\t%s (AX)\n", op) + fmt.Fprintf(&src, "\t%s conditionalSetGlobal(SB)\n", op) + fmt.Fprintf(&src, "\t%s ret+0(FP)\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "conditionalsetforms": { + Name: "conditionalsetforms", + Ret: I8, + Frame: FrameLayout{Results: []FrameSlot{{ + Offset: 0, + Type: I8, + Index: 0, + Field: -1, + }}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "conditional-set-forms.ll", "conditional-set-forms.o", ll) +} + +func TestTranslate386ConditionalSetCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT conditionalsetforms386(SB),NOSPLIT,$0-1\n") + for _, condition := range []string{"CC", "CS", "EQ", "GE", "GT", "HI", "LE", "LS", "LT", "MI", "NE", "OC", "OS", "PC", "PL", "PS"} { + op := "SET" + condition + fmt.Fprintf(&src, "\t%s DX\n", op) + fmt.Fprintf(&src, "\t%s AH\n", op) + fmt.Fprintf(&src, "\t%s BP\n", op) + fmt.Fprintf(&src, "\t%s SI\n", op) + fmt.Fprintf(&src, "\t%s DI\n", op) + fmt.Fprintf(&src, "\t%s (AX)\n", op) + fmt.Fprintf(&src, "\t%s ret+0(FP)\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "conditionalsetforms386": { + Name: "conditionalsetforms386", + Ret: I8, + Frame: FrameLayout{Results: []FrameSlot{{ + Offset: 0, + Type: I8, + Index: 0, + Field: -1, + }}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "conditional-set-forms-386.ll", "conditional-set-forms-386.o", ll) +} + +func TestTranslateAMD64ConditionalSetRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "SETNE X1", + "SETLE M1", + "SETEQ K1", + "SETCC $1", + "SETGT", + "SETGE AX, BX", + "SETHI.Z AX", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidconditionalset(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidconditionalset": {Name: "invalidconditionalset", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's SETcc tables", instruction) + } + }) + } +} + +func TestTranslate386ConditionalSetRejectsArchitectureRestrictedRegisters(t *testing.T) { + for _, register := range []string{"SP", "R8"} { + file, err := Parse(ArchAMD64, "TEXT invalidconditionalset386(SB),NOSPLIT,$0-0\n\tSETNE "+register+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidconditionalset386": {Name: "invalidconditionalset386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted SETNE %s for GOARCH=386", register) + } + } +} + +func TestTranslateAMD64VectorScalarMoveCompleteGoAssemblerForms(t *testing.T) { + // VMOVSD and VMOVSS share Go 1.27's _yvmovsd table. It contains VEX + // scalar register-to-memory, memory-to-register, and three-register merge + // forms plus their EVEX high-register and optional K-mask counterparts. + // Zeroing is valid only for masked register destinations. + var src strings.Builder + src.WriteString("TEXT vectorscalarmoveforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VMOVSD", "VMOVSS"} { + fmt.Fprintf(&src, "\t%s X1, (AX)\n", op) + fmt.Fprintf(&src, "\t%s (AX), X1\n", op) + fmt.Fprintf(&src, "\t%s X1, X2, X3\n", op) + fmt.Fprintf(&src, "\t%s X20, (AX)\n", op) + fmt.Fprintf(&src, "\t%s X20, K1, (AX)\n", op) + fmt.Fprintf(&src, "\t%s (AX), X20\n", op) + fmt.Fprintf(&src, "\t%s (AX), K1, X20\n", op) + fmt.Fprintf(&src, "\t%s.Z (AX), K7, X20\n", op) + fmt.Fprintf(&src, "\t%s X20, X21, X22\n", op) + fmt.Fprintf(&src, "\t%s X20, X21, K1, X22\n", op) + fmt.Fprintf(&src, "\t%s.Z X20, X21, K7, X22\n", op) + } + src.WriteString("\tRET\n") + + ll := translateAMD64EcosystemCase(t, src.String(), "vectorscalarmoveforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "vector-scalar-move-forms.ll", "vector-scalar-move-forms.o", ll) +} + +func TestTranslateAMD64VectorScalarMoveFrameSources(t *testing.T) { + src := ` +TEXT vmovsdframe(SB),NOSPLIT,$0-8 + VMOVSD value+0(FP), X0 + RET +TEXT vmovssframe(SB),NOSPLIT,$0-4 + VMOVSS value+0(FP), X0 + RET +TEXT vmovsdframeresult(SB),NOSPLIT,$0-8 + VMOVSD X0, value+0(FP) + RET +TEXT vmovssframeresult(SB),NOSPLIT,$0-4 + VMOVSS X0, value+0(FP) + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "vmovsdframe": { + Name: "vmovsdframe", + Args: []LLVMType{LLVMType("double")}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{ + Offset: 0, + Type: LLVMType("double"), + Index: 0, + Field: -1, + }}}, + }, + "vmovssframe": { + Name: "vmovssframe", + Args: []LLVMType{LLVMType("float")}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{ + Offset: 0, + Type: LLVMType("float"), + Index: 0, + Field: -1, + }}}, + }, + "vmovsdframeresult": { + Name: "vmovsdframeresult", + Ret: LLVMType("double"), + Frame: FrameLayout{Results: []FrameSlot{{ + Offset: 0, + Type: LLVMType("double"), + Index: 0, + Field: -1, + }}}, + }, + "vmovssframeresult": { + Name: "vmovssframeresult", + Ret: LLVMType("float"), + Frame: FrameLayout{Results: []FrameSlot{{ + Offset: 0, + Type: LLVMType("float"), + Index: 0, + Field: -1, + }}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "vector-scalar-move-frame.ll", "vector-scalar-move-frame.o", ll) +} + +func TestTranslateAMD64VectorScalarMoveRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VMOVSD X1, X2", + "VMOVSS (AX), (BX)", + "VMOVSD Y1, X2, X3", + "VMOVSS X1, Y2, X3", + "VMOVSD X1, X2, Y3", + "VMOVSS X1, X2, (AX)", + "VMOVSD (AX), K0, X1", + "VMOVSS X1, K0, (AX)", + "VMOVSD X1, X2, K0, X3", + "VMOVSS.Z (AX), X1", + "VMOVSD.Z X1, K1, (AX)", + "VMOVSS.Z X1, X2, X3", + "VMOVSD.BCST (AX), X1", + "VMOVSS.SAE X1, X2, X3", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidvectorscalarmove(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidvectorscalarmove": {Name: "invalidvectorscalarmove", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's VMOVSD/VMOVSS table", instruction) + } + }) + } +} + +func TestTranslate386VectorScalarMoveRejectsForms(t *testing.T) { + for _, op := range []string{"VMOVSD", "VMOVSS"} { + file, err := Parse(ArchAMD64, "TEXT invalidvectorscalarmove386(SB),NOSPLIT,$0-0\n\t"+op+" (AX), X1\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalidvectorscalarmove386": {Name: "invalidvectorscalarmove386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %s for GOARCH=386", op) + } + } +} + +func TestTranslateX86VectorScalarFlagCompareCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 gives VCOMISD/VCOMISS/VUCOMISD/VUCOMISS the shared + // _yvcomisd table. It has exactly two rows: VEX X/m,X and EVEX X/m,X. + // EVEX permits X0-X31 and .SAE for register sources; it does not permit + // masks, zeroing, broadcast, or vector widths other than X. Go's 386 + // assembler exposes the same two rows, including the EVEX register class. + var src strings.Builder + src.WriteString("TEXT vectorscalarflagcompareforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VCOMISD", "VCOMISS", "VUCOMISD", "VUCOMISS"} { + fmt.Fprintf(&src, "\t%s X1, X2\n", op) + fmt.Fprintf(&src, "\t%s (AX), X2\n", op) + fmt.Fprintf(&src, "\t%s X20, X2\n", op) + fmt.Fprintf(&src, "\t%s X1, X21\n", op) + fmt.Fprintf(&src, "\t%s (AX), X21\n", op) + fmt.Fprintf(&src, "\t%s.SAE X1, X2\n", op) + fmt.Fprintf(&src, "\t%s.SAE X20, X21\n", op) + } + src.WriteString("\tRET\n") + + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-macosx"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "vectorscalarflagcompareforms": {Name: "vectorscalarflagcompareforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "vector-scalar-flag-compare-"+target.goarch+".ll", "vector-scalar-flag-compare-"+target.goarch+".o", ll) + }) + } +} + +func TestTranslateX86VectorScalarFlagCompareRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + } { + t.Run(target.goarch, func(t *testing.T) { + for _, instruction := range []string{ + "VCOMISD", + "VCOMISS X1", + "VUCOMISD X1, X2, X3", + "VUCOMISS Y1, X2", + "VCOMISD X1, Y2", + "VCOMISS Z1, X2", + "VUCOMISD K1, X2", + "VUCOMISS X1, (AX)", + "VCOMISD $1, X2", + "VCOMISS.SAE (AX), X2", + "VUCOMISD.BCST (AX), X2", + "VUCOMISS.Z X1, X2", + "VCOMISD X1, K1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalidvectorscalarflagcompare(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "invalidvectorscalarflagcompare": {Name: "invalidvectorscalarflagcompare", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q for %s, which is absent from Go 1.27's _yvcomisd table", instruction, target.goarch) + } + }) + } + }) + } +} + +func TestTranslateAMD64AdditionalPackedIntegerFamilies(t *testing.T) { + src := ` +TEXT packedintegerfamilies(SB),NOSPLIT,$0-0 + PADDB X0, X1 + PCMPEQW X0, X1 + PMULLW X0, X1 + PABSD X0, X1 + PSUBUSB X0, X1 + PTEST X0, X1 + RET +` + translateAMD64EcosystemCase(t, src, "packedintegerfamilies") +} + +func TestTranslateAMD64AdditionalConditionalMoveWidths(t *testing.T) { + src := ` +TEXT conditionalmoves(SB),NOSPLIT,$0-0 + CMPQ AX, BX + CMOVQLE CX, DX + CMOVLGT CX, DX + CMOVWCC CX, DX + RET +` + translateAMD64EcosystemCase(t, src, "conditionalmoves") +} + +func TestTranslateAMD64LegacyScalarAndPackedFloatingPointFamilies(t *testing.T) { + src := ` +TEXT floatfamilies(SB),NOSPLIT,$0-0 + MOVSS (AX), X0 + SQRTSS X0, X1 + ADDSS X0, X1 + SUBSS X0, X1 + MULSS X0, X1 + DIVSS X0, X1 + MINSS X0, X1 + MAXSS X0, X1 + MOVSS X1, (BX) + MOVUPD (AX), X2 + MOVAPD X2, (BX) + MOVUPD X2, 16(BX) + XORPD X2, X3 + ANDPS X2, X3 + ADDPS X2, X3 + SUBPS X2, X3 + MULPS X2, X3 + DIVPS X2, X3 + MINPS X2, X3 + MAXPS X2, X3 + SQRTPS X2, X3 + ADDPD X2, X3 + SUBPD X2, X3 + MULPD X2, X3 + DIVPD X2, X3 + MINPD X2, X3 + MAXPD X2, X3 + SQRTPD X2, X3 + MOVLHPS X2, X3 + MOVHLPS X2, X3 + MOVLPD (AX), X3 + MOVLPD X3, (BX) + MOVHPD (AX), X3 + MOVHPD X3, (BX) + SHUFPD $1, X2, X3 + UNPCKLPS X2, X3 + UNPCKHPD X2, X3 + MOVDDUP X2, X3 + HADDPD X2, X3 + HADDPD (AX), X3 + HADDPS X2, X3 + HADDPS (AX), X3 + CVTSS2SD X2, X3 + CVTSS2SD (AX), X3 + CVTSD2SS X2, X3 + CVTSD2SS (AX), X3 + UCOMISS X2, X3 + UCOMISD X2, X3 + RET +` + translateAMD64EcosystemCase(t, src, "floatfamilies") +} + +func TestTranslateAMD64DuplicateMoveFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's legacy yxm table accepts X/m -> X for MOVDDUP, + // MOVSHDUP, and MOVSLDUP. Its shared _yvmovddup table accepts + // X/m -> X, Y/m -> Y, and Z/m -> Z for all three V-prefixed forms, + // with optional K masking (and .Z zero masking) on EVEX forms. + src := ` +TEXT duplicatemoveforms(SB),NOSPLIT,$0-8 + MOVDDUP X1, X2 + MOVDDUP (AX), X2 + MOVDDUP source(SB), X2 + MOVDDUP alpha+0(FP), X2 + MOVSHDUP X1, X2 + MOVSHDUP (AX), X2 + MOVSHDUP source(SB), X2 + MOVSLDUP X1, X2 + MOVSLDUP (AX), X2 + MOVSLDUP source(SB), X2 + VMOVDDUP X1, X2 + VMOVDDUP (AX), X2 + VMOVDDUP Y1, Y2 + VMOVDDUP (AX), Y2 + VMOVDDUP X16, X17 + VMOVDDUP X16, K1, X17 + VMOVDDUP.Z (AX), K1, X17 + VMOVDDUP Y16, Y17 + VMOVDDUP Y16, K1, Y17 + VMOVDDUP.Z (AX), K1, Y17 + VMOVDDUP Z1, Z2 + VMOVDDUP Z1, K1, Z2 + VMOVDDUP.Z source(SB), K1, Z2 + VMOVSHDUP X1, X2 + VMOVSHDUP (AX), X2 + VMOVSHDUP Y1, Y2 + VMOVSHDUP (AX), Y2 + VMOVSHDUP X16, X17 + VMOVSHDUP X16, K1, X17 + VMOVSHDUP.Z (AX), K1, X17 + VMOVSHDUP Y16, Y17 + VMOVSHDUP Y16, K1, Y17 + VMOVSHDUP.Z (AX), K1, Y17 + VMOVSHDUP Z1, Z2 + VMOVSHDUP Z1, K1, Z2 + VMOVSHDUP.Z source(SB), K1, Z2 + VMOVSLDUP X1, X2 + VMOVSLDUP (AX), X2 + VMOVSLDUP Y1, Y2 + VMOVSLDUP (AX), Y2 + VMOVSLDUP X16, X17 + VMOVSLDUP X16, K1, X17 + VMOVSLDUP.Z (AX), K1, X17 + VMOVSLDUP Y16, Y17 + VMOVSLDUP Y16, K1, Y17 + VMOVSLDUP.Z (AX), K1, Y17 + VMOVSLDUP Z1, Z2 + VMOVSLDUP Z1, K1, Z2 + VMOVSLDUP.Z source(SB), K1, Z2 + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + _, err = Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"duplicatemoveforms": { + Name: "duplicatemoveforms", + Args: []LLVMType{LLVMType("double")}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{ + Offset: 0, + Type: LLVMType("double"), + Index: 0, + Field: -1, + }}}, + }}, + }) + if err != nil { + t.Fatal(err) + } +} + +func TestTranslateAMD64DuplicateMoveFamilyRejectsFormsOutsideGoOptabs(t *testing.T) { + for _, instruction := range []string{ + "MOVSHDUP Y1, Y2", + "MOVSLDUP.Z X1, X2", + "VMOVSHDUP X1, Y2", + "VMOVSLDUP.Z X1, X2", + "VMOVDDUP.Z.Z X1, K1, X2", + "VMOVDDUP X1, K0, X2", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidduplicatemove(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidduplicatemove": {Name: "invalidduplicatemove", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's yxm/_yvmovddup tables", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedDwordMultiplyFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 uses yxm_q4 for PMULLD (X/m, X) and _yvandnpd for + // VPMULLD. The latter has VEX X/Y forms plus EVEX X/Y/Z forms with + // optional K1-K7 masking, .Z zero masking, and memory-only .BCST. + src := ` +TEXT packeddwordmultiplyforms(SB),NOSPLIT,$0-0 + PMULLD X1, X2 + PMULLD (AX), X2 + PMULLD source(SB), X2 + VPMULLD X1, X2, X3 + VPMULLD (AX), X2, X3 + VPMULLD Y1, Y2, Y3 + VPMULLD (AX), Y2, Y3 + VPMULLD X16, X17, X18 + VPMULLD X16, X17, K1, X18 + VPMULLD.Z (AX), X17, K1, X18 + VPMULLD Y16, Y17, Y18 + VPMULLD Y16, Y17, K1, Y18 + VPMULLD.Z (AX), Y17, K1, Y18 + VPMULLD Z1, Z2, Z3 + VPMULLD Z1, Z2, K1, Z3 + VPMULLD.Z source(SB), Z2, K1, Z3 + VPMULLD.BCST (AX), X17, X18 + VPMULLD.BCST (AX), Y17, K1, Y18 + VPMULLD.BCST.Z source(SB), Z2, K1, Z3 + RET +` + translateAMD64EcosystemCase(t, src, "packeddwordmultiplyforms") +} + +func TestTranslateAMD64PackedDwordMultiplyFamilyRejectsFormsOutsideGoOptabs(t *testing.T) { + for _, instruction := range []string{ + "PMULLD Y1, Y2", + "VPMULLD X1, Y2, Y3", + "VPMULLD X1, X2, K0, X3", + "VPMULLD.Z X1, X2, X3", + "VPMULLD.BCST X1, X2, K1, X3", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackeddwordmultiply(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackeddwordmultiply": {Name: "invalidpackeddwordmultiply", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's PMULLD/VPMULLD tables", instruction) + } + }) + } +} + +func TestTranslateAMD64MXCSRStateFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's ysvrs_mo/ysvrs_om and _yvldmxcsr tables give all four + // instructions exactly one memory operand. Exercise general, SP, SB, and + // named FP memory; VEX changes only encoding, not the operand shape. + src := ` +TEXT mxcsrstateforms(SB),NOSPLIT,$0-8 + LDMXCSR (AX) + LDMXCSR -8(SP) + LDMXCSR control(SB) + LDMXCSR input+0(FP) + VLDMXCSR (AX) + VLDMXCSR control(SB) + STMXCSR 4(BX) + STMXCSR -8(SP) + STMXCSR control(SB) + STMXCSR output+4(FP) + VSTMXCSR (AX) + VSTMXCSR output+4(FP) + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "mxcsrstateforms": { + Name: "mxcsrstateforms", + Args: []LLVMType{I32}, + Ret: I32, + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: I32, Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 4, Type: I32, Index: 0, Field: -1}}, + }, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, "%local_stack = alloca") { + t.Fatal("amd64 SP-relative MXCSR memory did not receive byte-addressable local-stack backing") + } + for _, intrinsic := range []string{"@llvm.x86.sse.ldmxcsr", "@llvm.x86.sse.stmxcsr"} { + if !strings.Contains(ll, intrinsic) { + t.Fatalf("MXCSR lowering omitted %s", intrinsic) + } + } +} + +func TestTranslateAMD64MXCSRStateFamilyRejectsNonMemoryForms(t *testing.T) { + for _, instruction := range []string{ + "LDMXCSR AX", + "VLDMXCSR $1", + "STMXCSR X1", + "VSTMXCSR.Z (AX)", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidmxcsrstate(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidmxcsrstate": {Name: "invalidmxcsrstate", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, but Go's MXCSR tables require one memory operand", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedFloatToDwordFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's yxcvm1 table gives both instructions X/m -> X and X/m -> M. + // An X destination consumes four float32 lanes; an MMX destination consumes + // two lanes (and therefore only 64 bits for a memory source). + src := ` +TEXT packedfloattodwordforms(SB),NOSPLIT,$0-0 + CVTPS2PL X1, X2 + CVTPS2PL (AX), X2 + CVTPS2PL source(SB), X2 + CVTPS2PL X1, M2 + CVTPS2PL (AX), M2 + CVTPS2PL source(SB), M2 + CVTTPS2PL X1, X2 + CVTTPS2PL (AX), X2 + CVTTPS2PL source(SB), X2 + CVTTPS2PL X1, M2 + CVTTPS2PL (AX), M2 + CVTTPS2PL source(SB), M2 + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "packedfloattodwordforms": {Name: "packedfloattodwordforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{"@llvm.x86.sse2.cvtps2dq", "@llvm.x86.sse2.cvttps2dq"} { + if !strings.Contains(ll, intrinsic) { + t.Fatalf("packed float-to-dword lowering omitted %s", intrinsic) + } + } +} + +func TestTranslateAMD64PackedFloatToDwordFamilyRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "CVTPS2PL Y1, X2", + "CVTPS2PL X1, Y2", + "CVTPS2PL $1, X2", + "CVTTPS2PL.Z X1, X2", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedfloattodword(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedfloattodword": {Name: "invalidpackedfloattodword", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's yxcvm1 table", instruction) + } + }) + } +} + +func TestTranslateAMD64ConditionalMoveFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 has 48 entries sharing yml_rl: W/L/Q width crossed with all + // 16 x86 condition codes. Yml accepts a same-width GP register or memory; + // Yrl requires a GP register destination. Exercise both source categories + // and both ordinary and extended registers for every instruction. + conditions := []string{"CC", "CS", "EQ", "GE", "GT", "HI", "LE", "LS", "LT", "MI", "NE", "OC", "OS", "PC", "PL", "PS"} + var src strings.Builder + src.WriteString("TEXT conditionalmoveforms(SB),NOSPLIT,$0-8\n") + for _, width := range []string{"W", "L", "Q"} { + for _, condition := range conditions { + op := "CMOV" + width + condition + fmt.Fprintf(&src, "\t%s CX, DX\n", op) + fmt.Fprintf(&src, "\t%s (R10), R11\n", op) + } + } + src.WriteString("\tCMOVQPS source(SB), R10\n") + src.WriteString("\tCMOVQPS input+0(FP), R9\n") + src.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"conditionalmoveforms": { + Name: "conditionalmoveforms", + Args: []LLVMType{I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{ + Offset: 0, Type: I64, Index: 0, Field: -1, + }}}, + }}, + }); err != nil { + t.Fatal(err) + } +} + +func TestTranslateAMD64ConditionalMoveFamilyRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "CMOVQPS $1, AX", + "CMOVQPS AX, (BX)", + "CMOVQPS X1, AX", + "CMOVQPS.Z AX, BX", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidconditionalmove(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidconditionalmove": {Name: "invalidconditionalmove", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, but Go 1.27's yml_rl requires register/memory source and register destination", instruction) + } + }) + } +} + +func TestTranslateAMD64PackedSingleToDoubleFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's legacy yxm entry is X/m64 -> X. The VCVTPS2PD + // _yvcvtph2ps table adds X/m64 -> X, X/m128 -> Y, and Y/m256 -> Z, + // with EVEX masks/zeroing, memory broadcast, and SAE on the Z form. + src := ` +TEXT packedsingletodoubleforms(SB),NOSPLIT,$0-0 + CVTPS2PD X1, X2 + CVTPS2PD (AX), X2 + CVTPS2PD source(SB), X2 + VCVTPS2PD X1, X2 + VCVTPS2PD (AX), X2 + VCVTPS2PD X16, X17 + VCVTPS2PD X16, K1, X17 + VCVTPS2PD.Z (AX), K7, X17 + VCVTPS2PD.BCST (AX), X17 + VCVTPS2PD.BCST.Z source(SB), K1, X17 + VCVTPS2PD X1, Y2 + VCVTPS2PD (AX), Y2 + VCVTPS2PD X16, Y17 + VCVTPS2PD X16, K1, Y17 + VCVTPS2PD.Z (AX), K7, Y17 + VCVTPS2PD.BCST (AX), Y17 + VCVTPS2PD.BCST.Z source(SB), K1, Y17 + VCVTPS2PD Y1, Z2 + VCVTPS2PD (AX), Z2 + VCVTPS2PD Y16, Z17 + VCVTPS2PD Y16, K1, Z17 + VCVTPS2PD.Z (AX), K7, Z17 + VCVTPS2PD.BCST (AX), Z17 + VCVTPS2PD.BCST.Z source(SB), K1, Z17 + VCVTPS2PD.SAE Y16, Z17 + VCVTPS2PD.SAE.Z Y16, K1, Z17 + RET +` + ll := translateAMD64EcosystemCase(t, src, "packedsingletodoubleforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-single-to-double.ll", "packed-single-to-double.o", ll) +} + +func TestTranslateAMD64PackedSingleToDoubleFamilyRejectsFormsOutsideGoOptabs(t *testing.T) { + for _, instruction := range []string{ + "CVTPS2PD Y1, X2", + "CVTPS2PD.Z X1, X2", + "VCVTPS2PD Y1, Y2", + "VCVTPS2PD X1, Z2", + "VCVTPS2PD Z1, Z2", + "VCVTPS2PD X1, K0, X2", + "VCVTPS2PD.Z X1, X2", + "VCVTPS2PD.BCST X1, X2", + "VCVTPS2PD.SAE (AX), Z2", + "VCVTPS2PD.SAE X1, X2", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidpackedsingletodouble(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "invalidpackedsingletodouble": {Name: "invalidpackedsingletodouble", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's CVTPS2PD/VCVTPS2PD tables", instruction) + } + }) + } +} + +func TestTranslateAMD64ComplexFrameBitwiseMoveForms(t *testing.T) { + // MOVSD and MOVUPS retain their ordinary yxmov X/m<->X formats when the + // memory operand names a complex64 or complex128 value in the Go FP frame. + src := ` +TEXT complexframemoves(SB),NOSPLIT,$0-48 + MOVSD input64+0(FP), X0 + MOVSD X0, result64+24(FP) + MOVUPS input128+8(FP), X1 + MOVUPS X1, result128+32(FP) + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "complexframemoves": { + Name: "complexframemoves", + Args: []LLVMType{"{ float, float }", "{ double, double }"}, + Ret: LLVMType("{ float, float, double, double }"), + Frame: FrameLayout{ + Params: []FrameSlot{ + {Offset: 0, Type: LLVMType("float"), Index: 0, Field: 0}, + {Offset: 4, Type: LLVMType("float"), Index: 0, Field: 1}, + {Offset: 8, Type: LLVMType("double"), Index: 1, Field: 0}, + {Offset: 16, Type: LLVMType("double"), Index: 1, Field: 1}, + }, + Results: []FrameSlot{ + {Offset: 24, Type: LLVMType("float"), Index: 0, Field: -1}, + {Offset: 28, Type: LLVMType("float"), Index: 1, Field: -1}, + {Offset: 32, Type: LLVMType("double"), Index: 2, Field: -1}, + {Offset: 40, Type: LLVMType("double"), Index: 3, Field: -1}, + }, + }, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "complex-frame-moves.ll", "complex-frame-moves.o", ll) +} + +func TestTranslateAMD64WritableFPParameterSlots(t *testing.T) { + // Go's assembler gives named FP parameter slots mutable frame semantics. + // Real assembly such as Gonum's GEMV kernels advances a slice base pointer + // by writing it back to base+off(FP), then reads the updated value later. + src := ` +TEXT writablefpparam(SB),NOSPLIT,$0-16 +body: + MOVQ input+0(FP), AX + ADDQ $8, AX + MOVQ AX, input+0(FP) + MOVQ input+0(FP), BX + MOVQ BX, result+8(FP) + RET +` + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "writablefpparam": { + Name: "writablefpparam", + Args: []LLVMType{Ptr}, + Ret: Ptr, + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 8, Type: Ptr, Index: 0, Field: -1}}, + }, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, "%fp_arg_0 = alloca ptr") { + t.Fatalf("writable FP parameter did not receive mutable shadow storage:\n%s", ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "writable-fp-param.ll", "writable-fp-param.o", ll) +} + +func TestTranslateAMD64ConditionalBranchAliasFamilyCompleteGoAssemblerForms(t *testing.T) { + // Keep this list aligned with the x86 aliases installed by + // cmd/asm/internal/arch.archX86 in Go 1.27. Every conditional branch uses + // yjcond: target, $0+target, and $1+target. + aliases := []string{ + "JA", "JAE", "JB", "JBE", "JC", "JCC", "JCS", + "JE", "JEQ", "JG", "JGE", "JGT", "JHI", "JHS", + "JL", "JLE", "JLO", "JLS", "JLT", "JMI", "JNA", + "JNAE", "JNB", "JNBE", "JNC", "JNE", "JNG", "JNGE", + "JNL", "JNLE", "JNO", "JNP", "JNS", "JNZ", "JO", + "JOC", "JOS", "JP", "JPC", "JPE", "JPL", "JPO", + "JPS", "JS", "JZ", + } + var src strings.Builder + src.WriteString("TEXT conditionalbranchaliases(SB),NOSPLIT,$0-0\n") + src.WriteString("\tUCOMISD X0, X1\n") + for i, alias := range aliases { + for hint := -1; hint <= 1; hint++ { + label := fmt.Sprintf("branch_alias_%d_%d", i, hint+1) + if hint < 0 { + fmt.Fprintf(&src, "\t%s %s\n", alias, label) + } else { + fmt.Fprintf(&src, "\t%s $%d, %s\n", alias, hint, label) + } + fmt.Fprintf(&src, "%s:\n", label) + } + } + src.WriteString("\tRET\n") + translateAMD64EcosystemCase(t, src.String(), "conditionalbranchaliases") +} + +func TestTranslateX86MSRAccessFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 assigns both RDMSR and WRMSR the operand-free ynone table on + // amd64 and 386. Their inputs/outputs are the architectural CX and DX:AX + // register tuple. + src := ` +TEXT msraccessforms(SB),NOSPLIT,$0-0 + MOVL $0x10, CX + RDMSR + WRMSR + RET +` + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + } { + t.Run(target.goarch, func(t *testing.T) { + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "msraccessforms": {Name: "msraccessforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`asm sideeffect "rdmsr"`, `asm sideeffect "wrmsr"`} { + if !strings.Contains(ll, want) { + t.Fatalf("MSR access lowering omitted %q:\n%s", want, ll) + } + } + compileLLVMToObject(t, llc, target.triple, "msr-access.ll", "msr-access.o", ll) + }) + } +} + +func TestTranslateX86MSRAccessFamilyRejectsFormsOutsideGoOptab(t *testing.T) { + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + } { + for _, instruction := range []string{"RDMSR AX", "WRMSR CX", "RDMSR.P", "WRMSR.Z"} { + name := target.goarch + "_" + strings.NewReplacer(" ", "_", ".", "_").Replace(instruction) + t.Run(name, func(t *testing.T) { + src := "TEXT invalidmsraccess(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "invalidmsraccess": {Name: "invalidmsraccess", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q for %s, but Go 1.27 uses ynone", instruction, target.goarch) + } + }) + } + } +} + +func TestTranslateX86DescriptorTableFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 groups the system descriptor instructions into these complete + // operand tables: LGDT/LIDT and SGDT/SIDT take memory; LLDT/LTR/LMSW take + // GP-register or memory inputs; SLDT*/SMSW*/STR* write GP registers or + // memory. Q forms exist only on amd64. + common := ` +TEXT descriptorforms(SB),NOSPLIT,$32-0 + LGDT (BX) + LIDT 8(SP) + SGDT (CX) + SIDT 16(SP) + LLDT AX + LLDT (BX) + LTR DI + LTR 8(SP) + LMSW CX + LMSW (DX) + SLDTW AX + SLDTW (BX) + SLDTL DI + SLDTL 8(SP) + SMSWW CX + SMSWW (DX) + SMSWL BP + SMSWL 16(SP) + STRW SI + STRW (DI) + STRL BX + STRL 24(SP) + STRL SP +` + amd64Only := ` + SLDTQ R11 + SLDTQ (R12) + SMSWQ R13 + SMSWQ (R14) + STRQ R15 + STRQ (R10) +` + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-macosx"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + src := common + if target.goarch == "amd64" { + src += amd64Only + } + src += "\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "descriptorforms": {Name: "descriptorforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `asm sideeffect "lgdt`, `asm sideeffect "lidt`, + `asm sideeffect "sgdt`, `asm sideeffect "sidt`, + `asm sideeffect "lldt`, `asm sideeffect "ltr`, `asm sideeffect "lmsw`, + `asm sideeffect "sldt`, `asm sideeffect "smsw`, `asm sideeffect "str`, + } { + if !strings.Contains(ll, want) { + t.Fatalf("descriptor-table lowering omitted %q:\n%s", want, ll) + } + } + compileLLVMToObject(t, llc, target.triple, "descriptor-table.ll", "descriptor-table.o", ll) + }) + } +} + +func TestTranslateX86DescriptorTableFamilyRejectsFormsOutsideGoOptab(t *testing.T) { + tests := []struct { + name string + goarch string + triple string + instruction string + }{ + {name: "lgdt-register", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "LGDT AX"}, + {name: "sgdt-register", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "SGDT R11"}, + {name: "lidt-immediate", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "LIDT $1"}, + {name: "sidt-two-operands", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "SIDT (AX), (BX)"}, + {name: "lldt-immediate", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "LLDT $1"}, + {name: "ltr-vector", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "LTR X0"}, + {name: "lmsw-two-operands", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "LMSW AX, BX"}, + {name: "sldtw-immediate", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "SLDTW $1"}, + {name: "smswl-vector", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "SMSWL X0"}, + {name: "strq-two-operands", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "STRQ AX, BX"}, + {name: "lgdt-suffix", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "LGDT.P (AX)"}, + {name: "sldtw-suffix", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "SLDTW.Z AX"}, + {name: "386-sldtq", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "SLDTQ AX"}, + {name: "386-smswq", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "SMSWQ AX"}, + {name: "386-strq", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "STRQ AX"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + src := "TEXT invaliddescriptor(SB),NOSPLIT,$0-0\n\t" + test.instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: test.triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{ + "invaliddescriptor": {Name: "invaliddescriptor", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q for %s outside the Go 1.27 optab", test.instruction, test.goarch) + } + }) + } +} + +func TestTranslateX86MachineRegisterMoveFamilyCompleteGoAssemblerForms(t *testing.T) { + // This is the complete special-register portion of Go 1.27's ymovtab, + // excluding the independently handled segment and TLS moves. MOVQ special + // forms are accepted in 386 mode too; CR8 is the sole 64-bit-only register. + common := ` +TEXT machineregistermoves(SB),NOSPLIT,$32-0 + MOVL CR0, AX + MOVL BX, CR0 + MOVL CR2, CX + MOVL DX, CR2 + MOVL CR3, BP + MOVL SI, CR3 + MOVL CR4, DI + MOVL AX, CR4 + MOVQ CR0, BX + MOVQ CX, CR0 + MOVQ CR2, DX + MOVQ BP, CR2 + MOVQ CR3, SI + MOVQ DI, CR3 + MOVQ CR4, AX + MOVQ BX, CR4 + MOVL DR0, CX + MOVL DX, DR0 + MOVL DR6, BP + MOVL SI, DR6 + MOVL DR7, DI + MOVL AX, DR7 + MOVQ DR0, BX + MOVQ CX, DR0 + MOVQ DR2, DX + MOVQ BP, DR2 + MOVQ DR3, SI + MOVQ DI, DR3 + MOVQ DR6, AX + MOVQ BX, DR6 + MOVQ DR7, CX + MOVQ DX, DR7 + MOVL TR6, AX + MOVL TR6, 0(SP) + MOVL BX, TR6 + MOVL 4(SP), TR6 + MOVL TR7, CX + MOVL TR7, 8(SP) + MOVL DX, TR7 + MOVL 12(SP), TR7 + MOVL 0(SP), GDTR + MOVL GDTR, 16(SP) + MOVL 0(SP), IDTR + MOVL IDTR, 16(SP) + MOVQ 0(SP), GDTR + MOVQ GDTR, 16(SP) + MOVQ 0(SP), IDTR + MOVQ IDTR, 16(SP) + MOVW AX, LDTR + MOVW 0(SP), LDTR + MOVW LDTR, BX + MOVW LDTR, 0(SP) + MOVW CX, MSW + MOVW 4(SP), MSW + MOVW MSW, DX + MOVW MSW, 4(SP) + MOVW BP, TASK + MOVW 8(SP), TASK + MOVW TASK, SI + MOVW TASK, 8(SP) + MOVL CR0, SP + MOVQ CR0, SP +` + amd64Only := ` + MOVL CR8, R11 + MOVL R12, CR8 + MOVQ CR8, R13 + MOVQ R14, CR8 +` + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-macosx"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + src := common + if target.goarch == "amd64" { + src += amd64Only + } + src += "\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "machineregistermoves": {Name: "machineregistermoves", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"%cr0", "%dr0", ".byte 0x0f, 0x24", ".byte 0x0f, 0x26"} { + if !strings.Contains(ll, want) { + t.Fatalf("machine-register lowering omitted %q:\n%s", want, ll) + } + } + compileLLVMToObject(t, llc, target.triple, "machine-register.ll", "machine-register.o", ll) + }) + } +} + +func TestTranslateX86MachineRegisterMoveFamilyRejectsFormsOutsideGoMovtab(t *testing.T) { + tests := []struct { + name string + goarch string + triple string + instruction string + }{ + {name: "cr1", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVQ CR1, AX"}, + {name: "cr5", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVL AX, CR5"}, + {name: "cr-memory", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVQ CR0, (AX)"}, + {name: "386-cr8-l", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVL CR8, AX"}, + {name: "386-cr8-q", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVQ AX, CR8"}, + {name: "movl-dr2", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVL DR2, AX"}, + {name: "movq-dr1", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVQ AX, DR1"}, + {name: "dr-memory", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVQ (AX), DR0"}, + {name: "tr5", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVL TR5, AX"}, + {name: "tr-q", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVQ TR6, AX"}, + {name: "gdtr-register", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVQ AX, GDTR"}, + {name: "gdtr-width", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVW (AX), GDTR"}, + {name: "ldtr-width", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVL AX, LDTR"}, + {name: "machine-suffix", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVQ.P CR0, AX"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + src := "TEXT invalidmachineregistermove(SB),NOSPLIT,$0-0\n\t" + test.instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: test.triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{ + "invalidmachineregistermove": {Name: "invalidmachineregistermove", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q for %s outside Go 1.27's ymovtab", test.instruction, test.goarch) + } + }) + } +} + +func TestTranslateX86ScalarExtensionMoveCompleteGo127Forms(t *testing.T) { + amd64Ops := []string{ + "MOVBWSX", "MOVBWZX", "MOVBLSX", "MOVBLZX", "MOVBQSX", "MOVBQZX", + "MOVWLSX", "MOVWLZX", "MOVWQSX", "MOVWQZX", "MOVLQSX", "MOVLQZX", + "MOVSWW", "MOVZWW", + } + ops386 := []string{ + "MOVBWSX", "MOVBWZX", "MOVBLSX", "MOVBLZX", + "MOVWLSX", "MOVWLZX", "MOVLQZX", "MOVSWW", "MOVZWW", + } + for _, target := range []struct { + name string + goarch string + triple string + ops []string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin", ops: amd64Ops}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", ops: amd64Ops}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc", ops: amd64Ops}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu", ops: ops386}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc", ops: ops386}, + } { + t.Run(target.name, func(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT scalar_extension_forms(SB),NOSPLIT,$0-1\n") + for _, op := range target.ops { + source := "AX" + if strings.HasPrefix(op, "MOVB") { + source = "AL" + if target.goarch == "386" { + source = "BP" // Go rewrites this Yrl32 byte source through BX. + } + } + fmt.Fprintf(&src, "\t%s %s, CX\n", op, source) + fmt.Fprintf(&src, "\t%s 8(BX), DX\n", op) + } + src.WriteString("\tMOVBWZX x+0(FP), SP\n\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "scalar_extension_forms": { + Name: "scalar_extension_forms", Args: []LLVMType{I8}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: I8, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "scalar-extension-"+target.name+".ll", "scalar-extension-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86ScalarExtensionMoveRejectsFormsOutsideGo127Tables(t *testing.T) { + tests := []struct { + name string + goarch string + triple string + instruction string + }{ + {name: "missing-source", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVBWZX AX"}, + {name: "too-many", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVBLZX AL, AX, BX"}, + {name: "immediate-source", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVBQZX $1, AX"}, + {name: "vector-source", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVBWZX X1, AX"}, + {name: "byte-source-for-word-class", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVWLZX AL, AX"}, + {name: "memory-destination", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVBLSX AL, (AX)"}, + {name: "byte-destination", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVWQZX AX, AL"}, + {name: "suffix", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "MOVLQZX.Z AX, BX"}, + {name: "386-byte-to-qword-sign", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVBQSX AL, AX"}, + {name: "386-byte-to-qword-zero", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVBQZX AL, AX"}, + {name: "386-word-to-qword-sign", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVWQSX AX, BX"}, + {name: "386-word-to-qword-zero", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVWQZX AX, BX"}, + {name: "386-long-to-qword-sign", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVLQSX AX, BX"}, + {name: "386-r8-source", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVWLZX R8, AX"}, + {name: "386-r8-destination", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVBLZX AL, R8"}, + {name: "386-sp-byte-source", goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "MOVBWZX SP, AX"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + src := "TEXT invalid_scalar_extension(SB),NOSPLIT,$0-0\n\t" + test.instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: test.triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{ + "invalid_scalar_extension": {Name: "invalid_scalar_extension", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q for %s outside Go 1.27's ymb_rl/yml_rl tables", test.instruction, test.goarch) + } + }) + } +} + +func TestTranslateX86MaskLogicalCompleteGo127Forms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT mask_logical_forms(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"KAND", "KANDN", "KOR", "KXNOR", "KXOR"} { + for _, width := range []string{"B", "W", "D", "Q"} { + fmt.Fprintf(&src, "\t%s%s K1, K2, K3\n", stem, width) + } + } + for _, stem := range []string{"KNOT", "KTEST", "KORTEST"} { + for _, width := range []string{"B", "W", "D", "Q"} { + fmt.Fprintf(&src, "\t%s%s K1, K2\n", stem, width) + } + } + src.WriteString("\tRET\n") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "mask_logical_forms": {Name: "mask_logical_forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "mask-logical-"+target.name+".ll", "mask-logical-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86MaskLogicalRejectsFormsOutsideGo127Tables(t *testing.T) { + for _, instruction := range []string{ + "KXNORW K1, K2", + "KXNORW K1, K2, K3, K4", + "KANDW K1, K2, AX", + "KANDNW K1, (AX), K3", + "KORQ $1, K2, K3", + "KXORB K1, K2, K8", + "KNOTD K1", + "KNOTQ K1, K2, K3", + "KNOTW AX, K2", + "KTESTB K1, (AX)", + "KTESTW K1, K2, K3", + "KORTESTD K1", + "KORTESTQ.Z K1, K2", + "KXORQ.Z K1, K2, K3", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalid_mask_logical(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + return + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + } { + if _, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "invalid_mask_logical": {Name: "invalid_mask_logical", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q for %s outside Go 1.27's _ykaddb/_yknotb tables", instruction, target.goarch) + } + } + }) + } +} + +func TestTranslateX86MaskMoveCompleteGo127Forms(t *testing.T) { + // Go 1.27 assigns KMOVB/W/D/Q the same _ykmovb table. Its four rows are: + // K -> memory, K -> GP, K-or-memory -> K, and GP -> K. Ykm therefore also + // includes the K -> K form. Exercise every row plus each Plan 9 memory + // spelling accepted as Ym, on both x86 architectures and all CI object + // formats. + var src strings.Builder + src.WriteString("TEXT mask_move_forms(SB),NOSPLIT,$0-16\n") + for _, op := range []string{"KMOVB", "KMOVW", "KMOVD", "KMOVQ"} { + fmt.Fprintf(&src, "\t%s K1, 16(BX)\n", op) + fmt.Fprintf(&src, "\t%s K1, AX\n", op) + fmt.Fprintf(&src, "\t%s K1, K2\n", op) + fmt.Fprintf(&src, "\t%s K0, K7\n", op) + fmt.Fprintf(&src, "\t%s 16(BX), K2\n", op) + fmt.Fprintf(&src, "\t%s AX, K2\n", op) + fmt.Fprintf(&src, "\t%s K5, SP\n", op) + fmt.Fprintf(&src, "\t%s SP, K5\n", op) + fmt.Fprintf(&src, "\t%s x+0(FP), K3\n", op) + fmt.Fprintf(&src, "\t%s K3, ret+8(FP)\n", op) + fmt.Fprintf(&src, "\t%s mask_move_source(SB), K4\n", op) + fmt.Fprintf(&src, "\t%s K4, mask_move_destination(SB)\n", op) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + targetSource := src.String() + if target.goarch == "amd64" { + var highRegisters strings.Builder + for _, op := range []string{"KMOVB", "KMOVW", "KMOVD", "KMOVQ"} { + fmt.Fprintf(&highRegisters, "\t%s K6, R15\n", op) + fmt.Fprintf(&highRegisters, "\t%s R15, K6\n", op) + } + targetSource += highRegisters.String() + } + targetSource += "\tRET\n" + file, err := Parse(ArchAMD64, targetSource) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "mask_move_forms": { + Name: "mask_move_forms", Args: []LLVMType{I64}, Ret: I64, + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: I64, Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 8, Type: I64, Index: 0, Field: -1}}, + }, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "mask-move-"+target.name+".ll", "mask-move-"+target.name+".o", ll) + }) + } +} + +func TestTranslate386MaskMoveRejectsAMD64OnlyYrlRegisters(t *testing.T) { + for _, instruction := range []string{"KMOVB K1, R8", "KMOVW R8, K1", "KMOVD K1, R15", "KMOVQ R15, K1"} { + src := "TEXT invalid_mask_move_386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalid_mask_move_386": {Name: "invalid_mask_move_386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q for 386 outside Go 1.27's Yrl class", instruction) + } + } +} + +func TestTranslateX86MaskMoveRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "KMOVB K1", + "KMOVW K1, K2, K3", + "KMOVD $1, K1", + "KMOVQ K1, $1", + "KMOVB 8(AX), BX", + "KMOVW AX, 8(BX)", + "KMOVD AX, BX", + "KMOVQ 8(AX), 16(BX)", + "KMOVB X1, K2", + "KMOVW K1, X2", + "KMOVD K8, AX", + "KMOVQ AX, K8", + "KMOVQ.Z K1, K2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT invalid_mask_move(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + return + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + } { + if _, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "invalid_mask_move": {Name: "invalid_mask_move", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q for %s outside Go 1.27's _ykmovb table", instruction, target.goarch) + } + } + }) + } +} + +func TestTranslateX86GatherCompleteGo127Forms(t *testing.T) { + // Go 1.27 has eight data-gather instructions over three operand tables, + // plus eight EVEX gather-prefetch instructions over two tables. Generate + // every row of all five tables for each opcode. The 386 assembler accepts + // EVEX gather with X/Y/Z0..7 VSIB indices; amd64 additionally accepts the + // high EVEX register classes. + dataGroups := []struct { + ops []string + table string + }{ + {ops: []string{"VGATHERDPS", "VGATHERQPD", "VPGATHERDD", "VPGATHERQQ"}, table: "dps"}, + {ops: []string{"VGATHERDPD", "VPGATHERDQ"}, table: "dpd"}, + {ops: []string{"VGATHERQPS", "VPGATHERQD"}, table: "qps"}, + } + prefetchGroups := []struct { + ops []string + indexWidth string + }{ + {ops: []string{"VGATHERPF0DPD", "VGATHERPF1DPD"}, indexWidth: "Y"}, + {ops: []string{ + "VGATHERPF0DPS", "VGATHERPF0QPD", "VGATHERPF0QPS", + "VGATHERPF1DPS", "VGATHERPF1QPD", "VGATHERPF1QPS", + }, indexWidth: "Z"}, + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT gather_forms(SB),NOSPLIT,$0-0\n") + for _, group := range dataGroups { + for _, op := range group.ops { + switch group.table { + case "dps": + fmt.Fprintf(&src, "\t%s X1, (BX)(X2*1), X3\n", op) + fmt.Fprintf(&src, "\t%s Y1, 4(BX)(Y2*2), Y3\n", op) + fmt.Fprintf(&src, "\t%s 8(X2*4), K1, X3\n", op) + fmt.Fprintf(&src, "\t%s 12(BX)(Y2*8), K1, Y3\n", op) + fmt.Fprintf(&src, "\t%s 16(BX)(Z2*4), K1, Z3\n", op) + case "dpd": + fmt.Fprintf(&src, "\t%s X1, (BX)(X2*1), X3\n", op) + fmt.Fprintf(&src, "\t%s Y1, 8(BX)(X2*2), Y3\n", op) + fmt.Fprintf(&src, "\t%s 16(X2*4), K1, X3\n", op) + fmt.Fprintf(&src, "\t%s 24(BX)(X2*8), K1, Y3\n", op) + fmt.Fprintf(&src, "\t%s 32(BX)(Y2*4), K1, Z3\n", op) + case "qps": + fmt.Fprintf(&src, "\t%s X1, (BX)(X2*1), X3\n", op) + fmt.Fprintf(&src, "\t%s X1, 4(BX)(Y2*2), X3\n", op) + fmt.Fprintf(&src, "\t%s 8(X2*4), K1, X3\n", op) + fmt.Fprintf(&src, "\t%s 12(BX)(Y2*8), K1, X3\n", op) + fmt.Fprintf(&src, "\t%s 16(BX)(Z2*4), K1, Y3\n", op) + } + // Unlike VSIB indices, Go 1.27 permits high EVEX X/Y + // destination registers even in 386 mode. + switch group.table { + case "dps": + fmt.Fprintf(&src, "\t%s (BX)(X2*4), K2, X20\n", op) + fmt.Fprintf(&src, "\t%s (BX)(Y2*4), K2, Y20\n", op) + case "dpd": + fmt.Fprintf(&src, "\t%s (BX)(X2*4), K2, X20\n", op) + fmt.Fprintf(&src, "\t%s (BX)(X2*4), K2, Y20\n", op) + case "qps": + fmt.Fprintf(&src, "\t%s (BX)(X2*8), K2, X20\n", op) + fmt.Fprintf(&src, "\t%s (BX)(Z2*8), K2, Y20\n", op) + } + if target.goarch == "amd64" { + switch group.table { + case "dps": + fmt.Fprintf(&src, "\t%s (BX)(X20*4), K2, X21\n", op) + fmt.Fprintf(&src, "\t%s (BX)(Y20*4), K2, Y21\n", op) + fmt.Fprintf(&src, "\t%s (BX)(Z20*4), K2, Z21\n", op) + case "dpd": + fmt.Fprintf(&src, "\t%s (BX)(X20*4), K2, X21\n", op) + fmt.Fprintf(&src, "\t%s (BX)(X20*4), K2, Y21\n", op) + fmt.Fprintf(&src, "\t%s (BX)(Y20*4), K2, Z21\n", op) + case "qps": + fmt.Fprintf(&src, "\t%s (BX)(X20*8), K2, X21\n", op) + fmt.Fprintf(&src, "\t%s (BX)(Y20*8), K2, X21\n", op) + fmt.Fprintf(&src, "\t%s (BX)(Z20*8), K2, Y21\n", op) + } + } + } + } + for _, group := range prefetchGroups { + for _, op := range group.ops { + fmt.Fprintf(&src, "\t%s K1, 40(BX)(%s2*4)\n", op, group.indexWidth) + if target.goarch == "amd64" { + fmt.Fprintf(&src, "\t%s K7, 48(%s20*8)\n", op, group.indexWidth) + } + } + } + src.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "gather_forms": {Name: "gather_forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "gather-"+target.name+".ll", "gather-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86GatherRejectsFormsOutsideGo127Tables(t *testing.T) { + tests := []struct { + name string + instruction string + }{ + {name: "missing-mask", instruction: "VPGATHERDD (AX)(X2*4), X3"}, + {name: "too-many", instruction: "VGATHERDPS (AX)(X2*4), K1, K2, X3"}, + {name: "plain-memory", instruction: "VPGATHERDD (AX), K1, X3"}, + {name: "gp-index", instruction: "VPGATHERDD (AX)(CX*4), K1, X3"}, + {name: "bad-scale", instruction: "VPGATHERDD (AX)(X2*3), K1, X3"}, + {name: "k0-mask", instruction: "VPGATHERDD (AX)(X2*4), K0, X3"}, + {name: "vector-mask-in-evex", instruction: "VPGATHERDD (AX)(X2*4), X1, X3"}, + {name: "k-mask-in-vex", instruction: "VPGATHERDD K1, (AX)(X2*4), X3"}, + {name: "dps-wrong-index", instruction: "VPGATHERDD (AX)(Y2*4), K1, X3"}, + {name: "dps-wrong-destination", instruction: "VPGATHERDD (AX)(X2*4), K1, Y3"}, + {name: "dpd-wrong-index", instruction: "VPGATHERDQ (AX)(Y2*4), K1, Y3"}, + {name: "dpd-wrong-destination", instruction: "VPGATHERDQ (AX)(Y2*4), K1, X3"}, + {name: "qps-wrong-index", instruction: "VPGATHERQD (AX)(Y2*8), K1, Y3"}, + {name: "qps-wrong-destination", instruction: "VPGATHERQD (AX)(Z2*8), K1, Z3"}, + {name: "vex-mask-index-alias", instruction: "VPGATHERDD X2, (AX)(X2*4), X3"}, + {name: "vex-mask-dest-alias", instruction: "VPGATHERDD X3, (AX)(X2*4), X3"}, + {name: "vex-index-dest-alias", instruction: "VPGATHERDD X1, (AX)(X3*4), X3"}, + {name: "evex-index-dest-alias", instruction: "VPGATHERDD (AX)(X3*4), K1, X3"}, + {name: "zero-suffix", instruction: "VPGATHERDD.Z (AX)(X2*4), K1, X3"}, + {name: "broadcast-suffix", instruction: "VPGATHERQQ.BCST (AX)(X2*8), K1, X3"}, + {name: "prefetch-k0", instruction: "VGATHERPF0DPD K0, (AX)(Y2*8)"}, + {name: "prefetch-wrong-index", instruction: "VGATHERPF0DPD K1, (AX)(Z2*8)"}, + {name: "prefetch-extra-dest", instruction: "VGATHERPF1DPS K1, (AX)(Z2*4), Z3"}, + {name: "prefetch-suffix", instruction: "VGATHERPF1QPS.Z K1, (AX)(Z2*8)"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + src := "TEXT invalid_gather(SB),NOSPLIT,$0-0\n\t" + test.instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + return + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + } { + if _, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "invalid_gather": {Name: "invalid_gather", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q for %s outside Go 1.27's gather tables", test.instruction, target.goarch) + } + } + }) + } +} + +func TestTranslate386GatherRejectsHighVSIBAndZRegisters(t *testing.T) { + for _, instruction := range []string{ + "VPGATHERDD (AX)(X8*4), K1, X3", + "VPGATHERDQ (AX)(Y8*4), K1, Z3", + "VPGATHERQD (AX)(Z8*8), K1, Y3", + "VPGATHERDD (AX)(Z2*4), K1, Z8", + "VGATHERPF0DPD K1, (AX)(Y8*8)", + "VGATHERPF1DPS K1, (AX)(Z8*4)", + } { + src := "TEXT invalid_gather_386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "invalid_gather_386": {Name: "invalid_gather_386", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's 386 VSIB/register classes", instruction) + } + } +} + +func TestTranslateAMD64TernaryLogicCompleteGo127Forms(t *testing.T) { + // VPTERNLOGD/Q share Go 1.27's six-row _yvalignd table: X/Y/Z, + // each with an unmasked and K1-K7 masked row. Their EVEX encodings add + // scalar D/Q broadcast and zeroing. Exercise every row/suffix combination, + // high EVEX registers, and every value in the unsigned-imm8 truth table. + var src strings.Builder + src.WriteString("TEXT ternary_logic_forms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VPTERNLOGD", "VPTERNLOGQ"} { + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&src, "\t%s $0, %s0, %s1, %s2\n", op, width, width, width) + fmt.Fprintf(&src, "\t%s $255, 8(BX), %s3, %s4\n", op, width, width) + fmt.Fprintf(&src, "\t%s $0xd8, %s5, %s6, K1, %s7\n", op, width, width, width) + fmt.Fprintf(&src, "\t%s.Z $0xaa, 16(BX), %s8, K2, %s9\n", op, width, width) + fmt.Fprintf(&src, "\t%s.BCST $0xcc, 24(BX), %s10, %s11\n", op, width, width) + fmt.Fprintf(&src, "\t%s.BCST.Z $0xf0, 32(BX), %s12, K3, %s13\n", op, width, width) + } + fmt.Fprintf(&src, "\t%s $0x96, X29, X30, X31\n", op) + fmt.Fprintf(&src, "\t%s $0x96, Y29, Y30, Y31\n", op) + fmt.Fprintf(&src, "\t%s $0x96, Z29, Z30, Z31\n", op) + } + for immediate := 0; immediate <= 255; immediate++ { + fmt.Fprintf(&src, "\tVPTERNLOGD $%d, X0, X1, X2\n", immediate) + fmt.Fprintf(&src, "\tVPTERNLOGQ $%d, X3, X4, X5\n", immediate) + } + src.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "ternary_logic_forms": {Name: "ternary_logic_forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "ternary-logic-"+target.name+".ll", "ternary-logic-"+target.name+".o", ll) + }) + } +} + +func TestAMD64TernaryLogicTruthTableOrderingExhaustive(t *testing.T) { + for immediate := 0; immediate <= 255; immediate++ { + for truthIndex := 0; truthIndex < 8; truthIndex++ { + a := truthIndex&4 != 0 + b := truthIndex&2 != 0 + third := truthIndex&1 != 0 + want := immediate&(1<i32) error = %v", err) @@ -285,8 +300,8 @@ func TestAMD64CtxHelperEdges(t *testing.T) { "alloca <64 x i8>", "alloca i64", "ptrtoint ptr %arg0 to i64", - "bitcast double %arg6 to i64", - "bitcast float %arg7 to i32", + "load double, ptr %fp_arg_48", + "load float, ptr %fp_arg_56", "trunc i64 11 to i32", "inttoptr i64 12 to ptr", "bitcast i64 13 to double", @@ -505,6 +520,20 @@ func TestAMD64AtomicAndBranchEdges(t *testing.T) { if err := c.tailCallAndRet(Operand{Kind: OpReg, Reg: AX}); err == nil { t.Fatalf("tailCallAndRet(non-sym) unexpectedly succeeded") } + + var b386 strings.Builder + c386 := newX86Ctx(&b386, Func{}, FuncSig{Name: "example.ptr386", Ret: Ptr}, testResolveSym("example"), map[string]FuncSig{ + "example.word386": {Name: "example.word386", Ret: I32}, + }, "386", "i386-unknown-linux-gnu", false) + if err := c386.emitEntryAllocas(); err != nil { + t.Fatal(err) + } + if err := c386.tailCallAndRet(Operand{Kind: OpSym, Sym: "word386(SB)"}); err != nil { + t.Fatalf("386 tailCallAndRet(i32 -> ptr) error = %v", err) + } + if got := b386.String(); !strings.Contains(got, "inttoptr i32") || !strings.Contains(got, "ret ptr") { + t.Fatalf("386 tailCallAndRet(i32 -> ptr) output:\n%s", got) + } if err := c.tailCallIndirectAddrAndRet("123"); err != nil { t.Fatalf("tailCallIndirectAddrAndRet() error = %v", err) } @@ -556,6 +585,9 @@ func TestAMD64ArithmeticCoverage(t *testing.T) { t.Fatalf("lowerArith(%s) = (%v, %v, %v)", op, ok, term, err) } } + if ok, term, err := c.lowerScalarShiftRotate("RCRQ", Instr{Raw: "RCRQ $1, AX", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}}}); !ok || term || err != nil { + t.Fatalf("lowerScalarShiftRotate(RCRQ) = (%v, %v, %v)", ok, term, err) + } mustLower("PUSHQ", Instr{Raw: "PUSHQ $1", Args: []Operand{{Kind: OpImm, Imm: 1}}}) mustLower("POPQ", Instr{Raw: "POPQ CX", Args: []Operand{{Kind: OpReg, Reg: CX}}}) @@ -572,7 +604,6 @@ func TestAMD64ArithmeticCoverage(t *testing.T) { mustLower("STOSQ", Instr{Raw: "STOSQ"}) mustLower("NEGL", Instr{Raw: "NEGL AX", Args: []Operand{{Kind: OpReg, Reg: AX}}}) mustLower("NEGL", Instr{Raw: "NEGL 4(BX)", Args: []Operand{{Kind: OpMem, Mem: MemRef{Base: BX, Off: 4}}}}) - mustLower("RCRQ", Instr{Raw: "RCRQ $1, AX", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}}}) mustLower("ADDQ", Instr{Raw: "ADDQ $2, AX", Args: []Operand{{Kind: OpImm, Imm: 2}, {Kind: OpReg, Reg: AX}}}) mustLower("SUBQ", Instr{Raw: "SUBQ CX, 8(BX)", Args: []Operand{{Kind: OpReg, Reg: CX}, {Kind: OpMem, Mem: MemRef{Base: BX, Off: 8}}}}) mustLower("XORQ", Instr{Raw: "XORQ $3, AX", Args: []Operand{{Kind: OpImm, Imm: 3}, {Kind: OpReg, Reg: AX}}}) @@ -581,8 +612,8 @@ func TestAMD64ArithmeticCoverage(t *testing.T) { mustLower("ADCQ", Instr{Raw: "ADCQ $1, AX", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}}}) mustLower("ADCB", Instr{Raw: "ADCB $1, AL", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AL}}}) mustLower("SBBQ", Instr{Raw: "SBBQ $1, AX", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}}}) - mustLower("ADCXQ", Instr{Raw: "ADCXQ $1, AX", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}}}) - mustLower("ADOXQ", Instr{Raw: "ADOXQ $1, AX", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}}}) + mustLower("ADCXQ", Instr{Raw: "ADCXQ CX, AX", Args: []Operand{{Kind: OpReg, Reg: CX}, {Kind: OpReg, Reg: AX}}}) + mustLower("ADOXQ", Instr{Raw: "ADOXQ CX, AX", Args: []Operand{{Kind: OpReg, Reg: CX}, {Kind: OpReg, Reg: AX}}}) mustLower("ADDL", Instr{Raw: "ADDL $1, AX", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}}}) mustLower("ADDB", Instr{Raw: "ADDB CL, DX", Args: []Operand{{Kind: OpReg, Reg: CL}, {Kind: OpReg, Reg: DX}}}) mustLower("SUBL", Instr{Raw: "SUBL CX, 12(BX)", Args: []Operand{{Kind: OpReg, Reg: CX}, {Kind: OpMem, Mem: MemRef{Base: BX, Off: 12}}}}) @@ -715,8 +746,8 @@ func TestAMD64EcosystemScalarValidationCoverage(t *testing.T) { {Raw: string(op) + " X0, AX", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: AX}}}, {Raw: string(op) + " AX, X0", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("X0")}}}, } { - if ok, term, err := c.lowerArith(op, ins); ok || term || err != nil { - t.Fatalf("lowerArith(%s) invalid form = (%v, %v, %v), want unsupported", op, ok, term, err) + if ok, term, err := c.lowerArith(op, ins); !ok || term || err == nil { + t.Fatalf("lowerArith(%s) invalid form = (%v, %v, %v), want recognized validation error", op, ok, term, err) } } } @@ -814,7 +845,7 @@ func TestAMD64ADCBUsesCarryFlag(t *testing.T) { "store i1 true, ptr %flags_cf", "load i1, ptr %flags_cf", "zext i1 %", - "add i8", + "add i16", "zext i8", "icmp ugt i16", "shl i64", @@ -923,7 +954,9 @@ func TestAMD64VectorCoverage(t *testing.T) { mustLower("MOVOU", Instr{Raw: "MOVOU X0, 112(BX)", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpMem, Mem: MemRef{Base: BX, Off: 112}}}}) mustLower("PXOR", Instr{Raw: "PXOR X0, X1", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("X1")}}}) mustLower("PAND", Instr{Raw: "PAND X0, X1", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("X1")}}}) - mustLower("PANDN", Instr{Raw: "PANDN X0, X1", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("X1")}}}) + if ok, term, err := c.lowerPackedAndNot("PANDN", Instr{Raw: "PANDN X0, X1", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("X1")}}}); !ok || term || err != nil { + t.Fatalf("lowerPackedAndNot(PANDN) = (%v, %v, %v)", ok, term, err) + } mustLower("PADDL", Instr{Raw: "PADDL X0, X1", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("X1")}}}) mustLower("PADDQ", Instr{Raw: "PADDQ X0, X1", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("X1")}}}) mustLower("PSUBL", Instr{Raw: "PSUBL X0, X1", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("X1")}}}) @@ -966,9 +999,6 @@ func TestAMD64VectorCoverage(t *testing.T) { if got := llvmShiftLeftBytesMask(3); !strings.Contains(got, "i32 16") { t.Fatalf("llvmShiftLeftBytesMask(3) = %q", got) } - if got := llvmAlignRightBytesMask(20); !strings.Contains(got, "i32 20") { - t.Fatalf("llvmAlignRightBytesMask(20) = %q", got) - } if got := llvmAllOnesI8Vec(4); got != "" { t.Fatalf("llvmAllOnesI8Vec(4) = %q", got) } @@ -1181,7 +1211,7 @@ func TestAMD64FPMovCoverage(t *testing.T) { c.setCmpFlags("1", "2") for _, ins := range []Instr{ {Op: "CMOVQLT", Args: []Operand{{Kind: OpReg, Reg: CX}, {Kind: OpReg, Reg: DX}}, Raw: "CMOVQLT CX, DX"}, - {Op: "MOVLQSX", Args: []Operand{{Kind: OpImm, Imm: 21}, {Kind: OpReg, Reg: AX}}, Raw: "MOVLQSX $21, AX"}, + {Op: "MOVLQSX", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: AX}}, Raw: "MOVLQSX AX, AX"}, {Op: "MOVLQSX", Args: []Operand{{Kind: OpReg, Reg: BX}, {Kind: OpReg, Reg: CX}}, Raw: "MOVLQSX BX, CX"}, {Op: "MOVLQSX", Args: []Operand{{Kind: OpFP, FPOffset: 16}, {Kind: OpReg, Reg: DX}}, Raw: "MOVLQSX arg+16(FP), DX"}, {Op: "MOVLQSX", Args: []Operand{{Kind: OpMem, Mem: MemRef{Base: SI, Off: 4}}, {Kind: OpReg, Reg: SI}}, Raw: "MOVLQSX 4(SI), SI"}, @@ -1329,7 +1359,7 @@ func TestAMD64CmpBtCoverage(t *testing.T) { if _, _, err := c.lowerCmpBt("TESTQ", Instr{Raw: "TESTQ AX", Args: []Operand{{Kind: OpReg, Reg: AX}}}); err == nil { t.Fatalf("short TESTQ unexpectedly succeeded") } - if _, _, err := c.lowerCmpBt("BTQ", Instr{Raw: "BTQ AX, BX", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: BX}}}); err == nil { + if _, _, err := c.lowerCmpBt("BTQ", Instr{Raw: "BTQ (AX), BX", Args: []Operand{{Kind: OpMem, Mem: MemRef{Base: AX}}, {Kind: OpReg, Reg: BX}}}); err == nil { t.Fatalf("bad BTQ unexpectedly succeeded") } if _, _, err := c.lowerCmpBt("BTSQ", Instr{Raw: "BTSQ AX", Args: []Operand{{Kind: OpReg, Reg: AX}}}); err == nil { @@ -1403,7 +1433,7 @@ func TestAMD64MovSyscallAndCRC32Coverage(t *testing.T) { } } - checkMov("MOVLQSX", Instr{Raw: "MOVLQSX $7, AX", Args: []Operand{{Kind: OpImm, Imm: 7}, {Kind: OpReg, Reg: AX}}}) + checkMov("MOVLQSX", Instr{Raw: "MOVLQSX AX, AX", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: AX}}}) checkMov("MOVLQSX", Instr{Raw: "MOVLQSX BX, CX", Args: []Operand{{Kind: OpReg, Reg: BX}, {Kind: OpReg, Reg: CX}}}) checkMov("MOVLQSX", Instr{Raw: "MOVLQSX arg+0(FP), DX", Args: []Operand{{Kind: OpFP, FPOffset: 0}, {Kind: OpReg, Reg: DX}}}) checkMov("MOVLQSX", Instr{Raw: "MOVLQSX 8(BX), SI", Args: []Operand{{Kind: OpMem, Mem: MemRef{Base: BX, Off: 8}}, {Kind: OpReg, Reg: SI}}}) @@ -1457,8 +1487,8 @@ func TestAMD64MovSyscallAndCRC32Coverage(t *testing.T) { } cBadReg, _ := newAMD64CtxWithFuncForTest(t, Func{}, sig, nil) - if ok, term, err := cBadReg.lowerMov("MOVB", Instr{Raw: "MOVB BAD, ret+24(FP)", Args: []Operand{{Kind: OpReg, Reg: Reg("BAD")}, {Kind: OpFP, FPOffset: 24}}}); !ok || term || err != nil { - t.Fatalf("MOVB missing src reg = (%v, %v, %v)", ok, term, err) + if ok, term, err := cBadReg.lowerMov("MOVB", Instr{Raw: "MOVB BAD, ret+24(FP)", Args: []Operand{{Kind: OpReg, Reg: Reg("BAD")}, {Kind: OpFP, FPOffset: 24}}}); !ok || term || err == nil { + t.Fatalf("MOVB invalid src reg = (%v, %v, %v), want handled error", ok, term, err) } if ok, term, err := cBadReg.lowerMov("CMOVQLT", Instr{Raw: "CMOVQLT BAD, BX", Args: []Operand{{Kind: OpReg, Reg: Reg("BAD")}, {Kind: OpReg, Reg: BX}}}); !ok || term || err != nil { t.Fatalf("CMOVQLT missing regs = (%v, %v, %v)", ok, term, err) @@ -1484,7 +1514,7 @@ func TestAMD64MovSyscallAndCRC32Coverage(t *testing.T) { t.Fatalf("MOVL bad src mem = (%v, %v, %v)", ok, term, err) } - if ok, term, err := c.lowerMov("MOVLQSX", Instr{Raw: "MOVLQSX broken, AX", Args: []Operand{{Kind: OpSym, Sym: "broken"}, {Kind: OpReg, Reg: AX}}}); !ok || term || err != nil { + if ok, term, err := c.lowerMov("MOVLQSX", Instr{Raw: "MOVLQSX broken, AX", Args: []Operand{{Kind: OpSym, Sym: "broken"}, {Kind: OpReg, Reg: AX}}}); !ok || term || err == nil { t.Fatalf("MOVLQSX bad sym = (%v, %v, %v)", ok, term, err) } if ok, term, err := c.lowerMov("MOVB", Instr{Raw: "MOVB broken, AX", Args: []Operand{{Kind: OpSym, Sym: "broken"}, {Kind: OpReg, Reg: AX}}}); !ok || term || err != nil { @@ -1543,7 +1573,7 @@ func TestAMD64MovSyscallAndCRC32Coverage(t *testing.T) { if ok, term, err := sysc.lowerSyscall("BAD", Instr{}); ok || term || err != nil { t.Fatalf("lowerSyscall(BAD) = (%v, %v, %v)", ok, term, err) } - if _, _, err := sysc.lowerCrc32("CRC32B", Instr{Raw: "CRC32B AX, BX", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: BX}}}); err == nil { + if _, _, err := sysc.lowerCrc32("CRC32B", Instr{Raw: "CRC32B $1, BX", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: BX}}}); err == nil { t.Fatalf("bad CRC32B unexpectedly succeeded") } if ok, term, err := sysc.lowerCrc32("BAD", Instr{}); ok || term || err != nil { @@ -1786,7 +1816,7 @@ func TestAMD64FPExtraCoverage(t *testing.T) { "fcmp une double", "fcmp ugt double", "fadd double", - "fmul double", + "call double @llvm.fma.f64", "fneg double", } { if !strings.Contains(out, want) { @@ -1866,7 +1896,7 @@ func TestAMD64VectorAliasAndErrorCoverage(t *testing.T) { check("MOVOU", Instr{Raw: "MOVOU example.global(SB), X0", Args: []Operand{{Kind: OpSym, Sym: "example.global(SB)"}, {Kind: OpReg, Reg: Reg("X0")}}}) check("MOVOA", Instr{Raw: "MOVOA X0, example.out(SB)", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpSym, Sym: "example.out(SB)"}}}) check("KMOVB", Instr{Raw: "KMOVB 8(BX), K1", Args: []Operand{{Kind: OpMem, Mem: MemRef{Base: BX, Off: 8}}, {Kind: OpReg, Reg: Reg("K1")}}}) - check("KMOVQ", Instr{Raw: "KMOVQ 8(BX), AX", Args: []Operand{{Kind: OpMem, Mem: MemRef{Base: BX, Off: 8}}, {Kind: OpReg, Reg: AX}}}) + check("KMOVD", Instr{Raw: "KMOVD K1, K7", Args: []Operand{{Kind: OpReg, Reg: Reg("K1")}, {Kind: OpReg, Reg: Reg("K7")}}}) check("VMOVDQU64", Instr{Raw: "VMOVDQU64 example.zin(SB), Z0", Args: []Operand{{Kind: OpSym, Sym: "example.zin(SB)"}, {Kind: OpReg, Reg: Reg("Z0")}}}) check("VMOVDQU64", Instr{Raw: "VMOVDQU64 Z0, example.zout(SB)", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpSym, Sym: "example.zout(SB)"}}}) check("VMOVDQU", Instr{Raw: "VMOVDQU example.yin(SB), Y0", Args: []Operand{{Kind: OpSym, Sym: "example.yin(SB)"}, {Kind: OpReg, Reg: Reg("Y0")}}}) @@ -1884,7 +1914,7 @@ func TestAMD64VectorAliasAndErrorCoverage(t *testing.T) { if _, _, err := c.lowerVec("MOVQ", Instr{Raw: "MOVQ X0, label", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpIdent, Ident: "label"}}}); err == nil { t.Fatalf("MOVQ bad dst unexpectedly succeeded") } - if ok, term, err := c.lowerVec("KXORQ", Instr{Raw: "KXORQ AX, K1, K2", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("K1")}, {Kind: OpReg, Reg: Reg("K2")}}}); ok || term || err != nil { + if ok, term, err := c.lowerVec("KXORQ", Instr{Raw: "KXORQ AX, K1, K2", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("K1")}, {Kind: OpReg, Reg: Reg("K2")}}}); !ok || term || err == nil { t.Fatalf("KXORQ non-k src = (%v, %v, %v)", ok, term, err) } if _, _, err := c.lowerVec("KMOVB", Instr{Raw: "KMOVB AX", Args: []Operand{{Kind: OpReg, Reg: AX}}}); err == nil { @@ -1902,19 +1932,19 @@ func TestAMD64VectorAliasAndErrorCoverage(t *testing.T) { if _, _, err := c.lowerVec("VPERMB", Instr{Raw: "VPERMB Z0, Z1, 7", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpImm, Imm: 7}}}); err == nil { t.Fatalf("VPERMB non-reg dst unexpectedly succeeded") } - if ok, term, err := c.lowerVec("VPERMB", Instr{Raw: "VPERMB Z0, Z1, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("Y0")}}}); ok || term || err != nil { + if ok, term, err := c.lowerVec("VPERMB", Instr{Raw: "VPERMB Z0, Z1, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("Y0")}}}); !ok || term || err == nil { t.Fatalf("VPERMB wrong dst reg = (%v, %v, %v)", ok, term, err) } if _, _, err := c.lowerVec("VPERMB", Instr{Raw: "VPERMB Z0, Z1, 7, Z2", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpImm, Imm: 7}, {Kind: OpReg, Reg: Reg("Z2")}}}); err == nil { t.Fatalf("VPERMB non-reg mask unexpectedly succeeded") } - if ok, term, err := c.lowerVec("VPERMB", Instr{Raw: "VPERMB Z0, Z1, AX, Z2", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Z2")}}}); ok || term || err != nil { + if ok, term, err := c.lowerVec("VPERMB", Instr{Raw: "VPERMB Z0, Z1, AX, Z2", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Z2")}}}); !ok || term || err == nil { t.Fatalf("VPERMB wrong mask reg = (%v, %v, %v)", ok, term, err) } if _, _, err := c.lowerVec("VGF2P8AFFINEQB", Instr{Raw: "VGF2P8AFFINEQB Z0, Z1, Z2", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("Z2")}}}); err == nil { t.Fatalf("VGF2P8AFFINEQB short form unexpectedly succeeded") } - if ok, term, err := c.lowerVec("VGF2P8AFFINEQB", Instr{Raw: "VGF2P8AFFINEQB $1, Z0, Z1, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("Y0")}}}); ok || term || err != nil { + if ok, term, err := c.lowerVec("VGF2P8AFFINEQB", Instr{Raw: "VGF2P8AFFINEQB $1, Z0, Z1, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("Y0")}}}); !ok || term || err == nil { t.Fatalf("VGF2P8AFFINEQB wrong dst reg = (%v, %v, %v)", ok, term, err) } if _, _, err := c.lowerVec("VPERMI2B", Instr{Raw: "VPERMI2B Z0", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}}}); err == nil { @@ -1923,13 +1953,13 @@ func TestAMD64VectorAliasAndErrorCoverage(t *testing.T) { if _, _, err := c.lowerVec("VPERMI2B", Instr{Raw: "VPERMI2B Z0, Z1, 7", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpImm, Imm: 7}}}); err == nil { t.Fatalf("VPERMI2B non-reg dst unexpectedly succeeded") } - if ok, term, err := c.lowerVec("VPERMI2B", Instr{Raw: "VPERMI2B Z0, Z1, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("Y0")}}}); ok || term || err != nil { + if ok, term, err := c.lowerVec("VPERMI2B", Instr{Raw: "VPERMI2B Z0, Z1, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("Y0")}}}); !ok || term || err == nil { t.Fatalf("VPERMI2B wrong dst reg = (%v, %v, %v)", ok, term, err) } if _, _, err := c.lowerVec("VPERMI2B", Instr{Raw: "VPERMI2B Z0, Z1, 7, Z2", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpImm, Imm: 7}, {Kind: OpReg, Reg: Reg("Z2")}}}); err == nil { t.Fatalf("VPERMI2B non-reg mask unexpectedly succeeded") } - if ok, term, err := c.lowerVec("VPERMI2B", Instr{Raw: "VPERMI2B Z0, Z1, AX, Z2", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Z2")}}}); ok || term || err != nil { + if ok, term, err := c.lowerVec("VPERMI2B", Instr{Raw: "VPERMI2B Z0, Z1, AX, Z2", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Z2")}}}); !ok || term || err == nil { t.Fatalf("VPERMI2B wrong mask reg = (%v, %v, %v)", ok, term, err) } for _, tc := range []struct { @@ -1938,27 +1968,27 @@ func TestAMD64VectorAliasAndErrorCoverage(t *testing.T) { want string wantHandled bool }{ - {"VPOPCNTB", Instr{Raw: "VPOPCNTB Z0, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst", false}, + {"VPOPCNTB", Instr{Raw: "VPOPCNTB Z0, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst", true}, {"VPCMPUQ", Instr{Raw: "VPCMPUQ $3, Z0, Z1, K1", Args: []Operand{{Kind: OpImm, Imm: 3}, {Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("K1")}}}, "bad imm", true}, {"VPCMPUQ", Instr{Raw: "VPCMPUQ $1, Z0, Z1, AX", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: AX}}}, "wrong dst reg", false}, - {"VPCOMPRESSQ", Instr{Raw: "VPCOMPRESSQ Z0, AX, Z1", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Z1")}}}, "wrong mask", false}, - {"VPCOMPRESSQ", Instr{Raw: "VPCOMPRESSQ Z0, K1, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("K1")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst", false}, + {"VPCOMPRESSQ", Instr{Raw: "VPCOMPRESSQ Z0, AX, Z1", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Z1")}}}, "wrong mask", true}, + {"VPCOMPRESSQ", Instr{Raw: "VPCOMPRESSQ Z0, K1, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("K1")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst", true}, {"VPXORQ", Instr{Raw: "VPXORQ Z0, Z1, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong z dst", true}, {"VPSHUFB", Instr{Raw: "VPSHUFB Y0, Y1, AX", Args: []Operand{{Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("Y1")}, {Kind: OpReg, Reg: AX}}}, "wrong dst", false}, - {"VPSHUFD", Instr{Raw: "VPSHUFD $1, X0, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong src class", false}, + {"VPSHUFD", Instr{Raw: "VPSHUFD $1, X0, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong src class", true}, {"VPSLLD", Instr{Raw: "VPSLLD Y0, Y1", Args: []Operand{{Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("Y1")}}}, "short form", true}, - {"VPERM2I128", Instr{Raw: "VPERM2I128 $1, Y0, Y1, X0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("Y1")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong dst", false}, + {"VPERM2I128", Instr{Raw: "VPERM2I128 $1, Y0, Y1, X0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("Y1")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong dst", true}, {"VINSERTI128", Instr{Raw: "VINSERTI128 $1, X0, Y0, X1", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("X1")}}}, "wrong dst", false}, {"VMOVNTDQ", Instr{Raw: "VMOVNTDQ Y0, AX", Args: []Operand{{Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: AX}}}, "bad dst", true}, {"AESKEYGENASSIST", Instr{Raw: "AESKEYGENASSIST X0, X1", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("X1")}}}, "missing imm", true}, - {"VPTEST", Instr{Raw: "VPTEST X0, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong src class", false}, - {"PCMPESTRI", Instr{Raw: "PCMPESTRI $1, 8(BX), X0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpMem, Mem: MemRef{Base: BX, Off: 8}}, {Kind: OpReg, Reg: Reg("X0")}}}, "unsupported imm", true}, + {"VPTEST", Instr{Raw: "VPTEST X0, Y0", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong src class", true}, + {"PCMPESTRI", Instr{Raw: "PCMPESTRI $-1, 8(BX), X0", Args: []Operand{{Kind: OpImm, Imm: -1}, {Kind: OpMem, Mem: MemRef{Base: BX, Off: 8}}, {Kind: OpReg, Reg: Reg("X0")}}}, "invalid imm", true}, {"PCMPESTRI", Instr{Raw: "PCMPESTRI $0x0c, AX, X0", Args: []Operand{{Kind: OpImm, Imm: 0x0c}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("X0")}}}, "bad mem operand", true}, {"VPBLENDD", Instr{Raw: "VPBLENDD $1, Y0, Y1, X0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("Y1")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong dst", false}, {"VPBROADCASTB", Instr{Raw: "VPBROADCASTB Y0, Y1", Args: []Operand{{Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("Y1")}}}, "wrong src", false}, - {"VPSRLDQ", Instr{Raw: "VPSRLDQ $2, X0, Y0", Args: []Operand{{Kind: OpImm, Imm: 2}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong src class", false}, + {"VPSRLDQ", Instr{Raw: "VPSRLDQ $2, X0, Y0", Args: []Operand{{Kind: OpImm, Imm: 2}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong src class", true}, {"PUNPCKLBW", Instr{Raw: "PUNPCKLBW Y0, X0", Args: []Operand{{Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong src class", false}, - {"PSHUFHW", Instr{Raw: "PSHUFHW $1, X0, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst", false}, + {"PSHUFHW", Instr{Raw: "PSHUFHW $1, X0, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst", true}, {"SHUFPS", Instr{Raw: "SHUFPS $1, X0, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst", false}, {"MOVOU", Instr{Raw: "MOVOU AX, X0", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong src class", true}, {"MOVOU", Instr{Raw: "MOVOU X0, AX", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: AX}}}, "wrong dst class", false}, @@ -1966,21 +1996,21 @@ func TestAMD64VectorAliasAndErrorCoverage(t *testing.T) { {"PADDL", Instr{Raw: "PADDL X0, AX", Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: AX}}}, "wrong dst class", false}, {"PSLLL", Instr{Raw: "PSLLL AX, X0", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("X0")}}}, "non-imm shift", true}, {"PCMPEQL", Instr{Raw: "PCMPEQL Y0, X0", Args: []Operand{{Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong src class", false}, - {"VPCLMULQDQ", Instr{Raw: "VPCLMULQDQ $1, Z0, Z1, X0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong dst class", false}, - {"VPTERNLOGD", Instr{Raw: "VPTERNLOGD $0x95, Z0, Z1, Z2", Args: []Operand{{Kind: OpImm, Imm: 0x95}, {Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("Z2")}}}, "unsupported imm", true}, + {"VPCLMULQDQ", Instr{Raw: "VPCLMULQDQ $1, Z0, Z1, X0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong dst class", true}, + {"VPTERNLOGD", Instr{Raw: "VPTERNLOGD $0x100, Z0, Z1, Z2", Args: []Operand{{Kind: OpImm, Imm: 0x100}, {Kind: OpReg, Reg: Reg("Z0")}, {Kind: OpReg, Reg: Reg("Z1")}, {Kind: OpReg, Reg: Reg("Z2")}}}, "out-of-range imm", true}, {"VEXTRACTF32X4", Instr{Raw: "VEXTRACTF32X4 $1, X0, X1", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("X1")}}}, "wrong src class", false}, {"PCLMULQDQ", Instr{Raw: "PCLMULQDQ AX, X0, X1", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: Reg("X1")}}}, "missing imm", true}, {"PCMPEQB", Instr{Raw: "PCMPEQB Y0, X0", Args: []Operand{{Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong src class", false}, {"PMOVMSKB", Instr{Raw: "PMOVMSKB Y0, AX", Args: []Operand{{Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: AX}}}, "wrong src class", false}, {"PSHUFB", Instr{Raw: "PSHUFB Y0, X0", Args: []Operand{{Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong mask class", true}, {"PINSRQ", Instr{Raw: "PINSRQ AX, X0", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("X0")}}}, "short form", true}, - {"PINSRD", Instr{Raw: "PINSRD $1, AX, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst class", false}, - {"PINSRW", Instr{Raw: "PINSRW $1, AX, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst class", false}, - {"PINSRB", Instr{Raw: "PINSRB $1, AX, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst class", false}, + {"PINSRD", Instr{Raw: "PINSRD $1, AX, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst class", true}, + {"PINSRW", Instr{Raw: "PINSRW $1, AX, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst class", true}, + {"PINSRB", Instr{Raw: "PINSRB $1, AX, Y0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("Y0")}}}, "wrong dst class", true}, {"PEXTRB", Instr{Raw: "PEXTRB AX, X0, BX", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: BX}}}, "missing imm", true}, - {"PALIGNR", Instr{Raw: "PALIGNR $1, Y0, X0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong src class", false}, - {"PSRLDQ", Instr{Raw: "PSRLDQ $17, X0", Args: []Operand{{Kind: OpImm, Imm: 17}, {Kind: OpReg, Reg: Reg("X0")}}}, "invalid imm", true}, - {"PSLLDQ", Instr{Raw: "PSLLDQ $17, X0", Args: []Operand{{Kind: OpImm, Imm: 17}, {Kind: OpReg, Reg: Reg("X0")}}}, "invalid imm", true}, + {"PALIGNR", Instr{Raw: "PALIGNR $1, Y0, X0", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("Y0")}, {Kind: OpReg, Reg: Reg("X0")}}}, "wrong src class", true}, + {"PSRLDQ", Instr{Raw: "PSRLDQ $128, X0", Args: []Operand{{Kind: OpImm, Imm: 128}, {Kind: OpReg, Reg: Reg("X0")}}}, "invalid imm", true}, + {"PSLLDQ", Instr{Raw: "PSLLDQ $128, X0", Args: []Operand{{Kind: OpImm, Imm: 128}, {Kind: OpReg, Reg: Reg("X0")}}}, "invalid imm", true}, {"PSRLQ", Instr{Raw: "PSRLQ AX, X0", Args: []Operand{{Kind: OpReg, Reg: AX}, {Kind: OpReg, Reg: Reg("X0")}}}, "non-imm shift", true}, {"PEXTRD", Instr{Raw: "PEXTRD $1, X0, label", Args: []Operand{{Kind: OpImm, Imm: 1}, {Kind: OpReg, Reg: Reg("X0")}, {Kind: OpIdent, Ident: "label"}}}, "bad dst kind", true}, } { @@ -2012,6 +2042,40 @@ func TestAMD64VectorAliasAndErrorCoverage(t *testing.T) { } } +func TestAMD64RejectedLegacyVectorDestinationDoesNotMutateIR(t *testing.T) { + for _, test := range []struct { + op Op + handled bool + }{ + {op: "PSUBUSB"}, + {op: "PABSD"}, + {op: "PTEST", handled: true}, + } { + t.Run(string(test.op), func(t *testing.T) { + ins := Instr{ + Op: test.op, Raw: string(test.op) + " X0, AX", + Args: []Operand{{Kind: OpReg, Reg: Reg("X0")}, {Kind: OpReg, Reg: AX}}, + } + c, b := newAMD64CtxWithFuncForTest(t, Func{Instrs: []Instr{ins}}, FuncSig{Ret: Void}, nil) + beforeIR, beforeTmp := b.String(), c.tmp + ok, term, err := c.lowerVec(test.op, ins) + if test.handled { + if !ok || term || err == nil { + t.Fatalf("lowerVec(%s) = (%v, %v, %v), want handled rejection", test.op, ok, term, err) + } + } else if ok || term || err != nil { + t.Fatalf("lowerVec(%s) = (%v, %v, %v), want unhandled rejection", test.op, ok, term, err) + } + if got := b.String(); got != beforeIR { + t.Fatalf("lowerVec(%s) emitted IR before rejecting destination:\n%s", test.op, strings.TrimPrefix(got, beforeIR)) + } + if c.tmp != beforeTmp { + t.Fatalf("lowerVec(%s) advanced temporary counter from %d to %d", test.op, beforeTmp, c.tmp) + } + }) + } +} + func TestAMD64CtxAliasAndFPFallbackCoverage(t *testing.T) { sig := FuncSig{ Name: "example.ctxfallback", @@ -2055,7 +2119,7 @@ func TestAMD64CtxAliasAndFPFallbackCoverage(t *testing.T) { t.Fatalf("storeRegSized(%s, %s) error = %v", tc.r, tc.ty, err) } } - for _, r := range []Reg{AL, AH, BL, BH, CL, CH, DL, DH} { + for _, r := range []Reg{AL, AH, BL, BH, CL, CH, DL, DH, BPB, SIB, DIB, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B} { if got, err := c.loadReg(r); err != nil || got == "" { t.Fatalf("loadReg(%s) = (%q, %v)", r, got, err) } @@ -2075,6 +2139,17 @@ func TestAMD64CtxAliasAndFPFallbackCoverage(t *testing.T) { {CH, "35"}, {DL, "20"}, {DH, "36"}, + {BPB, "22"}, + {SIB, "23"}, + {DIB, "24"}, + {R8B, "25"}, + {R9B, "26"}, + {R10B, "27"}, + {R11B, "28"}, + {R12B, "29"}, + {R13B, "30"}, + {R14B, "31"}, + {R15B, "32"}, } { if err := c.storeReg(tc.r, tc.v); err != nil { t.Fatalf("storeReg(%s) error = %v", tc.r, err) diff --git a/amd64_lower_abs_sign.go b/amd64_lower_abs_sign.go new file mode 100644 index 00000000..9d884a73 --- /dev/null +++ b/amd64_lower_abs_sign.go @@ -0,0 +1,255 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedAbsSuffix struct { + broadcast bool + zeroing bool +} + +func parseAMD64PackedAbsSuffix(rawOp, baseOp string) (amd64PackedAbsSuffix, error) { + var result amd64PackedAbsSuffix + if rawOp == baseOp { + return result, nil + } + suffixes := strings.Split(strings.TrimPrefix(rawOp, baseOp+"."), ".") + for index, suffix := range suffixes { + switch suffix { + case "BCST": + if result.broadcast || result.zeroing || index != 0 { + return result, fmt.Errorf("amd64 %s has invalid or duplicate .BCST suffix", baseOp) + } + result.broadcast = true + case "Z": + if result.zeroing || index != len(suffixes)-1 { + return result, fmt.Errorf("amd64 %s has invalid or misplaced .Z suffix", baseOp) + } + result.zeroing = true + default: + return result, fmt.Errorf("amd64 %s has unsupported suffix .%s", baseOp, suffix) + } + } + return result, nil +} + +// lowerPackedAbsSign implements Go 1.27's complete PABS*, VPABS*, PSIGN*, +// and VPSIGN* families. VPABS B/W/D share _yvmovddup, VPABSQ uses +// _yvexpandpd, and VPSIGN B/W/D are the two-width VEX-only _yvaddsubpd rows. +func (c *amd64Ctx) lowerPackedAbsSign(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + if laneBits, matched := amd64PackedAbsLaneBits(baseOp); matched { + properties, err := parseAMD64PackedAbsSuffix(rawOp, baseOp) + if err != nil { + return true, false, fmt.Errorf("%w: %q", err, ins.Raw) + } + return c.lowerPackedAbs(baseOp, laneBits, ins, properties) + } + if laneBits, vector, matched := amd64PackedSignLaneBits(baseOp); matched { + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s does not accept suffixes: %q", baseOp, ins.Raw) + } + return c.lowerPackedSign(baseOp, laneBits, vector, ins) + } + return false, false, nil +} + +func amd64PackedAbsLaneBits(op string) (int, bool) { + switch op { + case "PABSB", "VPABSB": + return 8, true + case "PABSW", "VPABSW": + return 16, true + case "PABSD", "VPABSD": + return 32, true + case "VPABSQ": + return 64, true + default: + return 0, false + } +} + +func amd64PackedSignLaneBits(op string) (laneBits int, vector bool, matched bool) { + switch op { + case "PSIGNB", "VPSIGNB": + laneBits = 8 + case "PSIGNW", "VPSIGNW": + laneBits = 16 + case "PSIGND", "VPSIGND": + laneBits = 32 + default: + return 0, false, false + } + return laneBits, strings.HasPrefix(op, "V"), true +} + +func (c *amd64Ctx) lowerPackedAbs(baseOp string, laneBits int, ins Instr, properties amd64PackedAbsSuffix) (bool, bool, error) { + vector := strings.HasPrefix(baseOp, "V") + if !vector { + if properties != (amd64PackedAbsSuffix{}) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("amd64 %s expects X/m128 source and X destination: %q", baseOp, ins.Raw) + } + if !c.isGoLegacyPackedAbsSignRegister(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's X register class: %q", c.goarch, baseOp, ins.Raw) + } + if (ins.Args[0].Kind == OpReg && !c.isGoLegacyPackedAbsSignRegister(ins.Args[0])) || + (ins.Args[0].Kind != OpReg && !isAMD64MemoryOperand(ins.Args[0])) { + return true, false, fmt.Errorf("%s %s source must be an in-range X register or memory: %q", c.goarch, baseOp, ins.Raw) + } + values, err := c.loadPackedCompareLanes(ins.Args[0], 16, laneBits, false) + if err != nil { + return true, false, err + } + result := c.emitPackedAbs(values, 16, laneBits) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, 128/laneBits, laneBits, result) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) + } + + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 %s expects source, [K mask,] destination: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if properties.zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z requires K1-K7: %q", baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + if properties.broadcast && laneBits != 32 && laneBits != 64 { + return true, false, fmt.Errorf("amd64 %s has no Go 1.27 broadcast form: %q", baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s destination must be X, Y, or Z: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's vector class: %q", baseOp, ins.Raw) + } + source := ins.Args[0] + if properties.broadcast { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory source: %q", baseOp, ins.Raw) + } + } else if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("amd64 %s source width does not match its destination: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s source must be a matching vector register or memory: %q", baseOp, ins.Raw) + } + values, err := c.loadPackedCompareLanes(source, byteWidth, laneBits, properties.broadcast) + if err != nil { + return true, false, err + } + result := c.emitPackedAbs(values, byteWidth, laneBits) + lanes := byteWidth * 8 / laneBits + if masked { + mask, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, laneBits, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPackedAbs(values string, byteWidth, laneBits int) string { + lanes := byteWidth * 8 / laneBits + negative := c.newTmp() + negated := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt <%d x i%d> %s, zeroinitializer\n", negative, lanes, laneBits, values) + fmt.Fprintf(c.b, " %%%s = sub <%d x i%d> zeroinitializer, %s\n", negated, lanes, laneBits, values) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, <%d x i%d> %%%s, <%d x i%d> %s\n", result, lanes, negative, lanes, laneBits, negated, lanes, laneBits, values) + return "%" + result +} + +func (c *amd64Ctx) lowerPackedSign(baseOp string, laneBits int, vector bool, ins Instr) (bool, bool, error) { + wantArgs := 2 + if vector { + wantArgs = 3 + } + if len(ins.Args) != wantArgs { + return true, false, fmt.Errorf("amd64 %s expects %d operands: %q", baseOp, wantArgs, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s destination must be X or Y: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if vector { + if byteWidth != 16 && byteWidth != 32 || !c.isGoVEXPackedAbsSignRegister(destination, byteWidth) || !c.isGoVEXPackedAbsSignRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s requires matching in-range X or Y data registers: %q", c.goarch, baseOp, ins.Raw) + } + } else { + byteWidth = 16 + if !c.isGoLegacyPackedAbsSignRegister(destination) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's X register class: %q", c.goarch, baseOp, ins.Raw) + } + } + control := ins.Args[0] + if control.Kind == OpReg { + valid := c.isGoVEXPackedAbsSignRegister(control, byteWidth) + if !vector { + valid = c.isGoLegacyPackedAbsSignRegister(control) + } + if !valid { + return true, false, fmt.Errorf("%s %s control source is outside Go 1.27's register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(control) { + return true, false, fmt.Errorf("amd64 %s control source must be a matching vector or memory: %q", baseOp, ins.Raw) + } + controlValues, err := c.loadPackedCompareLanes(control, byteWidth, laneBits, false) + if err != nil { + return true, false, err + } + dataOperand := destination + if vector { + dataOperand = ins.Args[1] + } + dataValues, err := c.loadPackedCompareLanes(dataOperand, byteWidth, laneBits, false) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / laneBits + positive := c.newTmp() + negative := c.newTmp() + negated := c.newTmp() + nonpositive := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp sgt <%d x i%d> %s, zeroinitializer\n", positive, lanes, laneBits, controlValues) + fmt.Fprintf(c.b, " %%%s = icmp slt <%d x i%d> %s, zeroinitializer\n", negative, lanes, laneBits, controlValues) + fmt.Fprintf(c.b, " %%%s = sub <%d x i%d> zeroinitializer, %s\n", negated, lanes, laneBits, dataValues) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, <%d x i%d> %%%s, <%d x i%d> zeroinitializer\n", nonpositive, lanes, negative, lanes, laneBits, negated, lanes, laneBits) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, <%d x i%d> %s, <%d x i%d> %%%s\n", result, lanes, positive, lanes, laneBits, dataValues, lanes, laneBits, nonpositive) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) isGoLegacyPackedAbsSignRegister(operand Operand) bool { + if !amd64VEXVectorRegister(operand, 16) { + return false + } + index, _ := amd64ParseXReg(operand.Reg) + return c.goarch != "386" || index < 8 +} + +func (c *amd64Ctx) isGoVEXPackedAbsSignRegister(operand Operand, byteWidth int) bool { + return amd64VEXVectorRegister(operand, byteWidth) +} diff --git a/amd64_lower_abs_sign_test.go b/amd64_lower_abs_sign_test.go new file mode 100644 index 00000000..c19a1c6c --- /dev/null +++ b/amd64_lower_abs_sign_test.go @@ -0,0 +1,244 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86PackedAbsSignCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 uses yxm_q4 for the legacy PABS*/PSIGN* rows, + // _yvmovddup for VPABSB/W/D, _yvexpandpd for VPABSQ, and + // _yvaddsubpd for the VEX-only VPSIGN* rows. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT packedabssignforms(SB),NOSPLIT,$0-0\n") + for index, suffix := range []string{"B", "W", "D"} { + fmt.Fprintf(&source, "\tPABS%s X0, X1\n", suffix) + fmt.Fprintf(&source, "\tPABS%s %d(AX), X2\n", suffix, 16*index) + fmt.Fprintf(&source, "\tPSIGN%s X3, X4\n", suffix) + fmt.Fprintf(&source, "\tPSIGN%s %d(AX), X5\n", suffix, 48+16*index) + fmt.Fprintf(&source, "\tVPABS%s X6, X7\n", suffix) + fmt.Fprintf(&source, "\tVPABS%s %d(AX), Y1\n", suffix, 96+32*index) + fmt.Fprintf(&source, "\tVPABS%s X20, X21\n", suffix) + fmt.Fprintf(&source, "\tVPABS%s X8, K1, X9\n", suffix) + fmt.Fprintf(&source, "\tVPABS%s.Z %d(AX), K2, Y3\n", suffix, 192+32*index) + fmt.Fprintf(&source, "\tVPABS%s Z4, K3, Z5\n", suffix) + fmt.Fprintf(&source, "\tVPSIGN%s X8, X9, X10\n", suffix) + fmt.Fprintf(&source, "\tVPSIGN%s %d(AX), Y11, Y12\n", suffix, 288+32*index) + } + source.WriteString(` VPABSD.BCST 384(AX), Y11 + VPABSD.BCST.Z 388(AX), K4, Z6 + VPABSQ X0, X1 + VPABSQ 400(AX), Y2 + VPABSQ Z3, K5, Z4 + VPABSQ.Z 464(AX), K6, Z5 + VPABSQ.BCST 472(AX), X6 + VPABSQ.BCST.Z 480(AX), K7, Y7 + RET +`) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedabssignforms": {Name: "packedabssignforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"icmp slt <", "icmp sgt <", "sub <", "select <"} { + if !strings.Contains(ll, want) { + t.Fatalf("packed abs/sign IR is missing %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-abs-sign-"+target.name+".ll", "packed-abs-sign-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedAbsSignRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PABSB Y0, X1", + "PABSQ X0, X1", + "PABSD.Z X0, X1", + "VPABSB X0, Y1", + "VPABSW Y0, X1", + "VPABSD Z0, Y1", + "VPABSQ X0, Y1", + "VPABSQ X0, K0, X1", + "VPABSB.Z X0, X1", + "VPABSW.BCST (AX), X1", + "VPABSQ.BCST X0, X1", + "PSIGNB Y0, X1", + "PSIGNQ X0, X1", + "VPSIGNB X0, X1", + "VPSIGNW Z0, Z1, Z2", + "VPSIGND X0, K1, X1, X2", + "VPSIGNB.Z X0, X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedAbsSignRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PABSB X8, X0", + "PABSW X0, X8", + "PSIGND X8, X0", + } { + assertX86PackedAbsSignRejected(t, "386", "i386-unknown-linux-gnu", instruction) + } +} + +func assertX86PackedAbsSignRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed abs/sign tables", instruction) + } +} + +func TestAMD64PackedAbsSignRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT packedabssign(SB),NOSPLIT,$0-40 + MOVQ out+0(FP), AX + MOVQ source+8(FP), BX + MOVQ control+16(FP), CX + MOVQ old+24(FP), DX + MOVQ mask+32(FP), SI + KMOVQ SI, K1 + + MOVOU (BX), X0 + PABSB X0, X0 + MOVOU X0, 0(AX) + + MOVOU (BX), X0 + PSIGNW (CX), X0 + MOVOU X0, 16(AX) + + VMOVDQU (DX), Y1 + VPABSD.BCST (BX), K1, Y1 + VMOVDQU Y1, 32(AX) + + VMOVDQU (BX), Y0 + VPSIGND (CX), Y0, Y2 + VMOVDQU Y2, 64(AX) + + VMOVDQU64 (BX), Z0 + VPABSQ.Z Z0, K1, Z1 + VMOVDQU64 Z1, 96(AX) + VZEROUPPER + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: I64, Index: 4, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "packedabssign": { + Name: "packedabssign", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, Frame: frame, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +#include +#include +extern void packedabssign(uint8_t *, const uint8_t *, const uint8_t *, const uint8_t *, uint64_t); +static uint8_t abs8(uint8_t v) { return (v & 0x80) ? (uint8_t)(0-v) : v; } +static int16_t sign16(int16_t value, int16_t control) { + return control > 0 ? value : control < 0 ? (int16_t)(0-(uint16_t)value) : 0; +} +static int32_t sign32(int32_t value, int32_t control) { + return control > 0 ? value : control < 0 ? (int32_t)(0-(uint32_t)value) : 0; +} +static int32_t abs32(int32_t value) { return value < 0 ? (int32_t)(0-(uint32_t)value) : value; } +static int64_t abs64(int64_t value) { return value < 0 ? (int64_t)(0-(uint64_t)value) : value; } +int main(void) { + union { uint8_t b[64]; int16_t w[32]; int32_t d[16]; int64_t q[8]; } source, control, old; + uint8_t out[160]; + for (int i = 0; i < 64; i++) { + source.b[i] = (uint8_t)(i * 29 + 0x80); + control.b[i] = (uint8_t)(i * 17 - 71); + old.b[i] = (uint8_t)(0xf0 - i); + } + control.w[0] = 1; control.w[1] = 0; control.w[2] = -1; control.w[3] = INT16_MIN; + control.d[0] = 1; control.d[1] = 0; control.d[2] = -1; control.d[3] = INT32_MIN; + memset(out, 0xcc, sizeof(out)); + const uint64_t mask = 0xa5; + packedabssign(out, source.b, control.b, old.b, mask); + for (int i = 0; i < 16; i++) if (out[i] != abs8(source.b[i])) return 10+i; + const int16_t *got16 = (const int16_t *)(out+16); + for (int i = 0; i < 8; i++) if (got16[i] != sign16(source.w[i], control.w[i])) return 40+i; + const int32_t *gotAbs32 = (const int32_t *)(out+32); + int32_t broadcast = abs32(source.d[0]); + for (int i = 0; i < 8; i++) { + int32_t want = (mask >> i) & 1 ? broadcast : old.d[i]; + if (gotAbs32[i] != want) return 60+i; + } + const int32_t *gotSign32 = (const int32_t *)(out+64); + for (int i = 0; i < 8; i++) if (gotSign32[i] != sign32(source.d[i], control.d[i])) return 80+i; + const int64_t *gotAbs64 = (const int64_t *)(out+96); + for (int i = 0; i < 8; i++) { + int64_t want = (mask >> i) & 1 ? abs64(source.q[i]) : 0; + if (gotAbs64[i] != want) return 100+i; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_abs_sign", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_accumulator_sign_extend.go b/amd64_lower_accumulator_sign_extend.go new file mode 100644 index 00000000..19f96868 --- /dev/null +++ b/amd64_lower_accumulator_sign_extend.go @@ -0,0 +1,50 @@ +package plan9asm + +import "fmt" + +// lowerAccumulatorSignExtend implements the complete Go 1.27 ynone family +// sharing opcodes 98/99: CBW/CWDE/CDQE extend into AX/EAX/RAX, while +// CWD/CDQ/CQO produce the sign half in DX/EDX/RDX. None of them modify flags. +func (c *amd64Ctx) lowerAccumulatorSignExtend(op Op, ins Instr) (ok bool, terminated bool, err error) { + sourceType := LLVMType("") + targetType := LLVMType("") + destination := AX + extendValue := true + switch op { + case "CBW": + sourceType, targetType = I8, I16 + case "CWDE": + sourceType, targetType = I16, I32 + case "CDQE": + if c.goarch == "386" { + return true, false, fmt.Errorf("386 CDQE is illegal in 32-bit mode: %q", ins.Raw) + } + sourceType, targetType = I32, I64 + case "CWD": + sourceType, targetType, destination, extendValue = I16, I16, DX, false + case "CDQ": + sourceType, targetType, destination, extendValue = I32, I32, DX, false + case "CQO": + if c.goarch == "386" { + return true, false, fmt.Errorf("386 CQO is illegal in 32-bit mode: %q", ins.Raw) + } + sourceType, targetType, destination, extendValue = I64, I64, DX, false + default: + return false, false, nil + } + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s %s takes no operands in Go 1.27's ynone table: %q", c.goarch, op, ins.Raw) + } + value, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, sourceType) + if err != nil { + return true, false, err + } + result := c.newTmp() + if extendValue { + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", result, sourceType, value, targetType) + } else { + bits, _ := amd64IntegerTypeBits(sourceType) + fmt.Fprintf(c.b, " %%%s = ashr %s %s, %d\n", result, sourceType, value, bits-1) + } + return true, false, c.storeRegSized(destination, targetType, "%"+result) +} diff --git a/amd64_lower_accumulator_sign_extend_test.go b/amd64_lower_accumulator_sign_extend_test.go new file mode 100644 index 00000000..1deb194f --- /dev/null +++ b/amd64_lower_accumulator_sign_extend_test.go @@ -0,0 +1,198 @@ +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func x86AccumulatorSignExtendCompleteFormsSource(goarch string) string { + ops := []string{"CBW", "CWDE", "CWD", "CDQ"} + if goarch == "amd64" { + ops = append(ops, "CDQE", "CQO") + } + var source strings.Builder + source.WriteString("TEXT signextendforms(SB),$0-0\n") + for _, op := range ops { + source.WriteString("\t" + op + "\n") + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86AccumulatorSignExtendCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86AccumulatorSignExtendCompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"signextendforms": {Name: "signextendforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sext i8", "sext i16", "ashr i16", "ashr i32"} { + if !strings.Contains(ir, want) { + t.Fatalf("accumulator sign-extension lowering omitted %q:\n%s", want, ir) + } + } + if target.goarch == "amd64" { + for _, want := range []string{"sext i32", "ashr i64"} { + if !strings.Contains(ir, want) { + t.Fatalf("amd64 accumulator sign-extension lowering omitted %q:\n%s", want, ir) + } + } + } + compileLLVMToObject(t, llc, target.triple, "accumulator-sign-extend-"+target.name+".ll", "accumulator-sign-extend-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86AccumulatorSignExtendRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "CBW AX"}, + {goarch: "amd64", instruction: "CWDE $1"}, + {goarch: "amd64", instruction: "CDQ AX, DX"}, + {goarch: "amd64", instruction: "CWD.Z"}, + {goarch: "386", instruction: "CDQE"}, + {goarch: "386", instruction: "CQO"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ynone tables", test.instruction) + } + }) + } +} + +func TestAMD64AccumulatorSignExtendRuntimeSemanticsAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT signextendsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVL $0x7fffffff, R8 + ADDL $1, R8 + STC + + MOVQ $0x1122334455660080, AX + CBW + MOVQ AX, 0(DI) + + MOVQ $0x1122334455667788, DX + MOVW $0x8001, AX + CWD + MOVQ DX, 8(DI) + + MOVQ $0x1122334455668001, AX + CWDE + MOVQ AX, 16(DI) + + MOVL $0x80000001, AX + MOVQ $0x1122334455667788, DX + CDQ + MOVQ DX, 24(DI) + + MOVL $0x80000001, AX + CDQE + MOVQ AX, 32(DI) + + MOVQ $0x8000000000000001, AX + CQO + MOVQ DX, 40(DI) + + SETCS 48(DI) + SETOS 49(DI) + SETEQ 50(DI) + SETMI 51(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "signextendsemantics": { + Name: "signextendsemantics", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void signextendsemantics(uint8_t *); +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + uint8_t out[56] = {0}; + signextendsemantics(out); + if (load64(out+0) != UINT64_C(0x112233445566ff80)) return 10; + if (load64(out+8) != UINT64_C(0x112233445566ffff)) return 11; + if (load64(out+16) != UINT64_C(0x00000000ffff8001)) return 12; + if (load64(out+24) != UINT64_C(0x00000000ffffffff)) return 13; + if (load64(out+32) != UINT64_C(0xffffffff80000001)) return 14; + if (load64(out+40) != UINT64_C(0xffffffffffffffff)) return 15; + if (out[48] != 1 || out[49] != 1 || out[50] != 0 || out[51] != 1) return 16; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "accumulator_sign_extend_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_adc_sbb.go b/amd64_lower_adc_sbb.go new file mode 100644 index 00000000..e0ab355e --- /dev/null +++ b/amd64_lower_adc_sbb.go @@ -0,0 +1,151 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerScalarADCSBB implements every operand row in Go 1.27's yxorb (B) +// and yaddl (W/L/Q) tables for add-with-carry and subtract-with-borrow. +func (c *amd64Ctx) lowerScalarADCSBB(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + add, bits, recognized := amd64ScalarADCSBBProperties(baseOp) + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects source and destination: %q", c.goarch, baseOp, ins.Raw) + } + if err := validateAMD64ScalarAddSubOperands(c.goarch, baseOp, bits, ins.Args[0], ins.Args[1], ins); err != nil { + return true, false, err + } + + source, destination := ins.Args[0], ins.Args[1] + typ := amd64IntegerTypeForBits(bits) + var sourceValue string + if source.Kind == OpImm { + sourceValue = amd64ScalarAddSubImmediate(source.Imm, bits) + } else { + sourceValue, err = c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + } + destinationValue, store, err := c.loadIntDestination(destination, typ) + if err != nil { + return true, false, err + } + + wideType := LLVMType(fmt.Sprintf("i%d", bits*2)) + widen := func(value string) string { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", wide, typ, value, wideType) + return "%" + wide + } + wideDestination := widen(destinationValue) + wideSource := widen(sourceValue) + carry := c.loadFlag(c.flagsCFSlot) + wideCarryName := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %s to %s\n", wideCarryName, carry, wideType) + wideCarry := "%" + wideCarryName + + partial := c.newTmp() + wideResult := c.newTmp() + var carryOut string + if add { + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", partial, wideType, wideDestination, wideSource) + fmt.Fprintf(c.b, " %%%s = add %s %%%s, %s\n", wideResult, wideType, partial, wideCarry) + carryOut = c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ugt %s %%%s, %s\n", carryOut, wideType, wideResult, amd64UnsignedMaximum(bits)) + } else { + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", partial, wideType, wideSource, wideCarry) + fmt.Fprintf(c.b, " %%%s = sub %s %s, %%%s\n", wideResult, wideType, wideDestination, partial) + carryOut = c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult %s %s, %%%s\n", carryOut, wideType, wideDestination, partial) + } + + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", result, wideType, wideResult, typ) + resultValue := "%" + result + if err := store(resultValue); err != nil { + return true, false, err + } + c.setScalarADCSBBFlags(typ, add, destinationValue, sourceValue, resultValue, "%"+carryOut) + return true, false, nil +} + +func amd64ScalarADCSBBProperties(op string) (add bool, bits int, ok bool) { + switch op { + case "ADCB": + return true, 8, true + case "ADCW": + return true, 16, true + case "ADCL": + return true, 32, true + case "ADCQ": + return true, 64, true + case "SBBB": + return false, 8, true + case "SBBW": + return false, 16, true + case "SBBL": + return false, 32, true + case "SBBQ": + return false, 64, true + default: + return false, 0, false + } +} + +func amd64UnsignedMaximum(bits int) string { + switch bits { + case 8: + return "255" + case 16: + return "65535" + case 32: + return "4294967295" + case 64: + return "18446744073709551615" + default: + panic(fmt.Sprintf("unsupported x86 integer width %d", bits)) + } +} + +func (c *amd64Ctx) setScalarADCSBBFlags(typ LLVMType, add bool, destination, source, result, carry string) { + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", carry, c.flagsCFSlot) + + xorOperands := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, %s\n", xorOperands, typ, destination, source) + overflowInput := "%" + xorOperands + if add { + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, -1\n", inverted, typ, overflowInput) + overflowInput = "%" + inverted + } + xorResult := c.newTmp() + overflowBits := c.newTmp() + overflow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, %s\n", xorResult, typ, destination, result) + fmt.Fprintf(c.b, " %%%s = and %s %s, %%%s\n", overflowBits, typ, overflowInput, xorResult) + fmt.Fprintf(c.b, " %%%s = icmp slt %s %%%s, 0\n", overflow, typ, overflowBits) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", overflow, c.flagsOFSlot) + + zero := c.newTmp() + sign := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, 0\n", zero, typ, result) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + fmt.Fprintf(c.b, " %%%s = icmp slt %s %s, 0\n", sign, typ, result) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", sign, c.flagsSltSlot) + c.setParityFlagSized(typ, result) +} diff --git a/amd64_lower_adc_sbb_test.go b/amd64_lower_adc_sbb_test.go new file mode 100644 index 00000000..d2ab819c --- /dev/null +++ b/amd64_lower_adc_sbb_test.go @@ -0,0 +1,173 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86ADCSBBCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT adcsbbforms(SB),NOSPLIT,$32-0\n") + for _, stem := range []string{"ADC", "SBB"} { + for _, width := range []string{"B", "W", "L", "Q"} { + if target.goarch == "386" && width == "Q" { + continue + } + op := stem + width + srcReg, dstReg := "BX", "AX" + if width == "B" { + srcReg, dstReg = "BL", "AL" + } + fmt.Fprintf(&source, "\t%s $1, %s\n", op, dstReg) + fmt.Fprintf(&source, "\t%s %s, %s\n", op, srcReg, dstReg) + fmt.Fprintf(&source, "\t%s 8(BX), %s\n", op, dstReg) + fmt.Fprintf(&source, "\t%s $1, 16(BX)\n", op) + fmt.Fprintf(&source, "\t%s %s, 24(BX)\n", op, srcReg) + if target.goarch == "386" && width != "B" { + fmt.Fprintf(&source, "\t%s $0, SP\n", op) + } + if target.goarch == "amd64" && width == "Q" { + fmt.Fprintf(&source, "\t%s $4294967295, AX\n", op) + } + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"adcsbbforms": {Name: "adcsbbforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "adc-sbb-"+target.name+".ll", "adc-sbb-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86ADCSBBRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + tests := []struct { + goarch string + triple string + instruction string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "ADCB SP, AL"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "SBBB AL, SP"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "ADCQ 0(BX), 8(CX)"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "SBBL X0, AX"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "ADCW.Z AX, BX"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "ADCQ $4294967296, AX"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "ADCQ AX, BX"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "SBBQ $1, 0(BX)"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "ADCL R8, AX"}, + } + for _, test := range tests { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+test.instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: test.triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ADC/SBB tables for %s", test.instruction, test.goarch) + } + }) + } +} + +func TestAMD64ADCSBBMemoryRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT adcsbbmemory(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVQ $0xffffffffffffffff, 0(DI) + CLC + ADCQ $1, 0(DI) + SETCS 32(DI) + SBBQ $0, 0(DI) + SETCS 33(DI) + MOVL $0x7fffffff, 8(DI) + STC + ADCL $0, 8(DI) + SETOS 34(DI) + MOVW $0, 16(DI) + STC + SBBW $0, 16(DI) + SETCS 35(DI) + MOVB $0xff, 24(DI) + CLC + ADCB $1, 24(DI) + SETCS 36(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "adcsbbmemory": {Name: "adcsbbmemory", Args: []LLVMType{Ptr}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +extern void adcsbbmemory(uint8_t *); +int main(void) { + uint8_t out[40] = {0}; + adcsbbmemory(out); + if (*(uint64_t *)(out+0) != UINT64_MAX) return 10; + if (*(uint32_t *)(out+8) != 0x80000000U) return 11; + if (*(uint16_t *)(out+16) != 0xffffU) return 12; + if (out[24] != 0) return 13; + for (int i = 32; i <= 36; i++) if (out[i] != 1) return 20+i; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "adc_sbb_memory", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_addsub.go b/amd64_lower_addsub.go new file mode 100644 index 00000000..d957966c --- /dev/null +++ b/amd64_lower_addsub.go @@ -0,0 +1,191 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerScalarAddSub implements all operand rows in Go 1.27's yxorb (B) and +// yaddl (W/L/Q) tables for ADD and SUB. +func (c *amd64Ctx) lowerScalarAddSub(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + add, bits, recognized := amd64ScalarAddSubProperties(baseOp) + if !recognized { + return false, false, nil + } + if err := validateAMD64ScalarAddSubInstruction(c.goarch, ins); err != nil { + return true, false, err + } + source, destination := ins.Args[0], ins.Args[1] + typ := amd64IntegerTypeForBits(bits) + var sourceValue string + if source.Kind == OpImm { + sourceValue = amd64ScalarAddSubImmediate(source.Imm, bits) + } else { + sourceValue, err = c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + } + destinationValue, store, err := c.loadIntDestination(destination, typ) + if err != nil { + return true, false, err + } + result := c.newTmp() + llvmOp := "sub" + if add { + llvmOp = "add" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", result, llvmOp, typ, destinationValue, sourceValue) + resultValue := "%" + result + if err := store(resultValue); err != nil { + return true, false, err + } + c.setScalarAddSubFlags(typ, add, destinationValue, sourceValue, resultValue) + return true, false, nil +} + +// validateAMD64ScalarAddSubInstruction is deliberately independent of a +// lowering context so the same Go-assembler table is enforced before either +// the direct/linear path or the CFG path is selected. +func validateAMD64ScalarAddSubInstruction(goarch string, ins Instr) error { + rawOp := strings.ToUpper(string(ins.Op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + _, bits, recognized := amd64ScalarAddSubProperties(baseOp) + if !recognized { + return nil + } + if rawOp != baseOp { + return fmt.Errorf("%s %s does not accept instruction suffixes: %q", goarch, baseOp, ins.Raw) + } + if goarch == "386" && bits == 64 { + return fmt.Errorf("386 %s is illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 2 { + return fmt.Errorf("%s %s expects source and destination: %q", goarch, baseOp, ins.Raw) + } + return validateAMD64ScalarAddSubOperands(goarch, baseOp, bits, ins.Args[0], ins.Args[1], ins) +} + +func validateAMD64ScalarAddSubFunction(goarch string, fn Func) error { + for _, ins := range fn.Instrs { + if err := validateAMD64ScalarAddSubInstruction(goarch, ins); err != nil { + return err + } + } + return nil +} + +func amd64ScalarAddSubProperties(op string) (add bool, bits int, ok bool) { + switch op { + case "ADDB": + return true, 8, true + case "ADDW": + return true, 16, true + case "ADDL": + return true, 32, true + case "ADDQ": + return true, 64, true + case "SUBB": + return false, 8, true + case "SUBW": + return false, 16, true + case "SUBL": + return false, 32, true + case "SUBQ": + return false, 64, true + default: + return false, 0, false + } +} + +func validateAMD64ScalarAddSubOperands(goarch, baseOp string, bits int, source, destination Operand, ins Instr) error { + registerAllowed := func(reg Reg) bool { + if bits == 8 { + // Although SP is in the wider general-register class, Go's + // ADD/SUB byte tables do not accept it as a direct byte operand. + return reg != SP && isGoYmbRegisterForArch(reg, goarch) + } + return isX86YrlRegisterForArch(reg, goarch) + } + destinationRegister := destination.Kind == OpReg && registerAllowed(destination.Reg) + destinationMemory := isAMD64MemoryOperand(destination) + if !destinationRegister && !destinationMemory { + return fmt.Errorf("%s %s destination is outside Go 1.27's Ymb/Yml classes: %q", goarch, baseOp, ins.Raw) + } + switch source.Kind { + case OpImm: + if goarch != "386" && (source.Imm < -2147483648 || source.Imm > 4294967295) { + return fmt.Errorf("amd64 %s immediate is outside Go 1.27's Yi32 class: %q", baseOp, ins.Raw) + } + case OpReg: + if !registerAllowed(source.Reg) { + return fmt.Errorf("%s %s source is outside Go 1.27's Yrb/Yrl classes: %q", goarch, baseOp, ins.Raw) + } + default: + if !isAMD64MemoryOperand(source) || !destinationRegister { + return fmt.Errorf("%s %s operands do not match Go 1.27's register/memory rows: %q", goarch, baseOp, ins.Raw) + } + } + return nil +} + +// The assembler emits only the low operand-width bits. Q-width immediates are +// encoded as imm32 and sign-extended by the CPU. +func amd64ScalarAddSubImmediate(immediate int64, bits int) string { + return fmt.Sprintf("%d", amd64ScalarAddSubImmediateInt64(immediate, bits)) +} + +func amd64ScalarAddSubImmediateInt64(immediate int64, bits int) int64 { + var normalized int64 + switch bits { + case 8: + normalized = int64(int8(uint8(immediate))) + case 16: + normalized = int64(int16(uint16(immediate))) + case 32, 64: + normalized = int64(int32(uint32(immediate))) + } + return normalized +} + +func (c *amd64Ctx) setScalarAddSubFlags(typ LLVMType, add bool, destination, source, result string) { + carry := c.newTmp() + if add { + fmt.Fprintf(c.b, " %%%s = icmp ult %s %s, %s\n", carry, typ, result, destination) + } else { + fmt.Fprintf(c.b, " %%%s = icmp ult %s %s, %s\n", carry, typ, destination, source) + } + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carry, c.flagsCFSlot) + + xorOperands := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, %s\n", xorOperands, typ, destination, source) + overflowInput := "%" + xorOperands + if add { + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, -1\n", inverted, typ, overflowInput) + overflowInput = "%" + inverted + } + xorResult := c.newTmp() + overflowBits := c.newTmp() + overflow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, %s\n", xorResult, typ, destination, result) + fmt.Fprintf(c.b, " %%%s = and %s %s, %%%s\n", overflowBits, typ, overflowInput, xorResult) + fmt.Fprintf(c.b, " %%%s = icmp slt %s %%%s, 0\n", overflow, typ, overflowBits) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", overflow, c.flagsOFSlot) + + zero := c.newTmp() + sign := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, 0\n", zero, typ, result) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + fmt.Fprintf(c.b, " %%%s = icmp slt %s %s, 0\n", sign, typ, result) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", sign, c.flagsSltSlot) + c.setParityFlagSized(typ, result) +} diff --git a/amd64_lower_addsub_float.go b/amd64_lower_addsub_float.go new file mode 100644 index 00000000..84919b77 --- /dev/null +++ b/amd64_lower_addsub_float.go @@ -0,0 +1,117 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerAlternatingFloatingAddSubtract implements the complete Go 1.27 yxm +// and _yvaddsubpd families. Even lanes subtract the Plan 9 first source from +// the destination/base source; odd lanes add it. +func (c *amd64Ctx) lowerAlternatingFloatingAddSubtract(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + laneBits := 0 + vector := false + switch baseOp { + case "ADDSUBPS": + laneBits = 32 + case "ADDSUBPD": + laneBits = 64 + case "VADDSUBPS": + laneBits, vector = 32, true + case "VADDSUBPD": + laneBits, vector = 64, true + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed forms in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if vector { + return c.lowerVectorAlternatingFloatingAddSubtract(baseOp, laneBits, ins) + } + return c.lowerLegacyAlternatingFloatingAddSubtract(baseOp, laneBits, ins) +} + +func (c *amd64Ctx) lowerLegacyAlternatingFloatingAddSubtract(baseOp string, laneBits int, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg || !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("%s %s expects X/m128, X using Go 1.27's yxm table: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s source is outside the legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s source must be X or memory: %q", c.goarch, baseOp, ins.Raw) + } + first, err := c.loadHorizontalFloatingOperand(ins.Args[0], 16, laneBits) + if err != nil { + return true, false, err + } + second, err := c.loadHorizontalFloatingOperand(ins.Args[1], 16, laneBits) + if err != nil { + return true, false, err + } + result := c.emitAlternatingFloatingAddSubtract(16, laneBits, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <16 x i8>\n", out, amd64FMA3LLVMType(128/laneBits, laneBits), result) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) +} + +func (c *amd64Ctx) lowerVectorAlternatingFloatingAddSubtract(baseOp string, laneBits int, ins Instr) (bool, bool, error) { + if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects src1, src2, destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(ins.Args[2].Reg) + if byteWidth != 16 && byteWidth != 32 || + !amd64VEXVectorRegister(ins.Args[1], byteWidth) || + !amd64VEXVectorRegister(ins.Args[2], byteWidth) { + return true, false, fmt.Errorf("%s %s second source and destination must be same-width VEX X/Y registers: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !amd64VEXVectorRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + first, err := c.loadHorizontalFloatingOperand(ins.Args[0], byteWidth, laneBits) + if err != nil { + return true, false, err + } + second, err := c.loadHorizontalFloatingOperand(ins.Args[1], byteWidth, laneBits) + if err != nil { + return true, false, err + } + result := c.emitAlternatingFloatingAddSubtract(byteWidth, laneBits, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", out, amd64FMA3LLVMType(byteWidth*8/laneBits, laneBits), result, byteWidth) + return true, false, c.storeVectorBytes(ins.Args[2].Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitAlternatingFloatingAddSubtract(byteWidth, laneBits int, first, second string) string { + lanes := byteWidth * 8 / laneBits + typeName := amd64FMA3LLVMType(lanes, laneBits) + elementType := amd64FMA3LLVMType(1, laneBits) + result := "poison" + for lane := 0; lane < lanes; lane++ { + left := c.newTmp() + right := c.newTmp() + value := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", left, typeName, second, lane) + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", right, typeName, first, lane) + operation := "fsub" + if lane%2 == 1 { + operation = "fadd" + } + fmt.Fprintf(c.b, " %%%s = %s %s %%%s, %%%s\n", value, operation, elementType, left, right) + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, %s %%%s, i32 %d\n", inserted, typeName, result, elementType, value, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_addsub_float_test.go b/amd64_lower_addsub_float_test.go new file mode 100644 index 00000000..dc6c30ad --- /dev/null +++ b/amd64_lower_addsub_float_test.go @@ -0,0 +1,94 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86AlternatingFloatingAddSubtractCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT alternatingfloataddsubforms(SB),NOSPLIT,$0-0\n") + for _, element := range []string{"PS", "PD"} { + op := "ADDSUB" + element + fmt.Fprintf(&src, "\t%s X0, X1\n", op) + fmt.Fprintf(&src, "\t%s (AX), X7\n", op) + vop := "V" + op + fmt.Fprintf(&src, "\t%s X0, X1, X2\n", vop) + fmt.Fprintf(&src, "\t%s (AX), X14, X15\n", vop) + fmt.Fprintf(&src, "\t%s Y0, Y1, Y2\n", vop) + fmt.Fprintf(&src, "\t%s (AX), Y14, Y15\n", vop) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "alternatingfloataddsubforms": {Name: "alternatingfloataddsubforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "alternating-float-addsub-"+target.name+".ll", "alternating-float-addsub-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86AlternatingFloatingAddSubtractRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, op := range []string{"ADDSUBPS", "ADDSUBPD", "VADDSUBPS", "VADDSUBPD"} { + forms := []string{"X0", "Y0, Y1", "X0, X1, X2"} + valid := "X0, X1" + if strings.HasPrefix(op, "V") { + forms = []string{"X0", "X0, X1", "X0, Y1, Y2", "Z0, Z1, Z2", "X0, X1, K1, X2"} + valid = "X0, X1, X2" + } + for _, operands := range forms { + instruction := op + " " + operands + t.Run(strings.NewReplacer(" ", "_", ",", "_").Replace(instruction), func(t *testing.T) { + assertX86AlternatingAddSubRejected(t, instruction) + }) + } + for _, suffix := range []string{".Z", ".BCST", ".SAE", ".RN_SAE"} { + instruction := op + suffix + " " + valid + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + assertX86AlternatingAddSubRejected(t, instruction) + }) + } + } +} + +func assertX86AlternatingAddSubRejected(t *testing.T, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's yxm/_yvaddsubpd tables", instruction) + } +} diff --git a/amd64_lower_addvec.go b/amd64_lower_addvec.go new file mode 100644 index 00000000..c8dfc173 --- /dev/null +++ b/amd64_lower_addvec.go @@ -0,0 +1,307 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedAddMode uint8 + +const ( + amd64PackedAddWrap amd64PackedAddMode = iota + amd64PackedAddSignedSaturating + amd64PackedAddUnsignedSaturating +) + +type amd64PackedAddForm uint8 + +const ( + // amd64PackedAddLegacyYMM is Go's ymm table: MMX/m64 and XMM/m128. + // Go only exposes the MMX rows in amd64 mode. + amd64PackedAddLegacyYMM amd64PackedAddForm = iota + // amd64PackedAddLegacyYXM is Go's yxm table: XMM/m128 only. + amd64PackedAddLegacyYXM + // amd64PackedAddVEXEVEX is Go's _yvandnpd table: X/Y/Z sources, + // optional EVEX masking, and opt-in D/Q memory broadcast. + amd64PackedAddVEXEVEX +) + +type amd64PackedAddSpec struct { + canonical Op + form amd64PackedAddForm + laneBits int + mode amd64PackedAddMode + allowBroadcast bool +} + +// amd64PackedAddSpecs is the complete typed grammar for Go 1.27's packed-add +// instruction family. Keep aliases here rather than duplicating lowering: +// cmd/asm maps PADDD to APADDL, while its VEX spelling remains VPADDD. +var amd64PackedAddSpecs = map[Op]amd64PackedAddSpec{ + "PADDB": {canonical: "PADDB", form: amd64PackedAddLegacyYMM, laneBits: 8, mode: amd64PackedAddWrap}, + "PADDW": {canonical: "PADDW", form: amd64PackedAddLegacyYMM, laneBits: 16, mode: amd64PackedAddWrap}, + "PADDL": {canonical: "PADDL", form: amd64PackedAddLegacyYMM, laneBits: 32, mode: amd64PackedAddWrap}, + "PADDD": {canonical: "PADDL", form: amd64PackedAddLegacyYMM, laneBits: 32, mode: amd64PackedAddWrap}, + "PADDQ": {canonical: "PADDQ", form: amd64PackedAddLegacyYXM, laneBits: 64, mode: amd64PackedAddWrap}, + "PADDSB": {canonical: "PADDSB", form: amd64PackedAddLegacyYMM, laneBits: 8, mode: amd64PackedAddSignedSaturating}, + "PADDSW": {canonical: "PADDSW", form: amd64PackedAddLegacyYMM, laneBits: 16, mode: amd64PackedAddSignedSaturating}, + "PADDUSB": {canonical: "PADDUSB", form: amd64PackedAddLegacyYMM, laneBits: 8, mode: amd64PackedAddUnsignedSaturating}, + "PADDUSW": {canonical: "PADDUSW", form: amd64PackedAddLegacyYMM, laneBits: 16, mode: amd64PackedAddUnsignedSaturating}, + "VPADDB": {canonical: "VPADDB", form: amd64PackedAddVEXEVEX, laneBits: 8, mode: amd64PackedAddWrap}, + "VPADDW": {canonical: "VPADDW", form: amd64PackedAddVEXEVEX, laneBits: 16, mode: amd64PackedAddWrap}, + "VPADDD": {canonical: "VPADDD", form: amd64PackedAddVEXEVEX, laneBits: 32, mode: amd64PackedAddWrap, allowBroadcast: true}, + "VPADDQ": {canonical: "VPADDQ", form: amd64PackedAddVEXEVEX, laneBits: 64, mode: amd64PackedAddWrap, allowBroadcast: true}, + "VPADDSB": {canonical: "VPADDSB", form: amd64PackedAddVEXEVEX, laneBits: 8, mode: amd64PackedAddSignedSaturating}, + "VPADDSW": {canonical: "VPADDSW", form: amd64PackedAddVEXEVEX, laneBits: 16, mode: amd64PackedAddSignedSaturating}, + "VPADDUSB": {canonical: "VPADDUSB", form: amd64PackedAddVEXEVEX, laneBits: 8, mode: amd64PackedAddUnsignedSaturating}, + "VPADDUSW": {canonical: "VPADDUSW", form: amd64PackedAddVEXEVEX, laneBits: 16, mode: amd64PackedAddUnsignedSaturating}, +} + +// lowerPackedIntegerAdd implements the complete Go 1.27 packed-integer add +// family: the legacy ymm/yxm tables and the _yvandnpd VEX/EVEX table. +func (c *amd64Ctx) lowerPackedIntegerAdd(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64PackedAddSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if spec.form != amd64PackedAddVEXEVEX { + if suffix != "" { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + return c.lowerLegacyPackedIntegerAdd(baseOp, spec, ins) + } + return c.lowerVectorPackedIntegerAdd(baseOp, suffix, spec, ins) +} + +func (c *amd64Ctx) lowerLegacyPackedIntegerAdd(baseOp string, spec amd64PackedAddSpec, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects MMX/m64, MMX or X/m128, X: %q", baseOp, ins.Raw) + } + dst := ins.Args[1].Reg + if _, ok := amd64ParseMReg(dst); ok { + if c.goarch == "386" { + return true, false, fmt.Errorf("386 %s MMX forms are illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + if spec.form != amd64PackedAddLegacyYMM { + return true, false, fmt.Errorf("amd64 PADDQ has no MMX form in Go 1.27's yxm table: %q", ins.Raw) + } + firstBits, err := c.loadLegacyMMXPackedSource(ins.Args[0]) + if err != nil { + return true, false, fmt.Errorf("amd64 %s MMX source: %w", baseOp, err) + } + secondBits, err := c.loadReg(dst) + if err != nil { + return true, false, err + } + lanes := 64 / spec.laneBits + first := c.bitcastI64ToIntegerLanes(lanes, spec.laneBits, firstBits) + second := c.bitcastI64ToIntegerLanes(lanes, spec.laneBits, secondBits) + result := c.emitPackedIntegerAdd(lanes, spec.laneBits, first, second, spec.mode) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to i64\n", bits, lanes, spec.laneBits, result) + return true, false, c.storeReg(dst, "%"+bits) + } + if !c.isGoLegacyXReg(dst) { + return true, false, fmt.Errorf("%s %s destination must be an in-range MMX or X register: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg && !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s XMM form requires an in-range X source: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpMem && !x86MemoryRegistersValidForArch(ins.Args[0].Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s source uses an out-of-range address register: %q", c.goarch, baseOp, ins.Raw) + } + firstBytes, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(dst) + if err != nil { + return true, false, err + } + lanes := 128 / spec.laneBits + first := c.bitcastVectorBytesToIntegerLanes(16, lanes, spec.laneBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(16, lanes, spec.laneBits, secondBytes) + result := c.emitPackedIntegerAdd(lanes, spec.laneBits, first, second, spec.mode) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, lanes, spec.laneBits, result) + return true, false, c.storeX(dst, "%"+out) +} + +func (c *amd64Ctx) loadLegacyMMXPackedSource(src Operand) (string, error) { + if src.Kind == OpReg { + if _, ok := amd64ParseMReg(src.Reg); !ok { + return "", fmt.Errorf("expected MMX register or memory, got %s", src.String()) + } + return c.loadReg(src.Reg) + } + if !isAMD64MemoryOperand(src) { + return "", fmt.Errorf("expected MMX register or memory, got %s", src.String()) + } + return c.evalIntSized(src, I64) +} + +func (c *amd64Ctx) bitcastI64ToIntegerLanes(lanes, laneBits int, value string) string { + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to <%d x i%d>\n", cast, value, lanes, laneBits) + return "%" + cast +} + +func (c *amd64Ctx) lowerVectorPackedIntegerAdd(baseOp, suffix string, spec amd64PackedAddSpec, ins Instr) (bool, bool, error) { + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("amd64 %s has a suffix absent from its Go 1.27 optab: %q", baseOp, ins.Raw) + } + if broadcast && !spec.allowBroadcast { + return true, false, fmt.Errorf("amd64 %s does not enable EVEX broadcast: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 %s expects src1, src2, [K mask,] destination: %q", baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects an X, Y, or Z destination: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth == 0 { + return true, false, fmt.Errorf("amd64 %s expects an X, Y, or Z destination: %q", baseOp, ins.Raw) + } + if !amd64VectorRegisterHasWidth(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("amd64 %s second source must match its destination width: %q", baseOp, ins.Raw) + } + if broadcast { + if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory first source: %q", baseOp, ins.Raw) + } + } else if ins.Args[0].Kind == OpReg && !amd64VectorRegisterHasWidth(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("amd64 %s first source must match its destination width: %q", baseOp, ins.Raw) + } + + masked := len(ins.Args) == 4 + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s zeroing requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + var mask string + if masked { + maskArg := ins.Args[2] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, ok := amd64ParseKReg(maskArg.Reg) + if !ok || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + var err error + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + lanes := byteWidth * 8 / spec.laneBits + var first string + var err error + if broadcast { + first, err = c.evalIntSized(ins.Args[0], amd64IntegerTypeForBits(spec.laneBits)) + if err == nil { + first = amd64SplatInteger(c, lanes, spec.laneBits, first) + } + } else { + var firstBytes string + firstBytes, err = c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err == nil { + first = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, firstBytes) + } + } + if err != nil { + return true, false, err + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + second := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, secondBytes) + result := c.emitPackedIntegerAdd(lanes, spec.laneBits, first, second, spec.mode) + if masked { + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPackedIntegerAdd(lanes, laneBits int, first, second string, mode amd64PackedAddMode) string { + vecType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + if mode == amd64PackedAddWrap { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", result, vecType, second, first) + return "%" + result + } + + wideBits := laneBits * 2 + wideType := fmt.Sprintf("<%d x i%d>", lanes, wideBits) + firstWide := c.newTmp() + secondWide := c.newTmp() + extend := "sext" + if mode == amd64PackedAddUnsignedSaturating { + extend = "zext" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", firstWide, extend, vecType, first, wideType) + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", secondWide, extend, vecType, second, wideType) + sum := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %%%s, %%%s\n", sum, wideType, secondWide, firstWide) + + max := int64((uint64(1) << laneBits) - 1) + predicate := "ugt" + if mode == amd64PackedAddSignedSaturating { + max = int64((uint64(1) << (laneBits - 1)) - 1) + predicate = "sgt" + } + above := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %s %s %%%s, %s\n", above, predicate, wideType, sum, llvmSplatSignedInteger(lanes, wideBits, max)) + capped := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %%%s\n", capped, lanes, above, wideType, llvmSplatSignedInteger(lanes, wideBits, max), wideType, sum) + clamped := "%" + capped + if mode == amd64PackedAddSignedSaturating { + min := -int64(uint64(1) << (laneBits - 1)) + below := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt %s %s, %s\n", below, wideType, clamped, llvmSplatSignedInteger(lanes, wideBits, min)) + bounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %s\n", bounded, lanes, below, wideType, llvmSplatSignedInteger(lanes, wideBits, min), wideType, clamped) + clamped = "%" + bounded + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", result, wideType, clamped, vecType) + return "%" + result +} + +func llvmSplatSignedInteger(lanes, bits int, value int64) string { + var b strings.Builder + b.WriteByte('<') + for lane := 0; lane < lanes; lane++ { + if lane != 0 { + b.WriteString(", ") + } + fmt.Fprintf(&b, "i%d %d", bits, value) + } + b.WriteByte('>') + return b.String() +} diff --git a/amd64_lower_adx.go b/amd64_lower_adx.go new file mode 100644 index 00000000..79ed6f9b --- /dev/null +++ b/amd64_lower_adx.go @@ -0,0 +1,68 @@ +package plan9asm + +import "fmt" + +// lowerADX implements ADCXL/Q and ADOXL/Q. All four opcodes use Go 1.27's +// yml_rl row: register/memory source and register destination. ADCX consumes +// and updates CF; ADOX independently consumes and updates OF. +func (c *amd64Ctx) lowerADX(op Op, ins Instr) (ok bool, terminated bool, err error) { + bits := 0 + flagSlot := "" + switch op { + case "ADCXL": + bits, flagSlot = 32, c.flagsCFSlot + case "ADCXQ": + bits, flagSlot = 64, c.flagsCFSlot + case "ADOXL": + bits, flagSlot = 32, c.flagsOFSlot + case "ADOXQ": + bits, flagSlot = 64, c.flagsOFSlot + default: + return false, false, nil + } + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", op, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects register/memory source and register destination: %q", c.goarch, op, ins.Raw) + } + source, destination := ins.Args[0], ins.Args[1] + if source.Kind == OpReg { + if !isX86YrlRegisterForArch(source.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yrl class: %q", c.goarch, op, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + sourceValue, err := c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + destinationValue, err := c.evalIntSized(destination, typ) + if err != nil { + return true, false, err + } + carryIn := c.loadFlag(flagSlot) + carryValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %s to %s\n", carryValue, carryIn, typ) + sum := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", sum, typ, destinationValue, sourceValue) + fmt.Fprintf(c.b, " %%%s = add %s %%%s, %%%s\n", result, typ, sum, carryValue) + carryFromOperands := c.newTmp() + carryFromInput := c.newTmp() + carryOut := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult %s %%%s, %s\n", carryFromOperands, typ, sum, destinationValue) + fmt.Fprintf(c.b, " %%%s = icmp ult %s %%%s, %%%s\n", carryFromInput, typ, result, sum) + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", carryOut, carryFromOperands, carryFromInput) + if err := c.storeRegSized(destination.Reg, typ, "%"+result); err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carryOut, flagSlot) + return true, false, nil +} diff --git a/amd64_lower_adx_test.go b/amd64_lower_adx_test.go new file mode 100644 index 00000000..5d73d5cd --- /dev/null +++ b/amd64_lower_adx_test.go @@ -0,0 +1,222 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86ADXCompleteFormsSource(goarch string) string { + var source strings.Builder + symbol := "adxdata" + size := 8 + if goarch == "386" { + symbol = "adxdata386" + size = 4 + } + fmt.Fprintf(&source, "DATA %s+0(SB)/%d, $1\n", symbol, size) + fmt.Fprintf(&source, "GLOBL %s(SB), $%d\n", symbol, size) + source.WriteString("TEXT adxforms(SB),$0-0\n") + widths := []string{"L"} + if goarch == "amd64" { + widths = append(widths, "Q") + } + for _, stem := range []string{"ADCX", "ADOX"} { + for _, width := range widths { + op := stem + width + fmt.Fprintf(&source, "\t%s AX, BX\n", op) + fmt.Fprintf(&source, "\t%s 8(BX), CX\n", op) + fmt.Fprintf(&source, "\t%s %s(SB), DX\n", op, symbol) + if goarch == "amd64" { + fmt.Fprintf(&source, "\t%s R11, R12\n", op) + } else { + fmt.Fprintf(&source, "\t%s AX, SP\n", op) + } + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86ADXCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86ADXCompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"adxforms": {Name: "adxforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"add i32", "icmp ult i32", `"target-features"="+adx"`} { + if !strings.Contains(ll, want) { + t.Fatalf("ADX lowering omitted %q:\n%s", want, ll) + } + } + if target.goarch == "amd64" && !strings.Contains(ll, "add i64") { + t.Fatalf("ADX Q-width lowering omitted add i64:\n%s", ll) + } + compileLLVMToObject(t, llc, target.triple, "adx-"+target.name+".ll", "adx-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86ADXRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "ADCXQ $1, AX"}, + {goarch: "amd64", instruction: "ADOXL AX, 0(BX)"}, + {goarch: "amd64", instruction: "ADCXL X0, AX"}, + {goarch: "amd64", instruction: "ADOXQ AX, X0"}, + {goarch: "amd64", instruction: "ADCXQ AX"}, + {goarch: "amd64", instruction: "ADOXL.Z AX, BX"}, + {goarch: "386", instruction: "ADCXL R8, AX"}, + {goarch: "386", instruction: "ADOXQ AX, BX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ADX yml_rl table", test.instruction) + } + }) + } +} + +func TestAMD64ADXRuntimeSemanticsAndIndependentFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT adxsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + + // ADCXL consumes CF, updates only CF, and zero-extends its destination. + MOVL $0x7fffffff, R8 + ADDL $1, R8 + STC + MOVL $-1, AX + MOVL $0, BX + ADCXL AX, BX + MOVQ BX, 0(DI) + SETCS 8(DI) + SETOS 9(DI) + SETEQ 10(DI) + SETMI 11(DI) + + // ADOXL consumes OF, updates only OF, and leaves CF untouched. + MOVL $0x7fffffff, R8 + ADDL $1, R8 + STC + MOVL $-1, AX + MOVL $0, BX + ADOXL AX, BX + MOVQ BX, 16(DI) + SETOS 24(DI) + SETCS 25(DI) + SETEQ 26(DI) + SETMI 27(DI) + + // The Q-width memory form uses CF while preserving OF and ZF. + XORQ R8, R8 + STC + MOVQ $-1, 32(DI) + MOVQ $0, BX + ADCXQ 32(DI), BX + MOVQ BX, 40(DI) + SETCS 48(DI) + SETOS 49(DI) + SETEQ 50(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "adxsemantics": { + Name: "adxsemantics", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void adxsemantics(uint8_t *); +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + uint8_t out[56] = {0}; + adxsemantics(out); + if (load64(out + 0) != 0) return 10; + const uint8_t adcx_flags[4] = {1, 1, 0, 1}; + for (int i = 0; i < 4; i++) if (out[8+i] != adcx_flags[i]) return 20+i; + if (load64(out + 16) != 0) return 30; + const uint8_t adox_flags[4] = {1, 1, 0, 1}; + for (int i = 0; i < 4; i++) if (out[24+i] != adox_flags[i]) return 40+i; + if (load64(out + 40) != 0) return 50; + const uint8_t adcxq_flags[3] = {1, 0, 1}; + for (int i = 0; i < 3; i++) if (out[48+i] != adcxq_flags[i]) return 60+i; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "adx_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_aes.go b/amd64_lower_aes.go new file mode 100644 index 00000000..8dee4938 --- /dev/null +++ b/amd64_lower_aes.go @@ -0,0 +1,170 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var amd64AESRoundIntrinsics = map[Op]string{ + "AESENC": "@llvm.x86.aesni.aesenc", + "AESENCLAST": "@llvm.x86.aesni.aesenclast", + "AESDEC": "@llvm.x86.aesni.aesdec", + "AESDECLAST": "@llvm.x86.aesni.aesdeclast", +} + +// lowerAES implements the complete Go 1.27 AES/VAES family. Wide VAES round +// instructions apply the corresponding 128-bit AES operation independently +// to every lane. +func (c *amd64Ctx) lowerAES(rawOp Op, ins Instr) (ok bool, terminated bool, err error) { + raw := strings.ToUpper(string(rawOp)) + parts := strings.Split(raw, ".") + baseOp := Op(parts[0]) + switch baseOp { + case "AESENC", "AESENCLAST", "AESDEC", "AESDECLAST", "AESIMC", "AESKEYGENASSIST", + "VAESENC", "VAESENCLAST", "VAESDEC", "VAESDECLAST", "VAESIMC", "VAESKEYGENASSIST": + // handled below; keep the literal family visible to supported-op extraction + default: + return false, false, nil + } + legacyOp := baseOp + vector := strings.HasPrefix(string(baseOp), "V") + if vector { + legacyOp = Op(strings.TrimPrefix(string(baseOp), "V")) + } + _, round := amd64AESRoundIntrinsics[legacyOp] + if len(parts) != 1 { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes in Go 1.27: %q", baseOp, ins.Raw) + } + + if round { + return c.lowerAESRound(baseOp, legacyOp, vector, ins) + } + if legacyOp == "AESIMC" { + return c.lowerAESInverseMixColumns(baseOp, ins) + } + return c.lowerAESKeygenAssist(baseOp, vector, ins) +} + +func (c *amd64Ctx) lowerAESRound(baseOp, legacyOp Op, vector bool, ins Instr) (bool, bool, error) { + if !vector { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("amd64 %s expects X/m128, X: %q", baseOp, ins.Raw) + } + key, destination := ins.Args[0], ins.Args[1] + if !c.isGoVEXVectorRegister(key, 16, true) || !c.isGoVEXVectorRegister(destination, 16, false) { + return true, false, fmt.Errorf("amd64 %s operands are outside Go 1.27's X/m128, X classes: %q", baseOp, ins.Raw) + } + keyBytes, err := c.loadPackedCompareBytes(key, 16) + if err != nil { + return true, false, err + } + stateBytes, err := c.loadX(destination.Reg) + if err != nil { + return true, false, err + } + result := c.emitAESRound(16, stateBytes, keyBytes, amd64AESRoundIntrinsics[legacyOp]) + return true, false, c.storeX(destination.Reg, result) + } + + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 %s expects X|Y|Z/mem, X|Y|Z, X|Y|Z: %q", baseOp, ins.Raw) + } + key, state, destination := ins.Args[0], ins.Args[1], ins.Args[2] + byteWidth := amd64VectorByteWidth(destination.Reg) + if destination.Kind != OpReg || byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's X/Y/Z classes: %q", baseOp, ins.Raw) + } + if !c.isGoEVEXVectorRegister(state, byteWidth) { + return true, false, fmt.Errorf("amd64 %s state source must match the destination width: %q", baseOp, ins.Raw) + } + if key.Kind == OpReg { + if !c.isGoEVEXVectorRegister(key, byteWidth) { + return true, false, fmt.Errorf("amd64 %s key source must match the destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(key) { + return true, false, fmt.Errorf("amd64 %s key source must be a vector register or memory: %q", baseOp, ins.Raw) + } + keyBytes, err := c.loadPackedCompareBytes(key, byteWidth) + if err != nil { + return true, false, err + } + stateBytes, err := c.loadPackedCompareBytes(state, byteWidth) + if err != nil { + return true, false, err + } + result := c.emitAESRound(byteWidth, stateBytes, keyBytes, amd64AESRoundIntrinsics[legacyOp]) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, result) +} + +func (c *amd64Ctx) lowerAESInverseMixColumns(baseOp Op, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("amd64 %s expects X/m128, X: %q", baseOp, ins.Raw) + } + source, destination := ins.Args[0], ins.Args[1] + if !c.isGoVEXVectorRegister(source, 16, true) || !c.isGoVEXVectorRegister(destination, 16, false) { + return true, false, fmt.Errorf("amd64 %s operands are outside Go 1.27's VEX X/m128, X classes: %q", baseOp, ins.Raw) + } + sourceBytes, err := c.loadPackedCompareBytes(source, 16) + if err != nil { + return true, false, err + } + sourceI64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", sourceI64, sourceBytes) + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %%%s)\n", call, sourceI64) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", result, call) + return true, false, c.storeX(destination.Reg, "%"+result) +} + +func (c *amd64Ctx) lowerAESKeygenAssist(baseOp Op, vector bool, ins Instr) (bool, bool, error) { + validImmediate := len(ins.Args) == 3 && amd64UnsignedImmediate(ins.Args[0], 8) + if vector { + validImmediate = len(ins.Args) == 3 && amd64VectorByteShiftImmediate(ins.Args[0]) + } + if !validImmediate { + return true, false, fmt.Errorf("amd64 %s expects $imm8, X/m128, X: %q", baseOp, ins.Raw) + } + source, destination := ins.Args[1], ins.Args[2] + if !c.isGoVEXVectorRegister(source, 16, true) || !c.isGoVEXVectorRegister(destination, 16, false) { + return true, false, fmt.Errorf("amd64 %s operands are outside Go 1.27's VEX X/m128, X classes: %q", baseOp, ins.Raw) + } + sourceBytes, err := c.loadPackedCompareBytes(source, 16) + if err != nil { + return true, false, err + } + sourceI64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", sourceI64, sourceBytes) + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %%%s, i8 %d)\n", call, sourceI64, uint8(ins.Args[0].Imm)) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", result, call) + return true, false, c.storeX(destination.Reg, "%"+result) +} + +func (c *amd64Ctx) emitAESRound(byteWidth int, stateBytes, keyBytes, intrinsic string) string { + qwords := byteWidth / 8 + state := c.newTmp() + key := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i64>\n", state, byteWidth, stateBytes, qwords) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i64>\n", key, byteWidth, keyBytes, qwords) + result := "zeroinitializer" + for lane := 0; lane < byteWidth/16; lane++ { + laneState := c.newTmp() + laneKey := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i64> %%%s, <%d x i64> poison, <2 x i32> \n", laneState, qwords, state, qwords, lane*2, lane*2+1) + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i64> %%%s, <%d x i64> poison, <2 x i32> \n", laneKey, qwords, key, qwords, lane*2, lane*2+1) + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <2 x i64> %s(<2 x i64> %%%s, <2 x i64> %%%s)\n", call, intrinsic, laneState, laneKey) + for word := 0; word < 2; word++ { + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 %d\n", extracted, call, word) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i64> %s, i64 %%%s, i32 %d\n", inserted, qwords, result, extracted, lane*2+word) + result = "%" + inserted + } + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", bytes, qwords, result, byteWidth) + return "%" + bytes +} diff --git a/amd64_lower_aes_test.go b/amd64_lower_aes_test.go new file mode 100644 index 00000000..8bfdb04b --- /dev/null +++ b/amd64_lower_aes_test.go @@ -0,0 +1,123 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86AESCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast := 15 + zLast := 31 + if target.goarch == "386" { + legacyLast = 7 + zLast = 7 + } + var source strings.Builder + source.WriteString("TEXT aesforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"AESENC", "AESENCLAST", "AESDEC", "AESDECLAST"} { + fmt.Fprintf(&source, "\t%s X0, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, legacyLast) + vop := "V" + op + source.WriteString("\t" + vop + " X0, X1, X2\n") + source.WriteString("\t" + vop + " 16(AX), X1, X2\n") + source.WriteString("\t" + vop + " Y0, Y1, Y2\n") + source.WriteString("\t" + vop + " 32(AX), Y1, Y2\n") + source.WriteString("\t" + vop + " X16, X30, X31\n") + fmt.Fprintf(&source, "\t%s Z0, Z1, Z%d\n", vop, zLast) + } + fmt.Fprintf(&source, "\tAESIMC X0, X%d\n", legacyLast) + fmt.Fprintf(&source, "\tAESIMC 8(AX), X%d\n", legacyLast) + fmt.Fprintf(&source, "\tVAESIMC X0, X%d\n", legacyLast) + fmt.Fprintf(&source, "\tVAESIMC 8(AX), X%d\n", legacyLast) + fmt.Fprintf(&source, "\tAESKEYGENASSIST $0, X0, X%d\n", legacyLast) + fmt.Fprintf(&source, "\tAESKEYGENASSIST $255, 8(AX), X%d\n", legacyLast) + fmt.Fprintf(&source, "\tVAESKEYGENASSIST $-128, X0, X%d\n", legacyLast) + fmt.Fprintf(&source, "\tVAESKEYGENASSIST $255, 8(AX), X%d\n", legacyLast) + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"aesforms": {Name: "aesforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "aes-"+target.name+".ll", "aes-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86AESRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "AESENC Y0, X1", + "AESENC X0, X16", + "AESENC.Z X0, X1", + "AESIMC X0, (AX)", + "AESKEYGENASSIST $-1, X0, X1", + "AESKEYGENASSIST $256, X0, X1", + "VAESENC X0, Y1, Y2", + "VAESENC X0, X1", + "VAESENC X0, X1, K1, X2", + "VAESENC.Z X0, X1, X2", + "VAESENC X0, X1, (AX)", + "VAESIMC Y0, Y1", + "VAESIMC X16, X1", + "VAESKEYGENASSIST $-129, X0, X1", + "VAESKEYGENASSIST $256, X0, X1", + "VAESKEYGENASSIST $1, Y0, Y1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86AESRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "AESENC X8, X0", + "AESIMC X0, X8", + "AESKEYGENASSIST $1, X8, X0", + "VAESIMC X8, X0", + "VAESKEYGENASSIST $1, X0, X8", + "VAESENC Z8, Z0, Z1", + } { + t.Run("386_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86AESRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86AESRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's AES/VAES tables for %s", instruction, goarch) + } +} diff --git a/amd64_lower_align_elements.go b/amd64_lower_align_elements.go new file mode 100644 index 00000000..c59a6caf --- /dev/null +++ b/amd64_lower_align_elements.go @@ -0,0 +1,133 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// amd64VectorAlignSpecs is the complete Go 1.27 VALIGN family. Both opcodes +// use _yvalignd; they differ only in element and broadcast width. +var amd64VectorAlignSpecs = map[Op]int{ + "VALIGND": 32, + "VALIGNQ": 64, +} + +func (c *amd64Ctx) lowerVectorAlign(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits, recognized := amd64VectorAlignSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + // The 386 assembler frontend rejects the required four- and five-operand + // spellings before reaching the shared _yvalignd table. + if c.goarch != "amd64" { + return true, false, fmt.Errorf("%s %s is rejected by Go 1.27's x86 assembler operand limit: %q", c.goarch, baseOp, ins.Raw) + } + + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("amd64 %s has a suffix absent from Go 1.27's EVEX encoding: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 4 && len(ins.Args) != 5 { + return true, false, fmt.Errorf("amd64 %s expects unsigned-imm8, src1, src2, [K mask,] destination: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 5 + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s zeroing requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + if !amd64UnsignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("amd64 %s first operand must be Go 1.27's unsigned-imm8 class: %q", baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s destination must be an X, Y, or Z register: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !amd64EVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's EVEX vector class: %q", baseOp, ins.Raw) + } + if !amd64EVEXVectorRegister(ins.Args[2], byteWidth) { + return true, false, fmt.Errorf("amd64 %s second source must be a same-width EVEX vector register: %q", baseOp, ins.Raw) + } + if broadcast { + if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory first source: %q", baseOp, ins.Raw) + } + } else if ins.Args[1].Kind == OpReg { + if !amd64EVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("amd64 %s first source must match the destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s first source must be a vector register or memory: %q", baseOp, ins.Raw) + } + + mask := "" + if masked { + if !amd64NonzeroKOperand(ins.Args[3]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(ins.Args[3].Reg) + if err != nil { + return true, false, err + } + } + + lanes := byteWidth * 8 / laneBits + var first string + if broadcast { + scalar, loadErr := c.evalIntSized(ins.Args[1], amd64IntegerTypeForBits(laneBits)) + if loadErr != nil { + return true, false, loadErr + } + first = amd64SplatInteger(c, lanes, laneBits, scalar) + } else { + firstBytes, loadErr := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if loadErr != nil { + return true, false, loadErr + } + first = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, firstBytes) + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[2], byteWidth) + if err != nil { + return true, false, err + } + second := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, secondBytes) + result := c.emitVectorAlign(lanes, laneBits, first, second, uint8(ins.Args[0].Imm)) + if masked { + oldBytes, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitVectorAlign(lanes, laneBits int, first, second string, immediate uint8) string { + count := int(immediate) & (lanes - 1) + indices := make([]string, lanes) + for lane := range indices { + indices[lane] = fmt.Sprintf("i32 %d", lane+count) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %s, <%d x i%d> %s, <%d x i32> <%s>\n", + result, lanes, laneBits, first, lanes, laneBits, second, lanes, strings.Join(indices, ", ")) + return "%" + result +} diff --git a/amd64_lower_align_elements_test.go b/amd64_lower_align_elements_test.go new file mode 100644 index 00000000..0978f2e6 --- /dev/null +++ b/amd64_lower_align_elements_test.go @@ -0,0 +1,218 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateAMD64VectorAlignCompleteGo127Forms(t *testing.T) { + // VALIGND/Q share Go 1.27's six-row _yvalignd table: X/Y/Z, + // each with an unmasked and K1-K7 masked row. Their EVEX attributes add + // D/Q scalar broadcast and zeroing. + var source strings.Builder + source.WriteString("TEXT vector_align_forms(SB),$0-0\n") + for _, op := range []string{"VALIGND", "VALIGNQ"} { + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&source, "\t%s $0, %s0, %s1, %s2\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s $255, 8(BX), %s3, %s4\n", op, width, width) + fmt.Fprintf(&source, "\t%s $1, %s5, %s6, K1, %s7\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s.Z $2, 16(BX), %s8, K2, %s9\n", op, width, width) + fmt.Fprintf(&source, "\t%s.BCST $3, 24(BX), %s10, %s11\n", op, width, width) + fmt.Fprintf(&source, "\t%s.BCST.Z $4, 32(BX), %s12, K3, %s13\n", op, width, width) + } + fmt.Fprintf(&source, "\t%s $5, X29, X30, X31\n", op) + fmt.Fprintf(&source, "\t%s $6, Y29, Y30, Y31\n", op) + fmt.Fprintf(&source, "\t%s $7, Z29, Z30, Z31\n", op) + } + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, "amd64", source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "vector_align_forms": {Name: "vector_align_forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "vector-align-"+target.name+".ll", "vector-align-"+target.name+".o", ir) + }) + } +} + +func TestTranslateAMD64VectorAlignRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "VALIGND X0, X1, X2", + "VALIGND $0, X0, X1", + "VALIGNQ $0, X0, X1, X2, X3, X4", + "VALIGND $-1, X0, X1, X2", + "VALIGNQ $256, X0, X1, X2", + "VALIGND AX, X0, X1, X2", + "VALIGND $0, Y0, X1, X2", + "VALIGNQ $0, X0, Y1, X2", + "VALIGND $0, X0, X1, Y2", + "VALIGNQ $0, X0, 8(BX), X2", + "VALIGND $0, X0, X1, 8(BX)", + "VALIGND $0, X0, X1, K0, X2", + "VALIGNQ $0, X0, X1, K8, X2", + "VALIGND.Z $0, X0, X1, X2", + "VALIGNQ.BCST $0, X0, X1, X2", + "VALIGND.BCST.Z $0, 8(BX), X1, X2", + "VALIGNQ.Z.BCST $0, 8(BX), X1, K1, X2", + "VALIGND.SAE $0, X0, X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VALIGND/Q table", instruction) + } + }) + } +} + +func TestTranslate386VectorAlignMatchesGoAssemblerOperandLimit(t *testing.T) { + for _, instruction := range []string{ + "VALIGND $0, X0, X1, X2", + "VALIGNQ $255, 8(BX), Y1, Y2", + "VALIGND.Z $1, Z0, Z1, K1, Z2", + "VALIGNQ.BCST.Z $2, 16(BX), X1, K7, X2", + } { + t.Run(strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "386", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + for _, triple := range []string{"i386-unknown-linux-gnu", "i686-pc-windows-msvc"} { + if _, err := Translate(file, Options{ + Goarch: "386", + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted 386 %q although Go 1.27 rejects its operand count", instruction) + } + } + }) + } +} + +func TestAMD64VectorAlignRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT vectorAlignSemantics(SB),NOSPLIT,$0-40 + MOVQ out+0(FP), AX + MOVQ first+8(FP), BX + MOVQ second+16(FP), CX + MOVQ scalar+24(FP), DX + VMOVDQU32 (BX), X0 + VMOVDQU32 (CX), X1 + VALIGND $1, X0, X1, X2 + VMOVDQU32 X2, 0(AX) + VALIGND $255, X0, X1, X3 + VMOVDQU32 X3, 16(AX) + VALIGNQ $1, X0, X1, X4 + VMOVDQU32 X4, 32(AX) + KMOVQ mask+32(FP), K1 + VMOVDQU32 X0, X5 + VALIGND $1, X0, X1, K1, X5 + VMOVDQU32 X5, 48(AX) + VALIGND.Z $1, X0, X1, K1, X6 + VMOVDQU32 X6, 64(AX) + VALIGND.BCST $1, (DX), X1, X7 + VMOVDQU32 X7, 80(AX) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: I64, Index: 4, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "vectorAlignSemantics": { + Name: "vectorAlignSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, I64}, + Ret: Void, + Frame: frame, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void vectorAlignSemantics(uint32_t *, const uint32_t *, const uint32_t *, const uint32_t *, uint64_t); +int main(void) { + uint32_t first[4] = {10, 11, 12, 13}; + uint32_t second[4] = {20, 21, 22, 23}; + uint32_t scalar = 99; + uint32_t out[24] = {0}; + const uint32_t want[24] = { + 11, 12, 13, 20, + 13, 20, 21, 22, + 12, 13, 20, 21, + 11, 11, 13, 13, + 11, 0, 13, 0, + 99, 99, 99, 20, + }; + vectorAlignSemantics(out, first, second, &scalar, 5); + for (int i = 0; i < 24; i++) if (out[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "vector_align", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_align_right.go b/amd64_lower_align_right.go new file mode 100644 index 00000000..dba8bfd7 --- /dev/null +++ b/amd64_lower_align_right.go @@ -0,0 +1,141 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedAlignRight implements the complete Go 1.27 PALIGNR and +// VPALIGNR tables. Each 128-bit lane is formed from the first Plan 9 source +// as its low half and the second source (or the legacy destination) as its +// high half, then shifted right by the immediate byte count. +func (c *amd64Ctx) lowerPackedAlignRight(rawOp Op, ins Instr) (ok bool, terminated bool, err error) { + raw := strings.ToUpper(string(rawOp)) + parts := strings.Split(raw, ".") + baseOp := Op(parts[0]) + if baseOp != "PALIGNR" && baseOp != "VPALIGNR" { + return false, false, nil + } + if len(parts) > 2 || len(parts) == 2 && parts[1] != "Z" { + return true, false, fmt.Errorf("amd64 %s has a suffix outside Go 1.27's align-right tables: %q", baseOp, ins.Raw) + } + zeroing := len(parts) == 2 + + if baseOp == "PALIGNR" { + if zeroing { + return true, false, fmt.Errorf("amd64 PALIGNR does not accept instruction suffixes: %q", ins.Raw) + } + if len(ins.Args) != 3 || !amd64UnsignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("amd64 PALIGNR expects $imm8, X/m128, X: %q", ins.Raw) + } + source, destination := ins.Args[1], ins.Args[2] + if !c.isGoVEXVectorRegister(destination, 16, false) { + return true, false, fmt.Errorf("amd64 PALIGNR destination is outside Go 1.27's X register class: %q", ins.Raw) + } + if !c.isGoVEXVectorRegister(source, 16, true) { + return true, false, fmt.Errorf("amd64 PALIGNR source is outside Go 1.27's X/m128 class: %q", ins.Raw) + } + low, err := c.loadPackedCompareBytes(source, 16) + if err != nil { + return true, false, err + } + high, err := c.loadX(destination.Reg) + if err != nil { + return true, false, err + } + result := c.emitPackedAlignRightBytes(16, low, high, ins.Args[0].Imm) + return true, false, c.storeX(destination.Reg, result) + } + + // cmd/asm's 386 parser cannot represent VPALIGNR's four- and five- + // operand spellings, even though the shared encoder table is present. + if c.goarch == "386" { + return true, false, fmt.Errorf("386 VPALIGNR is outside Go 1.27's accepted instruction forms: %q", ins.Raw) + } + masked := len(ins.Args) == 5 + if len(ins.Args) != 4 && !masked || !amd64UnsignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("amd64 VPALIGNR expects $imm8, X|Y|Z/mem, X|Y|Z, [K,] X|Y|Z: %q", ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 VPALIGNR.Z requires a writemask: %q", ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + byteWidth := amd64VectorByteWidth(destination.Reg) + if destination.Kind != OpReg || byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 VPALIGNR destination is outside Go 1.27's X/Y/Z register classes: %q", ins.Raw) + } + first, second := ins.Args[1], ins.Args[2] + if first.Kind == OpReg { + if !c.isGoEVEXVectorRegister(first, byteWidth) { + return true, false, fmt.Errorf("amd64 VPALIGNR first source must match its destination width: %q", ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 VPALIGNR first source must be a vector register or memory: %q", ins.Raw) + } + if !c.isGoEVEXVectorRegister(second, byteWidth) { + return true, false, fmt.Errorf("amd64 VPALIGNR second source must match its destination width: %q", ins.Raw) + } + + maskValue := "" + if masked { + mask := ins.Args[3] + maskIndex, validMask := amd64ParseKReg(mask.Reg) + if mask.Kind != OpReg || !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 VPALIGNR masked form requires K1..K7: %q", ins.Raw) + } + maskValue, err = c.loadK(mask.Reg) + if err != nil { + return true, false, err + } + } + low, err := c.loadPackedCompareBytes(first, byteWidth) + if err != nil { + return true, false, err + } + high, err := c.loadPackedCompareBytes(second, byteWidth) + if err != nil { + return true, false, err + } + result := c.emitPackedAlignRightBytes(byteWidth, low, high, ins.Args[0].Imm) + if masked { + old, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + result = amd64ApplyIntegerLaneMask(c, byteWidth, 8, result, old, maskValue, zeroing) + } + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, result) +} + +func amd64UnsignedImmediate(operand Operand, bits int) bool { + if operand.Kind != OpImm || bits <= 0 || bits >= 63 { + return false + } + return operand.Imm >= 0 && operand.Imm < int64(uint64(1)<= 32 { + return "zeroinitializer" + } + result := "zeroinitializer" + for laneBase := 0; laneBase < byteWidth; laneBase += 16 { + for destinationByte := 0; destinationByte < 16; destinationByte++ { + sourceByte := int64(destinationByte) + count + if sourceByte >= 32 { + continue + } + source := low + if sourceByte >= 16 { + source = high + sourceByte -= 16 + } + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i8> %s, i32 %d\n", extracted, byteWidth, source, laneBase+int(sourceByte)) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i8> %s, i8 %%%s, i32 %d\n", inserted, byteWidth, result, extracted, laneBase+destinationByte) + result = "%" + inserted + } + } + return result +} diff --git a/amd64_lower_align_right_test.go b/amd64_lower_align_right_test.go new file mode 100644 index 00000000..c1623dc4 --- /dev/null +++ b/amd64_lower_align_right_test.go @@ -0,0 +1,192 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86PackedAlignRightCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 15 + if target.goarch == "386" { + last = 7 + } + var source strings.Builder + fmt.Fprintf(&source, "TEXT packedalignrightforms(SB),$0-0\n\tPALIGNR $0, X0, X%d\n\tPALIGNR $255, 8(AX), X%d\n", last, last) + if target.goarch == "amd64" { + source.WriteString("\tVPALIGNR $0, X0, X1, X2\n") + source.WriteString("\tVPALIGNR $1, 8(AX), X1, X2\n") + source.WriteString("\tVPALIGNR $2, Y0, Y1, Y2\n") + source.WriteString("\tVPALIGNR $3, 8(AX), Y1, Y2\n") + source.WriteString("\tVPALIGNR $4, Z0, Z1, Z2\n") + source.WriteString("\tVPALIGNR $5, 8(AX), Z1, Z2\n") + source.WriteString("\tVPALIGNR $6, X16, X31, X0\n") + source.WriteString("\tVPALIGNR $7, X16, X31, K1, X0\n") + source.WriteString("\tVPALIGNR.Z $8, 16(AX), Y31, K2, Y0\n") + source.WriteString("\tVPALIGNR $9, Z16, Z31, K3, Z0\n") + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedalignrightforms": {Name: "packedalignrightforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-align-right-"+target.name+".ll", "packed-align-right-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedAlignRightRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PALIGNR $-1, X0, X1", + "PALIGNR $256, X0, X1", + "PALIGNR $1, M0, M1", + "PALIGNR $1, X16, X1", + "PALIGNR $1, Y0, Y1", + "PALIGNR.Z $1, X0, X1", + "PALIGNR $1, X0, (AX)", + "VPALIGNR $-1, X0, X1, X2", + "VPALIGNR $256, X0, X1, X2", + "VPALIGNR $1, X0, Y1, Y2", + "VPALIGNR $1, X0, X1, K0, X2", + "VPALIGNR.Z $1, X0, X1, X2", + "VPALIGNR.BCST $1, X0, X1, X2", + "VPALIGNR $1, X0, (AX), X2", + "VPALIGNR $1, X0, X1, (AX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedAlignRightRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PALIGNR $1, X8, X0", + "PALIGNR $1, X0, X8", + "VPALIGNR $1, X0, X1, X2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedAlignRightRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedAlignRightRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's PALIGNR/VPALIGNR tables for %s", instruction, goarch) + } +} + +func TestAMD64PackedAlignRightRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT alignrightlegacy(SB),NOSPLIT,$0-24 + MOVQ out+0(FP), AX + MOVQ low+8(FP), BX + MOVQ high+16(FP), CX + MOVOU (CX), X0 + PALIGNR $8, (BX), X0 + MOVOU X0, (AX) + RET +TEXT alignrightvector(SB),NOSPLIT,$0-24 + MOVQ out+0(FP), AX + MOVQ low+8(FP), BX + MOVQ high+16(FP), CX + VMOVDQU (BX), Y0 + VMOVDQU (CX), Y1 + VPALIGNR $8, Y0, Y1, Y2 + VMOVDQU Y2, (AX) + VZEROUPPER + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "alignrightlegacy": {Name: "alignrightlegacy", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, Frame: frame}, + "alignrightvector": {Name: "alignrightvector", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +extern void alignrightlegacy(uint8_t *, const uint8_t *, const uint8_t *); +extern void alignrightvector(uint8_t *, const uint8_t *, const uint8_t *); +int main(void) { + uint8_t low[32], high[32], out[32]; + for (int i = 0; i < 32; i++) { low[i] = (uint8_t)i; high[i] = (uint8_t)(100+i); out[i] = 0; } + alignrightlegacy(out, low, high); + for (int i = 0; i < 8; i++) if (out[i] != low[i+8]) return 10+i; + for (int i = 8; i < 16; i++) if (out[i] != high[i-8]) return 30+i; + for (int i = 0; i < 32; i++) out[i] = 0; + alignrightvector(out, low, high); + for (int lane = 0; lane < 2; lane++) { + int base = lane*16; + for (int i = 0; i < 8; i++) if (out[base+i] != low[base+i+8]) return 60+base+i; + for (int i = 8; i < 16; i++) if (out[base+i] != high[base+i-8]) return 100+base+i; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_align_right", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_andn_test.go b/amd64_lower_andn_test.go new file mode 100644 index 00000000..4b953414 --- /dev/null +++ b/amd64_lower_andn_test.go @@ -0,0 +1,267 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestX86RawANDNReportedEncoding(t *testing.T) { + const source = ` +TEXT rawANDN(SB),$0-0 + BYTE $0xc4 + BYTE $0x42 + BYTE $0x38 + BYTE $0xf2 + BYTE $0xe2 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "amd64", triple: "x86_64-apple-darwin"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"rawANDN": {Name: "rawANDN", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, `"target-features"="+bmi"`) { + t.Fatalf("raw ANDN did not infer BMI1 target feature:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "raw-andn.ll", "raw-andn.o", ir) + }) + } +} + +func TestX86ANDNCompleteGo127FormsAcrossTargets(t *testing.T) { + registers386 := []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"} + registersAMD64 := append(append([]string{}, registers386...), "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15") + targets := []struct { + name string + goarch string + triple string + registers []string + }{ + {name: "386-linux", goarch: "386", triple: "i386-unknown-linux-gnu", registers: registers386}, + {name: "386-windows", goarch: "386", triple: "i686-pc-windows-msvc", registers: registers386}, + {name: "amd64-darwin", goarch: "amd64", triple: "x86_64-apple-darwin", registers: registersAMD64}, + {name: "amd64-linux", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", registers: registersAMD64}, + {name: "amd64-windows", goarch: "amd64", triple: "x86_64-pc-windows-msvc", registers: registersAMD64}, + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range targets { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT andnall(SB),$0-0\n") + for _, width := range []string{"L", "Q"} { + for index, first := range target.registers { + second := target.registers[(index+3)%len(target.registers)] + destination := target.registers[(index+5)%len(target.registers)] + fmt.Fprintf(&source, "\tANDN%s %s, %s, %s\n", width, first, second, destination) + } + fmt.Fprintf(&source, "\tANDN%s 8(AX), CX, DX\n", width) + fmt.Fprintf(&source, "\tANDN%s 16(AX)(CX*4), DX, BX\n", width) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"andnall": {Name: "andnall", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, `"target-features"="+bmi"`) { + t.Fatalf("ANDN family did not infer BMI1 target feature:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "andn-family.ll", "andn-family.o", ir) + }) + } +} + +func TestX86RawANDNCompleteRegisterFields(t *testing.T) { + for _, mode := range []int{32, 64} { + registerCount := 8 + if mode == 64 { + registerCount = 16 + } + for _, width64 := range []bool{false, true} { + for first := 0; first < registerCount; first++ { + for second := 0; second < registerCount; second++ { + for destination := 0; destination < registerCount; destination++ { + p0 := byte((^destination>>3)&1)<<7 | 1<<6 | byte((^first>>3)&1)<<5 | 2 + p1 := byte((^second)&15) << 3 + if width64 { + p1 |= 0x80 + } + modRM := byte(0xc0 | destination&7<<3 | first&7) + encoding := []byte{0xc4, p0, p1, 0xf2, modRM} + instruction, length, ok, err := decodedX86ANDNInstruction(encoding, mode) + if !ok || err != nil || length != len(encoding) { + t.Fatalf("mode=%d width64=%v first=%d second=%d destination=%d: ok=%v length=%d err=%v", mode, width64, first, second, destination, ok, length, err) + } + wantOp := Op("ANDNL") + if width64 && mode == 64 { + wantOp = "ANDNQ" + } + wantFirst, _ := decodedX86GeneralRegister(first) + wantSecond, _ := decodedX86GeneralRegister(second) + wantDestination, _ := decodedX86GeneralRegister(destination) + if instruction.Op != wantOp || len(instruction.Args) != 3 || instruction.Args[0].Reg != wantFirst || instruction.Args[1].Reg != wantSecond || instruction.Args[2].Reg != wantDestination { + t.Fatalf("encoding %x decoded as %#v", encoding, instruction) + } + } + } + } + } + } +} + +func TestX86RawANDNMemoryForms(t *testing.T) { + for _, test := range []struct { + name string + encoding []byte + }{ + {name: "direct", encoding: []byte{0xc4, 0xe2, 0x30, 0xf2, 0x13}}, + {name: "extended base", encoding: []byte{0xc4, 0xc2, 0x30, 0xf2, 0x13}}, + {name: "sib disp8", encoding: []byte{0xc4, 0x82, 0x88, 0xf2, 0x54, 0x88, 0x10}}, + {name: "base less", encoding: []byte{0xc4, 0xe2, 0x30, 0xf2, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12}}, + {name: "segment", encoding: []byte{0x64, 0xc4, 0xe2, 0x30, 0xf2, 0x54, 0x48, 0x08}}, + } { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86ANDNInstruction(test.encoding, 64) + if !ok || err != nil || length != len(test.encoding) || len(instruction.Args) != 3 || instruction.Args[0].Kind != OpMem { + t.Fatalf("encoding %x: instruction=%#v ok=%v length=%d err=%v", test.encoding, instruction, ok, length, err) + } + }) + } +} + +func TestX86RawANDNRejectsReservedAndUnsafeForms(t *testing.T) { + for _, test := range []struct { + name string + mode int + encoding []byte + }{ + {name: "vex l", mode: 64, encoding: []byte{0xc4, 0xe2, 0x34, 0xf2, 0xd2}}, + {name: "vex pp", mode: 64, encoding: []byte{0xc4, 0xe2, 0x31, 0xf2, 0xd2}}, + {name: "missing modrm", mode: 64, encoding: []byte{0xc4, 0xe2, 0x30, 0xf2}}, + {name: "address override", mode: 64, encoding: []byte{0x67, 0xc4, 0xe2, 0x30, 0xf2, 0xd2}}, + {name: "rip relative", mode: 64, encoding: []byte{0xc4, 0xe2, 0x30, 0xf2, 0x15, 0, 0, 0, 0}}, + {name: "extended first 386", mode: 32, encoding: []byte{0xc4, 0xc2, 0x70, 0xf2, 0xc0}}, + {name: "extended second 386", mode: 32, encoding: []byte{0xc4, 0xe2, 0x38, 0xf2, 0xc0}}, + {name: "extended destination 386", mode: 32, encoding: []byte{0xc4, 0x62, 0x70, 0xf2, 0xc0}}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86ANDNInstruction(test.encoding, test.mode) + if !ok || err == nil { + t.Fatalf("encoding %x: ok=%v err=%v, want recognized rejection", test.encoding, ok, err) + } + }) + } +} + +func TestX86ANDNRuntimeSemanticsAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT andnsemantics(SB),$0-8 + MOVQ out+0(FP), DI + MOVQ $0xf0, AX + MOVQ $0xcc, BX + ANDNQ AX, BX, CX + MOVQ CX, 0(DI) + SETCS 24(DI) + SETEQ 25(DI) + SETMI 26(DI) + SETOS 27(DI) + MOVQ $0, AX + MOVQ $0, BX + ANDNQ AX, BX, CX + MOVQ CX, 8(DI) + SETCS 28(DI) + SETEQ 29(DI) + SETMI 30(DI) + SETOS 31(DI) + MOVL $0x80000000, AX + MOVL $0, BX + ANDNL AX, BX, CX + MOVQ CX, 16(DI) + SETCS 32(DI) + SETEQ 33(DI) + SETMI 34(DI) + SETOS 35(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "andnsemantics": {Name: "andnsemantics", Args: []LLVMType{Ptr}, Ret: Void, Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}}, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void andnsemantics(uint8_t *); +int main(void) { + uint8_t out[40] = {0}; + andnsemantics(out); + const uint64_t want[3] = {UINT64_C(0x30), 0, UINT64_C(0x80000000)}; + for (int i = 0; i < 3; i++) { + uint64_t got; + memcpy(&got, out + i * 8, sizeof(got)); + if (got != want[i]) return 10 + i; + } + const uint8_t flags[12] = {0,0,0,0, 0,1,0,0, 0,0,1,0}; + for (int i = 0; i < 12; i++) if (out[24+i] != flags[i]) return 30+i; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "andn_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_andnot.go b/amd64_lower_andnot.go new file mode 100644 index 00000000..cd56a68c --- /dev/null +++ b/amd64_lower_andnot.go @@ -0,0 +1,160 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedAndNot implements every Go 1.27 operand form in the packed +// AND-NOT family: PANDN (MMX/XMM), VPANDN (X/Y VEX), and VPANDND/Q +// (X/Y/Z EVEX, including masking, zeroing, and memory broadcast). +func (c *amd64Ctx) lowerPackedAndNot(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + switch baseOp { + case "PANDN": + if suffix != "" { + return true, false, fmt.Errorf("amd64 PANDN does not accept instruction suffixes: %q", ins.Raw) + } + return c.lowerLegacyPackedAndNot(ins) + case "VPANDN": + if suffix != "" { + return true, false, fmt.Errorf("amd64 VPANDN does not accept instruction suffixes: %q", ins.Raw) + } + return c.lowerVEXPackedAndNot(ins) + case "VPANDND", "VPANDNQ": + return c.lowerEVEXPackedLogical(op, ins) + default: + return false, false, nil + } +} + +func (c *amd64Ctx) lowerLegacyPackedAndNot(ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 PANDN expects MMX/m64, MMX or X/m128, X: %q", ins.Raw) + } + dst := ins.Args[1].Reg + if _, ok := amd64ParseMReg(dst); ok { + if c.goarch == "386" { + return true, false, fmt.Errorf("386 PANDN MMX forms are illegal in 32-bit mode: %q", ins.Raw) + } + var src string + var err error + if ins.Args[0].Kind == OpReg { + if _, ok := amd64ParseMReg(ins.Args[0].Reg); !ok { + return true, false, fmt.Errorf("amd64 PANDN MMX form requires an MMX source: %q", ins.Raw) + } + src, err = c.loadReg(ins.Args[0].Reg) + } else if isAMD64MemoryOperand(ins.Args[0]) { + src, err = c.evalIntSized(ins.Args[0], I64) + } else { + return true, false, fmt.Errorf("amd64 PANDN MMX form requires MMX or memory source: %q", ins.Raw) + } + if err != nil { + return true, false, err + } + old, err := c.loadReg(dst) + if err != nil { + return true, false, err + } + inverted := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i64 %s, -1\n", inverted, old) + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, %s\n", result, inverted, src) + return true, false, c.storeReg(dst, "%"+result) + } + if !c.isGoLegacyXReg(dst) { + return true, false, fmt.Errorf("amd64 PANDN destination must be MMX or X: %q", ins.Raw) + } + if ins.Args[0].Kind == OpReg && !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("amd64 PANDN XMM form requires an X source: %q", ins.Raw) + } + if ins.Args[0].Kind == OpMem && !x86MemoryRegistersValidForArch(ins.Args[0].Mem, c.goarch) { + return true, false, fmt.Errorf("%s PANDN source uses an out-of-range address register: %q", c.goarch, ins.Raw) + } + src, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + old, err := c.loadX(dst) + if err != nil { + return true, false, err + } + result := c.emitPackedAndNotBytes(16, src, old) + return true, false, c.storeX(dst, result) +} + +func (c *amd64Ctx) lowerVEXPackedAndNot(ins Instr) (bool, bool, error) { + if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("amd64 VPANDN expects X/m, X, X or Y/m, Y, Y: %q", ins.Raw) + } + dst := ins.Args[2].Reg + byteWidth := amd64VectorByteWidth(dst) + if byteWidth != 16 && byteWidth != 32 { + return true, false, fmt.Errorf("amd64 VPANDN destination must be X or Y: %q", ins.Raw) + } + if !amd64VectorRegisterHasWidth(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("amd64 VPANDN second source must match its destination width: %q", ins.Raw) + } + if ins.Args[0].Kind == OpReg && !amd64VectorRegisterHasWidth(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("amd64 VPANDN first source must match its destination width: %q", ins.Raw) + } + first, err := c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err != nil { + return true, false, err + } + second, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + result := c.emitPackedAndNotBytes(byteWidth, first, second) + return true, false, c.storeVectorBytes(dst, byteWidth, result) +} + +func amd64VectorByteWidth(r Reg) int { + switch { + case isAMD64XReg(r): + return 16 + case isAMD64YReg(r): + return 32 + case isAMD64ZReg(r): + return 64 + default: + return 0 + } +} + +func amd64VectorRegisterHasWidth(op Operand, byteWidth int) bool { + return op.Kind == OpReg && amd64VectorByteWidth(op.Reg) == byteWidth +} + +func (c *amd64Ctx) emitPackedAndNotBytes(byteWidth int, first, second string) string { + inverted := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor <%d x i8> %s, %s\n", inverted, byteWidth, second, llvmAllOnesI8Vec(byteWidth)) + fmt.Fprintf(c.b, " %%%s = and <%d x i8> %%%s, %s\n", result, byteWidth, inverted, first) + return "%" + result +} + +func (c *amd64Ctx) bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits int, value string) string { + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i%d>\n", cast, byteWidth, value, lanes, laneBits) + return "%" + cast +} + +func (c *amd64Ctx) storeVectorBytes(dst Reg, byteWidth int, value string) error { + switch byteWidth { + case 16: + return c.storeX(dst, value) + case 32: + return c.storeY(dst, value) + case 64: + return c.storeZ(dst, value) + default: + return fmt.Errorf("unsupported packed AND-NOT vector width %d", byteWidth) + } +} diff --git a/amd64_lower_approximate_math.go b/amd64_lower_approximate_math.go new file mode 100644 index 00000000..c43391e2 --- /dev/null +++ b/amd64_lower_approximate_math.go @@ -0,0 +1,285 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64ApproximateMathMode uint8 + +const ( + amd64ApproximateExp2 amd64ApproximateMathMode = iota + amd64ApproximateReciprocal28 + amd64ApproximateReciprocalSqrt28 +) + +type amd64ApproximateMathSpec struct { + laneBits int + scalar bool + mode amd64ApproximateMathMode +} + +// amd64ApproximateMathSpecs models the complete AVX512ER family exposed by +// Go 1.27's _yvexp2pd and _yvgetexpsd tables. The type axes describe the +// mathematical operation, lane type, and packed/scalar operand shape; the +// parser below derives every legal mask, zero, broadcast, and SAE form. +var amd64ApproximateMathSpecs = map[Op]amd64ApproximateMathSpec{ + "VEXP2PS": {laneBits: 32, mode: amd64ApproximateExp2}, + "VEXP2PD": {laneBits: 64, mode: amd64ApproximateExp2}, + "VRCP28PS": {laneBits: 32, mode: amd64ApproximateReciprocal28}, + "VRCP28PD": {laneBits: 64, mode: amd64ApproximateReciprocal28}, + "VRCP28SS": {laneBits: 32, scalar: true, mode: amd64ApproximateReciprocal28}, + "VRCP28SD": {laneBits: 64, scalar: true, mode: amd64ApproximateReciprocal28}, + "VRSQRT28PS": {laneBits: 32, mode: amd64ApproximateReciprocalSqrt28}, + "VRSQRT28PD": {laneBits: 64, mode: amd64ApproximateReciprocalSqrt28}, + "VRSQRT28SS": {laneBits: 32, scalar: true, mode: amd64ApproximateReciprocalSqrt28}, + "VRSQRT28SD": {laneBits: 64, scalar: true, mode: amd64ApproximateReciprocalSqrt28}, +} + +type amd64ApproximateMathForm struct { + properties amd64BinaryFloatingSuffix + source Operand + passthrough Operand + destination Operand + mask string +} + +func (c *amd64Ctx) lowerApproximateMath(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64ApproximateMathSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + form, err := c.parseApproximateMathForm(baseOp, suffix, spec, ins) + if err != nil { + return true, false, err + } + if spec.scalar { + return c.lowerScalarApproximateMath(spec, form) + } + return c.lowerPackedApproximateMath(spec, form) +} + +func (c *amd64Ctx) parseApproximateMathForm(baseOp, suffix string, spec amd64ApproximateMathSpec, ins Instr) (amd64ApproximateMathForm, error) { + var form amd64ApproximateMathForm + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix || properties.rounding != "" || spec.scalar && properties.broadcast { + return form, fmt.Errorf("%s %s has a suffix absent from Go 1.27's AVX512ER tables: %q", c.goarch, baseOp, ins.Raw) + } + wantArgs := 2 + if spec.scalar { + wantArgs = 3 + } + if len(ins.Args) != wantArgs && len(ins.Args) != wantArgs+1 { + return form, fmt.Errorf("%s %s has the wrong operand count for its packed/scalar grammar: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == wantArgs+1 + if c.goarch == "386" && spec.scalar && masked { + return form, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return form, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + maskIndex := len(ins.Args) - 2 + if masked && !amd64NonzeroKOperand(ins.Args[maskIndex]) { + return form, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return form, fmt.Errorf("%s %s destination must be a vector register: %q", c.goarch, baseOp, ins.Raw) + } + wantWidth := 64 + if spec.scalar { + wantWidth = 16 + } + if amd64VectorByteWidth(destination.Reg) != wantWidth || !c.isGoEVEXVectorRegister(destination, wantWidth) { + return form, fmt.Errorf("%s %s destination must be an in-range %s register: %q", c.goarch, baseOp, map[bool]string{true: "X", false: "Z"}[spec.scalar], ins.Raw) + } + + source := ins.Args[0] + if properties.broadcast { + if !isAMD64MemoryOperand(source) { + return form, fmt.Errorf("%s %s.BCST requires a scalar memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, wantWidth) { + return form, fmt.Errorf("%s %s source register must match its destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return form, fmt.Errorf("%s %s source must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if properties.sae && source.Kind != OpReg { + return form, fmt.Errorf("%s %s.SAE requires a register source: %q", c.goarch, baseOp, ins.Raw) + } + + passthrough := Operand{} + if spec.scalar { + passthrough = ins.Args[1] + if !c.isGoEVEXVectorRegister(passthrough, 16) { + return form, fmt.Errorf("%s %s scalar passthrough must be an in-range X register: %q", c.goarch, baseOp, ins.Raw) + } + } + mask := "" + if masked { + var err error + mask, err = c.loadK(ins.Args[maskIndex].Reg) + if err != nil { + return form, err + } + } + return amd64ApproximateMathForm{ + properties: properties, source: source, passthrough: passthrough, + destination: destination, mask: mask, + }, nil +} + +func (c *amd64Ctx) lowerPackedApproximateMath(spec amd64ApproximateMathSpec, form amd64ApproximateMathForm) (bool, bool, error) { + lanes := 512 / spec.laneBits + typ := amd64FloatingVectorType(lanes, spec.laneBits) + var source string + if form.properties.broadcast { + scalar, err := c.loadFloatingScalarOperand(form.source, spec.laneBits) + if err != nil { + return true, false, err + } + source = c.splatFloatingScalar(scalar, lanes, spec.laneBits) + } else { + var err error + source, err = c.loadFloatingVectorOperand(form.source, 64, lanes, spec.laneBits) + if err != nil { + return true, false, err + } + } + + result := c.newTmp() + assembly := approximateMathAssembly(spec, form.properties.sae, form.mask != "", form.properties.zeroing) + clobbers := "~{dirflag},~{fpsr},~{flags}" + if form.mask == "" { + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(%s %s)\n", result, typ, assembly, "=v,v,"+clobbers, typ, source) + } else { + merge := "zeroinitializer" + if !form.properties.zeroing { + var err error + merge, err = c.loadFloatingVectorOperand(form.destination, 64, lanes, spec.laneBits) + if err != nil { + return true, false, err + } + } + mask := c.approximateMathMask32(form.mask) + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(%s %s, %s %s, i32 %s)\n", + result, typ, assembly, "=v,0,v,r,~{k1},"+clobbers, typ, merge, typ, source, mask) + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <64 x i8>\n", bytes, typ, result) + return true, false, c.storeVectorBytes(form.destination.Reg, 64, "%"+bytes) +} + +func (c *amd64Ctx) lowerScalarApproximateMath(spec amd64ApproximateMathSpec, form amd64ApproximateMathForm) (bool, bool, error) { + lanes := 128 / spec.laneBits + typ := amd64FloatingVectorType(lanes, spec.laneBits) + var source string + if form.source.Kind == OpReg { + var err error + source, err = c.loadFloatingVectorOperand(form.source, 16, lanes, spec.laneBits) + if err != nil { + return true, false, err + } + } else { + scalar, err := c.loadFloatingScalarOperand(form.source, spec.laneBits) + if err != nil { + return true, false, err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s zeroinitializer, %s %s, i32 0\n", inserted, typ, amd64FloatingScalarType(spec.laneBits), scalar) + source = "%" + inserted + } + passthrough, err := c.loadFloatingVectorOperand(form.passthrough, 16, lanes, spec.laneBits) + if err != nil { + return true, false, err + } + + result := c.newTmp() + assembly := approximateMathAssembly(spec, form.properties.sae, form.mask != "", form.properties.zeroing) + clobbers := "~{dirflag},~{fpsr},~{flags}" + if form.mask == "" { + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(%s %s, %s %s)\n", + result, typ, assembly, "=v,v,v,"+clobbers, typ, source, typ, passthrough) + } else { + merge := "zeroinitializer" + if !form.properties.zeroing { + merge, err = c.loadFloatingVectorOperand(form.destination, 16, lanes, spec.laneBits) + if err != nil { + return true, false, err + } + } + mask := c.approximateMathMask32(form.mask) + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(%s %s, %s %s, %s %s, i32 %s)\n", + result, typ, assembly, "=v,0,v,v,r,~{k1},"+clobbers, + typ, merge, typ, source, typ, passthrough, mask) + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", bytes, typ, result) + return true, false, c.storeVectorBytes(form.destination.Reg, 16, "%"+bytes) +} + +func approximateMathAssembly(spec amd64ApproximateMathSpec, sae, masked, zeroing bool) string { + assembly := "" + if masked { + maskOperand := 3 + if spec.scalar { + maskOperand = 4 + } + assembly = fmt.Sprintf("kmovw ${%d:k}, %%k1; ", maskOperand) + } + assembly += approximateMathMnemonic(spec) + if sae { + assembly += " {sae}," + } + if spec.scalar { + if masked { + assembly += " $2, $3, $0" + } else { + assembly += " $1, $2, $0" + } + } else if masked { + assembly += " $2, $0" + } else { + assembly += " $1, $0" + } + if masked { + assembly += " {%k1}" + if zeroing { + assembly += " {z}" + } + } + return assembly +} + +func approximateMathMnemonic(spec amd64ApproximateMathSpec) string { + stem := map[amd64ApproximateMathMode]string{ + amd64ApproximateExp2: "vexp2", + amd64ApproximateReciprocal28: "vrcp28", + amd64ApproximateReciprocalSqrt28: "vrsqrt28", + }[spec.mode] + if spec.scalar { + if spec.laneBits == 32 { + return stem + "ss" + } + return stem + "sd" + } + if spec.laneBits == 32 { + return stem + "ps" + } + return stem + "pd" +} + +func (c *amd64Ctx) approximateMathMask32(mask string) string { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", truncated, mask) + return "%" + truncated +} diff --git a/amd64_lower_approximate_math_test.go b/amd64_lower_approximate_math_test.go new file mode 100644 index 00000000..472dff95 --- /dev/null +++ b/amd64_lower_approximate_math_test.go @@ -0,0 +1,159 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +type approximateMathTestSpec struct { + op string + laneBits int + scalar bool + mode amd64ApproximateMathMode +} + +func go127ApproximateMathSpecs() []approximateMathTestSpec { + return []approximateMathTestSpec{ + {op: "VEXP2PS", laneBits: 32, mode: amd64ApproximateExp2}, + {op: "VEXP2PD", laneBits: 64, mode: amd64ApproximateExp2}, + {op: "VRCP28PS", laneBits: 32, mode: amd64ApproximateReciprocal28}, + {op: "VRCP28PD", laneBits: 64, mode: amd64ApproximateReciprocal28}, + {op: "VRCP28SS", laneBits: 32, scalar: true, mode: amd64ApproximateReciprocal28}, + {op: "VRCP28SD", laneBits: 64, scalar: true, mode: amd64ApproximateReciprocal28}, + {op: "VRSQRT28PS", laneBits: 32, mode: amd64ApproximateReciprocalSqrt28}, + {op: "VRSQRT28PD", laneBits: 64, mode: amd64ApproximateReciprocalSqrt28}, + {op: "VRSQRT28SS", laneBits: 32, scalar: true, mode: amd64ApproximateReciprocalSqrt28}, + {op: "VRSQRT28SD", laneBits: 64, scalar: true, mode: amd64ApproximateReciprocalSqrt28}, + } +} + +func TestAMD64ApproximateMathGrammarCoversCompleteGoFamily(t *testing.T) { + expected := go127ApproximateMathSpecs() + if len(amd64ApproximateMathSpecs) != len(expected) { + t.Fatalf("approximate-math grammar has %d entries, want %d", len(amd64ApproximateMathSpecs), len(expected)) + } + for _, want := range expected { + got, ok := amd64ApproximateMathSpecs[Op(want.op)] + if !ok { + t.Errorf("approximate-math grammar omitted %s", want.op) + continue + } + if got.laneBits != want.laneBits || got.scalar != want.scalar || got.mode != want.mode { + t.Errorf("approximate-math grammar %s = %+v, want laneBits=%d scalar=%v mode=%d", want.op, got, want.laneBits, want.scalar, want.mode) + } + } +} + +func TestTranslateX86ApproximateMathCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + vectorDestination := 23 + if target.goarch == "386" { + vectorDestination = 7 + } + var source strings.Builder + source.WriteString("TEXT approximatemathforms(SB),$0-0\n") + for index, spec := range go127ApproximateMathSpecs() { + if spec.scalar { + fmt.Fprintf(&source, "\t%s X1, X2, X23\n", spec.op) + fmt.Fprintf(&source, "\t%s %d(AX), X2, X23\n", spec.op, index*8) + fmt.Fprintf(&source, "\t%s.SAE X1, X2, X23\n", spec.op) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s X1, X2, K1, X23\n", spec.op) + fmt.Fprintf(&source, "\t%s.Z %d(AX), X2, K2, X23\n", spec.op, index*8) + fmt.Fprintf(&source, "\t%s.SAE.Z X1, X2, K3, X23\n", spec.op) + } + continue + } + fmt.Fprintf(&source, "\t%s Z1, Z%d\n", spec.op, vectorDestination) + fmt.Fprintf(&source, "\t%s %d(AX), Z%d\n", spec.op, index*8, vectorDestination) + fmt.Fprintf(&source, "\t%s Z1, K1, Z%d\n", spec.op, vectorDestination) + fmt.Fprintf(&source, "\t%s.Z %d(AX), K2, Z%d\n", spec.op, index*8, vectorDestination) + fmt.Fprintf(&source, "\t%s.BCST %d(AX), Z%d\n", spec.op, index*8, vectorDestination) + fmt.Fprintf(&source, "\t%s.BCST.Z %d(AX), K3, Z%d\n", spec.op, index*8, vectorDestination) + fmt.Fprintf(&source, "\t%s.SAE Z1, Z%d\n", spec.op, vectorDestination) + fmt.Fprintf(&source, "\t%s.SAE.Z Z1, K4, Z%d\n", spec.op, vectorDestination) + } + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"approximatemathforms": {Name: "approximatemathforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, mnemonic := range []string{"vexp2ps", "vexp2pd", "vrcp28ps", "vrcp28pd", "vrcp28ss", "vrcp28sd", "vrsqrt28ps", "vrsqrt28pd", "vrsqrt28ss", "vrsqrt28sd"} { + if !strings.Contains(ir, mnemonic) { + t.Fatalf("translation omitted inline %s:\n%s", mnemonic, ir) + } + } + for _, fragment := range []string{"kmovw", "{%k1}", "{sae}", `"target-features"="+avx512f"`} { + if !strings.Contains(ir, fragment) { + t.Fatalf("translation omitted %q:\n%s", fragment, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "approximate-math-"+target.name+".ll", "approximate-math-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86ApproximateMathRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VEXP2PS X0, X1"}, + {goarch: "amd64", instruction: "VEXP2PD Y0, Y1"}, + {goarch: "amd64", instruction: "VRCP28PS Z0, K0, Z1"}, + {goarch: "amd64", instruction: "VRSQRT28PD.Z Z0, Z1"}, + {goarch: "amd64", instruction: "VEXP2PS.BCST Z0, Z1"}, + {goarch: "amd64", instruction: "VRCP28PD.SAE 0(AX), Z1"}, + {goarch: "amd64", instruction: "VRCP28SS X0, X1"}, + {goarch: "amd64", instruction: "VRSQRT28SD Y0, X1, X2"}, + {goarch: "amd64", instruction: "VRCP28SS.BCST 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VRSQRT28SD.SAE 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VEXP2PS.RN_SAE Z0, Z1"}, + {goarch: "386", instruction: "VEXP2PS Z0, Z8"}, + {goarch: "386", instruction: "VRCP28SS X0, X1, K1, X2"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's approximate-math tables", test.instruction) + } + }) + } +} diff --git a/amd64_lower_arith.go b/amd64_lower_arith.go index 2a25025c..eb7540cd 100644 --- a/amd64_lower_arith.go +++ b/amd64_lower_arith.go @@ -24,6 +24,17 @@ func (c *amd64Ctx) loadIntDestination(dst Operand, ty LLVMType) (string, func(st fmt.Fprintf(c.b, " store %s %s, %s %s, align 1\n", ty, out, ptrType, p) return nil }, nil + case OpFP: + value, err := c.evalFPToI64(dst.FPOffset) + if err != nil { + return "", nil, err + } + if ty != I64 { + value = c.truncI64(value, ty) + } + return value, func(out string) error { + return c.storeFPResult(dst.FPOffset, ty, out) + }, nil case OpSym: p, err := c.ptrFromSB(dst.Sym) if err != nil { @@ -48,6 +59,7 @@ type x86FlagSlot struct { func (c *amd64Ctx) x86FlagSlots() []x86FlagSlot { flags := []x86FlagSlot{ {c.flagsCFSlot, 0}, + {c.flagsPFSlot, 2}, {c.flagsZSlot, 6}, {c.flagsSltSlot, 7}, } @@ -100,68 +112,100 @@ func (c *amd64Ctx) truncI64(v string, ty LLVMType) string { return "%" + t } -func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err error) { - switch op { - case "PUSHL": - if c.goarch != "386" { - return true, false, fmt.Errorf("amd64 PUSHL requires GOARCH=386") - } - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("amd64 PUSHL expects src: %q", ins.Raw) - } - v32, err := c.evalIntSized(ins.Args[0], I32) - if err != nil { - return true, false, err - } - return true, false, c.pushI32(v32) - case "POPL": - if c.goarch != "386" { - return true, false, fmt.Errorf("amd64 POPL requires GOARCH=386") - } - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("amd64 POPL expects dst: %q", ins.Raw) - } - v32, err := c.popI32() - if err != nil { - return true, false, err - } - switch ins.Args[0].Kind { - case OpReg: - return true, false, c.storeRegSized(ins.Args[0].Reg, I32, v32) - case OpMem: - p, ptrType, err := c.ptrFromMem(ins.Args[0].Mem) - if err != nil { - return true, false, err - } - fmt.Fprintf(c.b, " store i32 %s, %s %s, align 1\n", v32, ptrType, p) - return true, false, nil +func isGoYmbRegisterForArch(r Reg, goarch string) bool { + if goarch == "386" { + // Go classifies SP/BP/SI/DI as Yrl32 in 386 mode, so they do not + // directly cover Ymb. Its assembler nevertheless accepts BP/SI/DI + // and synthesizes an equivalent sequence through BX; only a direct + // SP spelling remains invalid. + switch r { + case AX, BX, CX, DX, BP, SI, DI, AL, AH, BL, BH, CL, CH, DL, DH: + return true default: - return true, false, fmt.Errorf("amd64 POPL expects reg/mem dst: %q", ins.Raw) - } - case "PUSHFL": - if c.goarch != "386" { - return true, false, fmt.Errorf("amd64 PUSHFL requires GOARCH=386") + return false } - if len(ins.Args) != 0 { - return true, false, fmt.Errorf("amd64 PUSHFL takes no operands: %q", ins.Raw) - } - flags := c.truncI64(c.packX86Flags(), I32) - return true, false, c.pushI32(flags) - case "POPFL": - if c.goarch != "386" { - return true, false, fmt.Errorf("amd64 POPFL requires GOARCH=386") - } - if len(ins.Args) != 0 { - return true, false, fmt.Errorf("amd64 POPFL takes no operands: %q", ins.Raw) - } - flags32, err := c.popI32() - if err != nil { - return true, false, err + } + if isX86YrlRegisterForArch(r, goarch) { + return true + } + switch r { + case AL, AH, BL, BH, CL, CH, DL, DH, + BPB, SIB, DIB, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B: + return true + default: + return false + } +} + +// amd64YmbEffectiveRegister mirrors the raw ModRM numbering used when Go's +// broad Ymb table accepts a byte-register spelling for a wider NEG/NOT opcode. +func amd64YmbEffectiveRegister(r Reg, bits int) Reg { + if bits == 8 { + return r + } + switch r { + case AL: + return AX + case CL: + return CX + case DL: + return DX + case BL: + return BX + case AH: + return SP + case CH: + return BP + case DH: + return SI + case BH: + return DI + default: + if base, _, ok := amd64ByteAlias(r); ok { + return base } - flags64 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", flags64, flags32) - c.unpackX86Flags("%" + flags64) - return true, false, nil + return r + } +} + +func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err error) { + if ok, terminated, err := c.lowerStackWidth(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerAccumulatorSignExtend(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerBZHI(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerBEXTR(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerADX(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerLeadingZeroCount(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerBMI2VariableShift(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerScalarUnaryYmb(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerLowestSetBitManipulation(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerHardwareRandom(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerScalarADCSBB(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerScalarMultiplyDivide(op, ins); ok { + return ok, terminated, err + } + switch op { case "PUSHAL": if c.goarch != "386" { return true, false, fmt.Errorf("amd64 PUSHAL requires GOARCH=386") @@ -223,43 +267,21 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e } } return true, false, nil - case "PUSHQ": - // Stack-manipulation appears in syscall asm stubs (e.g. preserve return - // address register around SYSCALL). Lower to the local virtual stack. - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("amd64 PUSHQ expects src: %q", ins.Raw) - } - v, err := c.evalI64(ins.Args[0]) - if err != nil { - return true, false, err - } - c.pushI64(v) - return true, false, nil - case "POPQ": - if len(ins.Args) != 1 || ins.Args[0].Kind != OpReg { - return true, false, fmt.Errorf("amd64 POPQ expects dstReg: %q", ins.Raw) - } - v := c.popI64() - if err := c.storeReg(ins.Args[0].Reg, v); err != nil { - return true, false, err - } - return true, false, nil - case "PUSHFQ": - // Keep the historical amd64 stack-shape model. The 32-bit PUSHFL path - // above carries flags because 386 runtime asm consumes them. - c.pushI64("0") - return true, false, nil - case "POPFQ": - _ = c.popI64() - return true, false, nil case "LFENCE", "MFENCE", "SFENCE", "PAUSE": if c.goarch == "386" { fmt.Fprintf(c.b, " call void asm sideeffect %q, %q()\n", strings.ToLower(string(op)), "~{memory}") } return true, false, nil - case "PREFETCHNTA", "EMMS": - // Prefetch does not change SSA-visible values. MMX registers are modeled - // as ordinary integers, so there is no hardware x87 tag state to clear. + case "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2": + // Go 1.27's shared yprefetch table has exactly one memory operand for + // each locality hint. The hint has no SSA-visible result. + if len(ins.Args) != 1 || !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s expects one memory operand: %q", c.goarch, op, ins.Raw) + } + return true, false, nil + case "EMMS": + // MMX registers are modeled as ordinary integers, so there is no + // hardware x87 tag state to clear. return true, false, nil case "UNDEF": if c.goarch == "386" { @@ -282,6 +304,16 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e return true, false, err } return true, false, nil + case "RDPID": + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 1 || ins.Args[0].Kind != OpReg || !isAMD64YrlRegister(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s RDPID expects one general register with no suffix: %q", c.goarch, ins.Raw) + } + if c.goarch == "386" && amd64IsExtendedGPRegister(ins.Args[0].Reg) { + return true, false, fmt.Errorf("386 RDPID destination is outside the 386 register file: %q", ins.Raw) + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.x86.rdpid()\n", value) + return true, false, c.storeRegSized(ins.Args[0].Reg, I32, "%"+value) case OpCPUID: eax64, err := c.loadReg(AX) if err != nil { @@ -424,82 +456,6 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e return true, false, err } return true, false, nil - case "NEGL": - // 32-bit negate with x86 semantics: write back low 32 bits and zero-extend. - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("amd64 NEGL expects dst: %q", ins.Raw) - } - switch ins.Args[0].Kind { - case OpReg: - dv, err := c.loadReg(ins.Args[0].Reg) - if err != nil { - return true, false, err - } - t32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", t32, dv) - neg := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sub i32 0, %%%s\n", neg, t32) - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ne i32 %%%s, 0\n", cf, t32) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCFSlot) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, neg) - if err := c.storeReg(ins.Args[0].Reg, "%"+z); err != nil { - return true, false, err - } - c.setZSFlagsFromI32("%" + neg) - return true, false, nil - case OpMem: - addr, err := c.addrFromMem(ins.Args[0].Mem) - if err != nil { - return true, false, err - } - p := c.ptrFromAddrI64(addr) - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i32, ptr %s, align 1\n", ld, p) - neg := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sub i32 0, %%%s\n", neg, ld) - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ne i32 %%%s, 0\n", cf, ld) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCFSlot) - fmt.Fprintf(c.b, " store i32 %%%s, ptr %s, align 1\n", neg, p) - c.setZSFlagsFromI32("%" + neg) - return true, false, nil - default: - return true, false, fmt.Errorf("amd64 NEGL expects reg/mem dst: %q", ins.Raw) - } - case "RCRQ": - // Rotate through carry right (count=1) used by runtime time division path. - if len(ins.Args) != 2 || ins.Args[0].Kind != OpImm { - return true, false, fmt.Errorf("amd64 RCRQ expects $count, dstReg: %q", ins.Raw) - } - if ins.Args[0].Imm != 1 || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 RCRQ currently supports $1, reg: %q", ins.Raw) - } - dv, err := c.loadReg(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - oldCF := c.loadFlag(c.flagsCFSlot) - lsb := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %s, 1\n", lsb, dv) - newCF := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ne i64 %%%s, 0\n", newCF, lsb) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", newCF, c.flagsCFSlot) - shr := c.newTmp() - fmt.Fprintf(c.b, " %%%s = lshr i64 %s, 1\n", shr, dv) - cf64 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i1 %s to i64\n", cf64, oldCF) - cfhi := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shl i64 %%%s, 63\n", cfhi, cf64) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", out, shr, cfhi) - if err := c.storeReg(ins.Args[1].Reg, "%"+out); err != nil { - return true, false, err - } - c.setZSFlagsFromI64("%" + out) - return true, false, nil - case "ADDQ", "SUBQ", "XORQ", "ANDQ", "ORQ": if len(ins.Args) != 2 { return true, false, fmt.Errorf("amd64 %s expects src, dst: %q", op, ins.Raw) @@ -566,7 +522,24 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e default: fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsCFSlot) } - fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + if op == "ADDQ" || op == "SUBQ" { + xorOperands := c.newTmp() + xorResult := c.newTmp() + overflowBits := c.newTmp() + overflow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i64 %s, %s\n", xorOperands, dv, src) + if op == "ADDQ" { + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i64 %%%s, -1\n", inverted, xorOperands) + xorOperands = inverted + } + fmt.Fprintf(c.b, " %%%s = xor i64 %s, %s\n", xorResult, dv, r) + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, %%%s\n", overflowBits, xorOperands, xorResult) + fmt.Fprintf(c.b, " %%%s = icmp slt i64 %%%s, 0\n", overflow, overflowBits) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", overflow, c.flagsOFSlot) + } else { + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + } c.setZSFlagsFromI64(r) return true, false, nil @@ -759,53 +732,6 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", sf, c.flagsSltSlot) return true, false, nil - case "ADCXQ", "ADOXQ": - // BMI2 add-with-carry chains. - if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects src, dstReg: %q", op, ins.Raw) - } - src, err := c.evalI64(ins.Args[0]) - if err != nil { - return true, false, err - } - dst := ins.Args[1].Reg - dv, err := c.loadReg(dst) - if err != nil { - return true, false, err - } - carryIn := c.loadFlag(c.flagsCFSlot) - flagOut := c.flagsCFSlot - if op == "ADOXQ" { - carryIn = c.loadFlag(c.flagsOFSlot) - flagOut = c.flagsOFSlot - } - cf64t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i1 %s to i64\n", cf64t, carryIn) - cf64 := "%" + cf64t - sum := c.newTmp() - fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", sum, dv, src) - res := c.newTmp() - fmt.Fprintf(c.b, " %%%s = add i64 %%%s, %s\n", res, sum, cf64) - out := "%" + res - if err := c.storeReg(dst, out); err != nil { - return true, false, err - } - dv128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i64 %s to i128\n", dv128, dv) - src128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i64 %s to i128\n", src128, src) - cf128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i64 %s to i128\n", cf128, cf64) - total1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = add i128 %%%s, %%%s\n", total1, dv128, src128) - total2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = add i128 %%%s, %%%s\n", total2, total1, cf128) - carry := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ugt i128 %%%s, 18446744073709551615\n", carry, total2) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carry, flagOut) - // ADCX/ADOX do not define ZF/SF in the same way as ADD; keep current bits. - return true, false, nil - case "ADDL", "SUBL", "XORL", "ANDL", "ORL": // 32-bit arithmetic/logical ops: src, dst. if len(ins.Args) != 2 { @@ -1007,6 +933,12 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e fmt.Fprintf(c.b, " store i64 %s, ptr %s, align 1\n", out, p) return nil } + case OpFP: + var err error + v, storeDst, err = c.loadIntDestination(ins.Args[0], I64) + if err != nil { + return true, false, err + } default: return true, false, fmt.Errorf("amd64 %s expects reg/mem dst: %q", op, ins.Raw) } @@ -1055,11 +987,17 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e fmt.Fprintf(c.b, " store i32 %s, ptr %s, align 1\n", out32, p) return nil } + case OpFP: + var err error + v64, storeDst, err = c.loadIntDestination(ins.Args[0], I32) + if err != nil { + return true, false, err + } default: return true, false, fmt.Errorf("amd64 %s expects reg/mem dst: %q", op, ins.Raw) } tr := c.newTmp() - if ins.Args[0].Kind == OpMem { + if ins.Args[0].Kind == OpMem || ins.Args[0].Kind == OpFP { fmt.Fprintf(c.b, " %%%s = add i32 0, %s\n", tr, v64) } else { fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", tr, v64) @@ -1076,24 +1014,35 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e c.setZSFlagsFromI32("%" + x) return true, false, nil - case "LEAQ", "LEAL": - // LEA{Q,L} srcAddr, dstReg - if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects srcAddr, dstReg: %q", op, ins.Raw) + case "LEAW", "LEAL", "LEAQ": + // All three widths use Go 1.27's sole ym_rl row: an addressable + // memory expression and an in-range general-register destination. + if op == "LEAQ" && c.goarch == "386" { + return true, false, fmt.Errorf("386 LEAQ is illegal in 32-bit mode: %q", ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg || !isX86YrlRegisterForArch(ins.Args[1].Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s expects Ym address and Yrl destination: %q", c.goarch, op, ins.Raw) } dst := ins.Args[1].Reg storeLEA := func(addr string) error { - if op == "LEAL" { + switch op { + case "LEAW": + t := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i16\n", t, addr) + return c.storeRegSized(dst, I16, "%"+t) + case "LEAL": t := c.newTmp() fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", t, addr) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, t) - return c.storeReg(dst, "%"+z) + return c.storeRegSized(dst, I32, "%"+t) + default: + return c.storeRegSized(dst, I64, addr) } - return c.storeReg(dst, addr) } switch ins.Args[0].Kind { case OpMem: + if !x86MemoryRegistersValidForArch(ins.Args[0].Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s source uses an out-of-range address register: %q", c.goarch, op, ins.Raw) + } addr, err := c.addrFromMem(ins.Args[0].Mem) if err != nil { return true, false, err @@ -1152,74 +1101,95 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e return true, false, fmt.Errorf("amd64 %s unsupported src: %q", op, ins.Raw) } - case "POPCNTL", "POPCNTQ": - // POPCNT{L,Q} src, dstReg accepts the same register-or-memory source - // family as the Go x86 assembler. + case "POPCNTW", "POPCNTL", "POPCNTQ": + // All three widths use Go 1.27's yml_rl table: a Yml GP-or-memory + // source and a Yrl GP destination. POPCNTQ requires 64-bit mode. if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { return true, false, fmt.Errorf("amd64 %s expects src, dstReg: %q", op, ins.Raw) } + if op == "POPCNTQ" && c.goarch != "amd64" { + return true, false, fmt.Errorf("amd64 %s requires GOARCH=amd64: %q", op, ins.Raw) + } validFullReg := func(r Reg) bool { - if _, _, ok := amd64ByteAlias(r); ok || r == FS || r == GS { - return false - } - _, ok := amd64FullRegBase(r) - return ok + return isX86YrlRegisterForArch(r, c.goarch) } if !validFullReg(ins.Args[1].Reg) { - return false, false, nil + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's Yrl class: %q", op, ins.Raw) } src := ins.Args[0] switch src.Kind { case OpReg: if !validFullReg(src.Reg) { - return false, false, nil - } - case OpMem, OpFP: - case OpSym: - if strings.HasPrefix(strings.TrimSpace(src.Sym), "$") { - return false, false, nil + return true, false, fmt.Errorf("amd64 %s source is outside Go 1.27's Yml class: %q", op, ins.Raw) } + case OpMem, OpFP, OpSym: default: - return false, false, nil + return true, false, fmt.Errorf("amd64 %s source is outside Go 1.27's Yml class: %q", op, ins.Raw) } - if op == "POPCNTL" { - srcv, err := c.evalIntSized(src, I32) - if err != nil { - return true, false, err - } - call := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i32 @llvm.ctpop.i32(i32 %s)\n", call, srcv) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, call) - return true, false, c.storeReg(ins.Args[1].Reg, "%"+z) + bits := 64 + typ := I64 + switch op { + case "POPCNTW": + bits, typ = 16, I16 + case "POPCNTL": + bits, typ = 32, I32 } - srcv, err := c.evalIntSized(src, I64) + srcv, err := c.evalIntSized(src, typ) if err != nil { return true, false, err } call := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i64 @llvm.ctpop.i64(i64 %s)\n", call, srcv) - return true, false, c.storeReg(ins.Args[1].Reg, "%"+call) + fmt.Fprintf(c.b, " %%%s = call i%d @llvm.ctpop.i%d(i%d %s)\n", call, bits, bits, bits, srcv) + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %s, 0\n", zero, bits, srcv) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsSltSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsPFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + return true, false, c.storeRegSized(ins.Args[1].Reg, typ, "%"+call) - case "TZCNTQ": - // TZCNTQ srcReg, dstReg. - if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 TZCNTQ expects srcReg, dstReg: %q", ins.Raw) + case "TZCNTW", "TZCNTL", "TZCNTQ": + // All widths share Go 1.27's ycrc32l table: Yml source and Yrl + // destination. TZCNTQ requires 64-bit mode. + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects src, dstReg: %q", op, ins.Raw) } - srcv, err := c.loadReg(ins.Args[0].Reg) - if err != nil { - return true, false, err + if op == "TZCNTQ" && c.goarch != "amd64" { + return true, false, fmt.Errorf("amd64 TZCNTQ requires GOARCH=amd64: %q", ins.Raw) } - call := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i64 @llvm.cttz.i64(i64 %s, i1 false)\n", call, srcv) - if err := c.storeReg(ins.Args[1].Reg, "%"+call); err != nil { + if !isX86YrlRegisterForArch(ins.Args[1].Reg, c.goarch) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's Yrl class: %q", op, ins.Raw) + } + source := ins.Args[0] + if source.Kind == OpReg { + if !isX86YrlRegisterForArch(source.Reg, c.goarch) { + return true, false, fmt.Errorf("amd64 %s source is outside Go 1.27's Yml class: %q", op, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s source is outside Go 1.27's Yml class: %q", op, ins.Raw) + } + bits := 64 + typ := I64 + switch op { + case "TZCNTW": + bits, typ = 16, I16 + case "TZCNTL": + bits, typ = 32, I32 + } + sourceValue, err := c.evalIntSized(source, typ) + if err != nil { return true, false, err } - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp eq i64 %s, 0\n", cf, srcv) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCFSlot) - c.setZSFlagsFromI64("%" + call) - return true, false, nil + count := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i%d @llvm.cttz.i%d(i%d %s, i1 false)\n", count, bits, bits, bits, sourceValue) + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %s, 0\n", carry, bits, sourceValue) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carry, c.flagsCFSlot) + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", zero, bits, count) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + return true, false, c.storeRegSized(ins.Args[1].Reg, typ, "%"+count) case "BSFW", "BSRW": if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { @@ -1344,34 +1314,20 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e cond := "" switch op { case "SETEQ": - cond = c.loadFlag(c.flagsZSlot) + cond, err = c.x86Condition("EQ") case "SETLT": - cond = c.loadFlag(c.flagsSltSlot) + cond, err = c.x86Condition("LT") case "SETGT": - // signed > - slt := c.loadFlag(c.flagsSltSlot) - z := c.loadFlag(c.flagsZSlot) - t1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i1 %s, %s\n", t1, slt, z) - t2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", t2, t1) - cond = "%" + t2 + cond, err = c.x86Condition("GT") case "SETGE": - slt := c.loadFlag(c.flagsSltSlot) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", t, slt) - cond = "%" + t + cond, err = c.x86Condition("GE") case "SETHI": - // unsigned > - cf := c.loadFlag(c.flagsCFSlot) - z := c.loadFlag(c.flagsZSlot) - t1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i1 %s, %s\n", t1, cf, z) - t2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", t2, t1) - cond = "%" + t2 + cond, err = c.x86Condition("HI") case "SETCS": - cond = c.loadFlag(c.flagsCFSlot) + cond, err = c.x86Condition("CS") + } + if err != nil { + return true, false, err } switch ins.Args[0].Kind { case OpReg: @@ -1393,17 +1349,23 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e return true, false, fmt.Errorf("amd64 %s expects reg, mem, or fp destination: %q", op, ins.Raw) } - case "CMOVQEQ", "CMOVQNE", "CMOVQCS", "CMOVQCC", "CMOVQGT": + case "CMOVQEQ", "CMOVQNE", "CMOVQCS", "CMOVQCC", "CMOVQGT", "CMOVQLE", "CMOVLGT", "CMOVWCC": // Conditional move: src, dstReg if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { return true, false, fmt.Errorf("amd64 %s expects src, dstReg: %q", op, ins.Raw) } - src, err := c.evalI64(ins.Args[0]) + ty := I64 + if op == "CMOVLGT" { + ty = I32 + } else if op == "CMOVWCC" { + ty = I16 + } + src, err := c.evalIntSized(ins.Args[0], ty) if err != nil { return true, false, err } dst := ins.Args[1].Reg - cur, err := c.loadReg(dst) + cur, err := c.evalIntSized(ins.Args[1], ty) if err != nil { return true, false, err } @@ -1418,12 +1380,12 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e cond = "%" + nz case "CMOVQCS": cond = c.loadFlag(c.flagsCFSlot) - case "CMOVQCC": + case "CMOVQCC", "CMOVWCC": cf := c.loadFlag(c.flagsCFSlot) nc := c.newTmp() fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", nc, cf) cond = "%" + nc - case "CMOVQGT": + case "CMOVQGT", "CMOVLGT": slt := c.loadFlag(c.flagsSltSlot) z := c.loadFlag(c.flagsZSlot) t1 := c.newTmp() @@ -1431,121 +1393,54 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e t2 := c.newTmp() fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", t2, t1) cond = "%" + t2 + case "CMOVQLE": + slt := c.loadFlag(c.flagsSltSlot) + z := c.loadFlag(c.flagsZSlot) + t := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %s, %s\n", t, slt, z) + cond = "%" + t } sel := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %s, i64 %s, i64 %s\n", sel, cond, src, cur) - return true, false, c.storeReg(dst, "%"+sel) + fmt.Fprintf(c.b, " %%%s = select i1 %s, %s %s, %s %s\n", sel, cond, ty, src, ty, cur) + return true, false, c.storeRegSized(dst, ty, "%"+sel) case "ANDNL", "ANDNQ": - // BMI1 ANDN: dst = ~src2 & src1 - if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects src1, src2, dstReg: %q", op, ins.Raw) - } - src1, err := c.evalI64(ins.Args[0]) - if err != nil { - return true, false, err + // BMI1 ANDN: destination = ~second & first. Go's _yandnl table + // accepts Yml,Yrl,Yrl for both spellings. VEX.W is ignored in 386. + if len(ins.Args) != 3 || ins.Args[1].Kind != OpReg || !isX86YrlRegisterForArch(ins.Args[1].Reg, c.goarch) || ins.Args[2].Kind != OpReg || !isX86YrlRegisterForArch(ins.Args[2].Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s expects GP/memory source, GP source, GP destination: %q", c.goarch, op, ins.Raw) } - src2, err := c.evalI64(ins.Args[1]) - if err != nil { - return true, false, err - } - dst := ins.Args[2].Reg - if op == "ANDNQ" { - n := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i64 %s, -1\n", n, src2) - a := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %%%s, %s\n", a, n, src1) - return true, false, c.storeReg(dst, "%"+a) - } - s1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", s1, src1) - s2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", s2, src2) - n := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i32 %%%s, -1\n", n, s2) - a := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i32 %%%s, %%%s\n", a, n, s1) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, a) - return true, false, c.storeReg(dst, "%"+z) - - case "BEXTRQ": - // BMI1 bit field extract: control, src, dst. - if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 BEXTRQ expects control, src, dstReg: %q", ins.Raw) + if ins.Args[0].Kind == OpReg { + if !isX86YrlRegisterForArch(ins.Args[0].Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s first source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) } - ctrl, err := c.evalI64(ins.Args[0]) - if err != nil { - return true, false, err + typ := I32 + if op == "ANDNQ" && c.goarch == "amd64" { + typ = I64 } - src, err := c.evalI64(ins.Args[1]) + first, err := c.evalIntSized(ins.Args[0], typ) if err != nil { return true, false, err } - start := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %s, 255\n", start, ctrl) - lenShift := c.newTmp() - fmt.Fprintf(c.b, " %%%s = lshr i64 %s, 8\n", lenShift, ctrl) - length := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %%%s, 255\n", length, lenShift) - startOK := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ult i64 %%%s, 64\n", startOK, start) - safeStart := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 63\n", safeStart, startOK, start) - shifted := c.newTmp() - fmt.Fprintf(c.b, " %%%s = lshr i64 %s, %%%s\n", shifted, src, safeStart) - rawLen := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 0\n", rawLen, startOK, length) - remain := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sub i64 64, %%%s\n", remain, safeStart) - useRawLen := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ult i64 %%%s, %%%s\n", useRawLen, rawLen, remain) - effLen := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 %%%s\n", effLen, useRawLen, rawLen, remain) - isFull := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp eq i64 %%%s, 64\n", isFull, effLen) - safeLen := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %%%s, 63\n", safeLen, effLen) - one := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shl i64 1, %%%s\n", one, safeLen) - maskTmp := c.newTmp() - fmt.Fprintf(c.b, " %%%s = add i64 %%%s, -1\n", maskTmp, one) - mask := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 -1, i64 %%%s\n", mask, isFull, maskTmp) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %%%s, %%%s\n", out, shifted, mask) - return true, false, c.storeReg(ins.Args[2].Reg, "%"+out) - - case "BZHIQ": - // BMI2 zero high bits: index, src, dst. - if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 BZHIQ expects index, src, dstReg: %q", ins.Raw) - } - idx, err := c.evalI64(ins.Args[0]) + second, err := c.evalIntSized(ins.Args[1], typ) if err != nil { return true, false, err } - src, err := c.evalI64(ins.Args[1]) - if err != nil { - return true, false, err + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, -1\n", inverted, typ, second) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %s\n", result, typ, inverted, first) + if typ == I64 { + c.setZSFlagsFromI64("%" + result) + } else { + c.setZSFlagsFromI32("%" + result) } - valid := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ult i64 %s, 64\n", valid, idx) - isZero := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp eq i64 %s, 0\n", isZero, idx) - safeIdx := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %s, 63\n", safeIdx, idx) - one := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shl i64 1, %%%s\n", one, safeIdx) - maskTmp := c.newTmp() - fmt.Fprintf(c.b, " %%%s = add i64 %%%s, -1\n", maskTmp, one) - maskOrZero := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 0, i64 %%%s\n", maskOrZero, isZero, maskTmp) - mask := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 -1\n", mask, valid, maskOrZero) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %s, %%%s\n", out, src, mask) - return true, false, c.storeReg(ins.Args[2].Reg, "%"+out) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + return true, false, c.storeRegSized(ins.Args[2].Reg, typ, "%"+result) case "SHRQ", "SHLQ", "SARQ", "SHLL", "SHRL", "SARL", "SALQ", "SALL": // Shift ops: @@ -1708,38 +1603,6 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i8 %%%s, i8 0\n", out, inRange, sh) return true, false, c.storeRegSized(dst, I8, "%"+out) - case "SHLXQ", "SHRXQ": - // BMI2 variable shifts: amt, src, dst. - if len(ins.Args) != 3 || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects amt, srcReg, dstReg: %q", op, ins.Raw) - } - src, err := c.loadReg(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - var amt string - switch ins.Args[0].Kind { - case OpImm: - amt = fmt.Sprintf("%d", ins.Args[0].Imm&63) - case OpReg: - av, err := c.loadReg(ins.Args[0].Reg) - if err != nil { - return true, false, err - } - m := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %s, 63\n", m, av) - amt = "%" + m - default: - return true, false, fmt.Errorf("amd64 %s unsupported shift amt: %q", op, ins.Raw) - } - t := c.newTmp() - if op == "SHLXQ" { - fmt.Fprintf(c.b, " %%%s = shl i64 %s, %s\n", t, src, amt) - } else { - fmt.Fprintf(c.b, " %%%s = lshr i64 %s, %s\n", t, src, amt) - } - return true, false, c.storeReg(ins.Args[2].Reg, "%"+t) - case "ROLL": // 32-bit rotate-left: count, dstReg. if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { @@ -1903,18 +1766,26 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e return true, false, c.storeReg(dst, "%"+z) case "RORXL", "RORXQ": - // BMI2 rotate-right without flags: - // - RORXL $imm, srcReg, dstReg (32-bit) - // - RORXQ $imm, srcReg, dstReg (64-bit) - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects $imm, srcReg, dstReg: %q", op, ins.Raw) + // BMI2 rotate-right without flags. Go's Yml source class accepts a + // general register or every ModRM/SIB memory form; Yrl is the complete + // destination class. In 386 mode Go accepts the Q spelling too, but + // VEX.W is ignored and the architectural operation remains 32-bit. + if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[2].Kind != OpReg || !isX86YrlRegisterForArch(ins.Args[2].Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s expects $imm, GP/memory source, in-range GP destination: %q", c.goarch, op, ins.Raw) } - src, err := c.loadReg(ins.Args[1].Reg) - if err != nil { - return true, false, err + if ins.Args[1].Kind == OpReg { + if !isX86YrlRegisterForArch(ins.Args[1].Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) } dst := ins.Args[2].Reg - if op == "RORXQ" { + if op == "RORXQ" && c.goarch == "amd64" { + src, err := c.evalIntSized(ins.Args[1], I64) + if err != nil { + return true, false, err + } n := uint64(ins.Args[0].Imm) & 63 neg := c.newTmp() fmt.Fprintf(c.b, " %%%s = sub i64 64, %d\n", neg, n) @@ -1928,61 +1799,29 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", rot, lhs, rhs) return true, false, c.storeReg(dst, "%"+rot) } + src, err := c.evalIntSized(ins.Args[1], I32) + if err != nil { + return true, false, err + } n := uint32(ins.Args[0].Imm) & 31 - tr := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", tr, src) neg := c.newTmp() fmt.Fprintf(c.b, " %%%s = sub i32 32, %d\n", neg, n) nm := c.newTmp() fmt.Fprintf(c.b, " %%%s = and i32 %%%s, 31\n", nm, neg) lhs := c.newTmp() - fmt.Fprintf(c.b, " %%%s = lshr i32 %%%s, %d\n", lhs, tr, n) + fmt.Fprintf(c.b, " %%%s = lshr i32 %s, %d\n", lhs, src, n) rhs := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shl i32 %%%s, %%%s\n", rhs, tr, nm) + fmt.Fprintf(c.b, " %%%s = shl i32 %s, %%%s\n", rhs, src, nm) rot := c.newTmp() fmt.Fprintf(c.b, " %%%s = or i32 %%%s, %%%s\n", rot, lhs, rhs) z := c.newTmp() fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, rot) return true, false, c.storeReg(dst, "%"+z) - case "NOTB": - // NOT does not modify flags. For a register operand, only the selected - // low byte is changed and the remaining register bits are preserved. - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("amd64 NOTB expects one operand: %q", ins.Raw) - } - switch ins.Args[0].Kind { - case OpReg: - r := ins.Args[0].Reg - v64, err := c.loadReg(r) - if err != nil { - return true, false, err - } - v8 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i8\n", v8, v64) - not := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i8 %%%s, -1\n", not, v8) - return true, false, c.storeRegSized(r, I8, "%"+not) - case OpMem: - addr, err := c.addrFromMem(ins.Args[0].Mem) - if err != nil { - return true, false, err - } - p := c.ptrFromAddrI64(addr) - load := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i8, ptr %s, align 1\n", load, p) - not := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i8 %%%s, -1\n", not, load) - fmt.Fprintf(c.b, " store i8 %%%s, ptr %s, align 1\n", not, p) - return true, false, nil - default: - return true, false, fmt.Errorf("amd64 NOTB expects reg or mem: %q", ins.Raw) - } - - case "NOTL": - // 32-bit bitwise NOT, result zero-extended to 64-bit. + case "BSWAPL": + // BSWAPL reg: byte swap low 32 bits and zero-extend result to i64. if len(ins.Args) != 1 || ins.Args[0].Kind != OpReg { - return true, false, fmt.Errorf("amd64 NOTL expects reg: %q", ins.Raw) + return true, false, fmt.Errorf("amd64 BSWAPL expects reg: %q", ins.Raw) } r := ins.Args[0].Reg v64, err := c.loadReg(r) @@ -1991,94 +1830,67 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e } tr := c.newTmp() fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", tr, v64) - x := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i32 %%%s, -1\n", x, tr) + bswap := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.bswap.i32(i32 %%%s)\n", bswap, tr) z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, x) + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, bswap) return true, false, c.storeReg(r, "%"+z) - case "NOTQ": - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("amd64 NOTQ expects one operand: %q", ins.Raw) + case "MULXL": + // BMI2 MULXL src, loDst, hiDst multiplies the low 32 bits of DX by + // a 32-bit register or memory source and zero-extends both results. + if len(ins.Args) != 3 || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("amd64 MULXL expects src, loDst, hiDst: %q", ins.Raw) } + var src32 string switch ins.Args[0].Kind { case OpReg: - r := ins.Args[0].Reg - v, err := c.loadReg(r) + src64, err := c.loadReg(ins.Args[0].Reg) if err != nil { return true, false, err } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i64 %s, -1\n", t, v) - return true, false, c.storeReg(r, "%"+t) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", value, src64) + src32 = "%" + value case OpMem: - addr, err := c.addrFromMem(ins.Args[0].Mem) + pointer, pointerType, err := c.ptrFromMem(ins.Args[0].Mem) if err != nil { return true, false, err } - p := c.ptrFromAddrI64(addr) - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i64, ptr %s, align 1\n", ld, p) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i64 %%%s, -1\n", t, ld) - fmt.Fprintf(c.b, " store i64 %%%s, ptr %s, align 1\n", t, p) - return true, false, nil + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i32, %s %s, align 1\n", value, pointerType, pointer) + src32 = "%" + value default: - return true, false, fmt.Errorf("amd64 NOTQ expects reg or mem: %q", ins.Raw) - } - - case "BSWAPL": - // BSWAPL reg: byte swap low 32 bits and zero-extend result to i64. - if len(ins.Args) != 1 || ins.Args[0].Kind != OpReg { - return true, false, fmt.Errorf("amd64 BSWAPL expects reg: %q", ins.Raw) - } - r := ins.Args[0].Reg - v64, err := c.loadReg(r) - if err != nil { - return true, false, err - } - tr := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", tr, v64) - bswap := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i32 @llvm.bswap.i32(i32 %%%s)\n", bswap, tr) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, bswap) - return true, false, c.storeReg(r, "%"+z) - - case "MULQ": - // MULQ src: RDX:RAX = RAX * src (unsigned). - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("amd64 MULQ expects src: %q", ins.Raw) + return true, false, fmt.Errorf("amd64 MULXL source must be register or memory: %q", ins.Raw) } - src, err := c.evalI64(ins.Args[0]) - if err != nil { - return true, false, err - } - ax, err := c.loadReg(AX) + dx64, err := c.loadReg(DX) if err != nil { return true, false, err } - a128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i64 %s to i128\n", a128, ax) - b128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i64 %s to i128\n", b128, src) - p := c.newTmp() - fmt.Fprintf(c.b, " %%%s = mul i128 %%%s, %%%s\n", p, a128, b128) - lo := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", lo, p) + dx32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", dx32, dx64) + a64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", a64, dx32) + b64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", b64, src32) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %%%s\n", product, a64, b64) + lo32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", lo32, product) hiShift := c.newTmp() - fmt.Fprintf(c.b, " %%%s = lshr i128 %%%s, 64\n", hiShift, p) - hi := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", hi, hiShift) - if err := c.storeReg(AX, "%"+lo); err != nil { + fmt.Fprintf(c.b, " %%%s = lshr i64 %%%s, 32\n", hiShift, product) + hi32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", hi32, hiShift) + lo64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", lo64, lo32) + hi64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", hi64, hi32) + if err := c.storeReg(ins.Args[1].Reg, "%"+lo64); err != nil { return true, false, err } - if err := c.storeReg(DX, "%"+hi); err != nil { + if err := c.storeReg(ins.Args[2].Reg, "%"+hi64); err != nil { return true, false, err } - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ne i64 %%%s, 0\n", cf, hi) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCFSlot) return true, false, nil case "MULXQ": @@ -2114,260 +1926,6 @@ func (c *amd64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e } return true, false, nil - case "MULL": - // MULL src: EDX:EAX = EAX * src (unsigned 32-bit) - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("amd64 MULL expects src: %q", ins.Raw) - } - src32, err := c.evalIntSized(ins.Args[0], I32) - if err != nil { - return true, false, err - } - ax64, err := c.loadReg(AX) - if err != nil { - return true, false, err - } - ax32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", ax32, ax64) - az := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", az, ax32) - bz := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", bz, src32) - p := c.newTmp() - fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %%%s\n", p, az, bz) - lo32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", lo32, p) - hiShift := c.newTmp() - fmt.Fprintf(c.b, " %%%s = lshr i64 %%%s, 32\n", hiShift, p) - hi32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", hi32, hiShift) - lo64 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", lo64, lo32) - hi64 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", hi64, hi32) - if err := c.storeReg(AX, "%"+lo64); err != nil { - return true, false, err - } - if err := c.storeReg(DX, "%"+hi64); err != nil { - return true, false, err - } - return true, false, nil - - case "DIVL": - // DIVL src: unsigned divide EDX:EAX by src; quotient->EAX remainder->EDX. - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("amd64 DIVL expects src: %q", ins.Raw) - } - src32, err := c.evalIntSized(ins.Args[0], I32) - if err != nil { - return true, false, err - } - ax64, err := c.loadReg(AX) - if err != nil { - return true, false, err - } - dx64, err := c.loadReg(DX) - if err != nil { - return true, false, err - } - ax32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", ax32, ax64) - dx32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", dx32, dx64) - az := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", az, ax32) - dz := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", dz, dx32) - divisor := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", divisor, src32) - hi := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shl i64 %%%s, 32\n", hi, dz) - dividend := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", dividend, hi, az) - q := c.newTmp() - fmt.Fprintf(c.b, " %%%s = udiv i64 %%%s, %%%s\n", q, dividend, divisor) - r := c.newTmp() - fmt.Fprintf(c.b, " %%%s = urem i64 %%%s, %%%s\n", r, dividend, divisor) - q32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", q32, q) - r32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", r32, r) - q64 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", q64, q32) - r64 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", r64, r32) - if err := c.storeReg(AX, "%"+q64); err != nil { - return true, false, err - } - if err := c.storeReg(DX, "%"+r64); err != nil { - return true, false, err - } - return true, false, nil - - case "IMULL", "IMUL3L": - // Signed 32-bit multiply. The one-operand form writes DX:AX; the two- - // and three-operand forms write the low word to their explicit dst. - switch len(ins.Args) { - case 1: - src, err := c.evalIntSized(ins.Args[0], I32) - if err != nil { - return true, false, err - } - ax, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, I32) - if err != nil { - return true, false, err - } - a64 := c.newTmp() - b64 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sext i32 %s to i64\n", a64, ax) - fmt.Fprintf(c.b, " %%%s = sext i32 %s to i64\n", b64, src) - product := c.newTmp() - fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %%%s\n", product, a64, b64) - lo := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", lo, product) - hiShift := c.newTmp() - fmt.Fprintf(c.b, " %%%s = ashr i64 %%%s, 32\n", hiShift, product) - hi := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", hi, hiShift) - if err := c.storeRegSized(AX, I32, "%"+lo); err != nil { - return true, false, err - } - return true, false, c.storeRegSized(DX, I32, "%"+hi) - case 2: - if ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 IMULL expects src, dstReg: %q", ins.Raw) - } - src, err := c.evalIntSized(ins.Args[0], I32) - if err != nil { - return true, false, err - } - dst, err := c.evalIntSized(ins.Args[1], I32) - if err != nil { - return true, false, err - } - product := c.newTmp() - fmt.Fprintf(c.b, " %%%s = mul i32 %s, %s\n", product, dst, src) - return true, false, c.storeRegSized(ins.Args[1].Reg, I32, "%"+product) - case 3: - if op != "IMUL3L" || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects imm, src, dstReg: %q", op, ins.Raw) - } - a, err := c.evalIntSized(ins.Args[0], I32) - if err != nil { - return true, false, err - } - bv, err := c.evalIntSized(ins.Args[1], I32) - if err != nil { - return true, false, err - } - product := c.newTmp() - fmt.Fprintf(c.b, " %%%s = mul i32 %s, %s\n", product, bv, a) - return true, false, c.storeRegSized(ins.Args[2].Reg, I32, "%"+product) - default: - return true, false, fmt.Errorf("amd64 %s unsupported operand count: %q", op, ins.Raw) - } - - case "IMULQ", "IMUL3Q": - // IMULQ src -> RDX:RAX = signed RAX*src - // IMULQ src, dst -> dst = signed(dst*src) - // IMUL3Q imm,src,dst -> dst = signed(src*imm) - switch len(ins.Args) { - case 1: - src, err := c.evalI64(ins.Args[0]) - if err != nil { - return true, false, err - } - ax, err := c.loadReg(AX) - if err != nil { - return true, false, err - } - a128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sext i64 %s to i128\n", a128, ax) - b128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sext i64 %s to i128\n", b128, src) - p := c.newTmp() - fmt.Fprintf(c.b, " %%%s = mul i128 %%%s, %%%s\n", p, a128, b128) - lo := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", lo, p) - hiShift := c.newTmp() - fmt.Fprintf(c.b, " %%%s = ashr i128 %%%s, 64\n", hiShift, p) - hi := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", hi, hiShift) - if err := c.storeReg(AX, "%"+lo); err != nil { - return true, false, err - } - if err := c.storeReg(DX, "%"+hi); err != nil { - return true, false, err - } - return true, false, nil - case 2: - if ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 IMULQ expects src, dstReg: %q", ins.Raw) - } - src, err := c.evalI64(ins.Args[0]) - if err != nil { - return true, false, err - } - dst := ins.Args[1].Reg - dv, err := c.loadReg(dst) - if err != nil { - return true, false, err - } - a128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sext i64 %s to i128\n", a128, dv) - b128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sext i64 %s to i128\n", b128, src) - p := c.newTmp() - fmt.Fprintf(c.b, " %%%s = mul i128 %%%s, %%%s\n", p, a128, b128) - lo := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", lo, p) - return true, false, c.storeReg(dst, "%"+lo) - case 3: - if op != "IMUL3Q" || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects imm, src, dstReg: %q", op, ins.Raw) - } - imm, err := c.evalI64(ins.Args[0]) - if err != nil { - return true, false, err - } - src, err := c.evalI64(ins.Args[1]) - if err != nil { - return true, false, err - } - a128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sext i64 %s to i128\n", a128, src) - b128 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sext i64 %s to i128\n", b128, imm) - p := c.newTmp() - fmt.Fprintf(c.b, " %%%s = mul i128 %%%s, %%%s\n", p, a128, b128) - lo := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", lo, p) - return true, false, c.storeReg(ins.Args[2].Reg, "%"+lo) - default: - return true, false, fmt.Errorf("amd64 %s expects 1/2/3 operands: %q", op, ins.Raw) - } - - case "NEGQ": - // NEGQ reg - if len(ins.Args) != 1 || ins.Args[0].Kind != OpReg { - return true, false, fmt.Errorf("amd64 NEGQ expects reg: %q", ins.Raw) - } - r := ins.Args[0].Reg - v, err := c.loadReg(r) - if err != nil { - return true, false, err - } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sub i64 0, %s\n", t, v) - out := "%" + t - if err := c.storeReg(r, out); err != nil { - return true, false, err - } - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ne i64 %s, 0\n", cf, v) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCFSlot) - c.setZSFlagsFromI64(out) - return true, false, nil } return false, false, nil } diff --git a/amd64_lower_arithmetic_shift.go b/amd64_lower_arithmetic_shift.go new file mode 100644 index 00000000..94ed6403 --- /dev/null +++ b/amd64_lower_arithmetic_shift.go @@ -0,0 +1,241 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedArithmeticRightShift implements the two Go 1.27 packed uniform +// arithmetic-right-shift tables: legacy PSRAW/PSRAL use yps, VPSRAW/VPSRAD use +// _yvpslld, and EVEX-only VPSRAQ uses _yvpsraq. +func (c *amd64Ctx) lowerPackedArithmeticRightShift(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + switch baseOp { + case "PSRAW": + return c.lowerLegacyPackedArithmeticRightShift(baseOp, suffix, 16, ins) + case "PSRAL": + return c.lowerLegacyPackedArithmeticRightShift(baseOp, suffix, 32, ins) + case "VPSRAW": + return c.lowerVectorPackedArithmeticRightShift(baseOp, suffix, 16, false, ins) + case "VPSRAD": + return c.lowerVectorPackedArithmeticRightShift(baseOp, suffix, 32, true, ins) + case "VPSRAQ": + return c.lowerVectorPackedArithmeticRightShift(baseOp, suffix, 64, true, ins) + default: + return false, false, nil + } +} + +func (c *amd64Ctx) lowerLegacyPackedArithmeticRightShift(baseOp, suffix string, laneBits int, ins Instr) (bool, bool, error) { + if suffix != "" { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects count, packed destination: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[1].Reg + if _, mmx := amd64ParseMReg(destination); mmx { + if ins.Args[0].Kind != OpImm && ins.Args[0].Kind == OpReg { + if _, ok := amd64ParseMReg(ins.Args[0].Reg); !ok { + return true, false, fmt.Errorf("%s %s MMX form requires an immediate, MMX, or memory count: %q", c.goarch, baseOp, ins.Raw) + } + } else if ins.Args[0].Kind != OpImm && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s MMX form requires an immediate, MMX, or memory count: %q", c.goarch, baseOp, ins.Raw) + } + dataBits, err := c.loadReg(destination) + if err != nil { + return true, false, err + } + lanes := 64 / laneBits + data := c.bitcastI64ToIntegerLanes(lanes, laneBits, dataBits) + count, err := c.loadPackedUniformShiftCount(ins.Args[0], true, laneBits) + if err != nil { + return true, false, err + } + result := c.emitPackedArithmeticRightShift(lanes, laneBits, data, count) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to i64\n", bits, lanes, laneBits, result) + return true, false, c.storeReg(destination, "%"+bits) + } + + if !c.isGoLegacyXReg(destination) { + return true, false, fmt.Errorf("%s %s destination must be an in-range MMX or X register: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg && !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s XMM count must be an in-range X register: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpImm && ins.Args[0].Kind != OpReg && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s XMM form requires an immediate, X, or memory count: %q", c.goarch, baseOp, ins.Raw) + } + dataBytes, err := c.loadX(destination) + if err != nil { + return true, false, err + } + lanes := 128 / laneBits + data := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, dataBytes) + count, err := c.loadPackedUniformShiftCount(ins.Args[0], false, laneBits) + if err != nil { + return true, false, err + } + result := c.emitPackedArithmeticRightShift(lanes, laneBits, data, count) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, lanes, laneBits, result) + return true, false, c.storeX(destination, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedArithmeticRightShift(baseOp, suffix string, laneBits int, broadcastEnabled bool, ins Instr) (bool, bool, error) { + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix || properties.sae || properties.rounding != "" { + return true, false, fmt.Errorf("%s %s suffix is absent from its Go 1.27 table: %q", c.goarch, baseOp, ins.Raw) + } + if properties.broadcast && !broadcastEnabled { + return true, false, fmt.Errorf("%s %s does not enable EVEX broadcast: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects count, source, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7 as its third operand: %q", c.goarch, baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoPackedVectorMoveRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + + countArg, dataArg := ins.Args[0], ins.Args[1] + immediate := countArg.Kind == OpImm + if immediate { + if countArg.Imm < -128 || countArg.Imm > 255 { + return true, false, fmt.Errorf("%s %s immediate count is outside Go's signed/unsigned byte classes: %q", c.goarch, baseOp, ins.Raw) + } + if properties.broadcast { + if !isAMD64MemoryOperand(dataArg) { + return true, false, fmt.Errorf("%s %s.BCST requires an immediate count and scalar memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else if dataArg.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(dataArg, byteWidth) { + return true, false, fmt.Errorf("%s %s source register must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(dataArg) { + return true, false, fmt.Errorf("%s %s immediate form requires matching vector or memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else { + if properties.broadcast { + return true, false, fmt.Errorf("%s %s.BCST is absent from variable-count rows: %q", c.goarch, baseOp, ins.Raw) + } + if countArg.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(countArg, 16) { + return true, false, fmt.Errorf("%s %s variable count must be X/m128: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(countArg) { + return true, false, fmt.Errorf("%s %s variable count must be X/m128: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoPackedVectorMoveRegister(dataArg, byteWidth) { + return true, false, fmt.Errorf("%s %s variable-count data must be a matching vector register: %q", c.goarch, baseOp, ins.Raw) + } + } + + lanes := byteWidth * 8 / laneBits + var data string + var err error + if properties.broadcast { + var scalar string + scalar, err = c.evalIntSized(dataArg, amd64IntegerTypeForBits(laneBits)) + if err == nil { + data = amd64SplatInteger(c, lanes, laneBits, scalar) + } + } else { + var bytesValue string + bytesValue, err = c.loadPackedCompareBytes(dataArg, byteWidth) + if err == nil { + data = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, bytesValue) + } + } + if err != nil { + return true, false, err + } + count, err := c.loadPackedUniformShiftCount(countArg, false, laneBits) + if err != nil { + return true, false, err + } + result := c.emitPackedArithmeticRightShift(lanes, laneBits, data, count) + if masked { + mask, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, laneBits, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +// loadPackedUniformShiftCount returns an i64 count clamped to laneBits-1, as +// specified for x86 packed arithmetic shifts when the count is too large. +func (c *amd64Ctx) loadPackedUniformShiftCount(count Operand, mmx bool, laneBits int) (string, error) { + if count.Kind == OpImm { + value := uint64(count.Imm) & 0xff + if value >= uint64(laneBits) { + value = uint64(laneBits - 1) + } + return fmt.Sprintf("%d", value), nil + } + var count64 string + var err error + if mmx { + count64, err = c.loadLegacyMMXPackedSource(count) + } else { + var countBytes string + countBytes, err = c.loadXVecOperand(count) + if err == nil { + countWords := c.newTmp() + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", countWords, countBytes) + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 0\n", low, countWords) + count64 = "%" + low + } + } + if err != nil { + return "", err + } + inRange := c.newTmp() + clamped := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i64 %s, %d\n", inRange, count64, laneBits) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %s, i64 %d\n", clamped, inRange, count64, laneBits-1) + return "%" + clamped, nil +} + +func (c *amd64Ctx) emitPackedArithmeticRightShift(lanes, laneBits int, data, count64 string) string { + count := count64 + if laneBits < 64 { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrow, count64, laneBits) + count = "%" + narrow + } + counts := amd64SplatInteger(c, lanes, laneBits, count) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ashr <%d x i%d> %s, %s\n", result, lanes, laneBits, data, counts) + return "%" + result +} diff --git a/amd64_lower_arithmetic_shift_test.go b/amd64_lower_arithmetic_shift_test.go new file mode 100644 index 00000000..ec6802c1 --- /dev/null +++ b/amd64_lower_arithmetic_shift_test.go @@ -0,0 +1,138 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedArithmeticRightShiftCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast, zLast := 15, 22 + if target.goarch == "386" { + legacyLast, zLast = 7, 7 + } + var source strings.Builder + source.WriteString("TEXT packedarithmeticrightshiftforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PSRAW", "PSRAL"} { + fmt.Fprintf(&source, "\t%s $3, M1\n", op) + fmt.Fprintf(&source, "\t%s M0, M1\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), M1\n", op) + fmt.Fprintf(&source, "\t%s $-1, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s X0, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, legacyLast) + } + for _, op := range []string{"VPSRAW", "VPSRAD", "VPSRAQ"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&source, "\t%s $3, %s20, %s21\n", op, width, width) + fmt.Fprintf(&source, "\t%s $3, 8(AX), %s21\n", op, width) + fmt.Fprintf(&source, "\t%s X0, %s20, %s21\n", op, width, width) + fmt.Fprintf(&source, "\t%s 8(AX), %s20, %s21\n", op, width, width) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s $3, %s20, K1, %s22\n", op, width, width) + fmt.Fprintf(&source, "\t%s.Z X0, %s20, K7, %s22\n", op, width, width) + } + } + fmt.Fprintf(&source, "\t%s $3, Z6, Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s $3, 8(AX), Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s X0, Z6, Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s 8(AX), Z6, Z%d\n", op, zLast) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s $3, Z20, K2, Z22\n", op) + fmt.Fprintf(&source, "\t%s.Z 8(AX), Z20, K6, Z22\n", op) + } + if op != "VPSRAW" { + fmt.Fprintf(&source, "\t%s.BCST $3, 8(AX), X21\n", op) + fmt.Fprintf(&source, "\t%s.BCST $3, 8(AX), Y21\n", op) + fmt.Fprintf(&source, "\t%s.BCST $3, 8(AX), Z%d\n", op, zLast) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.BCST.Z $3, 8(AX), K5, Z22\n", op) + } + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedarithmeticrightshiftforms": {Name: "packedarithmeticrightshiftforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-arithmetic-right-shift-"+target.name+".ll", "packed-arithmetic-right-shift-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedArithmeticRightShiftRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PSRAW.Z $3, X0", + "PSRAL $3", + "PSRAW M0, X1", + "PSRAL X0, M1", + "PSRAQ $3, X0", + "PSRAW $3, Y0", + "VPSRAW R8, X1, X2", + "VPSRAD Y0, X1, X2", + "VPSRAQ X0, 8(AX), X2", + "VPSRAW.BCST $3, 8(AX), X2", + "VPSRAD.BCST X0, X1, X2", + "VPSRAQ.BCST $3, X1, X2", + "VPSRAW.Z $3, X1, X2", + "VPSRAD $3, X1, K0, X2", + "VPSRAQ $3, X1, K1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedArithmeticRightShiftRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PSRAW X8, X0", + "PSRAL X0, X8", + "VPSRAW $3, Z8, Z1", + "VPSRAD X0, Z1, Z8", + "VPSRAQ $3, X1, K1, X2", + "VPSRAW.Z X0, X1, K1, X2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedArithmeticRightShiftRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedArithmeticRightShiftRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed arithmetic-right-shift forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_atomic.go b/amd64_lower_atomic.go index c2783260..a85c94f6 100644 --- a/amd64_lower_atomic.go +++ b/amd64_lower_atomic.go @@ -3,240 +3,20 @@ package plan9asm import "fmt" func (c *amd64Ctx) lowerAtomic(op Op, ins Instr) (ok bool, terminated bool, err error) { + if _, _, recognized := amd64CompareExchangeProperties(normalizeInstructionOpcode(op)); recognized { + return c.lowerCompareExchange(op, ins) + } switch op { case "LOCK": // LOCK is a prefix in Plan 9 syntax. Our lowering emits atomic IR for // the following memory RMW instruction, so the prefix itself is a no-op. return true, false, nil - case "CMPXCHG8B": - if len(ins.Args) != 1 || ins.Args[0].Kind != OpMem { - return true, false, fmt.Errorf("amd64 CMPXCHG8B expects mem: %q", ins.Raw) - } - word := func(r Reg) (string, error) { - return c.evalIntSized(Operand{Kind: OpReg, Reg: r}, I32) - } - ax, err := word(AX) - if err != nil { - return true, false, err - } - dx, err := word(DX) - if err != nil { - return true, false, err - } - bx, err := word(BX) - if err != nil { - return true, false, err - } - cx, err := word(CX) - if err != nil { - return true, false, err - } - pair := func(lo, hi string) string { - lo64 := c.newTmp() - hi64 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", lo64, lo) - fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", hi64, hi) - shifted := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shl i64 %%%s, 32\n", shifted, hi64) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", out, shifted, lo64) - return "%" + out - } - expected := pair(ax, dx) - desired := pair(bx, cx) - ptr, ptrType, err := c.ptrFromMem(ins.Args[0].Mem) - if err != nil { - return true, false, err - } - if ptrType != "ptr" { - return true, false, fmt.Errorf("amd64 CMPXCHG8B does not support segment-relative memory: %q", ins.Raw) - } - result := c.newTmp() - fmt.Fprintf(c.b, " %%%s = cmpxchg ptr %s, i64 %s, i64 %s seq_cst seq_cst, align 8\n", result, ptr, expected, desired) - old := c.newTmp() - success := c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractvalue { i64, i1 } %%%s, 0\n", old, result) - fmt.Fprintf(c.b, " %%%s = extractvalue { i64, i1 } %%%s, 1\n", success, result) - oldLo := c.newTmp() - oldHiShift := c.newTmp() - oldHi := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", oldLo, old) - fmt.Fprintf(c.b, " %%%s = lshr i64 %%%s, 32\n", oldHiShift, old) - fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", oldHi, oldHiShift) - if err := c.storeRegSized(AX, I32, "%"+oldLo); err != nil { - return true, false, err - } - if err := c.storeRegSized(DX, I32, "%"+oldHi); err != nil { - return true, false, err - } - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", success, c.flagsZSlot) - return true, false, nil - - case "CMPXCHGL", "CMPXCHGQ": - if len(ins.Args) != 2 || ins.Args[1].Kind != OpMem { - return true, false, fmt.Errorf("amd64 %s expects src, mem: %q", op, ins.Raw) - } - ty := I32 - align := 4 - if op == "CMPXCHGQ" { - ty = I64 - align = 8 - } - - expAX, err := c.loadReg(AX) - if err != nil { - return true, false, err - } - exp, err := c.amd64AtomicTruncFromI64(expAX, ty) - if err != nil { - return true, false, err - } - newv64, err := c.evalI64(ins.Args[0]) - if err != nil { - return true, false, err - } - newv, err := c.amd64AtomicTruncFromI64(newv64, ty) - if err != nil { - return true, false, err - } - ptr, err := c.amd64AtomicPtrFromMem(ins.Args[1].Mem) - if err != nil { - return true, false, err - } - cx := c.newTmp() - fmt.Fprintf(c.b, " %%%s = cmpxchg ptr %s, %s %s, %s %s seq_cst seq_cst, align %d\n", cx, ptr, ty, exp, ty, newv, align) - old := c.newTmp() - okv := c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractvalue {%s, i1} %%%s, 0\n", old, ty, cx) - fmt.Fprintf(c.b, " %%%s = extractvalue {%s, i1} %%%s, 1\n", okv, ty, cx) - old64, err := c.amd64AtomicExtendToI64("%"+old, ty) - if err != nil { - return true, false, err - } - if err := c.storeReg(AX, old64); err != nil { - return true, false, err - } - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", okv, c.flagsZSlot) - return true, false, nil + case "XADDB", "XADDW", "XADDL", "XADDQ": + return c.lowerXADD(op, ins) - case "XADDL", "XADDQ": - if len(ins.Args) != 2 || ins.Args[1].Kind != OpMem { - return true, false, fmt.Errorf("amd64 %s expects srcReg, mem: %q", op, ins.Raw) - } - srcReg := ins.Args[0] - if srcReg.Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects register src: %q", op, ins.Raw) - } - ty := I32 - if op == "XADDQ" { - ty = I64 - } - src64, err := c.loadReg(srcReg.Reg) - if err != nil { - return true, false, err - } - src, err := c.amd64AtomicTruncFromI64(src64, ty) - if err != nil { - return true, false, err - } - ptr, err := c.amd64AtomicPtrFromMem(ins.Args[1].Mem) - if err != nil { - return true, false, err - } - old := c.newTmp() - fmt.Fprintf(c.b, " %%%s = atomicrmw add ptr %s, %s %s seq_cst\n", old, ptr, ty, src) - old64, err := c.amd64AtomicExtendToI64("%"+old, ty) - if err != nil { - return true, false, err - } - return true, false, c.storeReg(srcReg.Reg, old64) - - case "XCHGB", "XCHGL", "XCHGQ": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("amd64 %s expects srcReg, dst: %q", op, ins.Raw) - } - srcReg := ins.Args[0] - if srcReg.Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects register src: %q", op, ins.Raw) - } - ty := I8 - switch op { - case "XCHGL": - ty = I32 - case "XCHGQ": - ty = I64 - } - src64, err := c.loadReg(srcReg.Reg) - if err != nil { - return true, false, err - } - if ins.Args[1].Kind == OpReg { - dstReg := ins.Args[1].Reg - dst64, err := c.loadReg(dstReg) - if err != nil { - return true, false, err - } - switch ty { - case I64: - if err := c.storeReg(srcReg.Reg, dst64); err != nil { - return true, false, err - } - return true, false, c.storeReg(dstReg, src64) - case I32: - s32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", s32, src64) - d32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", d32, dst64) - sz := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", sz, s32) - dz := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", dz, d32) - if err := c.storeReg(srcReg.Reg, "%"+dz); err != nil { - return true, false, err - } - return true, false, c.storeReg(dstReg, "%"+sz) - default: - s8 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i8\n", s8, src64) - d8 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i8\n", d8, dst64) - sz := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i64\n", sz, s8) - dz := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i64\n", dz, d8) - if err := c.storeReg(srcReg.Reg, "%"+dz); err != nil { - return true, false, err - } - return true, false, c.storeReg(dstReg, "%"+sz) - } - } - if ins.Args[1].Kind != OpMem && ins.Args[1].Kind != OpSym { - return true, false, fmt.Errorf("amd64 %s expects srcReg, mem/reg: %q", op, ins.Raw) - } - src, err := c.amd64AtomicTruncFromI64(src64, ty) - if err != nil { - return true, false, err - } - ptr := "" - if ins.Args[1].Kind == OpMem { - ptr, err = c.amd64AtomicPtrFromMem(ins.Args[1].Mem) - if err != nil { - return true, false, err - } - } else { - ptr, err = c.ptrFromSB(ins.Args[1].Sym) - if err != nil { - return true, false, err - } - } - old := c.newTmp() - fmt.Fprintf(c.b, " %%%s = atomicrmw xchg ptr %s, %s %s seq_cst\n", old, ptr, ty, src) - old64, err := c.amd64AtomicExtendToI64("%"+old, ty) - if err != nil { - return true, false, err - } - return true, false, c.storeReg(srcReg.Reg, old64) + case "XCHGB", "XCHGW", "XCHGL", "XCHGQ": + return c.lowerXCHG(op, ins) case "ORB", "ANDB", "ORL", "ANDL", "ORQ", "ANDQ": if len(ins.Args) != 2 || ins.Args[1].Kind != OpMem { @@ -284,6 +64,155 @@ func (c *amd64Ctx) lowerAtomic(op Op, ins Instr) (ok bool, terminated bool, err return false, false, nil } +// lowerXADD implements every row selected by Go 1.27's yrb_mb and yrl_ml +// operand tables: a byte/general register source and a register or memory +// destination, across the B/W/L/Q opcode family. +func (c *amd64Ctx) lowerXADD(op Op, ins Instr) (bool, bool, error) { + bits := 8 + switch op { + case "XADDW": + bits = 16 + case "XADDL": + bits = 32 + case "XADDQ": + bits = 64 + } + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", op, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects register source and register/memory destination: %q", c.goarch, op, ins.Raw) + } + registerAllowed := func(reg Reg) bool { + if bits == 8 { + return isGoYmbRegisterForArch(reg, c.goarch) + } + return isX86YrlRegisterForArch(reg, c.goarch) + } + source, destination := ins.Args[0], ins.Args[1] + if source.Kind != OpReg || !registerAllowed(source.Reg) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yrb/Yrl class: %q", c.goarch, op, ins.Raw) + } + if destination.Kind == OpReg { + if !registerAllowed(destination.Reg) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Ymb/Yml class: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Ymb/Yml class: %q", c.goarch, op, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + sourceValue, err := c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + if destination.Kind == OpReg { + destinationValue, err := c.evalIntSized(destination, typ) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", result, typ, destinationValue, sourceValue) + // XADD reads both operands before either write. Writing the source first + // also preserves the right final value for identical and overlapping + // byte-register aliases when the destination write follows it. + if err := c.storeRegSized(source.Reg, typ, destinationValue); err != nil { + return true, false, err + } + if err := c.storeRegSized(destination.Reg, typ, "%"+result); err != nil { + return true, false, err + } + c.setScalarAddSubFlags(typ, true, destinationValue, sourceValue, "%"+result) + return true, false, nil + } + + ptr, ptrType, err := c.compareExchangePointer(destination) + if err != nil { + return true, false, err + } + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = atomicrmw add %s %s, %s %s seq_cst, align 1\n", old, ptrType, ptr, typ, sourceValue) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %%%s, %s\n", result, typ, old, sourceValue) + if err := c.storeRegSized(source.Reg, typ, "%"+old); err != nil { + return true, false, err + } + c.setScalarAddSubFlags(typ, true, "%"+old, sourceValue, "%"+result) + return true, false, nil +} + +// lowerXCHG implements Go 1.27's yml_mb byte rows and all four yxchg rows. +// XCHG is symmetric, so the memory operand may appear on either side. +func (c *amd64Ctx) lowerXCHG(op Op, ins Instr) (bool, bool, error) { + bits := 8 + switch op { + case "XCHGW": + bits = 16 + case "XCHGL": + bits = 32 + case "XCHGQ": + bits = 64 + } + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", op, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects two register/memory operands: %q", c.goarch, op, ins.Raw) + } + registerAllowed := func(reg Reg) bool { + if bits == 8 { + return isGoYmbRegisterForArch(reg, c.goarch) + } + return isX86YrlRegisterForArch(reg, c.goarch) + } + first, second := ins.Args[0], ins.Args[1] + if first.Kind == OpReg && second.Kind == OpReg { + if !registerAllowed(first.Reg) || !registerAllowed(second.Reg) { + return true, false, fmt.Errorf("%s %s register is outside Go 1.27's byte/general-register class: %q", c.goarch, op, ins.Raw) + } + typ := amd64IntegerTypeForBits(bits) + firstValue, err := c.evalIntSized(first, typ) + if err != nil { + return true, false, err + } + secondValue, err := c.evalIntSized(second, typ) + if err != nil { + return true, false, err + } + // Both values are loaded before either write. Source-first writeback also + // preserves overlapping AH/AL-style byte exchanges correctly. + if err := c.storeRegSized(first.Reg, typ, secondValue); err != nil { + return true, false, err + } + return true, false, c.storeRegSized(second.Reg, typ, firstValue) + } + + var register Operand + var memory Operand + if first.Kind == OpReg && isAMD64MemoryOperand(second) { + register, memory = first, second + } else if isAMD64MemoryOperand(first) && second.Kind == OpReg { + register, memory = second, first + } else { + return true, false, fmt.Errorf("%s %s expects one register and at most one memory operand: %q", c.goarch, op, ins.Raw) + } + if !registerAllowed(register.Reg) { + return true, false, fmt.Errorf("%s %s register is outside Go 1.27's byte/general-register class: %q", c.goarch, op, ins.Raw) + } + typ := amd64IntegerTypeForBits(bits) + registerValue, err := c.evalIntSized(register, typ) + if err != nil { + return true, false, err + } + ptr, ptrType, err := c.compareExchangePointer(memory) + if err != nil { + return true, false, err + } + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = atomicrmw xchg %s %s, %s %s seq_cst, align 1\n", old, ptrType, ptr, typ, registerValue) + return true, false, c.storeRegSized(register.Reg, typ, "%"+old) +} + func (c *amd64Ctx) amd64AtomicPtrFromMem(mem MemRef) (string, error) { ptr, ptrType, err := c.ptrFromMem(mem) if err != nil { diff --git a/amd64_lower_average.go b/amd64_lower_average.go new file mode 100644 index 00000000..c79ad0c5 --- /dev/null +++ b/amd64_lower_average.go @@ -0,0 +1,189 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedUnsignedAverage implements Go 1.27's complete PAVG/VPAVG family. +// Each unsigned B/W lane computes (a+b+1)>>1. Legacy forms use the ymm table +// (MMX and XMM); VEX/EVEX forms use _yvandnpd without broadcast. +func (c *amd64Ctx) lowerPackedUnsignedAverage(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits, vector, recognized := amd64PackedUnsignedAverageProperties(baseOp) + if !recognized { + return false, false, nil + } + if !vector { + if suffix != "" { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + return c.lowerLegacyPackedUnsignedAverage(baseOp, laneBits, ins) + } + return c.lowerVectorPackedUnsignedAverage(baseOp, suffix, laneBits, ins) +} + +func amd64PackedUnsignedAverageProperties(op string) (laneBits int, vector, ok bool) { + switch op { + case "PAVGB": + return 8, false, true + case "PAVGW": + return 16, false, true + case "VPAVGB": + return 8, true, true + case "VPAVGW": + return 16, true, true + default: + return 0, false, false + } +} + +func (c *amd64Ctx) lowerLegacyPackedUnsignedAverage(baseOp string, laneBits int, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects MMX/m64, MMX or X/m128, X: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[1].Reg + if _, mmx := amd64ParseMReg(destination); mmx { + if ins.Args[0].Kind == OpReg { + if _, ok := amd64ParseMReg(ins.Args[0].Reg); !ok { + return true, false, fmt.Errorf("%s %s MMX form requires an MMX source: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s MMX form requires MMX or memory source: %q", c.goarch, baseOp, ins.Raw) + } + firstBits, err := c.loadLegacyMMXPackedSource(ins.Args[0]) + if err != nil { + return true, false, err + } + secondBits, err := c.loadReg(destination) + if err != nil { + return true, false, err + } + lanes := 64 / laneBits + first := c.bitcastI64ToIntegerLanes(lanes, laneBits, firstBits) + second := c.bitcastI64ToIntegerLanes(lanes, laneBits, secondBits) + result := c.emitPackedUnsignedAverage(lanes, laneBits, first, second) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to i64\n", bits, lanes, laneBits, result) + return true, false, c.storeReg(destination, "%"+bits) + } + + if !c.isGoLegacyXReg(destination) { + return true, false, fmt.Errorf("%s %s destination must be an in-range MMX or X register: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg && !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s XMM form requires an in-range X source: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpReg && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s XMM form requires X or memory source: %q", c.goarch, baseOp, ins.Raw) + } + firstBytes, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(destination) + if err != nil { + return true, false, err + } + lanes := 128 / laneBits + first := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, secondBytes) + result := c.emitPackedUnsignedAverage(lanes, laneBits, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, lanes, laneBits, result) + return true, false, c.storeX(destination, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedUnsignedAverage(baseOp, suffix string, laneBits int, ins Instr) (bool, bool, error) { + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's _yvandnpd table: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects source2, source1, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7 as its third operand: %q", c.goarch, baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || + !c.isGoPackedVectorMoveRegister(destination, byteWidth) || + !c.isGoPackedVectorMoveRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s source1 and destination must be matching Go vector registers: %q", c.goarch, baseOp, ins.Raw) + } + firstArg := ins.Args[0] + if firstArg.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(firstArg, byteWidth) { + return true, false, fmt.Errorf("%s %s source2 register must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(firstArg) { + return true, false, fmt.Errorf("%s %s source2 must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + firstBytes, err := c.loadPackedCompareBytes(firstArg, byteWidth) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / laneBits + first := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, secondBytes) + result := c.emitPackedUnsignedAverage(lanes, laneBits, first, second) + if masked { + mask, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPackedUnsignedAverage(lanes, laneBits int, first, second string) string { + narrowType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + wideBits := laneBits * 2 + wideType := fmt.Sprintf("<%d x i%d>", lanes, wideBits) + firstWide := c.newTmp() + secondWide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", firstWide, narrowType, first, wideType) + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", secondWide, narrowType, second, wideType) + sum := c.newTmp() + rounded := c.newTmp() + average := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %%%s, %%%s\n", sum, wideType, firstWide, secondWide) + fmt.Fprintf(c.b, " %%%s = add %s %%%s, %s\n", rounded, wideType, sum, llvmSplatSignedInteger(lanes, wideBits, 1)) + fmt.Fprintf(c.b, " %%%s = lshr %s %%%s, %s\n", average, wideType, rounded, llvmSplatSignedInteger(lanes, wideBits, 1)) + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", result, wideType, average, narrowType) + return "%" + result +} diff --git a/amd64_lower_average_test.go b/amd64_lower_average_test.go new file mode 100644 index 00000000..a1ff8d3f --- /dev/null +++ b/amd64_lower_average_test.go @@ -0,0 +1,121 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedUnsignedAverageCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast, zLast := 15, 22 + if target.goarch == "386" { + legacyLast, zLast = 7, 7 + } + var source strings.Builder + source.WriteString("TEXT packedunsignedaverageforms(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"PAVGB", "PAVGW"} { + fmt.Fprintf(&source, "\t%s M0, M1\n", stem) + fmt.Fprintf(&source, "\t%s 8(AX), M2\n", stem) + fmt.Fprintf(&source, "\t%s X0, X%d\n", stem, legacyLast) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", stem, legacyLast) + vector := "V" + stem + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&source, "\t%s %s0, %s1, %s2\n", vector, width, width, width) + fmt.Fprintf(&source, "\t%s 8(AX), %s20, %s21\n", vector, width, width) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s %s20, %s21, K1, %s22\n", vector, width, width, width) + fmt.Fprintf(&source, "\t%s.Z 8(AX), %s21, K7, %s22\n", vector, width, width) + } + } + fmt.Fprintf(&source, "\t%s Z0, Z6, Z%d\n", vector, zLast) + fmt.Fprintf(&source, "\t%s 8(AX), Z6, Z%d\n", vector, zLast) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s Z20, Z21, K2, Z22\n", vector) + fmt.Fprintf(&source, "\t%s.Z 8(AX), Z21, K6, Z22\n", vector) + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedunsignedaverageforms": {Name: "packedunsignedaverageforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-unsigned-average-"+target.name+".ll", "packed-unsigned-average-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedUnsignedAverageRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PAVGB.Z X0, X1", + "PAVGW X0", + "PAVGB M0, X1", + "PAVGW X0, M1", + "PAVGB Y0, Y1", + "PAVGW X0, (AX)", + "VPAVGB X0, X1", + "VPAVGW X0, Y1, Y2", + "VPAVGB X0, X1, (AX)", + "VPAVGW.BCST 8(AX), X1, X2", + "VPAVGB.Z X0, X1, X2", + "VPAVGW X0, X1, K0, X2", + "VPAVGB X0, X1, K1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedUnsignedAverageRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PAVGB X8, X0", + "PAVGW X0, X8", + "VPAVGB Z8, Z1, Z2", + "VPAVGW Z0, Z1, Z8", + "VPAVGB X0, X1, K1, X2", + "VPAVGW.Z X0, X1, K1, X2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedUnsignedAverageRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedUnsignedAverageRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed unsigned-average forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_bextr.go b/amd64_lower_bextr.go new file mode 100644 index 00000000..a21afc9c --- /dev/null +++ b/amd64_lower_bextr.go @@ -0,0 +1,85 @@ +package plan9asm + +import "fmt" + +// lowerBEXTR implements Go 1.27's complete _ybextrl operand row for BEXTRL/Q: +// register control, register/memory source, and register destination. +func (c *amd64Ctx) lowerBEXTR(op Op, ins Instr) (ok bool, terminated bool, err error) { + bits := 0 + switch op { + case "BEXTRL": + bits = 32 + case "BEXTRQ": + bits = 64 + default: + return false, false, nil + } + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects register control, register/memory source, and register destination: %q", c.goarch, op, ins.Raw) + } + control, source, destination := ins.Args[0], ins.Args[1], ins.Args[2] + if control.Kind != OpReg || !isX86YrlRegisterForArch(control.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s control is outside Go 1.27's Yrl class: %q", c.goarch, op, ins.Raw) + } + if source.Kind == OpReg { + if !isX86YrlRegisterForArch(source.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yrl class: %q", c.goarch, op, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + controlValue, err := c.evalIntSized(control, typ) + if err != nil { + return true, false, err + } + sourceValue, err := c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + start := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, 255\n", start, typ, controlValue) + lengthShift := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %s, 8\n", lengthShift, typ, controlValue) + length := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %%%s, 255\n", length, typ, lengthShift) + startOK := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult %s %%%s, %d\n", startOK, typ, start, bits) + safeStart := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s %d\n", safeStart, startOK, typ, start, typ, bits-1) + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %%%s\n", shifted, typ, sourceValue, safeStart) + rawLength := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s 0\n", rawLength, startOK, typ, length, typ) + remaining := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s %d, %%%s\n", remaining, typ, bits, safeStart) + useRawLength := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult %s %%%s, %%%s\n", useRawLength, typ, rawLength, remaining) + effectiveLength := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s %%%s\n", effectiveLength, useRawLength, typ, rawLength, typ, remaining) + isFullWidth := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, %d\n", isFullWidth, typ, effectiveLength, bits) + safeLength := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %d\n", safeLength, typ, effectiveLength, bits-1) + one := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl %s 1, %%%s\n", one, typ, safeLength) + partialMask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %%%s, -1\n", partialMask, typ, one) + mask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s -1, %s %%%s\n", mask, isFullWidth, typ, typ, partialMask) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", result, typ, shifted, mask) + if err := c.storeRegSized(destination.Reg, typ, "%"+result); err != nil { + return true, false, err + } + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, 0\n", zero, typ, result) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + return true, false, nil +} diff --git a/amd64_lower_bextr_test.go b/amd64_lower_bextr_test.go new file mode 100644 index 00000000..92dd4f62 --- /dev/null +++ b/amd64_lower_bextr_test.go @@ -0,0 +1,198 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86BEXTRCompleteFormsSource(goarch string) string { + var source strings.Builder + source.WriteString("DATA bextrdata+0(SB)/8, $1\n") + source.WriteString("GLOBL bextrdata(SB), $8\n") + source.WriteString("TEXT bextrforms(SB),$0-0\n") + for _, width := range []string{"L", "Q"} { + op := "BEXTR" + width + fmt.Fprintf(&source, "\t%s AX, BX, CX\n", op) + fmt.Fprintf(&source, "\t%s DX, 8(BX), SI\n", op) + fmt.Fprintf(&source, "\t%s CX, bextrdata(SB), DX\n", op) + if goarch == "amd64" { + fmt.Fprintf(&source, "\t%s R11, R12, R13\n", op) + } else { + fmt.Fprintf(&source, "\t%s AX, BX, SP\n", op) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86BEXTRCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86BEXTRCompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"bextrforms": {Name: "bextrforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"lshr i32", "lshr i64", `"target-features"="+bmi"`} { + if !strings.Contains(ir, want) { + t.Fatalf("BEXTR lowering omitted %q:\n%s", want, ir) + } + } + if strings.Contains(ir, "+bmi2") { + t.Fatalf("BEXTR is BMI1 but inferred BMI2:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "bextr-"+target.name+".ll", "bextr-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86BEXTRRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "BEXTRL $1, AX, BX"}, + {goarch: "amd64", instruction: "BEXTRQ 0(AX), BX, CX"}, + {goarch: "amd64", instruction: "BEXTRQ AX, $1, CX"}, + {goarch: "amd64", instruction: "BEXTRL AX, BX, 0(CX)"}, + {goarch: "amd64", instruction: "BEXTRQ X0, AX, BX"}, + {goarch: "amd64", instruction: "BEXTRQ AX, X0, BX"}, + {goarch: "amd64", instruction: "BEXTRQ AX, BX, X0"}, + {goarch: "amd64", instruction: "BEXTRQ AX, BX"}, + {goarch: "amd64", instruction: "BEXTRQ.Z AX, BX, CX"}, + {goarch: "386", instruction: "BEXTRL R8, AX, BX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _ybextrl table", test.instruction) + } + }) + } +} + +func TestAMD64BEXTRRuntimeSemanticsAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT bextrsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + + MOVL $0x7fffffff, R8 + ADDL $1, R8 + STC + MOVL $0x0804, AX + MOVL $0x1234, BX + BEXTRL AX, BX, CX + MOVQ CX, 0(DI) + SETCS 8(DI) + SETOS 9(DI) + SETEQ 10(DI) + + MOVL $0x0120, AX + MOVL $-1, BX + BEXTRL AX, BX, CX + MOVQ CX, 16(DI) + SETEQ 24(DI) + + MOVQ $0x083c, AX + MOVQ $-1, 32(DI) + BEXTRQ AX, 32(DI), CX + MOVQ CX, 40(DI) + + MOVQ $0x0404, AX + MOVQ $0xf0, BX + BEXTRQ AX, BX, AX + MOVQ AX, 48(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "bextrsemantics": { + Name: "bextrsemantics", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void bextrsemantics(uint8_t *); +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + uint8_t out[56] = {0}; + bextrsemantics(out); + if (load64(out + 0) != UINT64_C(0x23)) return 10; + if (out[8] != 0 || out[9] != 0 || out[10] != 0) return 11; + if (load64(out + 16) != 0 || out[24] != 1) return 12; + if (load64(out + 40) != UINT64_C(0xf)) return 13; + if (load64(out + 48) != UINT64_C(0xf)) return 14; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "bextr_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_binary_float.go b/amd64_lower_binary_float.go new file mode 100644 index 00000000..bf9daa0a --- /dev/null +++ b/amd64_lower_binary_float.go @@ -0,0 +1,323 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64BinaryFloatingMode uint8 + +const ( + amd64BinaryFloatingAdd amd64BinaryFloatingMode = iota + amd64BinaryFloatingSub + amd64BinaryFloatingMul + amd64BinaryFloatingDiv + amd64BinaryFloatingMax + amd64BinaryFloatingMin + amd64BinaryFloatingSqrt + amd64BinaryFloatingScale +) + +type amd64BinaryFloatingSpec struct { + laneBits int + mode amd64BinaryFloatingMode + scalar bool + sae bool +} + +// amd64BinaryFloatingSpecs is the complete Go 1.27 V-prefixed binary +// floating-point family. Packed binary operations use _yvaddpd, while scalar +// binary operations and VSQRTSS/VSQRTSD use _yvaddsd. SCALEF uses the same +// source/destination shape through _yvscalefpd/_yvgetexpsd. MAX/MIN enable +// SAE; arithmetic, square-root, and scale operations enable explicit rounding. +var amd64BinaryFloatingSpecs = map[Op]amd64BinaryFloatingSpec{ + "VADDPS": {laneBits: 32, mode: amd64BinaryFloatingAdd}, + "VADDPD": {laneBits: 64, mode: amd64BinaryFloatingAdd}, + "VADDSS": {laneBits: 32, mode: amd64BinaryFloatingAdd, scalar: true}, + "VADDSD": {laneBits: 64, mode: amd64BinaryFloatingAdd, scalar: true}, + "VSUBPS": {laneBits: 32, mode: amd64BinaryFloatingSub}, + "VSUBPD": {laneBits: 64, mode: amd64BinaryFloatingSub}, + "VSUBSS": {laneBits: 32, mode: amd64BinaryFloatingSub, scalar: true}, + "VSUBSD": {laneBits: 64, mode: amd64BinaryFloatingSub, scalar: true}, + "VMULPS": {laneBits: 32, mode: amd64BinaryFloatingMul}, + "VMULPD": {laneBits: 64, mode: amd64BinaryFloatingMul}, + "VMULSS": {laneBits: 32, mode: amd64BinaryFloatingMul, scalar: true}, + "VMULSD": {laneBits: 64, mode: amd64BinaryFloatingMul, scalar: true}, + "VDIVPS": {laneBits: 32, mode: amd64BinaryFloatingDiv}, + "VDIVPD": {laneBits: 64, mode: amd64BinaryFloatingDiv}, + "VDIVSS": {laneBits: 32, mode: amd64BinaryFloatingDiv, scalar: true}, + "VDIVSD": {laneBits: 64, mode: amd64BinaryFloatingDiv, scalar: true}, + "VMAXPS": {laneBits: 32, mode: amd64BinaryFloatingMax, sae: true}, + "VMAXPD": {laneBits: 64, mode: amd64BinaryFloatingMax, sae: true}, + "VMAXSS": {laneBits: 32, mode: amd64BinaryFloatingMax, scalar: true, sae: true}, + "VMAXSD": {laneBits: 64, mode: amd64BinaryFloatingMax, scalar: true, sae: true}, + "VMINPS": {laneBits: 32, mode: amd64BinaryFloatingMin, sae: true}, + "VMINPD": {laneBits: 64, mode: amd64BinaryFloatingMin, sae: true}, + "VMINSS": {laneBits: 32, mode: amd64BinaryFloatingMin, scalar: true, sae: true}, + "VMINSD": {laneBits: 64, mode: amd64BinaryFloatingMin, scalar: true, sae: true}, + "VSQRTSS": {laneBits: 32, mode: amd64BinaryFloatingSqrt, scalar: true}, + "VSQRTSD": {laneBits: 64, mode: amd64BinaryFloatingSqrt, scalar: true}, + "VSCALEFPS": {laneBits: 32, mode: amd64BinaryFloatingScale}, + "VSCALEFPD": {laneBits: 64, mode: amd64BinaryFloatingScale}, + "VSCALEFSS": {laneBits: 32, mode: amd64BinaryFloatingScale, scalar: true}, + "VSCALEFSD": {laneBits: 64, mode: amd64BinaryFloatingScale, scalar: true}, +} + +type amd64BinaryFloatingSuffix struct { + broadcast bool + zeroing bool + rounding string + sae bool +} + +func parseAMD64BinaryFloatingSuffix(suffix string) (amd64BinaryFloatingSuffix, bool) { + switch suffix { + case "": + return amd64BinaryFloatingSuffix{}, true + case "Z": + return amd64BinaryFloatingSuffix{zeroing: true}, true + case "BCST": + return amd64BinaryFloatingSuffix{broadcast: true}, true + case "BCST.Z": + return amd64BinaryFloatingSuffix{broadcast: true, zeroing: true}, true + case "SAE": + return amd64BinaryFloatingSuffix{sae: true}, true + case "SAE.Z": + return amd64BinaryFloatingSuffix{sae: true, zeroing: true}, true + case "RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE": + return amd64BinaryFloatingSuffix{rounding: suffix}, true + case "RN_SAE.Z", "RD_SAE.Z", "RU_SAE.Z", "RZ_SAE.Z": + return amd64BinaryFloatingSuffix{rounding: strings.TrimSuffix(suffix, ".Z"), zeroing: true}, true + default: + return amd64BinaryFloatingSuffix{}, false + } +} + +func (c *amd64Ctx) lowerBinaryFloating(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64BinaryFloatingSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix { + return true, false, fmt.Errorf("%s %s has a suffix absent from Go 1.27's binary floating optab: %q", c.goarch, baseOp, ins.Raw) + } + if spec.scalar && properties.broadcast { + return true, false, fmt.Errorf("%s %s scalar forms do not support broadcast: %q", c.goarch, baseOp, ins.Raw) + } + if spec.sae { + if properties.rounding != "" { + return true, false, fmt.Errorf("%s %s supports SAE, not explicit rounding: %q", c.goarch, baseOp, ins.Raw) + } + } else if properties.sae { + return true, false, fmt.Errorf("%s %s supports explicit rounding, not SAE: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects src1, src2, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed Go 1.27's assembler operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be a vector register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if spec.scalar { + if byteWidth != 16 { + return true, false, fmt.Errorf("%s %s scalar destination must be an X register: %q", c.goarch, baseOp, ins.Raw) + } + } else if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s packed destination must be an X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoEVEXVectorRegister(destination, byteWidth) || !c.isGoEVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s second source and destination must be same-width Go 1.27 vector registers: %q", c.goarch, baseOp, ins.Raw) + } + if (properties.rounding != "" || properties.sae) && !spec.scalar && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s packed rounding/SAE is available only for Z registers: %q", c.goarch, baseOp, ins.Raw) + } + if properties.broadcast { + if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory first source: %q", c.goarch, baseOp, ins.Raw) + } + } else if ins.Args[0].Kind == OpReg { + if !c.isGoEVEXVectorRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match the destination width and register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if properties.rounding != "" || properties.sae { + return true, false, fmt.Errorf("%s %s explicit rounding/SAE requires a register first source: %q", c.goarch, baseOp, ins.Raw) + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + loadedMask, loadErr := c.loadK(ins.Args[2].Reg) + if loadErr != nil { + return true, false, loadErr + } + mask = loadedMask + } + if spec.scalar { + return c.lowerScalarBinaryFloating(spec, properties, ins, destination, mask) + } + return c.lowerPackedBinaryFloating(spec, properties, ins, destination, byteWidth, mask) +} + +func (c *amd64Ctx) lowerPackedBinaryFloating(spec amd64BinaryFloatingSpec, properties amd64BinaryFloatingSuffix, ins Instr, destination Operand, byteWidth int, mask string) (bool, bool, error) { + if spec.mode == amd64BinaryFloatingScale { + return c.lowerPackedScaleF(spec, properties, ins.Args[0], ins.Args[1], destination, byteWidth, mask) + } + lanes := byteWidth * 8 / spec.laneBits + llvmType := amd64FMA3LLVMType(lanes, spec.laneBits) + load := func(operand Operand, allowBroadcast bool) (string, error) { + if allowBroadcast && properties.broadcast { + var scalar string + var err error + if spec.laneBits == 32 { + scalar, err = c.evalF32(operand) + } else { + scalar, err = c.evalF64(operand) + } + if err != nil { + return "", err + } + return c.splatFMA3Scalar(lanes, spec.laneBits, scalar), nil + } + bytesValue, err := c.loadPackedCompareBytes(operand, byteWidth) + if err != nil { + return "", err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", value, byteWidth, bytesValue, llvmType) + return "%" + value, nil + } + first, err := load(ins.Args[0], true) + if err != nil { + return true, false, err + } + second, err := load(ins.Args[1], false) + if err != nil { + return true, false, err + } + computed := c.emitBinaryFloating(spec, llvmType, lanes, second, first, properties.rounding) + if mask != "" { + computedBits := c.bitcastFloatingToIntegerLanes(llvmType, lanes, spec.laneBits, computed) + oldBytes, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + oldBits := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + masked := amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, computedBits, oldBits, mask, properties.zeroing) + back := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to %s\n", back, lanes, spec.laneBits, masked, llvmType) + computed = "%" + back + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", out, llvmType, computed, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) lowerScalarBinaryFloating(spec amd64BinaryFloatingSpec, properties amd64BinaryFloatingSuffix, ins Instr, destination Operand, mask string) (bool, bool, error) { + if spec.mode == amd64BinaryFloatingScale { + return c.lowerScalarScaleF(spec, properties, ins.Args[0], ins.Args[1], destination, mask) + } + var first, second string + var err error + if spec.laneBits == 32 { + first, err = c.evalF32(ins.Args[0]) + if err == nil { + second, err = c.loadXLowF32(ins.Args[1].Reg) + } + } else { + first, err = c.evalF64(ins.Args[0]) + if err == nil { + second, err = c.loadXLowF64(ins.Args[1].Reg) + } + } + if err != nil { + return true, false, err + } + llvmType := amd64FMA3LLVMType(1, spec.laneBits) + computed := c.emitBinaryFloating(spec, llvmType, 1, second, first, properties.rounding) + computedBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to i%d\n", computedBits, llvmType, computed, spec.laneBits) + secondBytes, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + base := c.bitcastVectorBytesToIntegerLanes(16, 128/spec.laneBits, spec.laneBits, secondBytes) + return true, false, c.storeVectorScalarRegister(destination.Reg, spec.laneBits, "%"+computedBits, base, mask, properties.zeroing) +} + +func (c *amd64Ctx) emitBinaryFloating(spec amd64BinaryFloatingSpec, llvmType string, lanes int, left, right, rounding string) string { + result := c.newTmp() + switch spec.mode { + case amd64BinaryFloatingSqrt: + if rounding == "" { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.sqrt.%s(%s %s)\n", result, llvmType, amd64BinaryFloatingIntrinsicSuffix(lanes, spec.laneBits), llvmType, right) + } else { + intrinsic := fmt.Sprintf("llvm.experimental.constrained.sqrt.%s", amd64BinaryFloatingIntrinsicSuffix(lanes, spec.laneBits)) + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %s, metadata !\"%s\", metadata !\"fpexcept.ignore\")\n", result, llvmType, intrinsic, llvmType, right, amd64FMA3RoundingMetadata(rounding)) + } + case amd64BinaryFloatingMax, amd64BinaryFloatingMin: + predicate := "ogt" + if spec.mode == amd64BinaryFloatingMin { + predicate = "olt" + } + comparison := c.newTmp() + predicateType := "i1" + if lanes > 1 { + predicateType = fmt.Sprintf("<%d x i1>", lanes) + } + fmt.Fprintf(c.b, " %%%s = fcmp %s %s %s, %s\n", comparison, predicate, llvmType, left, right) + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %s, %s %s\n", result, predicateType, comparison, llvmType, left, llvmType, right) + default: + operation := "fadd" + switch spec.mode { + case amd64BinaryFloatingSub: + operation = "fsub" + case amd64BinaryFloatingMul: + operation = "fmul" + case amd64BinaryFloatingDiv: + operation = "fdiv" + } + if rounding == "" { + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", result, operation, llvmType, left, right) + } else { + intrinsic := fmt.Sprintf("llvm.experimental.constrained.%s.%s", operation, amd64BinaryFloatingIntrinsicSuffix(lanes, spec.laneBits)) + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %s, %s %s, metadata !\"%s\", metadata !\"fpexcept.ignore\")\n", result, llvmType, intrinsic, llvmType, left, llvmType, right, amd64FMA3RoundingMetadata(rounding)) + } + } + return "%" + result +} + +func (c *amd64Ctx) bitcastFloatingToIntegerLanes(llvmType string, lanes, laneBits int, value string) string { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i%d>\n", result, llvmType, value, lanes, laneBits) + return "%" + result +} + +func amd64BinaryFloatingIntrinsicSuffix(lanes, laneBits int) string { + suffix := "f32" + if laneBits == 64 { + suffix = "f64" + } + if lanes > 1 { + return fmt.Sprintf("v%d%s", lanes, suffix) + } + return suffix +} diff --git a/amd64_lower_bittest.go b/amd64_lower_bittest.go new file mode 100644 index 00000000..1085fb8f --- /dev/null +++ b/amd64_lower_bittest.go @@ -0,0 +1,202 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerBitTestFamily implements the complete Go 1.27 ybtl table. BTW/L/Q, +// BTCW/L/Q, BTRW/L/Q, and BTSW/L/Q all accept exactly either a signed imm8 or +// a Yrl register bit index followed by a Yml register/memory destination. +func (c *amd64Ctx) lowerBitTestFamily(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + stem, bits, recognized := amd64BitTestProperties(baseOp) + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects bit index and destination: %q", c.goarch, baseOp, ins.Raw) + } + + indexOperand := ins.Args[0] + if indexOperand.Kind == OpImm { + if indexOperand.Imm < -128 || indexOperand.Imm > 127 { + return true, false, fmt.Errorf("%s %s index is outside Go 1.27's signed-imm8 class: %q", c.goarch, baseOp, ins.Raw) + } + } else if indexOperand.Kind != OpReg || !isX86YrlRegisterForArch(indexOperand.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s index is outside Go 1.27's Yi8/Yrl classes: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[1] + if destination.Kind == OpReg { + if !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yml class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yml class: %q", c.goarch, baseOp, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + bitIndex, memoryWordOffset, registerIndex, err := c.bitTestIndex(indexOperand, bits, typ) + if err != nil { + return true, false, err + } + value, store, err := c.loadBitTestDestination(destination, typ, memoryWordOffset, registerIndex) + if err != nil { + return true, false, err + } + + shifted := c.newTmp() + bit := c.newTmp() + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %s\n", shifted, typ, value, bitIndex) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, 1\n", bit, typ, shifted) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, 0\n", carry, typ, bit) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carry, c.flagsCFSlot) + if stem == "BT" { + return true, false, nil + } + + bitMask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl %s 1, %s\n", bitMask, typ, bitIndex) + result := c.newTmp() + switch stem { + case "BTC": + fmt.Fprintf(c.b, " %%%s = xor %s %s, %%%s\n", result, typ, value, bitMask) + case "BTR": + inverseMask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %%%s, -1\n", inverseMask, typ, bitMask) + fmt.Fprintf(c.b, " %%%s = and %s %s, %%%s\n", result, typ, value, inverseMask) + case "BTS": + fmt.Fprintf(c.b, " %%%s = or %s %s, %%%s\n", result, typ, value, bitMask) + } + return true, false, store("%" + result) +} + +func amd64BitTestProperties(op string) (stem string, bits int, ok bool) { + switch op { + case "BTW": + return "BT", 16, true + case "BTL": + return "BT", 32, true + case "BTQ": + return "BT", 64, true + case "BTCW": + return "BTC", 16, true + case "BTCL": + return "BTC", 32, true + case "BTCQ": + return "BTC", 64, true + case "BTRW": + return "BTR", 16, true + case "BTRL": + return "BTR", 32, true + case "BTRQ": + return "BTR", 64, true + case "BTSW": + return "BTS", 16, true + case "BTSL": + return "BTS", 32, true + case "BTSQ": + return "BTS", 64, true + } + return "", 0, false +} + +// bitTestIndex returns the within-word index and, for a register index, the +// signed byte offset used when a memory destination is treated as an unbounded +// bit string. The index register has the same width as the instruction. +func (c *amd64Ctx) bitTestIndex(index Operand, bits int, typ LLVMType) (bitIndex, memoryWordOffset string, registerIndex bool, err error) { + if index.Kind == OpImm { + return fmt.Sprintf("%d", index.Imm&int64(bits-1)), "", false, nil + } + value, err := c.evalIntSized(index, typ) + if err != nil { + return "", "", false, err + } + withinWord := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %d\n", withinWord, typ, value, bits-1) + bitIndex = "%" + withinWord + + signedIndex := value + if bits != 64 { + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext %s %s to i64\n", extended, typ, value) + signedIndex = "%" + extended + } + wordIndex := c.newTmp() + byteOffset := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ashr i64 %s, %d\n", wordIndex, signedIndex, bitTestLog2(bits)) + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %d\n", byteOffset, wordIndex, bits/8) + return bitIndex, "%" + byteOffset, true, nil +} + +func bitTestLog2(bits int) int { + switch bits { + case 16: + return 4 + case 32: + return 5 + default: + return 6 + } +} + +func (c *amd64Ctx) loadBitTestDestination(destination Operand, typ LLVMType, memoryWordOffset string, registerIndex bool) (string, func(string) error, error) { + if !registerIndex || destination.Kind == OpReg || destination.Kind == OpFP { + return c.loadIntDestination(destination, typ) + } + + var address string + var addressSpace int + switch destination.Kind { + case OpMem: + var err error + address, err = c.addrFromPlainMem(destination.Mem) + if err != nil { + return "", nil, err + } + switch destination.Mem.Segment { + case "": + case GS: + addressSpace = 256 + case FS: + addressSpace = 257 + default: + return "", nil, fmt.Errorf("unsupported x86 segment register %s", destination.Mem.Segment) + } + case OpSym: + pointer, err := c.ptrFromSB(destination.Sym) + if err != nil { + return "", nil, err + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %s to i64\n", converted, pointer) + address = "%" + converted + default: + return "", nil, fmt.Errorf("expected register or memory destination, got %s", destination.String()) + } + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", adjusted, address, memoryWordOffset) + pointer := c.newTmp() + pointerType := "ptr" + if addressSpace != 0 { + pointerType = fmt.Sprintf("ptr addrspace(%d)", addressSpace) + } + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %%%s to %s\n", pointer, adjusted, pointerType) + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, %s %%%s, align 1\n", loaded, typ, pointerType, pointer) + return "%" + loaded, func(value string) error { + fmt.Fprintf(c.b, " store %s %s, %s %%%s, align 1\n", typ, value, pointerType, pointer) + return nil + }, nil +} diff --git a/amd64_lower_blend_imm.go b/amd64_lower_blend_imm.go new file mode 100644 index 00000000..634e8c36 --- /dev/null +++ b/amd64_lower_blend_imm.go @@ -0,0 +1,143 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerImmediatePackedBlend implements the complete Go 1.27 immediate +// packed-blend family. The legacy instructions use yxshuf, while all four +// V-prefixed instructions use _yvblendpd and therefore have VEX X/Y forms +// only (no EVEX Z, mask, zeroing, broadcast, or SAE forms). +func (c *amd64Ctx) lowerImmediatePackedBlend(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits, vector, recognized := amd64ImmediatePackedBlendProperties(baseOp) + if !recognized { + return false, false, nil + } + if suffix != "" { + return true, false, fmt.Errorf("%s %s has a suffix absent from its Go 1.27 optab: %q", c.goarch, baseOp, ins.Raw) + } + if !vector { + return c.lowerLegacyImmediatePackedBlend(baseOp, laneBits, ins) + } + return c.lowerVectorImmediatePackedBlend(baseOp, laneBits, ins) +} + +func amd64ImmediatePackedBlendProperties(op string) (laneBits int, vector, ok bool) { + switch op { + case "PBLENDW": + return 16, false, true + case "BLENDPS": + return 32, false, true + case "BLENDPD": + return 64, false, true + case "VPBLENDW": + return 16, true, true + case "VPBLENDD", "VBLENDPS": + return 32, true, true + case "VBLENDPD": + return 64, true, true + default: + return 0, false, false + } +} + +func (c *amd64Ctx) lowerLegacyImmediatePackedBlend(baseOp string, laneBits int, ins Instr) (bool, bool, error) { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects $u8, X/m128, X: %q", c.goarch, baseOp, ins.Raw) + } + imm, ok := amd64UnsignedImm8(ins.Args[0]) + if !ok { + return true, false, fmt.Errorf("%s %s immediate is outside Go 1.27's unsigned-imm8 class: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[2].Kind != OpReg || !c.isGoLegacyXReg(ins.Args[2].Reg) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[1].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s source must be X or memory: %q", c.goarch, baseOp, ins.Raw) + } + firstBytes, err := c.loadPackedCompareBytes(ins.Args[1], 16) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + result := c.emitImmediatePackedBlend(16, laneBits, imm, firstBytes, secondBytes) + return true, false, c.storeX(ins.Args[2].Reg, result) +} + +func (c *amd64Ctx) lowerVectorImmediatePackedBlend(baseOp string, laneBits int, ins Instr) (bool, bool, error) { + if c.goarch != "amd64" { + return true, false, fmt.Errorf("386 %s exceeds the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 %s expects $u8, X/Y memory-or-register, X/Y register, X/Y destination: %q", baseOp, ins.Raw) + } + imm, ok := amd64UnsignedImm8(ins.Args[0]) + if !ok { + return true, false, fmt.Errorf("amd64 %s immediate is outside Go 1.27's unsigned-imm8 class: %q", baseOp, ins.Raw) + } + dstArg := ins.Args[3] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects a vector-register destination: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth != 16 && byteWidth != 32 { + return true, false, fmt.Errorf("amd64 %s expects an X or Y destination: %q", baseOp, ins.Raw) + } + if !amd64VEXVectorRegister(dstArg, byteWidth) || !amd64VEXVectorRegister(ins.Args[2], byteWidth) { + return true, false, fmt.Errorf("amd64 %s second source and destination must be same-width VEX X/Y registers: %q", baseOp, ins.Raw) + } + if ins.Args[1].Kind == OpReg { + if !amd64VEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("amd64 %s first source must match its destination's VEX width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s first source must be a vector register or memory: %q", baseOp, ins.Raw) + } + firstBytes, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[2], byteWidth) + if err != nil { + return true, false, err + } + result := c.emitImmediatePackedBlend(byteWidth, laneBits, imm, firstBytes, secondBytes) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, result) +} + +// emitImmediatePackedBlend selects the first (r/m) source when the immediate +// bit is one and the second source when it is zero. VPBLENDW repeats the eight +// immediate bits independently in each 128-bit lane of a Y register. +func (c *amd64Ctx) emitImmediatePackedBlend(byteWidth, laneBits int, imm uint8, firstBytes, secondBytes string) string { + lanes := byteWidth * 8 / laneBits + first := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, secondBytes) + mask := make([]string, 0, lanes) + for lane := 0; lane < lanes; lane++ { + if imm&(1< %s, <%d x i%d> %s, <%d x i32> <%s>\n", + shuffled, lanes, laneBits, first, lanes, laneBits, second, lanes, strings.Join(mask, ", ")) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <%d x i8>\n", out, lanes, laneBits, shuffled, byteWidth) + return "%" + out +} diff --git a/amd64_lower_blend_mask.go b/amd64_lower_blend_mask.go new file mode 100644 index 00000000..31c0fda5 --- /dev/null +++ b/amd64_lower_blend_mask.go @@ -0,0 +1,111 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64MaskBlendSpec struct { + laneBits int + broadcast bool +} + +// amd64MaskBlendSpecs is the complete shared _yvblendmpd grammar for the +// floating-point and integer mask-blend families. +var amd64MaskBlendSpecs = map[Op]amd64MaskBlendSpec{ + "VBLENDMPS": {laneBits: 32, broadcast: true}, + "VBLENDMPD": {laneBits: 64, broadcast: true}, + "VPBLENDMB": {laneBits: 8}, + "VPBLENDMW": {laneBits: 16}, + "VPBLENDMD": {laneBits: 32, broadcast: true}, + "VPBLENDMQ": {laneBits: 64, broadcast: true}, +} + +// lowerMaskBlend implements Go 1.27's complete _yvblendmpd operand table for +// VBLENDM{PS,PD} and VPBLENDM{B,W,D,Q}. A set K bit selects the first Plan 9 +// (Intel r/m) source; an unset bit selects the second source, or zero for .Z. +func (c *amd64Ctx) lowerMaskBlend(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, ok := amd64MaskBlendSpecs[Op(baseOp)] + if !ok { + return false, false, nil + } + suffixes, err := amd64ParseTwoSourcePermuteSuffixes(rawOp, baseOp) + if err != nil { + return true, false, fmt.Errorf("%w: %q", err, ins.Raw) + } + if suffixes.broadcast && !spec.broadcast { + return true, false, fmt.Errorf("amd64 %s does not enable broadcast in Go 1.27: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 %s expects first source, second source, [K mask,] destination: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if masked && c.goarch == "386" { + return true, false, fmt.Errorf("386 %s masked form exceeds the Go assembler frontend's operand limit: %q", baseOp, ins.Raw) + } + if suffixes.zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + byteWidth := 0 + if destination.Kind == OpReg { + byteWidth = amd64VectorByteWidth(destination.Reg) + } + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s expects an in-range X, Y, or Z destination: %q", baseOp, ins.Raw) + } + second := ins.Args[1] + if !c.isGoPackedVectorMoveRegister(second, byteWidth) { + return true, false, fmt.Errorf("amd64 %s second source must match the destination width: %q", baseOp, ins.Raw) + } + first := ins.Args[0] + if first.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(first, byteWidth) { + return true, false, fmt.Errorf("amd64 %s first source register must match the destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 %s first source must be a matching vector register or memory: %q", baseOp, ins.Raw) + } + if suffixes.broadcast && !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory first source: %q", baseOp, ins.Raw) + } + + firstValue, err := c.loadPackedCompareLanes(first, byteWidth, spec.laneBits, suffixes.broadcast) + if err != nil { + return true, false, err + } + if !masked { + out := c.newTmp() + lanes := byteWidth * 8 / spec.laneBits + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, firstValue, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) + } + + maskArg := ins.Args[2] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, validMask := amd64ParseKReg(maskArg.Reg) + if !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err := c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + secondValue, err := c.loadPackedCompareLanes(second, byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / spec.laneBits + result := amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, firstValue, secondValue, mask, suffixes.zeroing) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} diff --git a/amd64_lower_blend_mask_test.go b/amd64_lower_blend_mask_test.go new file mode 100644 index 00000000..db5ae7e5 --- /dev/null +++ b/amd64_lower_blend_mask_test.go @@ -0,0 +1,233 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64MaskBlendGrammarCoversCompleteGoFamilies(t *testing.T) { + expected := map[Op]amd64MaskBlendSpec{ + "VBLENDMPS": {laneBits: 32, broadcast: true}, + "VBLENDMPD": {laneBits: 64, broadcast: true}, + "VPBLENDMB": {laneBits: 8}, + "VPBLENDMW": {laneBits: 16}, + "VPBLENDMD": {laneBits: 32, broadcast: true}, + "VPBLENDMQ": {laneBits: 64, broadcast: true}, + } + if len(amd64MaskBlendSpecs) != len(expected) { + t.Fatalf("mask-blend grammar has %d entries, want %d", len(amd64MaskBlendSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64MaskBlendSpecs[op]; !ok { + t.Errorf("mask-blend grammar omitted %s", op) + } else if got != want { + t.Errorf("mask-blend grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86MaskBlendCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 shares _yvblendmpd across VBLENDM{PS,PD} and + // VPBLENDM{B,W,D,Q}: matching X/Y/Z sources and destination, optional + // K1-K7 selection mask, and .Z. PS/PD/D/Q additionally enable + // scalar-memory broadcast on the first Plan 9 source. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastZ := 20 + if target.goarch == "386" { + lastZ = 7 + } + var source strings.Builder + source.WriteString("TEXT maskblendforms(SB),$0-0\n") + for _, family := range []struct { + op string + broadcast bool + }{ + {op: "VBLENDMPS", broadcast: true}, + {op: "VBLENDMPD", broadcast: true}, + {op: "VPBLENDMB"}, + {op: "VPBLENDMW"}, + {op: "VPBLENDMD", broadcast: true}, + {op: "VPBLENDMQ", broadcast: true}, + } { + op := family.op + fmt.Fprintf(&source, "\t%s X1, X20, X21\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), Y20, Y21\n", op) + fmt.Fprintf(&source, "\t%s Z1, Z2, Z%d\n", op, lastZ) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s X1, X20, K1, X21\n", op) + fmt.Fprintf(&source, "\t%s.Z Y1, Y20, K2, Y21\n", op) + fmt.Fprintf(&source, "\t%s.Z 40(AX), Z20, K3, Z21\n", op) + } + if family.broadcast { + fmt.Fprintf(&source, "\t%s.BCST 104(AX), X20, X21\n", op) + fmt.Fprintf(&source, "\t%s.BCST 112(AX), Y20, Y21\n", op) + fmt.Fprintf(&source, "\t%s.BCST 120(AX), Z2, Z%d\n", op, lastZ) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.BCST.Z 128(AX), Z20, K4, Z21\n", op) + } + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"maskblendforms": {Name: "maskblendforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "mask-blend-"+target.name+".ll", "mask-blend-"+target.name+".o", ll) + }) + } +} + +func TestAMD64FloatingMaskBlendRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT floatingmaskblendsemantics(SB),$0-32 + MOVQ out+0(FP), AX + MOVQ first+8(FP), BX + MOVQ second+16(FP), CX + MOVQ mask+24(FP), DX + KMOVQ DX, K1 + VMOVDQU64 0(BX), Z0 + VMOVDQU64 0(CX), Z1 + VBLENDMPS Z0, Z1, K1, Z2 + VMOVDQU64 Z2, 0(AX) + VBLENDMPD.Z Z0, Z1, K1, Z2 + VMOVDQU64 Z2, 64(AX) + VBLENDMPS.BCST 0(BX), Z1, K1, Z2 + VMOVDQU64 Z2, 128(AX) + VBLENDMPD.BCST.Z 0(BX), Z1, K1, Z2 + VMOVDQU64 Z2, 192(AX) + STC + VBLENDMPS Z0, Z1, K1, Z2 + SETCS 256(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"floatingmaskblendsemantics": { + Name: "floatingmaskblendsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: I64, Index: 3, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void floatingmaskblendsemantics(uint8_t *, const uint8_t *, const uint8_t *, uint64_t); +int main(void) { + uint32_t first32[16], second32[16]; uint8_t out[257] = {0}; + const uint64_t mask = UINT64_C(0xa55a); + for (int i=0;i<16;i++) { first32[i]=UINT32_C(0x7f000000)+i; second32[i]=UINT32_C(0x3f000000)+i; } + floatingmaskblendsemantics(out,(const uint8_t *)first32,(const uint8_t *)second32,mask); + uint32_t *ps=(uint32_t *)(out+0), *psbcst=(uint32_t *)(out+128); + for (int i=0;i<16;i++) { + uint32_t want=(mask>>i)&1 ? first32[i] : second32[i]; if (ps[i]!=want) return 10+i; + want=(mask>>i)&1 ? first32[0] : second32[i]; if (psbcst[i]!=want) return 30+i; + } + uint64_t first64[8], second64[8], pdzero[8], pdbczero[8]; + memcpy(first64,first32,64); memcpy(second64,second32,64); + memcpy(pdzero,out+64,64); memcpy(pdbczero,out+192,64); + for (int i=0;i<8;i++) { + uint64_t want=(mask>>i)&1 ? first64[i] : 0; if (pdzero[i]!=want) return 50+i; + want=(mask>>i)&1 ? first64[0] : 0; if (pdbczero[i]!=want) return 70+i; + } + if (out[256]!=1) return 90; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "floating_mask_blend_semantics", triple, ir, mainC, runPrefix) +} + +func TestTranslateX86MaskBlendRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VBLENDMPS X0, Y1, Y2", + "VBLENDMPD X0, X1, K0, X2", + "VBLENDMPS.BCST X0, X1, X2", + "VBLENDMPD.RN_SAE X0, X1, X2", + "VPBLENDMQ X0, X1", + "VPBLENDMQ X0, Y1, Y2", + "VPBLENDMQ X0, (AX), X2", + "VPBLENDMQ X0, X1, K0, X2", + "VPBLENDMQ X0, X1, AX", + "VPBLENDMQ.Z X0, X1, X2", + "VPBLENDMQ.BCST X0, X1, X2", + "VPBLENDMB.BCST (AX), X1, X2", + "VPBLENDMW.BCST (AX), X1, X2", + "VPBLENDMQ.Z.BCST (AX), X1, K1, X2", + "VPBLENDMQ.RN_SAE X0, X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + requireX86GoAssemblerResult(t, "amd64", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + assertX86MaskBlendRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + requireX86GoAssemblerResult(t, "386", "TEXT bad(SB),$0-0\n\tVPBLENDMQ X0, X1, K1, X2\n\tRET\n", false) + assertX86MaskBlendRejected(t, "386", "i386-unknown-linux-gnu", "VPBLENDMQ X0, X1, K1, X2") + requireX86GoAssemblerResult(t, "386", "TEXT bad(SB),$0-0\n\tVPBLENDMQ Z0, Z1, Z8\n\tRET\n", false) + assertX86MaskBlendRejected(t, "386", "i386-unknown-linux-gnu", "VPBLENDMQ Z0, Z1, Z8") +} + +func assertX86MaskBlendRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VPBLENDM forms", instruction) + } +} diff --git a/amd64_lower_blend_variable.go b/amd64_lower_blend_variable.go new file mode 100644 index 00000000..144bc208 --- /dev/null +++ b/amd64_lower_blend_variable.go @@ -0,0 +1,104 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerVariableBlend implements Go 1.27's complete yblendvpd and _yvblendvpd +// families. Each opcode tests the high bit of its mask lane: false selects the +// base/destination lane and true selects the register-or-memory source lane. +func (c *amd64Ctx) lowerVariableBlend(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + laneBits := 0 + vectorForm := false + switch baseOp { + case "BLENDVPS": + laneBits = 32 + case "BLENDVPD": + laneBits = 64 + case "PBLENDVB": + laneBits = 8 + case "VBLENDVPS": + laneBits, vectorForm = 32, true + case "VBLENDVPD": + laneBits, vectorForm = 64, true + case "VPBLENDVB": + laneBits, vectorForm = 8, true + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + wantArgs := 3 + if vectorForm { + wantArgs = 4 + } + if len(ins.Args) != wantArgs { + return true, false, fmt.Errorf("amd64 %s expects mask, source, %s: %q", baseOp, map[bool]string{false: "X destination", true: "base, destination"}[vectorForm], ins.Raw) + } + + maskArg, source := ins.Args[0], ins.Args[1] + base, destination := ins.Args[2], ins.Args[2] + if vectorForm { + destination = ins.Args[3] + } + if maskArg.Kind != OpReg || base.Kind != OpReg || destination.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects vector mask/base/destination registers: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(base.Reg) + if !vectorForm { + if maskArg.Reg != Reg("X0") || byteWidth != 16 || destination.Reg != base.Reg || !c.isGoLegacyXReg(base.Reg) { + return true, false, fmt.Errorf("%s %s expects implicit X0 mask and an in-range X destination: %q", c.goarch, baseOp, ins.Raw) + } + } else { + if byteWidth != 16 && byteWidth != 32 { + return true, false, fmt.Errorf("amd64 %s only accepts X or Y forms: %q", baseOp, ins.Raw) + } + if !amd64VEXVectorRegister(maskArg, byteWidth) || !amd64VEXVectorRegister(base, byteWidth) || !amd64VEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s operands must be same-width VEX registers: %q", baseOp, ins.Raw) + } + } + if source.Kind == OpReg { + valid := false + if vectorForm { + valid = amd64VEXVectorRegister(source, byteWidth) + } else { + valid = c.isGoLegacyXReg(source.Reg) + } + if !valid { + return true, false, fmt.Errorf("%s %s source register has the wrong width or range: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s source must be a same-width vector register or memory: %q", baseOp, ins.Raw) + } + + maskBytes, err := c.loadPackedCompareBytes(maskArg, byteWidth) + if err != nil { + return true, false, err + } + sourceBytes, err := c.loadPackedCompareBytes(source, byteWidth) + if err != nil { + return true, false, err + } + baseBytes, err := c.loadPackedCompareBytes(base, byteWidth) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / laneBits + maskLanes := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, maskBytes) + sourceLanes := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, sourceBytes) + baseLanes := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, baseBytes) + selectedMask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt <%d x i%d> %s, zeroinitializer\n", selectedMask, lanes, laneBits, maskLanes) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, <%d x i%d> %s, <%d x i%d> %s\n", result, lanes, selectedMask, lanes, laneBits, sourceLanes, lanes, laneBits, baseLanes) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} diff --git a/amd64_lower_blend_variable_test.go b/amd64_lower_blend_variable_test.go new file mode 100644 index 00000000..541be136 --- /dev/null +++ b/amd64_lower_blend_variable_test.go @@ -0,0 +1,105 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86VariableBlendCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's yblendvpd and _yvblendvpd tables are shared by the + // PS (dword lanes), PD (qword lanes), and PBLENDVB (byte lanes) variants. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast := 15 + if target.goarch == "386" { + legacyLast = 7 + } + var src strings.Builder + src.WriteString("TEXT variableblendforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"BLENDVPS", "BLENDVPD", "PBLENDVB"} { + fmt.Fprintf(&src, "\t%s X0, (AX), X1\n", op) + fmt.Fprintf(&src, "\t%s X0, X2, X%d\n", op, legacyLast) + } + for _, op := range []string{"VBLENDVPS", "VBLENDVPD", "VPBLENDVB"} { + fmt.Fprintf(&src, "\t%s X0, (AX), X1, X2\n", op) + fmt.Fprintf(&src, "\t%s X12, X13, X14, X15\n", op) + fmt.Fprintf(&src, "\t%s Y0, 32(AX), Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s Y12, Y13, Y14, Y15\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "variableblendforms": {Name: "variableblendforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "variable-blend-"+target.name+".ll", "variable-blend-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86VariableBlendRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "BLENDVPS X1, X2, X3", + "BLENDVPD X0, Y1, X2", + "PBLENDVB X0, X1, Y2", + "BLENDVPS.Z X0, X1, X2", + "VBLENDVPS X0, X1, X2", + "VBLENDVPD X0, X1, X2, X3, X4", + "VPBLENDVB (AX), X1, X2, X3", + "VBLENDVPS X0, Y1, X2, X3", + "VBLENDVPD Y0, Y1, X2, Y3", + "VPBLENDVB Y0, Y1, Y2, X3", + "VBLENDVPS.Z X0, X1, X2, X3", + "VBLENDVPD X16, X1, X2, X3", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86VariableBlendRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "BLENDVPS X0, X8, X1", + "BLENDVPD X0, X1, X8", + "PBLENDVB X8, X1, X2", + } { + assertX86VariableBlendRejected(t, "386", "i386-unknown-linux-gnu", instruction) + } +} + +func assertX86VariableBlendRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's variable blend tables", instruction) + } +} diff --git a/amd64_lower_bls.go b/amd64_lower_bls.go new file mode 100644 index 00000000..58f957b5 --- /dev/null +++ b/amd64_lower_bls.go @@ -0,0 +1,90 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerLowestSetBitManipulation implements Go 1.27's complete _yblsil table: +// BLSI, BLSMSK, and BLSR at L/Q widths, with a Yml register-or-memory source +// and a Yrl destination register. +func (c *amd64Ctx) lowerLowestSetBitManipulation(op Op, ins Instr) (ok bool, terminated bool, err error) { + name := strings.ToUpper(string(op)) + family := "" + bits := 0 + switch name { + case "BLSIL": + family, bits = "BLSI", 32 + case "BLSIQ": + family, bits = "BLSI", 64 + case "BLSMSKL": + family, bits = "BLSMSK", 32 + case "BLSMSKQ": + family, bits = "BLSMSK", 64 + case "BLSRL": + family, bits = "BLSR", 32 + case "BLSRQ": + family, bits = "BLSR", 64 + default: + return false, false, nil + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects source, destination register: %q", c.goarch, name, ins.Raw) + } + source, destination := ins.Args[0], ins.Args[1] + if source.Kind == OpReg { + if !isX86YrlRegisterForArch(source.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, name, ins.Raw) + } + } else if source.Kind == OpSym && strings.HasPrefix(strings.TrimSpace(source.Sym), "$") || !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, name, ins.Raw) + } + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yrl class: %q", c.goarch, name, ins.Raw) + } + + // VEX.W is ignored for this family in 32-bit mode. Go 1.27 therefore + // accepts the Q spellings for 386 and emits the same 32-bit operation. + typ := I32 + if bits == 64 && c.goarch != "386" { + typ = I64 + } + value, err := c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + minusOne := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s %s, 1\n", minusOne, typ, value) + result := c.newTmp() + carry := "" + switch family { + case "BLSI": + negative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s 0, %s\n", negative, typ, value) + fmt.Fprintf(c.b, " %%%s = and %s %s, %%%s\n", result, typ, value, negative) + carry = c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne %s %s, 0\n", carry, typ, value) + case "BLSMSK": + fmt.Fprintf(c.b, " %%%s = xor %s %s, %%%s\n", result, typ, value, minusOne) + carry = c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, 0\n", carry, typ, value) + case "BLSR": + fmt.Fprintf(c.b, " %%%s = and %s %s, %%%s\n", result, typ, value, minusOne) + carry = c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, 0\n", carry, typ, value) + } + + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carry, c.flagsCFSlot) + if family == "BLSMSK" { + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsZSlot) + } else { + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, 0\n", zero, typ, result) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + } + sign := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt %s %%%s, 0\n", sign, typ, result) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", sign, c.flagsSltSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + return true, false, c.storeRegSized(destination.Reg, typ, "%"+result) +} diff --git a/amd64_lower_bls_test.go b/amd64_lower_bls_test.go new file mode 100644 index 00000000..3391f975 --- /dev/null +++ b/amd64_lower_bls_test.go @@ -0,0 +1,376 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestX86RawBLSMSKReportedEncoding(t *testing.T) { + const source = `TEXT rawBLSMSK(SB), NOSPLIT, $0-0 + BYTE $0xc4 + BYTE $0xe2 + BYTE $0x88 + BYTE $0xf3 + BYTE $0xd2 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"rawBLSMSK": {Name: "rawBLSMSK", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, `"target-features"="+bmi"`) { + t.Fatalf("raw BLSMSK did not infer BMI1 target feature:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "raw-blsmsk-reported.ll", "raw-blsmsk-reported.o", ir) +} + +func TestTranslateX86BLSCompleteGoAssemblerForms(t *testing.T) { + registers386 := []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"} + registersAMD64 := append(append([]string{}, registers386...), "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15") + targets := []struct { + name string + goarch string + triple string + widths []string + registers []string + }{ + {name: "386-linux", goarch: "386", triple: "i386-unknown-linux-gnu", widths: []string{"L", "Q"}, registers: registers386}, + {name: "386-windows", goarch: "386", triple: "i686-pc-windows-msvc", widths: []string{"L", "Q"}, registers: registers386}, + {name: "amd64-darwin", goarch: "amd64", triple: "x86_64-apple-darwin", widths: []string{"L", "Q"}, registers: registersAMD64}, + {name: "amd64-linux", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", widths: []string{"L", "Q"}, registers: registersAMD64}, + {name: "amd64-windows", goarch: "amd64", triple: "x86_64-pc-windows-msvc", widths: []string{"L", "Q"}, registers: registersAMD64}, + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range targets { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT blsforms(SB),$0-0\n") + for _, family := range []string{"BLSI", "BLSMSK", "BLSR"} { + for _, width := range target.widths { + op := family + width + for index, register := range target.registers { + other := target.registers[(index+5)%len(target.registers)] + fmt.Fprintf(&source, "\t%s %s, %s\n", op, register, other) + fmt.Fprintf(&source, "\t%s %s, %s\n", op, other, register) + } + fmt.Fprintf(&source, "\t%s 8(AX), DX\n", op) + fmt.Fprintf(&source, "\t%s 16(AX)(CX*4), BX\n", op) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"blsforms": {Name: "blsforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, `"target-features"="+bmi"`) { + t.Fatalf("BLS family did not infer BMI1 target feature:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "bls-family.ll", "bls-family.o", ir) + }) + } +} + +func TestTranslateX86BLSRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "386", instruction: "BLSIL R8, AX"}, + {goarch: "386", instruction: "BLSIQ R8, AX"}, + {goarch: "386", instruction: "BLSIL AX, R8"}, + {goarch: "386", instruction: "BLSIQ AX, R8"}, + {goarch: "amd64", instruction: "BLSIW AX, DX"}, + {goarch: "amd64", instruction: "BLSIL AL, DX"}, + {goarch: "amd64", instruction: "BLSIL X0, DX"}, + {goarch: "amd64", instruction: "BLSIL $1, DX"}, + {goarch: "amd64", instruction: "BLSIL AX, 0(DX)"}, + {goarch: "amd64", instruction: "BLSIL AX"}, + {goarch: "amd64", instruction: "BLSIL AX, DX, BX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{Goarch: test.goarch, TargetTriple: triple, Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yblsil table", test.instruction) + } + }) + } +} + +func TestX86RawBLSCompleteRegisterFields(t *testing.T) { + families := []struct { + digit byte + name string + }{ + {digit: 1, name: "BLSR"}, + {digit: 2, name: "BLSMSK"}, + {digit: 3, name: "BLSI"}, + } + for _, mode := range []int{32, 64} { + registerCount := 8 + widths := []bool{false, true} + if mode == 64 { + registerCount = 16 + } + for _, family := range families { + for _, width64 := range widths { + for destinationNumber := 0; destinationNumber < registerCount; destinationNumber++ { + for sourceNumber := 0; sourceNumber < registerCount; sourceNumber++ { + vex1 := byte(0xe2) + if sourceNumber >= 8 { + vex1 &^= 0x20 + } + vex2 := byte((^destinationNumber & 15) << 3) + if width64 { + vex2 |= 0x80 + } + modRM := byte(0xc0 | int(family.digit)<<3 | sourceNumber&7) + code := []byte{0xc4, vex1, vex2, 0xf3, modRM} + instruction, length, ok, err := decodedX86BLSInstruction(code, mode) + if err != nil || !ok || length != len(code) { + t.Fatalf("mode=%d %x: instruction=%#v length=%d ok=%v err=%v", mode, code, instruction, length, ok, err) + } + width := "L" + if width64 && mode == 64 { + width = "Q" + } + source, _ := decodedX86GeneralRegister(sourceNumber) + destination, _ := decodedX86GeneralRegister(destinationNumber) + if instruction.Op != Op(family.name+width) || len(instruction.Args) != 2 || instruction.Args[0].Reg != source || instruction.Args[1].Reg != destination { + t.Fatalf("mode=%d %x decoded as %#v, want %s%s %s, %s", mode, code, instruction, family.name, width, source, destination) + } + } + } + } + } + } +} + +func TestX86RawBLSCompleteMemoryFormsAndTargets(t *testing.T) { + targets := []struct { + name string + goarch string + triple string + encodings [][]byte + }{ + { + name: "386-linux", goarch: "386", triple: "i386-unknown-linux-gnu", + encodings: [][]byte{ + {0xc4, 0xe2, 0x70, 0xf3, 0x18}, // BLSIL 0(AX), CX + {0xc4, 0xe2, 0x68, 0xf3, 0x54, 0x48, 0x08}, // BLSMSKL 8(AX)(CX*2), DX + {0xc4, 0xe2, 0x60, 0xf3, 0x0d, 0x78, 0x56, 0x34, 0x12}, // BLSRL 0x12345678, BX + }, + }, + { + name: "386-windows", goarch: "386", triple: "i686-pc-windows-msvc", + encodings: [][]byte{ + {0xc4, 0xe2, 0x70, 0xf3, 0x18}, + {0xc4, 0xe2, 0x68, 0xf3, 0x54, 0x48, 0x08}, + {0xc4, 0xe2, 0x60, 0xf3, 0x0d, 0x78, 0x56, 0x34, 0x12}, + }, + }, + { + name: "amd64-darwin", goarch: "amd64", triple: "x86_64-apple-darwin", + encodings: [][]byte{ + {0xc4, 0xe2, 0x88, 0xf3, 0xd2}, // reported BLSMSKQ DX, R14 + {0xc4, 0x82, 0x88, 0xf3, 0x5c, 0x88, 0x10}, // BLSIQ 16(R8)(R9*4), R14 + {0x64, 0xc4, 0xe2, 0x80, 0xf3, 0x4c, 0x48, 0x08}, // BLSRQ FS:8(AX)(CX*2), R15 + {0xc4, 0xe2, 0x80, 0xf3, 0x1c, 0x25, 0x78, 0x56, 0x34, 0x12}, // BLSIQ 0x12345678, R15 + }, + }, + { + name: "amd64-linux", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", + encodings: [][]byte{ + {0xc4, 0xe2, 0x88, 0xf3, 0xd2}, + {0xc4, 0x82, 0x88, 0xf3, 0x5c, 0x88, 0x10}, + {0x64, 0xc4, 0xe2, 0x80, 0xf3, 0x4c, 0x48, 0x08}, + {0xc4, 0xe2, 0x80, 0xf3, 0x1c, 0x25, 0x78, 0x56, 0x34, 0x12}, + }, + }, + { + name: "amd64-windows", goarch: "amd64", triple: "x86_64-pc-windows-msvc", + encodings: [][]byte{ + {0xc4, 0xe2, 0x88, 0xf3, 0xd2}, + {0xc4, 0x82, 0x88, 0xf3, 0x5c, 0x88, 0x10}, + {0x64, 0xc4, 0xe2, 0x80, 0xf3, 0x4c, 0x48, 0x08}, + {0xc4, 0xe2, 0x80, 0xf3, 0x1c, 0x25, 0x78, 0x56, 0x34, 0x12}, + }, + }, + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range targets { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + sigs := make(map[string]FuncSig) + for index, encoding := range target.encodings { + name := fmt.Sprintf("rawBLS_%d", index) + fmt.Fprintf(&source, "TEXT %s(SB),$0-0\n", name) + for _, value := range encoding { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + source.WriteString("\tRET\n") + sigs[name] = FuncSig{Name: name, Ret: Void} + } + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: target.goarch, TargetTriple: target.triple, Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-bls.ll", "raw-bls.o", ir) + }) + } +} + +func TestX86RawBLSRejectsInvalidOrLayoutDependentForms(t *testing.T) { + for _, test := range []struct { + name string + mode int + encoding []byte + }{ + {name: "vex_l", mode: 64, encoding: []byte{0xc4, 0xe2, 0x8c, 0xf3, 0xd2}}, + {name: "vex_prefix", mode: 64, encoding: []byte{0xc4, 0xe2, 0x89, 0xf3, 0xd2}}, + {name: "invalid_digit", mode: 64, encoding: []byte{0xc4, 0xe2, 0x88, 0xf3, 0xc2}}, + {name: "extended_destination_386", mode: 32, encoding: []byte{0xc4, 0xe2, 0x38, 0xf3, 0xd2}}, + {name: "address_size_override", mode: 64, encoding: []byte{0x67, 0xc4, 0xe2, 0x88, 0xf3, 0x54, 0x48, 0x08}}, + {name: "rip_relative", mode: 64, encoding: []byte{0xc4, 0xe2, 0x88, 0xf3, 0x15, 0, 0, 0, 0}}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86BLSInstruction(test.encoding, test.mode) + if test.name == "vex_l" || test.name == "vex_prefix" { + if ok { + t.Fatalf("reserved VEX encoding %x was recognized: %v", test.encoding, err) + } + return + } + if !ok || err == nil { + t.Fatalf("encoding %x: ok=%v err=%v, want recognized rejection", test.encoding, ok, err) + } + }) + } +} + +func TestAMD64BLSRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT blssemantics(SB),$0-8 + MOVQ out+0(FP), DI + MOVQ $0, AX + BLSIQ AX, BX + MOVQ BX, 0(DI) + SETCS 48(DI) + SETEQ 49(DI) + SETMI 50(DI) + SETOS 51(DI) + MOVQ $0x8000000000000000, AX + BLSIQ AX, BX + MOVQ BX, 8(DI) + MOVQ $0, AX + BLSMSKQ AX, BX + MOVQ BX, 16(DI) + SETCS 52(DI) + SETEQ 53(DI) + SETMI 54(DI) + SETOS 55(DI) + MOVQ $10, AX + BLSRQ AX, BX + MOVQ BX, 24(DI) + SETCS 56(DI) + SETEQ 57(DI) + SETMI 58(DI) + SETOS 59(DI) + MOVL $0x80000000, AX + BLSIL AX, BX + MOVQ BX, 32(DI) + MOVL $0, AX + BLSMSKL AX, BX + MOVQ BX, 40(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "blssemantics": {Name: "blssemantics", Args: []LLVMType{Ptr}, Ret: Void, Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}}, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void blssemantics(uint8_t *); +int main(void) { + uint8_t out[64] = {0}; + blssemantics(out); + const uint64_t want[6] = {0, UINT64_C(0x8000000000000000), UINT64_MAX, 8, UINT64_C(0x80000000), UINT64_C(0xffffffff)}; + for (int i = 0; i < 6; i++) { + uint64_t got; + memcpy(&got, out + i * 8, sizeof(got)); + if (got != want[i]) return 10 + i; + } + const uint8_t flags[12] = {0,1,0,0, 1,0,1,0, 0,0,0,0}; + for (int i = 0; i < 12; i++) if (out[48+i] != flags[i]) return 30+i; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "bls_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_bmi2_shift.go b/amd64_lower_bmi2_shift.go new file mode 100644 index 00000000..3441e941 --- /dev/null +++ b/amd64_lower_bmi2_shift.go @@ -0,0 +1,63 @@ +package plan9asm + +import "fmt" + +// lowerBMI2VariableShift implements the six SARX/SHLX/SHRX L/Q opcodes. Go +// 1.27 gives all of them the single _ybextrl row: Yrl count, Yml source, Yrl +// destination. Unlike legacy shifts, the count must be a register and flags +// are not modified. +func (c *amd64Ctx) lowerBMI2VariableShift(op Op, ins Instr) (ok bool, terminated bool, err error) { + bits := 0 + kind := "" + switch op { + case "SARXL": + bits, kind = 32, "ashr" + case "SARXQ": + bits, kind = 64, "ashr" + case "SHLXL": + bits, kind = 32, "shl" + case "SHLXQ": + bits, kind = 64, "shl" + case "SHRXL": + bits, kind = 32, "lshr" + case "SHRXQ": + bits, kind = 64, "lshr" + default: + return false, false, nil + } + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects count register, register/memory source, and destination register: %q", c.goarch, op, ins.Raw) + } + count, source, destination := ins.Args[0], ins.Args[1], ins.Args[2] + if count.Kind != OpReg || !isX86YrlRegisterForArch(count.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s count is outside Go 1.27's Yrl class: %q", c.goarch, op, ins.Raw) + } + if source.Kind == OpReg { + if !isX86YrlRegisterForArch(source.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yrl class: %q", c.goarch, op, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + countValue, err := c.evalIntSized(count, typ) + if err != nil { + return true, false, err + } + sourceValue, err := c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + maskedCount := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %d\n", maskedCount, typ, countValue, bits-1) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %%%s\n", result, kind, typ, sourceValue, maskedCount) + if err := c.storeRegSized(destination.Reg, typ, "%"+result); err != nil { + return true, false, err + } + return true, false, nil +} diff --git a/amd64_lower_bmi2_shift_test.go b/amd64_lower_bmi2_shift_test.go new file mode 100644 index 00000000..1e35e93e --- /dev/null +++ b/amd64_lower_bmi2_shift_test.go @@ -0,0 +1,191 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86BMI2VariableShiftFormsSource(goarch string) string { + var source strings.Builder + symbol := "bmi2shiftdata" + size := 8 + if goarch == "386" { + symbol = "bmi2shiftdata386" + size = 4 + } + fmt.Fprintf(&source, "DATA %s+0(SB)/%d, $1\n", symbol, size) + fmt.Fprintf(&source, "GLOBL %s(SB), $%d\n", symbol, size) + source.WriteString("TEXT bmi2shiftforms(SB),$0-0\n") + for _, stem := range []string{"SARX", "SHLX", "SHRX"} { + for _, width := range []string{"L", "Q"} { + op := stem + width + fmt.Fprintf(&source, "\t%s AX, BX, CX\n", op) + fmt.Fprintf(&source, "\t%s DX, 8(BX), SI\n", op) + fmt.Fprintf(&source, "\t%s CX, %s(SB), DX\n", op, symbol) + if goarch == "amd64" { + fmt.Fprintf(&source, "\t%s R11, R12, R13\n", op) + } + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86BMI2VariableShiftCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86BMI2VariableShiftFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"bmi2shiftforms": {Name: "bmi2shiftforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"ashr i32", "ashr i64", "shl i32", "shl i64", "lshr i32", "lshr i64", `"target-features"="+bmi2"`} { + if !strings.Contains(ll, want) { + t.Fatalf("BMI2 variable-shift lowering omitted %q:\n%s", want, ll) + } + } + compileLLVMToObject(t, llc, target.triple, "bmi2-shift-"+target.name+".ll", "bmi2-shift-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86BMI2VariableShiftRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "SHLXQ $1, AX, BX"}, + {goarch: "amd64", instruction: "SHRXQ 0(BX), AX, CX"}, + {goarch: "amd64", instruction: "SARXL AX, BX, 0(CX)"}, + {goarch: "amd64", instruction: "SHLXL X0, AX, BX"}, + {goarch: "amd64", instruction: "SHRXQ AX, X0, BX"}, + {goarch: "amd64", instruction: "SARXQ AX, BX"}, + {goarch: "amd64", instruction: "SHLXQ.Z AX, BX, CX"}, + {goarch: "386", instruction: "SHLXL R8, AX, BX"}, + {goarch: "386", instruction: "SHRXQ AX, R8, BX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _ybextrl table", test.instruction) + } + }) + } +} + +func TestAMD64BMI2VariableShiftRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT bmi2shiftsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVQ $36, AX + MOVQ $0x12345678, BX + SHLXL AX, BX, CX + MOVQ CX, 0(DI) + MOVQ $-81985529216486896, 8(DI) + MOVQ $72, AX + SHRXQ AX, 8(DI), CX + MOVQ CX, 8(DI) + MOVQ $0x80000000, BX + SARXL AX, BX, CX + MOVQ CX, 16(DI) + MOVQ $-9223372036854775808, BX + SARXQ AX, BX, CX + MOVQ CX, 24(DI) + MOVQ $1, AX + MOVQ $3, BX + CMPQ BX, BX + STC + SHLXQ AX, BX, AX + MOVQ AX, 32(DI) + SETCS 40(DI) + SETEQ 41(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "bmi2shiftsemantics": { + Name: "bmi2shiftsemantics", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void bmi2shiftsemantics(uint8_t *); +int main(void) { + uint8_t out[48] = {0}; + bmi2shiftsemantics(out); + if (*(uint64_t *)(out+0) != UINT64_C(0x23456780)) return 10; + if (*(uint64_t *)(out+8) != UINT64_C(0x00fedcba98765432)) return 11; + if (*(uint64_t *)(out+16) != UINT64_C(0xff800000)) return 12; + if (*(uint64_t *)(out+24) != UINT64_C(0xff80000000000000)) return 13; + if (*(uint64_t *)(out+32) != 6) return 14; + if (out[40] != 1 || out[41] != 1) return 15; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "bmi2_shift_semantics", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_bound.go b/amd64_lower_bound.go new file mode 100644 index 00000000..bd5f55a4 --- /dev/null +++ b/amd64_lower_bound.go @@ -0,0 +1,63 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var amd64BoundOperandBits = map[Op]int{ + "BOUNDW": 16, + "BOUNDL": 32, +} + +// lowerBound implements Go 1.27's complete yrl_m family. BOUND is valid only +// in 16/32-bit x86 modes, so plan9asm preserves the exact faulting instruction +// as constrained inline assembly rather than approximating its exception. +func (c *amd64Ctx) lowerBound(op Op, ins Instr) (ok bool, terminated bool, err error) { + raw := strings.ToUpper(string(op)) + base := raw + if dot := strings.IndexByte(raw, '.'); dot >= 0 { + base = raw[:dot] + } + bits, recognized := amd64BoundOperandBits[Op(base)] + if !recognized { + return false, false, nil + } + if raw != base { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, base, ins.Raw) + } + if c.goarch != "386" { + return true, false, fmt.Errorf("%s %s is unavailable outside 32-bit x86 mode: %q", c.goarch, base, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("386 %s expects GP register and bounds memory: %q", base, ins.Raw) + } + if ins.Args[0].Kind != OpReg || !isX86YrlRegisterForArch(ins.Args[0].Reg, c.goarch) { + return true, false, fmt.Errorf("386 %s source is outside Go 1.27's Yrl class: %q", base, ins.Raw) + } + if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("386 %s second operand must be Go 1.27 Ym memory: %q", base, ins.Raw) + } + typeName := I32 + if bits == 16 { + typeName = I16 + } + value, err := c.evalIntSized(ins.Args[0], typeName) + if err != nil { + return true, false, err + } + pointer, pointerType, err := c.x86DescriptorMemoryPointer(ins.Args[1]) + if err != nil { + return true, false, err + } + // LLVM 22's integrated assembler no longer recognizes the BOUND mnemonic, + // even for an i386 triple. Constrain the value and bounds pointer to AX/CX + // and emit 62 /r with ModRM 00:000:001. The 66 prefix selects BOUNDW. + encoding := ".byte 0x62, 0x01" + if bits == 16 { + encoding = ".byte 0x66, 0x62, 0x01" + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s %s, %s %s)\n", + encoding, "{ax},{cx},~{memory},~{dirflag},~{fpsr},~{flags}", typeName, value, pointerType, pointer) + return true, false, nil +} diff --git a/amd64_lower_bound_test.go b/amd64_lower_bound_test.go new file mode 100644 index 00000000..c455da06 --- /dev/null +++ b/amd64_lower_bound_test.go @@ -0,0 +1,81 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslate386BoundCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + triple string + }{ + {name: "linux-386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := "TEXT boundforms(SB),NOSPLIT,$16-0\n" + for _, op := range []string{"BOUNDW", "BOUNDL"} { + for _, reg := range []string{"AX", "BX", "CX", "DX", "SP", "BP", "SI", "DI"} { + source += "\t" + op + " " + reg + ", 0(SP)\n" + } + source += "\t" + op + " AX, 8(BX)\n" + } + source += "\tRET\n" + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "386", + Sigs: map[string]FuncSig{"boundforms": {Name: "boundforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{".byte 0x66, 0x62, 0x01", ".byte 0x62, 0x01", `"{ax},{cx},~{memory},~{dirflag},~{fpsr},~{flags}"`} { + if !strings.Contains(ll, want) { + t.Fatalf("translated BOUND family missing %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "bound-"+target.name+".ll", "bound-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86BoundRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + tests := []struct { + goarch string + triple string + instruction string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "BOUNDW AX, 0(BX)"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "BOUNDL AX, 0(BX)"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "BOUNDL X0, 0(BX)"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "BOUNDW $1, 0(BX)"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "BOUNDL AX, BX"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "BOUNDL.Z AX, 0(BX)"}, + } + for _, test := range tests { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+test.instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: test.triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's BOUND tables for %s", test.instruction, test.goarch) + } + }) + } +} diff --git a/amd64_lower_branch.go b/amd64_lower_branch.go index 345ec225..9c399308 100644 --- a/amd64_lower_branch.go +++ b/amd64_lower_branch.go @@ -34,6 +34,16 @@ func (c *amd64Ctx) lowerBranch(bi int, ii int, op Op, ins Instr, emitBr amd64Emi } return true, false, nil case OpSym: + if strings.HasPrefix(strings.TrimSpace(ins.Args[0].Sym), "*") { + addr, err := c.loadIndirectSymbolAddr(ins.Args[0].Sym) + if err != nil { + return true, false, err + } + if err := c.callIndirectAddr(addr); err != nil { + return true, false, err + } + return true, false, nil + } if err := c.callSym(ins.Args[0]); err != nil { return true, false, err } @@ -42,16 +52,22 @@ func (c *amd64Ctx) lowerBranch(bi int, ii int, op Op, ins Instr, emitBr amd64Emi return true, false, fmt.Errorf("amd64 CALL expects reg or symbol(SB) target: %q", ins.Raw) } - case "JMP", - "JE", "JEQ", "JZ", "JNE", "JNZ", - "JL", "JLT", "JLE", "JG", "JGT", "JGE", "JS", "JNS", - "JA", "JHI", "JAE", "JHS", "JB", "JLO", "JBE", "JLS", "JNA", - "JC", "JNC", "JCC": - // ok default: - return false, false, nil + if op != "JMP" && op != "LOOP" && !isAMD64ConditionalBranch(op) { + return false, false, nil + } } - if len(ins.Args) != 1 { + args := ins.Args + // The Go assembler accepts a legacy x86 branch-hint operand such as + // JEQ $1, target. It is not part of the encoded instruction on current + // toolchains, so preserve control flow and ignore the hint value. + if op != "JMP" && op != "LOOP" && !isAMD64CounterZeroBranch(op) && len(args) == 2 && args[0].Kind == OpImm { + if args[0].Imm != 0 && args[0].Imm != 1 { + return true, false, fmt.Errorf("amd64 %s branch hint must be $0 or $1: %q", op, ins.Raw) + } + args = args[1:] + } + if len(args) != 1 { return true, false, fmt.Errorf("amd64 %s expects 1 operand: %q", op, ins.Raw) } target := "" @@ -65,19 +81,19 @@ func (c *amd64Ctx) lowerBranch(bi int, ii int, op Op, ins Instr, emitBr amd64Emi } return false } - switch ins.Args[0].Kind { + switch args[0].Kind { case OpIdent: - target = ins.Args[0].Ident + target = args[0].Ident case OpReg: // Labels like V1 may be tokenized as registers. Prefer block labels; // otherwise treat JMP reg as an indirect tail jump. - name := string(ins.Args[0].Reg) + name := string(args[0].Reg) if knownBlock(name) { target = name break } if op == "JMP" { - addr, err := c.loadReg(ins.Args[0].Reg) + addr, err := c.loadReg(args[0].Reg) if err != nil { return true, false, err } @@ -88,10 +104,20 @@ func (c *amd64Ctx) lowerBranch(bi int, ii int, op Op, ins Instr, emitBr amd64Emi } return true, false, fmt.Errorf("amd64 %s invalid register target: %q", op, ins.Raw) case OpSym: - s := strings.TrimSpace(ins.Args[0].Sym) + s := strings.TrimSpace(args[0].Sym) + if op == "JMP" && strings.HasPrefix(s, "*") { + addr, err := c.loadIndirectSymbolAddr(s) + if err != nil { + return true, false, err + } + if err := c.tailCallIndirectAddrAndRet(addr); err != nil { + return true, false, err + } + return true, true, nil + } // Treat JMP foo(SB) as a tailcall to another TEXT (common in stdlib asm). if op == "JMP" && strings.HasSuffix(s, "(SB)") { - if err := c.tailCallAndRet(ins.Args[0]); err != nil { + if err := c.tailCallAndRet(args[0]); err != nil { return true, false, err } return true, true, nil @@ -103,13 +129,13 @@ func (c *amd64Ctx) lowerBranch(bi int, ii int, op Op, ins Instr, emitBr amd64Emi // PC-relative branches like "JEQ 2(PC)" are used as a compact way to skip // the next instruction. Handle them by mapping the offset to our block // sequence (blocks are split at terminators, so the pattern works well). - if strings.EqualFold(string(ins.Args[0].Mem.Base), "PC") { + if strings.EqualFold(string(args[0].Mem.Base), "PC") { pcRel = true - pcOff = ins.Args[0].Mem.Off + pcOff = args[0].Mem.Off break } if op == "JMP" { - addr, err := c.addrFromMem(ins.Args[0].Mem) + addr, err := c.addrFromMem(args[0].Mem) if err != nil { return true, false, err } @@ -150,70 +176,102 @@ func (c *amd64Ctx) lowerBranch(bi int, ii int, op Op, ins Instr, emitBr amd64Emi fall := c.blocks[bi+1].name cond := "" switch op { + case "LOOP": + counter, err := c.loadReg(CX) + if err != nil { + return true, false, err + } + if c.goarch == "386" { + old32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", old32, counter) + next32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 %%%s, 1\n", next32, old32) + next64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", next64, next32) + if err := c.storeReg(CX, "%"+next64); err != nil { + return true, false, err + } + test := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne i32 %%%s, 0\n", test, next32) + cond = "%" + test + } else { + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i64 %s, 1\n", next, counter) + if err := c.storeReg(CX, "%"+next); err != nil { + return true, false, err + } + test := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne i64 %%%s, 0\n", test, next) + cond = "%" + test + } + case "JCXZW", "JCXZL", "JCXZQ": + // cmd/internal/obj/x86 emits an address-size override only for + // JCXZL. Therefore Go's historical spellings test these widths: + // + // JCXZW JCXZL JCXZQ + // amd64 RCX ECX RCX + // 386 ECX CX ECX + // + // Preserve that behavior instead of inferring the width from the + // mnemonic suffix. + counter, err := c.loadReg(CX) + if err != nil { + return true, false, err + } + bits := 64 + if c.goarch == "386" { + bits = 32 + } + if op == "JCXZL" { + bits /= 2 + } + value := counter + if bits != 64 { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", truncated, counter, bits) + value = "%" + truncated + } + test := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %s, 0\n", test, bits, value) + cond = "%" + test case "JE", "JEQ", "JZ": - cond = c.loadFlag(c.flagsZSlot) + cond, err = c.x86Condition("EQ") case "JNE", "JNZ": - z := c.loadFlag(c.flagsZSlot) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", t, z) - cond = "%" + t - case "JL", "JLT": - cond = c.loadFlag(c.flagsSltSlot) - case "JGE": - slt := c.loadFlag(c.flagsSltSlot) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", t, slt) - cond = "%" + t - case "JS": - cond = c.loadFlag(c.flagsSltSlot) - case "JNS": - slt := c.loadFlag(c.flagsSltSlot) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", t, slt) - cond = "%" + t - case "JLE": - slt := c.loadFlag(c.flagsSltSlot) - z := c.loadFlag(c.flagsZSlot) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i1 %s, %s\n", t, slt, z) - cond = "%" + t - case "JG", "JGT": - slt := c.loadFlag(c.flagsSltSlot) - z := c.loadFlag(c.flagsZSlot) - t1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i1 %s, %s\n", t1, slt, z) - t2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", t2, t1) - cond = "%" + t2 - case "JB", "JLO", "JC": - cond = c.loadFlag(c.flagsCFSlot) - case "JNC", "JCC": - cf := c.loadFlag(c.flagsCFSlot) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", t, cf) - cond = "%" + t - case "JAE", "JHS": - cf := c.loadFlag(c.flagsCFSlot) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", t, cf) - cond = "%" + t + cond, err = c.x86Condition("NE") + case "JL", "JLT", "JNGE": + cond, err = c.x86Condition("LT") + case "JGE", "JNL": + cond, err = c.x86Condition("GE") + case "JS", "JMI": + cond, err = c.x86Condition("MI") + case "JNS", "JPL": + cond, err = c.x86Condition("PL") + case "JLE", "JNG": + cond, err = c.x86Condition("LE") + case "JG", "JGT", "JNLE": + cond, err = c.x86Condition("GT") + case "JB", "JLO", "JC", "JCS", "JNAE": + cond, err = c.x86Condition("CS") + case "JNC", "JCC", "JAE", "JHS", "JNB": + cond, err = c.x86Condition("CC") case "JBE", "JLS", "JNA": - cf := c.loadFlag(c.flagsCFSlot) - z := c.loadFlag(c.flagsZSlot) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i1 %s, %s\n", t, cf, z) - cond = "%" + t - case "JA", "JHI": - cf := c.loadFlag(c.flagsCFSlot) - z := c.loadFlag(c.flagsZSlot) - t1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i1 %s, %s\n", t1, cf, z) - t2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", t2, t1) - cond = "%" + t2 + cond, err = c.x86Condition("LS") + case "JA", "JHI", "JNBE": + cond, err = c.x86Condition("HI") + case "JO", "JOS": + cond, err = c.x86Condition("OS") + case "JNO", "JOC": + cond, err = c.x86Condition("OC") + case "JP", "JPE", "JPS": + cond, err = c.x86Condition("PS") + case "JNP", "JPO", "JPC": + cond, err = c.x86Condition("PC") default: return true, false, fmt.Errorf("amd64: unsupported branch %s", op) } + if err != nil { + return true, false, err + } if err := emitCondBr(cond, target, fall); err != nil { return true, false, err @@ -221,6 +279,26 @@ func (c *amd64Ctx) lowerBranch(bi int, ii int, op Op, ins Instr, emitBr amd64Emi return true, true, nil } +func (c *amd64Ctx) loadIndirectSymbolAddr(sym string) (string, error) { + sym = strings.TrimSpace(strings.TrimPrefix(strings.TrimSpace(sym), "*")) + if !strings.HasSuffix(sym, "(SB)") { + return "", fmt.Errorf("amd64 indirect branch expects register, memory, or *symbol(SB), got %q", sym) + } + ptr, err := c.ptrFromSB(sym) + if err != nil { + return "", err + } + value := c.newTmp() + if c.goarch == "386" { + fmt.Fprintf(c.b, " %%%s = load i32, ptr %s, align 1\n", value, ptr) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, value) + return "%" + wide, nil + } + fmt.Fprintf(c.b, " %%%s = load i64, ptr %s, align 1\n", value, ptr) + return "%" + value, nil +} + func (c *amd64Ctx) callIndirectAddr(addr string) error { fptr := c.newTmp() fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", fptr, addr) @@ -294,6 +372,7 @@ func (c *amd64Ctx) callSym(symOp Operand) error { if !strings.HasSuffix(s, "(SB)") { return fmt.Errorf("amd64 call expects (SB) symbol, got %q", s) } + internalABI := strings.HasSuffix(strings.TrimSuffix(s, "(SB)"), "") s = strings.TrimSuffix(s, "(SB)") callee := c.resolve(s) // Syscall stubs invoke runtime entersyscall/exitsyscall around SYSCALL. @@ -310,6 +389,24 @@ func (c *amd64Ctx) callSym(symOp Operand) error { } callee = funcSigSymbol(callee, csig) + stackABI := !internalABI && len(csig.ArgRegs) == 0 && len(csig.Frame.Params) != 0 + if stackABI { + args, err := c.abi0CallArgs(callee, csig) + if err != nil { + return err + } + if csig.Ret == Void { + fmt.Fprintf(c.b, " call void %s(%s)\n", llvmGlobal(callee), strings.Join(args, ", ")) + return nil + } + t := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s %s(%s)\n", t, csig.Ret, llvmGlobal(callee), strings.Join(args, ", ")) + if len(csig.Frame.Results) != 0 { + return c.storeABI0CallResult(callee, csig, "%"+t) + } + return fmt.Errorf("amd64 call %q: ABI0 result %s has no frame slot", callee, csig.Ret) + } + args := make([]string, 0, len(csig.Args)) goABI := []Reg{AX, BX, CX, DI, SI, Reg("R8"), Reg("R9"), Reg("R10"), Reg("R11")} regCursor := 0 @@ -418,12 +515,13 @@ func (c *amd64Ctx) tailCallAndRet(symOp Operand) error { // If ArgRegs is empty, default to register-based passing (ABIInternal-ish) // because most intra-asm tailcalls depend on explicit register setup. // - // Exception: for tailcalls to Go functions with an identical signature, + // Exception: for tailcalls to Go functions with identical argument types, // use the current function's LLVM args. This matches stdlib patterns like // "JMP ·countGeneric(SB)" that happen before any register shuffling and - // are stack-ABI tailcalls in the original asm. + // are stack-ABI tailcalls in the original asm. The return types may differ + // while using ABI-equivalent physical result slots. useLLVMArgs := false - if len(csig.ArgRegs) == 0 && len(csig.Args) == len(c.sig.Args) && csig.Ret == c.sig.Ret { + if len(csig.ArgRegs) == 0 && len(csig.Args) == len(c.sig.Args) { same := true for j := 0; j < len(csig.Args); j++ { if csig.Args[j] != c.sig.Args[j] { @@ -527,8 +625,22 @@ func (c *amd64Ctx) tailCallAndRet(symOp Operand) error { return nil } if c.sig.Ret != csig.Ret { + if adapted, ok, err := c.adaptTailCallAggregateReturn("%"+t, csig.Ret, c.sig.Ret); err != nil { + return fmt.Errorf("amd64 tailcall return type mismatch for %q: %w", callee, err) + } else if ok { + fmt.Fprintf(c.b, " ret %s %s\n", c.sig.Ret, adapted) + return nil + } conv := c.newTmp() switch { + case c.goarch == "386" && csig.Ret == I32 && c.sig.Ret == Ptr: + fmt.Fprintf(c.b, " %%%s = inttoptr i32 %%%s to ptr\n", conv, t) + fmt.Fprintf(c.b, " ret ptr %%%s\n", conv) + return nil + case c.goarch == "386" && csig.Ret == Ptr && c.sig.Ret == I32: + fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %%%s to i32\n", conv, t) + fmt.Fprintf(c.b, " ret i32 %%%s\n", conv) + return nil case csig.Ret == I64 && (c.sig.Ret == I1 || c.sig.Ret == I8 || c.sig.Ret == I16 || c.sig.Ret == I32): fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to %s\n", conv, t, c.sig.Ret) fmt.Fprintf(c.b, " ret %s %%%s\n", c.sig.Ret, conv) @@ -552,3 +664,47 @@ func (c *amd64Ctx) tailCallAndRet(symOp Operand) error { fmt.Fprintf(c.b, " ret %s %%%s\n", c.sig.Ret, t) return nil } + +func (c *amd64Ctx) adaptTailCallAggregateReturn(value string, fromTy, toTy LLVMType) (string, bool, error) { + fromFields, fromAggregate := parseLiteralStructFields(fromTy) + toFields, toAggregate := parseLiteralStructFields(toTy) + if !fromAggregate || !toAggregate { + return "", false, nil + } + if len(fromFields) != len(toFields) { + return "", false, fmt.Errorf("caller %s and callee %s use different aggregate field counts", toTy, fromTy) + } + + wordTy := I64 + if c.goarch == "386" { + wordTy = I32 + } + for i := range fromFields { + from, to := fromFields[i], toFields[i] + if from == to || (from == wordTy && to == Ptr) || (from == Ptr && to == wordTy) { + continue + } + return "", false, fmt.Errorf("caller field %d has type %s but callee field has ABI-incompatible type %s", i, to, from) + } + + result := "undef" + for i := range fromFields { + from, to := fromFields[i], toFields[i] + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", extracted, fromTy, value, i) + field := "%" + extracted + if from != to { + converted := c.newTmp() + if from == wordTy && to == Ptr { + fmt.Fprintf(c.b, " %%%s = inttoptr %s %s to ptr\n", converted, wordTy, field) + } else { + fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %s to %s\n", converted, field, wordTy) + } + field = "%" + converted + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertvalue %s %s, %s %s, %d\n", inserted, toTy, result, to, field, i) + result = "%" + inserted + } + return result, true, nil +} diff --git a/amd64_lower_broadcast.go b/amd64_lower_broadcast.go new file mode 100644 index 00000000..c044d788 --- /dev/null +++ b/amd64_lower_broadcast.go @@ -0,0 +1,133 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedScalarBroadcast implements the complete Go 1.27 +// _yvpbroadcastb operand table shared by VPBROADCASTB/W/D/Q. +func (c *amd64Ctx) lowerPackedScalarBroadcast(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits := 0 + switch baseOp { + case "VPBROADCASTB": + laneBits = 8 + case "VPBROADCASTW": + laneBits = 16 + case "VPBROADCASTD": + laneBits = 32 + case "VPBROADCASTQ": + laneBits = 64 + default: + return false, false, nil + } + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("amd64 %s accepts only the .Z suffix enabled by its Go 1.27 optab: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 %s expects scalar source, [K mask,] vector destination: %q", baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects an X, Y, or Z destination: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth == 0 { + return true, false, fmt.Errorf("amd64 %s expects an X, Y, or Z destination: %q", baseOp, ins.Raw) + } + + masked := len(ins.Args) == 3 + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s zeroing requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + var mask string + if masked { + maskArg := ins.Args[1] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, ok := amd64ParseKReg(maskArg.Reg) + if !ok || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + scalar, err := c.loadPackedBroadcastScalar(ins.Args[0], laneBits) + if err != nil { + return true, false, fmt.Errorf("amd64 %s source: %w", baseOp, err) + } + lanes := byteWidth * 8 / laneBits + result := amd64SplatInteger(c, lanes, laneBits, scalar) + if masked { + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) loadPackedBroadcastScalar(src Operand, laneBits int) (string, error) { + if src.Kind == OpReg { + if isAMD64XReg(src.Reg) { + bytesValue, err := c.loadX(src.Reg) + if err != nil { + return "", err + } + lanes := 128 / laneBits + laneVector := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, bytesValue) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 0\n", low, lanes, laneBits, laneVector) + return "%" + low, nil + } + if !isAMD64YrlRegister(src.Reg) { + return "", fmt.Errorf("expected an X register, GP register, or memory, got %s", src.String()) + } + return c.evalIntSized(src, amd64IntegerTypeForBits(laneBits)) + } + if src.Kind == OpSym { + // A bare integer in Go's x86 syntax is absolute memory, not an + // immediate (immediates carry a '$'). The parser keeps this spelling + // as OpSym so distinguish it here before the generic symbol loader. + if address, parseErr := parseInt(src.Sym); parseErr == nil { + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i%d, ptr %s, align 1\n", loaded, laneBits, c.ptrFromAddrI64(fmt.Sprintf("%d", address))) + return "%" + loaded, nil + } + } + if !isAMD64MemoryOperand(src) { + return "", fmt.Errorf("expected an X register, GP register, or memory, got %s", src.String()) + } + return c.evalIntSized(src, amd64IntegerTypeForBits(laneBits)) +} + +// isAMD64YrlRegister mirrors Go's amd64 Yrl register class. Byte aliases, +// vector, mask, MMX, and x87 registers are deliberately excluded. +func isAMD64YrlRegister(r Reg) bool { + switch strings.ToUpper(string(r)) { + case "AX", "BX", "CX", "DX", "SP", "BP", "SI", "DI", + "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15": + return true + default: + return false + } +} diff --git a/amd64_lower_broadcast_block.go b/amd64_lower_broadcast_block.go new file mode 100644 index 00000000..86c2d9e4 --- /dev/null +++ b/amd64_lower_broadcast_block.go @@ -0,0 +1,183 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedBlockBroadcastSpec struct { + sourceBytes int + laneBits int + allowXSource bool + vexMemoryOnly bool + allowDestinations map[int]bool +} + +var amd64PackedBlockBroadcastSpecs = map[string]amd64PackedBlockBroadcastSpec{ + "VBROADCASTF128": {sourceBytes: 16, laneBits: 64, vexMemoryOnly: true, allowDestinations: map[int]bool{32: true}}, + "VBROADCASTI128": {sourceBytes: 16, laneBits: 64, vexMemoryOnly: true, allowDestinations: map[int]bool{32: true}}, + "VBROADCASTF32X2": {sourceBytes: 8, laneBits: 32, allowXSource: true, allowDestinations: map[int]bool{32: true, 64: true}}, + "VBROADCASTI32X2": {sourceBytes: 8, laneBits: 32, allowXSource: true, allowDestinations: map[int]bool{16: true, 32: true, 64: true}}, + "VBROADCASTF32X4": {sourceBytes: 16, laneBits: 32, allowDestinations: map[int]bool{32: true, 64: true}}, + "VBROADCASTF64X2": {sourceBytes: 16, laneBits: 64, allowDestinations: map[int]bool{32: true, 64: true}}, + "VBROADCASTI32X4": {sourceBytes: 16, laneBits: 32, allowDestinations: map[int]bool{32: true, 64: true}}, + "VBROADCASTI64X2": {sourceBytes: 16, laneBits: 64, allowDestinations: map[int]bool{32: true, 64: true}}, + "VBROADCASTF32X8": {sourceBytes: 32, laneBits: 32, allowDestinations: map[int]bool{64: true}}, + "VBROADCASTF64X4": {sourceBytes: 32, laneBits: 64, allowDestinations: map[int]bool{64: true}}, + "VBROADCASTI32X8": {sourceBytes: 32, laneBits: 32, allowDestinations: map[int]bool{64: true}}, + "VBROADCASTI64X4": {sourceBytes: 32, laneBits: 64, allowDestinations: map[int]bool{64: true}}, +} + +// lowerPackedBlockBroadcast implements all Go 1.27 EVEX packed-block +// broadcast tables. The X2 forms copy the low 64 source bits; the X4 and X8 +// forms accept only 128- and 256-bit memory sources respectively. +func (c *amd64Ctx) lowerPackedBlockBroadcast(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + zeroing := false + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + suffix = rawOp[dot+1:] + if suffix != "Z" { + if _, known := amd64PackedBlockBroadcastSpecs[baseOp]; known { + return true, false, fmt.Errorf("amd64 %s accepts only the .Z suffix: %q", baseOp, ins.Raw) + } + return false, false, nil + } + zeroing = true + } + spec, ok := amd64PackedBlockBroadcastSpecs[baseOp] + if !ok { + return false, false, nil + } + if spec.vexMemoryOnly { + if suffix != "" || len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects Go 1.27's unsuffixed m128, Y form: %q", c.goarch, baseOp, ins.Raw) + } + } else if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 %s expects block source, [K mask,] vector destination: %q", baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + destinationBytes := 0 + if destination.Kind == OpReg { + destinationBytes = amd64VectorByteWidth(destination.Reg) + } + validDestination := spec.allowDestinations[destinationBytes] && c.isGoPackedVectorMoveRegister(destination, destinationBytes) + if validDestination && spec.vexMemoryOnly { + index, isY := amd64ParseYReg(destination.Reg) + validDestination = isY && index < 16 + } + if !validDestination { + return true, false, fmt.Errorf("amd64 %s destination is outside its Go 1.27 operand table: %q", baseOp, ins.Raw) + } + + source := ins.Args[0] + if source.Kind == OpReg { + if spec.vexMemoryOnly || !spec.allowXSource || !amd64EVEXVectorRegister(source, 16) { + return true, false, fmt.Errorf("amd64 %s requires a memory source for this block width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s expects a memory source%s: %q", baseOp, amd64PackedBlockXSourceHint(spec.allowXSource), ins.Raw) + } + + masked := !spec.vexMemoryOnly && len(ins.Args) == 3 + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + mask := "" + if masked { + maskArg := ins.Args[1] + maskIndex, validMask := amd64ParseKReg(maskArg.Reg) + if maskArg.Kind != OpReg || !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + block, err := c.loadPackedBlockBroadcastSource(source, spec.sourceBytes) + if err != nil { + return true, false, err + } + broadcast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i8> %s, <%d x i8> %s, <%d x i32> %s\n", + broadcast, spec.sourceBytes, block, spec.sourceBytes, block, destinationBytes, llvmRepeatI8Mask(spec.sourceBytes, destinationBytes)) + result := "%" + broadcast + + if masked { + lanes := destinationBytes * 8 / spec.laneBits + computed := c.bitcastVectorBytesToIntegerLanes(destinationBytes, lanes, spec.laneBits, result) + oldBytes, err := c.loadPackedCompareBytes(destination, destinationBytes) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(destinationBytes, lanes, spec.laneBits, oldBytes) + maskedResult := amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, computed, old, mask, zeroing) + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", cast, lanes, spec.laneBits, maskedResult, destinationBytes) + result = "%" + cast + } + return true, false, c.storeVectorBytes(destination.Reg, destinationBytes, result) +} + +func amd64PackedBlockXSourceHint(allowed bool) string { + if allowed { + return " or X-register source" + } + return "" +} + +func (c *amd64Ctx) loadPackedBlockBroadcastSource(source Operand, sourceBytes int) (string, error) { + if source.Kind == OpReg { + value, err := c.loadX(source.Reg) + if err != nil { + return "", err + } + words := c.newTmp() + low := c.newTmp() + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", words, value) + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 0\n", low, words) + fmt.Fprintf(c.b, " %%%s = bitcast i64 %%%s to <8 x i8>\n", bytesValue, low) + return "%" + bytesValue, nil + } + + switch source.Kind { + case OpMem: + address, err := c.addrFromMem(source.Mem) + if err != nil { + return "", err + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load <%d x i8>, ptr %s, align 1\n", loaded, sourceBytes, c.ptrFromAddrI64(address)) + return "%" + loaded, nil + case OpSym: + pointer, err := c.ptrFromSB(source.Sym) + if err != nil { + return "", err + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load <%d x i8>, ptr %s, align 1\n", loaded, sourceBytes, pointer) + return "%" + loaded, nil + case OpFP: + chunks := sourceBytes / 8 + words := "zeroinitializer" + for chunk := 0; chunk < chunks; chunk++ { + word, err := c.evalFPToI64(source.FPOffset + int64(chunk*8)) + if err != nil { + return "", err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i64> %s, i64 %s, i32 %d\n", inserted, chunks, words, word, chunk) + words = "%" + inserted + } + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", bytesValue, chunks, words, sourceBytes) + return "%" + bytesValue, nil + default: + return "", fmt.Errorf("expected packed-block broadcast memory source, got %s", source.String()) + } +} diff --git a/amd64_lower_broadcast_block_test.go b/amd64_lower_broadcast_block_test.go new file mode 100644 index 00000000..8abe9f7e --- /dev/null +++ b/amd64_lower_broadcast_block_test.go @@ -0,0 +1,212 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86PackedBlockBroadcastCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 exposes the complete VEX/EVEX packed-block broadcast family as: + // + // VBROADCASTF128 m128 -> Y + // VBROADCASTI128 m128 -> Y + // VBROADCASTF32X2 X/m64 -> Y/Z + // VBROADCASTI32X2 X/m64 -> X/Y/Z + // VBROADCASTF32X4 m128 -> Y/Z + // VBROADCASTF64X2 m128 -> Y/Z + // VBROADCASTI32X4 m128 -> Y/Z + // VBROADCASTI64X2 m128 -> Y/Z + // VBROADCASTF32X8 m256 -> Z + // VBROADCASTF64X4 m256 -> Z + // VBROADCASTI32X8 m256 -> Z + // VBROADCASTI64X4 m256 -> Z + // + // Every form also accepts K1-K7 merge masking and .Z zero masking. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastY := 15 + lastZ := 21 + if target.goarch == "386" { + lastZ = 7 + } + var src strings.Builder + src.WriteString("TEXT packedblockbroadcastforms(SB),$0-0\n") + fmt.Fprintf(&src, "\tVBROADCASTF128 0(AX), Y%d\n", lastY) + fmt.Fprintf(&src, "\tVBROADCASTI128 16(AX), Y%d\n", lastY) + src.WriteString("\tVBROADCASTF32X2 X20, Y21\n") + src.WriteString("\tVBROADCASTF32X2 8(AX), K1, Y20\n") + fmt.Fprintf(&src, "\tVBROADCASTF32X2.Z X20, K2, Z%d\n", lastZ) + src.WriteString("\tVBROADCASTI32X2 X20, X21\n") + src.WriteString("\tVBROADCASTI32X2 16(AX), K3, Y20\n") + fmt.Fprintf(&src, "\tVBROADCASTI32X2.Z X20, K4, Z%d\n", lastZ) + for _, op := range []string{ + "VBROADCASTF32X4", "VBROADCASTF64X2", + "VBROADCASTI32X4", "VBROADCASTI64X2", + } { + fmt.Fprintf(&src, "\t%s 24(AX), Y20\n", op) + fmt.Fprintf(&src, "\t%s 40(AX), K5, Y21\n", op) + fmt.Fprintf(&src, "\t%s.Z 56(AX), K6, Z%d\n", op, lastZ) + } + for _, op := range []string{ + "VBROADCASTF32X8", "VBROADCASTF64X4", + "VBROADCASTI32X8", "VBROADCASTI64X4", + } { + fmt.Fprintf(&src, "\t%s 72(AX), Z%d\n", op, lastZ) + fmt.Fprintf(&src, "\t%s.Z 104(AX), K7, Z%d\n", op, lastZ) + } + src.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, src.String(), true) + + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedblockbroadcastforms": {Name: "packedblockbroadcastforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-block-broadcast-"+target.name+".ll", "packed-block-broadcast-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedBlockBroadcastRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "VBROADCASTF128 (AX), Y16", + "VBROADCASTI128 (AX), Y16", + "VBROADCASTF128 X0, Y1", + "VBROADCASTI128 X0, Y1", + "VBROADCASTF128 (AX), X1", + "VBROADCASTI128 (AX), Z1", + "VBROADCASTF128 (AX), K1, Y1", + "VBROADCASTI128.Z (AX), K1, Y1", + "VBROADCASTF32X2 X0, X1", + "VBROADCASTF32X2 Y0, Y1", + "VBROADCASTI32X2 Y0, Y1", + "VBROADCASTF32X4 X0, Y1", + "VBROADCASTF64X2 X0, Y1", + "VBROADCASTI32X4 X0, Y1", + "VBROADCASTI64X2 X0, Y1", + "VBROADCASTF32X4 (AX), X1", + "VBROADCASTF32X8 (AX), Y1", + "VBROADCASTF64X4 Y0, Z1", + "VBROADCASTI32X8 Y0, Z1", + "VBROADCASTI64X4 (AX), Y1", + "VBROADCASTI32X4 (AX), K0, Y1", + "VBROADCASTI32X4.Z (AX), Y1", + "VBROADCASTI32X4.BCST (AX), Y1", + "VBROADCASTI32X4 (AX), K1, K2, Y1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + requireX86GoAssemblerResult(t, "amd64", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + assertX86PackedBlockBroadcastRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "VBROADCASTF128 (AX), Y16", + "VBROADCASTI128 (AX), Y16", + "VBROADCASTI32X2 X20, Z8", + "VBROADCASTI32X4 (AX), Z20", + } { + requireX86GoAssemblerResult(t, "386", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + assertX86PackedBlockBroadcastRejected(t, "386", "i386-unknown-linux-gnu", instruction) + } +} + +func assertX86PackedBlockBroadcastRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed-block broadcast forms", instruction) + } +} + +func TestAMD64LegacyBlockBroadcastRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT legacyblockbroadcast(SB),$0-16 + MOVQ out+0(FP), AX + MOVQ source+8(FP), BX + VBROADCASTF128 (BX), Y0 + VMOVDQU Y0, 0(AX) + VBROADCASTI128 (BX), Y1 + VMOVDQU Y1, 32(AX) + VZEROUPPER + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "legacyblockbroadcast": {Name: "legacyblockbroadcast", Args: []LLVMType{Ptr, Ptr}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +#include +extern void legacyblockbroadcast(uint8_t *, const uint8_t *); +int main(void) { + const uint8_t source[16] = {0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0xaa,0xbb,0xcc,0xdd,0xee,0xff}; + uint8_t out[64] = {0}; + legacyblockbroadcast(out, source); + for (int block = 0; block < 2; block++) { + if (memcmp(out + 32*block, source, 16) || memcmp(out + 32*block + 16, source, 16)) return block + 1; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "legacy_block_broadcast", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_broadcast_float.go b/amd64_lower_broadcast_float.go new file mode 100644 index 00000000..202bf421 --- /dev/null +++ b/amd64_lower_broadcast_float.go @@ -0,0 +1,104 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerScalarFloatBroadcast implements all Go 1.27 _yvbroadcastss and +// _yvbroadcastsd operand forms, including EVEX mask merge and zeroing. +func (c *amd64Ctx) lowerScalarFloatBroadcast(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits := 0 + switch baseOp { + case "VBROADCASTSS": + laneBits = 32 + case "VBROADCASTSD": + laneBits = 64 + default: + return false, false, nil + } + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("amd64 %s accepts only the .Z suffix: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 %s expects X-or-memory source, [K mask,] vector destination: %q", baseOp, ins.Raw) + } + dst := ins.Args[len(ins.Args)-1] + if dst.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects vector destination: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dst.Reg) + if byteWidth == 0 || laneBits == 64 && byteWidth == 16 { + return true, false, fmt.Errorf("amd64 %s destination is outside its Go 1.27 table: %q", baseOp, ins.Raw) + } + + masked := len(ins.Args) == 3 + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + var mask string + if masked { + maskArg := ins.Args[1] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, ok := amd64ParseKReg(maskArg.Reg) + if !ok || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + source := ins.Args[0] + var scalar string + if source.Kind == OpReg { + if !isAMD64XReg(source.Reg) { + return true, false, fmt.Errorf("amd64 %s source must be X or memory: %q", baseOp, ins.Raw) + } + bytesValue, err := c.loadX(source.Reg) + if err != nil { + return true, false, err + } + lanes := 128 / laneBits + values := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, bytesValue) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 0\n", low, lanes, laneBits, values) + scalar = "%" + low + } else { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s source must be X or memory: %q", baseOp, ins.Raw) + } + scalar, err = c.evalIntSized(source, amd64IntegerTypeForBits(laneBits)) + if err != nil { + return true, false, err + } + } + + lanes := byteWidth * 8 / laneBits + result := amd64SplatInteger(c, lanes, laneBits, scalar) + if masked { + oldBytes, err := c.loadPackedCompareBytes(dst, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(dst.Reg, byteWidth, "%"+out) +} diff --git a/amd64_lower_broadcast_mask.go b/amd64_lower_broadcast_mask.go new file mode 100644 index 00000000..3eeb2981 --- /dev/null +++ b/amd64_lower_broadcast_mask.go @@ -0,0 +1,61 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64MaskBroadcastSpec struct { + sourceBits int + laneBits int +} + +// amd64MaskBroadcastSpecs is the complete Go 1.27 _yvpbroadcastmb2q grammar. +// The low byte/word of a K register is zero-extended and broadcast into every +// qword/dword lane of an EVEX X, Y, or Z destination. +var amd64MaskBroadcastSpecs = map[Op]amd64MaskBroadcastSpec{ + "VPBROADCASTMB2Q": {sourceBits: 8, laneBits: 64}, + "VPBROADCASTMW2D": {sourceBits: 16, laneBits: 32}, +} + +func (c *amd64Ctx) lowerMaskRegisterBroadcast(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64MaskBroadcastSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed form in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects K source and X/Y/Z destination: %q", c.goarch, baseOp, ins.Raw) + } + if _, validMask := amd64ParseKReg(ins.Args[0].Reg); !validMask { + return true, false, fmt.Errorf("%s %s source must be K0-K7: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(ins.Args[1].Reg) + if (byteWidth != 16 && byteWidth != 32 && byteWidth != 64) || !c.isGoPackedVectorMoveRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go's EVEX X/Y/Z class: %q", c.goarch, baseOp, ins.Raw) + } + mask, err := c.loadK(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrow, mask, spec.sourceBits) + scalar := "%" + narrow + if spec.sourceBits != spec.laneBits { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i%d %s to i%d\n", wide, spec.sourceBits, scalar, spec.laneBits) + scalar = "%" + wide + } + lanes := byteWidth * 8 / spec.laneBits + result := amd64SplatInteger(c, lanes, spec.laneBits, scalar) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(ins.Args[1].Reg, byteWidth, "%"+out) +} diff --git a/amd64_lower_broadcast_mask_test.go b/amd64_lower_broadcast_mask_test.go new file mode 100644 index 00000000..38a3e7e3 --- /dev/null +++ b/amd64_lower_broadcast_mask_test.go @@ -0,0 +1,159 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64MaskBroadcastGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64MaskBroadcastSpec{ + "VPBROADCASTMB2Q": {sourceBits: 8, laneBits: 64}, + "VPBROADCASTMW2D": {sourceBits: 16, laneBits: 32}, + } + if len(amd64MaskBroadcastSpecs) != len(expected) { + t.Fatalf("mask-broadcast grammar has %d entries, want %d", len(amd64MaskBroadcastSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64MaskBroadcastSpecs[op]; !ok { + t.Errorf("mask-broadcast grammar omitted %s", op) + } else if got != want { + t.Errorf("mask-broadcast grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86MaskBroadcastCompleteFormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + xyLast, zLast := 31, 31 + if target.goarch == "386" { + zLast = 7 + } + var source strings.Builder + source.WriteString("TEXT maskbroadcastforms(SB),$0-0\n") + for _, op := range []string{"VPBROADCASTMB2Q", "VPBROADCASTMW2D"} { + fmt.Fprintf(&source, "\t%s K0, X%d\n", op, xyLast) + fmt.Fprintf(&source, "\t%s K7, Y%d\n", op, xyLast) + fmt.Fprintf(&source, "\t%s K1, Z%d\n", op, zLast) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: target.goarch, TargetTriple: target.triple, Sigs: map[string]FuncSig{"maskbroadcastforms": {Name: "maskbroadcastforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"<2 x i64>", "<8 x i32>", "<8 x i64>", "<16 x i32>"} { + if !strings.Contains(ir, want) { + t.Fatalf("mask broadcast lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "mask-broadcast-"+target.name+".ll", "mask-broadcast-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86MaskBroadcastRejectsFormsOutsideGoTable(t *testing.T) { + for _, instruction := range []string{ + "VPBROADCASTMB2Q AX, X0", + "VPBROADCASTMW2D K8, X0", + "VPBROADCASTMB2Q K1, K2", + "VPBROADCASTMW2D.Z K1, X0", + "VPBROADCASTMB2Q K1, K2, X0", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yvpbroadcastmb2q table", instruction) + } + }) + } +} + +func TestAMD64MaskBroadcastRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT maskbroadcastsemantics(SB),$0-16 + MOVQ out+0(FP), CX + MOVQ mask+8(FP), AX + KMOVQ AX, K1 + STC + VPBROADCASTMB2Q K1, X0 + MOVUPS X0, 0(CX) + VPBROADCASTMW2D K1, X1 + MOVUPS X1, 16(CX) + SETCS 32(CX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{"maskbroadcastsemantics": { + Name: "maskbroadcastsemantics", Args: []LLVMType{Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void maskbroadcastsemantics(uint8_t *, uint64_t); +int main(void) { + uint8_t out[33] = {0}; + uint64_t q[2]; uint32_t d[4]; + maskbroadcastsemantics(out, UINT64_C(0x1234beefa5)); + memcpy(q, out, 16); memcpy(d, out + 16, 16); + if (q[0] != UINT64_C(0xa5) || q[1] != UINT64_C(0xa5)) return 10; + for (int i = 0; i < 4; i++) if (d[i] != UINT32_C(0xefa5)) return 11 + i; + if (out[32] != 1) return 20; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "mask_broadcast_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_byte_shift.go b/amd64_lower_byte_shift.go new file mode 100644 index 00000000..10e40bd4 --- /dev/null +++ b/amd64_lower_byte_shift.go @@ -0,0 +1,119 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedByteShift implements Go 1.27's PSLLO/PSRLO aliases and +// PSLLDQ/PSRLDQ vector family. Every operation shifts bytes independently +// within each 128-bit lane and fills vacated bytes with zero. +func (c *amd64Ctx) lowerPackedByteShift(rawOp Op, ins Instr) (ok bool, terminated bool, err error) { + raw := strings.ToUpper(string(rawOp)) + if strings.Contains(raw, ".") { + base := strings.SplitN(raw, ".", 2)[0] + switch base { + case "PSLLO", "PSLLDQ", "PSRLO", "PSRLDQ", "VPSLLDQ", "VPSRLDQ": + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", base, ins.Raw) + } + return false, false, nil + } + left := raw == "PSLLO" || raw == "PSLLDQ" || raw == "VPSLLDQ" + switch raw { + case "PSLLO", "PSLLDQ", "PSRLO", "PSRLDQ": + if len(ins.Args) != 2 || !amd64SignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("amd64 %s expects $signed-imm8, X: %q", raw, ins.Raw) + } + destination := ins.Args[1] + if !c.isGoVEXVectorRegister(destination, 16, false) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's X register class: %q", raw, ins.Raw) + } + source, err := c.loadX(destination.Reg) + if err != nil { + return true, false, err + } + result := c.emitPackedByteShift(16, source, uint8(ins.Args[0].Imm), left) + return true, false, c.storeX(destination.Reg, result) + + case "VPSLLDQ", "VPSRLDQ": + if len(ins.Args) != 3 || !amd64VectorByteShiftImmediate(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s expects $imm8, X|Y|Z/mem, X|Y|Z: %q", raw, ins.Raw) + } + source, destination := ins.Args[1], ins.Args[2] + byteWidth := amd64VectorByteWidth(destination.Reg) + if destination.Kind != OpReg || byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's X/Y/Z register classes: %q", raw, ins.Raw) + } + if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("amd64 %s source must match its destination width: %q", raw, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s source must be a vector register or memory: %q", raw, ins.Raw) + } + + // The VEX rows admit signed or unsigned imm8 only for X/Y register + // sources. Memory, Z width, or a high vector register selects an EVEX + // row, whose immediate class is unsigned imm8. + if ins.Args[0].Imm < 0 && amd64PackedByteShiftRequiresEVEX(source, destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s EVEX form requires an unsigned imm8: %q", raw, ins.Raw) + } + value, err := c.loadPackedCompareBytes(source, byteWidth) + if err != nil { + return true, false, err + } + result := c.emitPackedByteShift(byteWidth, value, uint8(ins.Args[0].Imm), left) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, result) + default: + return false, false, nil + } +} + +func amd64SignedImmediate(operand Operand, bits int) bool { + if operand.Kind != OpImm || bits <= 0 || bits >= 63 { + return false + } + limit := int64(1) << (bits - 1) + return operand.Imm >= -limit && operand.Imm < limit +} + +func amd64VectorByteShiftImmediate(operand Operand) bool { + return operand.Kind == OpImm && operand.Imm >= -128 && operand.Imm <= 255 +} + +func amd64PackedByteShiftRequiresEVEX(source, destination Operand, byteWidth int) bool { + if byteWidth == 64 || isAMD64MemoryOperand(source) { + return true + } + for _, operand := range []Operand{source, destination} { + index, ok := amd64VectorRegisterIndex(operand.Reg, byteWidth) + if !ok || index >= 16 { + return true + } + } + return false +} + +func (c *amd64Ctx) emitPackedByteShift(byteWidth int, source string, count uint8, left bool) string { + if count >= 16 { + return "zeroinitializer" + } + result := "zeroinitializer" + for laneBase := 0; laneBase < byteWidth; laneBase += 16 { + for destinationByte := 0; destinationByte < 16; destinationByte++ { + sourceByte := destinationByte + int(count) + if left { + sourceByte = destinationByte - int(count) + } + if sourceByte < 0 || sourceByte >= 16 { + continue + } + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i8> %s, i32 %d\n", extracted, byteWidth, source, laneBase+sourceByte) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i8> %s, i8 %%%s, i32 %d\n", inserted, byteWidth, result, extracted, laneBase+destinationByte) + result = "%" + inserted + } + } + return result +} diff --git a/amd64_lower_byte_shift_test.go b/amd64_lower_byte_shift_test.go new file mode 100644 index 00000000..18b736fe --- /dev/null +++ b/amd64_lower_byte_shift_test.go @@ -0,0 +1,182 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86PackedByteShiftCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast := 15 + zSource, zDestination := 16, 31 + if target.goarch == "386" { + legacyLast = 7 + zSource, zDestination = 6, 7 + } + var source strings.Builder + source.WriteString("TEXT packedbyteshiftforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PSLLO", "PSLLDQ", "PSRLO", "PSRLDQ"} { + fmt.Fprintf(&source, "\t%s $-128, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s $127, X%d\n", op, legacyLast) + } + for _, op := range []string{"VPSLLDQ", "VPSRLDQ"} { + source.WriteString("\t" + op + " $-128, X0, X1\n") + source.WriteString("\t" + op + " $255, Y0, Y1\n") + source.WriteString("\t" + op + " $1, 8(AX), X2\n") + source.WriteString("\t" + op + " $2, 16(AX), Y2\n") + source.WriteString("\t" + op + " $3, X16, X31\n") + fmt.Fprintf(&source, "\t%s $4, Z%d, Z%d\n", op, zSource, zDestination) + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedbyteshiftforms": {Name: "packedbyteshiftforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-byte-shift-"+target.name+".ll", "packed-byte-shift-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedByteShiftRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PSLLO $-129, X0", + "PSLLDQ $128, X0", + "PSRLO $1, X16", + "PSRLDQ $1, Y0", + "PSLLDQ.Z $1, X0", + "VPSLLDQ $-129, X0, X1", + "VPSRLDQ $256, X0, X1", + "VPSLLDQ $-1, 8(AX), X1", + "VPSRLDQ $-1, X16, X1", + "VPSLLDQ $-1, Z0, Z1", + "VPSRLDQ $1, X0, Y1", + "VPSLLDQ $1, X0, K1, X1", + "VPSRLDQ.Z $1, X0, X1", + "VPSLLDQ $1, X0, (AX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedByteShiftRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PSLLO $1, X8", + "PSRLO $1, X15", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedByteShiftRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedByteShiftRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed byte-shift tables for %s", instruction, goarch) + } +} + +func TestAMD64PackedByteShiftRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT packedbyteshift(SB),NOSPLIT,$0-16 + MOVQ out+0(FP), AX + MOVQ in+8(FP), BX + VMOVDQU (BX), Y0 + VPSLLDQ $3, Y0, Y1 + VMOVDQU Y1, 0(AX) + VPSRLDQ $5, Y0, Y1 + VMOVDQU Y1, 32(AX) + VPSLLDQ $-1, Y0, Y1 + VMOVDQU Y1, 64(AX) + VZEROUPPER + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "packedbyteshift": {Name: "packedbyteshift", Args: []LLVMType{Ptr, Ptr}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +extern void packedbyteshift(uint8_t *, const uint8_t *); +int main(void) { + uint8_t in[32], out[96]; + for (int i = 0; i < 32; i++) in[i] = (uint8_t)(i+1); + for (int i = 0; i < 96; i++) out[i] = 0xff; + packedbyteshift(out, in); + for (int lane = 0; lane < 2; lane++) for (int i = 0; i < 16; i++) { + int base = lane*16; + uint8_t left = i < 3 ? 0 : in[base+i-3]; + uint8_t right = i+5 >= 16 ? 0 : in[base+i+5]; + if (out[base+i] != left) return 10+base+i; + if (out[32+base+i] != right) return 50+base+i; + if (out[64+base+i] != 0) return 90+base+i; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_byte_shift", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_bzhi.go b/amd64_lower_bzhi.go new file mode 100644 index 00000000..7e696c61 --- /dev/null +++ b/amd64_lower_bzhi.go @@ -0,0 +1,72 @@ +package plan9asm + +import "fmt" + +// lowerBZHI implements Go 1.27's complete _ybextrl operand row for BZHIL/Q: +// register index, register/memory source, and register destination. +func (c *amd64Ctx) lowerBZHI(op Op, ins Instr) (ok bool, terminated bool, err error) { + bits := 0 + switch op { + case "BZHIL": + bits = 32 + case "BZHIQ": + bits = 64 + default: + return false, false, nil + } + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects register index, register/memory source, and register destination: %q", c.goarch, op, ins.Raw) + } + index, source, destination := ins.Args[0], ins.Args[1], ins.Args[2] + if index.Kind != OpReg || !isX86YrlRegisterForArch(index.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s index is outside Go 1.27's Yrl class: %q", c.goarch, op, ins.Raw) + } + if source.Kind == OpReg { + if !isX86YrlRegisterForArch(source.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yrl class: %q", c.goarch, op, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + indexValue, err := c.evalIntSized(index, typ) + if err != nil { + return true, false, err + } + sourceValue, err := c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + indexLowByte := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, 255\n", indexLowByte, typ, indexValue) + indexInRange := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult %s %%%s, %d\n", indexInRange, typ, indexLowByte, bits) + safeIndex := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %d\n", safeIndex, typ, indexLowByte, bits-1) + one := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl %s 1, %%%s\n", one, typ, safeIndex) + partialMask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %%%s, -1\n", partialMask, typ, one) + mask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s -1\n", mask, indexInRange, typ, partialMask, typ) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %%%s\n", result, typ, sourceValue, mask) + if err := c.storeRegSized(destination.Reg, typ, "%"+result); err != nil { + return true, false, err + } + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", carry, indexInRange) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carry, c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, 0\n", zero, typ, result) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + sign := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt %s %%%s, 0\n", sign, typ, result) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", sign, c.flagsSltSlot) + return true, false, nil +} diff --git a/amd64_lower_bzhi_test.go b/amd64_lower_bzhi_test.go new file mode 100644 index 00000000..5562ca55 --- /dev/null +++ b/amd64_lower_bzhi_test.go @@ -0,0 +1,204 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86BZHICompleteFormsSource(goarch string) string { + var source strings.Builder + source.WriteString("DATA bzhidata+0(SB)/8, $1\n") + source.WriteString("GLOBL bzhidata(SB), $8\n") + source.WriteString("TEXT bzhiforms(SB),$0-0\n") + for _, width := range []string{"L", "Q"} { + op := "BZHI" + width + fmt.Fprintf(&source, "\t%s AX, BX, CX\n", op) + fmt.Fprintf(&source, "\t%s DX, 8(BX), SI\n", op) + fmt.Fprintf(&source, "\t%s CX, bzhidata(SB), DX\n", op) + if goarch == "amd64" { + fmt.Fprintf(&source, "\t%s R11, R12, R13\n", op) + } else { + fmt.Fprintf(&source, "\t%s AX, BX, SP\n", op) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86BZHICompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86BZHICompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"bzhiforms": {Name: "bzhiforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"shl i32", "shl i64", `"target-features"="+bmi2"`} { + if !strings.Contains(ir, want) { + t.Fatalf("BZHI lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "bzhi-"+target.name+".ll", "bzhi-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86BZHIRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "BZHIL $1, AX, BX"}, + {goarch: "amd64", instruction: "BZHIQ 0(AX), BX, CX"}, + {goarch: "amd64", instruction: "BZHIQ AX, $1, CX"}, + {goarch: "amd64", instruction: "BZHIL AX, BX, 0(CX)"}, + {goarch: "amd64", instruction: "BZHIQ X0, AX, BX"}, + {goarch: "amd64", instruction: "BZHIQ AX, X0, BX"}, + {goarch: "amd64", instruction: "BZHIQ AX, BX, X0"}, + {goarch: "amd64", instruction: "BZHIQ AX, BX"}, + {goarch: "amd64", instruction: "BZHIQ.Z AX, BX, CX"}, + {goarch: "386", instruction: "BZHIL R8, AX, BX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _ybextrl table", test.instruction) + } + }) + } +} + +func TestAMD64BZHIRuntimeSemanticsAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT bzhisemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + + MOVL $0x7fffffff, R8 + ADDL $1, R8 + MOVL $8, AX + MOVL $0x1234, BX + BZHIL AX, BX, CX + MOVQ CX, 0(DI) + SETCS 8(DI) + SETOS 9(DI) + SETEQ 10(DI) + SETMI 11(DI) + + MOVL $31, AX + MOVL $0x80000000, BX + BZHIL AX, BX, CX + MOVQ CX, 16(DI) + SETEQ 24(DI) + + MOVL $32, AX + MOVL $0x80000000, BX + BZHIL AX, BX, CX + MOVQ CX, 32(DI) + SETCS 40(DI) + SETMI 41(DI) + + MOVQ $0x1000000000000004, AX + MOVQ $-1, 48(DI) + BZHIQ AX, 48(DI), CX + MOVQ CX, 56(DI) + + MOVQ $64, AX + MOVQ $0x1234, BX + BZHIQ AX, BX, AX + MOVQ AX, 64(DI) + SETCS 72(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "bzhisemantics": { + Name: "bzhisemantics", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void bzhisemantics(uint8_t *); +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + uint8_t out[80] = {0}; + bzhisemantics(out); + if (load64(out + 0) != UINT64_C(0x34)) return 10; + if (out[8] != 0 || out[9] != 0 || out[10] != 0 || out[11] != 0) return 11; + if (load64(out + 16) != 0 || out[24] != 1) return 12; + if (load64(out + 32) != UINT64_C(0x80000000) || out[40] != 1 || out[41] != 1) return 13; + if (load64(out + 56) != UINT64_C(0xf)) return 14; + if (load64(out + 64) != UINT64_C(0x1234) || out[72] != 1) return 15; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "bzhi_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_cache_line.go b/amd64_lower_cache_line.go new file mode 100644 index 00000000..57dbc205 --- /dev/null +++ b/amd64_lower_cache_line.go @@ -0,0 +1,42 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var x86CacheLineWritebackOps = map[string]struct{}{ + "CLFLUSH": {}, + "CLFLUSHOPT": {}, + "CLWB": {}, +} + +// lowerCacheLineWriteback covers Go 1.27's complete x86 yclflush operand +// table. All three instructions accept exactly one Ym memory operand on both +// 386 and amd64. Preserve the architectural cache operation as inline +// assembly: replacing it with an ordinary load would lose ordering and +// persistence semantics. +func (c *amd64Ctx) lowerCacheLineWriteback(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + if _, ok := x86CacheLineWritebackOps[baseOp]; !ok { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 1 || !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s expects one Go 1.27 Ym memory operand: %q", c.goarch, baseOp, ins.Raw) + } + + ptr, ptrType, err := c.x86DescriptorMemoryPointer(ins.Args[0]) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s elementtype(i8) %s)\n", + strings.ToLower(baseOp)+" $0", "*m,~{memory},~{dirflag},~{fpsr},~{flags}", ptrType, ptr) + return true, false, nil +} diff --git a/amd64_lower_cache_line_test.go b/amd64_lower_cache_line_test.go new file mode 100644 index 00000000..816dd15a --- /dev/null +++ b/amd64_lower_cache_line_test.go @@ -0,0 +1,87 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateX86CacheLineWritebackCompleteGoAssemblerForms(t *testing.T) { + const source = ` +TEXT cachelinewriteback(SB),$16-0 + CLFLUSH (AX) + CLFLUSHOPT 8(BX) + CLWB local+0(SP) + RET +` + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + {goarch: "386", triple: "i686-pc-windows-msvc"}, + {goarch: "amd64", triple: "x86_64-apple-darwin"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.goarch+"/"+target.triple, func(t *testing.T) { + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: target.triple, Goarch: target.goarch, + Sigs: map[string]FuncSig{"cachelinewriteback": {Name: "cachelinewriteback", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, mnemonic := range []string{"clflush $0", "clflushopt $0", "clwb $0"} { + if !strings.Contains(ir, mnemonic) { + t.Fatalf("cache-line lowering omitted %q:\n%s", mnemonic, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "x86-cache-line-writeback.ll", "x86-cache-line-writeback.o", ir) + }) + } +} + +func TestTranslateX86CacheLineWritebackRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, goarch := range []string{"386", "amd64"} { + triple := "i386-unknown-linux-gnu" + if goarch == "amd64" { + triple = "x86_64-unknown-linux-gnu" + } + for _, instruction := range []string{ + "CLFLUSH", + "CLFLUSH AX", + "CLFLUSH $1", + "CLFLUSH (AX), (BX)", + "CLFLUSH.X (AX)", + "CLFLUSHOPT AX", + "CLWB AX", + } { + t.Run(goarch+"/"+strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + _, err = Translate(file, Options{ + TargetTriple: triple, Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + if err == nil { + t.Fatalf("Translate accepted form rejected by Go 1.27: %s", instruction) + } + }) + } + } +} diff --git a/amd64_lower_call_abi0_test.go b/amd64_lower_call_abi0_test.go new file mode 100644 index 00000000..8a0e0efc --- /dev/null +++ b/amd64_lower_call_abi0_test.go @@ -0,0 +1,133 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateX86ABI0CallUsesOutgoingStackFrame(t *testing.T) { + for _, target := range []struct { + goarch string + triple string + mov string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", mov: "MOVQ"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", mov: "MOVL"}, + } { + t.Run(target.goarch, func(t *testing.T) { + source := "TEXT ·abi0Caller(SB),$48-0\n" + + "\t" + target.mov + " $1, AX\n" + + "\t" + target.mov + " AX, 0(SP)\n" + + "\t" + target.mov + " $2, AX\n" + + "\t" + target.mov + " AX, 8(SP)\n" + + "\t" + target.mov + " $3, AX\n" + + "\t" + target.mov + " AX, 16(SP)\n" + + "\tMOVL $0x3fc00000, 24(SP)\n" + + "\t" + target.mov + " $4, AX\n" + + "\t" + target.mov + " AX, 32(SP)\n" + + "\tCALL ·abi0Callee(SB)\n" + + "\t" + target.mov + " 40(SP), AX\n" + + "\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + word := I64 + if target.goarch == "386" { + word = I32 + } + aggregate := LLVMType("{ " + string(Ptr) + ", " + string(word) + ", " + string(word) + " }") + callee := FuncSig{ + Name: "abi0Callee", + Args: []LLVMType{aggregate, LLVMType("float"), LLVMType("double")}, + Ret: word, + Frame: FrameLayout{ + Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: 0}, + {Offset: 8, Type: word, Index: 0, Field: 1}, + {Offset: 16, Type: word, Index: 0, Field: 2}, + {Offset: 24, Type: LLVMType("float"), Index: 1, Field: -1}, + {Offset: 32, Type: LLVMType("double"), Index: 2, Field: -1}, + }, + Results: []FrameSlot{{Offset: 40, Type: word, Index: 0, Field: -1}}, + }, + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "abi0Caller": {Name: "abi0Caller", Ret: Void}, + "abi0Callee": callee, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load ptr", "load float", "load double", "call " + string(word) + " @abi0Callee", "store " + string(word)} { + if !strings.Contains(ll, want) { + t.Fatalf("ABI0 call omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "abi0-call-"+target.goarch+".ll", "abi0-call-"+target.goarch+".o", ll) + }) + } +} + +func TestTranslateX86IndirectBranchCompatibilitySyntax(t *testing.T) { + const source = ` +TEXT ·indirectCallRegister(SB),$0-0 + CALL *AX + RET + +TEXT ·indirectCallSymbol(SB),$0-0 + CALL *·pointer(SB) + RET + +TEXT ·indirectJumpRegister(SB),$0-0 + JMP *AX +` + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + } { + t.Run(target.goarch, func(t *testing.T) { + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "indirectCallRegister": {Name: "indirectCallRegister", Ret: Void}, + "indirectCallSymbol": {Name: "indirectCallSymbol", Ret: Void}, + "indirectJumpRegister": {Name: "indirectJumpRegister", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if got := strings.Count(ll, "call i64 %"); got != 3 { + t.Fatalf("indirect CALL/JMP count = %d, want 3:\n%s", got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "indirect-branch-"+target.goarch+".ll", "indirect-branch-"+target.goarch+".o", ll) + }) + } +} diff --git a/amd64_lower_carry_flag_test.go b/amd64_lower_carry_flag_test.go new file mode 100644 index 00000000..2dd43d78 --- /dev/null +++ b/amd64_lower_carry_flag_test.go @@ -0,0 +1,133 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateX86CarryFlagControlCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT carryflagforms(SB),NOSPLIT,$0-0\n\tCLC\n\tSTC\n\tCMC\n\tRET\n") + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"carryflagforms": {Name: "carryflagforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"store i1 false, ptr %flags_cf", "store i1 true, ptr %flags_cf", "xor i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("carry flag lowering missing %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "carry-flag-"+target.name+".ll", "carry-flag-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86CarryFlagControlRejectsOperands(t *testing.T) { + for _, instruction := range []string{"CLC AX", "STC $1", "CMC 0(BX)", "CLC.Z"} { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's carry-control ynone table", instruction) + } + }) + } +} + +func TestAMD64CarryFlagControlRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT carryflagsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + CLC + MOVQ $0, AX + ADCQ $0, AX + MOVQ AX, 0(DI) + STC + MOVQ $0, AX + ADCQ $0, AX + MOVQ AX, 8(DI) + CLC + CMC + MOVQ $0, AX + ADCQ $0, AX + MOVQ AX, 16(DI) + STC + CMC + MOVQ $0, AX + ADCQ $0, AX + MOVQ AX, 24(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "carryflagsemantics": {Name: "carryflagsemantics", Args: []LLVMType{Ptr}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +extern void carryflagsemantics(uint64_t *); +int main(void) { + uint64_t out[4] = {9, 9, 9, 9}; + const uint64_t want[4] = {0, 1, 1, 0}; + carryflagsemantics(out); + for (int i = 0; i < 4; i++) if (out[i] != want[i]) return 10+i; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "carry_flag_semantics", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_carry_rotate_test.go b/amd64_lower_carry_rotate_test.go new file mode 100644 index 00000000..ac37f095 --- /dev/null +++ b/amd64_lower_carry_rotate_test.go @@ -0,0 +1,106 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86CarryRotateCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + widths := []string{"B", "W", "L"} + if target.goarch == "amd64" { + widths = append(widths, "Q") + } + var source strings.Builder + source.WriteString("TEXT carryrotateforms(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"RCL", "RCR"} { + for _, width := range widths { + op := stem + width + reg := "AX" + if width == "B" { + reg = "AH" + } + fmt.Fprintf(&source, "\t%s $1, %s\n", op, reg) + fmt.Fprintf(&source, "\t%s $255, 8(BX)\n", op) + fmt.Fprintf(&source, "\t%s CL, %s\n", op, reg) + fmt.Fprintf(&source, "\t%s CX, 16(BX)\n", op) + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "carryrotateforms": {Name: "carryrotateforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "carry-rotate-"+target.name+".ll", "carry-rotate-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86CarryRotateRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "RCLB $-1, AL", + "RCRW $256, AX", + "RCLL AX, BX", + "RCRQ (AX), BX", + "RCLQ $1, X0", + "RCRB.Z $1, AL", + "RCLL $1, AX, BX", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86CarryRotateRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "RCLQ $1, AX", + "RCRQ CL, (BX)", + "RCLB $1, SP", + "RCRL $1, R8", + } { + t.Run("386_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86CarryRotateRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86CarryRotateRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's RCL/RCR tables for %s", instruction, goarch) + } +} diff --git a/amd64_lower_clmul.go b/amd64_lower_clmul.go new file mode 100644 index 00000000..ffdc4eae --- /dev/null +++ b/amd64_lower_clmul.go @@ -0,0 +1,108 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedCarrylessMultiply implements Go 1.27's complete legacy and +// vector PCLMULQDQ tables. VPCLMULQDQ applies one independent 64x64->128 +// carryless multiplication to every 128-bit lane. +func (c *amd64Ctx) lowerPackedCarrylessMultiply(rawOp Op, ins Instr) (ok bool, terminated bool, err error) { + raw := strings.ToUpper(string(rawOp)) + if strings.Contains(raw, ".") { + base := strings.SplitN(raw, ".", 2)[0] + if base == "PCLMULQDQ" || base == "VPCLMULQDQ" { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", base, ins.Raw) + } + return false, false, nil + } + op := Op(raw) + if op != "PCLMULQDQ" && op != "VPCLMULQDQ" { + return false, false, nil + } + + if op == "PCLMULQDQ" { + if len(ins.Args) != 3 || !amd64UnsignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("amd64 PCLMULQDQ expects $imm8, X/m128, X: %q", ins.Raw) + } + source, destination := ins.Args[1], ins.Args[2] + if !c.isGoVEXVectorRegister(destination, 16, false) { + return true, false, fmt.Errorf("amd64 PCLMULQDQ destination is outside Go 1.27's X register class: %q", ins.Raw) + } + if !c.isGoVEXVectorRegister(source, 16, true) { + return true, false, fmt.Errorf("amd64 PCLMULQDQ source is outside Go 1.27's X/m128 class: %q", ins.Raw) + } + second, err := c.loadPackedCompareBytes(source, 16) + if err != nil { + return true, false, err + } + first, err := c.loadX(destination.Reg) + if err != nil { + return true, false, err + } + result := c.emitPackedCarrylessMultiply(16, first, second, uint8(ins.Args[0].Imm)) + return true, false, c.storeX(destination.Reg, result) + } + + // Go's 386 assembly parser rejects every four-operand VPCLMULQDQ form. + if c.goarch == "386" { + return true, false, fmt.Errorf("386 VPCLMULQDQ is outside Go 1.27's accepted instruction forms: %q", ins.Raw) + } + if len(ins.Args) != 4 || !amd64UnsignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("amd64 VPCLMULQDQ expects $imm8, X|Y|Z/mem, X|Y|Z, X|Y|Z: %q", ins.Raw) + } + destination := ins.Args[3] + byteWidth := amd64VectorByteWidth(destination.Reg) + if destination.Kind != OpReg || byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 VPCLMULQDQ destination is outside Go 1.27's X/Y/Z register classes: %q", ins.Raw) + } + rmSource, vSource := ins.Args[1], ins.Args[2] + if rmSource.Kind == OpReg { + if !c.isGoEVEXVectorRegister(rmSource, byteWidth) { + return true, false, fmt.Errorf("amd64 VPCLMULQDQ first source must match its destination width: %q", ins.Raw) + } + } else if !isAMD64MemoryOperand(rmSource) { + return true, false, fmt.Errorf("amd64 VPCLMULQDQ first source must be a vector register or memory: %q", ins.Raw) + } + if !c.isGoEVEXVectorRegister(vSource, byteWidth) { + return true, false, fmt.Errorf("amd64 VPCLMULQDQ second source must match its destination width: %q", ins.Raw) + } + second, err := c.loadPackedCompareBytes(rmSource, byteWidth) + if err != nil { + return true, false, err + } + first, err := c.loadPackedCompareBytes(vSource, byteWidth) + if err != nil { + return true, false, err + } + result := c.emitPackedCarrylessMultiply(byteWidth, first, second, uint8(ins.Args[0].Imm)) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, result) +} + +func (c *amd64Ctx) emitPackedCarrylessMultiply(byteWidth int, firstBytes, secondBytes string, immediate uint8) string { + qwords := byteWidth / 8 + first := c.newTmp() + second := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i64>\n", first, byteWidth, firstBytes, qwords) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i64>\n", second, byteWidth, secondBytes, qwords) + result := "zeroinitializer" + for lane := 0; lane < byteWidth/16; lane++ { + firstLane := c.newTmp() + secondLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i64> %%%s, <%d x i64> poison, <2 x i32> \n", firstLane, qwords, first, qwords, lane*2, lane*2+1) + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i64> %%%s, <%d x i64> poison, <2 x i32> \n", secondLane, qwords, second, qwords, lane*2, lane*2+1) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %%%s, <2 x i64> %%%s, i8 %d)\n", product, firstLane, secondLane, immediate) + for word := 0; word < 2; word++ { + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 %d\n", extracted, product, word) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i64> %s, i64 %%%s, i32 %d\n", inserted, qwords, result, extracted, lane*2+word) + result = "%" + inserted + } + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", bytes, qwords, result, byteWidth) + return "%" + bytes +} diff --git a/amd64_lower_clmul_test.go b/amd64_lower_clmul_test.go new file mode 100644 index 00000000..3104dc7b --- /dev/null +++ b/amd64_lower_clmul_test.go @@ -0,0 +1,179 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86PackedCarrylessMultiplyCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 15 + if target.goarch == "386" { + last = 7 + } + var source strings.Builder + fmt.Fprintf(&source, "TEXT carrylessmultiplyforms(SB),NOSPLIT,$0-0\n\tPCLMULQDQ $0, X0, X%d\n\tPCLMULQDQ $255, 8(AX), X%d\n", last, last) + if target.goarch == "amd64" { + source.WriteString("\tVPCLMULQDQ $0, X0, X1, X2\n") + source.WriteString("\tVPCLMULQDQ $1, 8(AX), X1, X2\n") + source.WriteString("\tVPCLMULQDQ $16, Y0, Y1, Y2\n") + source.WriteString("\tVPCLMULQDQ $17, 8(AX), Y1, Y2\n") + source.WriteString("\tVPCLMULQDQ $127, Z0, Z1, Z2\n") + source.WriteString("\tVPCLMULQDQ $128, 8(AX), Z1, Z2\n") + source.WriteString("\tVPCLMULQDQ $255, X16, X31, X0\n") + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "carrylessmultiplyforms": {Name: "carrylessmultiplyforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-carryless-multiply-"+target.name+".ll", "packed-carryless-multiply-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedCarrylessMultiplyRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PCLMULQDQ $-1, X0, X1", + "PCLMULQDQ $256, X0, X1", + "PCLMULQDQ $1, X16, X1", + "PCLMULQDQ $1, Y0, Y1", + "PCLMULQDQ.Z $1, X0, X1", + "PCLMULQDQ $1, X0, (AX)", + "VPCLMULQDQ $-1, X0, X1, X2", + "VPCLMULQDQ $256, X0, X1, X2", + "VPCLMULQDQ $1, X0, Y1, Y2", + "VPCLMULQDQ $1, X0, X1, K1, X2", + "VPCLMULQDQ.Z $1, X0, X1, X2", + "VPCLMULQDQ $1, X0, (AX), X2", + "VPCLMULQDQ $1, X0, X1, (AX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedCarrylessMultiplyRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PCLMULQDQ $1, X8, X0", + "PCLMULQDQ $1, X0, X8", + "VPCLMULQDQ $1, X0, X1, X2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedCarrylessMultiplyRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedCarrylessMultiplyRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's PCLMULQDQ/VPCLMULQDQ tables for %s", instruction, goarch) + } +} + +func TestAMD64PackedCarrylessMultiplyRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT carrylessmultiply(SB),NOSPLIT,$0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), BX + MOVQ b+16(FP), CX + VMOVDQU (BX), Y0 + VMOVDQU (CX), Y1 + VPCLMULQDQ $0x10, Y0, Y1, Y2 + VMOVDQU Y2, (AX) + VZEROUPPER + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "carrylessmultiply": {Name: "carrylessmultiply", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +extern void carrylessmultiply(uint64_t *, const uint64_t *, const uint64_t *); +static void clmul(uint64_t a, uint64_t b, uint64_t *lo, uint64_t *hi) { + uint64_t l = 0, h = 0; + for (unsigned i = 0; i < 64; i++) if ((b >> i) & 1) { + l ^= a << i; + if (i) h ^= a >> (64-i); + } + *lo = l; *hi = h; +} +int main(void) { + uint64_t a[4] = {0x123456789abcdef0ULL, 0xfedcba9876543210ULL, 0x1111222233334444ULL, 0x5555666677778888ULL}; + uint64_t b[4] = {0x0123456789abcdefULL, 0x0f1e2d3c4b5a6978ULL, 0x9999aaaabbbbccccULL, 0xddddeeeeffff0001ULL}; + uint64_t out[4] = {0}, want[4] = {0}; + clmul(b[0], a[1], &want[0], &want[1]); + clmul(b[2], a[3], &want[2], &want[3]); + carrylessmultiply(out, a, b); + for (int i = 0; i < 4; i++) if (out[i] != want[i]) return 10+i; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_carryless_multiply", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_cmov.go b/amd64_lower_cmov.go new file mode 100644 index 00000000..68cc626f --- /dev/null +++ b/amd64_lower_cmov.go @@ -0,0 +1,124 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerConditionalMove implements the complete Go 1.27 yml_rl conditional +// move table: every x86 condition code at W/L/Q width, with a register or +// memory source and a GP-register destination. +func (c *amd64Ctx) lowerConditionalMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + switch baseOp { + case "CMOVWCC", "CMOVWCS", "CMOVWEQ", "CMOVWGE", "CMOVWGT", "CMOVWHI", "CMOVWLE", "CMOVWLS", + "CMOVWLT", "CMOVWMI", "CMOVWNE", "CMOVWOC", "CMOVWOS", "CMOVWPC", "CMOVWPL", "CMOVWPS", + "CMOVLCC", "CMOVLCS", "CMOVLEQ", "CMOVLGE", "CMOVLGT", "CMOVLHI", "CMOVLLE", "CMOVLLS", + "CMOVLLT", "CMOVLMI", "CMOVLNE", "CMOVLOC", "CMOVLOS", "CMOVLPC", "CMOVLPL", "CMOVLPS", + "CMOVQCC", "CMOVQCS", "CMOVQEQ", "CMOVQGE", "CMOVQGT", "CMOVQHI", "CMOVQLE", "CMOVQLS", + "CMOVQLT", "CMOVQMI", "CMOVQNE", "CMOVQOC", "CMOVQOS", "CMOVQPC", "CMOVQPL", "CMOVQPS": + // handled below + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects register/memory source and register destination: %q", baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpReg && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s source must be a register or memory operand: %q", baseOp, ins.Raw) + } + if _, ok := amd64FullRegBase(ins.Args[1].Reg); !ok { + return true, false, fmt.Errorf("amd64 %s destination must be a GP register: %q", baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if _, ok := amd64FullRegBase(ins.Args[0].Reg); !ok { + return true, false, fmt.Errorf("amd64 %s register source must be a GP register: %q", baseOp, ins.Raw) + } + } + + ty := I64 + switch baseOp[4] { + case 'W': + ty = I16 + case 'L': + ty = I32 + case 'Q': + default: + panic("conditional move width precheck drift") + } + src, err := c.evalIntSized(ins.Args[0], ty) + if err != nil { + return true, false, err + } + cur, err := c.evalIntSized(ins.Args[1], ty) + if err != nil { + return true, false, err + } + condition, err := c.x86Condition(baseOp[5:]) + if err != nil { + return true, false, err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, %s %s, %s %s\n", selected, condition, ty, src, ty, cur) + return true, false, c.storeRegSized(ins.Args[1].Reg, ty, "%"+selected) +} + +func (c *amd64Ctx) x86Condition(code string) (string, error) { + invert := func(value string) string { + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", out, value) + return "%" + out + } + combine := func(instruction, left, right string) string { + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s i1 %s, %s\n", out, instruction, left, right) + return "%" + out + } + + switch code { + case "CC": + return invert(c.loadFlag(c.flagsCFSlot)), nil + case "CS": + return c.loadFlag(c.flagsCFSlot), nil + case "EQ": + return c.loadFlag(c.flagsZSlot), nil + case "GE", "GT", "LE", "LT": + signedLess := combine("xor", c.loadFlag(c.flagsSltSlot), c.loadFlag(c.flagsOFSlot)) + switch code { + case "LT": + return signedLess, nil + case "GE": + return invert(signedLess), nil + case "LE": + return combine("or", c.loadFlag(c.flagsZSlot), signedLess), nil + case "GT": + return invert(combine("or", c.loadFlag(c.flagsZSlot), signedLess)), nil + } + case "HI": + return combine("and", invert(c.loadFlag(c.flagsCFSlot)), invert(c.loadFlag(c.flagsZSlot))), nil + case "LS": + return combine("or", c.loadFlag(c.flagsCFSlot), c.loadFlag(c.flagsZSlot)), nil + case "MI": + return c.loadFlag(c.flagsSltSlot), nil + case "NE": + return invert(c.loadFlag(c.flagsZSlot)), nil + case "OC": + return invert(c.loadFlag(c.flagsOFSlot)), nil + case "OS": + return c.loadFlag(c.flagsOFSlot), nil + case "PC": + return invert(c.loadFlag(c.flagsPFSlot)), nil + case "PL": + return invert(c.loadFlag(c.flagsSltSlot)), nil + case "PS": + return c.loadFlag(c.flagsPFSlot), nil + } + return "", fmt.Errorf("unsupported x86 condition code %q", code) +} diff --git a/amd64_lower_cmpbt.go b/amd64_lower_cmpbt.go index 3b936985..abf0d84f 100644 --- a/amd64_lower_cmpbt.go +++ b/amd64_lower_cmpbt.go @@ -6,6 +6,9 @@ import ( ) func (c *amd64Ctx) lowerCmpBt(op Op, ins Instr) (ok bool, terminated bool, err error) { + if ok, terminated, err := c.lowerBitTestFamily(op, ins); ok { + return ok, terminated, err + } switch op { case "CMPB", "CMPW", "CMPL", "CMPQ": if len(ins.Args) != 2 { @@ -60,109 +63,6 @@ func (c *amd64Ctx) lowerCmpBt(op Op, ins Instr) (ok bool, terminated bool, err e c.setTestFlagsSized(ty, a, b) return true, false, nil - case "BTQ": - // BTQ $imm, reg (sets CF to selected bit) - if len(ins.Args) != 2 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 BTQ expects $imm, reg: %q", ins.Raw) - } - v, err := c.loadReg(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - amt := ins.Args[0].Imm & 63 - sh := c.newTmp() - fmt.Fprintf(c.b, " %%%s = lshr i64 %s, %d\n", sh, v, amt) - and := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %%%s, 1\n", and, sh) - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ne i64 %%%s, 0\n", cf, and) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCFSlot) - return true, false, nil - - case "BTSQ", "BTRQ": - // BTSQ/BTRQ src, dstReg|dstMem: CF = old bit, then set or - // clear the selected destination bit. - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("amd64 %s expects src, dst: %q", op, ins.Raw) - } - var amt string - var registerIndex string - switch ins.Args[0].Kind { - case OpImm: - amt = fmt.Sprintf("%d", ins.Args[0].Imm&63) - case OpReg: - av, err := c.loadReg(ins.Args[0].Reg) - if err != nil { - return true, false, err - } - m := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %s, 63\n", m, av) - amt = "%" + m - registerIndex = av - default: - return true, false, fmt.Errorf("amd64 %s expects imm/reg bit index: %q", op, ins.Raw) - } - - var dst string - var storeDst func(string) error - switch ins.Args[1].Kind { - case OpReg: - dv, err := c.loadReg(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - dst = dv - storeDst = func(v string) error { return c.storeReg(ins.Args[1].Reg, v) } - case OpMem: - addr, err := c.addrFromMem(ins.Args[1].Mem) - if err != nil { - return true, false, err - } - // A register bit index on a memory operand selects a bit in an - // unbounded bit string, not merely within the first qword. Adjust - // the address by floor(index/64)*8 and retain index&63 within it. - if registerIndex != "" { - word := c.newTmp() - fmt.Fprintf(c.b, " %%%s = ashr i64 %s, 6\n", word, registerIndex) - byteOff := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shl i64 %%%s, 3\n", byteOff, word) - adjusted := c.newTmp() - fmt.Fprintf(c.b, " %%%s = add i64 %s, %%%s\n", adjusted, addr, byteOff) - addr = "%" + adjusted - } - p := c.ptrFromAddrI64(addr) - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i64, ptr %s, align 1\n", ld, p) - dst = "%" + ld - storeDst = func(v string) error { - fmt.Fprintf(c.b, " store i64 %s, ptr %s, align 1\n", v, p) - return nil - } - default: - return true, false, fmt.Errorf("amd64 %s expects reg/mem dst: %q", op, ins.Raw) - } - - sh := c.newTmp() - fmt.Fprintf(c.b, " %%%s = lshr i64 %s, %s\n", sh, dst, amt) - and := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %%%s, 1\n", and, sh) - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ne i64 %%%s, 0\n", cf, and) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCFSlot) - one := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shl i64 1, %s\n", one, amt) - out := c.newTmp() - if op == "BTSQ" { - fmt.Fprintf(c.b, " %%%s = or i64 %s, %%%s\n", out, dst, one) - } else { - mask := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i64 %%%s, -1\n", mask, one) - fmt.Fprintf(c.b, " %%%s = and i64 %s, %%%s\n", out, dst, mask) - } - if err := storeDst("%" + out); err != nil { - return true, false, err - } - return true, false, nil } return false, false, nil } @@ -170,15 +70,27 @@ func (c *amd64Ctx) lowerCmpBt(op Op, ins Instr) (ok bool, terminated bool, err e func (c *amd64Ctx) setCmpFlagsSized(ty LLVMType, a, b string) { // Unlike most Plan 9 x86 instructions, CMP spells its operands in // comparison order: CMP a,b sets flags for a-b. + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s %s, %s\n", result, ty, a, b) zt := c.newTmp() fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, %s\n", zt, ty, a, b) fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zt, c.flagsZSlot) - slt := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp slt %s %s, %s\n", slt, ty, a, b) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", slt, c.flagsSltSlot) + sign := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt %s %%%s, 0\n", sign, ty, result) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", sign, c.flagsSltSlot) ult := c.newTmp() fmt.Fprintf(c.b, " %%%s = icmp ult %s %s, %s\n", ult, ty, a, b) fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", ult, c.flagsCFSlot) + xorOperands := c.newTmp() + xorResult := c.newTmp() + overflowBits := c.newTmp() + overflow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, %s\n", xorOperands, ty, a, b) + fmt.Fprintf(c.b, " %%%s = xor %s %s, %%%s\n", xorResult, ty, a, result) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", overflowBits, ty, xorOperands, xorResult) + fmt.Fprintf(c.b, " %%%s = icmp slt %s %%%s, 0\n", overflow, ty, overflowBits) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", overflow, c.flagsOFSlot) + c.setParityFlagSized(ty, "%"+result) } func (c *amd64Ctx) setTestFlagsSized(ty LLVMType, a, b string) { @@ -192,6 +104,8 @@ func (c *amd64Ctx) setTestFlagsSized(ty LLVMType, a, b string) { fmt.Fprintf(c.b, " %%%s = icmp slt %s %%%s, 0\n", slt, ty, and) fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", slt, c.flagsSltSlot) fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + c.setParityFlagSized(ty, "%"+and) } func (c *amd64Ctx) evalIntSized(op Operand, ty LLVMType) (string, error) { @@ -252,6 +166,13 @@ func (c *amd64Ctx) evalIntSized(op Operand, ty LLVMType) (string, error) { // Keep translation progressing with a conservative zero value. return "0", nil } + // Go's x86 syntax treats a bare integer as absolute memory. Keep + // this distinct from the '$' immediate spelling above. + if address, parseErr := parseInt(s); parseErr == nil { + t := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", t, ty, c.ptrFromAddrI64(fmt.Sprintf("%d", address))) + return "%" + t, nil + } if strings.HasSuffix(s, "(SB)") { p, err := c.ptrFromSB(s) if err != nil { diff --git a/amd64_lower_cmps_test.go b/amd64_lower_cmps_test.go new file mode 100644 index 00000000..a7ba9a61 --- /dev/null +++ b/amd64_lower_cmps_test.go @@ -0,0 +1,231 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86CMPSCompleteFormsSource(goarch string) string { + widths := []string{"B", "W", "L"} + if goarch == "amd64" { + widths = append(widths, "Q") + } + var source strings.Builder + source.WriteString("TEXT cmpsforms(SB),$0-0\n") + for _, width := range widths { + op := "CMPS" + width + fmt.Fprintf(&source, "\t%s\n", op) + fmt.Fprintf(&source, "\tCLD; REP; %s\n", op) + fmt.Fprintf(&source, "\tSTD; REPN; %s\n", op) + source.WriteString("\tCLD\n") + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86CMPSCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86CMPSCompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"cmpsforms": {Name: "cmpsforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, width := range []string{"b", "w", "l"} { + if want := "@__plan9asm_rep_cmps" + width; !strings.Contains(ir, want) { + t.Fatalf("CMPS lowering omitted %q:\n%s", want, ir) + } + } + if target.goarch == "amd64" && !strings.Contains(ir, "@__plan9asm_rep_cmpsq") { + t.Fatalf("CMPSQ lowering omitted qword helper:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "cmps-"+target.name+".ll", "cmps-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86CMPSRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "CMPSB AX"}, + {goarch: "amd64", instruction: "CMPSW AX, BX"}, + {goarch: "amd64", instruction: "CMPSL.Z"}, + {goarch: "386", instruction: "CMPSQ"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's CMPS ynone table", test.instruction) + } + }) + } +} + +func TestAMD64CMPSRuntimeSemanticsPrefixesDirectionAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT cmpssemantics(SB),NOSPLIT,$0-24 + MOVQ out+0(FP), R8 + MOVQ left+8(FP), R9 + MOVQ right+16(FP), R10 + + MOVQ R9, SI + MOVQ R10, DI + MOVQ $4, CX + CLD + REP; CMPSB + MOVQ SI, 0(R8) + MOVQ DI, 8(R8) + MOVQ CX, 16(R8) + SETCS 24(R8) + SETEQ 25(R8) + SETMI 26(R8) + SETOS 27(R8) + SETPS 28(R8) + + MOVQ R9, SI + ADDQ $8, SI + MOVQ R10, DI + ADDQ $8, DI + MOVQ $3, CX + REPN; CMPSW + MOVQ SI, 32(R8) + MOVQ DI, 40(R8) + MOVQ CX, 48(R8) + SETCS 56(R8) + SETEQ 57(R8) + + MOVQ R9, SI + ADDQ $28, SI + MOVQ R10, DI + ADDQ $28, DI + STD + CMPSL + CLD + MOVQ SI, 64(R8) + MOVQ DI, 72(R8) + SETCS 80(R8) + SETEQ 81(R8) + SETMI 82(R8) + SETOS 83(R8) + + MOVQ R9, SI + ADDQ $40, SI + MOVQ R10, DI + ADDQ $40, DI + CMPSQ + MOVQ SI, 88(R8) + MOVQ DI, 96(R8) + SETEQ 104(R8) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "cmpssemantics": { + Name: "cmpssemantics", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void cmpssemantics(uint8_t *, uint8_t *, uint8_t *); +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + uint8_t left[56] = {1,2,9,4}; + uint8_t right[56] = {1,2,3,4}; + const uint16_t leftw[3] = {5,7,8}, rightw[3] = {6,7,9}; + memcpy(left + 8, leftw, sizeof(leftw)); + memcpy(right + 8, rightw, sizeof(rightw)); + const uint32_t leftl[2] = {0,1}, rightl[2] = {0,2}; + memcpy(left + 24, leftl, sizeof(leftl)); + memcpy(right + 24, rightl, sizeof(rightl)); + const uint64_t q = UINT64_C(0x0123456789abcdef); + memcpy(left + 40, &q, sizeof(q)); + memcpy(right + 40, &q, sizeof(q)); + uint8_t out[112] = {0}; + cmpssemantics(out, left, right); + if (load64(out+0) != (uintptr_t)(left+3)) return 10; + if (load64(out+8) != (uintptr_t)(right+3)) return 11; + if (load64(out+16) != 1) return 12; + if (out[24] != 0 || out[25] != 0 || out[26] != 0 || out[27] != 0 || out[28] != 1) return 11; + if (load64(out+32) != (uintptr_t)(left+12) || load64(out+40) != (uintptr_t)(right+12) || load64(out+48) != 1) return 12; + if (out[56] != 0 || out[57] != 1) return 13; + if (load64(out+64) != (uintptr_t)(left+24) || load64(out+72) != (uintptr_t)(right+24)) return 14; + if (out[80] != 1 || out[81] != 0 || out[82] != 1 || out[83] != 0) return 15; + if (load64(out+88) != (uintptr_t)(left+48) || load64(out+96) != (uintptr_t)(right+48) || out[104] != 1) return 16; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "cmps_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_cmpxchg.go b/amd64_lower_cmpxchg.go new file mode 100644 index 00000000..721f93cd --- /dev/null +++ b/amd64_lower_cmpxchg.go @@ -0,0 +1,325 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerCompareExchange implements every operand row in Go 1.27's yrb_mb, +// yrl_ml, and yscond tables for the CMPXCHG family. +func (c *amd64Ctx) lowerCompareExchange(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + kind, bits, recognized := amd64CompareExchangeProperties(baseOp) + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && (bits == 64 && kind == "scalar" || bits == 128) { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + + switch kind { + case "scalar": + return c.lowerScalarCompareExchange(baseOp, bits, ins) + case "pair": + return c.lowerPairCompareExchange(baseOp, bits, ins) + default: + return true, false, fmt.Errorf("internal error: unknown CMPXCHG kind %q", kind) + } +} + +func amd64CompareExchangeProperties(op string) (kind string, bits int, ok bool) { + switch op { + case "CMPXCHGB": + return "scalar", 8, true + case "CMPXCHGW": + return "scalar", 16, true + case "CMPXCHGL": + return "scalar", 32, true + case "CMPXCHGQ": + return "scalar", 64, true + case "CMPXCHG8B": + return "pair", 64, true + case "CMPXCHG16B": + return "pair", 128, true + default: + return "", 0, false + } +} + +func (c *amd64Ctx) lowerScalarCompareExchange(baseOp string, bits int, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects register source and register/memory destination: %q", c.goarch, baseOp, ins.Raw) + } + registerAllowed := func(reg Reg) bool { + if bits == 8 { + return isGoYmbRegisterForArch(reg, c.goarch) + } + return isX86YrlRegisterForArch(reg, c.goarch) + } + source, destination := ins.Args[0], ins.Args[1] + if source.Kind != OpReg || !registerAllowed(source.Reg) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yrb/Yrl class: %q", c.goarch, baseOp, ins.Raw) + } + if destination.Kind == OpReg { + if !registerAllowed(destination.Reg) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Ymb/Yml class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Ymb/Yml class: %q", c.goarch, baseOp, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + accumulator, err := c.loadReg(AX) + if err != nil { + return true, false, err + } + expected, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, typ) + if err != nil { + return true, false, err + } + desired, err := c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + + var old, success string + if destination.Kind == OpReg { + old, err = c.evalIntSized(destination, typ) + if err != nil { + return true, false, err + } + equal := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, %s\n", equal, typ, expected, old) + success = "%" + equal + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, %s %s, %s %s\n", selected, success, typ, desired, typ, old) + if err := c.storeRegSized(destination.Reg, typ, "%"+selected); err != nil { + return true, false, err + } + } else { + ptr, ptrType, err := c.compareExchangePointer(destination) + if err != nil { + return true, false, err + } + align := bits / 8 + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = cmpxchg %s %s, %s %s, %s %s seq_cst seq_cst, align %d\n", result, ptrType, ptr, typ, expected, typ, desired, align) + oldName := c.newTmp() + successName := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue { %s, i1 } %%%s, 0\n", oldName, typ, result) + fmt.Fprintf(c.b, " %%%s = extractvalue { %s, i1 } %%%s, 1\n", successName, typ, result) + old, success = "%"+oldName, "%"+successName + } + + // On failure the accumulator receives the destination. On success it is not + // written at all. In particular, CMPXCHGL zero-extends EAX only on failure; + // a successful compare must preserve the original high half of RAX. + if destination.Kind != OpReg || !amd64CompareExchangeDestinationIsAccumulator(destination.Reg, bits) { + if err := c.storeScalarCompareExchangeAccumulator(accumulator, expected, old, success, typ); err != nil { + return true, false, err + } + } + difference := c.newTmp() + // CMPXCHG compares the accumulator with the destination, so its arithmetic + // flags come from accumulator - destination (Intel's temporary result). + fmt.Fprintf(c.b, " %%%s = sub %s %s, %s\n", difference, typ, expected, old) + c.setScalarAddSubFlags(typ, false, expected, old, "%"+difference) + // Keep the equality result authoritative even for unusual aliasing forms. + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", success, c.flagsZSlot) + return true, false, nil +} + +func (c *amd64Ctx) storeScalarCompareExchangeAccumulator(accumulator, expected, failureValue, success string, typ LLVMType) error { + if typ == I32 { + failure64 := c.newTmp() + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", failure64, failureValue) + fmt.Fprintf(c.b, " %%%s = select i1 %s, i64 %s, i64 %%%s\n", selected, success, accumulator, failure64) + return c.storeReg(AX, "%"+selected) + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, %s %s, %s %s\n", selected, success, typ, expected, typ, failureValue) + return c.storeRegSized(AX, typ, "%"+selected) +} + +func amd64CompareExchangeDestinationIsAccumulator(reg Reg, bits int) bool { + if bits == 8 { + return reg == AX || reg == AL + } + return reg == AX +} + +func (c *amd64Ctx) lowerPairCompareExchange(baseOp string, bits int, ins Instr) (bool, bool, error) { + if len(ins.Args) != 1 { + return true, false, fmt.Errorf("%s %s expects one Ymb register/memory operand: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[0] + if destination.Kind == OpReg { + if !isGoYmbRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s operand is outside Go 1.27's Ymb class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s %s operand is outside Go 1.27's Ymb class: %q", c.goarch, baseOp, ins.Raw) + } + + ax, err := c.loadReg(AX) + if err != nil { + return true, false, err + } + dx, err := c.loadReg(DX) + if err != nil { + return true, false, err + } + bx, err := c.loadReg(BX) + if err != nil { + return true, false, err + } + cx, err := c.loadReg(CX) + if err != nil { + return true, false, err + } + expected := c.compareExchangeJoinPair(ax, dx, bits) + desired := c.compareExchangeJoinPair(bx, cx, bits) + pairType := LLVMType("i64") + align := 8 + if bits == 128 { + pairType = LLVMType("i128") + align = 16 + } + + var old, success string + if destination.Kind == OpReg { + base, _, _ := amd64ByteRegBase(destination.Reg) + old64, err := c.loadReg(base) + if err != nil { + return true, false, err + } + old = old64 + if bits == 128 { + widened := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i64 %s to i128\n", widened, old64) + old = "%" + widened + } + equal := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, %s\n", equal, pairType, expected, old) + success = "%" + equal + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, %s %s, %s %s\n", selected, success, pairType, desired, pairType, old) + selected64 := "%" + selected + if bits == 128 { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", truncated, selected) + selected64 = "%" + truncated + } + if err := c.storeReg(base, selected64); err != nil { + return true, false, err + } + } else { + ptr, ptrType, err := c.compareExchangePointer(destination) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = cmpxchg %s %s, %s %s, %s %s seq_cst seq_cst, align %d\n", result, ptrType, ptr, pairType, expected, pairType, desired, align) + oldName := c.newTmp() + successName := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue { %s, i1 } %%%s, 0\n", oldName, pairType, result) + fmt.Fprintf(c.b, " %%%s = extractvalue { %s, i1 } %%%s, 1\n", successName, pairType, result) + old, success = "%"+oldName, "%"+successName + } + + oldLow, oldHigh := c.compareExchangeSplitPair(old, bits) + if err := c.storeCompareExchangePairAccumulator(AX, ax, oldLow, success, bits); err != nil { + return true, false, err + } + if err := c.storeCompareExchangePairAccumulator(DX, dx, oldHigh, success, bits); err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", success, c.flagsZSlot) + return true, false, nil +} + +func (c *amd64Ctx) compareExchangeJoinPair(low, high string, bits int) string { + partType := LLVMType("i32") + pairType := LLVMType("i64") + shift := 32 + if bits == 128 { + partType = I64 + pairType = LLVMType("i128") + shift = 64 + } + lowPart, highPart := low, high + if partType == I32 { + lowPart = c.truncI64(low, I32) + highPart = c.truncI64(high, I32) + } + lowWide := c.newTmp() + highWide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", lowWide, partType, lowPart, pairType) + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", highWide, partType, highPart, pairType) + shifted := c.newTmp() + joined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl %s %%%s, %d\n", shifted, pairType, highWide, shift) + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %%%s\n", joined, pairType, shifted, lowWide) + return "%" + joined +} + +func (c *amd64Ctx) compareExchangeSplitPair(pair string, bits int) (low, high string) { + pairType := LLVMType("i64") + partType := LLVMType("i32") + shift := 32 + if bits == 128 { + pairType = LLVMType("i128") + partType = I64 + shift = 64 + } + lowName := c.newTmp() + highShift := c.newTmp() + highName := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", lowName, pairType, pair, partType) + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %d\n", highShift, pairType, pair, shift) + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", highName, pairType, highShift, partType) + return "%" + lowName, "%" + highName +} + +func (c *amd64Ctx) storeCompareExchangePairAccumulator(reg Reg, original, failurePart, success string, bits int) error { + failure64 := failurePart + if bits == 64 { + widened := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", widened, failurePart) + failure64 = "%" + widened + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i64 %s, i64 %s\n", selected, success, original, failure64) + return c.storeReg(reg, "%"+selected) +} + +func (c *amd64Ctx) compareExchangePointer(destination Operand) (ptr, ptrType string, err error) { + switch destination.Kind { + case OpMem: + return c.ptrFromMem(destination.Mem) + case OpSym: + ptr, err := c.ptrFromSB(destination.Sym) + return ptr, "ptr", err + case OpFP: + if c.classicFrame != "" { + return c.classicFramePtr(destination.FPOffset), "ptr", nil + } + if ptr := c.fpParamAlloca[destination.FPOffset]; ptr != "" { + return ptr, "ptr", nil + } + if ptr, _, ok := c.fpResultAlloca(destination.FPOffset); ok { + return ptr, "ptr", nil + } + return "", "", fmt.Errorf("CMPXCHG FP operand has no mutable slot at +%d(FP)", destination.FPOffset) + default: + return "", "", fmt.Errorf("CMPXCHG expected memory destination, got %s", destination.String()) + } +} diff --git a/amd64_lower_compare_float.go b/amd64_lower_compare_float.go new file mode 100644 index 00000000..b8dcc2c4 --- /dev/null +++ b/amd64_lower_compare_float.go @@ -0,0 +1,408 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +// lowerFloatingCompare implements the complete Go 1.27 floating-point +// immediate-compare family: legacy CMP{PD,PS,SD,SS}, the VEX vector-result +// forms, and the EVEX K-result forms of VCMP{PD,PS,SD,SS}. +func (c *amd64Ctx) lowerFloatingCompare(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + elemBits, packed, vector, recognized := amd64FloatingCompareProperties(baseOp) + if !recognized { + return false, false, nil + } + if !vector { + return c.lowerLegacyFloatingCompare(baseOp, suffix, elemBits, packed, ins) + } + return c.lowerVectorFloatingCompare(baseOp, suffix, elemBits, packed, ins) +} + +func amd64FloatingCompareProperties(op string) (elemBits int, packed, vector, ok bool) { + switch op { + case "CMPPD": + return 64, true, false, true + case "CMPPS": + return 32, true, false, true + case "CMPSD": + return 64, false, false, true + case "CMPSS": + return 32, false, false, true + case "VCMPPD": + return 64, true, true, true + case "VCMPPS": + return 32, true, true, true + case "VCMPSD": + return 64, false, true, true + case "VCMPSS": + return 32, false, true, true + default: + return 0, false, false, false + } +} + +func (c *amd64Ctx) lowerLegacyFloatingCompare(baseOp, suffix string, elemBits int, packed bool, ins Instr) (bool, bool, error) { + if suffix != "" { + return true, false, fmt.Errorf("amd64 %s has no instruction suffixes in Go 1.27's yxcmpi table: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects X/m, X, signed-imm8: %q", baseOp, ins.Raw) + } + immediate, ok := amd64LegacyFloatingCompareImmediate(ins.Args[2]) + if !ok { + return true, false, fmt.Errorf("amd64 %s expects X/m, X, signed-imm8: %q", baseOp, ins.Raw) + } + if immediate < -128 || immediate > 127 { + return true, false, fmt.Errorf("amd64 %s immediate is outside Go 1.27's signed-imm8 class: %q", baseOp, ins.Raw) + } + if !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("amd64 %s destination is outside the Go 1.27 X-register class for %s: %q", baseOp, c.goarch, ins.Raw) + } + if ins.Args[0].Kind == OpReg && !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("amd64 %s register source is outside the Go 1.27 X-register class for %s: %q", baseOp, c.goarch, ins.Raw) + } + if ins.Args[0].Kind != OpReg && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s first operand must be X or memory: %q", baseOp, ins.Raw) + } + + predicate := amd64FloatingComparePredicate(uint8(immediate) & 7) + if packed { + return true, false, c.emitFloatingCompareVector(elemBits, 16, ins.Args[0], ins.Args[1], ins.Args[1].Reg, predicate, false) + } + return true, false, c.emitFloatingCompareScalarVector(elemBits, ins.Args[0], ins.Args[1], ins.Args[1].Reg, predicate) +} + +func amd64LegacyFloatingCompareImmediate(arg Operand) (int64, bool) { + if arg.Kind == OpImm { + return arg.Imm, true + } + // The pre-Go-1.5 x86 assembler wrote CMP{PD,PS,SD,SS} predicates as a + // bare decimal operand. Keep this compatibility confined to the legacy + // compare family's predicate position instead of accepting bare integers + // as immediates throughout the parser. + var text string + switch arg.Kind { + case OpIdent: + text = arg.Ident + case OpSym: + text = arg.Sym + default: + return 0, false + } + value, err := strconv.ParseInt(strings.TrimSpace(text), 10, 64) + return value, err == nil +} + +func (c *amd64Ctx) lowerVectorFloatingCompare(baseOp, suffix string, elemBits int, packed bool, ins Instr) (bool, bool, error) { + if c.goarch != "amd64" { + return true, false, fmt.Errorf("%s %s is absent from Go 1.27's 386 assembler forms: %q", c.goarch, baseOp, ins.Raw) + } + if suffix != "" && suffix != "BCST" && suffix != "SAE" { + return true, false, fmt.Errorf("amd64 %s suffix is absent from its Go 1.27 EVEX encoding: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 4 && len(ins.Args) != 5 { + return true, false, fmt.Errorf("amd64 %s expects unsigned-imm8, src1, src2, [K mask,] destination: %q", baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("amd64 %s first operand must be Go 1.27's unsigned-imm8 class: %q", baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s destination must be a vector or K register: %q", baseOp, ins.Raw) + } + predicate := amd64FloatingComparePredicate(uint8(ins.Args[0].Imm) & 31) + + if _, isK := amd64ParseKReg(dstArg.Reg); !isK { + return c.lowerVEXFloatingCompareVectorResult(baseOp, suffix, elemBits, packed, predicate, ins) + } + return c.lowerEVEXFloatingCompareMaskResult(baseOp, suffix, elemBits, packed, predicate, ins) +} + +func (c *amd64Ctx) lowerVEXFloatingCompareVectorResult(baseOp, suffix string, elemBits int, packed bool, predicate string, ins Instr) (bool, bool, error) { + if suffix != "" || len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 %s VEX vector-result form has no mask or suffix: %q", baseOp, ins.Raw) + } + dst := ins.Args[3].Reg + byteWidth := amd64VectorByteWidth(dst) + if !packed && byteWidth != 16 { + return true, false, fmt.Errorf("amd64 %s scalar VEX form requires an X destination: %q", baseOp, ins.Raw) + } + if packed && byteWidth != 16 && byteWidth != 32 { + return true, false, fmt.Errorf("amd64 %s packed VEX form requires an X or Y destination: %q", baseOp, ins.Raw) + } + if !amd64VEXVectorRegister(ins.Args[2], byteWidth) || !amd64VEXVectorRegister(dstArgOperand(dst), byteWidth) { + return true, false, fmt.Errorf("amd64 %s VEX source and destination registers must match and be numbered 0-15: %q", baseOp, ins.Raw) + } + if ins.Args[1].Kind == OpReg { + if !amd64VEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("amd64 %s VEX first source must match the destination width and be numbered 0-15: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s VEX first source must be a vector register or memory: %q", baseOp, ins.Raw) + } + if packed { + return true, false, c.emitFloatingCompareVector(elemBits, byteWidth, ins.Args[1], ins.Args[2], dst, predicate, false) + } + return true, false, c.emitFloatingCompareScalarVector(elemBits, ins.Args[1], ins.Args[2], dst, predicate) +} + +func (c *amd64Ctx) lowerEVEXFloatingCompareMaskResult(baseOp, suffix string, elemBits int, packed bool, predicate string, ins Instr) (bool, bool, error) { + dst := ins.Args[len(ins.Args)-1].Reg + if len(ins.Args) == 5 { + mask := ins.Args[3] + if mask.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + index, ok := amd64ParseKReg(mask.Reg) + if !ok || index == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + } + second := ins.Args[2] + if second.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s EVEX second source must be a vector register: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(second.Reg) + if !packed && byteWidth != 16 { + return true, false, fmt.Errorf("amd64 %s scalar EVEX form requires an X second source: %q", baseOp, ins.Raw) + } + if packed && byteWidth != 16 && byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("amd64 %s packed EVEX form requires an X, Y, or Z second source: %q", baseOp, ins.Raw) + } + if !amd64EVEXVectorRegister(second, byteWidth) { + return true, false, fmt.Errorf("amd64 %s EVEX second source register is invalid: %q", baseOp, ins.Raw) + } + first := ins.Args[1] + if first.Kind == OpReg { + if !amd64EVEXVectorRegister(first, byteWidth) { + return true, false, fmt.Errorf("amd64 %s EVEX first source must match the second source width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 %s EVEX first source must be a vector register or memory: %q", baseOp, ins.Raw) + } + + broadcast := suffix == "BCST" + if broadcast && (!packed || !isAMD64MemoryOperand(first)) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a packed EVEX memory source: %q", baseOp, ins.Raw) + } + if suffix == "SAE" { + if isAMD64MemoryOperand(first) || (packed && byteWidth != 64) { + return true, false, fmt.Errorf("amd64 %s.SAE requires the Go 1.27 EVEX register-source width: %q", baseOp, ins.Raw) + } + } + + lanes := 1 + var compared string + var err error + if packed { + lanes = byteWidth * 8 / elemBits + compared, err = c.compareFloatingVector(elemBits, byteWidth, first, second, predicate, broadcast) + } else { + compared, err = c.compareFloatingScalar(elemBits, first, second, predicate) + } + if err != nil { + return true, false, err + } + result := c.packFloatingCompareMask(compared, lanes) + if len(ins.Args) == 5 { + writeMask, err := c.loadK(ins.Args[3].Reg) + if err != nil { + return true, false, err + } + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %s\n", masked, result, writeMask) + result = "%" + masked + } + return true, false, c.storeK(dst, result) +} + +func (c *amd64Ctx) isGoLegacyXReg(r Reg) bool { + index, ok := amd64ParseXReg(r) + if !ok { + return false + } + if c.goarch == "386" { + return index < 8 + } + return index < 16 +} + +func dstArgOperand(r Reg) Operand { + return Operand{Kind: OpReg, Reg: r} +} + +func amd64VEXVectorRegister(op Operand, byteWidth int) bool { + if op.Kind != OpReg || amd64VectorByteWidth(op.Reg) != byteWidth { + return false + } + index, ok := amd64VectorRegisterIndex(op.Reg, byteWidth) + return ok && index < 16 +} + +func amd64EVEXVectorRegister(op Operand, byteWidth int) bool { + if op.Kind != OpReg || amd64VectorByteWidth(op.Reg) != byteWidth { + return false + } + index, ok := amd64VectorRegisterIndex(op.Reg, byteWidth) + return ok && index < 32 +} + +func amd64VectorRegisterIndex(r Reg, byteWidth int) (int, bool) { + switch byteWidth { + case 16: + return amd64ParseXReg(r) + case 32: + return amd64ParseYReg(r) + case 64: + return amd64ParseZReg(r) + default: + return 0, false + } +} + +func amd64FloatingComparePredicate(immediate uint8) string { + return [...]string{ + "oeq", "olt", "ole", "uno", "une", "uge", "ugt", "ord", + "ueq", "ult", "ule", "false", "one", "oge", "ogt", "true", + "oeq", "olt", "ole", "uno", "une", "uge", "ugt", "ord", + "ueq", "ult", "ule", "false", "one", "oge", "ogt", "true", + }[immediate&31] +} + +func (c *amd64Ctx) emitFloatingCompareVector(elemBits, byteWidth int, first, second Operand, dst Reg, predicate string, broadcast bool) error { + compared, err := c.compareFloatingVector(elemBits, byteWidth, first, second, predicate, broadcast) + if err != nil { + return err + } + lanes := byteWidth * 8 / elemBits + allBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext <%d x i1> %s to <%d x i%d>\n", allBits, lanes, compared, lanes, elemBits) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <%d x i8>\n", bytesValue, lanes, elemBits, allBits, byteWidth) + return c.storeVectorBytes(dst, byteWidth, "%"+bytesValue) +} + +func (c *amd64Ctx) compareFloatingVector(elemBits, byteWidth int, first, second Operand, predicate string, broadcast bool) (string, error) { + lanes := byteWidth * 8 / elemBits + vectorType := amd64FloatingVectorType(lanes, elemBits) + var firstValue string + var err error + if broadcast { + firstValue, err = c.loadFloatingScalarOperand(first, elemBits) + if err == nil { + firstValue = c.splatFloatingScalar(firstValue, lanes, elemBits) + } + } else { + firstValue, err = c.loadFloatingVectorOperand(first, byteWidth, lanes, elemBits) + } + if err != nil { + return "", err + } + secondValue, err := c.loadFloatingVectorOperand(second, byteWidth, lanes, elemBits) + if err != nil { + return "", err + } + compared := c.newTmp() + // Go/Plan 9 lists the Intel r/m source first: compare second with first. + fmt.Fprintf(c.b, " %%%s = fcmp %s %s %s, %s\n", compared, predicate, vectorType, secondValue, firstValue) + return "%" + compared, nil +} + +func (c *amd64Ctx) emitFloatingCompareScalarVector(elemBits int, first, second Operand, dst Reg, predicate string) error { + compared, err := c.compareFloatingScalar(elemBits, first, second, predicate) + if err != nil { + return err + } + mask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext i1 %s to i%d\n", mask, compared, elemBits) + secondBytes, err := c.loadPackedCompareBytes(second, 16) + if err != nil { + return err + } + lanes := 128 / elemBits + integerVector := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x i%d>\n", integerVector, secondBytes, lanes, elemBits) + updated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %%%s, i%d %%%s, i32 0\n", updated, lanes, elemBits, integerVector, elemBits, mask) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", bytesValue, lanes, elemBits, updated) + return c.storeX(dst, "%"+bytesValue) +} + +func (c *amd64Ctx) compareFloatingScalar(elemBits int, first, second Operand, predicate string) (string, error) { + firstValue, err := c.loadFloatingScalarOperand(first, elemBits) + if err != nil { + return "", err + } + secondValue, err := c.loadFloatingScalarOperand(second, elemBits) + if err != nil { + return "", err + } + compared := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp %s %s %s, %s\n", compared, predicate, amd64FloatingScalarType(elemBits), secondValue, firstValue) + return "%" + compared, nil +} + +func (c *amd64Ctx) loadFloatingVectorOperand(op Operand, byteWidth, lanes, elemBits int) (string, error) { + bytesValue, err := c.loadPackedCompareBytes(op, byteWidth) + if err != nil { + return "", err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", value, byteWidth, bytesValue, amd64FloatingVectorType(lanes, elemBits)) + return "%" + value, nil +} + +func (c *amd64Ctx) loadFloatingScalarOperand(op Operand, elemBits int) (string, error) { + if elemBits == 64 { + return c.evalF64(op) + } + return c.evalF32(op) +} + +func (c *amd64Ctx) splatFloatingScalar(value string, lanes, elemBits int) string { + vectorType := amd64FloatingVectorType(lanes, elemBits) + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, %s %s, i32 %d\n", inserted, vectorType, result, amd64FloatingScalarType(elemBits), value, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) packFloatingCompareMask(compared string, lanes int) string { + if lanes == 1 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %s to i64\n", wide, compared) + return "%" + wide + } + packedType := fmt.Sprintf("i%d", lanes) + packed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i1> %s to %s\n", packed, lanes, compared, packedType) + if lanes == 64 { + return "%" + packed + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %%%s to i64\n", wide, packedType, packed) + return "%" + wide +} + +func amd64FloatingScalarType(elemBits int) string { + if elemBits == 64 { + return "double" + } + return "float" +} + +func amd64FloatingVectorType(lanes, elemBits int) string { + return fmt.Sprintf("<%d x %s>", lanes, amd64FloatingScalarType(elemBits)) +} diff --git a/amd64_lower_compare_float_historical_test.go b/amd64_lower_compare_float_historical_test.go new file mode 100644 index 00000000..f7b50dad --- /dev/null +++ b/amd64_lower_compare_float_historical_test.go @@ -0,0 +1,52 @@ +package plan9asm + +import "testing" + +func TestTranslateAMD64LegacyFloatingCompareHistoricalBarePredicate(t *testing.T) { + source := "TEXT historicalcompare(SB),NOSPLIT,$0-0\n" + + "\tCMPPD X1, X0, 1\n" + + "\tCMPPS 8(AX), X0, 2\n" + + "\tCMPSD X1, X0, 5\n" + + "\tCMPSS 8(AX), X0, -1\n" + + "\tRET\n" + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "historicalcompare": {Name: "historicalcompare", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "historical-floating-compare.ll", "historical-floating-compare.o", ll) +} + +func TestTranslateAMD64LegacyFloatingCompareRejectsInvalidBarePredicate(t *testing.T) { + for _, instruction := range []string{ + "CMPPD X1, X0, predicate", + "CMPPS X1, X0, 128", + "CMPSD X1, X0, -129", + "CMPSS X1, X0, 1+1", + } { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted invalid historical predicate %q", instruction) + } + } +} diff --git a/amd64_lower_compare_greater_test.go b/amd64_lower_compare_greater_test.go new file mode 100644 index 00000000..e8d836f4 --- /dev/null +++ b/amd64_lower_compare_greater_test.go @@ -0,0 +1,135 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedSignedGreaterThanCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast, zLast := 15, 22 + if target.goarch == "386" { + legacyLast, zLast = 7, 7 + } + var source strings.Builder + source.WriteString("TEXT packedsignedgreaterthanforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PCMPGTB", "PCMPGTW", "PCMPGTL"} { + fmt.Fprintf(&source, "\t%s M0, M1\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), M2\n", op) + fmt.Fprintf(&source, "\t%s X0, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, legacyLast) + } + fmt.Fprintf(&source, "\tPCMPGTQ X0, X%d\n", legacyLast) + fmt.Fprintf(&source, "\tPCMPGTQ 8(AX), X%d\n", legacyLast) + for _, op := range []string{"VPCMPGTB", "VPCMPGTW", "VPCMPGTD", "VPCMPGTQ"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&source, "\t%s %s0, %s1, %s2\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s 8(AX), %s1, %s2\n", op, width, width) + fmt.Fprintf(&source, "\t%s %s20, %s21, K3\n", op, width, width) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s %s20, %s21, K1, K3\n", op, width, width) + } + } + fmt.Fprintf(&source, "\t%s Z0, Z6, K3\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), Z6, K0\n", op) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s Z20, Z21, K2, K3\n", op) + } else { + fmt.Fprintf(&source, "\t%s Z0, Z6, K%d\n", op, zLast) + } + if strings.HasSuffix(op, "D") || strings.HasSuffix(op, "Q") { + for _, width := range []string{"X", "Y", "Z"} { + reg := "21" + if width == "Z" && target.goarch == "386" { + reg = "6" + } + fmt.Fprintf(&source, "\t%s.BCST 8(AX), %s%s, K3\n", op, width, reg) + } + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedsignedgreaterthanforms": {Name: "packedsignedgreaterthanforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-signed-greater-than-"+target.name+".ll", "packed-signed-greater-than-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedSignedGreaterThanRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PCMPGTB.Z X0, X1", + "PCMPGTW X0", + "PCMPGTL M0, X1", + "PCMPGTQ M0, M1", + "PCMPGTB Y0, Y1", + "PCMPGTW X0, (AX)", + "VPCMPGTB X0, X1", + "VPCMPGTW X0, Y1, Y2", + "VPCMPGTD Z0, Z1, Z2", + "VPCMPGTQ X0, X1, K0, K2", + "VPCMPGTB.Z X0, X1, K2", + "VPCMPGTW.BCST 8(AX), X1, K2", + "VPCMPGTD.BCST X0, X1, K2", + "VPCMPGTQ.BCST 8(AX), X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedSignedGreaterThanRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PCMPGTW X8, X0", + "PCMPGTL X0, X8", + "VPCMPGTB X8, X1, X2", + "VPCMPGTW X0, X1, X8", + "VPCMPGTD Z8, Z1, K2", + "VPCMPGTQ Z0, Z1, K1, K2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedSignedGreaterThanRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedSignedGreaterThanRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed signed greater-than forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_compare_legacy_equal_test.go b/amd64_lower_compare_legacy_equal_test.go new file mode 100644 index 00000000..82d13890 --- /dev/null +++ b/amd64_lower_compare_legacy_equal_test.go @@ -0,0 +1,95 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86LegacyPackedEqualityCompleteGoAssemblerForms(t *testing.T) { + // PCMPEQ{B,W,L} use Go's ymm table (MMX/memory -> MMX and X/memory + // -> X). PCMPEQQ uses yxm_q4, which has only the X/memory -> X row. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastX := 15 + if target.goarch == "386" { + lastX = 7 + } + var source strings.Builder + source.WriteString("TEXT legacypackedequalityforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PCMPEQB", "PCMPEQW", "PCMPEQL"} { + fmt.Fprintf(&source, "\t%s M0, M1\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), M2\n", op) + fmt.Fprintf(&source, "\t%s X0, X%d\n", op, lastX) + fmt.Fprintf(&source, "\t%s 16(AX), X%d\n", op, lastX) + } + fmt.Fprintf(&source, "\tPCMPEQQ X0, X%d\n", lastX) + fmt.Fprintf(&source, "\tPCMPEQQ 24(AX), X%d\n", lastX) + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "legacypackedequalityforms": {Name: "legacypackedequalityforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "legacy-packed-equality-"+target.name+".ll", "legacy-packed-equality-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86LegacyPackedEqualityRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PCMPEQQ M0, M1", + "PCMPEQQ X0, M1", + "PCMPEQW M0, X1", + "PCMPEQL X0, M1", + "PCMPEQB Y0, X1", + "PCMPEQQ X0, Y1", + "PCMPEQQ.Z X0, X1", + "PCMPEQQ X0, X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86LegacyPackedEqualityRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + assertX86LegacyPackedEqualityRejected(t, "386", "i386-unknown-linux-gnu", "PCMPEQQ X8, X0") + assertX86LegacyPackedEqualityRejected(t, "386", "i386-unknown-linux-gnu", "PCMPEQQ X0, X8") +} + +func assertX86LegacyPackedEqualityRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's legacy packed equality forms", instruction) + } +} diff --git a/amd64_lower_compare_mask.go b/amd64_lower_compare_mask.go new file mode 100644 index 00000000..5605d35a --- /dev/null +++ b/amd64_lower_compare_mask.go @@ -0,0 +1,156 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64ImmediatePackedCompareSpec struct { + laneBits int + unsigned bool +} + +var amd64ImmediatePackedCompareSpecs = map[string]amd64ImmediatePackedCompareSpec{ + "VPCMPB": {laneBits: 8}, + "VPCMPW": {laneBits: 16}, + "VPCMPD": {laneBits: 32}, + "VPCMPQ": {laneBits: 64}, + "VPCMPUB": {laneBits: 8, unsigned: true}, + "VPCMPUW": {laneBits: 16, unsigned: true}, + "VPCMPUD": {laneBits: 32, unsigned: true}, + "VPCMPUQ": {laneBits: 64, unsigned: true}, +} + +// lowerImmediatePackedCompare implements the complete Go 1.27 _yvpcmpb +// operand table and all eight signed/unsigned element-width mnemonics. +func (c *amd64Ctx) lowerImmediatePackedCompare(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + broadcast := false + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + if rawOp[dot+1:] != "BCST" { + if _, known := amd64ImmediatePackedCompareSpecs[baseOp]; known { + return true, false, fmt.Errorf("amd64 %s accepts only the .BCST suffix: %q", baseOp, ins.Raw) + } + return false, false, nil + } + broadcast = true + } + spec, ok := amd64ImmediatePackedCompareSpecs[baseOp] + if !ok { + return false, false, nil + } + // cmd/asm's 386 parser cannot represent the four- and five-operand + // spellings used by this shared x86 table. + if c.goarch == "386" { + return true, false, fmt.Errorf("386 %s exceeds the Go assembler frontend's operand limit: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 4 && len(ins.Args) != 5 { + return true, false, fmt.Errorf("amd64 %s expects $imm8, first source, second source, [K mask,] K destination: %q", baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("amd64 %s expects an unsigned-byte immediate: %q", baseOp, ins.Raw) + } + + second := ins.Args[2] + byteWidth, validWidth := amd64PackedCompareWidth(second) + if !validWidth || !c.isGoPackedVectorMoveRegister(second, byteWidth) { + return true, false, fmt.Errorf("amd64 %s second source must be an in-range X, Y, or Z register: %q", baseOp, ins.Raw) + } + first := ins.Args[1] + if first.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(first, byteWidth) { + return true, false, fmt.Errorf("amd64 %s register sources must have matching widths: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 %s first source must be a matching vector register or memory: %q", baseOp, ins.Raw) + } + if broadcast { + if spec.laneBits != 32 && spec.laneBits != 64 { + return true, false, fmt.Errorf("amd64 %s does not enable broadcast in Go 1.27: %q", baseOp, ins.Raw) + } + if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory first source: %q", baseOp, ins.Raw) + } + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s destination must be K0-K7: %q", baseOp, ins.Raw) + } + if _, validDestination := amd64ParseKReg(destination.Reg); !validDestination { + return true, false, fmt.Errorf("amd64 %s destination must be K0-K7: %q", baseOp, ins.Raw) + } + + writeMask := "" + if len(ins.Args) == 5 { + mask := ins.Args[3] + if mask.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s write mask must be K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, validMask := amd64ParseKReg(mask.Reg) + if !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s write mask must be K1-K7: %q", baseOp, ins.Raw) + } + writeMask, err = c.loadK(mask.Reg) + if err != nil { + return true, false, err + } + } + + firstValue, err := c.loadPackedCompareLanes(first, byteWidth, spec.laneBits, broadcast) + if err != nil { + return true, false, err + } + secondValue, err := c.loadPackedCompareLanes(second, byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / spec.laneBits + compared := c.emitImmediatePackedComparePredicate(lanes, spec.laneBits, secondValue, firstValue, uint8(ins.Args[0].Imm), spec.unsigned) + packedType := fmt.Sprintf("i%d", lanes) + packed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i1> %s to %s\n", packed, lanes, compared, packedType) + result := "%" + packed + if lanes < 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to i64\n", wide, packedType, result) + result = "%" + wide + } + if writeMask != "" { + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %s\n", masked, result, writeMask) + result = "%" + masked + } + return true, false, c.storeK(destination.Reg, result) +} + +func (c *amd64Ctx) emitImmediatePackedComparePredicate(lanes, laneBits int, left, right string, immediate uint8, unsigned bool) string { + switch immediate & 7 { + case 3: + return "zeroinitializer" + case 7: + return llvmAllTrueI1VectorValue(lanes) + } + predicates := [8]string{"eq", "slt", "sle", "", "ne", "sge", "sgt", ""} + if unsigned { + predicates = [8]string{"eq", "ult", "ule", "", "ne", "uge", "ugt", ""} + } + compared := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %s <%d x i%d> %s, %s\n", compared, predicates[immediate&7], lanes, laneBits, left, right) + return "%" + compared +} + +func llvmAllTrueI1VectorValue(lanes int) string { + var value strings.Builder + value.WriteByte('<') + for lane := 0; lane < lanes; lane++ { + if lane != 0 { + value.WriteString(", ") + } + value.WriteString("i1 true") + } + value.WriteByte('>') + return value.String() +} diff --git a/amd64_lower_compare_mask_test.go b/amd64_lower_compare_mask_test.go new file mode 100644 index 00000000..b4a07810 --- /dev/null +++ b/amd64_lower_compare_mask_test.go @@ -0,0 +1,102 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86ImmediatePackedCompareCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 gives VPCMP{B,W,D,Q,UB,UW,UD,UQ} the same _yvpcmpb + // table: unsigned-byte immediate, X/Y/Z r/m first source, matching vector + // second source, optional K1-K7 write mask, and K destination. D/Q forms + // additionally enable scalar-memory broadcast. + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT immediatepackedcompareforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{ + "VPCMPB", "VPCMPW", "VPCMPD", "VPCMPQ", + "VPCMPUB", "VPCMPUW", "VPCMPUD", "VPCMPUQ", + } { + fmt.Fprintf(&source, "\t%s $0, X1, X20, K0\n", op) + fmt.Fprintf(&source, "\t%s $1, 8(AX), X20, K1, K2\n", op) + fmt.Fprintf(&source, "\t%s $2, Y1, Y20, K3\n", op) + fmt.Fprintf(&source, "\t%s $3, 40(AX), Y20, K4, K5\n", op) + fmt.Fprintf(&source, "\t%s $7, Z1, Z20, K6\n", op) + fmt.Fprintf(&source, "\t%s $255, 104(AX), Z20, K7, K0\n", op) + if strings.HasSuffix(op, "D") || strings.HasSuffix(op, "Q") { + fmt.Fprintf(&source, "\t%s.BCST $4, 168(AX), X20, K1\n", op) + fmt.Fprintf(&source, "\t%s.BCST $5, 176(AX), Y20, K2, K3\n", op) + fmt.Fprintf(&source, "\t%s.BCST $6, 184(AX), Z20, K4\n", op) + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "immediatepackedcompareforms": {Name: "immediatepackedcompareforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "immediate-packed-compare-"+target.name+".ll", "immediate-packed-compare-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86ImmediatePackedCompareRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPCMPUD X0, X1, K1", + "VPCMPUD $256, X0, X1, K1", + "VPCMPUD $1, X0, Y1, K1", + "VPCMPUD $1, X0, (AX), K1", + "VPCMPUD $1, X0, X1, K0, K1", + "VPCMPUD $1, X0, X1, AX", + "VPCMPUD.Z $1, X0, X1, K1", + "VPCMPUB.BCST $1, (AX), X1, K1", + "VPCMPUW.BCST $1, (AX), X1, K1", + "VPCMPUD.BCST $1, X0, X1, K1", + "VPCMPUQ $1, X32, X1, K1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86ImmediatePackedCompareRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + // cmd/asm's 386 frontend rejects this table's four- and five-operand + // spellings before its shared x86 optab is reached. + assertX86ImmediatePackedCompareRejected(t, "386", "i386-unknown-linux-gnu", "VPCMPUD $1, Y2, Y0, K2") +} + +func assertX86ImmediatePackedCompareRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's immediate packed compare forms", instruction) + } +} diff --git a/amd64_lower_compare_vec.go b/amd64_lower_compare_vec.go new file mode 100644 index 00000000..cc208b56 --- /dev/null +++ b/amd64_lower_compare_vec.go @@ -0,0 +1,365 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedIntegerCompare implements the legacy PCMPGT{B,W,L,Q} family and +// the complete Go 1.27 _yvpcmpeqb operand family shared by VPCMPEQ{B,W,D,Q} +// and VPCMPGT{B,W,D,Q}. +// VEX forms write X/Y vectors. EVEX forms compare X/Y/Z lanes into a K +// register, optionally gated by a non-K0 mask; D/Q memory operands can be +// broadcast for the EVEX forms. +func (c *amd64Ctx) lowerPackedIntegerCompare(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits := 0 + legacy := false + legacyMMX := false + switch baseOp { + case "PCMPEQB": + laneBits, legacy, legacyMMX = 8, true, true + case "PCMPEQW": + laneBits, legacy, legacyMMX = 16, true, true + case "PCMPEQL": + laneBits, legacy, legacyMMX = 32, true, true + case "PCMPEQQ": + laneBits, legacy = 64, true + case "PCMPGTB": + laneBits, legacy, legacyMMX = 8, true, true + case "PCMPGTW": + laneBits, legacy, legacyMMX = 16, true, true + case "PCMPGTL": + laneBits, legacy, legacyMMX = 32, true, true + case "PCMPGTQ": + laneBits, legacy = 64, true + case "VPCMPEQB", "VPCMPGTB": + laneBits = 8 + case "VPCMPEQW", "VPCMPGTW": + laneBits = 16 + case "VPCMPEQD", "VPCMPGTD": + laneBits = 32 + case "VPCMPEQQ", "VPCMPGTQ": + laneBits = 64 + default: + return false, false, nil + } + if legacy { + if suffix != "" { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + return c.lowerLegacyPackedIntegerCompare(baseOp, laneBits, legacyMMX, ins) + } + broadcast := suffix == "BCST" + if suffix != "" && !broadcast { + return true, false, fmt.Errorf("amd64 %s accepts only the .BCST suffix supported by its Go 1.27 optab: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 %s expects src1, src2, [K mask,] destination: %q", baseOp, ins.Raw) + } + if ins.Args[len(ins.Args)-1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects a vector or K destination: %q", baseOp, ins.Raw) + } + + dst := ins.Args[len(ins.Args)-1].Reg + if isAMD64XReg(dst) || isAMD64YReg(dst) { + if len(ins.Args) != 3 || broadcast { + return true, false, fmt.Errorf("amd64 %s vector-result form has no mask or suffix: %q", baseOp, ins.Raw) + } + byteWidth := 16 + if isAMD64YReg(dst) { + byteWidth = 32 + } + if !c.isGoVEXVectorRegister(ins.Args[0], byteWidth, true) || + !c.isGoVEXVectorRegister(ins.Args[1], byteWidth, false) || + !c.isGoVEXVectorRegister(ins.Args[2], byteWidth, false) { + return true, false, fmt.Errorf("%s %s VEX form requires matching in-range X or Y operands: %q", c.goarch, baseOp, ins.Raw) + } + return true, false, c.emitPackedIntegerVectorCompare(baseOp, laneBits, byteWidth, ins.Args[0], ins.Args[1], dst) + } + + if _, ok := amd64ParseKReg(dst); !ok { + return true, false, fmt.Errorf("amd64 %s EVEX form expects a K destination: %q", baseOp, ins.Raw) + } + byteWidth, ok := amd64PackedCompareWidth(ins.Args[1]) + if !ok || !c.isGoPackedVectorMoveRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("amd64 %s EVEX form expects X/Y/Z as its second source: %q", baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s EVEX source registers must match and be in range: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s EVEX first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast { + if laneBits != 32 && laneBits != 64 { + return true, false, fmt.Errorf("amd64 %s does not enable EVEX broadcast: %q", baseOp, ins.Raw) + } + if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory first source: %q", baseOp, ins.Raw) + } + } + + var writeMask string + if len(ins.Args) == 4 { + if c.goarch == "386" { + return true, false, fmt.Errorf("386 %s write-mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + mask := ins.Args[2] + if mask.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + index, ok := amd64ParseKReg(mask.Reg) + if !ok || index == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + writeMask, err = c.loadK(mask.Reg) + if err != nil { + return true, false, err + } + } + return true, false, c.emitPackedIntegerMaskCompare(baseOp, laneBits, byteWidth, ins.Args[0], ins.Args[1], dst, writeMask, broadcast) +} + +func (c *amd64Ctx) lowerLegacyPackedIntegerCompare(baseOp string, laneBits int, allowMMX bool, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects packed source, packed destination: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[1].Reg + if _, mmx := amd64ParseMReg(destination); mmx { + if !allowMMX { + return true, false, fmt.Errorf("%s %s has no MMX form in Go 1.27's yxm_q4 table: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if _, ok := amd64ParseMReg(ins.Args[0].Reg); !ok { + return true, false, fmt.Errorf("%s %s MMX form requires an MMX source: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s MMX form requires MMX or memory source: %q", c.goarch, baseOp, ins.Raw) + } + firstBits, err := c.loadLegacyMMXPackedSource(ins.Args[0]) + if err != nil { + return true, false, err + } + secondBits, err := c.loadReg(destination) + if err != nil { + return true, false, err + } + lanes := 64 / laneBits + first := c.bitcastI64ToIntegerLanes(lanes, laneBits, firstBits) + second := c.bitcastI64ToIntegerLanes(lanes, laneBits, secondBits) + result := c.emitLegacyPackedIntegerCompare(baseOp, lanes, laneBits, first, second) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to i64\n", bits, lanes, laneBits, result) + return true, false, c.storeReg(destination, "%"+bits) + } + + if !c.isGoLegacyXReg(destination) { + return true, false, fmt.Errorf("%s %s destination must be an in-range MMX or X register: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg && !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s XMM form requires an in-range X source: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpReg && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s XMM form requires X or memory source: %q", c.goarch, baseOp, ins.Raw) + } + firstBytes, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(destination) + if err != nil { + return true, false, err + } + lanes := 128 / laneBits + first := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, secondBytes) + result := c.emitLegacyPackedIntegerCompare(baseOp, lanes, laneBits, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, lanes, laneBits, result) + return true, false, c.storeX(destination, "%"+out) +} + +func (c *amd64Ctx) emitLegacyPackedIntegerCompare(baseOp string, lanes, laneBits int, first, second string) string { + compared := c.newTmp() + result := c.newTmp() + predicate := "eq" + if strings.HasPrefix(baseOp, "PCMPGT") { + predicate = "sgt" + } + fmt.Fprintf(c.b, " %%%s = icmp %s <%d x i%d> %s, %s\n", compared, predicate, lanes, laneBits, second, first) + fmt.Fprintf(c.b, " %%%s = sext <%d x i1> %%%s to <%d x i%d>\n", result, lanes, compared, lanes, laneBits) + return "%" + result +} + +func (c *amd64Ctx) isGoVEXVectorRegister(arg Operand, byteWidth int, allowMemory bool) bool { + if allowMemory && isAMD64MemoryOperand(arg) { + return true + } + if !amd64VEXVectorRegister(arg, byteWidth) { + return false + } + if c.goarch == "386" { + index, _ := amd64VectorRegisterIndex(arg.Reg, byteWidth) + return index < 8 + } + return true +} + +func amd64PackedCompareWidth(op Operand) (int, bool) { + if op.Kind != OpReg { + return 0, false + } + switch { + case isAMD64XReg(op.Reg): + return 16, true + case isAMD64YReg(op.Reg): + return 32, true + case isAMD64ZReg(op.Reg): + return 64, true + default: + return 0, false + } +} + +func (c *amd64Ctx) loadPackedCompareBytes(op Operand, byteWidth int) (string, error) { + if op.Kind == OpReg { + width, ok := amd64PackedCompareWidth(op) + if !ok || width != byteWidth { + return "", fmt.Errorf("expected %d-byte vector register, got %s", byteWidth, op.String()) + } + switch byteWidth { + case 16: + return c.loadX(op.Reg) + case 32: + return c.loadY(op.Reg) + case 64: + return c.loadZ(op.Reg) + } + } + if op.Kind == OpFP { + chunks := byteWidth / 8 + value := "zeroinitializer" + for i := 0; i < chunks; i++ { + word, err := c.evalFPToI64(op.FPOffset + int64(i*8)) + if err != nil { + return "", err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i64> %s, i64 %s, i32 %d\n", inserted, chunks, value, word, i) + value = "%" + inserted + } + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", bytesValue, chunks, value, byteWidth) + return "%" + bytesValue, nil + } + if op.Kind == OpSym { + // As in Go's x86 assembler, an unprefixed integer denotes an + // absolute memory address rather than an immediate value. + if address, parseErr := parseInt(strings.TrimSpace(op.Sym)); parseErr == nil { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load <%d x i8>, ptr %s, align 1\n", value, byteWidth, c.ptrFromAddrI64(fmt.Sprintf("%d", address))) + return "%" + value, nil + } + } + if !isAMD64MemoryOperand(op) { + return "", fmt.Errorf("expected vector register or memory, got %s", op.String()) + } + switch byteWidth { + case 16: + return c.loadXVecOperand(op) + case 32: + return c.loadYVecOperand(op) + case 64: + return c.loadZVecOperand(op) + default: + return "", fmt.Errorf("unsupported packed compare width %d", byteWidth) + } +} + +func (c *amd64Ctx) loadPackedCompareLanes(op Operand, byteWidth, laneBits int, broadcast bool) (string, error) { + lanes := byteWidth * 8 / laneBits + if broadcast { + value, err := c.evalIntSized(op, amd64IntegerTypeForBits(laneBits)) + if err != nil { + return "", err + } + return amd64SplatInteger(c, lanes, laneBits, value), nil + } + bytesValue, err := c.loadPackedCompareBytes(op, byteWidth) + if err != nil { + return "", err + } + lanesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i%d>\n", lanesValue, byteWidth, bytesValue, lanes, laneBits) + return "%" + lanesValue, nil +} + +func (c *amd64Ctx) comparePackedIntegerLanes(baseOp string, laneBits, byteWidth int, first, second Operand, broadcast bool) (string, error) { + firstValue, err := c.loadPackedCompareLanes(first, byteWidth, laneBits, broadcast) + if err != nil { + return "", err + } + secondValue, err := c.loadPackedCompareLanes(second, byteWidth, laneBits, false) + if err != nil { + return "", err + } + predicate := "eq" + if strings.HasPrefix(baseOp, "VPCMPGT") { + predicate = "sgt" + } + lanes := byteWidth * 8 / laneBits + compared := c.newTmp() + // Go/Plan 9 lists the Intel r/m operand first: dst = second cmp first. + fmt.Fprintf(c.b, " %%%s = icmp %s <%d x i%d> %s, %s\n", compared, predicate, lanes, laneBits, secondValue, firstValue) + return "%" + compared, nil +} + +func (c *amd64Ctx) emitPackedIntegerVectorCompare(baseOp string, laneBits, byteWidth int, first, second Operand, dst Reg) error { + compared, err := c.comparePackedIntegerLanes(baseOp, laneBits, byteWidth, first, second, false) + if err != nil { + return err + } + lanes := byteWidth * 8 / laneBits + allBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext <%d x i1> %s to <%d x i%d>\n", allBits, lanes, compared, lanes, laneBits) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <%d x i8>\n", bytesValue, lanes, laneBits, allBits, byteWidth) + switch byteWidth { + case 16: + return c.storeX(dst, "%"+bytesValue) + case 32: + return c.storeY(dst, "%"+bytesValue) + default: + return fmt.Errorf("Go 1.27 vector-result packed compare has no %d-byte form", byteWidth) + } +} + +func (c *amd64Ctx) emitPackedIntegerMaskCompare(baseOp string, laneBits, byteWidth int, first, second Operand, dst Reg, writeMask string, broadcast bool) error { + compared, err := c.comparePackedIntegerLanes(baseOp, laneBits, byteWidth, first, second, broadcast) + if err != nil { + return err + } + lanes := byteWidth * 8 / laneBits + packedType := fmt.Sprintf("i%d", lanes) + packed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i1> %s to %s\n", packed, lanes, compared, packedType) + result := "%" + packed + if lanes < 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to i64\n", wide, packedType, result) + result = "%" + wide + } + if writeMask != "" { + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %s\n", masked, result, writeMask) + result = "%" + masked + } + return c.storeK(dst, result) +} diff --git a/amd64_lower_compress.go b/amd64_lower_compress.go new file mode 100644 index 00000000..beaf6c1b --- /dev/null +++ b/amd64_lower_compress.go @@ -0,0 +1,162 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var amd64PackedCompressLaneBits = map[Op]int{ + "VCOMPRESSPS": 32, + "VCOMPRESSPD": 64, + "VPCOMPRESSB": 8, + "VPCOMPRESSW": 16, + "VPCOMPRESSD": 32, + "VPCOMPRESSQ": 64, +} + +// lowerPackedCompress implements the complete Go 1.27 _yvcompresspd table. +// Masked register forms compact selected source lanes and merge/zero only the +// tail. Masked memory forms write selected lanes contiguously and leave every +// byte after the compacted tail untouched, including for Go's accepted .Z +// spelling. +func (c *amd64Ctx) lowerPackedCompress(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits, ok := amd64PackedCompressLaneBits[Op(baseOp)] + if !ok { + return false, false, nil + } + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("%s %s accepts only Go 1.27's optional .Z suffix: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects source, [K1-K7,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s.Z requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[0] + if source.Kind != OpReg { + return true, false, fmt.Errorf("%s %s source must be an X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(source.Reg) + if byteWidth == 0 || !c.isGoEVEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source is outside Go's EVEX register range: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind == OpReg { + if !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s register destination must match the source width and range: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s %s destination must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + sourceBytes, err := c.loadPackedCompareBytes(source, byteWidth) + if err != nil { + return true, false, err + } + if !masked { + return true, false, c.storeVectorBytesOperand(destination, byteWidth, sourceBytes) + } + maskArg := ins.Args[1] + maskIndex, valid := amd64ParseKReg(maskArg.Reg) + if maskArg.Kind != OpReg || !valid || maskIndex == 0 { + return true, false, fmt.Errorf("%s %s masked form requires K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + mask, err := c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / laneBits + vectorType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + sourceValue := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, sourceBytes) + maskVector := amd64IntegerMaskVector(c, lanes, mask) + if destination.Kind != OpReg { + pointer, pointerType, intrinsicSuffix, err := c.packedVectorMemoryPointer(destination) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void @llvm.masked.compressstore.v%di%d%s(%s %s, %s %s, <%d x i1> %s)\n", + lanes, laneBits, intrinsicSuffix, vectorType, sourceValue, pointerType, pointer, lanes, maskVector) + if destination.Kind == OpFP { + c.markFPResultWritten(destination.FPOffset) + } + return true, false, nil + } + passthrough := "zeroinitializer" + if !zeroing { + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + passthrough = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + } + compressed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.experimental.vector.compress.v%di%d(%s %s, <%d x i1> %s, %s %s)\n", + compressed, vectorType, lanes, laneBits, vectorType, sourceValue, lanes, maskVector, vectorType, passthrough) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <%d x i8>\n", out, vectorType, compressed, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func amd64IntegerMaskVector(c *amd64Ctx, lanes int, mask string) string { + packed := mask + if lanes < 64 { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrow, mask, lanes) + packed = "%" + narrow + } + vector := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i%d %s to <%d x i1>\n", vector, lanes, packed, lanes) + return "%" + vector +} + +func (c *amd64Ctx) packedVectorMemoryPointer(operand Operand) (ptr, ptrType, intrinsicSuffix string, err error) { + switch operand.Kind { + case OpMem: + ptr, ptrType, err = c.ptrFromMem(operand.Mem) + if err != nil { + return "", "", "", err + } + switch ptrType { + case "ptr": + return ptr, ptrType, "", nil + case "ptr addrspace(256)": + return ptr, ptrType, ".p256", nil + case "ptr addrspace(257)": + return ptr, ptrType, ".p257", nil + default: + return "", "", "", fmt.Errorf("unsupported packed-vector pointer type %s", ptrType) + } + case OpSym: + if address, parseErr := parseInt(strings.TrimSpace(operand.Sym)); parseErr == nil { + return c.ptrFromAddrI64(fmt.Sprintf("%d", address)), "ptr", "", nil + } + ptr, err = c.ptrFromSB(operand.Sym) + return ptr, "ptr", "", err + case OpFP: + if c.classicFrame != "" { + return c.classicFramePtr(operand.FPOffset), "ptr", "", nil + } + if ptr = c.fpParamAlloca[operand.FPOffset]; ptr != "" { + return ptr, "ptr", "", nil + } + if ptr, _, ok := c.fpResultAlloca(operand.FPOffset); ok { + return ptr, "ptr", "", nil + } + return "", "", "", fmt.Errorf("%s %s FP operand has no addressable slot", c.goarch, operand.String()) + default: + return "", "", "", fmt.Errorf("%s expected a packed-vector memory operand, got %s", c.goarch, operand.String()) + } +} diff --git a/amd64_lower_compress_test.go b/amd64_lower_compress_test.go new file mode 100644 index 00000000..9adf7a4d --- /dev/null +++ b/amd64_lower_compress_test.go @@ -0,0 +1,229 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86PackedCompressCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT packedcompressforms(SB),$0-0\n") + for _, op := range []string{"VCOMPRESSPS", "VCOMPRESSPD", "VPCOMPRESSB", "VPCOMPRESSW", "VPCOMPRESSD", "VPCOMPRESSQ"} { + for _, width := range []string{"X", "Y", "Z"} { + sourceReg, destinationReg := 20, 22 + if target.goarch == "386" && width == "Z" { + sourceReg, destinationReg = 6, 7 + } + fmt.Fprintf(&source, "\t%s %s%d, %s%d\n", op, width, sourceReg, width, destinationReg) + fmt.Fprintf(&source, "\t%s %s%d, 8(AX)\n", op, width, sourceReg) + fmt.Fprintf(&source, "\t%s %s%d, K1, %s%d\n", op, width, sourceReg, width, destinationReg) + fmt.Fprintf(&source, "\t%s.Z %s%d, K7, %s%d\n", op, width, sourceReg, width, destinationReg) + fmt.Fprintf(&source, "\t%s %s%d, K2, 8(AX)\n", op, width, sourceReg) + fmt.Fprintf(&source, "\t%s.Z %s%d, K3, 8(AX)\n", op, width, sourceReg) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedcompressforms": {Name: "packedcompressforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-compress-"+target.name+".ll", "packed-compress-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedCompressRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VCOMPRESSPS 8(AX), X1", + "VCOMPRESSPD X0, Y1", + "VCOMPRESSPS X0, K0, X1", + "VCOMPRESSPD.Z Z0, Z1", + "VPCOMPRESSB 8(AX), X1", + "VPCOMPRESSW X0, Y1", + "VPCOMPRESSD X0, K0, X1", + "VPCOMPRESSQ.Z Z0, Z1", + "VPCOMPRESSB.BCST X0, X1", + "VPCOMPRESSW X0, AX", + "VPCOMPRESSD AX, X1", + "VPCOMPRESSQ Z0, K1, K2, Z1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + if currentGoMinorAtLeast(27) { + requireX86GoAssemblerResult(t, "amd64", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + } + assertX86PackedCompressRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "VPCOMPRESSB Z8, Z0", + "VPCOMPRESSW Z0, Z8", + "VPCOMPRESSD Z8, K1, 8(AX)", + "VPCOMPRESSQ Z0, K1, Z8", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + if currentGoMinorAtLeast(27) { + requireX86GoAssemblerResult(t, "386", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + } + assertX86PackedCompressRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedCompressRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yvcompresspd forms for %s", instruction, goarch) + } +} + +func TestAMD64PackedCompressRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT packedcompress(SB),$0-32 + MOVQ out+0(FP), AX + MOVQ source+8(FP), BX + MOVQ old+16(FP), CX + MOVQ mask+24(FP), DX + KMOVQ DX, K1 + VMOVDQU64 (BX), Z0 + VMOVDQU64 (CX), Z1 + VPCOMPRESSB Z0, K1, Z1 + VMOVDQU64 Z1, 0(AX) + VMOVDQU64 (CX), Z1 + VPCOMPRESSW.Z Z0, K1, Z1 + VMOVDQU64 Z1, 64(AX) + VMOVDQU64 (CX), Z1 + VPCOMPRESSD Z0, K1, Z1 + VMOVDQU64 Z1, 128(AX) + VMOVDQU64 (CX), Z1 + VPCOMPRESSQ.Z Z0, K1, Z1 + VMOVDQU64 Z1, 192(AX) + VPCOMPRESSB Z0, K1, 256(AX) + VPCOMPRESSW.Z Z0, K1, 320(AX) + VPCOMPRESSD Z0, K1, 384(AX) + VPCOMPRESSQ.Z Z0, K1, 448(AX) + VMOVDQU64 (CX), Z1 + VCOMPRESSPS Z0, K1, Z1 + VMOVDQU64 Z1, 512(AX) + VMOVDQU64 (CX), Z1 + VCOMPRESSPD.Z Z0, K1, Z1 + VMOVDQU64 Z1, 576(AX) + VCOMPRESSPS Z0, K1, 640(AX) + VCOMPRESSPD.Z Z0, K1, 704(AX) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: I64, Index: 3, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "packedcompress": {Name: "packedcompress", Args: []LLVMType{Ptr, Ptr, Ptr, I64}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +#include +extern void packedcompress(uint8_t *, const uint8_t *, const uint8_t *, uint64_t); +static int check_group(const uint8_t *got, const uint8_t *source, const uint8_t *old, int lane_bytes, uint64_t mask, int zero_tail, int memory) { + int lanes = 64 / lane_bytes, packed = 0; + for (int lane = 0; lane < lanes; lane++) if ((mask >> lane) & 1) { + if (memcmp(got + packed*lane_bytes, source + lane*lane_bytes, lane_bytes)) return 10 + lane; + packed++; + } + for (int lane = packed; lane < lanes; lane++) { + const uint8_t *want = old + lane*lane_bytes; + uint8_t zeros[8] = {0}, untouched[8]; memset(untouched, 0xcc, sizeof(untouched)); + if (memory) want = untouched; else if (zero_tail) want = zeros; + if (memcmp(got + lane*lane_bytes, want, lane_bytes)) return 80 + lane; + } + return 0; +} +int main(void) { + uint8_t source[64], old[64], out[768]; + const uint64_t mask = 0xa55aa55aa55aa55aULL; + for (int i = 0; i < 64; i++) { source[i] = (uint8_t)(i * 29 + 7); old[i] = (uint8_t)(0xf0 - i); } + memset(out, 0xcc, sizeof(out)); + packedcompress(out, source, old, mask); + int r; + if ((r = check_group(out+0, source, old, 1, mask, 0, 0))) return 100+r; + if ((r = check_group(out+64, source, old, 2, mask, 1, 0))) return 200+r; + if ((r = check_group(out+128, source, old, 4, mask, 0, 0))) return 300+r; + if ((r = check_group(out+192, source, old, 8, mask, 1, 0))) return 400+r; + if ((r = check_group(out+256, source, old, 1, mask, 0, 1))) return 500+r; + if ((r = check_group(out+320, source, old, 2, mask, 0, 1))) return 600+r; + if ((r = check_group(out+384, source, old, 4, mask, 0, 1))) return 700+r; + if ((r = check_group(out+448, source, old, 8, mask, 0, 1))) return 800+r; + if ((r = check_group(out+512, source, old, 4, mask, 0, 0))) return 900+r; + if ((r = check_group(out+576, source, old, 8, mask, 1, 0))) return 1000+r; + if ((r = check_group(out+640, source, old, 4, mask, 0, 1))) return 1100+r; + if ((r = check_group(out+704, source, old, 8, mask, 0, 1))) return 1200+r; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_compress", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_conflict.go b/amd64_lower_conflict.go new file mode 100644 index 00000000..8d78220a --- /dev/null +++ b/amd64_lower_conflict.go @@ -0,0 +1,125 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedConflictSpec struct { + laneBits int +} + +// amd64PackedConflictSpecs is the complete Go 1.27 VPCONFLICTD/Q grammar. +// Both instructions use _yvexpandpd: EVEX X/Y/Z register-or-memory sources, +// optional K1-K7 merge/.Z masking, and scalar-memory broadcast. +var amd64PackedConflictSpecs = map[Op]amd64PackedConflictSpec{ + "VPCONFLICTD": {laneBits: 32}, + "VPCONFLICTQ": {laneBits: 64}, +} + +func (c *amd64Ctx) lowerPackedConflict(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64PackedConflictSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s has a suffix outside Go 1.27's _yvexpandpd form: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects source, [K1-K7,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s.Z requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s requires an X, Y, or Z destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth == 0 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go's EVEX register range: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[0] + if broadcast { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) && !c.isGoEVEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source must be a matching X/Y/Z register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + mask := "" + if masked { + maskArg := ins.Args[1] + maskIndex, valid := amd64ParseKReg(maskArg.Reg) + if maskArg.Kind != OpReg || !valid || maskIndex == 0 { + return true, false, fmt.Errorf("%s %s masked form requires K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + lanes := byteWidth * 8 / spec.laneBits + values, err := c.loadPackedCompareLanes(source, byteWidth, spec.laneBits, broadcast) + if err != nil { + return true, false, err + } + computed := c.emitPackedConflict(values, lanes, spec.laneBits) + result := computed + if masked { + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, computed, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPackedConflict(values string, lanes, laneBits int) string { + elements := make([]string, lanes) + for lane := 0; lane < lanes; lane++ { + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", extracted, lanes, laneBits, values, lane) + elements[lane] = "%" + extracted + } + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + conflicts := "0" + for prior := 0; prior < lane; prior++ { + equal := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %s, %s\n", equal, laneBits, elements[lane], elements[prior]) + bit := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d 0\n", bit, equal, laneBits, uint64(1)< %s, i%d %s, i32 %d\n", inserted, lanes, laneBits, result, laneBits, conflicts, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_conflict_test.go b/amd64_lower_conflict_test.go new file mode 100644 index 00000000..27d4976d --- /dev/null +++ b/amd64_lower_conflict_test.go @@ -0,0 +1,221 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64PackedConflictGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64PackedConflictSpec{ + "VPCONFLICTD": {laneBits: 32}, + "VPCONFLICTQ": {laneBits: 64}, + } + if len(amd64PackedConflictSpecs) != len(expected) { + t.Fatalf("packed-conflict grammar has %d entries, want %d", len(amd64PackedConflictSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64PackedConflictSpecs[op]; !ok { + t.Errorf("packed-conflict grammar omitted %s", op) + } else if got != want { + t.Errorf("packed-conflict grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86PackedConflictCompleteGoFormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT packedconflictforms(SB),$0-0\n") + for _, op := range []string{"VPCONFLICTD", "VPCONFLICTQ"} { + for _, width := range []string{"X", "Y", "Z"} { + last := 31 + if target.goarch == "386" && width == "Z" { + last = 7 + } + fmt.Fprintf(&source, "\t%s %s0, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s 8(R9), %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s %s1, K1, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s.Z 16(R9), K7, %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST 24(R9), %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST.Z 32(R9), K2, %s%d\n", op, width, last) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "packedconflictforms": {Name: "packedconflictforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"icmp eq", "select i1", "<16 x i32>", "<8 x i64>"} { + if !strings.Contains(ir, want) { + t.Fatalf("packed-conflict lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "packed-conflict-"+target.name+".ll", "packed-conflict-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86PackedConflictRejectsFormsOutsideGoTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VPCONFLICTD X0, Y1"}, + {goarch: "amd64", instruction: "VPCONFLICTQ Y0, Z1"}, + {goarch: "amd64", instruction: "VPCONFLICTD X0, K0, X1"}, + {goarch: "amd64", instruction: "VPCONFLICTQ.Z X0, X1"}, + {goarch: "amd64", instruction: "VPCONFLICTD.BCST X0, X1"}, + {goarch: "amd64", instruction: "VPCONFLICTQ.Z.BCST 0(AX), K1, X1"}, + {goarch: "amd64", instruction: "VPCONFLICTD.RN_SAE X0, X1"}, + {goarch: "amd64", instruction: "VPCONFLICTQ X0, 0(AX)"}, + {goarch: "amd64", instruction: "VPCONFLICTD X0, K1, K2, X1"}, + {goarch: "386", instruction: "VPCONFLICTD Z8, Z0"}, + {goarch: "386", instruction: "VPCONFLICTQ Z0, K1, Z8"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yvexpandpd conflict table", test.instruction) + } + }) + } +} + +func TestAMD64PackedConflictRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT packedconflictsemantics(SB),$0-32 + MOVQ out+0(FP), AX + MOVQ source+8(FP), BX + MOVQ old+16(FP), CX + MOVQ mask+24(FP), DX + KMOVQ DX, K1 + VMOVDQU64 0(BX), Z0 + VMOVDQU64 0(CX), Z1 + STC + VPCONFLICTD Z0, Z2 + VMOVDQU64 Z2, 0(AX) + VPCONFLICTQ Z0, Z2 + VMOVDQU64 Z2, 64(AX) + VPCONFLICTD Z0, K1, Z1 + VMOVDQU64 Z1, 128(AX) + VMOVDQU64 0(CX), Z1 + VPCONFLICTQ.Z Z0, K1, Z1 + VMOVDQU64 Z1, 192(AX) + VPCONFLICTD.BCST 0(BX), Z2 + VMOVDQU64 Z2, 256(AX) + VPCONFLICTQ.BCST 0(BX), Z2 + VMOVDQU64 Z2, 320(AX) + SETCS 384(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{"packedconflictsemantics": { + Name: "packedconflictsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: I64, Index: 3, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void packedconflictsemantics(uint8_t *, const uint8_t *, const uint8_t *, uint64_t); +int main(void) { + uint32_t source32[16], old32[16]; uint8_t out[385] = {0}; + for (int i = 0; i < 16; i++) { source32[i] = (uint32_t)(i % 4); old32[i] = 0x90000000u + (uint32_t)i; } + const uint64_t mask = UINT64_C(0xa55a); + packedconflictsemantics(out, (const uint8_t *)source32, (const uint8_t *)old32, mask); + uint32_t *plain32 = (uint32_t *)(out + 0), *merge32 = (uint32_t *)(out + 128), *broadcast32 = (uint32_t *)(out + 256); + for (int i = 0; i < 16; i++) { + uint32_t conflict = 0; + for (int j = 0; j < i; j++) if (source32[j] == source32[i]) conflict |= UINT32_C(1) << j; + if (plain32[i] != conflict) return 10 + i; + uint32_t merged = (mask >> i) & 1 ? conflict : old32[i]; + if (merge32[i] != merged) return 30 + i; + uint32_t broadcast = i == 0 ? 0 : ((UINT32_C(1) << i) - 1); + if (broadcast32[i] != broadcast) return 50 + i; + } + uint64_t source64[8], old64[8], plain64[8], zero64[8], broadcast64[8]; + memcpy(source64, source32, 64); memcpy(old64, old32, 64); + memcpy(plain64, out + 64, 64); memcpy(zero64, out + 192, 64); memcpy(broadcast64, out + 320, 64); + for (int i = 0; i < 8; i++) { + uint64_t conflict = 0; + for (int j = 0; j < i; j++) if (source64[j] == source64[i]) conflict |= UINT64_C(1) << j; + if (plain64[i] != conflict) return 70 + i; + uint64_t masked = (mask >> i) & 1 ? conflict : 0; + if (zero64[i] != masked) return 80 + i; + uint64_t broadcast = i == 0 ? 0 : ((UINT64_C(1) << i) - 1); + if (broadcast64[i] != broadcast) return 90 + i; + } + if (out[384] != 1) return 100; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_conflict_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_convert.go b/amd64_lower_convert.go new file mode 100644 index 00000000..978d121e --- /dev/null +++ b/amd64_lower_convert.go @@ -0,0 +1,280 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +func amd64ParseMReg(r Reg) (idx int, ok bool) { + s := strings.ToUpper(strings.TrimSpace(string(r))) + if !strings.HasPrefix(s, "M") { + return 0, false + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "M")) + if err != nil || n < 0 || n > 7 { + return 0, false + } + return n, true +} + +// lowerPackedFloatToDword implements both entries in Go's yxcvm1 table for +// CVTPS2PL and CVTTPS2PL: X/m -> X and X/m64 -> M. +func (c *amd64Ctx) lowerPackedFloatToDword(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + switch baseOp { + case "CVTPS2PL", "CVTTPS2PL": + // handled below + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects X/m source and X or M destination: %q", baseOp, ins.Raw) + } + + dst := ins.Args[1].Reg + var source string + if isAMD64XReg(dst) { + bytesValue, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x float>\n", cast, bytesValue) + source = "%" + cast + } else if _, ok := amd64ParseMReg(dst); ok { + if ins.Args[0].Kind == OpReg { + bytesValue, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + all := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x float>\n", all, bytesValue) + source = "%" + all + } else { + bits, err := c.evalIntSized(ins.Args[0], I64) + if err != nil { + return true, false, err + } + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to <2 x float>\n", low, bits) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <2 x float> %%%s, <2 x float> zeroinitializer, <4 x i32> \n", wide, low) + source = "%" + wide + } + } else { + return true, false, fmt.Errorf("amd64 %s expects X or M destination: %q", baseOp, ins.Raw) + } + + intrinsic := "llvm.x86.sse2.cvtps2dq" + if baseOp == "CVTTPS2PL" { + intrinsic = "llvm.x86.sse2.cvttps2dq" + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <4 x i32> @%s(<4 x float> %s)\n", converted, intrinsic, source) + result := "%" + converted + + if isAMD64XReg(dst) { + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %s to <16 x i8>\n", bytesValue, result) + return true, false, c.storeX(dst, "%"+bytesValue) + } + packed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %s to <2 x i64>\n", packed, result) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 0\n", low, packed) + return true, false, c.storeReg(dst, "%"+low) +} + +// lowerPackedSingleToDouble implements every operand shape in Go 1.27's +// CVTPS2PD yxm and VCVTPS2PD _yvcvtph2ps tables. The widening itself is exact; +// SAE therefore only changes the accepted encoding, not the generated value. +func (c *amd64Ctx) lowerPackedSingleToDouble(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + switch baseOp { + case "CVTPS2PD", "VCVTPS2PD": + // handled below + default: + return false, false, nil + } + + broadcast := false + suppressAllExceptions := false + zeroMasking := false + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + suffixes := strings.Split(rawOp[dot+1:], ".") + for i, suffix := range suffixes { + switch suffix { + case "BCST": + if broadcast || suppressAllExceptions || zeroMasking || i != 0 { + return true, false, fmt.Errorf("amd64 %s has invalid or duplicate .BCST suffix: %q", baseOp, ins.Raw) + } + broadcast = true + case "SAE": + if suppressAllExceptions || broadcast || zeroMasking || i != 0 { + return true, false, fmt.Errorf("amd64 %s has invalid or duplicate .SAE suffix: %q", baseOp, ins.Raw) + } + suppressAllExceptions = true + case "Z": + if zeroMasking || i != len(suffixes)-1 { + return true, false, fmt.Errorf("amd64 %s has invalid or duplicate .Z suffix: %q", baseOp, ins.Raw) + } + zeroMasking = true + default: + return true, false, fmt.Errorf("amd64 %s has unsupported suffix .%s: %q", baseOp, suffix, ins.Raw) + } + } + } + + vectorForm := baseOp == "VCVTPS2PD" + if !vectorForm { + if rawOp != baseOp || len(ins.Args) != 2 { + return true, false, fmt.Errorf("amd64 CVTPS2PD expects X/m64 source and X destination: %q", ins.Raw) + } + } else if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 VCVTPS2PD expects source, [K mask,] vector destination: %q", ins.Raw) + } + masked := vectorForm && len(ins.Args) == 3 + if zeroMasking && !masked { + return true, false, fmt.Errorf("amd64 VCVTPS2PD .Z form requires a K mask: %q", ins.Raw) + } + if broadcast && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 VCVTPS2PD .BCST requires a memory source: %q", ins.Raw) + } + + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects a vector destination: %q", baseOp, ins.Raw) + } + dst := dstArg.Reg + lanes := 0 + byteWidth := 0 + var loadDst func() (string, error) + var storeDst func(string) error + switch { + case isAMD64XReg(dst): + lanes, byteWidth = 2, 16 + loadDst = func() (string, error) { return c.loadX(dst) } + storeDst = func(value string) error { return c.storeX(dst, value) } + case vectorForm && isAMD64YReg(dst): + lanes, byteWidth = 4, 32 + loadDst = func() (string, error) { return c.loadY(dst) } + storeDst = func(value string) error { return c.storeY(dst, value) } + case vectorForm && isAMD64ZReg(dst): + lanes, byteWidth = 8, 64 + loadDst = func() (string, error) { return c.loadZ(dst) } + storeDst = func(value string) error { return c.storeZ(dst, value) } + default: + return true, false, fmt.Errorf("amd64 %s has mismatched or non-vector destination: %q", baseOp, ins.Raw) + } + + srcArg := ins.Args[0] + if suppressAllExceptions && (lanes != 8 || srcArg.Kind != OpReg) { + return true, false, fmt.Errorf("amd64 VCVTPS2PD .SAE requires a Y register source and Z destination: %q", ins.Raw) + } + if srcArg.Kind == OpReg { + valid := (lanes <= 4 && isAMD64XReg(srcArg.Reg)) || (lanes == 8 && isAMD64YReg(srcArg.Reg)) + if !valid { + return true, false, fmt.Errorf("amd64 %s source width does not match destination: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(srcArg) { + return true, false, fmt.Errorf("amd64 %s expects a vector register or memory source: %q", baseOp, ins.Raw) + } + + var source string + if broadcast { + scalar, err := c.evalF32(srcArg) + if err != nil { + return true, false, err + } + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x float> poison, float %s, i32 0\n", seed, lanes, scalar) + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x float> %%%s, <%d x float> poison, <%d x i32> zeroinitializer\n", splat, lanes, seed, lanes, lanes) + source = "%" + splat + } else { + switch lanes { + case 2: + if srcArg.Kind == OpReg { + bytesValue, err := c.loadX(srcArg.Reg) + if err != nil { + return true, false, err + } + all := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x float>\n", all, bytesValue) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <4 x float> %%%s, <4 x float> poison, <2 x i32> \n", low, all) + source = "%" + low + } else { + bits, err := c.evalIntSized(srcArg, I64) + if err != nil { + return true, false, err + } + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to <2 x float>\n", cast, bits) + source = "%" + cast + } + case 4: + bytesValue, err := c.loadXVecOperand(srcArg) + if err != nil { + return true, false, err + } + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x float>\n", cast, bytesValue) + source = "%" + cast + case 8: + bytesValue, err := c.loadYVecOperand(srcArg) + if err != nil { + return true, false, err + } + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <32 x i8> %s to <8 x float>\n", cast, bytesValue) + source = "%" + cast + } + } + + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fpext <%d x float> %s to <%d x double>\n", converted, lanes, source, lanes) + result := "%" + converted + if masked { + maskArg := ins.Args[1] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 VCVTPS2PD masked form expects K1-K7: %q", ins.Raw) + } + maskIndex, ok := amd64ParseKReg(maskArg.Reg) + if !ok || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 VCVTPS2PD masked form expects K1-K7: %q", ins.Raw) + } + mask, err := c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + computedBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x double> %s to <%d x i64>\n", computedBits, lanes, result, lanes) + oldBytes, err := loadDst() + if err != nil { + return true, false, err + } + oldBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i64>\n", oldBits, byteWidth, oldBytes, lanes) + maskedBits := amd64ApplyIntegerLaneMask(c, lanes, 64, "%"+computedBits, "%"+oldBits, mask, zeroMasking) + maskedValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x double>\n", maskedValue, lanes, maskedBits, lanes) + result = "%" + maskedValue + } + + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x double> %s to <%d x i8>\n", out, lanes, result, byteWidth) + return true, false, storeDst("%" + out) +} diff --git a/amd64_lower_convert_double_dword.go b/amd64_lower_convert_double_dword.go new file mode 100644 index 00000000..49094b63 --- /dev/null +++ b/amd64_lower_convert_double_dword.go @@ -0,0 +1,361 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedDoubleDwordMode uint8 + +const ( + amd64PackedDwordToDouble amd64PackedDoubleDwordMode = iota + amd64PackedDoubleToDword +) + +type amd64PackedDoubleDwordSpec struct { + mode amd64PackedDoubleDwordMode + legacy bool + truncate bool + sourceBytes int + destBytes int + resultLanes int + explicitMode string +} + +// This table is both the translation dispatch and the source of truth used by +// cmd/plan9asmll's supported-opcode extractor. +var amd64PackedDoubleDwordOps = map[string]amd64PackedDoubleDwordSpec{ + "CVTPD2PL": {mode: amd64PackedDoubleToDword, legacy: true, sourceBytes: 16, destBytes: 16, resultLanes: 2}, + "CVTTPD2PL": {mode: amd64PackedDoubleToDword, legacy: true, truncate: true, sourceBytes: 16, destBytes: 16, resultLanes: 2}, + "VCVTDQ2PD": {mode: amd64PackedDwordToDouble}, + "VCVTPD2DQ": {mode: amd64PackedDoubleToDword, sourceBytes: 64, destBytes: 32, resultLanes: 8, explicitMode: "rounding"}, + "VCVTPD2DQX": {mode: amd64PackedDoubleToDword, sourceBytes: 16, destBytes: 16, resultLanes: 2}, + "VCVTPD2DQY": {mode: amd64PackedDoubleToDword, sourceBytes: 32, destBytes: 16, resultLanes: 4}, + "VCVTTPD2DQ": {mode: amd64PackedDoubleToDword, truncate: true, sourceBytes: 64, destBytes: 32, resultLanes: 8, explicitMode: "sae"}, + "VCVTTPD2DQX": {mode: amd64PackedDoubleToDword, truncate: true, sourceBytes: 16, destBytes: 16, resultLanes: 2}, + "VCVTTPD2DQY": {mode: amd64PackedDoubleToDword, truncate: true, sourceBytes: 32, destBytes: 16, resultLanes: 4}, +} + +type amd64PackedDoubleDwordSuffix struct { + broadcast bool + rounding string + sae bool + zeroing bool +} + +func parseAMD64PackedDoubleDwordSuffix(rawOp, baseOp string) (amd64PackedDoubleDwordSuffix, error) { + var result amd64PackedDoubleDwordSuffix + if rawOp == baseOp { + return result, nil + } + suffixes := strings.Split(strings.TrimPrefix(rawOp, baseOp+"."), ".") + for index, suffix := range suffixes { + switch suffix { + case "BCST": + if result.broadcast || result.rounding != "" || result.sae || result.zeroing || index != 0 { + return result, fmt.Errorf("amd64 %s has invalid or duplicate .BCST suffix", baseOp) + } + result.broadcast = true + case "RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE": + if result.broadcast || result.rounding != "" || result.sae || result.zeroing || index != 0 { + return result, fmt.Errorf("amd64 %s has invalid or duplicate .%s suffix", baseOp, suffix) + } + result.rounding = suffix + case "SAE": + if result.broadcast || result.rounding != "" || result.sae || result.zeroing || index != 0 { + return result, fmt.Errorf("amd64 %s has invalid or duplicate .SAE suffix", baseOp) + } + result.sae = true + case "Z": + if result.zeroing || index != len(suffixes)-1 { + return result, fmt.Errorf("amd64 %s has invalid or misplaced .Z suffix", baseOp) + } + result.zeroing = true + default: + return result, fmt.Errorf("amd64 %s has unsupported suffix .%s", baseOp, suffix) + } + } + return result, nil +} + +// lowerPackedDoubleDword implements the complete Go 1.27 signed packed +// double/dword conversion family. The legacy yxcvm1 rows include X and MMX +// destinations; the VEX/EVEX rows cover masks, zeroing, scalar broadcast, +// embedded rounding, and SAE. +func (c *amd64Ctx) lowerPackedDoubleDword(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, supported := amd64PackedDoubleDwordOps[baseOp] + if !supported { + return false, false, nil + } + suffixes, err := parseAMD64PackedDoubleDwordSuffix(rawOp, baseOp) + if err != nil { + return true, false, fmt.Errorf("%w: %q", err, ins.Raw) + } + if spec.legacy { + return c.lowerLegacyPackedDoubleToDword(baseOp, spec, ins, suffixes) + } + if spec.mode == amd64PackedDwordToDouble { + return c.lowerVectorPackedDwordToDouble(baseOp, ins, suffixes) + } + return c.lowerVectorPackedDoubleToDword(baseOp, spec, ins, suffixes) +} + +func (c *amd64Ctx) lowerLegacyPackedDoubleToDword(baseOp string, spec amd64PackedDoubleDwordSpec, ins Instr, suffixes amd64PackedDoubleDwordSuffix) (bool, bool, error) { + if suffixes != (amd64PackedDoubleDwordSuffix{}) || len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects X/m128 source and X or M destination: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[1] + _, mmx := amd64ParseMReg(destination.Reg) + if !mmx && !c.isGoLegacyPackedAbsSignRegister(destination) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's X/M register classes: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[0] + if source.Kind == OpReg { + if !c.isGoLegacyPackedAbsSignRegister(source) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's X register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be X or memory: %q", c.goarch, baseOp, ins.Raw) + } + doubles, err := c.loadPackedDoubleValues(source, spec.sourceBytes, spec.resultLanes, false) + if err != nil { + return true, false, err + } + result := c.emitPackedDoubleToDword(doubles, spec.resultLanes, spec.truncate, "") + if mmx { + packed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i32> %s to i64\n", packed, result) + return true, false, c.storeReg(destination.Reg, "%"+packed) + } + return true, false, c.storePackedDwordConversionResult(destination.Reg, spec.destBytes, spec.resultLanes, result) +} + +func (c *amd64Ctx) lowerVectorPackedDwordToDouble(baseOp string, ins Instr, suffixes amd64PackedDoubleDwordSuffix) (bool, bool, error) { + if suffixes.rounding != "" || suffixes.sae { + return true, false, fmt.Errorf("amd64 %s does not enable rounding or SAE suffixes: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 %s expects source, [K mask,] destination: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if suffixes.zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z requires K1-K7: %q", baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s destination must be X, Y, or Z: %q", baseOp, ins.Raw) + } + destBytes := amd64VectorByteWidth(destination.Reg) + if (destBytes != 16 && destBytes != 32 && destBytes != 64) || !c.isGoEVEXVectorRegister(destination, destBytes) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's vector class: %q", c.goarch, baseOp, ins.Raw) + } + resultLanes := destBytes / 8 + sourceRegisterBytes := 16 + if destBytes == 64 { + sourceRegisterBytes = 32 + } + source := ins.Args[0] + if suffixes.broadcast { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a scalar memory source: %q", baseOp, ins.Raw) + } + } else if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, sourceRegisterBytes) { + return true, false, fmt.Errorf("amd64 %s source width does not match its destination: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s source must be a matching vector register or memory: %q", baseOp, ins.Raw) + } + + var integers string + if suffixes.broadcast { + scalar, err := c.evalIntSized(source, I32) + if err != nil { + return true, false, err + } + integers = amd64SplatInteger(c, resultLanes, 32, scalar) + } else { + loaded, err := c.loadPackedExtendInputs(source, sourceRegisterBytes, resultLanes, 32) + if err != nil { + return true, false, err + } + integers = loaded + } + converted := c.newTmp() + floats := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sitofp <%d x i32> %s to <%d x double>\n", converted, resultLanes, integers, resultLanes) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x double> %%%s to <%d x i64>\n", floats, resultLanes, converted, resultLanes) + result := "%" + floats + if masked { + mask, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, destBytes) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(destBytes, resultLanes, 64, oldBytes) + result = amd64ApplyIntegerLaneMask(c, resultLanes, 64, result, old, mask, suffixes.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", out, resultLanes, result, destBytes) + return true, false, c.storeVectorBytes(destination.Reg, destBytes, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedDoubleToDword(baseOp string, spec amd64PackedDoubleDwordSpec, ins Instr, suffixes amd64PackedDoubleDwordSuffix) (bool, bool, error) { + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 %s expects source, [K mask,] destination: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if suffixes.zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z requires K1-K7: %q", baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + if suffixes.rounding != "" && spec.explicitMode != "rounding" { + return true, false, fmt.Errorf("amd64 %s does not enable explicit rounding: %q", baseOp, ins.Raw) + } + if suffixes.sae && spec.explicitMode != "sae" { + return true, false, fmt.Errorf("amd64 %s does not enable SAE: %q", baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg || amd64VectorByteWidth(destination.Reg) != spec.destBytes || !c.isGoEVEXVectorRegister(destination, spec.destBytes) { + return true, false, fmt.Errorf("amd64 %s destination does not match its X/Y result class: %q", baseOp, ins.Raw) + } + source := ins.Args[0] + if suffixes.broadcast { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a scalar memory source: %q", baseOp, ins.Raw) + } + } else if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, spec.sourceBytes) { + return true, false, fmt.Errorf("amd64 %s source width does not match its form: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s source must be a matching vector register or memory: %q", baseOp, ins.Raw) + } + if (suffixes.rounding != "" || suffixes.sae) && source.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s explicit rounding/SAE requires a register source: %q", baseOp, ins.Raw) + } + + doubles, err := c.loadPackedDoubleValues(source, spec.sourceBytes, spec.resultLanes, suffixes.broadcast) + if err != nil { + return true, false, err + } + result := c.emitPackedDoubleToDword(doubles, spec.resultLanes, spec.truncate, suffixes.rounding) + if masked { + mask, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, spec.destBytes) + if err != nil { + return true, false, err + } + physicalLanes := spec.destBytes / 4 + old := c.bitcastVectorBytesToIntegerLanes(spec.destBytes, physicalLanes, 32, oldBytes) + if physicalLanes != spec.resultLanes { + old = c.lowIntegerLanes(old, physicalLanes, spec.resultLanes, 32) + } + result = amd64ApplyIntegerLaneMask(c, spec.resultLanes, 32, result, old, mask, suffixes.zeroing) + } + return true, false, c.storePackedDwordConversionResult(destination.Reg, spec.destBytes, spec.resultLanes, result) +} + +func (c *amd64Ctx) loadPackedDoubleValues(source Operand, sourceBytes, lanes int, broadcast bool) (string, error) { + if broadcast { + scalar, err := c.evalF64(source) + if err != nil { + return "", err + } + seed := c.newTmp() + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x double> poison, double %s, i32 0\n", seed, lanes, scalar) + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x double> %%%s, <%d x double> poison, <%d x i32> zeroinitializer\n", splat, lanes, seed, lanes, lanes) + return "%" + splat, nil + } + bytes, err := c.loadPackedCompareBytes(source, sourceBytes) + if err != nil { + return "", err + } + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x double>\n", cast, sourceBytes, bytes, lanes) + return "%" + cast, nil +} + +func (c *amd64Ctx) emitPackedDoubleToDword(doubles string, lanes int, truncate bool, rounding string) string { + result := "poison" + for lane := 0; lane < lanes; lane++ { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x double> %s, i32 %d\n", value, lanes, doubles, lane) + rounded := c.newTmp() + switch { + case truncate || rounding == "RZ_SAE": + fmt.Fprintf(c.b, " %%%s = call double @llvm.trunc.f64(double %%%s)\n", rounded, value) + case rounding == "RN_SAE": + fmt.Fprintf(c.b, " %%%s = call double @llvm.roundeven.f64(double %%%s)\n", rounded, value) + case rounding == "RD_SAE": + fmt.Fprintf(c.b, " %%%s = call double @llvm.floor.f64(double %%%s)\n", rounded, value) + case rounding == "RU_SAE": + fmt.Fprintf(c.b, " %%%s = call double @llvm.ceil.f64(double %%%s)\n", rounded, value) + default: + fmt.Fprintf(c.b, " %%%s = call double @llvm.rint.f64(double %%%s)\n", rounded, value) + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.fptosi.sat.i32.f64(double %%%s)\n", converted, rounded) + lower := c.newTmp() + upper := c.newTmp() + valid := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp oge double %%%s, -2.147483648000000e+09\n", lower, rounded) + fmt.Fprintf(c.b, " %%%s = fcmp olt double %%%s, 2.147483648000000e+09\n", upper, rounded) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", valid, lower, upper) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %%%s, i32 -2147483648\n", selected, valid, converted) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i32> %s, i32 %%%s, i32 %d\n", inserted, lanes, result, selected, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) lowIntegerLanes(value string, physicalLanes, resultLanes, laneBits int) string { + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %s, <%d x i%d> poison, <%d x i32> <", low, physicalLanes, laneBits, value, physicalLanes, laneBits, resultLanes) + for lane := 0; lane < resultLanes; lane++ { + if lane != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", lane) + } + c.b.WriteString(">\n") + return "%" + low +} + +func (c *amd64Ctx) storePackedDwordConversionResult(destination Reg, destBytes, resultLanes int, result string) error { + physicalLanes := destBytes / 4 + if physicalLanes != resultLanes { + widened := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i32> %s, <%d x i32> zeroinitializer, <%d x i32> <", widened, resultLanes, result, resultLanes, physicalLanes) + for lane := 0; lane < physicalLanes; lane++ { + if lane != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", lane) + } + c.b.WriteString(">\n") + result = "%" + widened + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i32> %s to <%d x i8>\n", out, physicalLanes, result, destBytes) + return c.storeVectorBytes(destination, destBytes, "%"+out) +} diff --git a/amd64_lower_convert_double_dword_test.go b/amd64_lower_convert_double_dword_test.go new file mode 100644 index 00000000..6bbe1364 --- /dev/null +++ b/amd64_lower_convert_double_dword_test.go @@ -0,0 +1,254 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86PackedDoubleDwordCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + high := 20 + zBroadcast, zRound, zRoundMask := 8, 9, 11 + if target.goarch == "386" { + zBroadcast, zRound, zRoundMask = 0, 1, 3 + } + source := fmt.Sprintf(` +TEXT packeddoubledwordforms(SB),$0-0 + CVTPD2PL X0, X1 + CVTPD2PL 0(AX), M0 + CVTTPD2PL 16(AX), X2 + CVTTPD2PL X3, M1 + VCVTDQ2PD X0, X1 + VCVTDQ2PD 32(AX), Y2 + VCVTDQ2PD Y3, Z4 + VCVTDQ2PD X%d, K1, X%d + VCVTDQ2PD.Z 64(AX), K2, Y7 + VCVTDQ2PD.BCST 80(AX), Z%d + VCVTDQ2PD.BCST.Z 84(AX), K3, X9 + VCVTPD2DQX X0, X1 + VCVTPD2DQX 88(AX), X2 + VCVTPD2DQX X%d, K1, X%d + VCVTPD2DQX 96(AX), K1, X2 + VCVTPD2DQX.Z 104(AX), K2, X3 + VCVTPD2DQX.BCST 112(AX), X4 + VCVTPD2DQX.BCST.Z 120(AX), K3, X5 + VCVTPD2DQY Y%d, X%d + VCVTPD2DQY 128(AX), X4 + VCVTPD2DQY Y3, K1, X4 + VCVTPD2DQY.Z 128(AX), K2, X5 + VCVTPD2DQY.BCST 136(AX), X6 + VCVTPD2DQY.BCST.Z 144(AX), K3, X7 + VCVTPD2DQ Z6, Y7 + VCVTPD2DQ 160(AX), K1, Y8 + VCVTPD2DQ.Z 168(AX), K2, Y9 + VCVTPD2DQ.BCST 176(AX), Y10 + VCVTPD2DQ.BCST.Z 184(AX), K3, Y11 + VCVTPD2DQ.RN_SAE Z%d, Y10 + VCVTPD2DQ.RD_SAE.Z Z%d, K3, Y12 + VCVTPD2DQ.RU_SAE Z%d, Y13 + VCVTPD2DQ.RZ_SAE.Z Z%d, K4, Y14 + VCVTTPD2DQX X0, X1 + VCVTTPD2DQX 216(AX), X2 + VCVTTPD2DQX X%d, K1, X%d + VCVTTPD2DQX 224(AX), K1, X2 + VCVTTPD2DQX.Z 232(AX), K2, X3 + VCVTTPD2DQX.BCST 240(AX), X4 + VCVTTPD2DQX.BCST.Z 248(AX), K3, X5 + VCVTTPD2DQY Y%d, X%d + VCVTTPD2DQY 256(AX), X4 + VCVTTPD2DQY Y3, K1, X4 + VCVTTPD2DQY.Z 256(AX), K2, X5 + VCVTTPD2DQY.BCST 264(AX), X6 + VCVTTPD2DQY.BCST.Z 272(AX), K3, X7 + VCVTTPD2DQ Z6, Y7 + VCVTTPD2DQ 288(AX), K1, Y8 + VCVTTPD2DQ.Z 296(AX), K2, Y9 + VCVTTPD2DQ.BCST 304(AX), Y10 + VCVTTPD2DQ.BCST.Z 312(AX), K3, Y11 + VCVTTPD2DQ.SAE Z%d, Y10 + VCVTTPD2DQ.SAE.Z Z%d, K3, Y12 + RET +`, high, high+1, zBroadcast, + high, high+1, high, high+1, zRound, zRoundMask, zRound, zRoundMask, + high, high+1, high, high+1, zRound, zRoundMask) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packeddoubledwordforms": {Name: "packeddoubledwordforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sitofp <", "fptosi.sat.i32.f64", "select i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("packed double/dword IR is missing %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-double-dword-"+target.name+".ll", "packed-double-dword-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedDoubleDwordRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "CVTPD2PL Y0, X1", + "CVTTPD2PL X0, Y1", + "CVTTPD2PL.Z X0, X1", + "VCVTDQ2PD Y0, X1", + "VCVTDQ2PD X0, Z1", + "VCVTDQ2PD.BCST X0, X1", + "VCVTDQ2PD.RN_SAE Y0, Z1", + "VCVTPD2DQ X0, X1", + "VCVTPD2DQY X0, X1", + "VCVTPD2DQX Y0, X1", + "VCVTPD2DQY.BCST X0, X1", + "VCVTPD2DQ.RN_SAE 0(AX), Y1", + "VCVTTPD2DQX.SAE X0, X1", + "VCVTTPD2DQ.SAE 0(AX), Y1", + "VCVTTPD2DQ.Z Z0, Y1", + "VCVTTPD2DQ Z0, K0, Y1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedDoubleDwordRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + assertX86PackedDoubleDwordRejected(t, "386", "i386-unknown-linux-gnu", "VCVTPD2DQ Z8, Y1") +} + +func assertX86PackedDoubleDwordRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed double/dword tables", instruction) + } +} + +func TestAMD64PackedDoubleDwordRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT packeddoubledword(SB),NOSPLIT,$0-40 + MOVQ out+0(FP), AX + MOVQ doubles+8(FP), BX + MOVQ dwords+16(FP), CX + MOVQ old+24(FP), DX + MOVQ mask+32(FP), SI + KMOVQ SI, K1 + + VMOVDQU64 (DX), Z1 + VCVTDQ2PD (CX), K1, Z1 + VMOVDQU64 Z1, 0(AX) + + VCVTTPD2DQY (BX), X2 + VMOVDQU X2, 64(AX) + + VMOVDQU64 (BX), Z0 + VCVTPD2DQ.RD_SAE.Z Z0, K1, Y3 + VMOVDQU Y3, 80(AX) + + MOVOU (BX), X4 + CVTPD2PL X4, M0 + MOVQ M0, 112(AX) + VZEROUPPER + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: I64, Index: 4, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "packeddoubledword": { + Name: "packeddoubledword", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, Frame: frame, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +#include +#include +#include +extern void packeddoubledword(uint8_t *, const double *, const int32_t *, const double *, uint64_t); +int main(void) { + const double doubles[8] = {1.75, -2.75, 2147483648.0, NAN, -2147483648.0, -2147483649.0, 3.0, -0.0}; + const int32_t dwords[8] = {0, 1, -1, INT32_MAX, INT32_MIN, 123456789, -987654321, 42}; + const double old[8] = {100.5, 101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5}; + const uint64_t mask = 0xa5; + uint8_t out[120]; memset(out, 0xcc, sizeof(out)); + packeddoubledword(out, doubles, dwords, old, mask); + + const double *widened = (const double *)(out+0); + for (int i = 0; i < 8; i++) { + double want = (mask >> i) & 1 ? (double)dwords[i] : old[i]; + if (widened[i] != want) return 10+i; + } + const int32_t *truncated = (const int32_t *)(out+64); + const int32_t wantTruncated[4] = {1, -2, INT32_MIN, INT32_MIN}; + for (int i = 0; i < 4; i++) if (truncated[i] != wantTruncated[i]) return 30+i; + + const int32_t *roundedDown = (const int32_t *)(out+80); + const int32_t wantRoundedDown[8] = {1, 0, INT32_MIN, 0, 0, INT32_MIN, 0, 0}; + for (int i = 0; i < 8; i++) if (roundedDown[i] != wantRoundedDown[i]) return 50+i; + + const int32_t *legacy = (const int32_t *)(out+112); + if (legacy[0] != 2 || legacy[1] != -3) return 70; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_double_dword", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_convert_half.go b/amd64_lower_convert_half.go new file mode 100644 index 00000000..662fab4a --- /dev/null +++ b/amd64_lower_convert_half.go @@ -0,0 +1,241 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64HalfConversionSuffix struct { + sae bool + zeroing bool +} + +var amd64PackedHalfConversionOps = map[string]struct{}{ + "VCVTPH2PS": {}, + "VCVTPS2PH": {}, +} + +func parseAMD64HalfConversionSuffix(rawOp, baseOp string) (amd64HalfConversionSuffix, error) { + var result amd64HalfConversionSuffix + if rawOp == baseOp { + return result, nil + } + suffixes := strings.Split(strings.TrimPrefix(rawOp, baseOp+"."), ".") + for index, suffix := range suffixes { + switch suffix { + case "SAE": + if result.sae || index != 0 { + return result, fmt.Errorf("amd64 %s has invalid or duplicate .SAE suffix", baseOp) + } + result.sae = true + case "Z": + if result.zeroing || index != len(suffixes)-1 { + return result, fmt.Errorf("amd64 %s has invalid or duplicate .Z suffix", baseOp) + } + result.zeroing = true + default: + return result, fmt.Errorf("amd64 %s has unsupported suffix .%s", baseOp, suffix) + } + } + return result, nil +} + +// lowerPackedHalfConversion implements every Go 1.27 _yvcvtph2ps and +// _yvcvtps2ph row, including VEX signed immediates, EVEX masks, zeroing, SAE, +// exact-width memory accesses, and the distinct X/Y/Z narrowing widths. +func (c *amd64Ctx) lowerPackedHalfConversion(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + if _, supported := amd64PackedHalfConversionOps[baseOp]; !supported { + return false, false, nil + } + properties, err := parseAMD64HalfConversionSuffix(rawOp, baseOp) + if err != nil { + return true, false, fmt.Errorf("%w: %q", err, ins.Raw) + } + if baseOp == "VCVTPH2PS" { + return c.lowerPackedHalfToSingle(ins, properties) + } + return c.lowerPackedSingleToHalf(ins, properties) +} + +func (c *amd64Ctx) lowerPackedHalfToSingle(ins Instr, properties amd64HalfConversionSuffix) (bool, bool, error) { + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 VCVTPH2PS expects source, [K mask,] destination: %q", ins.Raw) + } + masked := len(ins.Args) == 3 + if properties.zeroing && !masked { + return true, false, fmt.Errorf("amd64 VCVTPH2PS .Z requires K1-K7: %q", ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 VCVTPH2PS masked form expects K1-K7: %q", ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("amd64 VCVTPH2PS destination must be X, Y, or Z: %q", ins.Raw) + } + destinationBytes := amd64VectorByteWidth(destination.Reg) + if destinationBytes != 16 && destinationBytes != 32 && destinationBytes != 64 || !c.isGoEVEXVectorRegister(destination, destinationBytes) { + return true, false, fmt.Errorf("amd64 VCVTPH2PS destination is outside Go 1.27's vector-register class: %q", ins.Raw) + } + sourceRegisterBytes := 16 + if destinationBytes == 64 { + sourceRegisterBytes = 32 + } + source := ins.Args[0] + if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, sourceRegisterBytes) { + return true, false, fmt.Errorf("amd64 VCVTPH2PS source width does not match its destination: %q", ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 VCVTPH2PS source must be X/Y or memory: %q", ins.Raw) + } + if properties.sae && (destinationBytes != 64 || source.Kind != OpReg) { + return true, false, fmt.Errorf("amd64 VCVTPH2PS .SAE requires a Y register source and Z destination: %q", ins.Raw) + } + + lanes := destinationBytes / 4 + inputBits, err := c.loadPackedExtendInputs(source, sourceRegisterBytes, lanes, 16) + if err != nil { + return true, false, err + } + halves := c.newTmp() + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i16> %s to <%d x half>\n", halves, lanes, inputBits, lanes) + fmt.Fprintf(c.b, " %%%s = fpext <%d x half> %%%s to <%d x float>\n", converted, lanes, halves, lanes) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x float> %%%s to <%d x i32>\n", bits, lanes, converted, lanes) + result := "%" + bits + if masked { + mask, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, destinationBytes) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(destinationBytes, lanes, 32, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, 32, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i32> %s to <%d x i8>\n", out, lanes, result, destinationBytes) + return true, false, c.storeVectorBytes(destination.Reg, destinationBytes, "%"+out) +} + +func (c *amd64Ctx) lowerPackedSingleToHalf(ins Instr, properties amd64HalfConversionSuffix) (bool, bool, error) { + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 VCVTPS2PH expects imm8, source, [K mask,] destination: %q", ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].Imm < -128 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("amd64 VCVTPS2PH expects a signed-or-unsigned imm8: %q", ins.Raw) + } + masked := len(ins.Args) == 4 + if properties.zeroing && !masked { + return true, false, fmt.Errorf("amd64 VCVTPS2PH .Z requires K1-K7: %q", ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 VCVTPS2PH masked form expects K1-K7: %q", ins.Raw) + } + if masked && c.goarch == "386" { + return true, false, fmt.Errorf("386 VCVTPS2PH does not expose Go 1.27's four-operand EVEX forms: %q", ins.Raw) + } + source := ins.Args[1] + if source.Kind != OpReg { + return true, false, fmt.Errorf("amd64 VCVTPS2PH source must be X, Y, or Z: %q", ins.Raw) + } + sourceBytes := amd64VectorByteWidth(source.Reg) + if sourceBytes != 16 && sourceBytes != 32 && sourceBytes != 64 || !c.isGoEVEXVectorRegister(source, sourceBytes) { + return true, false, fmt.Errorf("amd64 VCVTPS2PH source is outside Go 1.27's vector-register class: %q", ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + destinationRegisterBytes := 16 + if sourceBytes == 64 { + destinationRegisterBytes = 32 + } + if destination.Kind == OpReg { + if !c.isGoEVEXVectorRegister(destination, destinationRegisterBytes) { + return true, false, fmt.Errorf("amd64 VCVTPS2PH destination width does not match its source: %q", ins.Raw) + } + } else if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("amd64 VCVTPS2PH destination must be X/Y or memory: %q", ins.Raw) + } + if properties.zeroing && destination.Kind != OpReg { + return true, false, fmt.Errorf("amd64 VCVTPS2PH .Z requires a register destination: %q", ins.Raw) + } + requiresEVEX := masked || properties.sae || sourceBytes == 64 || amd64HalfConversionHighRegister(source) + if destination.Kind == OpReg && amd64HalfConversionHighRegister(destination) { + requiresEVEX = true + } + if ins.Args[0].Imm < 0 && requiresEVEX { + return true, false, fmt.Errorf("amd64 VCVTPS2PH EVEX forms require an unsigned imm8: %q", ins.Raw) + } + if properties.sae && (sourceBytes != 64 || source.Kind != OpReg) { + return true, false, fmt.Errorf("amd64 VCVTPS2PH .SAE requires a Z register source: %q", ins.Raw) + } + + lanes := sourceBytes / 4 + sourceBits, err := c.loadPackedExtendInputs(source, sourceBytes, lanes, 32) + if err != nil { + return true, false, err + } + floats := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i32> %s to <%d x float>\n", floats, lanes, sourceBits, lanes) + converted := c.newTmp() + rounding := int(ins.Args[0].Imm) & 7 + if rounding == 0 || rounding&4 != 0 { + fmt.Fprintf(c.b, " %%%s = fptrunc <%d x float> %%%s to <%d x half>\n", converted, lanes, floats, lanes) + } else { + metadata := [...]string{"round.tonearest", "round.downward", "round.upward", "round.towardzero"}[rounding] + fmt.Fprintf(c.b, " %%%s = call <%d x half> @llvm.experimental.constrained.fptrunc.v%df16.v%df32(<%d x float> %%%s, metadata !\"%s\", metadata !\"fpexcept.ignore\")\n", converted, lanes, lanes, lanes, lanes, floats, metadata) + } + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x half> %%%s to <%d x i16>\n", bits, lanes, converted, lanes) + result := "%" + bits + outputBytes := sourceBytes / 2 + if masked { + mask, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + old, err := c.loadPackedExtendInputs(destination, destinationRegisterBytes, lanes, 16) + if err != nil { + return true, false, err + } + result = amd64ApplyIntegerLaneMask(c, lanes, 16, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i16> %s to <%d x i8>\n", out, lanes, result, outputBytes) + return true, false, c.storePackedHalfResult(destination, destinationRegisterBytes, outputBytes, "%"+out) +} + +func amd64HalfConversionHighRegister(operand Operand) bool { + if operand.Kind != OpReg { + return false + } + width := amd64VectorByteWidth(operand.Reg) + index, ok := amd64VectorRegisterIndex(operand.Reg, width) + return ok && index >= 16 +} + +func (c *amd64Ctx) storePackedHalfResult(destination Operand, registerBytes, outputBytes int, value string) error { + if destination.Kind != OpReg { + return c.storeVectorBytesOperand(destination, outputBytes, value) + } + if outputBytes == registerBytes { + return c.storeVectorBytes(destination.Reg, registerBytes, value) + } + widened := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i8> %s, <%d x i8> zeroinitializer, <%d x i32> <", widened, outputBytes, value, outputBytes, registerBytes) + for lane := 0; lane < registerBytes; lane++ { + if lane > 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", lane) + } + c.b.WriteString(">\n") + return c.storeVectorBytes(destination.Reg, registerBytes, "%"+widened) +} diff --git a/amd64_lower_convert_half_test.go b/amd64_lower_convert_half_test.go new file mode 100644 index 00000000..86fa326d --- /dev/null +++ b/amd64_lower_convert_half_test.go @@ -0,0 +1,144 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedHalfConversionCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 defines the whole F16C/AVX-512 FP16 conversion pair in + // _yvcvtph2ps and _yvcvtps2ph: + // + // VCVTPH2PS X/m -> X or Y; Y/m -> Z + // VCVTPS2PH imm8, X -> X/m; Y -> X/m; Z -> Y/m + // + // EVEX forms additionally accept K1-K7 and register-destination zeroing. + // The VEX VCVTPS2PH rows accept both signed and unsigned imm8 spellings. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString(`TEXT halfconversionforms(SB),NOSPLIT,$0-0 + VCVTPH2PS X0, X1 + VCVTPH2PS 8(AX), X2 + VCVTPH2PS X20, X21 + VCVTPH2PS X3, K1, X4 + VCVTPH2PS.Z 16(AX), K2, X5 + VCVTPH2PS X6, Y7 + VCVTPH2PS 32(AX), Y8 + VCVTPH2PS X20, K3, Y21 + VCVTPH2PS.Z 48(AX), K4, Y9 + VCVTPH2PS Y10, Z1 + VCVTPH2PS 64(AX), Z2 + VCVTPH2PS Y20, K5, Z3 + VCVTPH2PS.Z 96(AX), K6, Z4 + VCVTPH2PS.SAE Y10, Z5 + VCVTPH2PS.SAE.Z Y11, K7, Z6 + VCVTPS2PH $0, X0, X1 + VCVTPS2PH $-1, X2, 128(AX) + VCVTPS2PH $255, Y3, X4 + VCVTPS2PH $-128, Y5, 160(AX) + VCVTPS2PH $7, Z1, Y2 + VCVTPS2PH.SAE $8, Z3, Y4 +`) + // Go 1.27's 386 assembler accepts the EVEX VCVTPH2PS mask + // rows, but its operand parser does not expose the four-operand + // masked VCVTPS2PH rows. Keep this difference visible here. + if target.goarch == "amd64" { + source.WriteString(` VCVTPS2PH $126, X7, K5, X17 + VCVTPS2PH.Z $126, X7, K5, X17 + VCVTPS2PH $126, X7, K5, 192(AX) + VCVTPS2PH $94, Y1, K7, X15 + VCVTPS2PH.Z $94, Y1, K7, X15 + VCVTPS2PH $94, Y1, K7, 224(AX) + VCVTPS2PH $121, Z5, K7, Y28 + VCVTPS2PH.SAE.Z $13, Z2, K6, Y13 + VCVTPS2PH $121, Z5, K7, 256(AX) +`) + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "halfconversionforms": {Name: "halfconversionforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"fpext <", "half>", "fptrunc <"} { + if !strings.Contains(ll, want) { + t.Fatalf("half conversion IR is missing %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-half-conversion-"+target.name+".ll", "packed-half-conversion-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedHalfConversionRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "VCVTPH2PS X0", + "VCVTPH2PS X0, X1, X2", + "VCVTPH2PS Y0, X1", + "VCVTPH2PS X0, Z1", + "VCVTPH2PS X0, K0, X1", + "VCVTPH2PS.Z X0, X1", + "VCVTPH2PS.BCST (AX), X1", + "VCVTPS2PH X0, X1", + "VCVTPS2PH $256, X0, X1", + "VCVTPS2PH $0, Z0, X1", + "VCVTPS2PH $0, X0, Y1", + "VCVTPS2PH $0, X0, K0, X1", + "VCVTPS2PH.Z $0, X0, X1", + "VCVTPS2PH.Z $0, X0, K1, (AX)", + "VCVTPS2PH.BCST $0, X0, X1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedHalfConversionRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "VCVTPS2PH $-1, X20, X21", + "VCVTPS2PH $-1, Y20, X21", + "VCVTPS2PH $0, X0, K1, X1", + "VCVTPS2PH $0, Y0, K1, X1", + "VCVTPS2PH $0, Z0, K1, Y1", + } { + assertX86PackedHalfConversionRejected(t, "386", "i386-unknown-linux-gnu", instruction) + } +} + +func assertX86PackedHalfConversionRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, fmt.Sprintf("TEXT bad(SB),NOSPLIT,$0-0\n\t%s\n\tRET\n", instruction)) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VCVTPH2PS/VCVTPS2PH tables", instruction) + } +} diff --git a/amd64_lower_convert_integer_float.go b/amd64_lower_convert_integer_float.go new file mode 100644 index 00000000..aa161851 --- /dev/null +++ b/amd64_lower_convert_integer_float.go @@ -0,0 +1,144 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerLegacyIntegerToFloat implements Go 1.27's complete legacy integer to +// floating-point conversion group: yxcvlf/yxcvqf scalar conversions and the +// two yxcvm2 packed conversions. +func (c *amd64Ctx) lowerLegacyIntegerToFloat(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + if strings.Contains(rawOp, ".") { + base := strings.SplitN(rawOp, ".", 2)[0] + switch base { + case "CVTSL2SS", "CVTSL2SD", "CVTSQ2SS", "CVTSQ2SD", "CVTPL2PS", "CVTPL2PD": + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", base, ins.Raw) + } + } + switch rawOp { + case "CVTSL2SS", "CVTSL2SD", "CVTSQ2SS", "CVTSQ2SD": + return c.lowerLegacyScalarIntegerToFloat(rawOp, ins) + case "CVTPL2PS", "CVTPL2PD": + return c.lowerLegacyPackedIntegerToFloat(rawOp, ins) + default: + return false, false, nil + } +} + +func (c *amd64Ctx) lowerLegacyScalarIntegerToFloat(op string, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg || !isAMD64XReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("%s %s expects GP-or-memory source and X destination: %q", c.goarch, op, ins.Raw) + } + source := ins.Args[0] + if source.Kind == OpReg { + if !c.isGoYrlRegister(source) { + return true, false, fmt.Errorf("%s %s expects GP-or-memory source: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s expects GP-or-memory source: %q", c.goarch, op, ins.Raw) + } + bits := 32 + if strings.Contains(op, "Q2") { + bits = 64 + if c.goarch == "386" { + return true, false, fmt.Errorf("386 %s is an illegal 64-bit form: %q", op, ins.Raw) + } + } + integerType := amd64IntegerTypeForBits(bits) + value, err := c.evalIntSized(source, integerType) + if err != nil { + return true, false, err + } + floatType := LLVMType("float") + if strings.HasSuffix(op, "SD") { + floatType = LLVMType("double") + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sitofp %s %s to %s\n", converted, integerType, value, floatType) + if floatType == LLVMType("float") { + return true, false, c.storeXLowF32(ins.Args[1].Reg, "%"+converted) + } + return true, false, c.storeXLowF64(ins.Args[1].Reg, "%"+converted) +} + +func (c *amd64Ctx) lowerLegacyPackedIntegerToFloat(op string, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg || !isAMD64XReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("amd64 %s expects X/MMX-or-memory source and X destination: %q", op, ins.Raw) + } + source := ins.Args[0] + sourceIsX := source.Kind == OpReg && isAMD64XReg(source.Reg) + sourceIsM := false + if source.Kind == OpReg { + _, sourceIsM = amd64ParseMReg(source.Reg) + } + if !sourceIsX && !sourceIsM && !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s expects X/MMX-or-memory source: %q", op, ins.Raw) + } + + if op == "CVTPL2PS" && !sourceIsM { + bytesValue, err := c.loadXVecOperand(source) + if err != nil { + return true, false, err + } + integers := c.newTmp() + floats := c.newTmp() + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", integers, bytesValue) + fmt.Fprintf(c.b, " %%%s = sitofp <4 x i32> %%%s to <4 x float>\n", floats, integers) + fmt.Fprintf(c.b, " %%%s = bitcast <4 x float> %%%s to <16 x i8>\n", out, floats) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) + } + + var pair string + if sourceIsX { + bytesValue, err := c.loadX(source.Reg) + if err != nil { + return true, false, err + } + all := c.newTmp() + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", all, bytesValue) + fmt.Fprintf(c.b, " %%%s = shufflevector <4 x i32> %%%s, <4 x i32> zeroinitializer, <2 x i32> \n", low, all) + pair = "%" + low + } else { + bits, err := c.evalIntSized(source, I64) + if err != nil { + return true, false, err + } + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to <2 x i32>\n", low, bits) + pair = "%" + low + } + + if op == "CVTPL2PD" { + converted := c.newTmp() + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sitofp <2 x i32> %s to <2 x double>\n", converted, pair) + fmt.Fprintf(c.b, " %%%s = bitcast <2 x double> %%%s to <16 x i8>\n", out, converted) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) + } + + // The MMX CVTPI2PS form replaces only the low two float lanes and keeps + // the high half of the X destination. + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sitofp <2 x i32> %s to <2 x float>\n", converted, pair) + oldBytes, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x float>\n", old, oldBytes) + result := "%" + old + for lane := 0; lane < 2; lane++ { + value := c.newTmp() + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x float> %%%s, i32 %d\n", value, converted, lane) + fmt.Fprintf(c.b, " %%%s = insertelement <4 x float> %s, float %%%s, i32 %d\n", next, result, value, lane) + result = "%" + next + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x float> %s to <16 x i8>\n", out, result) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) +} diff --git a/amd64_lower_convert_narrow.go b/amd64_lower_convert_narrow.go new file mode 100644 index 00000000..c49168aa --- /dev/null +++ b/amd64_lower_convert_narrow.go @@ -0,0 +1,209 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedDoubleToSingleProperties struct { + broadcast bool + rounding string + zeroing bool +} + +func amd64PackedDoubleToSingleSuffixes(rawOp, baseOp string) (amd64PackedDoubleToSingleProperties, error) { + var properties amd64PackedDoubleToSingleProperties + dot := strings.IndexByte(rawOp, '.') + if dot < 0 { + return properties, nil + } + suffixes := strings.Split(rawOp[dot+1:], ".") + for i, suffix := range suffixes { + switch suffix { + case "BCST": + if properties.broadcast || properties.rounding != "" || properties.zeroing || i != 0 { + return properties, fmt.Errorf("amd64 %s has invalid or duplicate .BCST suffix", baseOp) + } + properties.broadcast = true + case "RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE": + if properties.rounding != "" || properties.broadcast || properties.zeroing || i != 0 { + return properties, fmt.Errorf("amd64 %s has invalid or duplicate .%s suffix", baseOp, suffix) + } + properties.rounding = suffix + case "Z": + if properties.zeroing || i != len(suffixes)-1 { + return properties, fmt.Errorf("amd64 %s has invalid or duplicate .Z suffix", baseOp) + } + properties.zeroing = true + default: + return properties, fmt.Errorf("amd64 %s has unsupported suffix .%s", baseOp, suffix) + } + } + return properties, nil +} + +// lowerPackedDoubleToSingle implements the complete Go 1.27 CVTPD2PS family: +// CVTPD2PS X/m128->X, VCVTPD2PSX X/m128->X, VCVTPD2PSY Y/m256->X, +// and VCVTPD2PS Z/m512->Y, including EVEX masks, broadcast, and rounding. +func (c *amd64Ctx) lowerPackedDoubleToSingle(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + if baseOp != "CVTPD2PS" && baseOp != "VCVTPD2PS" && baseOp != "VCVTPD2PSX" && baseOp != "VCVTPD2PSY" { + return false, false, nil + } + + properties, err := amd64PackedDoubleToSingleSuffixes(rawOp, baseOp) + if err != nil { + return true, false, fmt.Errorf("%w: %q", err, ins.Raw) + } + vectorForm := baseOp != "CVTPD2PS" + if !vectorForm { + if rawOp != baseOp || len(ins.Args) != 2 { + return true, false, fmt.Errorf("amd64 CVTPD2PS expects X/m128 source and X destination: %q", ins.Raw) + } + } else if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 %s expects source, [K mask,] vector destination: %q", baseOp, ins.Raw) + } + + masked := vectorForm && len(ins.Args) == 3 + if properties.zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z form requires a K mask: %q", baseOp, ins.Raw) + } + if properties.broadcast && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s .BCST requires a memory source: %q", baseOp, ins.Raw) + } + if properties.rounding != "" && (baseOp != "VCVTPD2PS" || ins.Args[0].Kind != OpReg) { + return true, false, fmt.Errorf("amd64 %s .%s requires a Z register source and Y destination: %q", baseOp, properties.rounding, ins.Raw) + } + + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects a vector destination: %q", baseOp, ins.Raw) + } + inputBytes, convertedLanes, outputBytes := 0, 0, 0 + switch baseOp { + case "CVTPD2PS", "VCVTPD2PSX": + inputBytes, convertedLanes, outputBytes = 16, 2, 16 + if !isAMD64XReg(dstArg.Reg) { + return true, false, fmt.Errorf("amd64 %s expects an X destination: %q", baseOp, ins.Raw) + } + case "VCVTPD2PSY": + inputBytes, convertedLanes, outputBytes = 32, 4, 16 + if !isAMD64XReg(dstArg.Reg) { + return true, false, fmt.Errorf("amd64 VCVTPD2PSY expects an X destination: %q", ins.Raw) + } + case "VCVTPD2PS": + inputBytes, convertedLanes, outputBytes = 64, 8, 32 + if !isAMD64YReg(dstArg.Reg) { + return true, false, fmt.Errorf("amd64 VCVTPD2PS expects a Y destination: %q", ins.Raw) + } + } + if c.goarch == "386" && baseOp == "CVTPD2PS" { + dstIndex, _ := amd64ParseXReg(dstArg.Reg) + if dstIndex > 7 { + return true, false, fmt.Errorf("386 CVTPD2PS destination is outside Go 1.27's X register class: %q", ins.Raw) + } + } + + sourceArg := ins.Args[0] + if sourceArg.Kind == OpReg { + if !amd64VectorRegisterHasWidth(sourceArg, inputBytes) { + return true, false, fmt.Errorf("amd64 %s source width does not match its form: %q", baseOp, ins.Raw) + } + if c.goarch == "386" { + switch baseOp { + case "CVTPD2PS": + index, _ := amd64ParseXReg(sourceArg.Reg) + if index > 7 { + return true, false, fmt.Errorf("386 CVTPD2PS source is outside Go 1.27's X register class: %q", ins.Raw) + } + case "VCVTPD2PS": + index, _ := amd64ParseZReg(sourceArg.Reg) + if index > 7 { + return true, false, fmt.Errorf("386 VCVTPD2PS source is outside Go 1.27's Yzm register class: %q", ins.Raw) + } + } + } + } else if !isAMD64MemoryOperand(sourceArg) { + return true, false, fmt.Errorf("amd64 %s expects a vector register or memory source: %q", baseOp, ins.Raw) + } + + mask := "" + if masked { + maskArg := ins.Args[1] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, ok := amd64ParseKReg(maskArg.Reg) + if !ok || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + var source string + if properties.broadcast { + scalar, err := c.evalF64(sourceArg) + if err != nil { + return true, false, err + } + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x double> poison, double %s, i32 0\n", seed, convertedLanes, scalar) + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x double> %%%s, <%d x double> poison, <%d x i32> zeroinitializer\n", splat, convertedLanes, seed, convertedLanes, convertedLanes) + source = "%" + splat + } else { + bytesValue, err := c.loadPackedCompareBytes(sourceArg, inputBytes) + if err != nil { + return true, false, err + } + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x double>\n", cast, inputBytes, bytesValue, convertedLanes) + source = "%" + cast + } + + converted := c.newTmp() + if properties.rounding == "" { + fmt.Fprintf(c.b, " %%%s = fptrunc <%d x double> %s to <%d x float>\n", converted, convertedLanes, source, convertedLanes) + } else { + fmt.Fprintf(c.b, " %%%s = call <%d x float> @llvm.experimental.constrained.fptrunc.v%df32.v%df64(<%d x double> %s, metadata !\"%s\", metadata !\"fpexcept.ignore\")\n", converted, convertedLanes, convertedLanes, convertedLanes, convertedLanes, source, amd64FMA3RoundingMetadata(properties.rounding)) + } + result := "%" + converted + + if masked { + computedBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x float> %s to <%d x i32>\n", computedBits, convertedLanes, result, convertedLanes) + oldBytes, err := c.loadPackedCompareBytes(dstArg, outputBytes) + if err != nil { + return true, false, err + } + physicalLanes := outputBytes / 4 + oldAll := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i32>\n", oldAll, outputBytes, oldBytes, physicalLanes) + oldBits := "%" + oldAll + if physicalLanes != convertedLanes { + oldLow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i32> %s, <%d x i32> poison, <%d x i32> \n", oldLow, physicalLanes, oldBits, physicalLanes, convertedLanes) + oldBits = "%" + oldLow + } + maskedBits := amd64ApplyIntegerLaneMask(c, convertedLanes, 32, "%"+computedBits, oldBits, mask, properties.zeroing) + maskedValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i32> %s to <%d x float>\n", maskedValue, convertedLanes, maskedBits, convertedLanes) + result = "%" + maskedValue + } + + if convertedLanes == 2 { + widened := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <2 x float> %s, <2 x float> zeroinitializer, <4 x i32> \n", widened, result) + result = "%" + widened + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x float> %s to <%d x i8>\n", out, outputBytes/4, result, outputBytes) + return true, false, c.storeVectorBytes(dstArg.Reg, outputBytes, "%"+out) +} diff --git a/amd64_lower_convert_narrow_test.go b/amd64_lower_convert_narrow_test.go new file mode 100644 index 00000000..2fddce7a --- /dev/null +++ b/amd64_lower_convert_narrow_test.go @@ -0,0 +1,139 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedDoubleToSingleCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 uses four related tables for this family: + // CVTPD2PS: X/m128 -> X + // VCVTPD2PSX: X/m128 -> X + // VCVTPD2PSY: Y/m256 -> X + // VCVTPD2PS: Z/m512 -> Y + // The EVEX forms accept scalar-double broadcast and K1-K7 masking. Only + // the 512-bit source form accepts explicit rounding. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + // Go permits EVEX X/Y registers through 31 in 386 mode, while a + // Z source (the Yzm class) remains limited to Z0-Z7 there. + lastZ := 21 + if target.goarch == "386" { + lastZ = 7 + } + var src strings.Builder + src.WriteString("TEXT packeddoubletosingleforms(SB),NOSPLIT,$0-0\n") + src.WriteString("\tCVTPD2PS X0, X1\n") + src.WriteString("\tCVTPD2PS 8(AX), X2\n") + src.WriteString("\tVCVTPD2PSX X20, X0\n") + src.WriteString("\tVCVTPD2PSX (AX), X1\n") + src.WriteString("\tVCVTPD2PSX X20, K1, X21\n") + src.WriteString("\tVCVTPD2PSX.Z 16(AX), K2, X3\n") + src.WriteString("\tVCVTPD2PSX.BCST 24(AX), X4\n") + src.WriteString("\tVCVTPD2PSX.BCST.Z 32(AX), K3, X5\n") + src.WriteString("\tVCVTPD2PSY Y20, X0\n") + src.WriteString("\tVCVTPD2PSY (AX), X1\n") + src.WriteString("\tVCVTPD2PSY Y20, K4, X21\n") + src.WriteString("\tVCVTPD2PSY.Z 40(AX), K5, X3\n") + src.WriteString("\tVCVTPD2PSY.BCST 48(AX), X4\n") + src.WriteString("\tVCVTPD2PSY.BCST.Z 56(AX), K6, X5\n") + fmt.Fprintf(&src, "\tVCVTPD2PS Z%d, Y0\n", lastZ) + src.WriteString("\tVCVTPD2PS (AX), Y1\n") + fmt.Fprintf(&src, "\tVCVTPD2PS Z%d, K1, Y21\n", lastZ) + src.WriteString("\tVCVTPD2PS.Z 64(AX), K2, Y3\n") + src.WriteString("\tVCVTPD2PS.BCST 72(AX), Y4\n") + src.WriteString("\tVCVTPD2PS.BCST.Z 80(AX), K3, Y5\n") + for _, rounding := range []string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"} { + fmt.Fprintf(&src, "\tVCVTPD2PS.%s Z%d, Y6\n", rounding, lastZ) + } + fmt.Fprintf(&src, "\tVCVTPD2PS.RN_SAE.Z Z%d, K7, Y6\n", lastZ) + src.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packeddoubletosingleforms": {Name: "packeddoubletosingleforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-double-to-single-"+target.name+".ll", "packed-double-to-single-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedDoubleToSingleRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "CVTPD2PS X0", + "CVTPD2PS Y0, X1", + "CVTPD2PS X0, (AX)", + "CVTPD2PS.Z X0, X1", + "VCVTPD2PSX Y0, X1", + "VCVTPD2PSX X0, Y1", + "VCVTPD2PSY X0, X1", + "VCVTPD2PSY Y0, Y1", + "VCVTPD2PS Z0, X1", + "VCVTPD2PS Y0, Y1", + "VCVTPD2PS Z0, Z1", + "VCVTPD2PSX X0, K0, X1", + "VCVTPD2PSY.Z Y0, X1", + "VCVTPD2PS.Z Z0, Y1", + "VCVTPD2PSX.BCST X0, X1", + "VCVTPD2PSY.BCST Y0, X1", + "VCVTPD2PS.BCST Z0, Y1", + "VCVTPD2PSX.RN_SAE X0, X1", + "VCVTPD2PSY.RD_SAE Y0, X1", + "VCVTPD2PS.RU_SAE (AX), Y1", + "VCVTPD2PS.SAE Z0, Y1", + "VCVTPD2PS.BCST.RN_SAE (AX), Y1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedDoubleToSingleRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + + for _, instruction := range []string{ + "CVTPD2PS X8, X0", + "CVTPD2PS X0, X8", + "VCVTPD2PS Z8, Y0", + "VCVTPD2PS Z20, K1, Y0", + } { + assertX86PackedDoubleToSingleRejected(t, "386", "i386-unknown-linux-gnu", instruction) + } +} + +func assertX86PackedDoubleToSingleRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed double-to-single forms", instruction) + } +} diff --git a/amd64_lower_convert_samewidth.go b/amd64_lower_convert_samewidth.go new file mode 100644 index 00000000..655a0b4f --- /dev/null +++ b/amd64_lower_convert_samewidth.go @@ -0,0 +1,227 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64SameWidthConversionMode uint8 + +const ( + amd64SameWidthIntToFloat amd64SameWidthConversionMode = iota + amd64SameWidthFloatToInt + amd64SameWidthFloatToIntTruncate + amd64SameWidthSqrt +) + +type amd64SameWidthConversionSpec struct { + laneBits int + mode amd64SameWidthConversionMode + sae bool +} + +// lowerSameWidthPackedConversion implements all five opcodes sharing Go +// 1.27's _yvcvtdq2ps table. Although the table is shared, VCVTTPS2DQ enables +// SAE while the other four opcodes enable explicit rounding on Z forms. +func (c *amd64Ctx) lowerSameWidthPackedConversion(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + var spec amd64SameWidthConversionSpec + switch baseOp { + case "VCVTDQ2PS": + spec = amd64SameWidthConversionSpec{laneBits: 32, mode: amd64SameWidthIntToFloat} + case "VCVTPS2DQ": + spec = amd64SameWidthConversionSpec{laneBits: 32, mode: amd64SameWidthFloatToInt} + case "VCVTTPS2DQ": + spec = amd64SameWidthConversionSpec{laneBits: 32, mode: amd64SameWidthFloatToIntTruncate, sae: true} + case "VSQRTPD": + spec = amd64SameWidthConversionSpec{laneBits: 64, mode: amd64SameWidthSqrt} + case "VSQRTPS": + spec = amd64SameWidthConversionSpec{laneBits: 32, mode: amd64SameWidthSqrt} + default: + return false, false, nil + } + + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix { + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's _yvcvtdq2ps encodings: %q", c.goarch, baseOp, ins.Raw) + } + if spec.sae { + if properties.rounding != "" { + return true, false, fmt.Errorf("%s %s supports SAE, not explicit rounding: %q", c.goarch, baseOp, ins.Raw) + } + } else if properties.sae { + return true, false, fmt.Errorf("%s %s supports explicit rounding, not SAE: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects source, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's vector-register class: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[0] + explicitControl := properties.rounding != "" || properties.sae + if explicitControl && (byteWidth != 64 || source.Kind != OpReg) { + return true, false, fmt.Errorf("%s %s explicit rounding/SAE requires a Z register source: %q", c.goarch, baseOp, ins.Raw) + } + if properties.broadcast { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := byteWidth * 8 / spec.laneBits + var sourceBits string + if properties.broadcast { + scalar, err := c.evalIntSized(source, amd64IntegerTypeForBits(spec.laneBits)) + if err != nil { + return true, false, err + } + sourceBits = amd64SplatInteger(c, lanes, spec.laneBits, scalar) + } else { + bytes, err := c.loadPackedCompareBytes(source, byteWidth) + if err != nil { + return true, false, err + } + sourceBits = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, bytes) + } + computedBits := c.emitSameWidthPackedConversion(spec, sourceBits, byteWidth, properties) + if masked { + mask, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + computedBits = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, computedBits, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, computedBits, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitSameWidthPackedConversion(spec amd64SameWidthConversionSpec, sourceBits string, byteWidth int, properties amd64BinaryFloatingSuffix) string { + lanes := byteWidth * 8 / spec.laneBits + integerType := fmt.Sprintf("<%d x i%d>", lanes, spec.laneBits) + floatType := amd64FMA3LLVMType(lanes, spec.laneBits) + switch spec.mode { + case amd64SameWidthIntToFloat: + converted := c.newTmp() + if properties.rounding != "" { + fmt.Fprintf(c.b, " %%%s = call <16 x float> @llvm.experimental.constrained.sitofp.v16f32.v16i32(<16 x i32> %s, metadata !\"%s\", metadata !\"fpexcept.ignore\")\n", converted, sourceBits, amd64FMA3RoundingMetadata(properties.rounding)) + } else { + fmt.Fprintf(c.b, " %%%s = sitofp %s %s to %s\n", converted, integerType, sourceBits, floatType) + } + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to %s\n", bits, floatType, converted, integerType) + return "%" + bits + + case amd64SameWidthFloatToInt, amd64SameWidthFloatToIntTruncate: + floating := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", floating, integerType, sourceBits, floatType) + truncate := spec.mode == amd64SameWidthFloatToIntTruncate + return c.emitPackedFloatToDword("%"+floating, lanes, truncate, properties.rounding) + + case amd64SameWidthSqrt: + floating := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", floating, integerType, sourceBits, floatType) + computed := c.newTmp() + if properties.rounding != "" { + name := fmt.Sprintf("llvm.experimental.constrained.sqrt.v%df%d", lanes, spec.laneBits) + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %%%s, metadata !\"%s\", metadata !\"fpexcept.ignore\")\n", computed, floatType, name, floatType, floating, amd64FMA3RoundingMetadata(properties.rounding)) + } else { + name := fmt.Sprintf("llvm.sqrt.v%df%d", lanes, spec.laneBits) + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %%%s)\n", computed, floatType, name, floatType, floating) + } + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to %s\n", bits, floatType, computed, integerType) + return "%" + bits + } + panic("unreachable same-width packed conversion mode") +} + +func (c *amd64Ctx) emitPackedFloatToDword(floating string, lanes int, truncate bool, rounding string) string { + // LLVM 22 cannot legalize the chain-bearing AVX conversion intrinsics when + // a generic target has no AVX feature attribute. Scalarizing also avoids + // its LOOP_DEPENDENCE_MASK crash for constrained vector rounding on i386. + result := "poison" + for lane := 0; lane < lanes; lane++ { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x float> %s, i32 %d\n", value, lanes, floating, lane) + rounded := c.newTmp() + switch { + case truncate: + fmt.Fprintf(c.b, " %%%s = call float @llvm.trunc.f32(float %%%s)\n", rounded, value) + case rounding == "RN_SAE": + fmt.Fprintf(c.b, " %%%s = call float @llvm.floor.f32(float %%%s)\n", rounded, value) + fraction := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fsub float %%%s, %%%s\n", fraction, value, rounded) + aboveHalf := c.newTmp() + equalHalf := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp ogt float %%%s, 5.000000e-01\n", aboveHalf, fraction) + fmt.Fprintf(c.b, " %%%s = fcmp oeq float %%%s, 5.000000e-01\n", equalHalf, fraction) + floorInt := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.fptosi.sat.i32.f32(float %%%s)\n", floorInt, rounded) + floorLowBit := c.newTmp() + floorOdd := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i32 %%%s, 1\n", floorLowBit, floorInt) + fmt.Fprintf(c.b, " %%%s = icmp ne i32 %%%s, 0\n", floorOdd, floorLowBit) + tieRoundsUp := c.newTmp() + roundUp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", tieRoundsUp, equalHalf, floorOdd) + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", roundUp, aboveHalf, tieRoundsUp) + ceiling := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fadd float %%%s, 1.000000e+00\n", ceiling, rounded) + roundEven := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, float %%%s, float %%%s\n", roundEven, roundUp, ceiling, rounded) + rounded = roundEven + case rounding == "RD_SAE": + fmt.Fprintf(c.b, " %%%s = call float @llvm.floor.f32(float %%%s)\n", rounded, value) + case rounding == "RU_SAE": + fmt.Fprintf(c.b, " %%%s = call float @llvm.ceil.f32(float %%%s)\n", rounded, value) + case rounding == "RZ_SAE": + fmt.Fprintf(c.b, " %%%s = call float @llvm.trunc.f32(float %%%s)\n", rounded, value) + default: + fmt.Fprintf(c.b, " %%%s = call float @llvm.rint.f32(float %%%s)\n", rounded, value) + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.fptosi.sat.i32.f32(float %%%s)\n", converted, rounded) + lower := c.newTmp() + upper := c.newTmp() + valid := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp oge float %%%s, -2.147483648000000e+09\n", lower, rounded) + fmt.Fprintf(c.b, " %%%s = fcmp olt float %%%s, 2.147483648000000e+09\n", upper, rounded) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", valid, lower, upper) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %%%s, i32 -2147483648\n", selected, valid, converted) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i32> %s, i32 %%%s, i32 %d\n", inserted, lanes, result, selected, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_convert_samewidth_test.go b/amd64_lower_convert_samewidth_test.go new file mode 100644 index 00000000..02f04bae --- /dev/null +++ b/amd64_lower_convert_samewidth_test.go @@ -0,0 +1,129 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86SameWidthPackedConversionCompleteGoAssemblerForms(t *testing.T) { + // These five opcodes share Go 1.27's _yvcvtdq2ps table. All accept X/Y/Z + // register or memory sources, scalar-memory broadcast, and K1-K7 masks. + // The Z forms of all but VCVTTPS2DQ accept explicit rounding; the + // truncating conversion accepts SAE instead. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + zLast := 21 + if target.goarch == "386" { + zLast = 7 + } + var src strings.Builder + src.WriteString("TEXT samewidthpackedconversionforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VCVTDQ2PS", "VCVTPS2DQ", "VCVTTPS2DQ", "VSQRTPD", "VSQRTPS"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&src, "\t%s %s0, %s1\n", op, width, width) + fmt.Fprintf(&src, "\t%s (AX), %s2\n", op, width) + fmt.Fprintf(&src, "\t%s %s20, %s21\n", op, width, width) + fmt.Fprintf(&src, "\t%s %s20, K1, %s21\n", op, width, width) + fmt.Fprintf(&src, "\t%s.Z (AX), K2, %s22\n", op, width) + fmt.Fprintf(&src, "\t%s.BCST 8(AX), %s22\n", op, width) + fmt.Fprintf(&src, "\t%s.BCST.Z 8(AX), K3, %s23\n", op, width) + } + fmt.Fprintf(&src, "\t%s Z0, Z%d\n", op, zLast) + fmt.Fprintf(&src, "\t%s (AX), Z%d\n", op, zLast) + fmt.Fprintf(&src, "\t%s Z6, K4, Z%d\n", op, zLast) + fmt.Fprintf(&src, "\t%s.Z (AX), K5, Z%d\n", op, zLast) + fmt.Fprintf(&src, "\t%s.BCST 8(AX), Z%d\n", op, zLast) + fmt.Fprintf(&src, "\t%s.BCST.Z 8(AX), K6, Z%d\n", op, zLast) + if op == "VCVTTPS2DQ" { + fmt.Fprintf(&src, "\t%s.SAE Z6, Z%d\n", op, zLast) + fmt.Fprintf(&src, "\t%s.SAE.Z Z6, K7, Z%d\n", op, zLast) + } else { + for _, rounding := range []string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"} { + fmt.Fprintf(&src, "\t%s.%s Z6, Z%d\n", op, rounding, zLast) + } + fmt.Fprintf(&src, "\t%s.RN_SAE.Z Z6, K7, Z%d\n", op, zLast) + } + } + src.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "samewidthpackedconversionforms": {Name: "samewidthpackedconversionforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "same-width-packed-conversion-"+target.name+".ll", "same-width-packed-conversion-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86SameWidthPackedConversionRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VCVTDQ2PS X0", + "VCVTPS2DQ X0, Y1", + "VCVTTPS2DQ X0, (AX)", + "VSQRTPD X0, K0, X1", + "VSQRTPS.Z X0, X1", + "VCVTDQ2PS.BCST X0, X1", + "VCVTPS2DQ.SAE Z0, Z1", + "VCVTTPS2DQ.RN_SAE Z0, Z1", + "VSQRTPD.RN_SAE X0, X1", + "VSQRTPS.RN_SAE (AX), Z1", + "VCVTDQ2PS.BCST.RN_SAE (AX), Z1", + "VCVTTPS2DQ.BCST.SAE (AX), Z1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86SameWidthPackedConversionRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + + for _, instruction := range []string{ + "VCVTDQ2PS Z8, Z0", + "VCVTPS2DQ Z0, Z8", + "VCVTTPS2DQ.SAE Z8, Z0", + "VSQRTPD.RN_SAE Z0, Z8", + "VSQRTPS Z0, K1, Z8", + } { + t.Run("386_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86SameWidthPackedConversionRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86SameWidthPackedConversionRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yvcvtdq2ps forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_counter_zero_branch_test.go b/amd64_lower_counter_zero_branch_test.go new file mode 100644 index 00000000..cce53dac --- /dev/null +++ b/amd64_lower_counter_zero_branch_test.go @@ -0,0 +1,115 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86CounterZeroBranchCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := "TEXT counterzerobranchforms(SB),NOSPLIT,$0-0\n" + + "\tJCXZW width16\n" + + "width16:\n" + + "\tJCXZL width32\n" + + "width32:\n" + + "\tJCXZQ width64\n" + + "width64:\n" + + "\tRET\n" + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "counterzerobranchforms": {Name: "counterzerobranchforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "counter-zero-branch-"+target.name+".ll", "counter-zero-branch-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86CounterZeroBranchMatchesGoAssemblerAddressWidths(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + widths map[string]string + }{ + { + name: "amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", + widths: map[string]string{"JCXZW": "i64", "JCXZL": "i32", "JCXZQ": "i64"}, + }, + { + name: "386", goarch: "386", triple: "i386-unknown-linux-gnu", + widths: map[string]string{"JCXZW": "i32", "JCXZL": "i16", "JCXZQ": "i32"}, + }, + } { + for op, width := range target.widths { + t.Run(target.name+"_"+op, func(t *testing.T) { + source := fmt.Sprintf("TEXT counterzero(SB),NOSPLIT,$0-0\n\t%s zero\n\tRET\nzero:\n\tRET\n", op) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"counterzero": {Name: "counterzero", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, "icmp eq "+width) { + t.Fatalf("%s/%s did not test the Go assembler's %s counter width:\n%s", target.goarch, op, width, ll) + } + }) + } + } +} + +func TestTranslateX86CounterZeroBranchRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "JCXZW", + "JCXZL $1, done", + "JCXZQ done, other", + "JCXZQ AX", + "JCXZQ.Z done", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),NOSPLIT,$0-0\n\t" + instruction + "\ndone:\nother:\n\tRET\n" + file, err := Parse(ArchAMD64, source) + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's yloop table", instruction) + } + }) + } +} diff --git a/amd64_lower_crc32.go b/amd64_lower_crc32.go index 054f910a..3a9944a0 100644 --- a/amd64_lower_crc32.go +++ b/amd64_lower_crc32.go @@ -3,69 +3,57 @@ package plan9asm import "fmt" func (c *amd64Ctx) lowerCrc32(op Op, ins Instr) (ok bool, terminated bool, err error) { + sourceType := LLVMType("") + intrinsic := "" + resultType := I32 switch op { - case "CRC32B", "CRC32W", "CRC32L", "CRC32Q": - // ok + case "CRC32B": + sourceType = I8 + intrinsic = "llvm.x86.sse42.crc32.32.8" + case "CRC32W": + sourceType = I16 + intrinsic = "llvm.x86.sse42.crc32.32.16" + case "CRC32L": + sourceType = I32 + intrinsic = "llvm.x86.sse42.crc32.32.32" + case "CRC32Q": + if c.goarch == "386" { + return true, false, fmt.Errorf("386 CRC32Q is illegal in 32-bit mode: %q", ins.Raw) + } + sourceType = I64 + resultType = I64 + intrinsic = "llvm.x86.sse42.crc32.64.64" default: return false, false, nil } - if len(ins.Args) != 2 || ins.Args[0].Kind != OpMem || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects mem, reg: %q", op, ins.Raw) + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects register/memory source and register destination: %q", c.goarch, op, ins.Raw) + } + source, destination := ins.Args[0], ins.Args[1] + if source.Kind == OpReg { + valid := isX86YrlRegisterForArch(source.Reg, c.goarch) + if op == "CRC32B" { + valid = isGoYmbRegisterForArch(source.Reg, c.goarch) + } + if !valid { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's %s class: %q", c.goarch, op, map[bool]string{true: "Ymb", false: "Yml"}[op == "CRC32B"], ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's register/memory class: %q", c.goarch, op, ins.Raw) + } + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yrl class: %q", c.goarch, op, ins.Raw) } - src := ins.Args[0].Mem - dst := ins.Args[1].Reg - addr, err := c.addrFromMem(src) + sourceValue, err := c.evalIntSized(source, sourceType) if err != nil { return true, false, err } - p := c.ptrFromAddrI64(addr) - - dv, err := c.loadReg(dst) + crcValue, err := c.evalIntSized(destination, resultType) if err != nil { return true, false, err } - - switch op { - case "CRC32Q": - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i64, ptr %s, align 1\n", ld, p) - call := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i64 @llvm.x86.sse42.crc32.64.64(i64 %s, i64 %%%s)\n", call, dv, ld) - return true, false, c.storeReg(dst, "%"+call) - - case "CRC32L": - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i32, ptr %s, align 1\n", ld, p) - crc32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", crc32, dv) - call := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i32 @llvm.x86.sse42.crc32.32.32(i32 %%%s, i32 %%%s)\n", call, crc32, ld) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, call) - return true, false, c.storeReg(dst, "%"+z) - - case "CRC32W": - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i16, ptr %s, align 1\n", ld, p) - crc32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", crc32, dv) - call := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i32 @llvm.x86.sse42.crc32.32.16(i32 %%%s, i16 %%%s)\n", call, crc32, ld) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, call) - return true, false, c.storeReg(dst, "%"+z) - - case "CRC32B": - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i8, ptr %s, align 1\n", ld, p) - crc32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", crc32, dv) - call := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i32 @llvm.x86.sse42.crc32.32.8(i32 %%%s, i8 %%%s)\n", call, crc32, ld) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, call) - return true, false, c.storeReg(dst, "%"+z) - } - return true, false, fmt.Errorf("amd64: unknown CRC32 op %s", op) + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %s, %s %s)\n", call, resultType, intrinsic, resultType, crcValue, sourceType, sourceValue) + return true, false, c.storeRegSized(destination.Reg, resultType, "%"+call) } diff --git a/amd64_lower_crc32_complete_test.go b/amd64_lower_crc32_complete_test.go new file mode 100644 index 00000000..815c6699 --- /dev/null +++ b/amd64_lower_crc32_complete_test.go @@ -0,0 +1,232 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86CRC32CompleteFormsSource(goarch string) string { + var source strings.Builder + source.WriteString("DATA crc32data+0(SB)/8, $1\n") + source.WriteString("GLOBL crc32data(SB), $8\n") + source.WriteString("TEXT crc32forms(SB),$0-0\n") + for _, width := range []string{"B", "W", "L"} { + op := "CRC32" + width + sourceRegister := "AX" + if width == "B" { + sourceRegister = "AL" + } + fmt.Fprintf(&source, "\t%s %s, BX\n", op, sourceRegister) + fmt.Fprintf(&source, "\t%s 8(BX), CX\n", op) + fmt.Fprintf(&source, "\t%s crc32data(SB), DX\n", op) + if width == "B" { + fmt.Fprintf(&source, "\t%s AX, DI\n", op) + } + if goarch == "amd64" { + fmt.Fprintf(&source, "\t%s R11, R12\n", op) + } else { + fmt.Fprintf(&source, "\t%s %s, SP\n", op, sourceRegister) + } + } + if goarch == "amd64" { + for _, form := range []string{ + "CRC32Q AX, BX", + "CRC32Q 8(BX), CX", + "CRC32Q crc32data(SB), DX", + "CRC32Q R11, R12", + } { + fmt.Fprintf(&source, "\t%s\n", form) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86CRC32CompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86CRC32CompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"crc32forms": {Name: "crc32forms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "@llvm.x86.sse42.crc32.32.8", + "@llvm.x86.sse42.crc32.32.16", + "@llvm.x86.sse42.crc32.32.32", + `"target-features"="+crc32,+sse4.2"`, + } { + if !strings.Contains(ir, want) { + t.Fatalf("CRC32 lowering omitted %q:\n%s", want, ir) + } + } + if target.goarch == "amd64" && !strings.Contains(ir, "@llvm.x86.sse42.crc32.64.64") { + t.Fatalf("CRC32Q lowering omitted i64 intrinsic:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "crc32-"+target.name+".ll", "crc32-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86CRC32RejectsFormsOutsideGo127Optabs(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "CRC32B $1, AX"}, + {goarch: "amd64", instruction: "CRC32W AL, AX"}, + {goarch: "amd64", instruction: "CRC32L X0, AX"}, + {goarch: "amd64", instruction: "CRC32Q AX, 0(BX)"}, + {goarch: "amd64", instruction: "CRC32L AX, X0"}, + {goarch: "amd64", instruction: "CRC32L AX, AL"}, + {goarch: "amd64", instruction: "CRC32L AX"}, + {goarch: "amd64", instruction: "CRC32L.Z AX, BX"}, + {goarch: "386", instruction: "CRC32Q AX, BX"}, + {goarch: "386", instruction: "CRC32L R8, AX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ycrc32b/ycrc32l tables", test.instruction) + } + }) + } +} + +func TestAMD64CRC32RuntimeSemanticsAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT crc32semantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + + MOVL $0x12345678, BX + MOVL $0xab00, AX + CRC32B AH, BX + MOVQ BX, 0(DI) + + MOVL $0x23456789, BX + MOVL $0xcdef, AX + CRC32W AX, BX + MOVQ BX, 8(DI) + + MOVL $0x3456789a, BX + MOVL $0x89abcdef, 40(DI) + CRC32L 40(DI), BX + MOVQ BX, 16(DI) + + MOVL $0x456789ab, BX + MOVQ $0x0123456789abcdef, 48(DI) + CRC32Q 48(DI), BX + MOVQ BX, 24(DI) + + MOVL $0x7fffffff, R8 + ADDL $1, R8 + STC + MOVL $0, BX + CRC32B AL, BX + SETCS 32(DI) + SETOS 33(DI) + SETEQ 34(DI) + SETMI 35(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "crc32semantics": { + Name: "crc32semantics", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void crc32semantics(uint8_t *); +static uint32_t crc32c(uint32_t crc, uint64_t value, unsigned bytes) { + for (unsigned i = 0; i < bytes; i++) { + crc ^= (uint8_t)value; + value >>= 8; + for (unsigned bit = 0; bit < 8; bit++) + crc = (crc >> 1) ^ (UINT32_C(0x82f63b78) & (uint32_t)-(int32_t)(crc & 1)); + } + return crc; +} +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + uint8_t out[64] = {0}; + crc32semantics(out); + if (load64(out + 0) != crc32c(UINT32_C(0x12345678), UINT64_C(0xab), 1)) return 10; + if (load64(out + 8) != crc32c(UINT32_C(0x23456789), UINT64_C(0xcdef), 2)) return 11; + if (load64(out + 16) != crc32c(UINT32_C(0x3456789a), UINT64_C(0x89abcdef), 4)) return 12; + if (load64(out + 24) != crc32c(UINT32_C(0x456789ab), UINT64_C(0x0123456789abcdef), 8)) return 13; + if (out[32] != 1 || out[33] != 1 || out[34] != 0 || out[35] != 1) return 14; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "crc32_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_descriptor.go b/amd64_lower_descriptor.go new file mode 100644 index 00000000..5d8cf6f9 --- /dev/null +++ b/amd64_lower_descriptor.go @@ -0,0 +1,166 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var x86DescriptorOps = map[string]struct{}{ + "LGDT": {}, "LIDT": {}, "SGDT": {}, "SIDT": {}, + "LLDT": {}, "LTR": {}, "LMSW": {}, + "SLDTW": {}, "SLDTL": {}, "SLDTQ": {}, + "SMSWW": {}, "SMSWL": {}, "SMSWQ": {}, + "STRW": {}, "STRL": {}, "STRQ": {}, +} + +// lowerDescriptorTable covers Go 1.27's complete x86 descriptor-table and +// system-selector family. These instructions are privileged or may be blocked +// by UMIP, so the lowering preserves them as LLVM inline assembly rather than +// approximating their machine-state effects. +func (c *amd64Ctx) lowerDescriptorTable(op Op, ins Instr) (ok bool, terminated bool, err error) { + if ok, terminated, err := c.lowerSegmentQuery(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerFarPointer(op, ins); ok { + return ok, terminated, err + } + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + if _, ok := x86DescriptorOps[baseOp]; !ok { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 1 { + return true, false, fmt.Errorf("%s %s expects one operand: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && strings.HasSuffix(baseOp, "Q") { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + + operand := ins.Args[0] + switch baseOp { + case "LGDT", "LIDT": + if !isAMD64MemoryOperand(operand) { + return true, false, fmt.Errorf("%s %s expects Go 1.27 Ym memory: %q", c.goarch, baseOp, ins.Raw) + } + ptr, ptrType, err := c.x86DescriptorMemoryPointer(operand) + if err != nil { + return true, false, err + } + bytes := 10 + if c.goarch == "386" { + bytes = 6 + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s elementtype([%d x i8]) %s)\n", + strings.ToLower(baseOp)+" $0", "*m,~{memory},~{dirflag},~{fpsr},~{flags}", ptrType, bytes, ptr) + return true, false, nil + + case "SGDT", "SIDT": + if !isAMD64MemoryOperand(operand) { + return true, false, fmt.Errorf("%s %s expects Go 1.27 Ym memory: %q", c.goarch, baseOp, ins.Raw) + } + ptr, ptrType, err := c.x86DescriptorMemoryPointer(operand) + if err != nil { + return true, false, err + } + bytes := 10 + if c.goarch == "386" { + bytes = 6 + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s elementtype([%d x i8]) %s)\n", + strings.ToLower(baseOp)+" $0", "=*m,~{memory},~{dirflag},~{fpsr},~{flags}", ptrType, bytes, ptr) + return true, false, nil + + case "LLDT", "LTR", "LMSW": + if operand.Kind != OpReg && !isAMD64MemoryOperand(operand) { + return true, false, fmt.Errorf("%s %s expects Go 1.27 Yml register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if operand.Kind == OpReg { + if !isX86YrlRegisterForArch(operand.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s register is outside Go 1.27's Yml class: %q", c.goarch, baseOp, ins.Raw) + } + value, err := c.evalIntSized(operand, I16) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(i16 %s)\n", + strings.ToLower(baseOp)+" $0", "r,~{memory},~{dirflag},~{fpsr},~{flags}", value) + return true, false, nil + } + ptr, ptrType, err := c.x86DescriptorMemoryPointer(operand) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s elementtype(i16) %s)\n", + strings.ToLower(baseOp)+" $0", "*m,~{memory},~{dirflag},~{fpsr},~{flags}", ptrType, ptr) + return true, false, nil + + case "SLDTW", "SLDTL", "SLDTQ", "SMSWW", "SMSWL", "SMSWQ", "STRW", "STRL", "STRQ": + return true, false, c.lowerDescriptorResult(baseOp, operand, ins) + default: + panic("descriptor opcode precheck drift") + } +} + +func (c *amd64Ctx) lowerDescriptorResult(op string, destination Operand, ins Instr) error { + if destination.Kind != OpReg && !isAMD64MemoryOperand(destination) { + return fmt.Errorf("%s %s expects Go 1.27 Yml register or memory: %q", c.goarch, op, ins.Raw) + } + if destination.Kind == OpReg && !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return fmt.Errorf("%s %s register is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + typ := I16 + switch op[len(op)-1] { + case 'L': + typ = I32 + case 'Q': + typ = I64 + } + asm := strings.ToLower(op) + " $0" + if destination.Kind == OpReg { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q()\n", + result, typ, asm, "=r,~{memory},~{dirflag},~{fpsr},~{flags}") + return c.storeRegSized(destination.Reg, typ, "%"+result) + } + ptr, ptrType, err := c.x86DescriptorMemoryPointer(destination) + if err != nil { + return err + } + // Intel defines every memory destination as m16 even when Go selects the + // L/Q spelling (the operand-size prefix only affects a register target). + // LLVM's integrated assembler consequently rejects sldtl/sldtq, smswl/q, + // and strl/q with memory, so emit the architectural unsuffixed m16 form. + memoryAsm := strings.ToLower(op[:len(op)-1]) + " $0" + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s elementtype(%s) %s)\n", + memoryAsm, "=*m,~{memory},~{dirflag},~{fpsr},~{flags}", ptrType, I16, ptr) + return nil +} + +func (c *amd64Ctx) x86DescriptorMemoryPointer(operand Operand) (ptr, ptrType string, err error) { + switch operand.Kind { + case OpMem: + return c.ptrFromMem(operand.Mem) + case OpSym: + ptr, err := c.ptrFromSB(operand.Sym) + return ptr, "ptr", err + case OpFP: + if c.classicFrame != "" { + return c.classicFramePtr(operand.FPOffset), "ptr", nil + } + if ptr := c.fpParamAlloca[operand.FPOffset]; ptr != "" { + return ptr, "ptr", nil + } + if ptr, _, ok := c.fpResultAlloca(operand.FPOffset); ok { + return ptr, "ptr", nil + } + return "", "", fmt.Errorf("%s descriptor memory operand has no mutable FP slot at +%d(FP)", c.goarch, operand.FPOffset) + default: + return "", "", fmt.Errorf("%s descriptor instruction expected memory, got %s", c.goarch, operand.String()) + } +} diff --git a/amd64_lower_dot_float.go b/amd64_lower_dot_float.go new file mode 100644 index 00000000..98c97e7b --- /dev/null +++ b/amd64_lower_dot_float.go @@ -0,0 +1,141 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedFloatingDotForm uint8 + +const ( + // amd64PackedFloatingDotLegacy is Go's yxshuf table: imm8, X/m128, X. + amd64PackedFloatingDotLegacy amd64PackedFloatingDotForm = iota + // amd64PackedFloatingDotVEX128 is Go's _yvdppd table: imm8, X/m128, + // X, X. The Go 386 frontend cannot represent the four operands. + amd64PackedFloatingDotVEX128 + // amd64PackedFloatingDotVEX128Or256 is Go's _yvblendpd table, adding + // the corresponding Y/m256, Y, Y row. + amd64PackedFloatingDotVEX128Or256 +) + +type amd64PackedFloatingDotSpec struct { + form amd64PackedFloatingDotForm + laneBits int +} + +// amd64PackedFloatingDotSpecs is the complete Go 1.27 grammar for the SSE4.1 +// and AVX floating dot-product family. The form class captures operand count, +// legal vector widths, and the 386 frontend restriction; laneBits selects the +// hardware intrinsic and immediate-bit interpretation. +var amd64PackedFloatingDotSpecs = map[Op]amd64PackedFloatingDotSpec{ + "DPPD": {form: amd64PackedFloatingDotLegacy, laneBits: 64}, + "DPPS": {form: amd64PackedFloatingDotLegacy, laneBits: 32}, + "VDPPD": {form: amd64PackedFloatingDotVEX128, laneBits: 64}, + "VDPPS": {form: amd64PackedFloatingDotVEX128Or256, laneBits: 32}, +} + +func (c *amd64Ctx) lowerPackedFloatingDot(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64PackedFloatingDotSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed form in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) == 0 || ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("%s %s expects a Yu8 immediate: %q", c.goarch, baseOp, ins.Raw) + } + + if spec.form == amd64PackedFloatingDotLegacy { + return c.lowerLegacyPackedFloatingDot(baseOp, spec, ins) + } + return c.lowerVEXPackedFloatingDot(baseOp, spec, ins) +} + +func (c *amd64Ctx) lowerLegacyPackedFloatingDot(baseOp string, spec amd64PackedFloatingDotSpec, ins Instr) (bool, bool, error) { + if len(ins.Args) != 3 || !c.isGoVEXVectorRegister(ins.Args[2], 16, false) { + return true, false, fmt.Errorf("%s %s expects imm8, X/m128, X: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoVEXVectorRegister(ins.Args[1], 16, true) { + return true, false, fmt.Errorf("%s %s source must be X/m128: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[1].Kind == OpMem && !x86MemoryRegistersValidForArch(ins.Args[1].Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s source uses an out-of-range address register: %q", c.goarch, baseOp, ins.Raw) + } + first, err := c.loadPackedFloatingDotOperand(ins.Args[1], 16, spec.laneBits) + if err != nil { + return true, false, err + } + second, err := c.loadPackedFloatingDotOperand(ins.Args[2], 16, spec.laneBits) + if err != nil { + return true, false, err + } + result := c.emitPackedFloatingDot(spec, 16, first, second, uint8(ins.Args[0].Imm)) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <16 x i8>\n", out, amd64FMA3LLVMType(128/spec.laneBits, spec.laneBits), result) + return true, false, c.storeX(ins.Args[2].Reg, "%"+out) +} + +func (c *amd64Ctx) lowerVEXPackedFloatingDot(baseOp string, spec amd64PackedFloatingDotSpec, ins Instr) (bool, bool, error) { + if c.goarch == "386" { + return true, false, fmt.Errorf("386 %s exceeds the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 4 || ins.Args[3].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects imm8, source1, source2, destination: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(ins.Args[3].Reg) + if byteWidth != 16 && (spec.form != amd64PackedFloatingDotVEX128Or256 || byteWidth != 32) { + return true, false, fmt.Errorf("amd64 %s destination width is absent from its Go 1.27 table: %q", baseOp, ins.Raw) + } + if !c.isGoVEXVectorRegister(ins.Args[3], byteWidth, false) || !c.isGoVEXVectorRegister(ins.Args[2], byteWidth, false) { + return true, false, fmt.Errorf("amd64 %s second source and destination must be matching VEX registers: %q", baseOp, ins.Raw) + } + if !c.isGoVEXVectorRegister(ins.Args[1], byteWidth, true) { + return true, false, fmt.Errorf("amd64 %s first source must be a matching VEX register or memory: %q", baseOp, ins.Raw) + } + if ins.Args[1].Kind == OpMem && !x86MemoryRegistersValidForArch(ins.Args[1].Mem, c.goarch) { + return true, false, fmt.Errorf("amd64 %s source uses an out-of-range address register: %q", baseOp, ins.Raw) + } + first, err := c.loadPackedFloatingDotOperand(ins.Args[1], byteWidth, spec.laneBits) + if err != nil { + return true, false, err + } + second, err := c.loadPackedFloatingDotOperand(ins.Args[2], byteWidth, spec.laneBits) + if err != nil { + return true, false, err + } + result := c.emitPackedFloatingDot(spec, byteWidth, first, second, uint8(ins.Args[0].Imm)) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", out, amd64FMA3LLVMType(byteWidth*8/spec.laneBits, spec.laneBits), result, byteWidth) + return true, false, c.storeVectorBytes(ins.Args[3].Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) loadPackedFloatingDotOperand(operand Operand, byteWidth, laneBits int) (string, error) { + bytesValue, err := c.loadPackedCompareBytes(operand, byteWidth) + if err != nil { + return "", err + } + lanes := byteWidth * 8 / laneBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", result, byteWidth, bytesValue, amd64FMA3LLVMType(lanes, laneBits)) + return "%" + result, nil +} + +func (c *amd64Ctx) emitPackedFloatingDot(spec amd64PackedFloatingDotSpec, byteWidth int, first, second string, immediate uint8) string { + lanes := byteWidth * 8 / spec.laneBits + typeName := amd64FMA3LLVMType(lanes, spec.laneBits) + intrinsic := "llvm.x86.sse41.dpps" + if spec.laneBits == 64 { + intrinsic = "llvm.x86.sse41.dppd" + } else if byteWidth == 32 { + intrinsic = "llvm.x86.avx.dp.ps.256" + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %s, %s %s, i8 %d)\n", result, typeName, intrinsic, typeName, second, typeName, first, immediate) + return "%" + result +} diff --git a/amd64_lower_dot_float_test.go b/amd64_lower_dot_float_test.go new file mode 100644 index 00000000..36807768 --- /dev/null +++ b/amd64_lower_dot_float_test.go @@ -0,0 +1,207 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64PackedFloatingDotGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64PackedFloatingDotSpec{ + "DPPD": {form: amd64PackedFloatingDotLegacy, laneBits: 64}, + "DPPS": {form: amd64PackedFloatingDotLegacy, laneBits: 32}, + "VDPPD": {form: amd64PackedFloatingDotVEX128, laneBits: 64}, + "VDPPS": {form: amd64PackedFloatingDotVEX128Or256, laneBits: 32}, + } + if len(amd64PackedFloatingDotSpecs) != len(expected) { + t.Fatalf("floating dot grammar has %d entries, want %d", len(amd64PackedFloatingDotSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64PackedFloatingDotSpecs[op]; !ok { + t.Errorf("floating dot grammar omitted %s", op) + } else if got != want { + t.Errorf("floating dot grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86PackedFloatingDotCompleteFormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 15 + if target.goarch == "386" { + last = 7 + } + var sourceBuilder strings.Builder + sourceBuilder.WriteString("TEXT floatdotforms(SB),$0-0\n") + fmt.Fprintf(&sourceBuilder, "\tDPPD $0x31, X0, X%d\n", last) + fmt.Fprintf(&sourceBuilder, "\tDPPD $0x31, 0(AX), X%d\n", last) + fmt.Fprintf(&sourceBuilder, "\tDPPS $0xf1, X0, X%d\n", last) + fmt.Fprintf(&sourceBuilder, "\tDPPS $0xf1, 16(AX), X%d\n", last) + if target.goarch == "amd64" { + fmt.Fprintf(&sourceBuilder, "\tVDPPD $0x31, X0, X1, X%d\n", last) + fmt.Fprintf(&sourceBuilder, "\tVDPPD $0x31, 32(AX), X1, X%d\n", last) + fmt.Fprintf(&sourceBuilder, "\tVDPPS $0xf1, X0, X1, X%d\n", last) + fmt.Fprintf(&sourceBuilder, "\tVDPPS $0xf1, 48(AX), X1, X%d\n", last) + fmt.Fprintf(&sourceBuilder, "\tVDPPS $0xf1, Y0, Y1, Y%d\n", last) + fmt.Fprintf(&sourceBuilder, "\tVDPPS $0xf1, 64(AX), Y1, Y%d\n", last) + } + sourceBuilder.WriteString("\tRET\n") + source := sourceBuilder.String() + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"floatdotforms": {Name: "floatdotforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "call <2 x double> @llvm.x86.sse41.dppd", + "call <4 x float> @llvm.x86.sse41.dpps", + } { + if !strings.Contains(ir, want) { + t.Fatalf("packed floating dot lowering omitted %q:\n%s", want, ir) + } + } + if target.goarch == "amd64" && !strings.Contains(ir, "call <8 x float> @llvm.x86.avx.dp.ps.256") { + t.Fatalf("packed floating dot lowering omitted Y-width intrinsic:\n%s", ir) + } + wantFeatures := `"target-features"="+sse4.1"` + if target.goarch == "amd64" { + wantFeatures = `"target-features"="+avx,+sse4.1"` + } + if !strings.Contains(ir, wantFeatures) { + t.Fatalf("packed floating dot lowering omitted %s:\n%s", wantFeatures, ir) + } + compileLLVMToObject(t, llc, target.triple, "float-dot-"+target.name+".ll", "float-dot-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86PackedFloatingDotRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "DPPD $-1, X0, X1"}, + {goarch: "amd64", instruction: "DPPD $256, X0, X1"}, + {goarch: "amd64", instruction: "DPPS.Z $1, X0, X1"}, + {goarch: "amd64", instruction: "DPPD $1, Y0, Y1"}, + {goarch: "amd64", instruction: "VDPPD $1, Y0, Y1, Y2"}, + {goarch: "amd64", instruction: "VDPPS $1, Z0, Z1, Z2"}, + {goarch: "amd64", instruction: "VDPPS $1, X0, Y1, Y2"}, + {goarch: "386", instruction: "DPPD $1, X0, X8"}, + {goarch: "386", instruction: "VDPPS $1, Y0, Y1, Y2"}, + {goarch: "386", instruction: "VDPPS $1, Y0, Y1, Y8"}, + {goarch: "386", instruction: "VDPPS $1, 8(R9), Y1, Y2"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside the Go table for %s", test.instruction, test.goarch) + } + }) + } +} + +func TestAMD64PackedFloatingDotRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT floatdotsemantics(SB),$0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), CX + MOVQ b+16(FP), DX + MOVUPS 0(CX), X0 + MOVUPS 0(DX), X1 + STC + DPPS $0xf1, X0, X1 + MOVUPS X1, 0(AX) + SETCS 16(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "floatdotsemantics": { + Name: "floatdotsemantics", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void floatdotsemantics(uint8_t *, const float *, const float *); +int main(void) { + uint8_t out[17] = {0}; + const float a[4] = {1.0f, 2.0f, 3.0f, 4.0f}; + const float b[4] = {5.0f, 6.0f, 7.0f, 8.0f}; + float got[4]; + floatdotsemantics(out, a, b); + memcpy(got, out, 16); + if (got[0] != 70.0f || got[1] != 0.0f || got[2] != 0.0f || got[3] != 0.0f) return 10; + if (out[16] != 1) return 11; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_float_dot_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_dot_product.go b/amd64_lower_dot_product.go new file mode 100644 index 00000000..d86a4963 --- /dev/null +++ b/amd64_lower_dot_product.go @@ -0,0 +1,166 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedDotProductSpec struct { + inputBits int + saturate bool +} + +// lowerPackedDotProduct implements the four VNNI dot-product opcodes sharing +// Go 1.27's _yvblendmpd table. Plan 9 lists the signed r/m source first and +// the encoded V source second; VPDPBUSD treats that second source as unsigned. +func (c *amd64Ctx) lowerPackedDotProduct(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + var spec amd64PackedDotProductSpec + switch baseOp { + case "VPDPBUSD": + spec = amd64PackedDotProductSpec{inputBits: 8} + case "VPDPBUSDS": + spec = amd64PackedDotProductSpec{inputBits: 8, saturate: true} + case "VPDPWSSD": + spec = amd64PackedDotProductSpec{inputBits: 16} + case "VPDPWSSDS": + spec = amd64PackedDotProductSpec{inputBits: 16, saturate: true} + default: + return false, false, nil + } + + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix || properties.sae || properties.rounding != "" { + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's _yvblendmpd encodings: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects source2, source1, [K mask,] accumulator: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7 as its third operand: %q", baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s accumulator must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || + !c.isGoPackedVectorMoveRegister(destination, byteWidth) || + !c.isGoPackedVectorMoveRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s source1 and accumulator must be matching Go vector registers: %q", c.goarch, baseOp, ins.Raw) + } + rmSource := ins.Args[0] + if properties.broadcast { + if !isAMD64MemoryOperand(rmSource) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory source2: %q", c.goarch, baseOp, ins.Raw) + } + } else if rmSource.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(rmSource, byteWidth) { + return true, false, fmt.Errorf("%s %s source2 register must match the accumulator width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(rmSource) { + return true, false, fmt.Errorf("%s %s source2 must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + dwordLanes := byteWidth / 4 + inputLanes := byteWidth * 8 / spec.inputBits + var rmBytes string + if properties.broadcast { + scalar, err := c.evalIntSized(rmSource, I32) + if err != nil { + return true, false, err + } + dwords := amd64SplatInteger(c, dwordLanes, 32, scalar) + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i32> %s to <%d x i8>\n", cast, dwordLanes, dwords, byteWidth) + rmBytes = "%" + cast + } else { + rmBytes, err = c.loadPackedCompareBytes(rmSource, byteWidth) + if err != nil { + return true, false, err + } + } + vBytes, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + rm := c.bitcastVectorBytesToIntegerLanes(byteWidth, inputLanes, spec.inputBits, rmBytes) + v := c.bitcastVectorBytesToIntegerLanes(byteWidth, inputLanes, spec.inputBits, vBytes) + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, dwordLanes, 32, oldBytes) + computed := c.emitPackedDotProduct(spec, dwordLanes, rm, v, old) + if masked { + mask, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + computed = amd64ApplyI32LaneMask(c, dwordLanes, computed, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i32> %s to <%d x i8>\n", out, dwordLanes, computed, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPackedDotProduct(spec amd64PackedDotProductSpec, dwordLanes int, rm, v, accumulator string) string { + inputsPerDword := 32 / spec.inputBits + result := "poison" + for lane := 0; lane < dwordLanes; lane++ { + accumulatorLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i32> %s, i32 %d\n", accumulatorLane, dwordLanes, accumulator, lane) + wideAccumulator := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext i32 %%%s to i64\n", wideAccumulator, accumulatorLane) + total := "%" + wideAccumulator + for item := 0; item < inputsPerDword; item++ { + inputLane := lane*inputsPerDword + item + rmLane := c.newTmp() + vLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", rmLane, dwordLanes*inputsPerDword, spec.inputBits, rm, inputLane) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", vLane, dwordLanes*inputsPerDword, spec.inputBits, v, inputLane) + wideRM := c.newTmp() + wideV := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext i%d %%%s to i64\n", wideRM, spec.inputBits, rmLane) + if spec.inputBits == 8 { + fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i64\n", wideV, vLane) + } else { + fmt.Fprintf(c.b, " %%%s = sext i16 %%%s to i64\n", wideV, vLane) + } + product := c.newTmp() + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %%%s\n", product, wideRM, wideV) + fmt.Fprintf(c.b, " %%%s = add i64 %s, %%%s\n", next, total, product) + total = "%" + next + } + if spec.saturate { + above := c.newTmp() + below := c.newTmp() + capped := c.newTmp() + bounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp sgt i64 %s, 2147483647\n", above, total) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 2147483647, i64 %s\n", capped, above, total) + fmt.Fprintf(c.b, " %%%s = icmp slt i64 %%%s, -2147483648\n", below, capped) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 -2147483648, i64 %%%s\n", bounded, below, capped) + total = "%" + bounded + } + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", narrow, total) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i32> %s, i32 %%%s, i32 %d\n", inserted, dwordLanes, result, narrow, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_dot_product_test.go b/amd64_lower_dot_product_test.go new file mode 100644 index 00000000..cab55ff6 --- /dev/null +++ b/amd64_lower_dot_product_test.go @@ -0,0 +1,119 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedDotProductCompleteGoAssemblerForms(t *testing.T) { + // These four opcodes share Go 1.27's six-row _yvblendmpd table. Each + // width accepts register/memory source 2, register source 1, and an + // accumulator destination; amd64 additionally accepts K1-K7 merge/.Z. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + zLast := 22 + if target.goarch == "386" { + zLast = 7 + } + var source strings.Builder + source.WriteString("TEXT packeddotproductforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VPDPBUSD", "VPDPBUSDS", "VPDPWSSD", "VPDPWSSDS"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&source, "\t%s %s0, %s1, %s2\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s 8(AX), %s20, %s21\n", op, width, width) + fmt.Fprintf(&source, "\t%s.BCST 12(AX), %s20, %s22\n", op, width, width) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s %s20, %s21, K1, %s22\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s.Z 8(AX), %s21, K7, %s22\n", op, width, width) + fmt.Fprintf(&source, "\t%s.BCST.Z 12(AX), %s21, K2, %s22\n", op, width, width) + } + } + fmt.Fprintf(&source, "\t%s Z0, Z6, Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s 8(AX), Z6, Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s.BCST 12(AX), Z6, Z%d\n", op, zLast) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s Z20, Z21, K3, Z22\n", op) + fmt.Fprintf(&source, "\t%s.Z 8(AX), Z21, K4, Z22\n", op) + fmt.Fprintf(&source, "\t%s.BCST.Z 12(AX), Z21, K5, Z22\n", op) + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packeddotproductforms": {Name: "packeddotproductforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-dot-product-"+target.name+".ll", "packed-dot-product-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedDotProductRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPDPBUSD X0, X1", + "VPDPBUSDS X0, X1, (AX)", + "VPDPWSSD X0, Y1, X2", + "VPDPWSSDS Z0, Z1, Y2", + "VPDPBUSD X0, X1, K0, X2", + "VPDPBUSD X0, K1, X1, X2", + "VPDPBUSD.Z X0, X1, X2", + "VPDPBUSDS.SAE X0, X1, X2", + "VPDPWSSD.BCST X0, X1, X2", + "VPDPWSSDS.BCST 8(AX), Y1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedDotProductRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "VPDPBUSD Z8, Z0, Z1", + "VPDPBUSDS Z0, Z8, Z1", + "VPDPWSSD Z0, Z1, Z8", + "VPDPWSSDS X0, X1, K1, X2", + "VPDPBUSD.Z X0, X1, K1, X2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedDotProductRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedDotProductRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yvblendmpd forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_duplicate.go b/amd64_lower_duplicate.go new file mode 100644 index 00000000..d8fbf2fc --- /dev/null +++ b/amd64_lower_duplicate.go @@ -0,0 +1,167 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerDuplicateMove implements the complete Go x86 duplicate-move family. +// The legacy forms use yxm (X/m -> X), while all V-prefixed forms share +// _yvmovddup (X/Y/Z memory or matching register, with optional EVEX K mask). +func (c *amd64Ctx) lowerDuplicateMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := string(op) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + switch baseOp { + case "MOVDDUP", "VMOVDDUP", "MOVSHDUP", "VMOVSHDUP", "MOVSLDUP", "VMOVSLDUP": + // handled below + default: + return false, false, nil + } + zeroMasking := false + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + for _, suffix := range strings.Split(rawOp[dot+1:], ".") { + if suffix != "Z" || zeroMasking { + return true, false, fmt.Errorf("amd64 %s has unsupported suffix .%s: %q", rawOp[:dot], suffix, ins.Raw) + } + zeroMasking = true + } + rawOp = baseOp + } + + elemBits := 0 + duplicateOdd := false + switch rawOp { + case "MOVDDUP", "VMOVDDUP": + elemBits = 64 + case "MOVSHDUP", "VMOVSHDUP": + elemBits = 32 + duplicateOdd = true + case "MOVSLDUP", "VMOVSLDUP": + elemBits = 32 + default: + panic("duplicate-move opcode precheck drift") + } + + vectorForm := strings.HasPrefix(rawOp, "V") + wantArgs := 2 + if vectorForm { + wantArgs = 3 + } + if len(ins.Args) != 2 && (!vectorForm || len(ins.Args) != wantArgs) { + return true, false, fmt.Errorf("amd64 %s expects src, [K mask,] vector dst: %q", rawOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if !vectorForm && (masked || zeroMasking) { + return true, false, fmt.Errorf("amd64 %s legacy form does not accept EVEX masking: %q", rawOp, ins.Raw) + } + if zeroMasking && !masked { + return true, false, fmt.Errorf("amd64 %s .Z form requires a K mask: %q", rawOp, ins.Raw) + } + + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects vector destination: %q", rawOp, ins.Raw) + } + byteWidth := 0 + var loadOperand func(Operand) (string, error) + var loadDst func() (string, error) + var storeDst func(string) error + switch { + case isAMD64XReg(dstArg.Reg): + byteWidth = 16 + loadOperand = c.loadXVecOperand + loadDst = func() (string, error) { return c.loadX(dstArg.Reg) } + storeDst = func(value string) error { return c.storeX(dstArg.Reg, value) } + case vectorForm && isAMD64YReg(dstArg.Reg): + byteWidth = 32 + loadOperand = c.loadYVecOperand + loadDst = func() (string, error) { return c.loadY(dstArg.Reg) } + storeDst = func(value string) error { return c.storeY(dstArg.Reg, value) } + case vectorForm && isAMD64ZReg(dstArg.Reg): + byteWidth = 64 + loadOperand = c.loadZVecOperand + loadDst = func() (string, error) { return c.loadZ(dstArg.Reg) } + storeDst = func(value string) error { return c.storeZ(dstArg.Reg, value) } + default: + return true, false, fmt.Errorf("amd64 %s has mismatched or non-vector destination: %q", rawOp, ins.Raw) + } + + lanes := byteWidth * 8 / elemBits + var sourceLanes string + // MOVDDUP's 128-bit memory form reads one scalar double and duplicates it. + // Wider memory forms read a full Y/Z vector and duplicate the low double of + // each 128-bit lane. A register source always reads the full vector. + if elemBits == 64 && byteWidth == 16 && ins.Args[0].Kind != OpReg { + scalar, err := c.evalF64(ins.Args[0]) + if err != nil { + return true, false, err + } + bits := c.newTmp() + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", bits, scalar) + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> poison, i64 %%%s, i32 0\n", seed, bits) + sourceLanes = "%" + seed + } else { + sourceBytes, err := loadOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i%d>\n", cast, byteWidth, sourceBytes, lanes, elemBits) + sourceLanes = "%" + cast + } + + indices := make([]int, lanes) + for lane := range indices { + if duplicateOdd { + indices[lane] = lane | 1 + } else { + indices[lane] = lane &^ 1 + } + } + shuffle := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %s, <%d x i%d> poison, <%d x i32> %s\n", + shuffle, lanes, elemBits, sourceLanes, lanes, elemBits, lanes, llvmI32Mask(indices)) + result := "%" + shuffle + + if masked { + maskArg := ins.Args[1] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K register: %q", rawOp, ins.Raw) + } + if maskIndex, ok := amd64ParseKReg(maskArg.Reg); !ok || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K register: %q", rawOp, ins.Raw) + } + mask, err := c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + oldBytes, err := loadDst() + if err != nil { + return true, false, err + } + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i%d>\n", old, byteWidth, oldBytes, lanes, elemBits) + result = amd64ApplyIntegerLaneMask(c, lanes, elemBits, result, "%"+old, mask, zeroMasking) + } + + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, elemBits, result, byteWidth) + return true, false, storeDst("%" + out) +} + +func llvmI32Mask(indices []int) string { + var b strings.Builder + b.WriteByte('<') + for i, index := range indices { + if i != 0 { + b.WriteString(", ") + } + fmt.Fprintf(&b, "i32 %d", index) + } + b.WriteByte('>') + return b.String() +} diff --git a/amd64_lower_expand.go b/amd64_lower_expand.go new file mode 100644 index 00000000..a48b274a --- /dev/null +++ b/amd64_lower_expand.go @@ -0,0 +1,149 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedExpandSpec struct { + laneBits int +} + +// amd64PackedExpandSpecs is the complete Go 1.27 _yvexpandpd grammar for the +// packed floating-point and integer expand families. None of these optabs has +// an EVEX broadcast attribute. +var amd64PackedExpandSpecs = map[Op]amd64PackedExpandSpec{ + "VEXPANDPD": {laneBits: 64}, + "VEXPANDPS": {laneBits: 32}, + "VPEXPANDB": {laneBits: 8}, + "VPEXPANDW": {laneBits: 16}, + "VPEXPANDD": {laneBits: 32}, + "VPEXPANDQ": {laneBits: 64}, +} + +// lowerPackedExpand implements all six _yvexpandpd rows for every instruction +// above: X/Y/Z register or memory sources and the corresponding K1-K7 merge or +// .Z forms. Masked memory uses llvm.masked.expandload so disabled lanes do not +// spuriously read beyond the compact source array. +func (c *amd64Ctx) lowerPackedExpand(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, ok := amd64PackedExpandSpecs[Op(baseOp)] + if !ok { + return false, false, nil + } + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("%s %s accepts only Go 1.27's optional .Z suffix: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects source, [K1-K7,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s.Z requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be an X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth == 0 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go's EVEX register range: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[0] + if !isAMD64MemoryOperand(source) && !c.isGoEVEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source must be matching X/Y/Z register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if !masked { + sourceBytes, err := c.loadPackedCompareBytes(source, byteWidth) + if err != nil { + return true, false, err + } + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, sourceBytes) + } + + maskArg := ins.Args[1] + maskIndex, valid := amd64ParseKReg(maskArg.Reg) + if maskArg.Kind != OpReg || !valid || maskIndex == 0 { + return true, false, fmt.Errorf("%s %s masked form requires K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + mask, err := c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / spec.laneBits + vectorType := fmt.Sprintf("<%d x i%d>", lanes, spec.laneBits) + maskVector := amd64IntegerMaskVector(c, lanes, mask) + passthrough := "zeroinitializer" + if !zeroing { + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + passthrough = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + } + + result := "" + if isAMD64MemoryOperand(source) { + pointer, pointerType, intrinsicSuffix, err := c.packedVectorMemoryPointer(source) + if err != nil { + return true, false, err + } + expanded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.masked.expandload.v%di%d%s(%s %s, <%d x i1> %s, %s %s)\n", + expanded, vectorType, lanes, spec.laneBits, intrinsicSuffix, pointerType, pointer, lanes, maskVector, vectorType, passthrough) + result = "%" + expanded + } else { + sourceBytes, err := c.loadPackedCompareBytes(source, byteWidth) + if err != nil { + return true, false, err + } + sourceLanes := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, sourceBytes) + result = c.expandPackedRegisterLanes(lanes, spec.laneBits, sourceLanes, passthrough, mask, maskVector) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", out, vectorType, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +// expandPackedRegisterLanes is the register-source inverse of vector +// compression. For destination lane i, the compact source index is the number +// of set mask bits below i. Building each lane from the original source before +// the final store keeps source/destination aliasing safe. +func (c *amd64Ctx) expandPackedRegisterLanes(lanes, laneBits int, source, passthrough, mask, maskVector string) string { + vectorType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + result := passthrough + for lane := 0; lane < lanes; lane++ { + active := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i1> %s, i32 %d\n", active, lanes, maskVector, lane) + sourceIndex := "0" + if lane != 0 { + below := c.newTmp() + count := c.newTmp() + index := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %d\n", below, mask, (uint64(1)< +#include +extern void packedexpandsemantics(uint8_t *, const uint8_t *, const uint8_t *, uint64_t); +static int check(const uint8_t *got, const uint8_t *source, const uint8_t *old, + int lane_bytes, uint64_t mask, int zeroing) { + int lanes = 64 / lane_bytes, packed = 0; + for (int lane = 0; lane < lanes; lane++) { + const uint8_t *want = zeroing ? (const uint8_t[8]){0} : old + lane*lane_bytes; + if ((mask >> lane) & 1) want = source + packed++*lane_bytes; + if (memcmp(got + lane*lane_bytes, want, lane_bytes)) return 10 + lane; + } + return 0; +} +int main(void) { + uint8_t source[64], old[64], out[513]; + const uint64_t mask = UINT64_C(0xa55aa55aa55aa55a); + for (int i = 0; i < 64; i++) { source[i] = (uint8_t)(i*37 + 9); old[i] = (uint8_t)(0xe0 - i); } + memset(out, 0xcc, sizeof(out)); + packedexpandsemantics(out, source, old, mask); + int r; + if ((r = check(out+0, source, old, 1, mask, 0))) return 100+r; + if ((r = check(out+64, source, old, 2, mask, 1))) return 200+r; + if ((r = check(out+128, source, old, 4, mask, 0))) return 300+r; + if ((r = check(out+192, source, old, 8, mask, 1))) return 400+r; + if ((r = check(out+256, source, old, 4, mask, 0))) return 500+r; + if ((r = check(out+320, source, old, 8, mask, 1))) return 600+r; + if ((r = check(out+384, source, source, 4, mask, 0))) return 700+r; + if (memcmp(out+448, old, 64)) return 800; + if (out[512] != 1) return 801; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_expand_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_explicit_mask_move.go b/amd64_lower_explicit_mask_move.go new file mode 100644 index 00000000..e8628ef5 --- /dev/null +++ b/amd64_lower_explicit_mask_move.go @@ -0,0 +1,89 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64ExplicitMaskMoveSpec struct { + laneBits int +} + +// amd64ExplicitMaskMoveSpecs is Go 1.27's complete _yvmaskmovpd grammar. +// Floating and integer spellings have identical bitwise lane-mask semantics; +// only the lane width differs. +var amd64ExplicitMaskMoveSpecs = map[Op]amd64ExplicitMaskMoveSpec{ + "VMASKMOVPS": {laneBits: 32}, + "VMASKMOVPD": {laneBits: 64}, + "VPMASKMOVD": {laneBits: 32}, + "VPMASKMOVQ": {laneBits: 64}, +} + +func (c *amd64Ctx) lowerExplicitMaskMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64ExplicitMaskMoveSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed forms in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects memory/data, mask, destination/memory: %q", c.goarch, baseOp, ins.Raw) + } + load := isAMD64MemoryOperand(ins.Args[0]) + store := isAMD64MemoryOperand(ins.Args[2]) + if load == store { + return true, false, fmt.Errorf("%s %s requires memory only as its first (load) or last (store) operand: %q", c.goarch, baseOp, ins.Raw) + } + maskArg := ins.Args[1] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s mask must be an X or Y register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(maskArg.Reg) + if byteWidth != 16 && byteWidth != 32 || !amd64VEXVectorRegister(maskArg, byteWidth) { + return true, false, fmt.Errorf("%s %s mask must be an in-range X or Y register: %q", c.goarch, baseOp, ins.Raw) + } + registerArg := ins.Args[2] + memoryArg := ins.Args[0] + if store { + registerArg = ins.Args[0] + memoryArg = ins.Args[2] + } + if !amd64VEXVectorRegister(registerArg, byteWidth) { + return true, false, fmt.Errorf("%s %s data register must match the mask width: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := byteWidth * 8 / spec.laneBits + mask, err := c.loadPackedCompareLanes(maskArg, byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + predicate := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt <%d x i%d> %s, zeroinitializer\n", predicate, lanes, spec.laneBits, mask) + pointer, pointerType, intrinsicSuffix, err := c.packedVectorMemoryPointer(memoryArg) + if err != nil { + return true, false, err + } + intrinsicType := fmt.Sprintf("v%di%d", lanes, spec.laneBits) + vectorType := fmt.Sprintf("<%d x i%d>", lanes, spec.laneBits) + if load { + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.masked.load.%s%s(%s align 1 %s, <%d x i1> %%%s, %s zeroinitializer)\n", + loaded, vectorType, intrinsicType, intrinsicSuffix, pointerType, pointer, lanes, predicate, vectorType) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <%d x i8>\n", bytesValue, vectorType, loaded, byteWidth) + return true, false, c.storeVectorBytes(registerArg.Reg, byteWidth, "%"+bytesValue) + } + data, err := c.loadPackedCompareLanes(registerArg, byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void @llvm.masked.store.%s%s(%s %s, %s align 1 %s, <%d x i1> %%%s)\n", + intrinsicType, intrinsicSuffix, vectorType, data, pointerType, pointer, lanes, predicate) + return true, false, nil +} diff --git a/amd64_lower_explicit_mask_move_test.go b/amd64_lower_explicit_mask_move_test.go new file mode 100644 index 00000000..6258fc2e --- /dev/null +++ b/amd64_lower_explicit_mask_move_test.go @@ -0,0 +1,209 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64ExplicitMaskMoveGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64ExplicitMaskMoveSpec{ + "VMASKMOVPS": {laneBits: 32}, + "VMASKMOVPD": {laneBits: 64}, + "VPMASKMOVD": {laneBits: 32}, + "VPMASKMOVQ": {laneBits: 64}, + } + if len(amd64ExplicitMaskMoveSpecs) != len(expected) { + t.Fatalf("explicit-mask-move grammar has %d entries, want %d", len(amd64ExplicitMaskMoveSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64ExplicitMaskMoveSpecs[op]; !ok { + t.Errorf("explicit-mask-move grammar omitted %s", op) + } else if got != want { + t.Errorf("explicit-mask-move grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86ExplicitMaskMoveCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT explicitmaskmoveforms(SB),$0-0\n") + for _, op := range []string{"VMASKMOVPS", "VMASKMOVPD", "VPMASKMOVD", "VPMASKMOVQ"} { + for _, width := range []string{"X", "Y"} { + last := 15 + fmt.Fprintf(&source, "\t%s 8(AX), %s1, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s %s%d, %s1, 16(AX)\n", op, width, last, width) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"explicitmaskmoveforms": {Name: "explicitmaskmoveforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"@llvm.masked.load.v4i32", "@llvm.masked.store.v8i32", "@llvm.masked.load.v2i64", "@llvm.masked.store.v4i64"} { + if !strings.Contains(ir, want) { + t.Errorf("IR omitted fault-suppressing intrinsic %s", want) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "explicit-mask-move-"+target.name+".ll", "explicit-mask-move-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86ExplicitMaskMoveRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VPMASKMOVD (AX), X0"}, + {goarch: "amd64", instruction: "VPMASKMOVD X0, X1, X2"}, + {goarch: "amd64", instruction: "VPMASKMOVD (AX), X0, (BX)"}, + {goarch: "amd64", instruction: "VPMASKMOVD X0, (AX), X1"}, + {goarch: "amd64", instruction: "VPMASKMOVD (AX), X0, Y1"}, + {goarch: "amd64", instruction: "VPMASKMOVD (AX), Z0, Z1"}, + {goarch: "amd64", instruction: "VPMASKMOVD.Z (AX), X0, X1"}, + {goarch: "amd64", instruction: "VMASKMOVPD (AX), X0, AX"}, + {goarch: "386", instruction: "VPMASKMOVQ (AX), X16, X0"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's explicit-mask-move table", test.instruction) + } + }) + } +} + +func TestAMD64ExplicitMaskMoveRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT explicitmaskmovesemantics(SB),$0-40 + MOVQ out+0(FP), AX + MOVQ loadmem+8(FP), BX + MOVQ data+16(FP), CX + MOVQ mask+24(FP), DX + MOVQ storemem+32(FP), R8 + VMOVDQU 0(CX), Y0 + VMOVDQU 0(DX), Y1 + STC + VPMASKMOVD 0(BX), Y1, Y2 + VMOVDQU Y2, 0(AX) + VPMASKMOVD Y0, Y1, 0(R8) + VPMASKMOVQ 0(BX), Y1, Y3 + VMOVDQU Y3, 32(AX) + VPMASKMOVQ Y0, Y1, 32(R8) + VMASKMOVPS 0(BX), Y1, Y4 + VMOVDQU Y4, 64(AX) + VMASKMOVPS Y0, Y1, 64(R8) + VMASKMOVPD 0(BX), Y1, Y5 + VMOVDQU Y5, 96(AX) + VMASKMOVPD Y0, Y1, 96(R8) + SETCS 128(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"explicitmaskmovesemantics": { + Name: "explicitmaskmovesemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void explicitmaskmovesemantics(uint8_t *, const uint8_t *, const uint8_t *, const uint8_t *, uint8_t *); +static uint32_t u32(const uint8_t *p) { uint32_t v; memcpy(&v,p,4); return v; } +static uint64_t u64(const uint8_t *p) { uint64_t v; memcpy(&v,p,8); return v; } +int main(void) { + uint32_t load32[8], data32[8], mask32[8]; + uint8_t out[129]={0}, store[128]; + for (int i=0;i<8;i++) { + load32[i]=UINT32_C(0x10203040)+(uint32_t)i; + data32[i]=UINT32_C(0xa0b0c000)+(uint32_t)i; + mask32[i]=(i==1||i==2||i==5)?UINT32_C(0x80000000):UINT32_C(0x7fffffff); + } + memset(store,0x5a,sizeof(store)); + explicitmaskmovesemantics(out,(uint8_t*)load32,(uint8_t*)data32,(uint8_t*)mask32,store); + for (int i=0;i<8;i++) { + int enabled=(int32_t)mask32[i]<0; + if (u32(out+4*i)!=(enabled?load32[i]:0)) return 10; + if (u32(store+4*i)!=(enabled?data32[i]:UINT32_C(0x5a5a5a5a))) return 11; + if (u32(out+64+4*i)!=(enabled?load32[i]:0)) return 12; + if (u32(store+64+4*i)!=(enabled?data32[i]:UINT32_C(0x5a5a5a5a))) return 13; + } + for (int i=0;i<4;i++) { + int enabled=(int64_t)u64((uint8_t*)mask32+8*i)<0; + if (u64(out+32+8*i)!=(enabled?u64((uint8_t*)load32+8*i):0)) return 20; + if (u64(store+32+8*i)!=(enabled?u64((uint8_t*)data32+8*i):UINT64_C(0x5a5a5a5a5a5a5a5a))) return 21; + if (u64(out+96+8*i)!=(enabled?u64((uint8_t*)load32+8*i):0)) return 22; + if (u64(store+96+8*i)!=(enabled?u64((uint8_t*)data32+8*i):UINT64_C(0x5a5a5a5a5a5a5a5a))) return 23; + } + if (out[128]!=1) return 30; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "explicit_mask_move_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_extract.go b/amd64_lower_extract.go new file mode 100644 index 00000000..1f4795d1 --- /dev/null +++ b/amd64_lower_extract.go @@ -0,0 +1,171 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64VectorExtractProperties struct { + outputBytes int + laneBits int + legacy bool + allowY bool + allowZ bool +} + +// lowerVectorLaneExtract implements all Go 1.27 forms in _yvextractf128, +// _yvextractf32x4, and _yvextractf32x8 for their F/I lane-extract mnemonics. +func (c *amd64Ctx) lowerVectorLaneExtract(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + properties, ok := amd64VectorExtractOpProperties(baseOp) + if !ok { + return false, false, nil + } + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("amd64 %s accepts only the .Z suffix enabled by its Go 1.27 optab: %q", baseOp, ins.Raw) + } + if properties.legacy && suffix != "" { + return true, false, fmt.Errorf("amd64 %s VEX form has no suffix: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 %s expects $imm, source, [K mask,] destination: %q", baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects an immediate and vector-register source: %q", baseOp, ins.Raw) + } + inputBytes := amd64VectorByteWidth(ins.Args[1].Reg) + if (inputBytes == 32 && !properties.allowY) || (inputBytes == 64 && !properties.allowZ) || (inputBytes != 32 && inputBytes != 64) { + return true, false, fmt.Errorf("amd64 %s source has a width absent from its Go 1.27 optab: %q", baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind == OpReg { + if !amd64VectorRegisterHasWidth(dstArg, properties.outputBytes) { + return true, false, fmt.Errorf("amd64 %s register destination must be %d bytes: %q", baseOp, properties.outputBytes, ins.Raw) + } + } else if !isAMD64MemoryOperand(dstArg) { + return true, false, fmt.Errorf("amd64 %s destination must be a vector register or memory: %q", baseOp, ins.Raw) + } + + masked := len(ins.Args) == 4 + if properties.legacy && masked { + return true, false, fmt.Errorf("amd64 %s VEX form has no mask: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s zeroing requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + if zeroing && dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s zeroing is invalid for a memory destination: %q", baseOp, ins.Raw) + } + var mask string + if masked { + maskArg := ins.Args[2] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, ok := amd64ParseKReg(maskArg.Reg) + if !ok || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + source, err := c.loadPackedCompareBytes(ins.Args[1], inputBytes) + if err != nil { + return true, false, err + } + chunkCount := inputBytes / properties.outputBytes + chunk := int(uint64(ins.Args[0].Imm) & uint64(chunkCount-1)) + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i8> %s, <%d x i8> poison, <%d x i32> %s\n", extracted, inputBytes, source, inputBytes, properties.outputBytes, llvmI32RangeMask(chunk*properties.outputBytes, properties.outputBytes)) + result := "%" + extracted + if masked { + lanes := properties.outputBytes * 8 / properties.laneBits + computed := c.bitcastVectorBytesToIntegerLanes(properties.outputBytes, lanes, properties.laneBits, result) + oldBytes, err := c.loadPackedCompareBytes(dstArg, properties.outputBytes) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(properties.outputBytes, lanes, properties.laneBits, oldBytes) + computed = amd64ApplyIntegerLaneMask(c, lanes, properties.laneBits, computed, old, mask, zeroing) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, properties.laneBits, computed, properties.outputBytes) + result = "%" + out + } + return true, false, c.storeVectorBytesOperand(dstArg, properties.outputBytes, result) +} + +func amd64VectorExtractOpProperties(op string) (amd64VectorExtractProperties, bool) { + switch op { + case "VEXTRACTF128", "VEXTRACTI128": + return amd64VectorExtractProperties{outputBytes: 16, laneBits: 8, legacy: true, allowY: true}, true + case "VEXTRACTF32X4", "VEXTRACTI32X4": + return amd64VectorExtractProperties{outputBytes: 16, laneBits: 32, allowY: true, allowZ: true}, true + case "VEXTRACTF64X2", "VEXTRACTI64X2": + return amd64VectorExtractProperties{outputBytes: 16, laneBits: 64, allowY: true, allowZ: true}, true + case "VEXTRACTF32X8", "VEXTRACTI32X8": + return amd64VectorExtractProperties{outputBytes: 32, laneBits: 32, allowZ: true}, true + case "VEXTRACTF64X4", "VEXTRACTI64X4": + return amd64VectorExtractProperties{outputBytes: 32, laneBits: 64, allowZ: true}, true + default: + return amd64VectorExtractProperties{}, false + } +} + +func (c *amd64Ctx) storeVectorBytesOperand(dst Operand, byteWidth int, value string) error { + return c.storeVectorBytesOperandWithMetadata(dst, byteWidth, value, "") +} + +func (c *amd64Ctx) storeVectorBytesOperandWithMetadata(dst Operand, byteWidth int, value, metadata string) error { + if dst.Kind == OpReg { + if metadata != "" { + return fmt.Errorf("vector register destination cannot carry store metadata: %s", dst.String()) + } + if !amd64VectorRegisterHasWidth(dst, byteWidth) { + return fmt.Errorf("expected %d-byte vector register, got %s", byteWidth, dst.String()) + } + return c.storeVectorBytes(dst.Reg, byteWidth, value) + } + switch dst.Kind { + case OpMem: + addr, err := c.addrFromMem(dst.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store <%d x i8> %s, ptr %s, align 1%s\n", byteWidth, value, c.ptrFromAddrI64(addr), metadata) + return nil + case OpSym: + p, err := c.ptrFromSB(dst.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store <%d x i8> %s, ptr %s, align 1%s\n", byteWidth, value, p, metadata) + return nil + case OpFP: + chunks := byteWidth / 8 + words := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i64>\n", words, byteWidth, value, chunks) + for i := 0; i < chunks; i++ { + word := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %%%s, i32 %d\n", word, chunks, words, i) + if err := c.storeFPResultWithMetadata(dst.FPOffset+int64(i*8), I64, "%"+word, metadata); err != nil { + return err + } + } + return nil + default: + return fmt.Errorf("expected vector register or memory destination, got %s", dst.String()) + } +} diff --git a/amd64_lower_extract_scalar.go b/amd64_lower_extract_scalar.go new file mode 100644 index 00000000..5e5901dc --- /dev/null +++ b/amd64_lower_extract_scalar.go @@ -0,0 +1,146 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedScalarExtractSpec struct { + bits int + vector bool + maxImmediate int64 + allowMMX bool +} + +// amd64PackedScalarExtractSpecs models the complete Go 1.27 yextractps, +// yextr/yextrw, and AVX _yvextractps family. Immediate domains, result widths, +// encoding generation, and the legacy encoded-MMX quirk are data rather than +// repeated opcode branches. +var amd64PackedScalarExtractSpecs = map[Op]amd64PackedScalarExtractSpec{ + "EXTRACTPS": {bits: 32, maxImmediate: 3}, + "VEXTRACTPS": {bits: 32, vector: true, maxImmediate: 255}, + "PEXTRB": {bits: 8, maxImmediate: 255, allowMMX: true}, + "PEXTRW": {bits: 16, maxImmediate: 255}, + "PEXTRD": {bits: 32, maxImmediate: 255, allowMMX: true}, + "PEXTRQ": {bits: 64, maxImmediate: 255, allowMMX: true}, + "VPEXTRB": {bits: 8, vector: true, maxImmediate: 255}, + "VPEXTRW": {bits: 16, vector: true, maxImmediate: 255}, + "VPEXTRD": {bits: 32, vector: true, maxImmediate: 255}, + "VPEXTRQ": {bits: 64, vector: true, maxImmediate: 255}, +} + +// lowerPackedScalarExtract implements every Go 1.27 operand form from the +// legacy yextractps/yextr/yextrw tables and the AVX +// _yvextractps/_yvpextrw tables. +func (c *amd64Ctx) lowerPackedScalarExtract(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + + spec, recognized := amd64PackedScalarExtractSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s has no instruction suffixes in Go 1.27's optab: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects $imm8, X source, GP-or-memory destination: %q", baseOp, ins.Raw) + } + if c.goarch == "386" && spec.bits == 64 && !spec.vector { + return true, false, fmt.Errorf("386 %s is absent from Go 1.27's 32-bit encoding tables: %q", baseOp, ins.Raw) + } + + sourceIndex, sourceOK := amd64ParseXReg(ins.Args[1].Reg) + maxSourceIndex := 15 + if spec.vector { + maxSourceIndex = 31 + } + if c.goarch == "386" { + maxSourceIndex = 7 + } + if !sourceOK || sourceIndex > maxSourceIndex { + return true, false, fmt.Errorf("amd64 %s source is outside its Go 1.27 X-register class: %q", baseOp, ins.Raw) + } + + // The VEX entries cover both Yi8 and Yu8, while the EVEX entries (which + // are required for X16-X31) cover only Yu8. Legacy entries also use Yu8. + minimumImmediate := int64(0) + if spec.vector && sourceIndex <= 15 { + minimumImmediate = -128 + } + if immediate := ins.Args[0].Imm; immediate < minimumImmediate || immediate > spec.maxImmediate { + return true, false, fmt.Errorf("amd64 %s immediate is outside its Go 1.27 encoding table: %q", baseOp, ins.Raw) + } + + destination := ins.Args[2] + destinationReg := Reg("") + if destination.Kind == OpReg { + if isX86YrlRegisterForArch(destination.Reg, c.goarch) { + destinationReg = destination.Reg + } else if mmxIndex, mmx := amd64ParseMReg(destination.Reg); mmx && spec.allowMMX { + // The legacy B/D/Q yextr table uses Ymm. Go therefore accepts M0-M7 + // here and encodes their ModRM numbers as AX/CX/DX/BX/SP/BP/SI/DI. + destinationReg = amd64MMXEncodingGP(mmxIndex) + } else { + return true, false, fmt.Errorf("amd64 %s register destination is outside its Go 1.27 table: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("amd64 %s destination must be a GP register or memory: %q", baseOp, ins.Raw) + } + if destination.Kind == OpMem && !x86MemoryRegistersValidForArch(destination.Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s memory destination uses an out-of-range address register: %q", c.goarch, baseOp, ins.Raw) + } + + source, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + lanes := 128 / spec.bits + laneVector := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x i%d>\n", laneVector, source, lanes, spec.bits) + extracted := c.newTmp() + lane := int(uint64(ins.Args[0].Imm) & uint64(lanes-1)) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %%%s, i32 %d\n", extracted, lanes, spec.bits, laneVector, lane) + value := "%" + extracted + + if destination.Kind == OpReg { + if spec.bits < 32 { + widened := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i%d %s to i32\n", widened, spec.bits, value) + return true, false, c.storeRegSized(destinationReg, I32, "%"+widened) + } + return true, false, c.storeRegSized(destinationReg, amd64IntegerTypeForBits(spec.bits), value) + } + return true, false, c.storePackedScalarExtractMemory(destination, amd64IntegerTypeForBits(spec.bits), value) +} + +func amd64MMXEncodingGP(index int) Reg { + return [...]Reg{AX, CX, DX, BX, SP, BP, SI, DI}[index] +} + +func (c *amd64Ctx) storePackedScalarExtractMemory(destination Operand, typ LLVMType, value string) error { + switch destination.Kind { + case OpMem: + pointer, pointerType, err := c.ptrFromMem(destination.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, %s %s, align 1\n", typ, value, pointerType, pointer) + return nil + case OpSym: + pointer, err := c.ptrFromSB(destination.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, ptr %s, align 1\n", typ, value, pointer) + return nil + case OpFP: + return c.storeFPResult(destination.FPOffset, typ, value) + default: + return fmt.Errorf("expected packed scalar extract memory destination, got %s", destination.String()) + } +} diff --git a/amd64_lower_far_pointer.go b/amd64_lower_far_pointer.go new file mode 100644 index 00000000..95b71a52 --- /dev/null +++ b/amd64_lower_far_pointer.go @@ -0,0 +1,90 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64FarPointerSpec struct { + segment Reg + bits int +} + +// amd64FarPointerSpecs is the complete Go 1.27 LFS/LGS/LSS grammar. Segment +// selection and offset width are data; memory shape, destination class, and +// architecture availability are parsed once for all nine opcodes. +var amd64FarPointerSpecs = map[Op]amd64FarPointerSpec{ + "LFSW": {segment: FS, bits: 16}, + "LFSL": {segment: FS, bits: 32}, + "LFSQ": {segment: FS, bits: 64}, + "LGSW": {segment: GS, bits: 16}, + "LGSL": {segment: GS, bits: 32}, + "LGSQ": {segment: GS, bits: 64}, + "LSSW": {segment: SS, bits: 16}, + "LSSL": {segment: SS, bits: 32}, + "LSSQ": {segment: SS, bits: 64}, +} + +type amd64FarPointerForm struct { + memory Operand + destination Reg +} + +func (c *amd64Ctx) lowerFarPointer(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64FarPointerSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && spec.bits == 64 { + return true, false, fmt.Errorf("386 %s is absent from Go 1.27's 32-bit encoding table: %q", baseOp, ins.Raw) + } + form, err := c.parseFarPointerForm(baseOp, ins) + if err != nil { + return true, false, err + } + return c.emitFarPointer(spec, form) +} + +func (c *amd64Ctx) parseFarPointerForm(op string, ins Instr) (amd64FarPointerForm, error) { + var form amd64FarPointerForm + if len(ins.Args) != 2 { + return form, fmt.Errorf("%s %s expects far-pointer memory and GP destination: %q", c.goarch, op, ins.Raw) + } + memory, destination := ins.Args[0], ins.Args[1] + if !isAMD64MemoryOperand(memory) { + return form, fmt.Errorf("%s %s source must be Go 1.27 Ym memory: %q", c.goarch, op, ins.Raw) + } + if memory.Kind == OpMem && !x86MemoryRegistersValidForArch(memory.Mem, c.goarch) { + return form, fmt.Errorf("%s %s source address uses an out-of-range register: %q", c.goarch, op, ins.Raw) + } + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return form, fmt.Errorf("%s %s destination must be a Go 1.27 Yrl register: %q", c.goarch, op, ins.Raw) + } + return amd64FarPointerForm{memory: memory, destination: destination.Reg}, nil +} + +func (c *amd64Ctx) emitFarPointer(spec amd64FarPointerSpec, form amd64FarPointerForm) (bool, bool, error) { + pointer, pointerType, err := c.x86DescriptorMemoryPointer(form.memory) + if err != nil { + return true, false, err + } + typ := amd64IntegerTypeForBits(spec.bits) + memoryBytes := spec.bits/8 + 2 + width := map[int]string{16: "w", 32: "l", 64: "q"}[spec.bits] + result := c.newTmp() + assembly := "l" + strings.ToLower(string(spec.segment)) + width + " $1, $0" + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(%s elementtype([%d x i8]) %s)\n", + result, typ, assembly, "=r,*m,~{memory},~{dirflag},~{fpsr},~{flags}", pointerType, memoryBytes, pointer) + if err := c.storeRegSized(form.destination, typ, "%"+result); err != nil { + return true, false, err + } + return true, false, nil +} diff --git a/amd64_lower_far_pointer_test.go b/amd64_lower_far_pointer_test.go new file mode 100644 index 00000000..45e8b3f6 --- /dev/null +++ b/amd64_lower_far_pointer_test.go @@ -0,0 +1,106 @@ +package plan9asm + +import ( + "reflect" + "sort" + "strings" + "testing" +) + +func TestAMD64FarPointerGrammarIsComplete(t *testing.T) { + got := make([]string, 0, len(amd64FarPointerSpecs)) + for op := range amd64FarPointerSpecs { + got = append(got, string(op)) + } + sort.Strings(got) + want := []string{"LFSL", "LFSQ", "LFSW", "LGSL", "LGSQ", "LGSW", "LSSL", "LSSQ", "LSSW"} + if !reflect.DeepEqual(got, want) { + t.Fatalf("far-pointer grammar opcodes = %v, want %v", got, want) + } +} + +func TestTranslateX86FarPointerCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + destination := "DI" + base := "BX" + if target.goarch == "amd64" { + destination = "R12" + base = "R13" + } + source := "TEXT farpointerforms(SB),$0-0\n" + for _, family := range []string{"LFS", "LGS", "LSS"} { + source += "\t" + family + "W 0(BX), AX\n" + source += "\t" + family + "W 2(" + base + "), " + destination + "\n" + source += "\t" + family + "L 4(BX), DX\n" + if target.goarch == "amd64" { + source += "\t" + family + "Q 8(" + base + "), " + destination + "\n" + } else { + source += "\t" + family + "L 8(BX), SP\n" + } + } + source += "\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"farpointerforms": {Name: "farpointerforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "far-pointer-"+target.name+".ll", "far-pointer-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86FarPointerRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "LFSW AX, DX"}, + {goarch: "amd64", instruction: "LFSL (BX), (CX)"}, + {goarch: "amd64", instruction: "LGSQ (BX), X0"}, + {goarch: "amd64", instruction: "LSSW.Z (BX), DX"}, + {goarch: "386", instruction: "LFSQ (BX), AX"}, + {goarch: "386", instruction: "LGSL (R11), AX"}, + {goarch: "386", instruction: "LSSL (BX), R11"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's far-pointer tables", test.instruction) + } + }) + } +} diff --git a/amd64_lower_far_return.go b/amd64_lower_far_return.go new file mode 100644 index 00000000..1979b09e --- /dev/null +++ b/amd64_lower_far_return.go @@ -0,0 +1,105 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64FarReturnKind uint8 + +const ( + amd64InterruptReturn amd64FarReturnKind = iota + amd64FarReturn +) + +type amd64FarReturnSpec struct { + kind amd64FarReturnKind + bits int + allowImmediate bool +} + +// amd64FarReturnSpecs is the complete Go 1.27 interrupt/far-return grammar. +// Every RETF width accepts both the operand-free CB encoding and Go's Yi32 +// immediate row, whose value is truncated to the architectural imm16. Q-width +// rows are absent from the 386 encoder even though W/L rows are shared. +var amd64FarReturnSpecs = map[Op]amd64FarReturnSpec{ + "IRETW": {kind: amd64InterruptReturn, bits: 16}, + "IRETL": {kind: amd64InterruptReturn, bits: 32}, + "IRETQ": {kind: amd64InterruptReturn, bits: 64}, + "RETFW": {kind: amd64FarReturn, bits: 16, allowImmediate: true}, + "RETFL": {kind: amd64FarReturn, bits: 32, allowImmediate: true}, + "RETFQ": {kind: amd64FarReturn, bits: 64, allowImmediate: true}, +} + +type amd64FarReturnForm struct { + hasImmediate bool + immediate uint16 +} + +func (c *amd64Ctx) lowerFarReturn(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64FarReturnSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && spec.bits == 64 { + return true, false, fmt.Errorf("386 %s is absent from Go 1.27's 32-bit encoding table: %q", baseOp, ins.Raw) + } + form, err := c.parseFarReturnForm(baseOp, spec, ins) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q()\n", + spec.encoding(form), "~{memory},~{dirflag},~{fpsr},~{flags}") + c.b.WriteString(" unreachable\n") + return true, true, nil +} + +func (c *amd64Ctx) parseFarReturnForm(op string, spec amd64FarReturnSpec, ins Instr) (amd64FarReturnForm, error) { + var form amd64FarReturnForm + if len(ins.Args) == 0 { + return form, nil + } + if !spec.allowImmediate || len(ins.Args) != 1 || ins.Args[0].Kind != OpImm { + return form, fmt.Errorf("%s %s expects no operands or one Go 1.27 Yi32 immediate: %q", c.goarch, op, ins.Raw) + } + value := ins.Args[0].Imm + if c.goarch != "386" && (value < -2147483648 || value > 4294967295) { + return form, fmt.Errorf("amd64 %s immediate is outside Go 1.27's Yi32 class: %q", op, ins.Raw) + } + form.hasImmediate = true + form.immediate = uint16(value) + return form, nil +} + +func (spec amd64FarReturnSpec) encoding(form amd64FarReturnForm) string { + bytes := make([]byte, 0, 4) + switch spec.bits { + case 16: + bytes = append(bytes, 0x66) + case 32: + case 64: + bytes = append(bytes, 0x48) + default: + panic("unknown amd64 far-return width") + } + if spec.kind == amd64InterruptReturn { + bytes = append(bytes, 0xcf) + } else if form.hasImmediate { + bytes = append(bytes, 0xca, byte(form.immediate), byte(form.immediate>>8)) + } else { + bytes = append(bytes, 0xcb) + } + parts := make([]string, len(bytes)) + for index, value := range bytes { + parts[index] = fmt.Sprintf("0x%02x", value) + } + return ".byte " + strings.Join(parts, ", ") +} diff --git a/amd64_lower_far_return_test.go b/amd64_lower_far_return_test.go new file mode 100644 index 00000000..55cd44a0 --- /dev/null +++ b/amd64_lower_far_return_test.go @@ -0,0 +1,177 @@ +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +func TestAMD64FarReturnGrammarIsComplete(t *testing.T) { + want := map[Op]amd64FarReturnSpec{ + "IRETW": {kind: amd64InterruptReturn, bits: 16}, + "IRETL": {kind: amd64InterruptReturn, bits: 32}, + "IRETQ": {kind: amd64InterruptReturn, bits: 64}, + "RETFW": {kind: amd64FarReturn, bits: 16, allowImmediate: true}, + "RETFL": {kind: amd64FarReturn, bits: 32, allowImmediate: true}, + "RETFQ": {kind: amd64FarReturn, bits: 64, allowImmediate: true}, + } + if !reflect.DeepEqual(amd64FarReturnSpecs, want) { + t.Fatalf("far-return grammar = %+v, want %+v", amd64FarReturnSpecs, want) + } +} + +func TestAMD64FarReturnSplitsFollowingInstructions(t *testing.T) { + source := "TEXT splitfarreturn(SB),$0-0\n\tIRETL\n\tMOVL $1, AX\n\tRET\n" + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"splitfarreturn": {Name: "splitfarreturn", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "anon_1:") || !strings.Contains(ir, "zext i32 1 to i64") { + t.Fatalf("instruction after IRETL was not retained in its own block:\n%s", ir) + } +} + +func TestTranslateX86FarReturnCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + forms := []struct { + op string + arg string + }{ + {op: "IRETW"}, + {op: "IRETL"}, + {op: "RETFW"}, + {op: "RETFW", arg: "$4"}, + {op: "RETFL"}, + {op: "RETFL", arg: "$4294967295"}, + } + if target.goarch == "386" { + forms = append(forms, struct { + op string + arg string + }{op: "RETFL", arg: "$4294967296"}) + } else { + forms = append(forms, + struct { + op string + arg string + }{op: "IRETQ"}, + struct { + op string + arg string + }{op: "RETFQ"}, + struct { + op string + arg string + }{op: "RETFQ", arg: "$4294967295"}, + ) + } + var source strings.Builder + sigs := make(map[string]FuncSig, len(forms)) + for index, form := range forms { + name := fmt.Sprintf("farreturnform%d", index) + fmt.Fprintf(&source, "TEXT %s(SB),$0-0\n\t%s", name, form.op) + if form.arg != "" { + fmt.Fprintf(&source, " %s", form.arg) + } + source.WriteByte('\n') + sigs[name] = FuncSig{Name: name, Ret: Void} + } + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: target.goarch, TargetTriple: target.triple, Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `.byte 0x66, 0xcf`, + `.byte 0xcf`, + `.byte 0x66, 0xcb`, + `.byte 0x66, 0xca, 0x04, 0x00`, + `.byte 0xcb`, + `.byte 0xca, 0xff, 0xff`, + } { + if !strings.Contains(ir, want) { + t.Errorf("IR is missing %s:\n%s", want, ir) + } + } + if target.goarch == "386" { + if !strings.Contains(ir, `.byte 0xca, 0x00, 0x00`) { + t.Errorf("386 IR is missing truncated Yi32 compatibility encoding:\n%s", ir) + } + } else { + for _, want := range []string{`.byte 0x48, 0xcf`, `.byte 0x48, 0xcb`, `.byte 0x48, 0xca, 0xff, 0xff`} { + if !strings.Contains(ir, want) { + t.Errorf("amd64 IR is missing %s:\n%s", want, ir) + } + } + } + if got := strings.Count(ir, "unreachable"); got != len(forms) { + t.Errorf("unreachable count = %d, want %d", got, len(forms)) + } + compileLLVMToObject(t, llc, target.triple, "far-return-"+target.name+".ll", "far-return-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86FarReturnRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "IRETW AX"}, + {goarch: "amd64", instruction: "IRETL.P"}, + {goarch: "amd64", instruction: "IRETQ $4"}, + {goarch: "amd64", instruction: "RETFW AX"}, + {goarch: "amd64", instruction: "RETFL $-2147483649"}, + {goarch: "amd64", instruction: "RETFQ $4294967296"}, + {goarch: "amd64", instruction: "RETFL $1, $2"}, + {goarch: "386", instruction: "IRETQ"}, + {goarch: "386", instruction: "RETFQ"}, + {goarch: "386", instruction: "RETFQ $4"}, + } { + t.Run(test.goarch+"_"+strings.ReplaceAll(test.instruction, " ", "_"), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's far-return tables", test.instruction) + } + }) + } +} diff --git a/amd64_lower_fixed_system.go b/amd64_lower_fixed_system.go new file mode 100644 index 00000000..ef18604b --- /dev/null +++ b/amd64_lower_fixed_system.go @@ -0,0 +1,65 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64FixedSystemEffect uint8 + +const ( + amd64FixedSystemContinue amd64FixedSystemEffect = iota + amd64FixedSystemTrap + amd64FixedSystemControlTransfer +) + +type amd64FixedSystemSpec struct { + encoding string + effect amd64FixedSystemEffect +} + +// amd64FixedSystemSpecs is the complete Go 1.27 operand-free system/state +// family that has no modeled GP-register data flow. Exact bytes keep Go's +// accepted 386 compatibility rows (notably ENDBR64 and SWAPGS) object-level +// compatible even when LLVM's mnemonic matcher applies architectural mode +// restrictions. Effects remain typed so traps and non-returning RSM cannot +// accidentally acquire ordinary fallthrough. +var amd64FixedSystemSpecs = map[Op]amd64FixedSystemSpec{ + "CLAC": {encoding: ".byte 0x0f, 0x01, 0xca"}, + "CLI": {encoding: ".byte 0xfa"}, + "CLTS": {encoding: ".byte 0x0f, 0x06"}, + "ENDBR64": {encoding: ".byte 0xf3, 0x0f, 0x1e, 0xfa"}, + "ICEBP": {encoding: ".byte 0xf1", effect: amd64FixedSystemTrap}, + "INVD": {encoding: ".byte 0x0f, 0x08"}, + "RSM": {encoding: ".byte 0x0f, 0xaa", effect: amd64FixedSystemControlTransfer}, + "STAC": {encoding: ".byte 0x0f, 0x01, 0xcb"}, + "STI": {encoding: ".byte 0xfb"}, + "SWAPGS": {encoding: ".byte 0x0f, 0x01, 0xf8"}, + "UD1": {encoding: ".byte 0x0f, 0xb9, 0x00", effect: amd64FixedSystemTrap}, + "WBINVD": {encoding: ".byte 0x0f, 0x09"}, +} + +func (c *amd64Ctx) lowerFixedSystem(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64FixedSystemSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, baseOp, ins.Raw) + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q()\n", + spec.encoding, "~{memory},~{dirflag},~{fpsr},~{flags}") + if spec.effect == amd64FixedSystemContinue { + return true, false, nil + } + c.b.WriteString(" unreachable\n") + return true, true, nil +} diff --git a/amd64_lower_fixed_system_test.go b/amd64_lower_fixed_system_test.go new file mode 100644 index 00000000..2b82df37 --- /dev/null +++ b/amd64_lower_fixed_system_test.go @@ -0,0 +1,147 @@ +package plan9asm + +import ( + "reflect" + "strings" + "testing" +) + +func TestAMD64FixedSystemGrammarIsComplete(t *testing.T) { + want := map[Op]amd64FixedSystemSpec{ + "CLAC": {encoding: ".byte 0x0f, 0x01, 0xca"}, + "CLI": {encoding: ".byte 0xfa"}, + "CLTS": {encoding: ".byte 0x0f, 0x06"}, + "ENDBR64": {encoding: ".byte 0xf3, 0x0f, 0x1e, 0xfa"}, + "ICEBP": {encoding: ".byte 0xf1", effect: amd64FixedSystemTrap}, + "INVD": {encoding: ".byte 0x0f, 0x08"}, + "RSM": {encoding: ".byte 0x0f, 0xaa", effect: amd64FixedSystemControlTransfer}, + "STAC": {encoding: ".byte 0x0f, 0x01, 0xcb"}, + "STI": {encoding: ".byte 0xfb"}, + "SWAPGS": {encoding: ".byte 0x0f, 0x01, 0xf8"}, + "UD1": {encoding: ".byte 0x0f, 0xb9, 0x00", effect: amd64FixedSystemTrap}, + "WBINVD": {encoding: ".byte 0x0f, 0x09"}, + } + if !reflect.DeepEqual(amd64FixedSystemSpecs, want) { + t.Fatalf("fixed-system grammar = %+v, want %+v", amd64FixedSystemSpecs, want) + } +} + +func TestTranslateX86FixedSystemCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := `TEXT fixedsystemforms(SB),$0-0 + CLAC + CLI + CLTS + ENDBR64 + INVD + STAC + STI + SWAPGS + WBINVD + RET +TEXT fixedsystemicebp(SB),$0-0 + ICEBP +TEXT fixedsystemrsm(SB),$0-0 + RSM +TEXT fixedsystemud1(SB),$0-0 + UD1 +` + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "fixedsystemforms": {Name: "fixedsystemforms", Ret: Void}, + "fixedsystemicebp": {Name: "fixedsystemicebp", Ret: Void}, + "fixedsystemrsm": {Name: "fixedsystemrsm", Ret: Void}, + "fixedsystemud1": {Name: "fixedsystemud1", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `.byte 0x0f, 0x01, 0xca`, + `.byte 0xfa`, + `.byte 0x0f, 0x06`, + `.byte 0xf3, 0x0f, 0x1e, 0xfa`, + `.byte 0x0f, 0x08`, + `.byte 0x0f, 0x01, 0xcb`, + `.byte 0xfb`, + `.byte 0x0f, 0x01, 0xf8`, + `.byte 0x0f, 0x09`, + `.byte 0xf1`, + `.byte 0x0f, 0xaa`, + `.byte 0x0f, 0xb9, 0x00`, + `unreachable`, + } { + if !strings.Contains(ir, want) { + t.Errorf("IR is missing %s:\n%s", want, ir) + } + } + if got := strings.Count(ir, "unreachable"); got != 3 { + t.Errorf("unreachable count = %d, want 3", got) + } + compileLLVMToObject(t, llc, target.triple, "fixed-system-"+target.name+".ll", "fixed-system-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86FixedSystemRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "CLAC AX"}, + {goarch: "amd64", instruction: "CLI.P"}, + {goarch: "amd64", instruction: "CLTS AX"}, + {goarch: "amd64", instruction: "ENDBR64 AX"}, + {goarch: "amd64", instruction: "ICEBP AX"}, + {goarch: "amd64", instruction: "INVD AX"}, + {goarch: "amd64", instruction: "RSM AX"}, + {goarch: "amd64", instruction: "STAC AX"}, + {goarch: "amd64", instruction: "STI AX"}, + {goarch: "amd64", instruction: "SWAPGS AX"}, + {goarch: "amd64", instruction: "UD1 AX"}, + {goarch: "amd64", instruction: "WBINVD AX"}, + {goarch: "386", instruction: "ENDBR64.P"}, + {goarch: "386", instruction: "SWAPGS AX"}, + } { + t.Run(test.goarch+"_"+strings.ReplaceAll(test.instruction, " ", "_"), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's fixed-system tables", test.instruction) + } + }) + } +} diff --git a/amd64_lower_fixupimm.go b/amd64_lower_fixupimm.go new file mode 100644 index 00000000..652afc02 --- /dev/null +++ b/amd64_lower_fixupimm.go @@ -0,0 +1,205 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64FixupImmediateSpec struct { + laneBits int + scalar bool +} + +var amd64FixupImmediateSpecs = map[Op]amd64FixupImmediateSpec{ + "VFIXUPIMMPS": {laneBits: 32}, + "VFIXUPIMMPD": {laneBits: 64}, + "VFIXUPIMMSS": {laneBits: 32, scalar: true}, + "VFIXUPIMMSD": {laneBits: 64, scalar: true}, +} + +func (c *amd64Ctx) lowerFixupImmediate(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64FixupImmediateSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + shape := amd64UnaryImmediateFloatingShape{laneBits: spec.laneBits, scalar: spec.scalar, twoSource: true} + form, err := c.parseUnaryImmediateFloatingForm(baseOp, suffix, shape, ins) + if err != nil { + return true, false, err + } + daz := c.loadMXCSRDAZ() + if spec.scalar { + return c.lowerScalarFixupImmediate(spec, form, daz) + } + return c.lowerPackedFixupImmediate(spec, form, daz) +} + +func (c *amd64Ctx) lowerPackedFixupImmediate(spec amd64FixupImmediateSpec, form amd64UnaryImmediateFloatingForm, daz string) (bool, bool, error) { + lanes := form.byteWidth * 8 / spec.laneBits + table, err := c.loadPackedCompareLanes(form.source, form.byteWidth, spec.laneBits, form.properties.broadcast) + if err != nil { + return true, false, err + } + classified, err := c.loadPackedCompareLanes(form.passthrough, form.byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(form.destination, form.byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(form.byteWidth, lanes, spec.laneBits, oldBytes) + result := c.emitFixupImmediateBits(lanes, spec.laneBits, classified, table, old, daz) + if form.mask != "" { + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, form.mask, form.properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, form.byteWidth) + return true, false, c.storeVectorBytes(form.destination.Reg, form.byteWidth, "%"+out) +} + +func (c *amd64Ctx) lowerScalarFixupImmediate(spec amd64FixupImmediateSpec, form amd64UnaryImmediateFloatingForm, daz string) (bool, bool, error) { + tableBits, err := c.loadFloatingScalarBits(form.source, spec.laneBits) + if err != nil { + return true, false, err + } + classifiedBytes, err := c.loadX(form.passthrough.Reg) + if err != nil { + return true, false, err + } + classifiedVector := c.bitcastVectorBytesToIntegerLanes(16, 128/spec.laneBits, spec.laneBits, classifiedBytes) + classifiedLow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 0\n", classifiedLow, 128/spec.laneBits, spec.laneBits, classifiedVector) + oldLow, err := c.loadXLowInteger(form.destination.Reg, spec.laneBits) + if err != nil { + return true, false, err + } + tableVector, classifiedOne, oldVector := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", tableVector, spec.laneBits, spec.laneBits, tableBits) + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %%%s, i32 0\n", classifiedOne, spec.laneBits, spec.laneBits, classifiedLow) + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", oldVector, spec.laneBits, spec.laneBits, oldLow) + result := c.emitFixupImmediateBits(1, spec.laneBits, "%"+classifiedOne, "%"+tableVector, "%"+oldVector, daz) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i%d> %s, i32 0\n", low, spec.laneBits, result) + return true, false, c.storeVectorScalarRegister(form.destination.Reg, spec.laneBits, "%"+low, classifiedVector, form.mask, form.properties.zeroing) +} + +// emitFixupImmediateBits implements the data-result portion of Intel's +// FIXUPIMM_SP/FIXUPIMM_DP grammar. imm8 controls only MXCSR exception +// reporting; plan9asm does not currently expose floating exception state. +func (c *amd64Ctx) emitFixupImmediateBits(lanes, laneBits int, classified, table, old, daz string) string { + vectorType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + exponentMask := uint64(0x7f800000) + mantissaMask := uint64(0x007fffff) + quietBit := uint64(0x00400000) + signBit := uint64(0x80000000) + positiveOne := uint64(0x3f800000) + constants := [16]uint64{ + 0, 0, 0, 0xffc00000, + 0xff800000, 0x7f800000, 0, 0x80000000, + 0, 0xbf800000, 0x3f800000, 0x3f000000, + 0x42b40000, 0x3fc90fdb, 0x7f7fffff, 0xff7fffff, + } + if laneBits == 64 { + exponentMask = uint64(0x7ff0000000000000) + mantissaMask = uint64(0x000fffffffffffff) + quietBit = uint64(0x0008000000000000) + signBit = uint64(0x8000000000000000) + positiveOne = uint64(0x3ff0000000000000) + constants = [16]uint64{ + 0, 0, 0, 0xfff8000000000000, + 0xfff0000000000000, 0x7ff0000000000000, 0, 0x8000000000000000, + 0, 0xbff0000000000000, 0x3ff0000000000000, 0x3fe0000000000000, + 0x4056800000000000, 0x3ff921fb54442d18, 0x7fefffffffffffff, 0xffefffffffffffff, + } + } + result := "poison" + for lane := 0; lane < lanes; lane++ { + raw, tableLane, oldLane := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", raw, vectorType, classified, lane) + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", tableLane, vectorType, table, lane) + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", oldLane, vectorType, old, lane) + rawExponent, exponentZero, dazZero := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", rawExponent, laneBits, raw, exponentMask) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", exponentZero, laneBits, rawExponent) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %s\n", dazZero, exponentZero, daz) + effective := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d 0, i%d %%%s\n", effective, dazZero, laneBits, laneBits, raw) + + exponent, mantissa, sign, absolute := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", exponent, laneBits, effective, exponentMask) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", mantissa, laneBits, effective, mantissaMask) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", sign, laneBits, effective, signBit) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", absolute, laneBits, effective, signBit-1) + exponentOnes, mantissaZero, mantissaNonzero, negative, zero := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, %d\n", exponentOnes, laneBits, exponent, exponentMask) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", mantissaZero, laneBits, mantissa) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", mantissaNonzero, laneBits, mantissa) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", negative, laneBits, sign) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", zero, laneBits, absolute) + isNaN, isInfinity, quietSet := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isNaN, exponentOnes, mantissaNonzero) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isInfinity, exponentOnes, mantissaZero) + quietValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", quietValue, laneBits, mantissa, quietBit) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", quietSet, laneBits, quietValue) + notQuiet, signalingNaN, quietNaN := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", notQuiet, quietSet) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", signalingNaN, isNaN, notQuiet) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", quietNaN, isNaN, quietSet) + negativeInfinity, positiveInfinity, notNegative := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", negativeInfinity, isInfinity, negative) + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", notNegative, negative) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", positiveInfinity, isInfinity, notNegative) + positiveOneValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, %d\n", positiveOneValue, laneBits, effective, positiveOne) + + token := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d 6, i%d 7\n", token, negative, laneBits, laneBits) + for _, selection := range []struct { + predicate string + value int + }{ + {predicate: positiveInfinity, value: 5}, + {predicate: negativeInfinity, value: 4}, + {predicate: positiveOneValue, value: 3}, + {predicate: zero, value: 2}, + {predicate: signalingNaN, value: 1}, + {predicate: quietNaN, value: 0}, + } { + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d %%%s\n", selected, selection.predicate, laneBits, selection.value, laneBits, token) + token = selected + } + shift, shiftedTable, response := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i%d %%%s, 2\n", shift, laneBits, token) + fmt.Fprintf(c.b, " %%%s = lshr i%d %%%s, %%%s\n", shiftedTable, laneBits, tableLane, shift) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, 15\n", response, laneBits, shiftedTable) + + quieted, signedInfinity := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %d\n", quieted, laneBits, effective, exponentMask|quietBit) + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %d\n", signedInfinity, laneBits, sign, exponentMask) + responseValues := [16]string{ + "%" + oldLane, "%" + effective, "%" + quieted, + fmt.Sprintf("%d", constants[3]), fmt.Sprintf("%d", constants[4]), fmt.Sprintf("%d", constants[5]), "%" + signedInfinity, + fmt.Sprintf("%d", constants[7]), fmt.Sprintf("%d", constants[8]), fmt.Sprintf("%d", constants[9]), fmt.Sprintf("%d", constants[10]), + fmt.Sprintf("%d", constants[11]), fmt.Sprintf("%d", constants[12]), fmt.Sprintf("%d", constants[13]), fmt.Sprintf("%d", constants[14]), fmt.Sprintf("%d", constants[15]), + } + laneResult := responseValues[0] + for responseValue := 1; responseValue < len(responseValues); responseValue++ { + matches, selected := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, %d\n", matches, laneBits, response, responseValue) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %s, i%d %s\n", selected, matches, laneBits, responseValues[responseValue], laneBits, laneResult) + laneResult = "%" + selected + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %s, i32 %d\n", inserted, vectorType, result, laneBits, laneResult, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_fixupimm_test.go b/amd64_lower_fixupimm_test.go new file mode 100644 index 00000000..8cd63792 --- /dev/null +++ b/amd64_lower_fixupimm_test.go @@ -0,0 +1,265 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +type fixupImmediateTestSpec struct { + op string + laneBits int + scalar bool +} + +func go127FixupImmediateSpecs() []fixupImmediateTestSpec { + return []fixupImmediateTestSpec{ + {op: "VFIXUPIMMPS", laneBits: 32}, + {op: "VFIXUPIMMPD", laneBits: 64}, + {op: "VFIXUPIMMSS", laneBits: 32, scalar: true}, + {op: "VFIXUPIMMSD", laneBits: 64, scalar: true}, + } +} + +func TestAMD64FixupImmediateGrammarCoversCompleteGoFamily(t *testing.T) { + expected := go127FixupImmediateSpecs() + if len(amd64FixupImmediateSpecs) != len(expected) { + t.Fatalf("FIXUPIMM grammar has %d entries, want %d", len(amd64FixupImmediateSpecs), len(expected)) + } + for _, want := range expected { + got, ok := amd64FixupImmediateSpecs[Op(want.op)] + if !ok { + t.Errorf("FIXUPIMM grammar omitted %s", want.op) + continue + } + if got.laneBits != want.laneBits || got.scalar != want.scalar { + t.Errorf("FIXUPIMM grammar %s = %+v, want laneBits=%d scalar=%v", want.op, got, want.laneBits, want.scalar) + } + } +} + +func TestTranslateX86FixupImmediateCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT fixupimmforms(SB),$0-0\n") + for index, spec := range go127FixupImmediateSpecs() { + if spec.scalar { + fmt.Fprintf(&source, "\t%s $%d, X0, X1, X23\n", spec.op, index) + fmt.Fprintf(&source, "\t%s $%d, %d(AX), X1, X23\n", spec.op, index+16, index*8) + fmt.Fprintf(&source, "\t%s $%d, X2, X1, K1, X23\n", spec.op, index+32) + fmt.Fprintf(&source, "\t%s.Z $%d, %d(AX), X1, K2, X23\n", spec.op, index+48, index*8) + fmt.Fprintf(&source, "\t%s.SAE $%d, X3, X1, X23\n", spec.op, index+64) + fmt.Fprintf(&source, "\t%s.SAE.Z $%d, X4, X1, K3, X23\n", spec.op, index+80) + continue + } + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&source, "\t%s $%d, %s0, %s1, %s23\n", spec.op, index, width, width, width) + fmt.Fprintf(&source, "\t%s $%d, %d(AX), %s1, %s23\n", spec.op, index+16, index*8, width, width) + fmt.Fprintf(&source, "\t%s.BCST $%d, %d(AX), %s1, %s23\n", spec.op, index+32, index*8, width, width) + fmt.Fprintf(&source, "\t%s $%d, %s2, %s1, K1, %s23\n", spec.op, index+48, width, width, width) + fmt.Fprintf(&source, "\t%s.BCST.Z $%d, %d(AX), %s1, K2, %s23\n", spec.op, index+64, index*8, width, width) + } + fmt.Fprintf(&source, "\t%s.SAE $%d, Z3, Z1, Z23\n", spec.op, index+80) + fmt.Fprintf(&source, "\t%s.SAE.Z $%d, Z4, Z1, K3, Z23\n", spec.op, index+96) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, "amd64", source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: target.triple, + Sigs: map[string]FuncSig{"fixupimmforms": {Name: "fixupimmforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "fixupimm-"+target.name+".ll", "fixupimm-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86FixupImmediateRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VFIXUPIMMPS $-1, X0, X1, X2"}, + {goarch: "amd64", instruction: "VFIXUPIMMPS $256, X0, X1, X2"}, + {goarch: "amd64", instruction: "VFIXUPIMMPS.Z $1, X0, X1, X2"}, + {goarch: "amd64", instruction: "VFIXUPIMMPS $1, X0, Y1, Y2"}, + {goarch: "amd64", instruction: "VFIXUPIMMPS.SAE $1, X0, X1, X2"}, + {goarch: "amd64", instruction: "VFIXUPIMMPS.SAE $1, 0(AX), Z1, Z2"}, + {goarch: "amd64", instruction: "VFIXUPIMMPS $1, X0, X1, K0, X2"}, + {goarch: "amd64", instruction: "VFIXUPIMMSS.BCST $1, 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VFIXUPIMMSS.SAE $1, 0(AX), X1, X2"}, + {goarch: "386", instruction: "VFIXUPIMMPS $1, X0, X1, X2"}, + {goarch: "386", instruction: "VFIXUPIMMSS $1, X0, X1, X2"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's FIXUPIMM tables", test.instruction) + } + }) + } +} + +func TestAMD64FixupImmediateRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT fixupimmsemantics(SB),$0-64 + MOVQ out+0(FP), AX + MOVQ src32+8(FP), BX + MOVQ table32+16(FP), CX + MOVQ old32+24(FP), DX + MOVQ src64+32(FP), R8 + MOVQ table64+40(FP), R9 + MOVQ old64+48(FP), R10 + MOVQ mask+56(FP), R11 + KMOVQ R11, K1 + VMOVDQU32 0(BX), Z1 + VMOVDQU32 0(CX), Z0 + VMOVDQU32 0(DX), Z2 + STC + VFIXUPIMMPS $0, Z0, Z1, Z2 + VMOVDQU32 Z2, 0(AX) + VMOVDQU32 0(DX), Z2 + VFIXUPIMMPS $0, Z0, Z1, K1, Z2 + VMOVDQU32 Z2, 64(AX) + VFIXUPIMMPS.Z $0, Z0, Z1, K1, Z3 + VMOVDQU32 Z3, 128(AX) + VMOVDQU64 0(R8), Z5 + VMOVDQU64 0(R9), Z4 + VMOVDQU64 0(R10), Z6 + VFIXUPIMMPD $0, Z4, Z5, Z6 + VMOVDQU64 Z6, 192(AX) + VMOVDQU64 0(R8), X5 + VMOVDQU64 0(R9), X4 + VMOVDQU64 0(R10), X6 + VFIXUPIMMSD $0, X4, X5, X6 + VMOVDQU64 X6, 256(AX) + VMOVDQU32 0(BX), X1 + VMOVDQU32 0(CX), X0 + VMOVDQU32 0(DX), X2 + VFIXUPIMMSS $0, X0, X1, X2 + VMOVDQU32 X2, 272(AX) + SETCS 288(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"fixupimmsemantics": { + Name: "fixupimmsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + {Offset: 48, Type: Ptr, Index: 6, Field: -1}, + {Offset: 56, Type: I64, Index: 7, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +#include +extern void fixupimmsemantics(uint8_t *, const uint32_t *, const uint32_t *, const uint32_t *, const uint64_t *, const uint64_t *, const uint64_t *, uint64_t); +static unsigned token32(uint32_t x, int daz) { + if (daz && (x & UINT32_C(0x7f800000)) == 0) x = 0; + uint32_t a=x&UINT32_C(0x7fffffff),m=x&UINT32_C(0x007fffff),e=x&UINT32_C(0x7f800000); + if(e==UINT32_C(0x7f800000)&&m) return m&UINT32_C(0x00400000)?0:1; + if(a==0)return 2;if(x==UINT32_C(0x3f800000))return 3; + if(a==UINT32_C(0x7f800000))return x>>31?4:5;return x>>31?6:7; +} +static unsigned token64(uint64_t x, int daz) { + if (daz && (x & UINT64_C(0x7ff0000000000000)) == 0) x = 0; + uint64_t a=x&UINT64_C(0x7fffffffffffffff),m=x&UINT64_C(0x000fffffffffffff),e=x&UINT64_C(0x7ff0000000000000); + if(e==UINT64_C(0x7ff0000000000000)&&m) return m&UINT64_C(0x0008000000000000)?0:1; + if(a==0)return 2;if(x==UINT64_C(0x3ff0000000000000))return 3; + if(a==UINT64_C(0x7ff0000000000000))return x>>63?4:5;return x>>63?6:7; +} +static uint32_t effective32(uint32_t x,int daz){return daz&&(x&UINT32_C(0x7f800000))==0?0:x;} +static uint64_t effective64(uint64_t x,int daz){return daz&&(x&UINT64_C(0x7ff0000000000000))==0?0:x;} +static uint32_t fix32(uint32_t old,uint32_t x,uint32_t table,int daz){ + x=effective32(x,daz);unsigned r=(table>>(4*token32(x,0)))&15; + static const uint32_t c[16]={0,0,0,UINT32_C(0xffc00000),UINT32_C(0xff800000),UINT32_C(0x7f800000),0,UINT32_C(0x80000000),0,UINT32_C(0xbf800000),UINT32_C(0x3f800000),UINT32_C(0x3f000000),UINT32_C(0x42b40000),UINT32_C(0x3fc90fdb),UINT32_C(0x7f7fffff),UINT32_C(0xff7fffff)}; + if(r==0)return old;if(r==1)return x;if(r==2)return x|UINT32_C(0x7fc00000);if(r==6)return (x&UINT32_C(0x80000000))|UINT32_C(0x7f800000);return c[r]; +} +static uint64_t fix64(uint64_t old,uint64_t x,uint64_t table,int daz){ + x=effective64(x,daz);unsigned r=(table>>(4*token64(x,0)))&15; + static const uint64_t c[16]={0,0,0,UINT64_C(0xfff8000000000000),UINT64_C(0xfff0000000000000),UINT64_C(0x7ff0000000000000),0,UINT64_C(0x8000000000000000),0,UINT64_C(0xbff0000000000000),UINT64_C(0x3ff0000000000000),UINT64_C(0x3fe0000000000000),UINT64_C(0x4056800000000000),UINT64_C(0x3ff921fb54442d18),UINT64_C(0x7fefffffffffffff),UINT64_C(0xffefffffffffffff)}; + if(r==0)return old;if(r==1)return x;if(r==2)return x|UINT64_C(0x7ff8000000000000);if(r==6)return (x&UINT64_C(0x8000000000000000))|UINT64_C(0x7ff0000000000000);return c[r]; +} +int main(void){ + const uint32_t src32[16]={UINT32_C(0x7fc12345),1,UINT32_C(0xc0200001),0,UINT32_C(0xff800000),UINT32_C(0x7f800000),UINT32_C(0xc0000000),UINT32_C(0x40000000),UINT32_C(0x80000000),UINT32_C(0x3f800000),UINT32_C(0x7f812345),UINT32_C(0x80000001),UINT32_C(0x40400000),UINT32_C(0xc0800000),UINT32_C(0x3f400000),UINT32_C(0xbf400000)}; + const uint64_t src64[8]={UINT64_C(0x7ff8123456789abc),1,UINT64_C(0xc004000000000001),0,UINT64_C(0xfff0000000000000),UINT64_C(0x7ff0000000000000),UINT64_C(0xc000000000000000),UINT64_C(0x4000000000000000)}; + uint32_t old32[16],table32[16],got32[48],want32[48];uint64_t old64[8],table64[8],got64[10],want64[10];uint8_t out[289]; + const uint64_t mask=UINT64_C(0xa55a);unsigned original=_mm_getcsr(); + for(int i=0;i<16;i++)old32[i]=UINT32_C(0x41000000)+i;for(int i=0;i<8;i++)old64[i]=UINT64_C(0x4020000000000000)+i; + for(int daz=0;daz<2;daz++){ + _mm_setcsr((original&~64u)|(daz?64u:0));memset(out,0,sizeof(out)); + for(int i=0;i<16;i++)table32[i]=(uint32_t)i<<(4*token32(src32[i],daz)); + for(int i=0;i<8;i++)table64[i]=(uint64_t)(i+8)<<(4*token64(src64[i],daz)); + fixupimmsemantics(out,src32,table32,old32,src64,table64,old64,mask);memcpy(got32,out,192);memcpy(got64,out+192,80); + for(int i=0;i<16;i++){uint32_t v=fix32(old32[i],src32[i],table32[i],daz);want32[i]=v;want32[16+i]=(mask>>i)&1?v:old32[i];want32[32+i]=(mask>>i)&1?v:0;} + for(int i=0;i<8;i++)want64[i]=fix64(old64[i],src64[i],table64[i],daz);want64[8]=fix64(old64[0],src64[0],table64[0],daz);want64[9]=src64[1]; + for(int i=0;i<48;i++)if(got32[i]!=want32[i])return 10+daz; + for(int i=0;i<10;i++)if(got64[i]!=want64[i])return 20+daz; + uint32_t scalar32[4];memcpy(scalar32,out+272,16);if(scalar32[0]!=fix32(old32[0],src32[0],table32[0],daz)||scalar32[1]!=src32[1]||scalar32[2]!=src32[2]||scalar32[3]!=src32[3])return 30+daz; + if(out[288]!=1)return 40+daz; + } + _mm_setcsr(original);return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "fixupimm_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_float_movemask_test.go b/amd64_lower_float_movemask_test.go new file mode 100644 index 00000000..99542474 --- /dev/null +++ b/amd64_lower_float_movemask_test.go @@ -0,0 +1,94 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86FloatingMoveMaskCompleteGoAssemblerForms(t *testing.T) { + // MOVMSK{PS,PD} uses Go's legacy yxrrl table (X -> Yrl), while the + // VMOVMSK forms use _yvmovmskpd (X/Y -> Yrl). Neither table accepts + // memory, EVEX registers, masks, or opcode suffixes. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastLegacyX := 15 + if target.goarch == "386" { + lastLegacyX = 7 + } + source := fmt.Sprintf(` +TEXT floatingmovemaskforms(SB),NOSPLIT,$0-0 + MOVMSKPS X%d, AX + MOVMSKPD X%d, BX + VMOVMSKPS X15, CX + VMOVMSKPS Y15, DX + VMOVMSKPD X15, SI + VMOVMSKPD Y15, DI + RET +`, lastLegacyX, lastLegacyX) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"floatingmovemaskforms": {Name: "floatingmovemaskforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "floating-movemask-"+target.name+".ll", "floating-movemask-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86FloatingMoveMaskRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "MOVMSKPS Y0, AX", + "MOVMSKPD (AX), BX", + "MOVMSKPS X16, AX", + "VMOVMSKPS Z0, AX", + "VMOVMSKPD X16, AX", + "VMOVMSKPS Y16, AX", + "VMOVMSKPD (AX), BX", + "VMOVMSKPS X0, X1", + "VMOVMSKPD X0, K1, AX", + "MOVMSKPS.Z X0, AX", + "VMOVMSKPD.BCST Y0, AX", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86FloatingMoveMaskRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + assertX86FloatingMoveMaskRejected(t, "386", "i386-unknown-linux-gnu", "MOVMSKPS X8, AX") +} + +func assertX86FloatingMoveMaskRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's floating movemask forms", instruction) + } +} diff --git a/amd64_lower_fma3.go b/amd64_lower_fma3.go new file mode 100644 index 00000000..dd6b943a --- /dev/null +++ b/amd64_lower_fma3.go @@ -0,0 +1,396 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64FMA3Mode uint8 + +const ( + amd64FMA3Add amd64FMA3Mode = iota + amd64FMA3Sub + amd64FMA3NegAdd + amd64FMA3NegSub + amd64FMA3AddSub + amd64FMA3SubAdd +) + +type amd64FMA3Spec struct { + laneBits int + order int + mode amd64FMA3Mode + scalar bool +} + +// amd64FMA3Specs is the complete Go 1.27 FMA3 family. The 36 packed +// instructions use _yvaddpd and the 24 scalar instructions use _yvaddsd. +var amd64FMA3Specs = map[Op]amd64FMA3Spec{ + "VFMADD132PS": {laneBits: 32, order: 132, mode: amd64FMA3Add}, + "VFMADD132PD": {laneBits: 64, order: 132, mode: amd64FMA3Add}, + "VFMADD132SS": {laneBits: 32, order: 132, mode: amd64FMA3Add, scalar: true}, + "VFMADD132SD": {laneBits: 64, order: 132, mode: amd64FMA3Add, scalar: true}, + "VFMADD213PS": {laneBits: 32, order: 213, mode: amd64FMA3Add}, + "VFMADD213PD": {laneBits: 64, order: 213, mode: amd64FMA3Add}, + "VFMADD213SS": {laneBits: 32, order: 213, mode: amd64FMA3Add, scalar: true}, + "VFMADD213SD": {laneBits: 64, order: 213, mode: amd64FMA3Add, scalar: true}, + "VFMADD231PS": {laneBits: 32, order: 231, mode: amd64FMA3Add}, + "VFMADD231PD": {laneBits: 64, order: 231, mode: amd64FMA3Add}, + "VFMADD231SS": {laneBits: 32, order: 231, mode: amd64FMA3Add, scalar: true}, + "VFMADD231SD": {laneBits: 64, order: 231, mode: amd64FMA3Add, scalar: true}, + "VFMSUB132PS": {laneBits: 32, order: 132, mode: amd64FMA3Sub}, + "VFMSUB132PD": {laneBits: 64, order: 132, mode: amd64FMA3Sub}, + "VFMSUB132SS": {laneBits: 32, order: 132, mode: amd64FMA3Sub, scalar: true}, + "VFMSUB132SD": {laneBits: 64, order: 132, mode: amd64FMA3Sub, scalar: true}, + "VFMSUB213PS": {laneBits: 32, order: 213, mode: amd64FMA3Sub}, + "VFMSUB213PD": {laneBits: 64, order: 213, mode: amd64FMA3Sub}, + "VFMSUB213SS": {laneBits: 32, order: 213, mode: amd64FMA3Sub, scalar: true}, + "VFMSUB213SD": {laneBits: 64, order: 213, mode: amd64FMA3Sub, scalar: true}, + "VFMSUB231PS": {laneBits: 32, order: 231, mode: amd64FMA3Sub}, + "VFMSUB231PD": {laneBits: 64, order: 231, mode: amd64FMA3Sub}, + "VFMSUB231SS": {laneBits: 32, order: 231, mode: amd64FMA3Sub, scalar: true}, + "VFMSUB231SD": {laneBits: 64, order: 231, mode: amd64FMA3Sub, scalar: true}, + "VFNMADD132PS": {laneBits: 32, order: 132, mode: amd64FMA3NegAdd}, + "VFNMADD132PD": {laneBits: 64, order: 132, mode: amd64FMA3NegAdd}, + "VFNMADD132SS": {laneBits: 32, order: 132, mode: amd64FMA3NegAdd, scalar: true}, + "VFNMADD132SD": {laneBits: 64, order: 132, mode: amd64FMA3NegAdd, scalar: true}, + "VFNMADD213PS": {laneBits: 32, order: 213, mode: amd64FMA3NegAdd}, + "VFNMADD213PD": {laneBits: 64, order: 213, mode: amd64FMA3NegAdd}, + "VFNMADD213SS": {laneBits: 32, order: 213, mode: amd64FMA3NegAdd, scalar: true}, + "VFNMADD213SD": {laneBits: 64, order: 213, mode: amd64FMA3NegAdd, scalar: true}, + "VFNMADD231PS": {laneBits: 32, order: 231, mode: amd64FMA3NegAdd}, + "VFNMADD231PD": {laneBits: 64, order: 231, mode: amd64FMA3NegAdd}, + "VFNMADD231SS": {laneBits: 32, order: 231, mode: amd64FMA3NegAdd, scalar: true}, + "VFNMADD231SD": {laneBits: 64, order: 231, mode: amd64FMA3NegAdd, scalar: true}, + "VFNMSUB132PS": {laneBits: 32, order: 132, mode: amd64FMA3NegSub}, + "VFNMSUB132PD": {laneBits: 64, order: 132, mode: amd64FMA3NegSub}, + "VFNMSUB132SS": {laneBits: 32, order: 132, mode: amd64FMA3NegSub, scalar: true}, + "VFNMSUB132SD": {laneBits: 64, order: 132, mode: amd64FMA3NegSub, scalar: true}, + "VFNMSUB213PS": {laneBits: 32, order: 213, mode: amd64FMA3NegSub}, + "VFNMSUB213PD": {laneBits: 64, order: 213, mode: amd64FMA3NegSub}, + "VFNMSUB213SS": {laneBits: 32, order: 213, mode: amd64FMA3NegSub, scalar: true}, + "VFNMSUB213SD": {laneBits: 64, order: 213, mode: amd64FMA3NegSub, scalar: true}, + "VFNMSUB231PS": {laneBits: 32, order: 231, mode: amd64FMA3NegSub}, + "VFNMSUB231PD": {laneBits: 64, order: 231, mode: amd64FMA3NegSub}, + "VFNMSUB231SS": {laneBits: 32, order: 231, mode: amd64FMA3NegSub, scalar: true}, + "VFNMSUB231SD": {laneBits: 64, order: 231, mode: amd64FMA3NegSub, scalar: true}, + "VFMADDSUB132PS": {laneBits: 32, order: 132, mode: amd64FMA3AddSub}, + "VFMADDSUB132PD": {laneBits: 64, order: 132, mode: amd64FMA3AddSub}, + "VFMADDSUB213PS": {laneBits: 32, order: 213, mode: amd64FMA3AddSub}, + "VFMADDSUB213PD": {laneBits: 64, order: 213, mode: amd64FMA3AddSub}, + "VFMADDSUB231PS": {laneBits: 32, order: 231, mode: amd64FMA3AddSub}, + "VFMADDSUB231PD": {laneBits: 64, order: 231, mode: amd64FMA3AddSub}, + "VFMSUBADD132PS": {laneBits: 32, order: 132, mode: amd64FMA3SubAdd}, + "VFMSUBADD132PD": {laneBits: 64, order: 132, mode: amd64FMA3SubAdd}, + "VFMSUBADD213PS": {laneBits: 32, order: 213, mode: amd64FMA3SubAdd}, + "VFMSUBADD213PD": {laneBits: 64, order: 213, mode: amd64FMA3SubAdd}, + "VFMSUBADD231PS": {laneBits: 32, order: 231, mode: amd64FMA3SubAdd}, + "VFMSUBADD231PD": {laneBits: 64, order: 231, mode: amd64FMA3SubAdd}, +} + +type amd64FMA3Suffix struct { + broadcast bool + zeroing bool + rounding string +} + +func parseAMD64FMA3Suffix(suffix string) (amd64FMA3Suffix, bool) { + switch suffix { + case "": + return amd64FMA3Suffix{}, true + case "Z": + return amd64FMA3Suffix{zeroing: true}, true + case "BCST": + return amd64FMA3Suffix{broadcast: true}, true + case "BCST.Z": + return amd64FMA3Suffix{broadcast: true, zeroing: true}, true + case "RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE": + return amd64FMA3Suffix{rounding: suffix}, true + case "RN_SAE.Z", "RD_SAE.Z", "RU_SAE.Z", "RZ_SAE.Z": + return amd64FMA3Suffix{zeroing: true, rounding: strings.TrimSuffix(suffix, ".Z")}, true + default: + return amd64FMA3Suffix{}, false + } +} + +func (c *amd64Ctx) lowerFMA3(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64FMA3Specs[Op(baseOp)] + if !recognized { + return false, false, nil + } + properties, validSuffix := parseAMD64FMA3Suffix(suffix) + if !validSuffix { + return true, false, fmt.Errorf("%s %s has a suffix absent from Go 1.27's FMA3 optab: %q", c.goarch, baseOp, ins.Raw) + } + if spec.scalar && properties.broadcast { + return true, false, fmt.Errorf("%s %s scalar forms do not support broadcast: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects src1, src2, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed Go 1.27's assembler operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be a vector register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if spec.scalar { + if byteWidth != 16 { + return true, false, fmt.Errorf("%s %s scalar destination must be an X register: %q", c.goarch, baseOp, ins.Raw) + } + } else if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s packed destination must be an X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoEVEXVectorRegister(dstArg, byteWidth) || !c.isGoEVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s second source and destination must be same-width Go 1.27 EVEX registers: %q", c.goarch, baseOp, ins.Raw) + } + if properties.rounding != "" && !spec.scalar && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s packed rounding is available only for Z registers: %q", c.goarch, baseOp, ins.Raw) + } + if properties.broadcast { + if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory first source: %q", c.goarch, baseOp, ins.Raw) + } + } else if ins.Args[0].Kind == OpReg { + if !c.isGoEVEXVectorRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match the destination width and register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if properties.rounding != "" { + return true, false, fmt.Errorf("%s %s explicit rounding requires a register first source: %q", c.goarch, baseOp, ins.Raw) + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + loadedMask, loadErr := c.loadK(ins.Args[2].Reg) + if loadErr != nil { + return true, false, loadErr + } + mask = loadedMask + } + if spec.scalar { + return c.lowerScalarFMA3(spec, properties, ins, dstArg, mask) + } + return c.lowerPackedFMA3(spec, properties, ins, dstArg, byteWidth, mask) +} + +func (c *amd64Ctx) lowerPackedFMA3(spec amd64FMA3Spec, properties amd64FMA3Suffix, ins Instr, dstArg Operand, byteWidth int, mask string) (bool, bool, error) { + lanes := byteWidth * 8 / spec.laneBits + llvmType := amd64FMA3LLVMType(lanes, spec.laneBits) + load := func(arg Operand, allowBroadcast bool) (string, error) { + if allowBroadcast && properties.broadcast { + var scalar string + var err error + if spec.laneBits == 32 { + scalar, err = c.evalF32(arg) + } else { + scalar, err = c.evalF64(arg) + } + if err != nil { + return "", err + } + return c.splatFMA3Scalar(lanes, spec.laneBits, scalar), nil + } + bytesValue, err := c.loadPackedCompareBytes(arg, byteWidth) + if err != nil { + return "", err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", value, byteWidth, bytesValue, llvmType) + return "%" + value, nil + } + first, err := load(ins.Args[0], true) + if err != nil { + return true, false, err + } + second, err := load(ins.Args[1], false) + if err != nil { + return true, false, err + } + old, err := load(dstArg, false) + if err != nil { + return true, false, err + } + computed := c.emitFMA3(spec, llvmType, lanes, first, second, old, properties.rounding) + if mask != "" { + computedBits := c.newTmp() + oldBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i%d>\n", computedBits, llvmType, computed, lanes, spec.laneBits) + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i%d>\n", oldBits, llvmType, old, lanes, spec.laneBits) + masked := amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, "%"+computedBits, "%"+oldBits, mask, properties.zeroing) + back := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to %s\n", back, lanes, spec.laneBits, masked, llvmType) + computed = "%" + back + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", out, llvmType, computed, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) lowerScalarFMA3(spec amd64FMA3Spec, properties amd64FMA3Suffix, ins Instr, dstArg Operand, mask string) (bool, bool, error) { + var first, second, old string + var err error + if spec.laneBits == 32 { + first, err = c.evalF32(ins.Args[0]) + if err == nil { + second, err = c.loadXLowF32(ins.Args[1].Reg) + } + if err == nil { + old, err = c.loadXLowF32(dstArg.Reg) + } + } else { + first, err = c.evalF64(ins.Args[0]) + if err == nil { + second, err = c.loadXLowF64(ins.Args[1].Reg) + } + if err == nil { + old, err = c.loadXLowF64(dstArg.Reg) + } + } + if err != nil { + return true, false, err + } + llvmType := amd64FMA3LLVMType(1, spec.laneBits) + computed := c.emitFMA3(spec, llvmType, 1, first, second, old, properties.rounding) + if mask != "" { + bit := amd64MaskBitI1(c, mask, 0) + fallback := old + if properties.zeroing { + fallback = "0.000000e+00" + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, %s %s, %s %s\n", selected, bit, llvmType, computed, llvmType, fallback) + computed = "%" + selected + } + destinationBytes, err := c.loadX(dstArg.Reg) + if err != nil { + return true, false, err + } + lanes := 128 / spec.laneBits + words := c.newTmp() + bits := c.newTmp() + inserted := c.newTmp() + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x i%d>\n", words, destinationBytes, lanes, spec.laneBits) + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to i%d\n", bits, llvmType, computed, spec.laneBits) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %%%s, i%d %%%s, i32 0\n", inserted, lanes, spec.laneBits, words, spec.laneBits, bits) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", out, lanes, spec.laneBits, inserted) + return true, false, c.storeX(dstArg.Reg, "%"+out) +} + +func amd64FMA3LLVMType(lanes, laneBits int) string { + element := "float" + if laneBits == 64 { + element = "double" + } + if lanes == 1 { + return element + } + return fmt.Sprintf("<%d x %s>", lanes, element) +} + +func (c *amd64Ctx) splatFMA3Scalar(lanes, laneBits int, scalar string) string { + typeName := amd64FMA3LLVMType(lanes, laneBits) + element := amd64FMA3LLVMType(1, laneBits) + seed := c.newTmp() + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s poison, %s %s, i32 0\n", seed, typeName, element, scalar) + fmt.Fprintf(c.b, " %%%s = shufflevector %s %%%s, %s poison, <%d x i32> zeroinitializer\n", splat, typeName, seed, typeName, lanes) + return "%" + splat +} + +func (c *amd64Ctx) emitFMA3(spec amd64FMA3Spec, llvmType string, lanes int, first, second, old, rounding string) string { + a, b, addend := old, first, second + switch spec.order { + case 213: + a, b, addend = second, old, first + case 231: + a, b, addend = second, first, old + } + if spec.mode == amd64FMA3NegAdd || spec.mode == amd64FMA3NegSub { + negated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", negated, llvmType, a) + a = "%" + negated + } + switch spec.mode { + case amd64FMA3Sub, amd64FMA3NegSub: + negated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", negated, llvmType, addend) + addend = "%" + negated + case amd64FMA3AddSub, amd64FMA3SubAdd: + addend = c.alternateFMA3Addend(llvmType, lanes, addend, spec.mode == amd64FMA3AddSub) + } + result := c.newTmp() + intrinsic := amd64FMA3IntrinsicName(lanes, spec.laneBits, rounding != "") + if rounding == "" { + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %s, %s %s, %s %s)\n", result, llvmType, intrinsic, llvmType, a, llvmType, b, llvmType, addend) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %s, %s %s, %s %s, metadata !\"%s\", metadata !\"fpexcept.ignore\")\n", result, llvmType, intrinsic, llvmType, a, llvmType, b, llvmType, addend, amd64FMA3RoundingMetadata(rounding)) + } + return "%" + result +} + +func (c *amd64Ctx) alternateFMA3Addend(llvmType string, lanes int, addend string, negateEven bool) string { + negated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", negated, llvmType, addend) + var mask strings.Builder + mask.WriteByte('<') + for lane := 0; lane < lanes; lane++ { + if lane > 0 { + mask.WriteString(", ") + } + selected := lane%2 == 0 + if !negateEven { + selected = !selected + } + fmt.Fprintf(&mask, "i1 %t", selected) + } + mask.WriteByte('>') + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %s, %s %%%s, %s %s\n", result, lanes, mask.String(), llvmType, negated, llvmType, addend) + return "%" + result +} + +func amd64FMA3IntrinsicName(lanes, laneBits int, constrained bool) string { + prefix := "llvm.fma." + if constrained { + prefix = "llvm.experimental.constrained.fma." + } + suffix := "f32" + if laneBits == 64 { + suffix = "f64" + } + if lanes > 1 { + suffix = fmt.Sprintf("v%d%s", lanes, suffix) + } + return prefix + suffix +} + +func amd64FMA3RoundingMetadata(rounding string) string { + switch rounding { + case "RD_SAE": + return "round.downward" + case "RU_SAE": + return "round.upward" + case "RZ_SAE": + return "round.towardzero" + default: + return "round.tonearest" + } +} diff --git a/amd64_lower_four_source.go b/amd64_lower_four_source.go new file mode 100644 index 00000000..416f66b9 --- /dev/null +++ b/amd64_lower_four_source.go @@ -0,0 +1,343 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64FourSourceMode uint8 + +const ( + amd64FourSourceFMA amd64FourSourceMode = iota + amd64FourSourceDotWords +) + +type amd64FourSourceSpec struct { + mode amd64FourSourceMode + scalar bool + negative bool + saturating bool +} + +// amd64FourSourceSpecs is the complete Go 1.27 AVX512_4FMAPS/AVX512_4VNNIW +// grammar. The opcode table records only semantic axes; memory, a consecutive +// four-register range, optional K mask, zeroing, and architecture rules are +// parsed once below. +var amd64FourSourceSpecs = map[Op]amd64FourSourceSpec{ + "V4FMADDPS": {mode: amd64FourSourceFMA}, + "V4FMADDSS": {mode: amd64FourSourceFMA, scalar: true}, + "V4FNMADDPS": {mode: amd64FourSourceFMA, negative: true}, + "V4FNMADDSS": {mode: amd64FourSourceFMA, scalar: true, negative: true}, + "VP4DPWSSD": {mode: amd64FourSourceDotWords}, + "VP4DPWSSDS": {mode: amd64FourSourceDotWords, saturating: true}, +} + +type amd64FourSourceForm struct { + memory Operand + sourceBase int + destination Operand + mask string + zeroing bool +} + +func (c *amd64Ctx) lowerFourSource(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64FourSourceSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + form, err := c.parseFourSourceForm(baseOp, suffix, spec, ins) + if err != nil { + return true, false, err + } + if spec.mode == amd64FourSourceFMA { + return c.lowerFourSourceFMA(spec, form) + } + return c.lowerFourSourceDotWords(spec, form) +} + +func (c *amd64Ctx) parseFourSourceForm(baseOp, suffix string, spec amd64FourSourceSpec, ins Instr) (amd64FourSourceForm, error) { + var form amd64FourSourceForm + if suffix != "" && suffix != "Z" { + return form, fmt.Errorf("%s %s has a suffix absent from Go 1.27's four-source tables: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return form, fmt.Errorf("%s %s expects memory, four-register range, [K1-K7,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return form, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if suffix == "Z" && !masked { + return form, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if !isAMD64MemoryOperand(ins.Args[0]) { + return form, fmt.Errorf("%s %s first source must be 16-byte memory: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpMem && !x86MemoryRegistersValidForArch(ins.Args[0].Mem, c.goarch) { + return form, fmt.Errorf("%s %s memory source uses an out-of-range address register: %q", c.goarch, baseOp, ins.Raw) + } + + width := 64 + if spec.scalar { + width = 16 + } + rangeOperand := ins.Args[1] + if rangeOperand.Kind != OpRegList || !rangeOperand.RegListRange || len(rangeOperand.RegList) != 4 { + return form, fmt.Errorf("%s %s second source must be one consecutive four-register range: %q", c.goarch, baseOp, ins.Raw) + } + first := -1 + for index, register := range rangeOperand.RegList { + registerIndex, valid := amd64VectorRegisterIndex(register, width) + if !valid || c.goarch == "386" && registerIndex >= 8 || index != 0 && registerIndex != first+index { + return form, fmt.Errorf("%s %s source range is outside Go 1.27's four-register class: %q", c.goarch, baseOp, ins.Raw) + } + if index == 0 { + first = registerIndex + } + } + + destination := ins.Args[len(ins.Args)-1] + destinationIndex, valid := amd64VectorRegisterIndex(destination.Reg, width) + if destination.Kind != OpReg || !valid || c.goarch == "386" && destinationIndex >= 8 { + return form, fmt.Errorf("%s %s destination must be an in-range %s register: %q", c.goarch, baseOp, map[bool]string{true: "X", false: "Z"}[spec.scalar], ins.Raw) + } + mask := "" + if masked { + if !amd64NonzeroKOperand(ins.Args[2]) { + return form, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + loadedMask, loadErr := c.loadK(ins.Args[2].Reg) + if loadErr != nil { + return form, loadErr + } + mask = loadedMask + } + + // The hardware ignores the low two encoded source-register bits. Preserve + // that behavior for Go spellings such as [Z10-Z13], which the assembler + // accepts even though the architectural block begins at Z8. + return amd64FourSourceForm{ + memory: ins.Args[0], sourceBase: first &^ 3, destination: destination, + mask: mask, zeroing: suffix == "Z", + }, nil +} + +func (c *amd64Ctx) lowerFourSourceFMA(spec amd64FourSourceSpec, form amd64FourSourceForm) (bool, bool, error) { + activeMaskBits := 16 + if spec.scalar { + activeMaskBits = 1 + } + memoryBits, err := c.loadFourSourceMemoryI32(form, activeMaskBits) + if err != nil { + return true, false, err + } + memoryName := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %s to <4 x float>\n", memoryName, memoryBits) + memory := "%" + memoryName + if spec.scalar { + return c.lowerFourSourceScalarFMA(spec, form, memory) + } + + accumulator, err := c.loadFloatingVectorOperand(form.destination, 64, 16, 32) + if err != nil { + return true, false, err + } + original := accumulator + for sourceIndex := 0; sourceIndex < 4; sourceIndex++ { + sourceReg := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("Z%d", form.sourceBase+sourceIndex))} + source, loadErr := c.loadFloatingVectorOperand(sourceReg, 64, 16, 32) + if loadErr != nil { + return true, false, loadErr + } + factor := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x float> %s, i32 %d\n", factor, memory, sourceIndex) + factors := c.splatFMA3Scalar(16, 32, "%"+factor) + if spec.negative { + negated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg <16 x float> %s\n", negated, source) + source = "%" + negated + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <16 x float> @llvm.fma.v16f32(<16 x float> %s, <16 x float> %s, <16 x float> %s)\n", result, source, factors, accumulator) + accumulator = "%" + result + } + if form.mask != "" { + computedBits := c.newTmp() + originalBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x float> %s to <16 x i32>\n", computedBits, accumulator) + fmt.Fprintf(c.b, " %%%s = bitcast <16 x float> %s to <16 x i32>\n", originalBits, original) + masked := amd64ApplyI32LaneMask(c, 16, "%"+computedBits, "%"+originalBits, form.mask, form.zeroing) + back := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i32> %s to <16 x float>\n", back, masked) + accumulator = "%" + back + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x float> %s to <64 x i8>\n", out, accumulator) + return true, false, c.storeZ(form.destination.Reg, "%"+out) +} + +func (c *amd64Ctx) lowerFourSourceScalarFMA(spec amd64FourSourceSpec, form amd64FourSourceForm, memory string) (bool, bool, error) { + accumulator, err := c.loadXLowF32(form.destination.Reg) + if err != nil { + return true, false, err + } + original := accumulator + for sourceIndex := 0; sourceIndex < 4; sourceIndex++ { + sourceReg := Reg(fmt.Sprintf("X%d", form.sourceBase+sourceIndex)) + source, loadErr := c.loadXLowF32(sourceReg) + if loadErr != nil { + return true, false, loadErr + } + if spec.negative { + negated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg float %s\n", negated, source) + source = "%" + negated + } + factor := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x float> %s, i32 %d\n", factor, memory, sourceIndex) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call float @llvm.fma.f32(float %s, float %%%s, float %s)\n", result, source, factor, accumulator) + accumulator = "%" + result + } + if form.mask != "" { + bit := amd64MaskBitI1(c, form.mask, 0) + fallback := original + if form.zeroing { + fallback = "0.000000e+00" + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, float %s, float %s\n", selected, bit, accumulator, fallback) + accumulator = "%" + selected + } + destination, err := c.loadX(form.destination.Reg) + if err != nil { + return true, false, err + } + words := c.newTmp() + bits := c.newTmp() + inserted := c.newTmp() + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", words, destination) + fmt.Fprintf(c.b, " %%%s = bitcast float %s to i32\n", bits, accumulator) + fmt.Fprintf(c.b, " %%%s = insertelement <4 x i32> %%%s, i32 %%%s, i32 0\n", inserted, words, bits) + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %%%s to <16 x i8>\n", out, inserted) + return true, false, c.storeX(form.destination.Reg, "%"+out) +} + +func (c *amd64Ctx) lowerFourSourceDotWords(spec amd64FourSourceSpec, form amd64FourSourceForm) (bool, bool, error) { + memoryDwords, err := c.loadFourSourceMemoryI32(form, 16) + if err != nil { + return true, false, err + } + memoryName := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %s to <8 x i16>\n", memoryName, memoryDwords) + memory := "%" + memoryName + destinationBytes, err := c.loadZ(form.destination.Reg) + if err != nil { + return true, false, err + } + original := c.bitcastVectorBytesToIntegerLanes(64, 16, 32, destinationBytes) + accumulator := original + for sourceIndex := 0; sourceIndex < 4; sourceIndex++ { + sourceReg := Reg(fmt.Sprintf("Z%d", form.sourceBase+sourceIndex)) + sourceBytes, loadErr := c.loadZ(sourceReg) + if loadErr != nil { + return true, false, loadErr + } + source := c.bitcastVectorBytesToIntegerLanes(64, 32, 16, sourceBytes) + accumulator = c.emitFourSourceDotStep(accumulator, source, memory, sourceIndex, spec.saturating) + } + if form.mask != "" { + accumulator = amd64ApplyI32LaneMask(c, 16, accumulator, original, form.mask, form.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i32> %s to <64 x i8>\n", out, accumulator) + return true, false, c.storeZ(form.destination.Reg, "%"+out) +} + +func (c *amd64Ctx) loadFourSourceMemoryI32(form amd64FourSourceForm, activeMaskBits int) (string, error) { + if form.mask == "" { + bytes, err := c.loadPackedCompareBytes(form.memory, 16) + if err != nil { + return "", err + } + return c.bitcastVectorBytesToIntegerLanes(16, 4, 32, bytes), nil + } + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %d\n", masked, form.mask, (uint64(1)< poison, i1 %%%s, i32 0\n", seed, active) + fmt.Fprintf(c.b, " %%%s = shufflevector <4 x i1> %%%s, <4 x i1> poison, <4 x i32> zeroinitializer\n", predicate, seed) + pointer, pointerType, intrinsicSuffix, err := c.packedVectorMemoryPointer(form.memory) + if err != nil { + return "", err + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <4 x i32> @llvm.masked.load.v4i32%s(%s align 1 %s, <4 x i1> %%%s, <4 x i32> zeroinitializer)\n", + loaded, intrinsicSuffix, pointerType, pointer, predicate) + return "%" + loaded, nil +} + +func (c *amd64Ctx) emitFourSourceDotStep(accumulator, source, memory string, sourceIndex int, saturating bool) string { + result := "poison" + for lane := 0; lane < 16; lane++ { + accumulatorLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <16 x i32> %s, i32 %d\n", accumulatorLane, accumulator, lane) + total := "" + if saturating { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext i32 %%%s to i64\n", wide, accumulatorLane) + total = "%" + wide + } else { + total = "%" + accumulatorLane + } + for word := 0; word < 2; word++ { + sourceLane := c.newTmp() + memoryLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <32 x i16> %s, i32 %d\n", sourceLane, source, lane*2+word) + fmt.Fprintf(c.b, " %%%s = extractelement <8 x i16> %s, i32 %d\n", memoryLane, memory, sourceIndex*2+word) + wideSource := c.newTmp() + wideMemory := c.newTmp() + bits := 32 + if saturating { + bits = 64 + } + fmt.Fprintf(c.b, " %%%s = sext i16 %%%s to i%d\n", wideSource, sourceLane, bits) + fmt.Fprintf(c.b, " %%%s = sext i16 %%%s to i%d\n", wideMemory, memoryLane, bits) + product := c.newTmp() + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i%d %%%s, %%%s\n", product, bits, wideSource, wideMemory) + fmt.Fprintf(c.b, " %%%s = add i%d %s, %%%s\n", next, bits, total, product) + total = "%" + next + } + if saturating { + total = c.saturateFourSourceI64ToI32(total) + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <16 x i32> %s, i32 %s, i32 %d\n", inserted, result, total, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) saturateFourSourceI64ToI32(value string) string { + above := c.newTmp() + capped := c.newTmp() + below := c.newTmp() + bounded := c.newTmp() + narrowed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp sgt i64 %s, 2147483647\n", above, value) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 2147483647, i64 %s\n", capped, above, value) + fmt.Fprintf(c.b, " %%%s = icmp slt i64 %%%s, -2147483648\n", below, capped) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 -2147483648, i64 %%%s\n", bounded, below, capped) + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", narrowed, bounded) + return "%" + narrowed +} diff --git a/amd64_lower_four_source_test.go b/amd64_lower_four_source_test.go new file mode 100644 index 00000000..0448085a --- /dev/null +++ b/amd64_lower_four_source_test.go @@ -0,0 +1,242 @@ +package plan9asm + +import ( + "runtime" + "sort" + "strings" + "testing" +) + +func TestAMD64FourSourceGrammarIsComplete(t *testing.T) { + got := make([]string, 0, len(amd64FourSourceSpecs)) + for op := range amd64FourSourceSpecs { + got = append(got, string(op)) + } + sort.Strings(got) + want := []string{"V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VP4DPWSSD", "VP4DPWSSDS"} + if strings.Join(got, ",") != strings.Join(want, ",") { + t.Fatalf("four-source grammar opcodes = %v, want %v", got, want) + } +} + +func TestTranslateX86FourSourceCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := `TEXT foursourceforms(SB),$0-0 + V4FMADDPS (BX), [Z0-Z3], Z4 + V4FNMADDPS 32(BX), [Z0-Z3], Z5 + V4FMADDSS 64(BX), [X0-X3], X4 + V4FNMADDSS 96(BX), [X0-X3], X5 + VP4DPWSSD 128(BX), [Z0-Z3], Z6 + VP4DPWSSDS 160(BX), [Z0-Z3], Z7 +` + if target.goarch == "amd64" { + source += ` V4FMADDPS 8(BX), [Z2-Z5], K7, Z4 + V4FMADDPS.Z 16(BX), [Z2-Z5], K1, Z4 + V4FNMADDPS 40(BX), [Z2-Z5], K7, Z5 + V4FNMADDPS.Z 48(BX), [Z2-Z5], K2, Z5 + V4FMADDSS 72(BX), [X2-X5], K7, X4 + V4FMADDSS.Z 80(BX), [X2-X5], K3, X4 + V4FNMADDSS 104(BX), [X2-X5], K7, X5 + V4FNMADDSS.Z 112(BX), [X2-X5], K4, X5 + VP4DPWSSD 136(BX), [Z2-Z5], K7, Z6 + VP4DPWSSD.Z 144(BX), [Z2-Z5], K5, Z6 + VP4DPWSSDS 168(BX), [Z2-Z5], K7, Z7 + VP4DPWSSDS.Z 176(BX), [Z2-Z5], K6, Z7 +` + } + source += "\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"foursourceforms": {Name: "foursourceforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "four-source-"+target.name+".ll", "four-source-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86FourSourceRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "V4FMADDPS Z0, [Z0-Z3], Z4"}, + {goarch: "amd64", instruction: "V4FMADDPS (AX), [Z0-Z2], Z4"}, + {goarch: "amd64", instruction: "V4FMADDPS (AX), [Z0,Z1,Z2,Z3], Z4"}, + {goarch: "amd64", instruction: "V4FMADDPS (AX), [X0-X3], Z4"}, + {goarch: "amd64", instruction: "V4FMADDPS (AX), [Z0-Z3], K0, Z4"}, + {goarch: "amd64", instruction: "V4FMADDPS.Z (AX), [Z0-Z3], Z4"}, + {goarch: "amd64", instruction: "V4FMADDPS.BCST (AX), [Z0-Z3], Z4"}, + {goarch: "amd64", instruction: "V4FMADDSS (AX), [X0-X3], Z4"}, + {goarch: "amd64", instruction: "VP4DPWSSD (AX), [Z0-Z3], X4"}, + {goarch: "386", instruction: "VP4DPWSSD (AX), [Z6-Z9], Z4"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "$", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's four-source tables", test.instruction) + } + }) + } +} + +func TestAMD64FourSourceRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT foursourcesemantics(SB),NOSPLIT,$0-24 + MOVQ in+0(FP), AX + MOVQ out+8(FP), BX + MOVQ mask+16(FP), CX + VBROADCASTSS 0(AX), Z0 + VBROADCASTSS 16(AX), Z1 + VBROADCASTSS 32(AX), Z2 + VBROADCASTSS 48(AX), Z3 + VBROADCASTSS 64(AX), Z4 + V4FMADDPS 128(AX), [Z2-Z5], Z4 + VMOVUPS Z4, 0(BX) + VBROADCASTSS 64(AX), Z5 + KMOVQ CX, K1 + V4FNMADDPS.Z 128(AX), [Z0-Z3], K1, Z5 + VMOVUPS Z5, 64(BX) + MOVUPS 0(AX), X0 + MOVUPS 16(AX), X1 + MOVUPS 32(AX), X2 + MOVUPS 48(AX), X3 + MOVUPS 64(AX), X6 + V4FMADDSS 128(AX), [X0-X3], X6 + MOVUPS X6, 128(BX) + VMOVDQU64 192(AX), Z0 + VMOVDQU64 256(AX), Z1 + VMOVDQU64 320(AX), Z2 + VMOVDQU64 384(AX), Z3 + VMOVDQU64 448(AX), Z7 + VP4DPWSSD 144(AX), [Z0-Z3], Z7 + VMOVDQU64 Z7, 144(BX) + VMOVDQU64 448(AX), Z7 + VP4DPWSSDS 144(AX), [Z0-Z3], Z7 + VMOVDQU64 Z7, 208(BX) + RET + +TEXT foursourcefaultsuppression(SB),NOSPLIT,$0-24 + MOVQ memory+0(FP), AX + MOVQ out+8(FP), BX + MOVQ mask+16(FP), CX + KMOVQ CX, K1 + V4FMADDPS.Z (AX), [Z0-Z3], K1, Z4 + VMOVUPS Z4, 0(BX) + V4FMADDSS.Z (AX), [X0-X3], K1, X4 + MOVUPS X4, 64(BX) + VP4DPWSSD.Z (AX), [Z0-Z3], K1, Z5 + VMOVUPS Z5, 80(BX) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{ + "foursourcesemantics": { + Name: "foursourcesemantics", Args: []LLVMType{Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }, + "foursourcefaultsuppression": { + Name: "foursourcefaultsuppression", Args: []LLVMType{Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +#include +extern void foursourcesemantics(void *, void *, uint64_t); +extern void foursourcefaultsuppression(void *, void *, uint64_t); +static void putf(uint8_t *p, float v) { memcpy(p, &v, 4); } +static float getf(const uint8_t *p) { float v; memcpy(&v, p, 4); return v; } +static void put16(uint8_t *p, int16_t v) { memcpy(p, &v, 2); } +static void put32(uint8_t *p, int32_t v) { memcpy(p, &v, 4); } +static int32_t get32(const uint8_t *p) { int32_t v; memcpy(&v, p, 4); return v; } +int main(void) { + uint8_t in[512] = {0}, out[272] = {0}, faultOut[144] = {1}; + for (int r=0;r<4;r++) for (int lane=0;lane<4;lane++) putf(in+r*16+lane*4, (float)(r+1)); + for (int lane=0;lane<4;lane++) putf(in+64+lane*4, 10.0f+(float)lane); + putf(in+128, 1); putf(in+132, 2); putf(in+136, 3); putf(in+140, 4); + for (int r=0;r<4;r++) for (int lane=0;lane<32;lane++) put16(in+192+r*64+lane*2, (int16_t)(r+1)); + put16(in+144, 1); put16(in+146, 2); put16(in+148, 3); put16(in+150, 4); + put16(in+152, 5); put16(in+154, 6); put16(in+156, 7); put16(in+158, 8); + for (int lane=0;lane<16;lane++) put32(in+448+lane*4, lane==0 ? INT_MAX-5 : lane); + foursourcesemantics(in, out, 5); + foursourcefaultsuppression(0, faultOut, 0); + if (getf(out) != 40 || getf(out+4) != 40 || getf(out+8) != 40 || getf(out+12) != 40) return 10; + if (getf(out+64) != -20) return 21; + if (getf(out+68) != 0) return 22; + if (getf(out+72) != -20) return 23; + if (getf(out+76) != 0) return 24; + if (getf(out+128) != 40 || getf(out+132) != 11 || getf(out+136) != 12 || getf(out+140) != 13) return 12; + if (get32(out+144) != INT_MIN+104 || get32(out+148) != 111) return 13; + if (get32(out+208) != INT_MAX || get32(out+212) != 111) return 14; + for (int i=0;i<144;i++) if (faultOut[i] != 0) return 15; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "four_source_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_fp.go b/amd64_lower_fp.go index 58f7fdf0..751a3aa2 100644 --- a/amd64_lower_fp.go +++ b/amd64_lower_fp.go @@ -7,50 +7,360 @@ import ( ) func (c *amd64Ctx) lowerFP(op Op, ins Instr) (ok bool, terminated bool, err error) { + if ok, term, err := c.lowerApproximateMath(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerFixupImmediate(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerScaledRound(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerGetMant(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerGetExp(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerFPClass(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerFloatingRange(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerReciprocal14(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerReciprocalEstimate(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerRound(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerScalarFloatToInteger(op, ins); ok { + return ok, term, err + } + if raw := strings.ToUpper(string(op)); raw != "" { + base := raw + if dot := strings.IndexByte(raw, '.'); dot >= 0 { + base = raw[:dot] + } + if _, recognized := amd64HorizontalFloatingSpecs[Op(base)]; recognized { + return c.lowerHorizontalFloating(op, ins) + } + } + if raw := strings.ToUpper(string(op)); raw != "" { + base := raw + if dot := strings.IndexByte(raw, '.'); dot >= 0 { + base = raw[:dot] + } + if _, recognized := amd64BinaryFloatingSpecs[Op(base)]; recognized { + return c.lowerBinaryFloating(op, ins) + } + } + if raw := strings.ToUpper(string(op)); raw != "" { + base := raw + if dot := strings.IndexByte(raw, '.'); dot >= 0 { + base = raw[:dot] + } + if _, recognized := amd64FMA3Specs[Op(base)]; recognized { + return c.lowerFMA3(op, ins) + } + } + if raw := strings.ToUpper(string(op)); raw != "" { + base := raw + if dot := strings.IndexByte(raw, '.'); dot >= 0 { + base = raw[:dot] + } + if _, recognized := amd64PackedFloatingLogicalSpecs[Op(base)]; recognized { + return c.lowerPackedFloatingLogical(op, ins) + } + } + if raw := strings.ToUpper(string(op)); raw != "" { + base := raw + if dot := strings.IndexByte(raw, '.'); dot >= 0 { + base = raw[:dot] + } + if base == "VCVTSS2SD" || base == "VCVTSD2SS" { + return c.lowerVEXScalarFloatConvert(op, ins) + } + } switch op { - case "MOVSD", "MOVAPD", "ANDPD", "ANDNPD", "ORPD", "XORPS", + case "MOVSS", "MOVSD", "MOVAPD", "MOVUPD", + "ADDSS", "SUBSS", "MULSS", "DIVSS", "MAXSS", "MINSS", "SQRTSS", + "ADDPS", "SUBPS", "MULPS", "DIVPS", "MAXPS", "MINPS", + "ADDPD", "SUBPD", "MULPD", "DIVPD", "MAXPD", "MINPD", + "SQRTPS", "SQRTPD", + "MOVLHPS", "MOVHLPS", "MOVLPS", "MOVHPS", "MOVLPD", "MOVHPD", + "VMOVLPS", "VMOVHPS", "VMOVLPD", "VMOVHPD", "SHUFPD", "UNPCKLPS", "UNPCKHPD", "ADDSD", "SUBSD", "MULSD", "DIVSD", "MAXSD", "MINSD", "SQRTSD", - "COMISD", "CMPSD", "VADDSD", "VFMADD213SD", "VFNMADD231SD", - "CVTSD2SL", "CVTSL2SD", "CVTSQ2SD", "CVTTSD2SQ": + "COMISS", "UCOMISS", "COMISD", "UCOMISD", "CMPSD", + "CVTSS2SD", "VCVTSS2SD", "CVTSD2SS", "VCVTSD2SS", "CVTSL2SD", "CVTSQ2SD": // handled below default: return false, false, nil } switch op { - case "MOVAPD", "ANDPD", "ANDNPD", "ORPD", "XORPS": + case "VCVTSS2SD": + return c.lowerVEXScalarFloatConvert(op, ins) + + case "VCVTSD2SS": + return c.lowerVEXScalarFloatConvert(op, ins) + + case "MOVAPD", "MOVUPD": + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("amd64 %s expects src, dst: %q", op, ins.Raw) + } + if ins.Args[1].Kind == OpReg { + if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { + return false, false, nil + } + srcv, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + return true, false, c.storeX(ins.Args[1].Reg, srcv) + } + if ins.Args[0].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s store expects X source: %q", op, ins.Raw) + } + srcv, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + if err := c.storeXVecOperand(ins.Args[1], srcv); err != nil { + return true, false, fmt.Errorf("amd64 %s unsupported destination %s: %w", op, ins.Args[1].String(), err) + } + return true, false, nil + + case "MOVSS": + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("amd64 MOVSS expects src, dst: %q", ins.Raw) + } + v, err := c.evalF32(ins.Args[0]) + if err != nil { + return true, false, err + } + switch ins.Args[1].Kind { + case OpReg: + if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { + return true, false, fmt.Errorf("amd64 MOVSS expects X-reg destination: %q", ins.Raw) + } + if ins.Args[0].Kind == OpReg { + return true, false, c.storeXLowF32(ins.Args[1].Reg, v) + } + return true, false, c.storeXLowF32ClearingUpper(ins.Args[1].Reg, v) + case OpFP: + return true, false, c.storeFPResult(ins.Args[1].FPOffset, LLVMType("float"), v) + case OpMem: + addr, err := c.addrFromMem(ins.Args[1].Mem) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store float %s, ptr %s, align 1\n", v, c.ptrFromAddrI64(addr)) + return true, false, nil + case OpSym: + p, err := c.ptrFromSB(ins.Args[1].Sym) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store float %s, ptr %s, align 1\n", v, p) + return true, false, nil + default: + return true, false, fmt.Errorf("amd64 MOVSS unsupported destination: %q", ins.Raw) + } + + case "ADDSS", "SUBSS", "MULSS", "DIVSS", "MAXSS", "MINSS": if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { return true, false, fmt.Errorf("amd64 %s expects src, Xdst: %q", op, ins.Raw) } if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { return false, false, nil } - dst := ins.Args[1].Reg - srcv, err := c.loadXVecOperand(ins.Args[0]) + src, err := c.evalF32(ins.Args[0]) if err != nil { return true, false, err } - if op == "MOVAPD" { - return true, false, c.storeX(dst, srcv) - } - dstv, err := c.loadX(dst) + dst, err := c.loadXLowF32(ins.Args[1].Reg) if err != nil { return true, false, err } - t := c.newTmp() + value := c.newTmp() switch op { - case "ANDPD": - fmt.Fprintf(c.b, " %%%s = and <16 x i8> %s, %s\n", t, dstv, srcv) - case "ORPD": - fmt.Fprintf(c.b, " %%%s = or <16 x i8> %s, %s\n", t, dstv, srcv) - case "XORPS": - fmt.Fprintf(c.b, " %%%s = xor <16 x i8> %s, %s\n", t, dstv, srcv) - case "ANDNPD": - notv := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor <16 x i8> %s, %s\n", notv, dstv, llvmAllOnesI8Vec(16)) - fmt.Fprintf(c.b, " %%%s = and <16 x i8> %%%s, %s\n", t, notv, srcv) - } - return true, false, c.storeX(dst, "%"+t) + case "ADDSS": + fmt.Fprintf(c.b, " %%%s = fadd float %s, %s\n", value, dst, src) + case "SUBSS": + fmt.Fprintf(c.b, " %%%s = fsub float %s, %s\n", value, dst, src) + case "MULSS": + fmt.Fprintf(c.b, " %%%s = fmul float %s, %s\n", value, dst, src) + case "DIVSS": + fmt.Fprintf(c.b, " %%%s = fdiv float %s, %s\n", value, dst, src) + case "MAXSS", "MINSS": + cmp := c.newTmp() + pred := "ogt" + if op == "MINSS" { + pred = "olt" + } + fmt.Fprintf(c.b, " %%%s = fcmp %s float %s, %s\n", cmp, pred, dst, src) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, float %s, float %s\n", value, cmp, dst, src) + } + return true, false, c.storeXLowF32(ins.Args[1].Reg, "%"+value) + + case "SQRTSS": + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 SQRTSS expects src, Xdst: %q", ins.Raw) + } + if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { + return false, false, nil + } + src, err := c.evalF32(ins.Args[0]) + if err != nil { + return true, false, err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call float @llvm.sqrt.f32(float %s)\n", value, src) + return true, false, c.storeXLowF32(ins.Args[1].Reg, "%"+value) + + case "ADDPS", "SUBPS", "MULPS", "DIVPS", "MAXPS", "MINPS", + "ADDPD", "SUBPD", "MULPD", "DIVPD", "MAXPD", "MINPD": + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects src, Xdst: %q", op, ins.Raw) + } + if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { + return false, false, nil + } + vectorType := "<4 x float>" + if strings.HasSuffix(string(op), "PD") { + vectorType = "<2 x double>" + } + src, err := c.loadXTypedVectorOperand(ins.Args[0], vectorType) + if err != nil { + return true, false, err + } + dst, err := c.loadXTypedVectorOperand(ins.Args[1], vectorType) + if err != nil { + return true, false, err + } + value := c.newTmp() + switch { + case strings.HasPrefix(string(op), "ADD"): + fmt.Fprintf(c.b, " %%%s = fadd %s %s, %s\n", value, vectorType, dst, src) + case strings.HasPrefix(string(op), "SUB"): + fmt.Fprintf(c.b, " %%%s = fsub %s %s, %s\n", value, vectorType, dst, src) + case strings.HasPrefix(string(op), "MUL"): + fmt.Fprintf(c.b, " %%%s = fmul %s %s, %s\n", value, vectorType, dst, src) + case strings.HasPrefix(string(op), "DIV"): + fmt.Fprintf(c.b, " %%%s = fdiv %s %s, %s\n", value, vectorType, dst, src) + default: + cmp := c.newTmp() + pred := "ogt" + if strings.HasPrefix(string(op), "MIN") { + pred = "olt" + } + lanes := 4 + if vectorType == "<2 x double>" { + lanes = 2 + } + fmt.Fprintf(c.b, " %%%s = fcmp %s %s %s, %s\n", cmp, pred, vectorType, dst, src) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %s\n", value, lanes, cmp, vectorType, dst, vectorType, src) + } + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", bytesValue, vectorType, value) + return true, false, c.storeX(ins.Args[1].Reg, "%"+bytesValue) + + case "SQRTPS", "SQRTPD": + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects src, Xdst: %q", op, ins.Raw) + } + if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { + return false, false, nil + } + vectorType := "<4 x float>" + intrinsic := "@llvm.sqrt.v4f32" + if op == "SQRTPD" { + vectorType = "<2 x double>" + intrinsic = "@llvm.sqrt.v2f64" + } + src, err := c.loadXTypedVectorOperand(ins.Args[0], vectorType) + if err != nil { + return true, false, err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s %s(%s %s)\n", value, vectorType, intrinsic, vectorType, src) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", bytesValue, vectorType, value) + return true, false, c.storeX(ins.Args[1].Reg, "%"+bytesValue) + + case "MOVLHPS", "MOVHLPS": + if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects Xsrc, Xdst: %q", op, ins.Raw) + } + src, err := c.loadXAsI64x2(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + dst, err := c.loadXAsI64x2(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + mask := "" + if op == "MOVHLPS" { + mask = "" + } + shuffled := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <2 x i64> %s, <2 x i64> %s, <2 x i32> %s\n", shuffled, dst, src, mask) + return true, false, c.storeXFromI64x2(ins.Args[1].Reg, "%"+shuffled) + + case "MOVLPS", "MOVHPS", "MOVLPD", "MOVHPD", "VMOVLPS", "VMOVHPS", "VMOVLPD", "VMOVHPD": + return c.lowerMOVHalf(op, ins) + + case "SHUFPD": + if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("amd64 SHUFPD expects $imm, Xsrc, Xdst: %q", ins.Raw) + } + src, err := c.loadXAsI64x2(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + dst, err := c.loadXAsI64x2(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + lo := ins.Args[0].Imm & 1 + hi := 2 + ((ins.Args[0].Imm >> 1) & 1) + shuffled := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <2 x i64> %s, <2 x i64> %s, <2 x i32> \n", shuffled, dst, src, lo, hi) + return true, false, c.storeXFromI64x2(ins.Args[2].Reg, "%"+shuffled) + + case "UNPCKLPS", "UNPCKHPD": + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects src, Xdst: %q", op, ins.Raw) + } + if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { + return false, false, nil + } + vectorType := "<4 x float>" + maskType := "<4 x i32>" + mask := "" + if op == "UNPCKHPD" { + vectorType = "<2 x double>" + maskType = "<2 x i32>" + mask = "" + } + src, err := c.loadXTypedVectorOperand(ins.Args[0], vectorType) + if err != nil { + return true, false, err + } + dst, err := c.loadXTypedVectorOperand(ins.Args[1], vectorType) + if err != nil { + return true, false, err + } + shuffled := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector %s %s, %s %s, %s %s\n", shuffled, vectorType, dst, vectorType, src, maskType, mask) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", bytesValue, vectorType, shuffled) + return true, false, c.storeX(ins.Args[1].Reg, "%"+bytesValue) case "MOVSD": if len(ins.Args) != 2 { @@ -138,7 +448,22 @@ func (c *amd64Ctx) lowerFP(op Op, ins Instr) (ok bool, terminated bool, err erro fmt.Fprintf(c.b, " %%%s = call double @llvm.sqrt.f64(double %s)\n", t, src) return true, false, c.storeXLowF64(ins.Args[1].Reg, "%"+t) - case "COMISD": + case "COMISS", "UCOMISS": + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("amd64 %s expects src, dst: %q", op, ins.Raw) + } + src, err := c.evalF32(ins.Args[0]) + if err != nil { + return true, false, err + } + dst, err := c.evalF32(ins.Args[1]) + if err != nil { + return true, false, err + } + c.setScalarFloatCompareFlags(LLVMType("float"), dst, src) + return true, false, nil + + case "COMISD", "UCOMISD": if len(ins.Args) != 2 { return true, false, fmt.Errorf("amd64 COMISD expects src, dst: %q", ins.Raw) } @@ -150,15 +475,7 @@ func (c *amd64Ctx) lowerFP(op Op, ins Instr) (ok bool, terminated bool, err erro if err != nil { return true, false, err } - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fcmp ueq double %s, %s\n", z, dst, src) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", z, c.flagsZSlot) - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fcmp ult double %s, %s\n", cf, dst, src) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCFSlot) - lt := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fcmp olt double %s, %s\n", lt, dst, src) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", lt, c.flagsSltSlot) + c.setScalarFloatCompareFlags(LLVMType("double"), dst, src) return true, false, nil case "CMPSD": @@ -213,17 +530,35 @@ func (c *amd64Ctx) lowerFP(op Op, ins Instr) (ok bool, terminated bool, err erro fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 -1, i64 0\n", mask, cmp) return true, false, c.storeXLowI64(ins.Args[1].Reg, "%"+mask) - case "CVTTSD2SQ": + case "CVTSS2SD": if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 CVTTSD2SQ expects src, dstReg: %q", ins.Raw) + return true, false, fmt.Errorf("amd64 CVTSS2SD expects src, Xdst: %q", ins.Raw) + } + if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { + return false, false, nil + } + src, err := c.evalF32(ins.Args[0]) + if err != nil { + return true, false, err + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fpext float %s to double\n", converted, src) + return true, false, c.storeXLowF64(ins.Args[1].Reg, "%"+converted) + + case "CVTSD2SS": + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 CVTSD2SS expects src, Xdst: %q", ins.Raw) + } + if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { + return false, false, nil } src, err := c.evalF64(ins.Args[0]) if err != nil { return true, false, err } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fptosi double %s to i64\n", t, src) - return true, false, c.storeReg(ins.Args[1].Reg, "%"+t) + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fptrunc double %s to float\n", converted, src) + return true, false, c.storeXLowF32(ins.Args[1].Reg, "%"+converted) case "CVTSQ2SD": if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { @@ -240,22 +575,6 @@ func (c *amd64Ctx) lowerFP(op Op, ins Instr) (ok bool, terminated bool, err erro fmt.Fprintf(c.b, " %%%s = sitofp i64 %s to double\n", t, src) return true, false, c.storeXLowF64(ins.Args[1].Reg, "%"+t) - case "CVTSD2SL": - if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 CVTSD2SL expects src, dstReg: %q", ins.Raw) - } - src, err := c.evalF64(ins.Args[0]) - if err != nil { - return true, false, err - } - round := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call double @llvm.rint.f64(double %s)\n", round, src) - i32v := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fptosi double %%%s to i32\n", i32v, round) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, i32v) - return true, false, c.storeReg(ins.Args[1].Reg, "%"+z) - case "CVTSL2SD": if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { return true, false, fmt.Errorf("amd64 CVTSL2SD expects srcReg, Xdst: %q", ins.Raw) @@ -273,76 +592,6 @@ func (c *amd64Ctx) lowerFP(op Op, ins Instr) (ok bool, terminated bool, err erro fmt.Fprintf(c.b, " %%%s = sitofp i32 %%%s to double\n", t, i32v) return true, false, c.storeXLowF64(ins.Args[1].Reg, "%"+t) - case "VADDSD": - if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VADDSD expects src1, src2, Xdst: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - s1, err := c.evalF64(ins.Args[0]) - if err != nil { - return true, false, err - } - s2, err := c.evalF64(ins.Args[1]) - if err != nil { - return true, false, err - } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fadd double %s, %s\n", t, s2, s1) - return true, false, c.storeXLowF64(ins.Args[2].Reg, "%"+t) - - case "VFMADD213SD": - if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VFMADD213SD expects src1, src2, Xdst: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - s1, err := c.evalF64(ins.Args[0]) - if err != nil { - return true, false, err - } - s2, err := c.evalF64(ins.Args[1]) - if err != nil { - return true, false, err - } - dst, err := c.loadXLowF64(ins.Args[2].Reg) - if err != nil { - return true, false, err - } - mul := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fmul double %s, %s\n", mul, dst, s2) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fadd double %%%s, %s\n", t, mul, s1) - return true, false, c.storeXLowF64(ins.Args[2].Reg, "%"+t) - - case "VFNMADD231SD": - if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VFNMADD231SD expects src1, src2, Xdst: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - s1, err := c.evalF64(ins.Args[0]) - if err != nil { - return true, false, err - } - s2, err := c.evalF64(ins.Args[1]) - if err != nil { - return true, false, err - } - dst, err := c.loadXLowF64(ins.Args[2].Reg) - if err != nil { - return true, false, err - } - mul := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fmul double %s, %s\n", mul, s1, s2) - neg := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fneg double %%%s\n", neg, mul) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fadd double %%%s, %s\n", t, neg, dst) - return true, false, c.storeXLowF64(ins.Args[2].Reg, "%"+t) } return false, false, nil } @@ -371,11 +620,64 @@ func (c *amd64Ctx) loadXVecOperand(op Operand) (string, error) { t := c.newTmp() fmt.Fprintf(c.b, " %%%s = load <16 x i8>, ptr %s, align 1\n", t, p) return "%" + t, nil + case OpFP: + low, err := c.evalFPToI64(op.FPOffset) + if err != nil { + return "", err + } + high, err := c.evalFPToI64(op.FPOffset + 8) + if err != nil { + return "", err + } + lowLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> zeroinitializer, i64 %s, i32 0\n", lowLane, low) + both := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> %%%s, i64 %s, i32 1\n", both, lowLane, high) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", bytesValue, both) + return "%" + bytesValue, nil default: return "", fmt.Errorf("amd64: unsupported X-vector operand %s", op.String()) } } +func (c *amd64Ctx) storeXVecOperand(op Operand, value string) error { + switch op.Kind { + case OpReg: + if !isAMD64XReg(op.Reg) { + return fmt.Errorf("expected X register, got %s", op.String()) + } + return c.storeX(op.Reg, value) + case OpMem: + addr, err := c.addrFromMem(op.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store <16 x i8> %s, ptr %s, align 1\n", value, c.ptrFromAddrI64(addr)) + return nil + case OpSym: + p, err := c.ptrFromSB(op.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store <16 x i8> %s, ptr %s, align 1\n", value, p) + return nil + case OpFP: + lanes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", lanes, value) + low := c.newTmp() + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 0\n", low, lanes) + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 1\n", high, lanes) + if err := c.storeFPResult(op.FPOffset, I64, "%"+low); err != nil { + return err + } + return c.storeFPResult(op.FPOffset+8, I64, "%"+high) + default: + return fmt.Errorf("unsupported X-vector destination %s", op.String()) + } +} + func (c *amd64Ctx) loadYVecOperand(op Operand) (string, error) { switch op.Kind { case OpReg: @@ -456,6 +758,20 @@ func (c *amd64Ctx) loadXLowF64(r Reg) (string, error) { return "%" + t, nil } +func (c *amd64Ctx) loadXLowF32(r Reg) (string, error) { + xv, err := c.loadX(r) + if err != nil { + return "", err + } + words := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", words, xv) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x i32> %%%s, i32 0\n", low, words) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", value, low) + return "%" + value, nil +} + func (c *amd64Ctx) storeXLowI64(r Reg, low string) error { cur, err := c.loadX(r) if err != nil { @@ -480,6 +796,450 @@ func (c *amd64Ctx) storeXLowF64(r Reg, v string) error { return c.storeXLowI64(r, "%"+t) } +func (c *amd64Ctx) storeXLowF32(r Reg, v string) error { + cur, err := c.loadX(r) + if err != nil { + return err + } + words := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", words, cur) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %s to i32\n", bits, v) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <4 x i32> %%%s, i32 %%%s, i32 0\n", inserted, words, bits) + back := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %%%s to <16 x i8>\n", back, inserted) + return c.storeX(r, "%"+back) +} + +func (c *amd64Ctx) storeXLowF32ClearingUpper(r Reg, v string) error { + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %s to i32\n", bits, v) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <4 x i32> zeroinitializer, i32 %%%s, i32 0\n", inserted, bits) + back := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %%%s to <16 x i8>\n", back, inserted) + return c.storeX(r, "%"+back) +} + +func (c *amd64Ctx) loadXTypedVectorOperand(op Operand, vectorType string) (string, error) { + bytesValue, err := c.loadXVecOperand(op) + if err != nil { + return "", err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to %s\n", value, bytesValue, vectorType) + return "%" + value, nil +} + +func (c *amd64Ctx) loadXAsI64x2(r Reg) (string, error) { + if _, ok := amd64ParseXReg(r); !ok { + return "", fmt.Errorf("amd64: expected X register, got %s", r) + } + bytesValue, err := c.loadX(r) + if err != nil { + return "", err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", value, bytesValue) + return "%" + value, nil +} + +func (c *amd64Ctx) storeXFromI64x2(r Reg, value string) error { + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %s to <16 x i8>\n", bytesValue, value) + return c.storeX(r, "%"+bytesValue) +} + +type amd64MoveHalfSpec struct { + high bool + vector bool +} + +// amd64MoveHalfSpecs is the complete Go 1.27 yxmov/_yvmovhpd family. Legacy +// register forms alias MOVHLPS/MOVLHPS; VEX/EVEX forms deliberately accept +// only memory loads (memory, upper-lane X, destination X) and memory stores. +var amd64MoveHalfSpecs = map[Op]amd64MoveHalfSpec{ + "MOVLPS": {}, + "MOVHPS": {high: true}, + "MOVLPD": {}, + "MOVHPD": {high: true}, + "VMOVLPS": {vector: true}, + "VMOVHPS": {high: true, vector: true}, + "VMOVLPD": {vector: true}, + "VMOVHPD": {high: true, vector: true}, +} + +func (c *amd64Ctx) lowerMOVHalf(op Op, ins Instr) (bool, bool, error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64MoveHalfSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed form in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if spec.vector { + return c.lowerVEXMOVHalf(baseOp, spec, ins) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("amd64 %s expects src, dst: %q", baseOp, ins.Raw) + } + destinationLane := int64(0) + if spec.high { + destinationLane = 1 + } + if ins.Args[1].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's X register class: %q", baseOp, ins.Raw) + } + bits := "" + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("amd64 %s source is outside Go 1.27's X register class: %q", baseOp, ins.Raw) + } + source, err := c.loadXAsI64x2(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + // Register encodings of the low/high moves alias MOVHLPS and + // MOVLHPS respectively, regardless of the PS/PD prefix. + sourceLane := int64(0) + if destinationLane == 0 { + sourceLane = 1 + } + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %s, i32 %d\n", extracted, source, sourceLane) + bits = "%" + extracted + } else { + if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s source must be X or memory: %q", baseOp, ins.Raw) + } + value, err := c.evalF64(ins.Args[0]) + if err != nil { + return true, false, err + } + loadedBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", loadedBits, value) + bits = "%" + loadedBits + } + cur, err := c.loadXAsI64x2(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> %s, i64 %s, i32 %d\n", inserted, cur, bits, destinationLane) + return true, false, c.storeXFromI64x2(ins.Args[1].Reg, "%"+inserted) + } + if ins.Args[0].Kind != OpReg || !c.isGoLegacyXReg(ins.Args[0].Reg) || !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s store expects X source and memory destination: %q", baseOp, ins.Raw) + } + src, err := c.loadXAsI64x2(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %s, i32 %d\n", bits, src, destinationLane) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %%%s to double\n", value, bits) + switch ins.Args[1].Kind { + case OpFP: + return true, false, c.storeFPResult(ins.Args[1].FPOffset, LLVMType("double"), "%"+value) + case OpMem: + addr, err := c.addrFromMem(ins.Args[1].Mem) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store double %%%s, ptr %s, align 1\n", value, c.ptrFromAddrI64(addr)) + return true, false, nil + case OpSym: + p, err := c.ptrFromSB(ins.Args[1].Sym) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store double %%%s, ptr %s, align 1\n", value, p) + return true, false, nil + default: + return true, false, fmt.Errorf("amd64 %s unsupported destination: %q", baseOp, ins.Raw) + } +} + +func (c *amd64Ctx) lowerVEXMOVHalf(baseOp string, spec amd64MoveHalfSpec, ins Instr) (bool, bool, error) { + lane := int64(0) + if spec.high { + lane = 1 + } + if len(ins.Args) == 2 { + if !c.isGoPackedVectorMoveRegister(ins.Args[0], 16) || !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s store expects X source and memory destination: %q", c.goarch, baseOp, ins.Raw) + } + source, err := c.loadXAsI64x2(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %s, i32 %d\n", bits, source, lane) + return true, false, c.storeMOVHalfBits(ins.Args[1], "%"+bits) + } + if len(ins.Args) != 3 || !isAMD64MemoryOperand(ins.Args[0]) || + !c.isGoPackedVectorMoveRegister(ins.Args[1], 16) || !c.isGoPackedVectorMoveRegister(ins.Args[2], 16) { + return true, false, fmt.Errorf("%s %s load expects memory, upper-lane X, destination X: %q", c.goarch, baseOp, ins.Raw) + } + value, err := c.evalF64(ins.Args[0]) + if err != nil { + return true, false, err + } + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", bits, value) + base, err := c.loadXAsI64x2(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> %s, i64 %%%s, i32 %d\n", inserted, base, bits, lane) + return true, false, c.storeXFromI64x2(ins.Args[2].Reg, "%"+inserted) +} + +func (c *amd64Ctx) storeMOVHalfBits(destination Operand, bits string) error { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to double\n", value, bits) + switch destination.Kind { + case OpFP: + return c.storeFPResult(destination.FPOffset, LLVMType("double"), "%"+value) + case OpMem: + addr, err := c.addrFromMem(destination.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store double %%%s, ptr %s, align 1\n", value, c.ptrFromAddrI64(addr)) + return nil + case OpSym: + p, err := c.ptrFromSB(destination.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store double %%%s, ptr %s, align 1\n", value, p) + return nil + default: + return fmt.Errorf("unsupported half-vector destination %s", destination.String()) + } +} + +func (c *amd64Ctx) lowerVEXScalarFloatConvert(op Op, ins Instr) (bool, bool, error) { + rawOp := strings.ToUpper(string(op)) + parts := strings.Split(rawOp, ".") + baseOp := parts[0] + rounding := "" + sae, zeroing := false, false + for _, suffix := range parts[1:] { + switch suffix { + case "Z": + if zeroing { + return true, false, fmt.Errorf("%s %s repeats .Z: %q", c.goarch, baseOp, ins.Raw) + } + zeroing = true + case "SAE": + if baseOp != "VCVTSS2SD" || sae || rounding != "" { + return true, false, fmt.Errorf("%s %s suffix .%s is absent from its Go 1.27 EVEX form: %q", c.goarch, baseOp, suffix, ins.Raw) + } + sae = true + case "RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE": + if baseOp != "VCVTSD2SS" || sae || rounding != "" { + return true, false, fmt.Errorf("%s %s suffix .%s is absent from its Go 1.27 EVEX form: %q", c.goarch, baseOp, suffix, ins.Raw) + } + rounding = suffix + default: + return true, false, fmt.Errorf("%s %s has unsupported suffix .%s: %q", c.goarch, baseOp, suffix, ins.Raw) + } + } + if baseOp != "VCVTSS2SD" && baseOp != "VCVTSD2SS" { + return false, false, nil + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects src, upper Xsrc, [K mask,] Xdst: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if !c.isGoEVEXVectorRegister(ins.Args[1], 16) { + return true, false, fmt.Errorf("%s %s upper source must be a Go 1.27 X register: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoEVEXVectorRegister(destination, 16) { + return true, false, fmt.Errorf("%s %s destination must be a Go 1.27 X register: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoEVEXVectorRegister(ins.Args[0], 16) { + return true, false, fmt.Errorf("%s %s register source must be a Go 1.27 X register: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s source must be an X register or memory operand: %q", c.goarch, baseOp, ins.Raw) + } + if (sae || rounding != "") && ins.Args[0].Kind != OpReg { + return true, false, fmt.Errorf("%s %s embedded rounding/SAE requires a register source: %q", c.goarch, baseOp, ins.Raw) + } + var converted string + var err error + if baseOp == "VCVTSS2SD" { + src, e := c.evalF32(ins.Args[0]) + if e != nil { + return true, false, e + } + converted = c.newTmp() + fmt.Fprintf(c.b, " %%%s = fpext float %s to double\n", converted, src) + } else { + src, e := c.evalF64(ins.Args[0]) + if e != nil { + return true, false, e + } + converted = c.emitRoundedF64ToF32(src, rounding) + } + upperBytes, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + mask := "" + if masked { + mask, err = c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + } + if baseOp == "VCVTSS2SD" { + upperWords := c.bitcastVectorBytesToIntegerLanes(16, 2, 64, upperBytes) + lowBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %%%s to i64\n", lowBits, converted) + return true, false, c.storeVectorScalarRegister(destination.Reg, 64, "%"+lowBits, upperWords, mask, zeroing) + } + + upperWords := c.bitcastVectorBytesToIntegerLanes(16, 4, 32, upperBytes) + lowBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %%%s to i32\n", lowBits, converted) + return true, false, c.storeVectorScalarRegister(destination.Reg, 32, "%"+lowBits, upperWords, mask, zeroing) +} + +// emitRoundedF64ToF32 implements EVEX embedded rounding independently of the +// host floating-point environment. LLVM's scalar constrained fptrunc may lower +// to the ambient MXCSR mode on targets without AVX-512, so compute the nearest +// result first and step one IEEE-754 float toward the requested direction only +// when extending it back to double proves that adjustment is necessary. +func (c *amd64Ctx) emitRoundedF64ToF32(source, rounding string) string { + nearest := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fptrunc double %s to float\n", nearest, source) + if rounding == "" || rounding == "RN_SAE" { + return nearest + } + expanded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fpext float %%%s to double\n", expanded, nearest) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %%%s to i32\n", bits, nearest) + negativeBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i32 %%%s, 0\n", negativeBits, bits) + incremented := c.newTmp() + decremented := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %%%s, 1\n", incremented, bits) + fmt.Fprintf(c.b, " %%%s = sub i32 %%%s, 1\n", decremented, bits) + nextUpBits := c.newTmp() + nextDownBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %%%s, i32 %%%s\n", nextUpBits, negativeBits, decremented, incremented) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %%%s, i32 %%%s\n", nextDownBits, negativeBits, incremented, decremented) + nextUp := c.newTmp() + nextDown := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", nextUp, nextUpBits) + fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", nextDown, nextDownBits) + needsUp := c.newTmp() + needsDown := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp olt double %%%s, %s\n", needsUp, expanded, source) + fmt.Fprintf(c.b, " %%%s = fcmp ogt double %%%s, %s\n", needsDown, expanded, source) + upResult := c.newTmp() + downResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, float %%%s, float %%%s\n", upResult, needsUp, nextUp, nearest) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, float %%%s, float %%%s\n", downResult, needsDown, nextDown, nearest) + switch rounding { + case "RD_SAE": + return downResult + case "RU_SAE": + return upResult + case "RZ_SAE": + negativeSource := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp olt double %s, 0.000000e+00\n", negativeSource, source) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, float %%%s, float %%%s\n", result, negativeSource, upResult, downResult) + return result + default: + return nearest + } +} + +func (c *amd64Ctx) evalF32(op Operand) (string, error) { + switch op.Kind { + case OpReg: + if _, ok := amd64ParseXReg(op.Reg); !ok { + return "", fmt.Errorf("amd64: expected X register for f32 operand, got %s", op.String()) + } + return c.loadXLowF32(op.Reg) + case OpImm: + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %d to i32\n", bits, op.Imm) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", value, bits) + return "%" + value, nil + case OpFP: + return c.evalFPToF32(op.FPOffset) + case OpMem: + p, ptrType, err := c.ptrFromMem(op.Mem) + if err != nil { + return "", err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load float, %s %s, align 1\n", value, ptrType, p) + return "%" + value, nil + case OpSym: + p, err := c.ptrFromSB(op.Sym) + if err != nil { + return "", err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load float, ptr %s, align 1\n", value, p) + return "%" + value, nil + default: + return "", fmt.Errorf("amd64: unsupported f32 operand %s", op.String()) + } +} + +func (c *amd64Ctx) evalFPToF32(off int64) (string, error) { + slot, ok := c.fpParam(off) + if !ok { + return "", fmt.Errorf("unsupported FP read slot for f32: +%d(FP)", off) + } + ty := slot.Type + arg, err := c.loadFPParamValue(slot) + if err != nil { + return "", fmt.Errorf("FP read slot for f32 at +%d(FP): %w", off, err) + } + switch ty { + case LLVMType("float"): + return arg, nil + case I32: + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i32 %s to float\n", value, arg) + return "%" + value, nil + default: + return "", fmt.Errorf("FP read unsupported type %q for f32 at +%d(FP)", ty, off) + } +} + func (c *amd64Ctx) evalF64(op Operand) (string, error) { switch op.Kind { case OpReg: @@ -519,25 +1279,34 @@ func (c *amd64Ctx) evalFPToF64(off int64) (string, error) { if !ok { return "", fmt.Errorf("unsupported FP read slot for f64: +%d(FP)", off) } - idx := slot.Index - if idx < 0 || idx >= len(c.sig.Args) { - return "", fmt.Errorf("FP read slot for f64: invalid arg index %d at +%d(FP)", idx, off) - } - arg := fmt.Sprintf("%%arg%d", idx) ty := slot.Type - if c.classicFrame != "" { - loaded := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", loaded, ty, c.classicFramePtr(off)) - arg = "%" + loaded - } else if slot.Field >= 0 { - aggTy := c.sig.Args[idx] - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", t, aggTy, arg, slot.Field) - arg = "%" + t + arg, err := c.loadFPParamValue(slot) + if err != nil { + return "", fmt.Errorf("FP read slot for f64 at +%d(FP): %w", off, err) } switch ty { case LLVMType("double"): return arg, nil + case LLVMType("float"): + next, ok := c.fpParam(off + 4) + if !ok || next.Type != LLVMType("float") { + return "", fmt.Errorf("FP read at +%d(FP) cannot form MOVSD's 64-bit memory operand", off) + } + low, err := c.evalFPToI64(off) + if err != nil { + return "", err + } + high, err := c.evalFPToI64(off + 4) + if err != nil { + return "", err + } + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i64 %s, 32\n", shifted, high) + packed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i64 %s, %%%s\n", packed, low, shifted) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %%%s to double\n", value, packed) + return "%" + value, nil case I64: t := c.newTmp() fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to double\n", t, arg) diff --git a/amd64_lower_fpclass.go b/amd64_lower_fpclass.go new file mode 100644 index 00000000..ded8fefe --- /dev/null +++ b/amd64_lower_fpclass.go @@ -0,0 +1,204 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64FPClassSpec struct { + laneBits int + bytes int + scalar bool +} + +// amd64FPClassSpecs mirrors the width-specialized opcode names in Go 1.27's +// _yvfpclasspdx/_yvfpclasspdy/_yvfpclasspdz tables. Classification itself is +// shared across every packed and scalar form. +var amd64FPClassSpecs = map[Op]amd64FPClassSpec{ + "VFPCLASSPDX": {laneBits: 64, bytes: 16}, + "VFPCLASSPDY": {laneBits: 64, bytes: 32}, + "VFPCLASSPDZ": {laneBits: 64, bytes: 64}, + "VFPCLASSPSX": {laneBits: 32, bytes: 16}, + "VFPCLASSPSY": {laneBits: 32, bytes: 32}, + "VFPCLASSPSZ": {laneBits: 32, bytes: 64}, + "VFPCLASSSD": {laneBits: 64, bytes: 16, scalar: true}, + "VFPCLASSSS": {laneBits: 32, bytes: 16, scalar: true}, +} + +func (c *amd64Ctx) lowerFPClass(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64FPClassSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + broadcast := suffix == "BCST" + if suffix != "" && !broadcast { + return true, false, fmt.Errorf("%s %s has a suffix absent from Go 1.27's FPCLASS optab: %q", c.goarch, baseOp, ins.Raw) + } + if spec.scalar && broadcast { + return true, false, fmt.Errorf("%s %s scalar forms do not support broadcast: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects immediate, source, [K mask,] K destination: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("%s %s immediate must be an unsigned byte: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("%s %s input mask must be K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if !amd64IsKOperand(destination) { + return true, false, fmt.Errorf("%s %s destination must be K0-K7: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[1] + if broadcast { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, spec.bytes) { + return true, false, fmt.Errorf("%s %s source register does not match its opcode width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be its named vector width or memory: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := spec.bytes * 8 / spec.laneBits + var bits string + if spec.scalar { + scalarBits, loadErr := c.loadFloatingScalarBits(source, spec.laneBits) + if loadErr != nil { + return true, false, loadErr + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", inserted, spec.laneBits, spec.laneBits, scalarBits) + bits = "%" + inserted + lanes = 1 + } else { + bits, err = c.loadPackedCompareLanes(source, spec.bytes, spec.laneBits, broadcast) + if err != nil { + return true, false, err + } + } + classified := c.emitFPClassPredicate(lanes, spec.laneBits, bits, uint8(ins.Args[0].Imm)) + var result string + if lanes == 1 { + low := c.newTmp() + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i1> %s, i32 0\n", low, classified) + fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to i64\n", wide, low) + result = "%" + wide + } else { + result = c.packFloatingCompareMask(classified, lanes) + } + if masked { + writeMask, loadErr := c.loadK(ins.Args[2].Reg) + if loadErr != nil { + return true, false, loadErr + } + maskedResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %s\n", maskedResult, result, writeMask) + result = "%" + maskedResult + } + return true, false, c.storeK(destination.Reg, result) +} + +func (c *amd64Ctx) emitFPClassPredicate(lanes, laneBits int, bits string, immediate uint8) string { + integerType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + predicateType := fmt.Sprintf("<%d x i1>", lanes) + exponentMask := uint64(0x7f800000) + mantissaMask := uint64(0x007fffff) + quietBit := uint64(0x00400000) + if laneBits == 64 { + exponentMask = uint64(0x7ff0000000000000) + mantissaMask = uint64(0x000fffffffffffff) + quietBit = uint64(0x0008000000000000) + } + exponent, mantissa, quiet := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", exponent, integerType, bits, llvmSplatInteger(lanes, laneBits, exponentMask)) + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", mantissa, integerType, bits, llvmSplatInteger(lanes, laneBits, mantissaMask)) + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", quiet, integerType, bits, llvmSplatInteger(lanes, laneBits, quietBit)) + exponentOnes, exponentNotOnes := c.newTmp(), c.newTmp() + exponentZero, exponentNotZero := c.newTmp(), c.newTmp() + mantissaZero, mantissaNonzero := c.newTmp(), c.newTmp() + quietSet, quietClear := c.newTmp(), c.newTmp() + negative, nonnegative := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, %s\n", exponentOnes, integerType, exponent, llvmSplatInteger(lanes, laneBits, exponentMask)) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, %s\n", exponentNotOnes, integerType, exponent, llvmSplatInteger(lanes, laneBits, exponentMask)) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, zeroinitializer\n", exponentZero, integerType, exponent) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, zeroinitializer\n", exponentNotZero, integerType, exponent) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, zeroinitializer\n", mantissaZero, integerType, mantissa) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, zeroinitializer\n", mantissaNonzero, integerType, mantissa) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, zeroinitializer\n", quietSet, integerType, quiet) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, zeroinitializer\n", quietClear, integerType, quiet) + fmt.Fprintf(c.b, " %%%s = icmp slt %s %s, zeroinitializer\n", negative, integerType, bits) + fmt.Fprintf(c.b, " %%%s = icmp sge %s %s, zeroinitializer\n", nonnegative, integerType, bits) + daz := c.loadMXCSRDAZ() + dazClear := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i1 %s, false\n", dazClear, daz) + dazSetVector := amd64SplatI1(c, lanes, daz) + dazClearVector := amd64SplatI1(c, lanes, "%"+dazClear) + and := func(first, second string) string { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", value, predicateType, first, second) + return "%" + value + } + categories := [8]string{} + nan := and("%"+exponentOnes, "%"+mantissaNonzero) + categories[0] = and(nan, "%"+quietSet) + effectiveMantissaZero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %s\n", effectiveMantissaZero, predicateType, mantissaZero, dazSetVector) + zero := and("%"+exponentZero, "%"+effectiveMantissaZero) + categories[1] = and(zero, "%"+nonnegative) + categories[2] = and(zero, "%"+negative) + infinity := and("%"+exponentOnes, "%"+mantissaZero) + categories[3] = and(infinity, "%"+nonnegative) + categories[4] = and(infinity, "%"+negative) + effectiveMantissaNonzero := and("%"+mantissaNonzero, dazClearVector) + categories[5] = and("%"+exponentZero, effectiveMantissaNonzero) + negativeFinite := and("%"+negative, "%"+exponentNotOnes) + effectiveNonzero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %s\n", effectiveNonzero, predicateType, exponentNotZero, effectiveMantissaNonzero) + categories[6] = and(negativeFinite, "%"+effectiveNonzero) + categories[7] = and(nan, "%"+quietClear) + result := "zeroinitializer" + for category, predicate := range categories { + if immediate&(1< +#include +#include +extern void fpclasssemantics(uint8_t *, const uint32_t *, const uint64_t *, uint64_t); +static uint64_t u64(const uint8_t *p) { uint64_t v; memcpy(&v,p,8); return v; } +int main(void) { + const uint32_t source32[16]={ + 0x7fc12345,0x00000000,0x80000000,0x7f800000, + 0xff800000,0x00000001,0xbf800000,0x7f812345, + 0x3f800000,0x40000000,0x00800000,0x7f7fffff, + 0x3f000000,0x40400000,0x3f800001,0x3f800002}; + const uint64_t source64[8]={ + UINT64_C(0x7ff8123456789abc),UINT64_C(0),UINT64_C(0x8000000000000000),UINT64_C(0x7ff0000000000000), + UINT64_C(0xfff0000000000000),UINT64_C(1),UINT64_C(0xbff0000000000000),UINT64_C(0x7ff0123456789abc)}; + uint8_t out[273]={0}, outDaz[273]={0}; + fpclasssemantics(out,source32,source64,UINT64_C(0xa5)); + unsigned oldCsr=_mm_getcsr(); + _mm_setcsr(oldCsr|UINT32_C(0x40)); + fpclasssemantics(outDaz,source32,source64,UINT64_C(0xa5)); + _mm_setcsr(oldCsr); + for (int category=0;category<8;category++) { + uint64_t bit=UINT64_C(1)<= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64FunnelShiftSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix || properties.sae || properties.rounding != "" { + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's funnel-shift encoding: %q", c.goarch, baseOp, ins.Raw) + } + if spec.laneBits == 16 && properties.broadcast { + return true, false, fmt.Errorf("%s %s word forms do not enable EVEX broadcast: %q", c.goarch, baseOp, ins.Raw) + } + + unmaskedArgs := 4 + maskedArgs := 5 + if spec.variable { + unmaskedArgs, maskedArgs = 3, 4 + } + if len(ins.Args) != unmaskedArgs && len(ins.Args) != maskedArgs { + return true, false, fmt.Errorf("%s %s has an operand count outside Go 1.27's encoding table: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == maskedArgs + if !spec.variable && c.goarch == "386" { + return true, false, fmt.Errorf("386 %s is rejected by the Go assembler frontend's operand limit: %q", baseOp, ins.Raw) + } + if spec.variable && c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + + immediateOffset := 0 + if !spec.variable { + if !amd64UnsignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("%s %s first operand must be Go 1.27's unsigned-imm8 class: %q", c.goarch, baseOp, ins.Raw) + } + immediateOffset = 1 + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || + !c.isGoPackedVectorMoveRegister(destination, byteWidth) || + !c.isGoPackedVectorMoveRegister(ins.Args[immediateOffset+1], byteWidth) { + return true, false, fmt.Errorf("%s %s second vector source and destination must be matching Go vector registers: %q", c.goarch, baseOp, ins.Raw) + } + rmSource := ins.Args[immediateOffset] + if properties.broadcast { + if !isAMD64MemoryOperand(rmSource) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory first vector source: %q", c.goarch, baseOp, ins.Raw) + } + } else if rmSource.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(rmSource, byteWidth) { + return true, false, fmt.Errorf("%s %s first vector source must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(rmSource) { + return true, false, fmt.Errorf("%s %s first vector source must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + maskOperandIndex := len(ins.Args) - 2 + if masked && !amd64NonzeroKOperand(ins.Args[maskOperandIndex]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7 before the destination: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := byteWidth * 8 / spec.laneBits + first, err := c.loadPackedCompareLanes(rmSource, byteWidth, spec.laneBits, properties.broadcast) + if err != nil { + return true, false, err + } + second, err := c.loadPackedCompareLanes(ins.Args[immediateOffset+1], byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + old := "" + if spec.variable || masked { + oldBytes, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + old = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + } + + count := first + leftInput, rightInput := old, second + if !spec.variable { + count = amd64SplatInteger(c, lanes, spec.laneBits, fmt.Sprintf("%d", uint8(ins.Args[0].Imm))) + leftInput, rightInput = second, first + } + intrinsic := "fshl" + firstArgument, secondArgument := leftInput, rightInput + if !spec.left { + intrinsic = "fshr" + firstArgument, secondArgument = rightInput, leftInput + } + vectorType := fmt.Sprintf("<%d x i%d>", lanes, spec.laneBits) + computedName := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.v%di%d(%s %s, %s %s, %s %s)\n", + computedName, vectorType, intrinsic, lanes, spec.laneBits, + vectorType, firstArgument, vectorType, secondArgument, vectorType, count) + computed := "%" + computedName + if masked { + mask, loadErr := c.loadK(ins.Args[maskOperandIndex].Reg) + if loadErr != nil { + return true, false, loadErr + } + computed = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, computed, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", out, vectorType, computed, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} diff --git a/amd64_lower_funnel_shift_test.go b/amd64_lower_funnel_shift_test.go new file mode 100644 index 00000000..843461e2 --- /dev/null +++ b/amd64_lower_funnel_shift_test.go @@ -0,0 +1,287 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86FunnelShiftCompleteGo127Forms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT funnel_shift_forms(SB),$0-0\n") + if target.goarch == "amd64" { + for _, op := range []string{"VPSHLDW", "VPSHLDD", "VPSHLDQ", "VPSHRDW", "VPSHRDD", "VPSHRDQ"} { + broadcast := !strings.HasSuffix(op, "W") + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&source, "\t%s $0, %s0, %s1, %s2\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s $255, 8(BX), %s3, %s4\n", op, width, width) + fmt.Fprintf(&source, "\t%s $1, %s20, %s21, K1, %s22\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s.Z $2, 16(BX), %s23, K7, %s24\n", op, width, width) + if broadcast { + fmt.Fprintf(&source, "\t%s.BCST $3, 24(BX), %s25, %s26\n", op, width, width) + fmt.Fprintf(&source, "\t%s.BCST.Z $4, 32(BX), %s27, K2, %s28\n", op, width, width) + } + } + } + } + for _, op := range []string{"VPSHLDVW", "VPSHLDVD", "VPSHLDVQ", "VPSHRDVW", "VPSHRDVD", "VPSHRDVQ"} { + broadcast := !strings.HasSuffix(op, "VW") + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&source, "\t%s %s0, %s1, %s2\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s 8(BX), %s3, %s4\n", op, width, width) + if broadcast { + fmt.Fprintf(&source, "\t%s.BCST 16(BX), %s5, %s6\n", op, width, width) + } + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s %s20, %s21, K1, %s22\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s.Z 24(BX), %s23, K7, %s24\n", op, width, width) + if broadcast { + fmt.Fprintf(&source, "\t%s.BCST.Z 32(BX), %s25, K2, %s26\n", op, width, width) + } + } + } + } + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "funnel_shift_forms": {Name: "funnel_shift_forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "funnel-shift-"+target.name+".ll", "funnel-shift-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86FunnelShiftRejectsFormsOutsideGo127Tables(t *testing.T) { + for _, instruction := range []string{ + "VPSHRDQ $0, X0, X1", + "VPSHLDW $-1, X0, X1, X2", + "VPSHRDD $256, X0, X1, X2", + "VPSHLDQ AX, X0, X1, X2", + "VPSHRDW $0, Y0, X1, X2", + "VPSHLDVD Y0, X1, X2", + "VPSHRDVQ X0, Y1, X2", + "VPSHLDVW X0, X1, Y2", + "VPSHRDQ $0, X0, 8(BX), X2", + "VPSHLDVD X0, 8(BX), X2", + "VPSHRDVQ X0, X1, 8(BX)", + "VPSHLDQ $0, X0, X1, K0, X2", + "VPSHRDVD X0, K1, X1, X2", + "VPSHLDW.Z $0, X0, X1, X2", + "VPSHRDVW.Z X0, X1, X2", + "VPSHLDW.BCST $0, 8(BX), X1, X2", + "VPSHRDVW.BCST 8(BX), X1, X2", + "VPSHLDQ.BCST X0, X1, X2", + "VPSHRDVD.BCST X0, X1, X2", + "VPSHLDQ.Z.BCST $0, 8(BX), X1, K1, X2", + "VPSHRDVQ.SAE X0, X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's funnel-shift tables", instruction) + } + }) + } + for _, instruction := range []string{ + "VPSHRDQ $0, X0, X1, X2", + "VPSHLDW $0, 8(BX), Y1, Y2", + "VPSHRDVD X0, X1, K1, X2", + "VPSHLDVQ.Z 8(BX), Y1, K7, Y2", + "VPSHRDVD.BCST.Z 16(BX), Z1, K2, Z2", + "VPSHLDVW Z8, Z0, Z1", + "VPSHRDVQ Z0, Z8, Z1", + "VPSHLDVD Z0, Z1, Z8", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "386", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + Goarch: "386", + TargetTriple: "i386-unknown-linux-gnu", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted 386 %q outside Go 1.27's frontend boundary", instruction) + } + }) + } +} + +func TestAMD64FunnelShiftRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT funnelShiftSemantics(SB),$0-64 + MOVQ out+0(FP), AX + MOVQ first+8(FP), BX + MOVQ second+16(FP), CX + MOVQ old+24(FP), DX + MOVQ counts+32(FP), SI + MOVQ scalarCount+40(FP), R8 + MOVQ scalarData+48(FP), R9 + VMOVDQU64 (BX), X0 + VMOVDQU64 (CX), X1 + VMOVDQU64 (SI), X3 + VPSHLDW $4, X0, X1, X4 + VMOVDQU64 X4, 0(AX) + VPSHRDW $4, X0, X1, X5 + VMOVDQU64 X5, 16(AX) + VPSHLDD $8, X0, X1, X6 + VMOVDQU64 X6, 32(AX) + VPSHRDD $8, X0, X1, X7 + VMOVDQU64 X7, 48(AX) + VPSHLDQ $13, X0, X1, X8 + VMOVDQU64 X8, 64(AX) + VPSHRDQ $32, X0, X1, X9 + VMOVDQU64 X9, 80(AX) + VMOVDQU64 (DX), X10 + VPSHLDVW X3, X1, X10 + VMOVDQU64 X10, 96(AX) + VMOVDQU64 (DX), X11 + VPSHRDVD X3, X1, X11 + VMOVDQU64 X11, 112(AX) + VMOVDQU64 (DX), X12 + VPSHLDVQ X3, X1, X12 + VMOVDQU64 X12, 128(AX) + KMOVQ mask+56(FP), K1 + VMOVDQU64 (DX), X13 + VPSHRDQ $32, X0, X1, K1, X13 + VMOVDQU64 X13, 144(AX) + VMOVDQU64 (DX), X14 + VPSHRDQ.Z $32, X0, X1, K1, X14 + VMOVDQU64 X14, 160(AX) + VMOVDQU64 (DX), X15 + VPSHLDVD.BCST (R8), X1, X15 + VMOVDQU64 X15, 176(AX) + VPSHRDD.BCST $8, (R9), X1, X16 + VMOVDQU64 X16, 192(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + {Offset: 48, Type: Ptr, Index: 6, Field: -1}, + {Offset: 56, Type: I64, Index: 7, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "funnelShiftSemantics": { + Name: "funnelShiftSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, I64}, + Ret: Void, + Frame: frame, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +typedef union { uint8_t b[16]; uint16_t w[8]; uint32_t d[4]; uint64_t q[2]; } V; +extern void funnelShiftSemantics(V *, const V *, const V *, const V *, const V *, const uint32_t *, const uint32_t *, uint64_t); +static uint16_t shl16(uint16_t a, uint16_t b, unsigned c) { c &= 15; return c ? (uint16_t)((a << c) | (b >> (16-c))) : a; } +static uint16_t shr16(uint16_t a, uint16_t b, unsigned c) { c &= 15; return c ? (uint16_t)((a >> c) | (b << (16-c))) : a; } +static uint32_t shl32(uint32_t a, uint32_t b, unsigned c) { c &= 31; return c ? (a << c) | (b >> (32-c)) : a; } +static uint32_t shr32(uint32_t a, uint32_t b, unsigned c) { c &= 31; return c ? (a >> c) | (b << (32-c)) : a; } +static uint64_t shl64(uint64_t a, uint64_t b, unsigned c) { c &= 63; return c ? (a << c) | (b >> (64-c)) : a; } +static uint64_t shr64(uint64_t a, uint64_t b, unsigned c) { c &= 63; return c ? (a >> c) | (b << (64-c)) : a; } +int main(void) { + V first = {.q = {UINT64_C(0x0123456789abcdef), UINT64_C(0xfedcba9876543210)}}; + V second = {.q = {UINT64_C(0x8877665544332211), UINT64_C(0x1020304050607080)}}; + V old = {.q = {UINT64_C(0x0f1e2d3c4b5a6978), UINT64_C(0x8796a5b4c3d2e1f0)}}; + V counts = {.q = {UINT64_C(0x001f000800030000), UINT64_C(0x0041002000110004)}}; + uint32_t scalarCount = 37; + uint32_t scalarData = UINT32_C(0xa1b2c3d4); + V out[13] = {0}, want[13] = {0}; + for (int i = 0; i < 8; i++) { + want[0].w[i] = shl16(second.w[i], first.w[i], 4); + want[1].w[i] = shr16(second.w[i], first.w[i], 4); + want[6].w[i] = shl16(old.w[i], second.w[i], counts.w[i]); + } + for (int i = 0; i < 4; i++) { + want[2].d[i] = shl32(second.d[i], first.d[i], 8); + want[3].d[i] = shr32(second.d[i], first.d[i], 8); + want[7].d[i] = shr32(old.d[i], second.d[i], counts.d[i]); + want[11].d[i] = shl32(old.d[i], second.d[i], scalarCount); + want[12].d[i] = shr32(second.d[i], scalarData, 8); + } + for (int i = 0; i < 2; i++) { + want[4].q[i] = shl64(second.q[i], first.q[i], 13); + want[5].q[i] = shr64(second.q[i], first.q[i], 32); + want[8].q[i] = shl64(old.q[i], second.q[i], counts.q[i]); + } + want[9].q[0] = want[5].q[0]; want[9].q[1] = old.q[1]; + want[10].q[0] = want[5].q[0]; want[10].q[1] = 0; + funnelShiftSemantics(out, &first, &second, &old, &counts, &scalarCount, &scalarData, 1); + return memcmp(out, want, sizeof(out)) == 0 ? 0 : 1; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "funnel_shift", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_gather.go b/amd64_lower_gather.go new file mode 100644 index 00000000..69817082 --- /dev/null +++ b/amd64_lower_gather.go @@ -0,0 +1,380 @@ +package plan9asm + +import "fmt" + +type amd64GatherTable uint8 + +const ( + amd64GatherDPS amd64GatherTable = iota + amd64GatherDPD + amd64GatherQPS +) + +type amd64GatherSpec struct { + table amd64GatherTable + elemBits int + indexBits int +} + +// amd64GatherSpecs is the complete Go 1.27 data-gather family. The eight +// spellings share _yvgatherdps, _yvgatherdpd, and _yvgatherqps. +var amd64GatherSpecs = map[Op]amd64GatherSpec{ + "VGATHERDPS": {table: amd64GatherDPS, elemBits: 32, indexBits: 32}, + "VGATHERQPD": {table: amd64GatherDPS, elemBits: 64, indexBits: 64}, + "VPGATHERDD": {table: amd64GatherDPS, elemBits: 32, indexBits: 32}, + "VPGATHERQQ": {table: amd64GatherDPS, elemBits: 64, indexBits: 64}, + "VGATHERDPD": {table: amd64GatherDPD, elemBits: 64, indexBits: 32}, + "VPGATHERDQ": {table: amd64GatherDPD, elemBits: 64, indexBits: 32}, + "VGATHERQPS": {table: amd64GatherQPS, elemBits: 32, indexBits: 64}, + "VPGATHERQD": {table: amd64GatherQPS, elemBits: 32, indexBits: 64}, +} + +type amd64VSIBPrefetchDirection uint8 + +const ( + amd64VSIBPrefetchGather amd64VSIBPrefetchDirection = iota + amd64VSIBPrefetchScatter +) + +type amd64VSIBPrefetchSpec struct { + direction amd64VSIBPrefetchDirection + hint int + elemBits int + indexBits int + indexBytes int +} + +// amd64VSIBPrefetchSpecs is the complete Go 1.27 gather/scatter prefetch +// grammar. Direction, cache hint, element width, and VSIB index width are data; +// all sixteen opcodes share one exact operand validator. These instructions +// are architectural hints, so lowering has no observable IR side effect. +var amd64VSIBPrefetchSpecs = map[Op]amd64VSIBPrefetchSpec{ + "VGATHERPF0DPD": {direction: amd64VSIBPrefetchGather, hint: 0, elemBits: 64, indexBits: 32, indexBytes: 32}, + "VGATHERPF0DPS": {direction: amd64VSIBPrefetchGather, hint: 0, elemBits: 32, indexBits: 32, indexBytes: 64}, + "VGATHERPF0QPD": {direction: amd64VSIBPrefetchGather, hint: 0, elemBits: 64, indexBits: 64, indexBytes: 64}, + "VGATHERPF0QPS": {direction: amd64VSIBPrefetchGather, hint: 0, elemBits: 32, indexBits: 64, indexBytes: 64}, + "VGATHERPF1DPD": {direction: amd64VSIBPrefetchGather, hint: 1, elemBits: 64, indexBits: 32, indexBytes: 32}, + "VGATHERPF1DPS": {direction: amd64VSIBPrefetchGather, hint: 1, elemBits: 32, indexBits: 32, indexBytes: 64}, + "VGATHERPF1QPD": {direction: amd64VSIBPrefetchGather, hint: 1, elemBits: 64, indexBits: 64, indexBytes: 64}, + "VGATHERPF1QPS": {direction: amd64VSIBPrefetchGather, hint: 1, elemBits: 32, indexBits: 64, indexBytes: 64}, + "VSCATTERPF0DPD": {direction: amd64VSIBPrefetchScatter, hint: 0, elemBits: 64, indexBits: 32, indexBytes: 32}, + "VSCATTERPF0DPS": {direction: amd64VSIBPrefetchScatter, hint: 0, elemBits: 32, indexBits: 32, indexBytes: 64}, + "VSCATTERPF0QPD": {direction: amd64VSIBPrefetchScatter, hint: 0, elemBits: 64, indexBits: 64, indexBytes: 64}, + "VSCATTERPF0QPS": {direction: amd64VSIBPrefetchScatter, hint: 0, elemBits: 32, indexBits: 64, indexBytes: 64}, + "VSCATTERPF1DPD": {direction: amd64VSIBPrefetchScatter, hint: 1, elemBits: 64, indexBits: 32, indexBytes: 32}, + "VSCATTERPF1DPS": {direction: amd64VSIBPrefetchScatter, hint: 1, elemBits: 32, indexBits: 32, indexBytes: 64}, + "VSCATTERPF1QPD": {direction: amd64VSIBPrefetchScatter, hint: 1, elemBits: 64, indexBits: 64, indexBytes: 64}, + "VSCATTERPF1QPS": {direction: amd64VSIBPrefetchScatter, hint: 1, elemBits: 32, indexBits: 64, indexBytes: 64}, +} + +func (c *amd64Ctx) lowerGather(op Op, ins Instr) error { + if prefetch, ok := amd64VSIBPrefetchSpecs[op]; ok { + return c.lowerVSIBPrefetch(op, prefetch, ins) + } + spec := amd64GatherSpecs[op] + if len(ins.Args) != 3 { + return fmt.Errorf("amd64 %s expects exactly three operands from its Go 1.27 gather table: %q", op, ins.Raw) + } + + var memory Operand + var mask Operand + var destination Operand + evex := false + if ins.Args[0].Kind == OpMem { + evex = true + memory, mask, destination = ins.Args[0], ins.Args[1], ins.Args[2] + } else { + mask, memory, destination = ins.Args[0], ins.Args[1], ins.Args[2] + } + if memory.Kind != OpMem || destination.Kind != OpReg { + return fmt.Errorf("amd64 %s expects vector-mask,memory,vector or memory,K-mask,vector: %q", op, ins.Raw) + } + destinationBytes := amd64VectorByteWidth(destination.Reg) + indexBytes := amd64VectorByteWidth(memory.Mem.Index) + if destinationBytes == 0 || indexBytes == 0 || !amd64GatherTableAllows(spec.table, evex, destinationBytes, indexBytes) { + return fmt.Errorf("amd64 %s vector widths are outside its Go 1.27 gather table: %q", op, ins.Raw) + } + if err := c.validateGatherMemory(memory.Mem, indexBytes, evex); err != nil { + return fmt.Errorf("amd64 %s invalid VSIB memory: %q: %w", op, ins.Raw, err) + } + destinationIndex, ok := amd64GatherRegisterIndex(destination.Reg, destinationBytes, evex, c.goarch, false) + if !ok { + return fmt.Errorf("amd64 %s destination is outside its Go 1.27 register class: %q", op, ins.Raw) + } + indexIndex, ok := amd64GatherRegisterIndex(memory.Mem.Index, indexBytes, evex, c.goarch, true) + if !ok { + return fmt.Errorf("amd64 %s VSIB index is outside its Go 1.27 register class: %q", op, ins.Raw) + } + if destinationIndex == indexIndex { + return fmt.Errorf("amd64 %s index and destination registers must be distinct: %q", op, ins.Raw) + } + + if evex { + maskIndex, ok := amd64ParseKReg(mask.Reg) + if mask.Kind != OpReg || !ok || maskIndex == 0 { + return fmt.Errorf("amd64 %s EVEX form requires K1..K7: %q", op, ins.Raw) + } + } else { + maskBytes := amd64VectorByteWidth(mask.Reg) + maskIndex, ok := amd64GatherRegisterIndex(mask.Reg, destinationBytes, false, c.goarch, false) + if mask.Kind != OpReg || !ok || maskBytes != destinationBytes { + return fmt.Errorf("amd64 %s VEX form requires a destination-width vector mask: %q", op, ins.Raw) + } + if maskIndex == indexIndex || maskIndex == destinationIndex { + return fmt.Errorf("amd64 %s mask, index, and destination registers must be distinct: %q", op, ins.Raw) + } + } + + return c.emitGather(spec, memory.Mem, mask, destination.Reg, destinationBytes, indexBytes, evex) +} + +func (c *amd64Ctx) lowerVSIBPrefetch(op Op, spec amd64VSIBPrefetchSpec, ins Instr) error { + if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpMem { + return fmt.Errorf("amd64 %s expects K1..K7 and VSIB memory: %q", op, ins.Raw) + } + maskIndex, ok := amd64ParseKReg(ins.Args[0].Reg) + if !ok || maskIndex == 0 { + return fmt.Errorf("amd64 %s requires K1..K7: %q", op, ins.Raw) + } + indexBytes := spec.indexBytes + if amd64VectorByteWidth(ins.Args[1].Mem.Index) != indexBytes { + return fmt.Errorf("amd64 %s has the wrong VSIB index width: %q", op, ins.Raw) + } + if err := c.validateGatherMemory(ins.Args[1].Mem, indexBytes, true); err != nil { + return fmt.Errorf("amd64 %s invalid VSIB memory: %q: %w", op, ins.Raw, err) + } + if _, ok := amd64GatherRegisterIndex(ins.Args[1].Mem.Index, indexBytes, true, c.goarch, true); !ok { + return fmt.Errorf("amd64 %s VSIB index is outside its Go 1.27 register class: %q", op, ins.Raw) + } + return nil +} + +func amd64GatherTableAllows(table amd64GatherTable, evex bool, destinationBytes, indexBytes int) bool { + allowed := false + switch table { + case amd64GatherDPS: + allowed = (destinationBytes == 16 && indexBytes == 16) || + (destinationBytes == 32 && indexBytes == 32) || + (destinationBytes == 64 && indexBytes == 64) + case amd64GatherDPD: + allowed = (destinationBytes == 16 && indexBytes == 16) || + (destinationBytes == 32 && indexBytes == 16) || + (destinationBytes == 64 && indexBytes == 32) + case amd64GatherQPS: + allowed = (destinationBytes == 16 && (indexBytes == 16 || indexBytes == 32)) || + (destinationBytes == 32 && indexBytes == 64) + } + if !allowed { + return false + } + if !evex { + return destinationBytes != 64 + } + return true +} + +func (c *amd64Ctx) validateGatherMemory(memory MemRef, indexBytes int, evex bool) error { + if memory.Index == "" || amd64VectorByteWidth(memory.Index) != indexBytes { + return fmt.Errorf("expected a VSIB vector index") + } + if memory.Scale == 0 { + memory.Scale = 1 + } + if memory.Scale != 1 && memory.Scale != 2 && memory.Scale != 4 && memory.Scale != 8 { + return fmt.Errorf("VSIB scale must be 1, 2, 4, or 8") + } + if memory.Sym != "" { + return fmt.Errorf("Go's x86 assembler does not accept an SB base with VSIB") + } + if memory.Base != "" && !isX86YrlRegisterForArch(memory.Base, c.goarch) { + return fmt.Errorf("VSIB base is not a GP register for %s", c.goarch) + } + if memory.Segment != "" && memory.Segment != FS && memory.Segment != GS { + return fmt.Errorf("unsupported VSIB segment %s", memory.Segment) + } + _ = evex + return nil +} + +func amd64GatherRegisterIndex(register Reg, byteWidth int, evex bool, goarch string, index bool) (int, bool) { + var registerIndex int + var ok bool + switch byteWidth { + case 16: + registerIndex, ok = amd64ParseXReg(register) + case 32: + registerIndex, ok = amd64ParseYReg(register) + case 64: + registerIndex, ok = amd64ParseZReg(register) + } + if !ok { + return 0, false + } + limit := 15 + if evex { + limit = 31 + } + if goarch == "386" && (index || byteWidth == 64) { + limit = 7 + } + return registerIndex, registerIndex <= limit +} + +func (c *amd64Ctx) emitGather(spec amd64GatherSpec, memory MemRef, mask Operand, destination Reg, destinationBytes, indexBytes int, evex bool) error { + destinationValue, err := c.loadGatherVector(destination, destinationBytes) + if err != nil { + return err + } + destinationLanes := destinationBytes * 8 / spec.elemBits + destinationType := fmt.Sprintf("<%d x i%d>", destinationLanes, spec.elemBits) + destinationValues := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", destinationValues, destinationBytes, destinationValue, destinationType) + result := "%" + destinationValues + + indexValue, err := c.loadGatherVector(memory.Index, indexBytes) + if err != nil { + return err + } + indexLanes := indexBytes * 8 / spec.indexBits + indexType := fmt.Sprintf("<%d x i%d>", indexLanes, spec.indexBits) + indexValues := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", indexValues, indexBytes, indexValue, indexType) + activeLanes := destinationLanes + if indexLanes < activeLanes { + activeLanes = indexLanes + // QPS/QD with an X index has two active dword lanes and architecturally + // zeroes the upper two lanes of the X destination. + for lane := activeLanes; lane < destinationLanes; lane++ { + zeroed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d 0, i32 %d\n", zeroed, destinationType, result, spec.elemBits, lane) + result = "%" + zeroed + } + } + + var maskValues string + var kMask string + if evex { + kMask, err = c.loadK(mask.Reg) + } else { + maskBytes, err := c.loadGatherVector(mask.Reg, destinationBytes) + if err != nil { + return err + } + maskValues = c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", maskValues, destinationBytes, maskBytes, destinationType) + maskValues = "%" + maskValues + } + + base, err := c.gatherBaseAddress(memory) + if err != nil { + return err + } + for lane := 0; lane < activeLanes; lane++ { + indexLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", indexLane, indexType, indexValues, lane) + wideIndex := "%" + indexLane + if spec.indexBits == 32 { + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext i32 %%%s to i64\n", extended, indexLane) + wideIndex = "%" + extended + } + if memory.Scale != 0 && memory.Scale != 1 { + scaled := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i64 %s, %d\n", scaled, wideIndex, memory.Scale) + wideIndex = "%" + scaled + } + address := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", address, base, wideIndex) + pointer, pointerType := c.gatherPointer(memory, "%"+address) + + condition := "" + if evex { + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i64 %s, %d\n", shifted, kMask, lane) + bit := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, 1\n", bit, shifted) + set := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne i64 %%%s, 0\n", set, bit) + condition = "%" + set + } else { + maskLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", maskLane, destinationType, maskValues, lane) + set := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i%d %%%s, 0\n", set, spec.elemBits, maskLane) + condition = "%" + set + } + + oldLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", oldLane, destinationType, result, lane) + loadLabel := c.newTmp() + "_gather_load" + skipLabel := c.newTmp() + "_gather_skip" + joinLabel := c.newTmp() + "_gather_join" + loaded := c.newTmp() + selected := c.newTmp() + fmt.Fprintf(c.b, " br i1 %s, label %%%s, label %%%s\n", condition, loadLabel, skipLabel) + fmt.Fprintf(c.b, "%s:\n", loadLabel) + fmt.Fprintf(c.b, " %%%s = load i%d, %s %s, align 1\n", loaded, spec.elemBits, pointerType, pointer) + fmt.Fprintf(c.b, " br label %%%s\n", joinLabel) + fmt.Fprintf(c.b, "%s:\n", skipLabel) + fmt.Fprintf(c.b, " br label %%%s\n", joinLabel) + fmt.Fprintf(c.b, "%s:\n", joinLabel) + fmt.Fprintf(c.b, " %%%s = phi i%d [ %%%s, %%%s ], [ %%%s, %%%s ]\n", selected, spec.elemBits, loaded, loadLabel, oldLane, skipLabel) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %%%s, i32 %d\n", inserted, destinationType, result, spec.elemBits, selected, lane) + result = "%" + inserted + } + + bytesResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", bytesResult, destinationType, result, destinationBytes) + if err := c.storeVectorBytes(destination, destinationBytes, "%"+bytesResult); err != nil { + return err + } + if evex { + return c.storeK(mask.Reg, "0") + } + return c.storeVectorBytes(mask.Reg, destinationBytes, "zeroinitializer") +} + +func (c *amd64Ctx) loadGatherVector(register Reg, byteWidth int) (string, error) { + switch byteWidth { + case 16: + return c.loadX(register) + case 32: + return c.loadY(register) + case 64: + return c.loadZ(register) + default: + return "", fmt.Errorf("unsupported gather vector width %d", byteWidth) + } +} + +func (c *amd64Ctx) gatherBaseAddress(memory MemRef) (string, error) { + base := "0" + if memory.Base != "" { + value, err := c.loadReg(memory.Base) + if err != nil { + return "", err + } + base = value + } + if memory.Off != 0 { + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %d\n", adjusted, base, memory.Off) + base = "%" + adjusted + } + return base, nil +} + +func (c *amd64Ctx) gatherPointer(memory MemRef, address string) (string, string) { + if memory.Segment == "" { + return c.ptrFromAddrI64(address), "ptr" + } + addressSpace := 257 + if memory.Segment == GS { + addressSpace = 256 + } + pointerType := fmt.Sprintf("ptr addrspace(%d)", addressSpace) + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to %s\n", pointer, address, pointerType) + return "%" + pointer, pointerType +} diff --git a/amd64_lower_getexp.go b/amd64_lower_getexp.go new file mode 100644 index 00000000..01d31f84 --- /dev/null +++ b/amd64_lower_getexp.go @@ -0,0 +1,198 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64GetExpSpec struct { + laneBits int + scalar bool +} + +var amd64GetExpSpecs = map[Op]amd64GetExpSpec{ + "VGETEXPPS": {laneBits: 32}, + "VGETEXPPD": {laneBits: 64}, + "VGETEXPSS": {laneBits: 32, scalar: true}, + "VGETEXPSD": {laneBits: 64, scalar: true}, +} + +func (c *amd64Ctx) lowerGetExp(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64GetExpSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix || properties.rounding != "" { + return true, false, fmt.Errorf("%s %s has a suffix absent from Go 1.27's GETEXP optab: %q", c.goarch, baseOp, ins.Raw) + } + if spec.scalar && properties.broadcast { + return true, false, fmt.Errorf("%s %s scalar forms do not support broadcast: %q", c.goarch, baseOp, ins.Raw) + } + wantArgs := 2 + if spec.scalar { + wantArgs = 3 + } + if len(ins.Args) != wantArgs && len(ins.Args) != wantArgs+1 { + return true, false, fmt.Errorf("%s %s has the wrong operand count for its packed/scalar grammar: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == wantArgs+1 + if c.goarch == "386" && spec.scalar && masked { + return true, false, fmt.Errorf("386 %s mask form exceeds the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + maskIndex := len(ins.Args) - 2 + if masked && !amd64NonzeroKOperand(ins.Args[maskIndex]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be a vector register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if spec.scalar { + if byteWidth != 16 || !c.isGoEVEXVectorRegister(destination, 16) || !c.isGoEVEXVectorRegister(ins.Args[1], 16) { + return true, false, fmt.Errorf("%s %s scalar pass-through and destination must be X registers: %q", c.goarch, baseOp, ins.Raw) + } + } else if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s packed destination must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[0] + if properties.broadcast { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source register must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if properties.sae { + if source.Kind != OpReg || !spec.scalar && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s.SAE requires a register source and scalar or Z form: %q", c.goarch, baseOp, ins.Raw) + } + } + + mask := "" + if masked { + mask, err = c.loadK(ins.Args[maskIndex].Reg) + if err != nil { + return true, false, err + } + } + daz := c.loadMXCSRDAZ() + if spec.scalar { + return c.lowerScalarGetExp(spec, properties, source, ins.Args[1], destination, mask, daz) + } + return c.lowerPackedGetExp(spec, properties, source, destination, byteWidth, mask, daz) +} + +func (c *amd64Ctx) lowerPackedGetExp(spec amd64GetExpSpec, properties amd64BinaryFloatingSuffix, source, destination Operand, byteWidth int, mask, daz string) (bool, bool, error) { + lanes := byteWidth * 8 / spec.laneBits + input, err := c.loadPackedCompareLanes(source, byteWidth, spec.laneBits, properties.broadcast) + if err != nil { + return true, false, err + } + result := c.emitGetExpBits(lanes, spec.laneBits, input, daz) + if mask != "" { + oldBytes, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) lowerScalarGetExp(spec amd64GetExpSpec, properties amd64BinaryFloatingSuffix, source, passthrough, destination Operand, mask, daz string) (bool, bool, error) { + sourceBits, err := c.loadFloatingScalarBits(source, spec.laneBits) + if err != nil { + return true, false, err + } + input := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", input, spec.laneBits, spec.laneBits, sourceBits) + result := c.emitGetExpBits(1, spec.laneBits, "%"+input, daz) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i%d> %s, i32 0\n", low, spec.laneBits, result) + passthroughBytes, err := c.loadX(passthrough.Reg) + if err != nil { + return true, false, err + } + base := c.bitcastVectorBytesToIntegerLanes(16, 128/spec.laneBits, spec.laneBits, passthroughBytes) + return true, false, c.storeVectorScalarRegister(destination.Reg, spec.laneBits, "%"+low, base, mask, properties.zeroing) +} + +func (c *amd64Ctx) emitGetExpBits(lanes, laneBits int, input, daz string) string { + vectorType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + floatType := amd64FloatingScalarType(laneBits) + mantissaBits, bias, denormalOffset := 23, 127, 149 + exponentMask := uint64(0x7f800000) + mantissaMask := uint64(0x007fffff) + quietBit := uint64(0x00400000) + signBit := uint64(0x80000000) + if laneBits == 64 { + mantissaBits, bias, denormalOffset = 52, 1023, 1074 + exponentMask = uint64(0x7ff0000000000000) + mantissaMask = uint64(0x000fffffffffffff) + quietBit = uint64(0x0008000000000000) + signBit = uint64(0x8000000000000000) + } + positiveInfinity := exponentMask + negativeInfinity := signBit | exponentMask + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + bits, exponent, mantissa := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", bits, vectorType, input, lane) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", exponent, laneBits, bits, exponentMask) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", mantissa, laneBits, bits, mantissaMask) + exponentZero, exponentOnes := c.newTmp(), c.newTmp() + mantissaZero, mantissaNonzero := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", exponentZero, laneBits, exponent) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, %d\n", exponentOnes, laneBits, exponent, exponentMask) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", mantissaZero, laneBits, mantissa) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", mantissaNonzero, laneBits, mantissa) + isNaN, isInfinity, isDenormal := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isNaN, exponentOnes, mantissaNonzero) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isInfinity, exponentOnes, mantissaZero) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isDenormal, exponentZero, mantissaNonzero) + zeroOrDAZ, isEffectiveZero := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %s\n", zeroOrDAZ, mantissaZero, daz) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isEffectiveZero, exponentZero, zeroOrDAZ) + + normalField, normalExponent := c.newTmp(), c.newTmp() + leadingZeros, highestBit, denormalExponent := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i%d %%%s, %d\n", normalField, laneBits, exponent, mantissaBits) + fmt.Fprintf(c.b, " %%%s = sub i%d %%%s, %d\n", normalExponent, laneBits, normalField, bias) + fmt.Fprintf(c.b, " %%%s = call i%d @llvm.ctlz.i%d(i%d %%%s, i1 false)\n", leadingZeros, laneBits, laneBits, laneBits, mantissa) + fmt.Fprintf(c.b, " %%%s = sub i%d %d, %%%s\n", highestBit, laneBits, laneBits-1, leadingZeros) + fmt.Fprintf(c.b, " %%%s = sub i%d %%%s, %d\n", denormalExponent, laneBits, highestBit, denormalOffset) + exponentValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", exponentValue, isDenormal, laneBits, denormalExponent, laneBits, normalExponent) + exponentFloat, exponentBits := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = sitofp i%d %%%s to %s\n", exponentFloat, laneBits, exponentValue, floatType) + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to i%d\n", exponentBits, floatType, exponentFloat, laneBits) + withInfinity, withZero := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d %%%s\n", withInfinity, isInfinity, laneBits, positiveInfinity, laneBits, exponentBits) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d %%%s\n", withZero, isEffectiveZero, laneBits, negativeInfinity, laneBits, withInfinity) + quietNaN := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %d\n", quietNaN, laneBits, bits, quietBit) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", selected, isNaN, laneBits, quietNaN, laneBits, withZero) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %%%s, i32 %d\n", inserted, vectorType, result, laneBits, selected, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_getexp_test.go b/amd64_lower_getexp_test.go new file mode 100644 index 00000000..76033dc6 --- /dev/null +++ b/amd64_lower_getexp_test.go @@ -0,0 +1,274 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64GetExpGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64GetExpSpec{ + "VGETEXPPS": {laneBits: 32}, + "VGETEXPPD": {laneBits: 64}, + "VGETEXPSS": {laneBits: 32, scalar: true}, + "VGETEXPSD": {laneBits: 64, scalar: true}, + } + if len(amd64GetExpSpecs) != len(expected) { + t.Fatalf("GETEXP grammar has %d entries, want %d", len(amd64GetExpSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64GetExpSpecs[op]; !ok { + t.Errorf("GETEXP grammar omitted %s", op) + } else if got != want { + t.Errorf("GETEXP grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86GetExpCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT getexpforms(SB),$0-0\n") + for _, op := range []string{"VGETEXPPS", "VGETEXPPD"} { + for _, width := range []string{"X", "Y", "Z"} { + last := 31 + if target.goarch == "386" && width == "Z" { + last = 7 + } + fmt.Fprintf(&source, "\t%s %s1, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s 8(AX), %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST 16(AX), %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s %s1, K1, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s.Z 24(AX), K2, %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST.Z 32(AX), K3, %s%d\n", op, width, last) + if width == "Z" { + fmt.Fprintf(&source, "\t%s.SAE Z1, Z%d\n", op, last) + fmt.Fprintf(&source, "\t%s.SAE.Z Z1, K4, Z%d\n", op, last) + } + } + } + for _, op := range []string{"VGETEXPSS", "VGETEXPSD"} { + last := 31 + fmt.Fprintf(&source, "\t%s X1, X2, X%d\n", op, last) + fmt.Fprintf(&source, "\t%s 40(AX), X2, X%d\n", op, last) + fmt.Fprintf(&source, "\t%s.SAE X1, X2, X%d\n", op, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s X1, X2, K5, X%d\n", op, last) + fmt.Fprintf(&source, "\t%s.Z 48(AX), X2, K6, X%d\n", op, last) + fmt.Fprintf(&source, "\t%s.SAE.Z X1, X2, K7, X%d\n", op, last) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"getexpforms": {Name: "getexpforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "getexp-"+target.name+".ll", "getexp-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86GetExpRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VGETEXPPS X0"}, + {goarch: "amd64", instruction: "VGETEXPPS X0, Y1"}, + {goarch: "amd64", instruction: "VGETEXPPS.BCST X0, X1"}, + {goarch: "amd64", instruction: "VGETEXPPS.SAE X0, X1"}, + {goarch: "amd64", instruction: "VGETEXPPS.SAE 0(AX), Z1"}, + {goarch: "amd64", instruction: "VGETEXPPS.RN_SAE Z0, Z1"}, + {goarch: "amd64", instruction: "VGETEXPPS.Z X0, X1"}, + {goarch: "amd64", instruction: "VGETEXPPS X0, K0, X1"}, + {goarch: "amd64", instruction: "VGETEXPSS Y0, X1, X2"}, + {goarch: "amd64", instruction: "VGETEXPSS.BCST 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VGETEXPSD X0, X1, Y2"}, + {goarch: "386", instruction: "VGETEXPSS X0, X1, K1, X2"}, + {goarch: "386", instruction: "VGETEXPPS Z8, Z0"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's GETEXP table", test.instruction) + } + }) + } +} + +func TestAMD64GetExpRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT getexpsemantics(SB),$0-56 + MOVQ out+0(FP), AX + MOVQ source32+8(FP), BX + MOVQ source64+16(FP), CX + MOVQ old32+24(FP), DX + MOVQ old64+32(FP), R8 + MOVQ upper+40(FP), R9 + MOVQ mask+48(FP), R10 + KMOVQ R10, K1 + STC + VGETEXPPS 0(BX), Z0 + VMOVDQU32 Z0, 0(AX) + VMOVDQU32 0(DX), Z1 + VGETEXPPS 0(BX), K1, Z1 + VMOVDQU32 Z1, 64(AX) + VGETEXPPS.Z 0(BX), K1, Z1 + VMOVDQU32 Z1, 128(AX) + VGETEXPPS.BCST 0(BX), Z1 + VMOVDQU32 Z1, 192(AX) + VGETEXPPD 0(CX), Z2 + VMOVDQU64 Z2, 256(AX) + VMOVDQU64 0(R8), Z3 + VGETEXPPD 0(CX), K1, Z3 + VMOVDQU64 Z3, 320(AX) + VGETEXPPD.Z 0(CX), K1, Z3 + VMOVDQU64 Z3, 384(AX) + VGETEXPPD.BCST 0(CX), Z3 + VMOVDQU64 Z3, 448(AX) + VMOVDQU64 0(R9), X4 + VGETEXPSS 40(BX), X4, X5 + VMOVDQU64 X5, 512(AX) + VGETEXPSD 40(CX), X4, X6 + VMOVDQU64 X6, 528(AX) + SETCS 544(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"getexpsemantics": { + Name: "getexpsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + {Offset: 48, Type: I64, Index: 6, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +#include +extern void getexpsemantics(uint8_t *, const uint32_t *, const uint64_t *, const uint32_t *, const uint64_t *, const uint64_t *, uint64_t); +static uint32_t f32bits(float f) { uint32_t u; memcpy(&u,&f,4); return u; } +static uint64_t f64bits(double f) { uint64_t u; memcpy(&u,&f,8); return u; } +static uint32_t getexp32(uint32_t u, int daz) { + uint32_t exp=u&UINT32_C(0x7f800000), mant=u&UINT32_C(0x007fffff); + if (exp==UINT32_C(0x7f800000)) return mant?(u|UINT32_C(0x00400000)):UINT32_C(0x7f800000); + if (exp==0 && (mant==0||daz)) return UINT32_C(0xff800000); + int e; + if (exp) e=(int)(exp>>23)-127; + else { int p=31-__builtin_clz(mant); e=p-149; } + return f32bits((float)e); +} +static uint64_t getexp64(uint64_t u, int daz) { + uint64_t exp=u&UINT64_C(0x7ff0000000000000), mant=u&UINT64_C(0x000fffffffffffff); + if (exp==UINT64_C(0x7ff0000000000000)) return mant?(u|UINT64_C(0x0008000000000000)):UINT64_C(0x7ff0000000000000); + if (exp==0 && (mant==0||daz)) return UINT64_C(0xfff0000000000000); + int e; + if (exp) e=(int)(exp>>52)-1023; + else { int p=63-__builtin_clzll(mant); e=p-1074; } + return f64bits((double)e); +} +int main(void) { + const uint32_t source32[16]={ + 0x3f800000,0x40000000,0x3f400000,0xc1000000,0,0x80000000,0x7f800000,0xff800000, + 0x7fc12345,0x7f812345,1,0x007fffff,0x80000001,0x00800000,0x7f7fffff,0x3e800000}; + const uint64_t source64[8]={ + UINT64_C(0x3ff0000000000000),UINT64_C(0x4000000000000000),UINT64_C(0x3fe8000000000000),UINT64_C(0xc020000000000000), + 0,1,UINT64_C(0x000fffffffffffff),UINT64_C(0x8000000000000001)}; + uint32_t old32[16]; uint64_t old64[8]; + const uint64_t upper[2]={UINT64_C(0x1122334455667788),UINT64_C(0x99aabbccddeeff00)}; + uint8_t out[545]={0}, outDaz[545]={0}; const uint64_t mask=UINT64_C(0xa55a); + for (int i=0;i<16;i++) old32[i]=UINT32_C(0x41000000)+(uint32_t)i; + for (int i=0;i<8;i++) old64[i]=UINT64_C(0x4020000000000000)+(uint64_t)i; + getexpsemantics(out,source32,source64,old32,old64,upper,mask); + unsigned csr=_mm_getcsr(); _mm_setcsr(csr|UINT32_C(0x40)); + getexpsemantics(outDaz,source32,source64,old32,old64,upper,mask); _mm_setcsr(csr); + for (int i=0;i<16;i++) { + uint32_t want=getexp32(source32[i],0), got; memcpy(&got,out+4*i,4); if (got!=want) return 10; + memcpy(&got,out+64+4*i,4); if (got!=(((mask>>i)&1)?want:old32[i])) return 11; + memcpy(&got,out+128+4*i,4); if (got!=(((mask>>i)&1)?want:0)) return 12; + memcpy(&got,out+192+4*i,4); if (got!=getexp32(source32[0],0)) return 13; + } + for (int i=0;i<8;i++) { + uint64_t want=getexp64(source64[i],0), got; memcpy(&got,out+256+8*i,8); if (got!=want) return 20; + memcpy(&got,out+320+8*i,8); if (got!=(((mask>>i)&1)?want:old64[i])) return 21; + memcpy(&got,out+384+8*i,8); if (got!=(((mask>>i)&1)?want:0)) return 22; + memcpy(&got,out+448+8*i,8); if (got!=getexp64(source64[0],0)) return 23; + } + uint32_t scalar32; memcpy(&scalar32,out+512,4); if (scalar32!=getexp32(source32[10],0)) return 30; + if (memcmp(out+516,(uint8_t*)upper+4,12)) return 31; + uint64_t scalar64; memcpy(&scalar64,out+528,8); if (scalar64!=getexp64(source64[5],0)) return 32; + if (memcmp(out+536,(uint8_t*)upper+8,8)) return 33; + if (out[544]!=1) return 34; + uint32_t daz32; memcpy(&daz32,outDaz+40,4); if (daz32!=UINT32_C(0xff800000)) return 40; + uint64_t daz64; memcpy(&daz64,outDaz+296,8); if (daz64!=UINT64_C(0xfff0000000000000)) return 41; + memcpy(&daz32,outDaz+512,4); if (daz32!=UINT32_C(0xff800000)) return 42; + memcpy(&daz64,outDaz+528,8); if (daz64!=UINT64_C(0xfff0000000000000)) return 43; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "getexp_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_getmant.go b/amd64_lower_getmant.go new file mode 100644 index 00000000..edc07c92 --- /dev/null +++ b/amd64_lower_getmant.go @@ -0,0 +1,190 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64GetMantSpec = amd64UnaryImmediateFloatingShape + +var amd64GetMantSpecs = map[Op]amd64GetMantSpec{ + "VGETMANTPS": {laneBits: 32}, + "VGETMANTPD": {laneBits: 64}, + "VGETMANTSS": {laneBits: 32, scalar: true}, + "VGETMANTSD": {laneBits: 64, scalar: true}, +} + +func (c *amd64Ctx) lowerGetMant(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64GetMantSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + form, err := c.parseUnaryImmediateFloatingForm(baseOp, suffix, spec, ins) + if err != nil { + return true, false, err + } + daz := c.loadMXCSRDAZ() + if spec.scalar { + return c.lowerScalarGetMant(spec, form.properties, form.source, form.passthrough, form.destination, form.mask, daz, form.immediate) + } + return c.lowerPackedGetMant(spec, form.properties, form.source, form.destination, form.byteWidth, form.mask, daz, form.immediate) +} + +func (c *amd64Ctx) lowerPackedGetMant(spec amd64GetMantSpec, properties amd64BinaryFloatingSuffix, source, destination Operand, byteWidth int, mask, daz string, immediate uint8) (bool, bool, error) { + lanes := byteWidth * 8 / spec.laneBits + input, err := c.loadPackedCompareLanes(source, byteWidth, spec.laneBits, properties.broadcast) + if err != nil { + return true, false, err + } + result := c.emitGetMantBits(lanes, spec.laneBits, input, daz, immediate) + if mask != "" { + oldBytes, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) lowerScalarGetMant(spec amd64GetMantSpec, properties amd64BinaryFloatingSuffix, source, passthrough, destination Operand, mask, daz string, immediate uint8) (bool, bool, error) { + sourceBits, err := c.loadFloatingScalarBits(source, spec.laneBits) + if err != nil { + return true, false, err + } + input := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", input, spec.laneBits, spec.laneBits, sourceBits) + result := c.emitGetMantBits(1, spec.laneBits, "%"+input, daz, immediate) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i%d> %s, i32 0\n", low, spec.laneBits, result) + passthroughBytes, err := c.loadX(passthrough.Reg) + if err != nil { + return true, false, err + } + base := c.bitcastVectorBytesToIntegerLanes(16, 128/spec.laneBits, spec.laneBits, passthroughBytes) + return true, false, c.storeVectorScalarRegister(destination.Reg, spec.laneBits, "%"+low, base, mask, properties.zeroing) +} + +func (c *amd64Ctx) emitGetMantBits(lanes, laneBits int, input, daz string, immediate uint8) string { + vectorType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + mantissaBits, bias := 23, 127 + exponentMask := uint64(0x7f800000) + mantissaMask := uint64(0x007fffff) + quietBit := uint64(0x00400000) + signBit := uint64(0x80000000) + indefinite := uint64(0xffc00000) + if laneBits == 64 { + mantissaBits, bias = 52, 1023 + exponentMask = uint64(0x7ff0000000000000) + mantissaMask = uint64(0x000fffffffffffff) + quietBit = uint64(0x0008000000000000) + signBit = uint64(0x8000000000000000) + indefinite = uint64(0xfff8000000000000) + } + interval := immediate & 3 + signControl := immediate >> 2 & 3 + positiveOne := uint64(bias) << mantissaBits + signedOne := positiveOne + if signControl&1 == 0 { + signedOne |= signBit + } + dazClear := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i1 %s, false\n", dazClear, daz) + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + bits, exponent, mantissa, sign := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", bits, vectorType, input, lane) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", exponent, laneBits, bits, exponentMask) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", mantissa, laneBits, bits, mantissaMask) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", sign, laneBits, bits, signBit) + exponentZero, exponentOnes := c.newTmp(), c.newTmp() + mantissaZero, mantissaNonzero, negative := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", exponentZero, laneBits, exponent) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, %d\n", exponentOnes, laneBits, exponent, exponentMask) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", mantissaZero, laneBits, mantissa) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", mantissaNonzero, laneBits, mantissa) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", negative, laneBits, sign) + isNaN, isInfinity, isDenormal := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isNaN, exponentOnes, mantissaNonzero) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isInfinity, exponentOnes, mantissaZero) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isDenormal, exponentZero, mantissaNonzero) + activeDenormal := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", activeDenormal, isDenormal, dazClear) + zeroOrDAZ, effectiveZero := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %s\n", zeroOrDAZ, mantissaZero, daz) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", effectiveZero, exponentZero, zeroOrDAZ) + + leadingZeros, shiftCount, shifted, normalizedFraction := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i%d @llvm.ctlz.i%d(i%d %%%s, i1 false)\n", leadingZeros, laneBits, laneBits, laneBits, mantissa) + fmt.Fprintf(c.b, " %%%s = sub i%d %%%s, %d\n", shiftCount, laneBits, leadingZeros, laneBits-mantissaBits-1) + fmt.Fprintf(c.b, " %%%s = shl i%d %%%s, %%%s\n", shifted, laneBits, mantissa, shiftCount) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", normalizedFraction, laneBits, shifted, mantissaMask) + fraction := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", fraction, activeDenormal, laneBits, normalizedFraction, laneBits, mantissa) + exponentField, unbiasedNormal, unbiasedDenormal, unbiased := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i%d %%%s, %d\n", exponentField, laneBits, exponent, mantissaBits) + fmt.Fprintf(c.b, " %%%s = sub i%d %%%s, %d\n", unbiasedNormal, laneBits, exponentField, bias) + fmt.Fprintf(c.b, " %%%s = sub i%d 0, %%%s\n", unbiasedDenormal, laneBits, shiftCount) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", unbiased, activeDenormal, laneBits, unbiasedDenormal, laneBits, unbiasedNormal) + oddValue, odd := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, 1\n", oddValue, laneBits, unbiased) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", odd, laneBits, oddValue) + fractionTop, topSet := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", fractionTop, laneBits, fraction, quietBit) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", topSet, laneBits, fractionTop) + normalizedExponent := fmt.Sprintf("%d", bias) + switch interval { + case 1: + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d %d\n", selected, odd, laneBits, bias-1, laneBits, bias) + normalizedExponent = "%" + selected + case 2: + normalizedExponent = fmt.Sprintf("%d", bias-1) + case 3: + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d %d\n", selected, topSet, laneBits, bias-1, laneBits, bias) + normalizedExponent = "%" + selected + } + exponentBits, magnitude := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i%d %s, %d\n", exponentBits, laneBits, normalizedExponent, mantissaBits) + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %%%s\n", magnitude, laneBits, exponentBits, fraction) + computed := "%" + magnitude + if signControl&1 == 0 { + withSign := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %%%s\n", withSign, laneBits, magnitude, sign) + computed = "%" + withSign + } + zeroOrInfinity := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", zeroOrInfinity, effectiveZero, isInfinity) + specialOne := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d %d\n", specialOne, negative, laneBits, signedOne, laneBits, positiveOne) + withSpecial := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %s\n", withSpecial, zeroOrInfinity, laneBits, specialOne, laneBits, computed) + selected := "%" + withSpecial + if signControl&2 != 0 { + notZero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", notZero, effectiveZero) + nonzeroNegative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", nonzeroNegative, negative, notZero) + indefiniteResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d %s\n", indefiniteResult, nonzeroNegative, laneBits, indefinite, laneBits, selected) + selected = "%" + indefiniteResult + } + quietNaN := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %d\n", quietNaN, laneBits, bits, quietBit) + final := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %s\n", final, isNaN, laneBits, quietNaN, laneBits, selected) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %%%s, i32 %d\n", inserted, vectorType, result, laneBits, final, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_getmant_test.go b/amd64_lower_getmant_test.go new file mode 100644 index 00000000..c7fbd93f --- /dev/null +++ b/amd64_lower_getmant_test.go @@ -0,0 +1,306 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64GetMantGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64GetMantSpec{ + "VGETMANTPS": {laneBits: 32}, + "VGETMANTPD": {laneBits: 64}, + "VGETMANTSS": {laneBits: 32, scalar: true}, + "VGETMANTSD": {laneBits: 64, scalar: true}, + } + if len(amd64GetMantSpecs) != len(expected) { + t.Fatalf("GETMANT grammar has %d entries, want %d", len(amd64GetMantSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64GetMantSpecs[op]; !ok { + t.Errorf("GETMANT grammar omitted %s", op) + } else if got != want { + t.Errorf("GETMANT grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86GetMantCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT getmantforms(SB),$0-0\n") + for _, op := range []string{"VGETMANTPS", "VGETMANTPD"} { + for _, width := range []string{"X", "Y", "Z"} { + last := 31 + if target.goarch == "386" && width == "Z" { + last = 7 + } + fmt.Fprintf(&source, "\t%s $0, %s1, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s $255, 8(AX), %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST $1, 16(AX), %s%d\n", op, width, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s $2, %s1, K1, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s.Z $3, 24(AX), K2, %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST.Z $4, 32(AX), K3, %s%d\n", op, width, last) + } + if width == "Z" { + fmt.Fprintf(&source, "\t%s.SAE $5, Z1, Z%d\n", op, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.SAE.Z $6, Z1, K4, Z%d\n", op, last) + } + } + } + } + if target.goarch == "amd64" { + for _, op := range []string{"VGETMANTSS", "VGETMANTSD"} { + fmt.Fprintf(&source, "\t%s $0, X1, X2, X31\n", op) + fmt.Fprintf(&source, "\t%s $255, 40(AX), X2, X31\n", op) + fmt.Fprintf(&source, "\t%s.SAE $1, X1, X2, X31\n", op) + fmt.Fprintf(&source, "\t%s $2, X1, X2, K5, X31\n", op) + fmt.Fprintf(&source, "\t%s.Z $3, 48(AX), X2, K6, X31\n", op) + fmt.Fprintf(&source, "\t%s.SAE.Z $4, X1, X2, K7, X31\n", op) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"getmantforms": {Name: "getmantforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "getmant-"+target.name+".ll", "getmant-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86GetMantRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VGETMANTPS $-1, X0, X1"}, + {goarch: "amd64", instruction: "VGETMANTPS $256, X0, X1"}, + {goarch: "amd64", instruction: "VGETMANTPS X0, X1"}, + {goarch: "amd64", instruction: "VGETMANTPS $0, X0, Y1"}, + {goarch: "amd64", instruction: "VGETMANTPS.BCST $0, X0, X1"}, + {goarch: "amd64", instruction: "VGETMANTPS.SAE $0, Z0, X1"}, + {goarch: "amd64", instruction: "VGETMANTPS.SAE $0, 0(AX), Z1"}, + {goarch: "amd64", instruction: "VGETMANTPS.RN_SAE $0, Z0, Z1"}, + {goarch: "amd64", instruction: "VGETMANTPS.Z $0, X0, X1"}, + {goarch: "amd64", instruction: "VGETMANTPS $0, X0, K0, X1"}, + {goarch: "amd64", instruction: "VGETMANTSS $0, Y0, X1, X2"}, + {goarch: "amd64", instruction: "VGETMANTSS.BCST $0, 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VGETMANTSD $0, X0, X1, Y2"}, + {goarch: "386", instruction: "VGETMANTSS $0, X0, X1, X2"}, + {goarch: "386", instruction: "VGETMANTPS $0, X0, K1, X2"}, + {goarch: "386", instruction: "VGETMANTPS $0, Z8, Z0"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's GETMANT table", test.instruction) + } + }) + } +} + +func TestAMD64GetMantRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + var source strings.Builder + source.WriteString(`TEXT getmantsemantics(SB),$0-56 + MOVQ out+0(FP), AX + MOVQ source32+8(FP), BX + MOVQ source64+16(FP), CX + MOVQ old32+24(FP), DX + MOVQ old64+32(FP), R8 + MOVQ upper+40(FP), R9 + MOVQ mask+48(FP), R10 + KMOVQ R10, K1 + STC +`) + for immediate := 0; immediate < 16; immediate++ { + fmt.Fprintf(&source, "\tVGETMANTPS $%d, 0(BX), Z0\n", immediate) + fmt.Fprintf(&source, "\tVMOVDQU32 Z0, %d(AX)\n", immediate*64) + fmt.Fprintf(&source, "\tVGETMANTPD $%d, 0(CX), Z1\n", immediate) + fmt.Fprintf(&source, "\tVMOVDQU64 Z1, %d(AX)\n", 1024+immediate*64) + } + source.WriteString(` VMOVDQU32 0(DX), Z2 + VGETMANTPS $3, 0(BX), K1, Z2 + VMOVDQU32 Z2, 2048(AX) + VGETMANTPS.Z $3, 0(BX), K1, Z2 + VMOVDQU32 Z2, 2112(AX) + VGETMANTPS.BCST $5, 0(BX), Z2 + VMOVDQU32 Z2, 2176(AX) + VMOVDQU64 0(R8), Z3 + VGETMANTPD $3, 0(CX), K1, Z3 + VMOVDQU64 Z3, 2240(AX) + VGETMANTPD.Z $3, 0(CX), K1, Z3 + VMOVDQU64 Z3, 2304(AX) + VGETMANTPD.BCST $5, 0(CX), Z3 + VMOVDQU64 Z3, 2368(AX) + VMOVDQU64 0(R9), X4 + VGETMANTSS $11, 12(BX), X4, X5 + VMOVDQU64 X5, 2432(AX) + VGETMANTSD $11, 24(CX), X4, X6 + VMOVDQU64 X6, 2448(AX) + SETCS 2464(AX) + RET +`) + requireX86GoAssemblerResult(t, "amd64", source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"getmantsemantics": { + Name: "getmantsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + {Offset: 48, Type: I64, Index: 6, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +#include +extern void getmantsemantics(uint8_t *, const uint32_t *, const uint64_t *, const uint32_t *, const uint64_t *, const uint64_t *, uint64_t); +static uint32_t getmant32(uint32_t u, unsigned imm, int daz) { + const uint32_t em=UINT32_C(0x7f800000), fm=UINT32_C(0x007fffff), qb=UINT32_C(0x00400000), sb=UINT32_C(0x80000000); + uint32_t exp=u&em, frac=u&fm, sign=u&sb; unsigned sc=(imm>>2)&3, interval=imm&3; + int nan=exp==em&&frac!=0, inf=exp==em&&frac==0, zero=exp==0&&(frac==0||daz), neg=sign!=0; + if (nan) return u|qb; + uint32_t one=UINT32_C(0x3f800000), signedOne=one|((sc&1)?0:sign); + if (neg && !zero && (sc&2)) return UINT32_C(0xffc00000); + if (zero||inf) return neg?signedOne:one; + int unbiased; + if (exp==0) { int shift=__builtin_clz(frac)-8; frac=(frac<>23)-127; + uint32_t outExp=127; + if (interval==1) outExp=(unbiased&1)?126:127; + else if (interval==2) outExp=126; + else if (interval==3) outExp=(frac&qb)?126:127; + return (outExp<<23)|frac|((sc&1)?0:sign); +} +static uint64_t getmant64(uint64_t u, unsigned imm, int daz) { + const uint64_t em=UINT64_C(0x7ff0000000000000), fm=UINT64_C(0x000fffffffffffff), qb=UINT64_C(0x0008000000000000), sb=UINT64_C(0x8000000000000000); + uint64_t exp=u&em, frac=u&fm, sign=u&sb; unsigned sc=(imm>>2)&3, interval=imm&3; + int nan=exp==em&&frac!=0, inf=exp==em&&frac==0, zero=exp==0&&(frac==0||daz), neg=sign!=0; + if (nan) return u|qb; + uint64_t one=UINT64_C(0x3ff0000000000000), signedOne=one|((sc&1)?0:sign); + if (neg && !zero && (sc&2)) return UINT64_C(0xfff8000000000000); + if (zero||inf) return neg?signedOne:one; + int unbiased; + if (exp==0) { int shift=__builtin_clzll(frac)-11; frac=(frac<>52)-1023; + uint64_t outExp=1023; + if (interval==1) outExp=(unbiased&1)?1022:1023; + else if (interval==2) outExp=1022; + else if (interval==3) outExp=(frac&qb)?1022:1023; + return (outExp<<52)|frac|((sc&1)?0:sign); +} +static uint32_t u32(const uint8_t *p) { uint32_t v; memcpy(&v,p,4); return v; } +static uint64_t u64(const uint8_t *p) { uint64_t v; memcpy(&v,p,8); return v; } +int main(void) { + const uint32_t source32[16]={ + 0x3f800000,0xbf800000,0x40400000,0xc0400000,0x3f400000,0xbf400000,0,0x80000000, + 0x7f800000,0xff800000,0x7fc12345,0xff812345,1,0x807fffff,0x00800000,0x7f7fffff}; + const uint64_t source64[8]={ + UINT64_C(0x3ff0000000000000),UINT64_C(0xbff0000000000000),UINT64_C(0x4008000000000000),UINT64_C(0xc008000000000000), + 0,UINT64_C(0x8000000000000000),UINT64_C(1),UINT64_C(0xfff0000000000000)}; + uint32_t old32[16]; uint64_t old64[8]; + const uint64_t upper[2]={UINT64_C(0x1122334455667788),UINT64_C(0x99aabbccddeeff00)}; + uint8_t out[2465]={0}, outDaz[2465]={0}; const uint64_t mask=UINT64_C(0xa55a); + for (int i=0;i<16;i++) old32[i]=UINT32_C(0x41000000)+(uint32_t)i; + for (int i=0;i<8;i++) old64[i]=UINT64_C(0x4020000000000000)+(uint64_t)i; + getmantsemantics(out,source32,source64,old32,old64,upper,mask); + unsigned csr=_mm_getcsr(); _mm_setcsr(csr|UINT32_C(0x40)); + getmantsemantics(outDaz,source32,source64,old32,old64,upper,mask); _mm_setcsr(csr); + for (unsigned imm=0;imm<16;imm++) { + for (int i=0;i<16;i++) { + if (u32(out+imm*64+i*4)!=getmant32(source32[i],imm,0)) return 10; + if (u32(outDaz+imm*64+i*4)!=getmant32(source32[i],imm,1)) return 11; + } + for (int i=0;i<8;i++) { + if (u64(out+1024+imm*64+i*8)!=getmant64(source64[i],imm,0)) return 12; + if (u64(outDaz+1024+imm*64+i*8)!=getmant64(source64[i],imm,1)) return 13; + } + } + for (int i=0;i<16;i++) { + uint32_t want=getmant32(source32[i],3,0); + if (u32(out+2048+i*4)!=(((mask>>i)&1)?want:old32[i])) return 20; + if (u32(out+2112+i*4)!=(((mask>>i)&1)?want:0)) return 21; + if (u32(out+2176+i*4)!=getmant32(source32[0],5,0)) return 22; + } + for (int i=0;i<8;i++) { + uint64_t want=getmant64(source64[i],3,0); + if (u64(out+2240+i*8)!=(((mask>>i)&1)?want:old64[i])) return 23; + if (u64(out+2304+i*8)!=(((mask>>i)&1)?want:0)) return 24; + if (u64(out+2368+i*8)!=getmant64(source64[0],5,0)) return 25; + } + if (u32(out+2432)!=getmant32(source32[3],11,0)) return 30; + if (memcmp(out+2436,(const uint8_t *)upper+4,12)) return 31; + if (u64(out+2448)!=getmant64(source64[3],11,0)) return 32; + if (memcmp(out+2456,(const uint8_t *)upper+8,8)) return 33; + if (out[2464]!=1) return 34; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "getmant_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_gfni.go b/amd64_lower_gfni.go new file mode 100644 index 00000000..b5c67cbc --- /dev/null +++ b/amd64_lower_gfni.go @@ -0,0 +1,248 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64GFNIMode uint8 + +const ( + amd64GFNIMultiply amd64GFNIMode = iota + amd64GFNIAffine + amd64GFNIAffineInverse +) + +type amd64GFNISpec struct { + mode amd64GFNIMode + immediate bool + broadcast bool +} + +// amd64GFNISpecs models the whole Go 1.27 GFNI family. VGF2P8MULB uses the +// eight _yvandnpd rows; both affine instructions use the eight +// _yvgf2p8affineinvqb rows, including qword broadcast for their matrix source. +var amd64GFNISpecs = map[Op]amd64GFNISpec{ + "VGF2P8MULB": {mode: amd64GFNIMultiply}, + "VGF2P8AFFINEQB": {mode: amd64GFNIAffine, immediate: true, broadcast: true}, + "VGF2P8AFFINEINVQB": {mode: amd64GFNIAffineInverse, immediate: true, broadcast: true}, +} + +func (c *amd64Ctx) lowerGFNI(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64GFNISpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s has a suffix absent from Go 1.27's GFNI table: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast && !spec.broadcast { + return true, false, fmt.Errorf("%s %s does not support broadcast: %q", c.goarch, baseOp, ins.Raw) + } + // The 386 assembler frontend can encode the three-operand multiply forms, + // but cannot represent the affine family's four-operand minimum. + if c.goarch == "386" && spec.immediate { + return true, false, fmt.Errorf("386 %s exceeds the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + + minimumArgs := 3 + if spec.immediate { + minimumArgs = 4 + } + if len(ins.Args) != minimumArgs && len(ins.Args) != minimumArgs+1 { + return true, false, fmt.Errorf("%s %s has the wrong operand count for Go 1.27's GFNI table: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == minimumArgs+1 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s masked form exceeds the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s.Z requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + + operandOffset := 0 + immediate := uint8(0) + if spec.immediate { + if !amd64UnsignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("%s %s expects an unsigned 8-bit immediate: %q", c.goarch, baseOp, ins.Raw) + } + immediate = uint8(ins.Args[0].Imm) + operandOffset = 1 + } + first := ins.Args[operandOffset] + second := ins.Args[operandOffset+1] + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's vector-register class: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoPackedVectorMoveRegister(second, byteWidth) { + return true, false, fmt.Errorf("%s %s second source must be a same-width vector register: %q", c.goarch, baseOp, ins.Raw) + } + if first.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(first, byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast && !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory matrix source: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + maskArg := ins.Args[len(ins.Args)-2] + if !amd64NonzeroKOperand(maskArg) { + return true, false, fmt.Errorf("%s %s masked form requires K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + firstBytes, err := c.loadGFNIFirstSource(first, byteWidth, broadcast) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadPackedCompareBytes(second, byteWidth) + if err != nil { + return true, false, err + } + computed := "" + switch spec.mode { + case amd64GFNIMultiply: + computed = c.emitGF2P8Multiply(byteWidth, firstBytes, secondBytes) + case amd64GFNIAffine, amd64GFNIAffineInverse: + if spec.mode == amd64GFNIAffineInverse { + secondBytes = c.emitGF2P8Inverse(byteWidth, secondBytes) + } + computed = c.emitGF2P8Affine(byteWidth, firstBytes, secondBytes, immediate) + } + if masked { + old, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + computed = amd64ApplyIntegerLaneMask(c, byteWidth, 8, computed, old, mask, zeroing) + } + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, computed) +} + +func (c *amd64Ctx) loadGFNIFirstSource(source Operand, byteWidth int, broadcast bool) (string, error) { + if !broadcast { + return c.loadPackedCompareBytes(source, byteWidth) + } + qwords, err := c.loadPackedCompareLanes(source, byteWidth, 64, true) + if err != nil { + return "", err + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", bytes, byteWidth/8, qwords, byteWidth) + return "%" + bytes, nil +} + +// emitGF2P8Multiply performs lane-wise carry-less multiplication reduced by +// x^8+x^4+x^3+x+1 (0x11b). Generic IR keeps translated programs runnable on +// hosts without GFNI while preserving exactly the instruction's byte lanes. +func (c *amd64Ctx) emitGF2P8Multiply(lanes int, first, second string) string { + vectorType := fmt.Sprintf("<%d x i8>", lanes) + result := "zeroinitializer" + multiplicand, multiplier := first, second + for bit := 0; bit < 8; bit++ { + lowBit := c.newTmp() + active := c.newTmp() + selected := c.newTmp() + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", lowBit, vectorType, multiplier, llvmSplatInteger(lanes, 8, 1)) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, zeroinitializer\n", active, vectorType, lowBit) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s zeroinitializer\n", selected, lanes, active, vectorType, multiplicand, vectorType) + fmt.Fprintf(c.b, " %%%s = xor %s %s, %%%s\n", combined, vectorType, result, selected) + result = "%" + combined + if bit == 7 { + break + } + highBit := c.newTmp() + reduce := c.newTmp() + shifted := c.newTmp() + reduced := c.newTmp() + nextMultiplicand := c.newTmp() + nextMultiplier := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", highBit, vectorType, multiplicand, llvmSplatInteger(lanes, 8, 0x80)) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, zeroinitializer\n", reduce, vectorType, highBit) + fmt.Fprintf(c.b, " %%%s = shl %s %s, %s\n", shifted, vectorType, multiplicand, llvmSplatInteger(lanes, 8, 1)) + fmt.Fprintf(c.b, " %%%s = xor %s %%%s, %s\n", reduced, vectorType, shifted, llvmSplatInteger(lanes, 8, 0x1b)) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %%%s, %s %%%s\n", nextMultiplicand, lanes, reduce, vectorType, reduced, vectorType, shifted) + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %s\n", nextMultiplier, vectorType, multiplier, llvmSplatInteger(lanes, 8, 1)) + multiplicand, multiplier = "%"+nextMultiplicand, "%"+nextMultiplier + } + return result +} + +func (c *amd64Ctx) emitGF2P8Inverse(lanes int, source string) string { + powers := make([]string, 7) + powers[0] = c.emitGF2P8Multiply(lanes, source, source) + for i := 1; i < len(powers); i++ { + powers[i] = c.emitGF2P8Multiply(lanes, powers[i-1], powers[i-1]) + } + result := powers[0] + for i := 1; i < len(powers); i++ { + result = c.emitGF2P8Multiply(lanes, result, powers[i]) + } + return result +} + +func (c *amd64Ctx) emitGF2P8Affine(lanes int, matrix, data string, immediate uint8) string { + vectorType := fmt.Sprintf("<%d x i8>", lanes) + result := "zeroinitializer" + for bit := 0; bit < 8; bit++ { + row := c.newTmp() + masked := c.newTmp() + parities := c.newTmp() + oneBit := c.newTmp() + positioned := c.newTmp() + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector %s %s, %s poison, <%d x i32> %s\n", row, vectorType, matrix, vectorType, lanes, llvmGFNIMatrixRowMask(lanes, bit)) + fmt.Fprintf(c.b, " %%%s = and %s %s, %%%s\n", masked, vectorType, data, row) + fmt.Fprintf(c.b, " %%%s = call %s @llvm.ctpop.v%di8(%s %%%s)\n", parities, vectorType, lanes, vectorType, masked) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %s\n", oneBit, vectorType, parities, llvmSplatInteger(lanes, 8, 1)) + fmt.Fprintf(c.b, " %%%s = shl %s %%%s, %s\n", positioned, vectorType, oneBit, llvmSplatInteger(lanes, 8, uint64(bit))) + fmt.Fprintf(c.b, " %%%s = or %s %s, %%%s\n", combined, vectorType, result, positioned) + result = "%" + combined + } + withImmediate := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, %s\n", withImmediate, vectorType, result, llvmSplatInteger(lanes, 8, uint64(immediate))) + return "%" + withImmediate +} + +func llvmGFNIMatrixRowMask(lanes, bit int) string { + var b strings.Builder + b.WriteByte('<') + for lane := 0; lane < lanes; lane++ { + if lane != 0 { + b.WriteString(", ") + } + fmt.Fprintf(&b, "i32 %d", lane/8*8+7-bit) + } + b.WriteByte('>') + return b.String() +} diff --git a/amd64_lower_gfni_test.go b/amd64_lower_gfni_test.go new file mode 100644 index 00000000..8c54ce2d --- /dev/null +++ b/amd64_lower_gfni_test.go @@ -0,0 +1,263 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64GFNIGrammarCoversCompleteGoFamilies(t *testing.T) { + expected := map[Op]amd64GFNISpec{ + "VGF2P8MULB": {mode: amd64GFNIMultiply}, + "VGF2P8AFFINEQB": {mode: amd64GFNIAffine, immediate: true, broadcast: true}, + "VGF2P8AFFINEINVQB": {mode: amd64GFNIAffineInverse, immediate: true, broadcast: true}, + } + if len(amd64GFNISpecs) != len(expected) { + t.Fatalf("GFNI grammar has %d entries, want %d", len(amd64GFNISpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64GFNISpecs[op]; !ok { + t.Errorf("GFNI grammar omitted %s", op) + } else if got != want { + t.Errorf("GFNI grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86GFNICompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT gfniforms(SB),$0-0\n") + for _, width := range []string{"X", "Y", "Z"} { + last := 31 + if target.goarch == "386" && width == "Z" { + last = 7 + } + fmt.Fprintf(&source, "\tVGF2P8MULB %s1, %s2, %s%d\n", width, width, width, last) + fmt.Fprintf(&source, "\tVGF2P8MULB 8(AX), %s2, %s%d\n", width, width, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\tVGF2P8AFFINEQB $0x63, %s1, %s2, %s%d\n", width, width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEQB $0x63, 16(AX), %s2, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEINVQB $0xa5, %s1, %s2, %s%d\n", width, width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEINVQB $0xa5, 24(AX), %s2, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEQB.BCST $0x63, 32(AX), %s2, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEINVQB.BCST $0xa5, 40(AX), %s2, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVGF2P8MULB %s1, %s2, K1, %s%d\n", width, width, width, last) + fmt.Fprintf(&source, "\tVGF2P8MULB.Z 48(AX), %s2, K2, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEQB $0x63, %s1, %s2, K3, %s%d\n", width, width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEQB.Z $0x63, 56(AX), %s2, K4, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEINVQB $0xa5, %s1, %s2, K5, %s%d\n", width, width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEINVQB.Z $0xa5, 64(AX), %s2, K6, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEQB.BCST.Z $0x63, 72(AX), %s2, K7, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVGF2P8AFFINEINVQB.BCST.Z $0xa5, 80(AX), %s2, K1, %s%d\n", width, width, last) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"gfniforms": {Name: "gfniforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "gfni-"+target.name+".ll", "gfni-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86GFNIRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VGF2P8MULB X0, Y1, Y2"}, + {goarch: "amd64", instruction: "VGF2P8MULB X0, X1, K0, X2"}, + {goarch: "amd64", instruction: "VGF2P8MULB.Z X0, X1, X2"}, + {goarch: "amd64", instruction: "VGF2P8MULB.BCST 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VGF2P8MULB X0, X1, 0(AX)"}, + {goarch: "amd64", instruction: "VGF2P8AFFINEQB $256, X0, X1, X2"}, + {goarch: "amd64", instruction: "VGF2P8AFFINEINVQB $1, X0, Y1, Y2"}, + {goarch: "amd64", instruction: "VGF2P8AFFINEQB.BCST $1, X0, X1, X2"}, + {goarch: "amd64", instruction: "VGF2P8AFFINEINVQB.Z.BCST $1, 0(AX), X1, K1, X2"}, + {goarch: "amd64", instruction: "VGF2P8AFFINEQB $1, X0, X1, K0, X2"}, + {goarch: "amd64", instruction: "VGF2P8AFFINEQB $1, X0, X1"}, + {goarch: "386", instruction: "VGF2P8MULB X0, X1, K1, X2"}, + {goarch: "386", instruction: "VGF2P8AFFINEQB $1, X0, X1, X2"}, + {goarch: "386", instruction: "VGF2P8MULB Z0, Z1, Z8"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's GFNI table", test.instruction) + } + }) + } +} + +func TestAMD64GFNIRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT gfnisemantics(SB),$0-48 + MOVQ out+0(FP), AX + MOVQ matrix+8(FP), BX + MOVQ data+16(FP), CX + MOVQ other+24(FP), DX + MOVQ old+32(FP), R8 + MOVQ mask+40(FP), R9 + KMOVQ R9, K1 + VMOVDQU64 0(BX), Z0 + VMOVDQU64 0(CX), Z1 + VMOVDQU64 0(DX), Z2 + VMOVDQU64 0(R8), Z3 + STC + VGF2P8MULB Z2, Z1, Z4 + VMOVDQU64 Z4, 0(AX) + VGF2P8AFFINEQB $0x63, Z0, Z1, Z4 + VMOVDQU64 Z4, 64(AX) + VGF2P8AFFINEINVQB $0xa5, Z0, Z1, Z4 + VMOVDQU64 Z4, 128(AX) + VGF2P8MULB Z2, Z1, K1, Z3 + VMOVDQU64 Z3, 192(AX) + VGF2P8AFFINEQB.Z $0x63, Z0, Z1, K1, Z4 + VMOVDQU64 Z4, 256(AX) + VGF2P8AFFINEQB.BCST $0x63, 0(BX), Z1, Z4 + VMOVDQU64 Z4, 320(AX) + VMOVDQU64 0(R8), Z3 + VGF2P8AFFINEINVQB.BCST.Z $0xa5, 0(BX), Z1, K1, Z3 + VMOVDQU64 Z3, 384(AX) + VGF2P8MULB Z2, Z1, Z2 + VMOVDQU64 Z2, 448(AX) + SETCS 512(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"gfnisemantics": { + Name: "gfnisemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: I64, Index: 5, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void gfnisemantics(uint8_t *, const uint8_t *, const uint8_t *, const uint8_t *, const uint8_t *, uint64_t); +static uint8_t gf_mul(uint8_t a, uint8_t b) { + uint8_t r = 0; + for (int i = 0; i < 8; i++) { + if (b & 1) r ^= a; + uint8_t hi = a & 0x80; + a <<= 1; + if (hi) a ^= 0x1b; + b >>= 1; + } + return r; +} +static uint8_t gf_inv(uint8_t x) { + if (!x) return 0; + uint8_t r = 1, a = x; + for (unsigned e = 254; e; e >>= 1) { + if (e & 1) r = gf_mul(r, a); + a = gf_mul(a, a); + } + return r; +} +static unsigned parity8(uint8_t x) { + x ^= x >> 4; x &= 0xf; + return (0x6996u >> x) & 1u; +} +static uint8_t affine(const uint8_t *matrix, uint8_t x, uint8_t imm, int inverse) { + if (inverse) x = gf_inv(x); + uint8_t r = 0; + for (int bit = 0; bit < 8; bit++) r |= (uint8_t)(parity8(matrix[7-bit] & x) << bit); + return r ^ imm; +} +int main(void) { + uint8_t matrix[64], data[64], other[64], old[64], out[513] = {0}; + const uint64_t mask = UINT64_C(0xa55aa55af00f0ff0); + for (int i = 0; i < 64; i++) { + matrix[i] = (uint8_t)(0x81u + 29u * (unsigned)i); + data[i] = (uint8_t)(3u + 17u * (unsigned)i); + other[i] = (uint8_t)(7u + 11u * (unsigned)i); + old[i] = (uint8_t)(0xe0u - (unsigned)i); + } + gfnisemantics(out, matrix, data, other, old, mask); + for (int i = 0; i < 64; i++) { + const uint8_t mul = gf_mul(other[i], data[i]); + const uint8_t aq = affine(matrix + (i/8)*8, data[i], 0x63, 0); + const uint8_t ai = affine(matrix + (i/8)*8, data[i], 0xa5, 1); + if (out[i] != mul) return 10; + if (out[64+i] != aq) return 11; + if (out[128+i] != ai) return 12; + if (out[192+i] != (((mask>>i)&1) ? mul : old[i])) return 13; + if (out[256+i] != (((mask>>i)&1) ? aq : 0)) return 14; + if (out[320+i] != affine(matrix, data[i], 0x63, 0)) return 15; + if (out[384+i] != (((mask>>i)&1) ? affine(matrix, data[i], 0xa5, 1) : 0)) return 16; + if (out[448+i] != mul) return 17; + } + if (out[512] != 1) return 18; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "gfni_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_halt_test.go b/amd64_lower_halt_test.go new file mode 100644 index 00000000..7c9644d2 --- /dev/null +++ b/amd64_lower_halt_test.go @@ -0,0 +1,61 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateX86HLTCompleteGoAssemblerForms(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT haltforms(SB),NOSPLIT,$0-0\n\tHLT\n") + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"haltforms": {Name: "haltforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, `asm sideeffect "hlt"`) || !strings.Contains(ll, "unreachable") { + t.Fatalf("HLT must retain the hardware instruction and terminate control flow:\n%s", ll) + } + compileLLVMToObject(t, llc, target.triple, "hlt-"+target.name+".ll", "hlt-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86HLTRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{"HLT AX", "HLT $1", "HLT.P"} { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n") + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's HLT ynone table", instruction) + } + } +} diff --git a/amd64_lower_horizontal_float.go b/amd64_lower_horizontal_float.go new file mode 100644 index 00000000..314e8e2a --- /dev/null +++ b/amd64_lower_horizontal_float.go @@ -0,0 +1,147 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64HorizontalFloatingSpec struct { + laneBits int + subtract bool + vector bool +} + +// amd64HorizontalFloatingSpecs is the complete Go 1.27 horizontal +// floating-point add/subtract family. Legacy forms use yxm; V-prefixed forms +// use _yvaddsubpd and are deliberately limited to VEX X/Y registers. +var amd64HorizontalFloatingSpecs = map[Op]amd64HorizontalFloatingSpec{ + "HADDPS": {laneBits: 32}, + "HADDPD": {laneBits: 64}, + "HSUBPS": {laneBits: 32, subtract: true}, + "HSUBPD": {laneBits: 64, subtract: true}, + "VHADDPS": {laneBits: 32, vector: true}, + "VHADDPD": {laneBits: 64, vector: true}, + "VHSUBPS": {laneBits: 32, subtract: true, vector: true}, + "VHSUBPD": {laneBits: 64, subtract: true, vector: true}, +} + +func (c *amd64Ctx) lowerHorizontalFloating(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64HorizontalFloatingSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed forms in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if spec.vector { + return c.lowerVectorHorizontalFloating(baseOp, spec, ins) + } + return c.lowerLegacyHorizontalFloating(baseOp, spec, ins) +} + +func (c *amd64Ctx) lowerLegacyHorizontalFloating(baseOp string, spec amd64HorizontalFloatingSpec, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || !amd64VEXVectorRegister(ins.Args[1], 16) { + return true, false, fmt.Errorf("%s %s expects X/m128, X using Go 1.27's yxm table: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !amd64VEXVectorRegister(ins.Args[0], 16) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's X register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s source must be X or memory: %q", c.goarch, baseOp, ins.Raw) + } + first, err := c.loadHorizontalFloatingOperand(ins.Args[0], 16, spec.laneBits) + if err != nil { + return true, false, err + } + second, err := c.loadHorizontalFloatingOperand(ins.Args[1], 16, spec.laneBits) + if err != nil { + return true, false, err + } + result := c.emitHorizontalFloating(spec, 16, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <16 x i8>\n", out, amd64FMA3LLVMType(128/spec.laneBits, spec.laneBits), result) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) +} + +func (c *amd64Ctx) lowerVectorHorizontalFloating(baseOp string, spec amd64HorizontalFloatingSpec, ins Instr) (bool, bool, error) { + if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects src1, src2, destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(ins.Args[2].Reg) + if byteWidth != 16 && byteWidth != 32 { + return true, false, fmt.Errorf("%s %s destination must be a VEX X or Y register: %q", c.goarch, baseOp, ins.Raw) + } + if !amd64VEXVectorRegister(ins.Args[2], byteWidth) || !amd64VEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s second source and destination must be same-width Go 1.27 VEX registers: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !amd64VEXVectorRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match the destination's VEX register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + first, err := c.loadHorizontalFloatingOperand(ins.Args[0], byteWidth, spec.laneBits) + if err != nil { + return true, false, err + } + second, err := c.loadHorizontalFloatingOperand(ins.Args[1], byteWidth, spec.laneBits) + if err != nil { + return true, false, err + } + result := c.emitHorizontalFloating(spec, byteWidth, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", out, amd64FMA3LLVMType(byteWidth*8/spec.laneBits, spec.laneBits), result, byteWidth) + return true, false, c.storeVectorBytes(ins.Args[2].Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) loadHorizontalFloatingOperand(operand Operand, byteWidth, laneBits int) (string, error) { + bytesValue, err := c.loadPackedCompareBytes(operand, byteWidth) + if err != nil { + return "", err + } + lanes := byteWidth * 8 / laneBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", result, byteWidth, bytesValue, amd64FMA3LLVMType(lanes, laneBits)) + return "%" + result, nil +} + +func (c *amd64Ctx) emitHorizontalFloating(spec amd64HorizontalFloatingSpec, byteWidth int, first, second string) string { + lanes := byteWidth * 8 / spec.laneBits + lanesPer128 := 128 / spec.laneBits + typeName := amd64FMA3LLVMType(lanes, spec.laneBits) + elementType := amd64FMA3LLVMType(1, spec.laneBits) + result := "poison" + for lane := 0; lane < lanes; lane++ { + position := lane % lanesPer128 + block := lane - position + source := second + pair := position + if position >= lanesPer128/2 { + source = first + pair -= lanesPer128 / 2 + } + leftIndex := block + 2*pair + rightIndex := leftIndex + 1 + left := c.newTmp() + right := c.newTmp() + value := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", left, typeName, source, leftIndex) + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", right, typeName, source, rightIndex) + operation := "fadd" + if spec.subtract { + operation = "fsub" + } + fmt.Fprintf(c.b, " %%%s = %s %s %%%s, %%%s\n", value, operation, elementType, left, right) + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, %s %%%s, i32 %d\n", inserted, typeName, result, elementType, value, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_horizontal_integer.go b/amd64_lower_horizontal_integer.go new file mode 100644 index 00000000..2ac194af --- /dev/null +++ b/amd64_lower_horizontal_integer.go @@ -0,0 +1,207 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64HorizontalIntegerSpec struct { + laneBits int + subtract bool + saturate bool + vector bool + allowMMX bool +} + +// amd64HorizontalIntegerSpecs covers the complete Go 1.27 PHADD/PHSUB +// family. PHADDD's legacy ymmxmm0f38 table uniquely includes MMX; the other +// legacy operations use yxm_q4. All V-prefixed operations use _yvaddsubpd, +// which has only VEX X/Y rows. +var amd64HorizontalIntegerSpecs = map[Op]amd64HorizontalIntegerSpec{ + "PHADDD": {laneBits: 32, allowMMX: true}, + "PHADDSW": {laneBits: 16, saturate: true}, + "PHADDW": {laneBits: 16}, + "PHSUBD": {laneBits: 32, subtract: true}, + "PHSUBSW": {laneBits: 16, subtract: true, saturate: true}, + "PHSUBW": {laneBits: 16, subtract: true}, + "VPHADDD": {laneBits: 32, vector: true}, + "VPHADDSW": {laneBits: 16, saturate: true, vector: true}, + "VPHADDW": {laneBits: 16, vector: true}, + "VPHSUBD": {laneBits: 32, subtract: true, vector: true}, + "VPHSUBSW": {laneBits: 16, subtract: true, saturate: true, vector: true}, + "VPHSUBW": {laneBits: 16, subtract: true, vector: true}, +} + +func (c *amd64Ctx) lowerHorizontalInteger(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64HorizontalIntegerSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed forms in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if spec.vector { + return c.lowerVectorHorizontalInteger(baseOp, spec, ins) + } + return c.lowerLegacyHorizontalInteger(baseOp, spec, ins) +} + +func (c *amd64Ctx) lowerLegacyHorizontalInteger(baseOp string, spec amd64HorizontalIntegerSpec, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects packed source and destination: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[1].Reg + if _, mmx := amd64ParseMReg(destination); mmx { + if !spec.allowMMX { + return true, false, fmt.Errorf("%s %s has no MMX form in Go 1.27's yxm_q4 table: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if _, ok := amd64ParseMReg(ins.Args[0].Reg); !ok { + return true, false, fmt.Errorf("%s %s MMX form requires an MMX source: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s MMX form requires MMX or memory source: %q", c.goarch, baseOp, ins.Raw) + } + firstBits, err := c.loadLegacyMMXPackedSource(ins.Args[0]) + if err != nil { + return true, false, err + } + secondBits, err := c.loadReg(destination) + if err != nil { + return true, false, err + } + first := c.bitcastI64ToIntegerLanes(2, 32, firstBits) + second := c.bitcastI64ToIntegerLanes(2, 32, secondBits) + result := c.emitHorizontalInteger(spec, 8, first, second) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i32> %s to i64\n", bits, result) + return true, false, c.storeReg(destination, "%"+bits) + } + + if !c.isGoLegacyXReg(destination) { + return true, false, fmt.Errorf("%s %s destination must be an in-range X register: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s source must be an in-range X register or memory: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s source must be an in-range X register or memory: %q", c.goarch, baseOp, ins.Raw) + } + first, err := c.loadHorizontalIntegerOperand(ins.Args[0], 16, spec.laneBits) + if err != nil { + return true, false, err + } + second, err := c.loadHorizontalIntegerOperand(ins.Args[1], 16, spec.laneBits) + if err != nil { + return true, false, err + } + result := c.emitHorizontalInteger(spec, 16, first, second) + lanes := 128 / spec.laneBits + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, lanes, spec.laneBits, result) + return true, false, c.storeX(destination, "%"+out) +} + +func (c *amd64Ctx) lowerVectorHorizontalInteger(baseOp string, spec amd64HorizontalIntegerSpec, ins Instr) (bool, bool, error) { + if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects source2, source1, destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(ins.Args[2].Reg) + if byteWidth != 16 && byteWidth != 32 || + !c.isGoVEXVectorRegister(ins.Args[2], byteWidth, false) || + !c.isGoVEXVectorRegister(ins.Args[1], byteWidth, false) || + !c.isGoVEXVectorRegister(ins.Args[0], byteWidth, true) { + return true, false, fmt.Errorf("%s %s requires matching in-range VEX X/Y sources and destination: %q", c.goarch, baseOp, ins.Raw) + } + first, err := c.loadHorizontalIntegerOperand(ins.Args[0], byteWidth, spec.laneBits) + if err != nil { + return true, false, err + } + second, err := c.loadHorizontalIntegerOperand(ins.Args[1], byteWidth, spec.laneBits) + if err != nil { + return true, false, err + } + result := c.emitHorizontalInteger(spec, byteWidth, first, second) + lanes := byteWidth * 8 / spec.laneBits + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(ins.Args[2].Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) loadHorizontalIntegerOperand(operand Operand, byteWidth, laneBits int) (string, error) { + bytesValue, err := c.loadPackedCompareBytes(operand, byteWidth) + if err != nil { + return "", err + } + lanes := byteWidth * 8 / laneBits + return c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, bytesValue), nil +} + +func (c *amd64Ctx) emitHorizontalInteger(spec amd64HorizontalIntegerSpec, byteWidth int, first, second string) string { + lanes := byteWidth * 8 / spec.laneBits + lanesPer128 := 128 / spec.laneBits + // The legacy MMX PHADDD row is one 64-bit lane group rather than one + // 128-bit group, but the same half-from-each-source construction applies. + if byteWidth == 8 { + lanesPer128 = lanes + } + typeName := fmt.Sprintf("<%d x i%d>", lanes, spec.laneBits) + elementType := fmt.Sprintf("i%d", spec.laneBits) + result := "poison" + for lane := 0; lane < lanes; lane++ { + position := lane % lanesPer128 + block := lane - position + source := second + pair := position + if position >= lanesPer128/2 { + source = first + pair -= lanesPer128 / 2 + } + leftIndex := block + 2*pair + rightIndex := leftIndex + 1 + left := c.newTmp() + right := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", left, typeName, source, leftIndex) + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", right, typeName, source, rightIndex) + value := c.emitHorizontalIntegerPair(spec, "%"+left, "%"+right) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, %s %s, i32 %d\n", inserted, typeName, result, elementType, value, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) emitHorizontalIntegerPair(spec amd64HorizontalIntegerSpec, left, right string) string { + operation := "add" + if spec.subtract { + operation = "sub" + } + if !spec.saturate { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s i%d %s, %s\n", value, operation, spec.laneBits, left, right) + return "%" + value + } + leftWide := c.newTmp() + rightWide := c.newTmp() + value := c.newTmp() + below := c.newTmp() + lowerClamped := c.newTmp() + above := c.newTmp() + clamped := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext i16 %s to i32\n", leftWide, left) + fmt.Fprintf(c.b, " %%%s = sext i16 %s to i32\n", rightWide, right) + fmt.Fprintf(c.b, " %%%s = %s i32 %%%s, %%%s\n", value, operation, leftWide, rightWide) + fmt.Fprintf(c.b, " %%%s = icmp slt i32 %%%s, -32768\n", below, value) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 -32768, i32 %%%s\n", lowerClamped, below, value) + fmt.Fprintf(c.b, " %%%s = icmp sgt i32 %%%s, 32767\n", above, lowerClamped) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 32767, i32 %%%s\n", clamped, above, lowerClamped) + fmt.Fprintf(c.b, " %%%s = trunc i32 %%%s to i16\n", result, clamped) + return "%" + result +} diff --git a/amd64_lower_horizontal_integer_test.go b/amd64_lower_horizontal_integer_test.go new file mode 100644 index 00000000..c724b14c --- /dev/null +++ b/amd64_lower_horizontal_integer_test.go @@ -0,0 +1,114 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86HorizontalIntegerCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 15 + if target.goarch == "386" { + last = 7 + } + var source strings.Builder + source.WriteString("TEXT horizontalintegerforms(SB),NOSPLIT,$0-0\n") + // PHADDD uniquely uses Go's ymmxmm0f38 table and therefore has + // both MMX/m64 and XMM/m128 legacy rows. + source.WriteString("\tPHADDD M0, M1\n\tPHADDD 8(AX), M2\n") + for _, op := range []string{"PHADDD", "PHADDSW", "PHADDW", "PHSUBD", "PHSUBSW", "PHSUBW"} { + fmt.Fprintf(&source, "\t%s X0, X%d\n", op, last) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, last) + vector := "V" + op + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&source, "\t%s %s0, %s1, %s%d\n", vector, width, width, width, last) + fmt.Fprintf(&source, "\t%s 8(AX), %s1, %s%d\n", vector, width, width, last) + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "horizontalintegerforms": {Name: "horizontalintegerforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "horizontal-integer-"+target.name+".ll", "horizontal-integer-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86HorizontalIntegerRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PHADDD.Z X0, X1", + "PHADDD X0", + "PHADDSW M0, M1", + "PHADDW M0, M1", + "PHSUBD M0, M1", + "PHSUBSW M0, M1", + "PHSUBW M0, M1", + "PHADDW X0, M1", + "PHSUBD Y0, Y1", + "VPHADDD.Z X0, X1, X2", + "VPHADDSW X0, X1", + "VPHADDW X0, Y1, Y2", + "VPHSUBD Z0, Z1, Z2", + "VPHSUBSW X0, X1, K1, X2", + "VPHSUBW X0, X1, (AX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86HorizontalIntegerRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PHADDD X8, X0", + "PHADDW X0, X8", + "VPHADDD X8, X1, X2", + "VPHADDSW X0, X8, X2", + "VPHADDW X0, X1, X8", + "VPHSUBD Y8, Y1, Y2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86HorizontalIntegerRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86HorizontalIntegerRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's horizontal-integer forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_ifma.go b/amd64_lower_ifma.go new file mode 100644 index 00000000..6c4ee233 --- /dev/null +++ b/amd64_lower_ifma.go @@ -0,0 +1,138 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64IFMASpec struct { + high bool +} + +// amd64IFMASpecs is the complete Go 1.27 integer fused multiply-add family. +// Both instructions use _yvblendmpd and operate on the low unsigned 52 bits +// of each qword source. LUQ adds product bits 51:0; HUQ adds bits 103:52. +var amd64IFMASpecs = map[Op]amd64IFMASpec{ + "VPMADD52HUQ": {high: true}, + "VPMADD52LUQ": {}, +} + +func (c *amd64Ctx) lowerIFMA(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64IFMASpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix || properties.sae || properties.rounding != "" { + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's _yvblendmpd encoding: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects source2, source1, [K mask,] accumulator: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7 as its third operand: %q", c.goarch, baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s accumulator must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || + !c.isGoPackedVectorMoveRegister(destination, byteWidth) || + !c.isGoPackedVectorMoveRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s source1 and accumulator must be matching Go vector registers: %q", c.goarch, baseOp, ins.Raw) + } + rmSource := ins.Args[0] + if properties.broadcast { + if !isAMD64MemoryOperand(rmSource) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory source2: %q", c.goarch, baseOp, ins.Raw) + } + } else if rmSource.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(rmSource, byteWidth) { + return true, false, fmt.Errorf("%s %s source2 register must match the accumulator width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(rmSource) { + return true, false, fmt.Errorf("%s %s source2 must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := byteWidth / 8 + first, err := c.loadPackedCompareLanes(rmSource, byteWidth, 64, properties.broadcast) + if err != nil { + return true, false, err + } + second, err := c.loadPackedCompareLanes(ins.Args[1], byteWidth, 64, false) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 64, oldBytes) + computed := c.emitIFMA(spec, lanes, first, second, old) + if masked { + mask, loadErr := c.loadK(ins.Args[2].Reg) + if loadErr != nil { + return true, false, loadErr + } + computed = amd64ApplyIntegerLaneMask(c, lanes, 64, computed, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", out, lanes, computed, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitIFMA(spec amd64IFMASpec, lanes int, first, second, accumulator string) string { + const low52Mask = "4503599627370495" + result := "poison" + for lane := 0; lane < lanes; lane++ { + firstLane := c.newTmp() + secondLane := c.newTmp() + oldLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %s, i32 %d\n", firstLane, lanes, first, lane) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %s, i32 %d\n", secondLane, lanes, second, lane) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %s, i32 %d\n", oldLane, lanes, accumulator, lane) + maskedFirst := c.newTmp() + maskedSecond := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, %s\n", maskedFirst, firstLane, low52Mask) + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, %s\n", maskedSecond, secondLane, low52Mask) + wideFirst := c.newTmp() + wideSecond := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i64 %%%s to i128\n", wideFirst, maskedFirst) + fmt.Fprintf(c.b, " %%%s = zext i64 %%%s to i128\n", wideSecond, maskedSecond) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i128 %%%s, %%%s\n", product, wideFirst, wideSecond) + selected := "%" + product + if spec.high { + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i128 %%%s, 52\n", high, product) + selected = "%" + high + } else { + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i128 %%%s, %s\n", low, product, low52Mask) + selected = "%" + low + } + productPart := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i128 %s to i64\n", productPart, selected) + added := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %%%s, %%%s\n", added, oldLane, productPart) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i64> %s, i64 %%%s, i32 %d\n", inserted, lanes, result, added, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_ifma_test.go b/amd64_lower_ifma_test.go new file mode 100644 index 00000000..02e57880 --- /dev/null +++ b/amd64_lower_ifma_test.go @@ -0,0 +1,225 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86IFMACompleteGo127Forms(t *testing.T) { + // VPMADD52HUQ/LUQ share Go 1.27's six-row _yvblendmpd table: X/Y/Z, + // each with an unmasked and K1-K7 masked row. Their EVEX attributes add + // scalar qword broadcast and zeroing. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT ifma_forms(SB),$0-0\n") + for _, op := range []string{"VPMADD52HUQ", "VPMADD52LUQ"} { + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&source, "\t%s %s0, %s1, %s2\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s 8(BX), %s3, %s4\n", op, width, width) + fmt.Fprintf(&source, "\t%s.BCST 16(BX), %s5, %s6\n", op, width, width) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s %s20, %s21, K1, %s22\n", op, width, width, width) + fmt.Fprintf(&source, "\t%s.Z 24(BX), %s23, K7, %s24\n", op, width, width) + fmt.Fprintf(&source, "\t%s.BCST.Z 32(BX), %s25, K2, %s26\n", op, width, width) + } + } + } + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "ifma_forms": {Name: "ifma_forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "ifma-"+target.name+".ll", "ifma-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86IFMARejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "VPMADD52HUQ X0, X1", + "VPMADD52LUQ X0, X1, X2, X3, X4", + "VPMADD52HUQ Y0, X1, X2", + "VPMADD52LUQ X0, Y1, X2", + "VPMADD52HUQ X0, X1, Y2", + "VPMADD52LUQ X0, 8(BX), X2", + "VPMADD52HUQ X0, X1, 8(BX)", + "VPMADD52LUQ X0, X1, K0, X2", + "VPMADD52HUQ X0, K1, X1, X2", + "VPMADD52LUQ.Z X0, X1, X2", + "VPMADD52HUQ.BCST X0, X1, X2", + "VPMADD52LUQ.BCST.Z 8(BX), X1, X2", + "VPMADD52HUQ.Z.BCST 8(BX), X1, K1, X2", + "VPMADD52LUQ.SAE X0, X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's IFMA table", instruction) + } + }) + } + for _, instruction := range []string{ + "VPMADD52HUQ X0, X1, K1, X2", + "VPMADD52LUQ.Z 8(BX), Y1, K7, Y2", + "VPMADD52HUQ.BCST.Z 16(BX), Z1, K2, Z2", + "VPMADD52LUQ Z8, Z0, Z1", + "VPMADD52HUQ Z0, Z8, Z1", + "VPMADD52LUQ Z0, Z1, Z8", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "386", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + Goarch: "386", + TargetTriple: "i386-unknown-linux-gnu", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted 386 %q outside Go 1.27's IFMA frontend boundary", instruction) + } + }) + } +} + +func TestAMD64IFMARuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT ifmaSemantics(SB),$0-48 + MOVQ out+0(FP), AX + MOVQ first+8(FP), BX + MOVQ second+16(FP), CX + MOVQ accumulator+24(FP), DX + MOVQ scalar+32(FP), SI + VMOVDQU64 (BX), X0 + VMOVDQU64 (CX), X1 + VMOVDQU64 (DX), X2 + VPMADD52LUQ X0, X1, X2 + VMOVDQU64 X2, 0(AX) + VMOVDQU64 (DX), X3 + VPMADD52HUQ X0, X1, X3 + VMOVDQU64 X3, 16(AX) + KMOVQ mask+40(FP), K1 + VMOVDQU64 (DX), X4 + VPMADD52LUQ X0, X1, K1, X4 + VMOVDQU64 X4, 32(AX) + VMOVDQU64 (DX), X5 + VPMADD52LUQ.Z X0, X1, K1, X5 + VMOVDQU64 X5, 48(AX) + VMOVDQU64 (DX), X6 + VPMADD52LUQ.BCST (SI), X1, X6 + VMOVDQU64 X6, 64(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: I64, Index: 5, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "ifmaSemantics": { + Name: "ifmaSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, I64}, + Ret: Void, + Frame: frame, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void ifmaSemantics(uint64_t *, const uint64_t *, const uint64_t *, const uint64_t *, const uint64_t *, uint64_t); +static const uint64_t mask52 = (((uint64_t)1) << 52) - 1; +static uint64_t lo(uint64_t a, uint64_t b) { + return (uint64_t)((((unsigned __int128)(a & mask52)) * (b & mask52)) & mask52); +} +static uint64_t hi(uint64_t a, uint64_t b) { + return (uint64_t)((((unsigned __int128)(a & mask52)) * (b & mask52)) >> 52); +} +int main(void) { + const uint64_t first[2] = {(UINT64_C(1) << 60) | mask52, (UINT64_C(1) << 55) | (UINT64_C(1) << 51) | 3}; + const uint64_t second[2] = {(UINT64_C(1) << 59) | mask52, (UINT64_C(1) << 58) | (UINT64_C(1) << 51) | 5}; + const uint64_t accumulator[2] = {UINT64_MAX - 15, 100}; + const uint64_t scalar = (UINT64_C(1) << 63) | 7; + uint64_t out[10] = {0}; + const uint64_t want[10] = { + accumulator[0] + lo(first[0], second[0]), accumulator[1] + lo(first[1], second[1]), + accumulator[0] + hi(first[0], second[0]), accumulator[1] + hi(first[1], second[1]), + accumulator[0] + lo(first[0], second[0]), accumulator[1], + accumulator[0] + lo(first[0], second[0]), 0, + accumulator[0] + lo(scalar, second[0]), accumulator[1] + lo(scalar, second[1]), + }; + ifmaSemantics(out, first, second, accumulator, &scalar, 1); + for (int i = 0; i < 10; i++) if (out[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "ifma", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_implicit_legacy_test.go b/amd64_lower_implicit_legacy_test.go new file mode 100644 index 00000000..bd6db908 --- /dev/null +++ b/amd64_lower_implicit_legacy_test.go @@ -0,0 +1,177 @@ +package plan9asm + +import ( + "reflect" + "runtime" + "strings" + "testing" +) + +func TestAMD64LeaveGrammarIsComplete(t *testing.T) { + want := map[Op]amd64LeaveSpec{ + "LEAVEW": {bits: 16}, + "LEAVEL": {bits: 32}, + "LEAVEQ": {bits: 64}, + } + if !reflect.DeepEqual(amd64LeaveSpecs, want) { + t.Fatalf("LEAVE grammar = %+v, want %+v", amd64LeaveSpecs, want) + } +} + +func TestTranslateX86LeaveAndXLATCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + secondLeave := "LEAVEQ" + if target.goarch == "386" { + secondLeave = "LEAVEL" + } + source := "TEXT implicitlegacyforms(SB),$0-0\n" + + "\tLEAVEW\n" + + "\t" + secondLeave + "\n" + + "\tXLAT\n" + + "\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "implicitlegacyforms": {Name: "implicitlegacyforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load i16", "load i8", "getelementptr i8", "-256"} { + if !strings.Contains(ir, want) { + t.Errorf("IR is missing %s:\n%s", want, ir) + } + } + if target.goarch == "386" { + if !strings.Contains(ir, "load i32") { + t.Errorf("386 IR is missing LEAVEL load:\n%s", ir) + } + } else if !strings.Contains(ir, "load i64") { + t.Errorf("amd64 IR is missing LEAVEQ load:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "implicit-legacy-"+target.name+".ll", "implicit-legacy-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86LeaveAndXLATRejectFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "LEAVEW AX"}, + {goarch: "amd64", instruction: "LEAVEL"}, + {goarch: "amd64", instruction: "LEAVEQ.P"}, + {goarch: "amd64", instruction: "XLAT AX"}, + {goarch: "amd64", instruction: "XLAT.P"}, + {goarch: "386", instruction: "LEAVEQ"}, + {goarch: "386", instruction: "LEAVEL AX"}, + {goarch: "386", instruction: "XLAT AX"}, + } { + t.Run(test.goarch+"_"+strings.ReplaceAll(test.instruction, " ", "_"), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's LEAVE/XLAT tables", test.instruction) + } + }) + } +} + +func TestAMD64LeaveAndXLATRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT implicitlegacysemantics(SB),NOSPLIT,$0-16 + MOVQ out+0(FP), R8 + MOVQ data+8(FP), BP + LEAVEQ + MOVQ BP, 0(R8) + MOVQ SP, 8(R8) + MOVQ data+8(FP), BX + ADDQ $16, BX + MOVQ $0x1122334455667703, AX + XLAT + MOVQ AX, 16(R8) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{ + "implicitlegacysemantics": { + Name: "implicitlegacysemantics", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void implicitlegacysemantics(uint8_t *, uint8_t *); +static uint64_t load64(const uint8_t *p) { uint64_t v; memcpy(&v,p,8); return v; } +int main(void) { + uint8_t data[256] = {0}, out[24] = {0}; + const uint64_t saved = UINT64_C(0xa1b2c3d4e5f60718); memcpy(data,&saved,8); + data[19] = 0xaa; + implicitlegacysemantics(out,data); + if (load64(out) != saved) return 10; + if (load64(out+8) != (uintptr_t)(data+8)) return 11; + if (load64(out+16) != UINT64_C(0x11223344556677aa)) return 12; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "implicit_legacy_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_implicit_mask_move.go b/amd64_lower_implicit_mask_move.go new file mode 100644 index 00000000..b87df78e --- /dev/null +++ b/amd64_lower_implicit_mask_move.go @@ -0,0 +1,93 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64ImplicitMaskMoveSpec struct { + byteWidth int + vector bool +} + +// Go's frontend exposes the legacy SSE spelling both as MASKMOVOU and via +// the Intel-name alias MASKMOVDQU. MASKMOVQ is the corresponding MMX form; +// VMASKMOVDQU is the VEX spelling. All use the first operand as a byte mask, +// the second as data, and DI as the implicit memory destination. +var amd64ImplicitMaskMoveSpecs = map[Op]amd64ImplicitMaskMoveSpec{ + "MASKMOVQ": {byteWidth: 8}, + "MASKMOVOU": {byteWidth: 16}, + "MASKMOVDQU": {byteWidth: 16}, + "VMASKMOVDQU": {byteWidth: 16, vector: true}, +} + +func (c *amd64Ctx) lowerImplicitMaskMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64ImplicitMaskMoveSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed forms in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects mask and data registers: %q", c.goarch, baseOp, ins.Raw) + } + if spec.byteWidth == 8 { + for _, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s uses Go's MMX-register-only ymr table: %q", c.goarch, baseOp, ins.Raw) + } + if _, ok := amd64ParseMReg(arg.Reg); !ok { + return true, false, fmt.Errorf("%s %s uses Go's MMX-register-only ymr table: %q", c.goarch, baseOp, ins.Raw) + } + } + maskBits, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + dataBits, err := c.loadReg(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + mask := c.bitcastI64ToIntegerLanes(8, 8, maskBits) + data := c.bitcastI64ToIntegerLanes(8, 8, dataBits) + return true, false, c.emitImplicitByteMaskStore(data, mask, 8) + } + + valid := func(arg Operand) bool { + if spec.vector { + return c.isGoVEXVectorRegister(arg, 16, false) + } + return arg.Kind == OpReg && c.isGoLegacyXReg(arg.Reg) + } + if !valid(ins.Args[0]) || !valid(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s uses Go's X-register-only table: %q", c.goarch, baseOp, ins.Raw) + } + mask, err := c.loadX(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + data, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + return true, false, c.emitImplicitByteMaskStore(data, mask, 16) +} + +func (c *amd64Ctx) emitImplicitByteMaskStore(data, mask string, byteWidth int) error { + predicate := c.newTmp() + addressInteger, err := c.loadReg(DI) + if err != nil { + return err + } + address := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt <%d x i8> %s, zeroinitializer\n", predicate, byteWidth, mask) + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", address, addressInteger) + fmt.Fprintf(c.b, " call void @llvm.masked.store.v%di8.p0(<%d x i8> %s, ptr %%%s, i32 1, <%d x i1> %%%s)\n", byteWidth, byteWidth, data, address, byteWidth, predicate) + return nil +} diff --git a/amd64_lower_implicit_mask_move_test.go b/amd64_lower_implicit_mask_move_test.go new file mode 100644 index 00000000..bec2fa1f --- /dev/null +++ b/amd64_lower_implicit_mask_move_test.go @@ -0,0 +1,102 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86ImplicitMaskMoveCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 15 + if target.goarch == "386" { + last = 7 + } + source := fmt.Sprintf("TEXT implicitmaskmoveforms(SB),NOSPLIT,$0-0\n"+ + "\tMASKMOVQ M0, M7\n"+ + "\tMASKMOVOU X0, X%d\n"+ + "\tMASKMOVDQU X0, X%d\n"+ + "\tVMASKMOVDQU X0, X%d\n"+ + "\tRET\n", last, last, last) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "implicitmaskmoveforms": {Name: "implicitmaskmoveforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "implicit-mask-move-"+target.name+".ll", "implicit-mask-move-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86ImplicitMaskMoveRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "MASKMOVQ.Z M0, M1", + "MASKMOVQ M0", + "MASKMOVQ M0, X1", + "MASKMOVQ 8(AX), M1", + "MASKMOVOU.Z X0, X1", + "MASKMOVOU X0", + "MASKMOVOU M0, M1", + "MASKMOVOU X0, Y1", + "MASKMOVDQU.Z X0, X1", + "MASKMOVDQU X0, X1, X2", + "MASKMOVDQU 8(AX), X1", + "VMASKMOVDQU.Z X0, X1", + "VMASKMOVDQU X0", + "VMASKMOVDQU Y0, Y1", + "VMASKMOVDQU X0, K1, X1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86ImplicitMaskMoveRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "MASKMOVOU X8, X0", + "MASKMOVDQU X0, X8", + "VMASKMOVDQU X8, X0", + "VMASKMOVDQU X0, X8", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86ImplicitMaskMoveRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86ImplicitMaskMoveRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's implicit mask-move forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_implicit_system.go b/amd64_lower_implicit_system.go new file mode 100644 index 00000000..de221b04 --- /dev/null +++ b/amd64_lower_implicit_system.go @@ -0,0 +1,165 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64ImplicitSystemOperand uint8 + +const ( + amd64ImplicitSystemNoOperand amd64ImplicitSystemOperand = iota + amd64ImplicitSystemGP +) + +type amd64ImplicitRegisterSet uint8 + +const ( + amd64ImplicitAX amd64ImplicitRegisterSet = 1 << iota + amd64ImplicitCX + amd64ImplicitDX +) + +type amd64ImplicitSystemSpec struct { + operand amd64ImplicitSystemOperand + inputs amd64ImplicitRegisterSet + outputs amd64ImplicitRegisterSet + writesCarry bool +} + +// amd64ImplicitSystemSpecs is the complete Go 1.27 grammar for the system +// instructions whose architectural state is carried by implicit AX/CX/DX +// registers, plus the WAITPKG instructions' one explicit Yrl register. The +// table separates operand syntax from data flow so parsing, register liveness, +// and emission all consume the same typed description. +var amd64ImplicitSystemSpecs = map[Op]amd64ImplicitSystemSpec{ + "MONITOR": {inputs: amd64ImplicitAX | amd64ImplicitCX | amd64ImplicitDX}, + "MWAIT": {inputs: amd64ImplicitAX | amd64ImplicitCX}, + "RDPMC": {inputs: amd64ImplicitCX, outputs: amd64ImplicitAX | amd64ImplicitDX}, + "RDPKRU": {inputs: amd64ImplicitCX, outputs: amd64ImplicitAX | amd64ImplicitDX}, + "WRPKRU": {inputs: amd64ImplicitAX | amd64ImplicitCX | amd64ImplicitDX}, + "XSETBV": {inputs: amd64ImplicitAX | amd64ImplicitCX | amd64ImplicitDX}, + "UMONITOR": {operand: amd64ImplicitSystemGP}, + "UMWAIT": {operand: amd64ImplicitSystemGP, inputs: amd64ImplicitAX | amd64ImplicitDX, writesCarry: true}, + "TPAUSE": {operand: amd64ImplicitSystemGP, inputs: amd64ImplicitAX | amd64ImplicitDX, writesCarry: true}, +} + +type amd64ImplicitSystemForm struct { + register Reg +} + +func (c *amd64Ctx) lowerImplicitSystem(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64ImplicitSystemSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + form, err := c.parseImplicitSystemForm(baseOp, spec, ins) + if err != nil { + return true, false, err + } + return c.emitImplicitSystem(baseOp, spec, form) +} + +func (c *amd64Ctx) parseImplicitSystemForm(op string, spec amd64ImplicitSystemSpec, ins Instr) (amd64ImplicitSystemForm, error) { + var form amd64ImplicitSystemForm + switch spec.operand { + case amd64ImplicitSystemNoOperand: + if len(ins.Args) != 0 { + return form, fmt.Errorf("%s %s takes no operands: %q", c.goarch, op, ins.Raw) + } + case amd64ImplicitSystemGP: + if len(ins.Args) != 1 || ins.Args[0].Kind != OpReg || !isX86YrlRegisterForArch(ins.Args[0].Reg, c.goarch) { + return form, fmt.Errorf("%s %s expects one Go 1.27 Yrl register: %q", c.goarch, op, ins.Raw) + } + form.register = ins.Args[0].Reg + default: + panic("unknown amd64 implicit-system operand kind") + } + return form, nil +} + +func (c *amd64Ctx) emitImplicitSystem(op string, spec amd64ImplicitSystemSpec, form amd64ImplicitSystemForm) (bool, bool, error) { + wordType := I64 + if c.goarch == "386" { + wordType = I32 + } + constraints := make([]string, 0, 8) + arguments := make([]string, 0, 4) + if spec.outputs == amd64ImplicitAX|amd64ImplicitDX { + constraints = append(constraints, "={ax}", "={dx}") + } + if spec.writesCarry { + constraints = append(constraints, "=q") + } + if spec.operand == amd64ImplicitSystemGP { + value, err := c.evalIntSized(Operand{Kind: OpReg, Reg: form.register}, wordType) + if err != nil { + return true, false, err + } + constraints = append(constraints, "r") + arguments = append(arguments, fmt.Sprintf("%s %s", wordType, value)) + } + for _, implicit := range []struct { + bit amd64ImplicitRegisterSet + reg Reg + constraint string + }{ + {bit: amd64ImplicitAX, reg: AX, constraint: "{ax}"}, + {bit: amd64ImplicitCX, reg: CX, constraint: "{cx}"}, + {bit: amd64ImplicitDX, reg: DX, constraint: "{dx}"}, + } { + if spec.inputs&implicit.bit == 0 { + continue + } + value, err := c.evalIntSized(Operand{Kind: OpReg, Reg: implicit.reg}, I32) + if err != nil { + return true, false, err + } + constraints = append(constraints, implicit.constraint) + arguments = append(arguments, "i32 "+value) + } + constraints = append(constraints, "~{memory}", "~{dirflag}", "~{fpsr}", "~{flags}") + + assembly := strings.ToLower(op) + if spec.operand == amd64ImplicitSystemGP { + operandIndex := 0 + if spec.writesCarry { + operandIndex = 1 + } + assembly += fmt.Sprintf(" $%d", operandIndex) + } + if spec.writesCarry { + assembly += "; setc $0" + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i8 asm sideeffect %q, %q(%s)\n", + call, assembly, strings.Join(constraints, ","), strings.Join(arguments, ", ")) + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i8 %%%s to i1\n", carry, call) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carry, c.flagsCFSlot) + return true, false, nil + } + if spec.outputs == amd64ImplicitAX|amd64ImplicitDX { + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call { i32, i32 } asm sideeffect %q, %q(%s)\n", + call, assembly, strings.Join(constraints, ","), strings.Join(arguments, ", ")) + for index, reg := range []Reg{AX, DX} { + part := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue { i32, i32 } %%%s, %d\n", part, call, index) + if err := c.storeRegSized(reg, I32, "%"+part); err != nil { + return true, false, err + } + } + return true, false, nil + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s)\n", + assembly, strings.Join(constraints, ","), strings.Join(arguments, ", ")) + return true, false, nil +} diff --git a/amd64_lower_implicit_system_test.go b/amd64_lower_implicit_system_test.go new file mode 100644 index 00000000..7b39bafd --- /dev/null +++ b/amd64_lower_implicit_system_test.go @@ -0,0 +1,131 @@ +package plan9asm + +import ( + "reflect" + "strings" + "testing" +) + +func TestAMD64ImplicitSystemGrammarIsComplete(t *testing.T) { + want := map[Op]amd64ImplicitSystemSpec{ + "MONITOR": {inputs: amd64ImplicitAX | amd64ImplicitCX | amd64ImplicitDX}, + "MWAIT": {inputs: amd64ImplicitAX | amd64ImplicitCX}, + "RDPMC": {inputs: amd64ImplicitCX, outputs: amd64ImplicitAX | amd64ImplicitDX}, + "RDPKRU": {inputs: amd64ImplicitCX, outputs: amd64ImplicitAX | amd64ImplicitDX}, + "WRPKRU": {inputs: amd64ImplicitAX | amd64ImplicitCX | amd64ImplicitDX}, + "XSETBV": {inputs: amd64ImplicitAX | amd64ImplicitCX | amd64ImplicitDX}, + "UMONITOR": {operand: amd64ImplicitSystemGP}, + "UMWAIT": {operand: amd64ImplicitSystemGP, inputs: amd64ImplicitAX | amd64ImplicitDX, writesCarry: true}, + "TPAUSE": {operand: amd64ImplicitSystemGP, inputs: amd64ImplicitAX | amd64ImplicitDX, writesCarry: true}, + } + if !reflect.DeepEqual(amd64ImplicitSystemSpecs, want) { + t.Fatalf("implicit-system grammar = %+v, want %+v", amd64ImplicitSystemSpecs, want) + } +} + +func TestTranslateX86ImplicitSystemCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + register := "R11" + if target.goarch == "386" { + register = "BX" + } + source := "TEXT implicitsystemforms(SB),$0-0\n" + + "\tMONITOR\n" + + "\tMWAIT\n" + + "\tRDPMC\n" + + "\tRDPKRU\n" + + "\tWRPKRU\n" + + "\tXSETBV\n" + + "\tUMONITOR " + register + "\n" + + "\tUMWAIT " + register + "\n" + + "\tTPAUSE " + register + "\n" + + "\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "implicitsystemforms": {Name: "implicitsystemforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+pku,+waitpkg,+xsave"`, + `asm sideeffect "monitor"`, + `asm sideeffect "mwait"`, + `asm sideeffect "rdpmc"`, + `asm sideeffect "rdpkru"`, + `asm sideeffect "wrpkru"`, + `asm sideeffect "xsetbv"`, + `asm sideeffect "umonitor $0"`, + `asm sideeffect "umwait $1; setc $0"`, + `asm sideeffect "tpause $1; setc $0"`, + `store i1 %`, + } { + if !strings.Contains(ir, want) { + t.Errorf("IR is missing %s:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "implicit-system-"+target.name+".ll", "implicit-system-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86ImplicitSystemRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "MONITOR AX"}, + {goarch: "amd64", instruction: "MWAIT.P"}, + {goarch: "amd64", instruction: "RDPMC AX"}, + {goarch: "amd64", instruction: "RDPKRU.P"}, + {goarch: "amd64", instruction: "WRPKRU AX"}, + {goarch: "amd64", instruction: "XSETBV AX"}, + {goarch: "amd64", instruction: "UMONITOR (BX)"}, + {goarch: "amd64", instruction: "UMWAIT X1"}, + {goarch: "amd64", instruction: "TPAUSE"}, + {goarch: "386", instruction: "UMONITOR R11"}, + {goarch: "386", instruction: "UMWAIT R11"}, + {goarch: "386", instruction: "TPAUSE R11"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's implicit-system tables", test.instruction) + } + }) + } +} diff --git a/amd64_lower_incdec.go b/amd64_lower_incdec.go new file mode 100644 index 00000000..ffde28d8 --- /dev/null +++ b/amd64_lower_incdec.go @@ -0,0 +1,86 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerScalarIncDec implements the complete Go 1.27 INCB/W/L/Q and +// DECB/W/L/Q tables. INC and DEC preserve CF while updating the modeled +// ZF/SF/PF/OF flags. +func (c *amd64Ctx) lowerScalarIncDec(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + bits := 0 + switch baseOp { + case "INCB", "DECB": + bits = 8 + case "INCW", "DECW": + bits = 16 + case "INCL", "DECL": + bits = 32 + case "INCQ", "DECQ": + bits = 64 + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 1 { + return true, false, fmt.Errorf("%s %s expects one destination: %q", c.goarch, baseOp, ins.Raw) + } + dst := ins.Args[0] + if dst.Kind == OpReg { + if bits == 8 { + if !isGoYmbRegisterForArch(dst.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Ymb class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isX86YrlRegisterForArch(dst.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yml class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(dst) { + return true, false, fmt.Errorf("%s %s expects a GP register or memory destination: %q", c.goarch, baseOp, ins.Raw) + } + + ty := amd64IntegerTypeForBits(bits) + old, err := c.evalIntSized(dst, ty) + if err != nil { + return true, false, err + } + result := c.newTmp() + llvmOp := "add" + if baseOp[:3] == "DEC" { + llvmOp = "sub" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s, 1\n", result, llvmOp, ty, old) + value := "%" + result + if err := c.storeScalarIntegerOperand(dst, ty, value); err != nil { + return true, false, err + } + + zero := c.newTmp() + sign := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, 0\n", zero, ty, value) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + fmt.Fprintf(c.b, " %%%s = icmp slt %s %s, 0\n", sign, ty, value) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", sign, c.flagsSltSlot) + c.setParityFlagSized(ty, value) + + overflowInput := int64(1) << (bits - 1) + if baseOp[:3] == "INC" { + overflowInput-- + } else { + overflowInput = -overflowInput + } + overflow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, %d\n", overflow, ty, old, overflowInput) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", overflow, c.flagsOFSlot) + return true, false, nil +} diff --git a/amd64_lower_insert.go b/amd64_lower_insert.go new file mode 100644 index 00000000..7dd020c0 --- /dev/null +++ b/amd64_lower_insert.go @@ -0,0 +1,157 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedVectorInsertSpec struct { + insertBytes int + laneBits int + legacyVEX bool + allowY bool + allowZ bool +} + +// lowerPackedVectorInsert implements every Go 1.27 form in _yvinsertf128, +// _yvinsertf32x4, and _yvinsertf32x8. The floating and integer spellings have +// identical bit-level insert behavior; their lane type only changes EVEX mask +// granularity. +func (c *amd64Ctx) lowerPackedVectorInsert(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + + var spec amd64PackedVectorInsertSpec + switch baseOp { + case "VINSERTF128", "VINSERTI128": + spec = amd64PackedVectorInsertSpec{insertBytes: 16, laneBits: 64, legacyVEX: true, allowY: true} + case "VINSERTF32X4", "VINSERTI32X4": + spec = amd64PackedVectorInsertSpec{insertBytes: 16, laneBits: 32, allowY: true, allowZ: true} + case "VINSERTF64X2", "VINSERTI64X2": + spec = amd64PackedVectorInsertSpec{insertBytes: 16, laneBits: 64, allowY: true, allowZ: true} + case "VINSERTF32X8", "VINSERTI32X8": + spec = amd64PackedVectorInsertSpec{insertBytes: 32, laneBits: 32, allowZ: true} + case "VINSERTF64X4", "VINSERTI64X4": + spec = amd64PackedVectorInsertSpec{insertBytes: 32, laneBits: 64, allowZ: true} + default: + return false, false, nil + } + if c.goarch == "386" { + return true, false, fmt.Errorf("386 %s exceeds the Go assembler frontend's operand limit: %q", baseOp, ins.Raw) + } + + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("%s %s does not accept .%s in its Go 1.27 insert table: %q", c.goarch, baseOp, suffix, ins.Raw) + } + if spec.legacyVEX { + if suffix != "" { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects imm8, X/m source, Y base, Y destination: %q", c.goarch, baseOp, ins.Raw) + } + } else if len(ins.Args) != 4 && len(ins.Args) != 5 { + return true, false, fmt.Errorf("%s %s expects imm8, source, base, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) < 4 || ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("%s %s requires an unsigned 8-bit immediate: %q", c.goarch, baseOp, ins.Raw) + } + + masked := !spec.legacyVEX && len(ins.Args) == 5 + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[3]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7 before the destination: %q", c.goarch, baseOp, ins.Raw) + } + + source := ins.Args[1] + base := ins.Args[2] + destination := ins.Args[len(ins.Args)-1] + if base.Kind != OpReg || destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s base and destination must be vector registers: %q", c.goarch, baseOp, ins.Raw) + } + outputBytes := amd64VectorByteWidth(base.Reg) + validOutputWidth := outputBytes == 32 && spec.allowY || outputBytes == 64 && spec.allowZ + if outputBytes == 0 || amd64VectorByteWidth(destination.Reg) != outputBytes || + !validOutputWidth { + return true, false, fmt.Errorf("%s %s has incompatible base/destination widths: %q", c.goarch, baseOp, ins.Raw) + } + + if spec.legacyVEX { + if !amd64VEXVectorRegister(base, outputBytes) || !amd64VEXVectorRegister(destination, outputBytes) { + return true, false, fmt.Errorf("%s %s requires in-range VEX Y base/destination registers: %q", c.goarch, baseOp, ins.Raw) + } + } else if !c.isGoPackedVectorMoveRegister(base, outputBytes) || !c.isGoPackedVectorMoveRegister(destination, outputBytes) { + return true, false, fmt.Errorf("%s %s requires in-range EVEX base/destination registers: %q", c.goarch, baseOp, ins.Raw) + } + + if source.Kind == OpReg { + valid := amd64VectorByteWidth(source.Reg) == spec.insertBytes + if spec.legacyVEX { + valid = valid && amd64VEXVectorRegister(source, spec.insertBytes) + } else { + valid = valid && c.isGoPackedVectorMoveRegister(source, spec.insertBytes) + } + if !valid { + return true, false, fmt.Errorf("%s %s source has the wrong vector width or register range: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + inserted, err := c.loadPackedCompareBytes(source, spec.insertBytes) + if err != nil { + return true, false, err + } + baseValue, err := c.loadPackedCompareBytes(base, outputBytes) + if err != nil { + return true, false, err + } + insertWords := spec.insertBytes / 8 + outputWords := outputBytes / 8 + insertAsWords := c.newTmp() + baseAsWords := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i64>\n", insertAsWords, spec.insertBytes, inserted, insertWords) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i64>\n", baseAsWords, outputBytes, baseValue, outputWords) + chunk := int(ins.Args[0].Imm) % (outputBytes / spec.insertBytes) + resultWords := "%" + baseAsWords + for i := 0; i < insertWords; i++ { + word := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %%%s, i32 %d\n", word, insertWords, insertAsWords, i) + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i64> %s, i64 %%%s, i32 %d\n", next, outputWords, resultWords, word, chunk*insertWords+i) + resultWords = "%" + next + } + computedName := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", computedName, outputWords, resultWords, outputBytes) + computed := "%" + computedName + + if masked { + mask, err := c.loadK(ins.Args[3].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, outputBytes) + if err != nil { + return true, false, err + } + lanes := outputBytes * 8 / spec.laneBits + computedLanes := c.bitcastVectorBytesToIntegerLanes(outputBytes, lanes, spec.laneBits, computed) + oldLanes := c.bitcastVectorBytesToIntegerLanes(outputBytes, lanes, spec.laneBits, oldBytes) + maskedLanes := amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, computedLanes, oldLanes, mask, zeroing) + maskedBytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", maskedBytes, lanes, spec.laneBits, maskedLanes, outputBytes) + computed = "%" + maskedBytes + } + return true, false, c.storeVectorBytesOperand(destination, outputBytes, computed) +} diff --git a/amd64_lower_insert_integer.go b/amd64_lower_insert_integer.go new file mode 100644 index 00000000..a69e1be9 --- /dev/null +++ b/amd64_lower_insert_integer.go @@ -0,0 +1,102 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedIntegerInsertSpec struct { + laneBits int + legacy bool +} + +var amd64PackedIntegerInsertSpecs = map[string]amd64PackedIntegerInsertSpec{ + "PINSRB": {laneBits: 8, legacy: true}, + "PINSRW": {laneBits: 16, legacy: true}, + "PINSRD": {laneBits: 32, legacy: true}, + "PINSRQ": {laneBits: 64, legacy: true}, + "VPINSRB": {laneBits: 8}, + "VPINSRW": {laneBits: 16}, + "VPINSRD": {laneBits: 32}, + "VPINSRQ": {laneBits: 64}, +} + +// lowerPackedIntegerInsert implements Go 1.27's yinsr/yinsrw and +// _yvpinsrb tables. The legacy forms update their X destination in place; +// the VEX/EVEX forms take a separate X base and destination. +func (c *amd64Ctx) lowerPackedIntegerInsert(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, handled := amd64PackedIntegerInsertSpecs[baseOp] + if !handled { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && (!spec.legacy || spec.laneBits == 64) { + return true, false, fmt.Errorf("386 %s is absent from Go 1.27's assembler tables: %q", baseOp, ins.Raw) + } + + wantArgs := 3 + if !spec.legacy { + wantArgs = 4 + } + if len(ins.Args) != wantArgs || ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("%s %s expects unsigned imm8, GP/memory source, %s: %q", c.goarch, baseOp, map[bool]string{true: "X destination", false: "X base, X destination"}[spec.legacy], ins.Raw) + } + + source := ins.Args[1] + base := ins.Args[2] + destination := ins.Args[2] + if !spec.legacy { + destination = ins.Args[3] + } + if source.Kind == OpReg { + if !isAMD64YrlRegister(source.Reg) || c.goarch == "386" && amd64IsExtendedGPRegister(source.Reg) { + return true, false, fmt.Errorf("%s %s source must be an in-range general register or memory: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be a general register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if base.Kind != OpReg || destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s base and destination must be X registers: %q", c.goarch, baseOp, ins.Raw) + } + if spec.legacy { + if !c.isGoLegacyXReg(destination.Reg) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's legacy X register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !amd64EVEXVectorRegister(base, 16) || !amd64EVEXVectorRegister(destination, 16) { + return true, false, fmt.Errorf("amd64 %s base/destination is outside Go 1.27's VEX/EVEX X register class: %q", baseOp, ins.Raw) + } + + scalarType := amd64IntegerTypeForBits(spec.laneBits) + scalar, err := c.evalIntSized(source, scalarType) + if err != nil { + return true, false, err + } + baseBytes, err := c.loadX(base.Reg) + if err != nil { + return true, false, err + } + lanes := 128 / spec.laneBits + baseLanes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x i%d>\n", baseLanes, baseBytes, lanes, spec.laneBits) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %%%s, i%d %s, i32 %d\n", inserted, lanes, spec.laneBits, baseLanes, spec.laneBits, scalar, int(ins.Args[0].Imm)%lanes) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", out, lanes, spec.laneBits, inserted) + return true, false, c.storeX(destination.Reg, "%"+out) +} + +func amd64IsExtendedGPRegister(reg Reg) bool { + switch strings.ToUpper(string(reg)) { + case "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15": + return true + default: + return false + } +} diff --git a/amd64_lower_insert_integer_test.go b/amd64_lower_insert_integer_test.go new file mode 100644 index 00000000..932a4384 --- /dev/null +++ b/amd64_lower_insert_integer_test.go @@ -0,0 +1,128 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedIntegerInsertCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast := 15 + if target.goarch == "386" { + legacyLast = 7 + } + var source strings.Builder + source.WriteString("TEXT packedintegerinsertforms(SB),$0-0\n") + legacyOps := []string{"PINSRB", "PINSRW", "PINSRD", "PINSRQ"} + vectorOps := []string{"VPINSRB", "VPINSRW", "VPINSRD", "VPINSRQ"} + if target.goarch == "386" { + legacyOps = legacyOps[:3] + vectorOps = nil + } + for _, op := range legacyOps { + fmt.Fprintf(&source, "\t%s $0, AX, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s $255, 8(AX), X%d\n", op, legacyLast) + } + for _, op := range vectorOps { + fmt.Fprintf(&source, "\t%s $0, AX, X0, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s $255, 8(AX), X0, X%d\n", op, legacyLast) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s $82, R9, X22, X31\n", op) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedintegerinsertforms": {Name: "packedintegerinsertforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-integer-insert.ll", "packed-integer-insert.o", ll) + }) + } +} + +func TestTranslateX86PackedIntegerInsertRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "PINSRB $-1, AX, X0", + "PINSRW $256, AX, X0", + "PINSRD $1, AX, Y0", + "PINSRQ.Z $1, AX, X0", + "PINSRB $1, AL, X0", + "PINSRD $1, X0, X1", + "PINSRQ $1, AX, X16", + "VPINSRB $1, AX, X0, Y1", + "VPINSRW $1, AX, Y0, X1", + "VPINSRD $1, X0, X1, X2", + "VPINSRQ $1, AX, X0, K1, X1", + "VPINSRQ.Z $1, AX, X0, X1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's PINSR/VPINSR tables", instruction) + } + }) + } + + for _, instruction := range []string{ + "PINSRQ $1, AX, X0", + "VPINSRB $1, AX, X0, X1", + "VPINSRQ $1, AX, X0, X1", + "PINSRD $1, R8, X0", + "PINSRD $1, AX, X8", + } { + t.Run("386_"+strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "386", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's 386 PINSR/VPINSR tables", instruction) + } + }) + } +} diff --git a/amd64_lower_insert_test.go b/amd64_lower_insert_test.go new file mode 100644 index 00000000..deac8e30 --- /dev/null +++ b/amd64_lower_insert_test.go @@ -0,0 +1,145 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedVectorInsertCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 defines three complete insert tables: + // _yvinsertf128: imm8, X/m, Y, Y + // _yvinsertf32x4: imm8, X/m, Y|Z, [K1-K7,] Y|Z + // _yvinsertf32x8: imm8, Y/m, Z, [K1-K7,] Z + // Exercise register and memory members of every source class, every + // destination width, and both merge and zero masking for all ten opcodes. + for _, target := range []struct { + name string + goarch string + triple string + zreg int + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin", zreg: 21}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", zreg: 21}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc", zreg: 21}, + } { + t.Run(target.name, func(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT packedvectorinsertforms(SB),NOSPLIT,$0-0\n") + if target.goarch == "amd64" { + for _, op := range []string{"VINSERTF128", "VINSERTI128"} { + fmt.Fprintf(&src, "\t%s $0, X0, Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s $255, (AX), Y3, Y4\n", op) + } + } + for _, op := range []string{"VINSERTF32X4", "VINSERTF64X2", "VINSERTI32X4", "VINSERTI64X2"} { + fmt.Fprintf(&src, "\t%s $0, X0, Y1, Y2\n", op) + fmt.Fprintf(&src, "\t%s $255, (AX), Y3, Y4\n", op) + fmt.Fprintf(&src, "\t%s $1, X20, Y20, K1, Y21\n", op) + fmt.Fprintf(&src, "\t%s.Z $2, (AX), Y20, K2, Y21\n", op) + fmt.Fprintf(&src, "\t%s $0, X0, Z0, Z%d\n", op, target.zreg) + fmt.Fprintf(&src, "\t%s $255, (AX), Z0, Z%d\n", op, target.zreg) + fmt.Fprintf(&src, "\t%s $3, X20, Z0, K3, Z%d\n", op, target.zreg) + fmt.Fprintf(&src, "\t%s.Z $1, (AX), Z0, K4, Z%d\n", op, target.zreg) + } + for _, op := range []string{"VINSERTF32X8", "VINSERTF64X4", "VINSERTI32X8", "VINSERTI64X4"} { + fmt.Fprintf(&src, "\t%s $0, Y0, Z0, Z%d\n", op, target.zreg) + fmt.Fprintf(&src, "\t%s $255, (AX), Z0, Z%d\n", op, target.zreg) + fmt.Fprintf(&src, "\t%s $1, Y20, Z0, K5, Z%d\n", op, target.zreg) + fmt.Fprintf(&src, "\t%s.Z $1, (AX), Z0, K6, Z%d\n", op, target.zreg) + } + src.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, strings.Replace(src.String(), ",NOSPLIT", "", 1), true) + + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedvectorinsertforms": {Name: "packedvectorinsertforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-vector-insert-"+target.name+".ll", "packed-vector-insert-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedVectorInsertRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "VINSERTI128 $0, Y0, Y1, Y2", + "VINSERTF128 $0, X0, Z1, Z2", + "VINSERTI128 $256, X0, Y1, Y2", + "VINSERTF128 $-1, X0, Y1, Y2", + "VINSERTI128.Z $0, X0, Y1, Y2", + "VINSERTF128 $0, X0, Y1, K1, Y2", + "VINSERTI32X4 $0, Y0, Y1, Y2", + "VINSERTF64X2 $0, X0, X1, X2", + "VINSERTI64X2 $0, X0, Y1, Z2", + "VINSERTF32X4 $0, X0, Y1, K0, Y2", + "VINSERTI32X4.Z $0, X0, Y1, Y2", + "VINSERTF64X2.BCST $0, (AX), Z1, Z2", + "VINSERTI32X8 $0, X0, Z1, Z2", + "VINSERTF64X4 $0, Y0, Y1, Y2", + "VINSERTI64X4 $0, Y0, Z1, K0, Z2", + "VINSERTF32X8.Z $0, Y0, Z1, Z2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + src := "TEXT bad(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", strings.Replace(src, ",NOSPLIT", "", 1), false) + file, err := Parse(ArchAMD64, src) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's packed insert tables", instruction) + } + }) + } + + for _, instruction := range []string{ + "VINSERTI128 $0, X0, Y0, Y1", + "VINSERTF128 $0, X0, Y0, Y1", + "VINSERTI128 $0, X16, Y0, Y1", + "VINSERTF128 $0, X0, Y16, Y1", + "VINSERTF32X4 $0, X0, Y0, Y1", + "VINSERTF64X2 $0, X0, Y0, Y1", + "VINSERTI32X4 $0, X0, Y0, Y1", + "VINSERTI64X2 $0, X0, Y0, Y1", + "VINSERTF32X8 $0, Y0, Z0, Z1", + "VINSERTF64X4 $0, Y0, Z0, Z1", + "VINSERTI32X8 $0, Y0, Z0, Z1", + "VINSERTI64X4 $0, Y0, Z0, Z1", + "VINSERTI32X4 $0, X0, Z8, Z0", + "VINSERTF64X2 $0, X0, Z0, K1, Z8", + "VINSERTI32X8 $0, Y0, Z8, Z0", + "VINSERTI64X4.Z $0, Y0, Z0, K1, Z8", + } { + src := "TEXT bad386(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "386", strings.Replace(src, ",NOSPLIT", "", 1), false) + file, err := Parse(ArchAMD64, src) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad386": {Name: "bad386", Ret: Void}}, + }); err == nil { + t.Fatalf("386 Translate accepted architecture-restricted %q", instruction) + } + } +} diff --git a/amd64_lower_insertps.go b/amd64_lower_insertps.go new file mode 100644 index 00000000..e28f440c --- /dev/null +++ b/amd64_lower_insertps.go @@ -0,0 +1,99 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerInsertPackedSingle implements all forms in Go 1.27's yxshuf and +// _yvinsertps tables. The imm8 selects the register-source lane in bits 7:6, +// the destination lane in bits 5:4, and lanes to clear in bits 3:0. +func (c *amd64Ctx) lowerInsertPackedSingle(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + if baseOp != "INSERTPS" && baseOp != "VINSERTPS" { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + wantArgs := 3 + if baseOp == "VINSERTPS" { + wantArgs = 4 + } + if len(ins.Args) != wantArgs || ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("amd64 %s expects unsigned imm8, X/m32 source, %s: %q", baseOp, map[bool]string{false: "X destination", true: "X base, X destination"}[baseOp == "VINSERTPS"], ins.Raw) + } + + source := ins.Args[1] + base := ins.Args[2] + destination := ins.Args[2] + if baseOp == "VINSERTPS" { + destination = ins.Args[3] + } + if base.Kind != OpReg || destination.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects X base/destination registers: %q", baseOp, ins.Raw) + } + if baseOp == "INSERTPS" { + if !c.isGoLegacyXReg(base.Reg) { + return true, false, fmt.Errorf("%s INSERTPS destination is outside Go 1.27's X register class: %q", c.goarch, ins.Raw) + } + } else if !amd64EVEXVectorRegister(base, 16) || !amd64EVEXVectorRegister(destination, 16) { + return true, false, fmt.Errorf("%s VINSERTPS base/destination is outside Go 1.27's VEX/EVEX X register class: %q", c.goarch, ins.Raw) + } + + var inserted string + if source.Kind == OpReg { + valid := c.isGoLegacyXReg(source.Reg) + if baseOp == "VINSERTPS" { + valid = amd64EVEXVectorRegister(source, 16) + } + if !valid { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's X register class: %q", c.goarch, baseOp, ins.Raw) + } + sourceBytes, err := c.loadX(source.Reg) + if err != nil { + return true, false, err + } + sourceLanes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", sourceLanes, sourceBytes) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x i32> %%%s, i32 %d\n", selected, sourceLanes, (ins.Args[0].Imm>>6)&3) + inserted = "%" + selected + } else { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s expects an X register or memory source: %q", baseOp, ins.Raw) + } + value, err := c.evalF32(source) + if err != nil { + return true, false, err + } + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %s to i32\n", bits, value) + inserted = "%" + bits + } + + baseBytes, err := c.loadX(base.Reg) + if err != nil { + return true, false, err + } + baseLanes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", baseLanes, baseBytes) + placed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <4 x i32> %%%s, i32 %s, i32 %d\n", placed, baseLanes, inserted, (ins.Args[0].Imm>>4)&3) + result := "%" + placed + for lane := 0; lane < 4; lane++ { + if ins.Args[0].Imm&(1< %s, i32 0, i32 %d\n", cleared, result, lane) + result = "%" + cleared + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %s to <16 x i8>\n", out, result) + return true, false, c.storeX(destination.Reg, "%"+out) +} diff --git a/amd64_lower_insertps_test.go b/amd64_lower_insertps_test.go new file mode 100644 index 00000000..fc3a7ea6 --- /dev/null +++ b/amd64_lower_insertps_test.go @@ -0,0 +1,104 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86InsertPSCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's yxshuf and _yvinsertps tables contain exactly: + // INSERTPS imm8, X/m32, X + // VINSERTPS imm8, X/m32, X, X + // VINSERTPS can select either its VEX (<16) or EVEX (<32) entry. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast := 15 + if target.goarch == "386" { + legacyLast = 7 + } + src := fmt.Sprintf(`TEXT insertpsforms(SB),NOSPLIT,$0-0 + INSERTPS $0, X0, X1 + INSERTPS $255, 4(AX), X%d + VINSERTPS $0, X0, X1, X2 + VINSERTPS $255, 8(AX), X14, X15 + VINSERTPS $16, X20, X21, X22 + VINSERTPS $32, 12(AX), X30, X31 + RET +`, legacyLast) + file, err := Parse(ArchAMD64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "insertpsforms": {Name: "insertpsforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "insertps-"+target.name+".ll", "insertps-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86InsertPSRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "INSERTPS X0, X1", + "INSERTPS $-1, X0, X1", + "INSERTPS $256, X0, X1", + "INSERTPS $0, Y0, X1", + "INSERTPS $0, X0, Y1", + "INSERTPS.Z $0, X0, X1", + "VINSERTPS $0, X0, X1", + "VINSERTPS $0, X0, X1, X2, X3", + "VINSERTPS $0, Y0, X1, X2", + "VINSERTPS $0, X0, Y1, X2", + "VINSERTPS $0, X0, X1, Y2", + "VINSERTPS $0, X0, K1, X1", + "VINSERTPS.Z $0, X0, X1, X2", + "VINSERTPS.BCST $0, (AX), X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86InsertPSRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "INSERTPS $0, X8, X0", + "INSERTPS $0, X0, X8", + } { + assertX86InsertPSRejected(t, "386", "i386-unknown-linux-gnu", instruction) + } +} + +func assertX86InsertPSRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's INSERTPS tables", instruction) + } +} diff --git a/amd64_lower_lddqu.go b/amd64_lower_lddqu.go new file mode 100644 index 00000000..e15cb649 --- /dev/null +++ b/amd64_lower_lddqu.go @@ -0,0 +1,53 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64UnalignedLoadSpec struct { + maxBytes int + vector bool +} + +// amd64UnalignedLoadSpecs is the complete Go 1.27 ylddqu/_yvlddqu grammar. +// Both instructions are load-only; legacy LDDQU is X-width, while VLDDQU +// adds the VEX Y-width row. +var amd64UnalignedLoadSpecs = map[Op]amd64UnalignedLoadSpec{ + "LDDQU": {maxBytes: 16}, + "VLDDQU": {maxBytes: 32, vector: true}, +} + +func (c *amd64Ctx) lowerUnalignedVectorLoad(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64UnalignedLoadSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed form in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 || !isAMD64MemoryOperand(ins.Args[0]) || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects memory, X%s: %q", c.goarch, baseOp, map[bool]string{true: "/Y"}[spec.maxBytes == 32], ins.Raw) + } + byteWidth := amd64VectorByteWidth(ins.Args[1].Reg) + validDestination := c.isGoVEXVectorRegister(ins.Args[1], byteWidth, false) + if spec.vector { + validDestination = amd64VEXVectorRegister(ins.Args[1], byteWidth) + } + if (byteWidth != 16 && byteWidth != 32) || byteWidth > spec.maxBytes || !validDestination { + return true, false, fmt.Errorf("%s %s destination width or register is outside its Go 1.27 table: %q", c.goarch, baseOp, ins.Raw) + } + if !spec.vector && ins.Args[0].Kind == OpMem && !x86MemoryRegistersValidForArch(ins.Args[0].Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s source uses an out-of-range address register: %q", c.goarch, baseOp, ins.Raw) + } + value, err := c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err != nil { + return true, false, err + } + return true, false, c.storeVectorBytes(ins.Args[1].Reg, byteWidth, value) +} diff --git a/amd64_lower_lddqu_test.go b/amd64_lower_lddqu_test.go new file mode 100644 index 00000000..7d24affe --- /dev/null +++ b/amd64_lower_lddqu_test.go @@ -0,0 +1,163 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64UnalignedLoadGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64UnalignedLoadSpec{ + "LDDQU": {maxBytes: 16}, + "VLDDQU": {maxBytes: 32, vector: true}, + } + if len(amd64UnalignedLoadSpecs) != len(expected) { + t.Fatalf("unaligned-load grammar has %d entries, want %d", len(amd64UnalignedLoadSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64UnalignedLoadSpecs[op]; !ok { + t.Errorf("unaligned-load grammar omitted %s", op) + } else if got != want { + t.Errorf("unaligned-load grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86LDDQUCompleteFormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 15 + if target.goarch == "386" { + last = 7 + } + source := fmt.Sprintf(`TEXT lddquforms(SB),$0-0 + LDDQU 1(AX), X%d + VLDDQU 2(AX), X%d + VLDDQU 3(AX), Y%d +`, last, last, last) + if target.goarch == "386" { + source += "\tVLDDQU 4(R9), Y8\n" + } + source += "\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: target.goarch, TargetTriple: target.triple, Sigs: map[string]FuncSig{"lddquforms": {Name: "lddquforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load <16 x i8>", "load <32 x i8>"} { + if !strings.Contains(ir, want) { + t.Fatalf("LDDQU/VLDDQU lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "lddqu-"+target.name+".ll", "lddqu-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86LDDQURejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "LDDQU X0, X1"}, + {goarch: "amd64", instruction: "LDDQU 0(AX), Y1"}, + {goarch: "amd64", instruction: "VLDDQU X0, X1"}, + {goarch: "amd64", instruction: "VLDDQU 0(AX), Z1"}, + {goarch: "amd64", instruction: "VLDDQU.Z 0(AX), X1"}, + {goarch: "386", instruction: "LDDQU 0(AX), X8"}, + {goarch: "386", instruction: "LDDQU 0(R9), X0"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{Goarch: test.goarch, TargetTriple: triple, Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside the Go table for %s", test.instruction, test.goarch) + } + }) + } +} + +func TestAMD64LDDQURuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT lddqusemantics(SB),$0-16 + MOVQ out+0(FP), AX + MOVQ in+8(FP), CX + STC + LDDQU 1(CX), X0 + MOVUPS X0, 0(AX) + SETCS 16(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{"lddqusemantics": { + Name: "lddqusemantics", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void lddqusemantics(uint8_t *, const uint8_t *); +int main(void) { + uint8_t in[17], out[17] = {0}; + for (int i = 0; i < 17; i++) in[i] = (uint8_t)(i * 7 + 3); + lddqusemantics(out, in); + for (int i = 0; i < 16; i++) if (out[i] != in[i + 1]) return 10 + i; + if (out[16] != 1) return 30; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "lddqu_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_lea_complete_test.go b/amd64_lower_lea_complete_test.go new file mode 100644 index 00000000..d9fcb57c --- /dev/null +++ b/amd64_lower_lea_complete_test.go @@ -0,0 +1,179 @@ +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func x86LEACompleteFormsSource(goarch string) string { + var source strings.Builder + source.WriteString("DATA leadata+0(SB)/8, $1\n") + source.WriteString("GLOBL leadata(SB), $8\n") + source.WriteString("TEXT leaforms(SB),$0-0\n") + widths := []string{"W", "L"} + if goarch == "amd64" { + widths = append(widths, "Q") + } + for _, width := range widths { + op := "LEA" + width + source.WriteString("\t" + op + " 8(BX)(CX*2), AX\n") + source.WriteString("\t" + op + " leadata(SB), DX\n") + source.WriteString("\t" + op + " 16(BX), SP\n") + if goarch == "amd64" { + source.WriteString("\t" + op + " 24(R11)(R12*4), R13\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86LEACompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86LEACompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"leaforms": {Name: "leaforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"trunc i64", "to i16", "to i32"} { + if !strings.Contains(ir, want) { + t.Fatalf("LEA lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "lea-complete-"+target.name+".ll", "lea-complete-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86LEARejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "LEAW AX, BX"}, + {goarch: "amd64", instruction: "LEAL 8(AX), X0"}, + {goarch: "amd64", instruction: "LEAQ 8(AX)"}, + {goarch: "amd64", instruction: "LEAW.Z 8(AX), BX"}, + {goarch: "386", instruction: "LEAQ 8(AX), BX"}, + {goarch: "386", instruction: "LEAW 8(R9), AX"}, + {goarch: "386", instruction: "LEAL 8(AX), R8"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ym_rl table", test.instruction) + } + }) + } +} + +func TestAMD64LEARuntimeWidthsAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT leasementics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVL $0x7fffffff, R8 + ADDL $1, R8 + STC + MOVQ $0x1122334455667788, AX + LEAW 0x1234(DI), AX + MOVQ AX, 0(DI) + LEAL 0x1234(DI), BX + MOVQ BX, 8(DI) + LEAQ 0x1234(DI), CX + MOVQ CX, 16(DI) + SETCS 24(DI) + SETOS 25(DI) + SETEQ 26(DI) + SETMI 27(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "leasementics": { + Name: "leasementics", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void leasementics(uint8_t *); +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + uint8_t out[32] = {0}; + uintptr_t address = (uintptr_t)(out + 0x1234); + leasementics(out); + uint64_t want16 = UINT64_C(0x1122334455660000) | (address & UINT64_C(0xffff)); + if (load64(out+0) != want16) return 10; + if (load64(out+8) != (uint32_t)address) return 11; + if (load64(out+16) != address) return 12; + if (out[24] != 1 || out[25] != 1 || out[26] != 0 || out[27] != 1) return 13; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "lea_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_leave.go b/amd64_lower_leave.go new file mode 100644 index 00000000..95696d25 --- /dev/null +++ b/amd64_lower_leave.go @@ -0,0 +1,73 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64LeaveSpec struct { + bits int +} + +// amd64LeaveSpecs is the complete Go 1.27 LEAVE grammar. W is shared, +// L is 386-only, and Q is amd64-only. The lowering models the architectural +// sequence SP = BP; POP BP against the translated register/address state. +var amd64LeaveSpecs = map[Op]amd64LeaveSpec{ + "LEAVEW": {bits: 16}, + "LEAVEL": {bits: 32}, + "LEAVEQ": {bits: 64}, +} + +func (c *amd64Ctx) lowerLeave(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64LeaveSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && spec.bits == 64 { + return true, false, fmt.Errorf("386 %s is absent from Go 1.27's 32-bit encoding table: %q", baseOp, ins.Raw) + } + if c.goarch != "386" && spec.bits == 32 { + return true, false, fmt.Errorf("amd64 %s is absent from Go 1.27's 64-bit encoding table: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, baseOp, ins.Raw) + } + + base, err := c.loadReg(BP) + if err != nil { + return true, false, err + } + address := base + if c.goarch == "386" { + low := c.truncI64(base, I32) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, low) + address = "%" + wide + } + pointer := c.ptrFromAddrI64(address) + typ := amd64StackLLVMType(spec.bits) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", value, typ, pointer) + if err := c.storeRegSized(BP, typ, "%"+value); err != nil { + return true, false, err + } + if c.goarch == "386" { + address32 := c.truncI64(address, I32) + next32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %d\n", next32, address32, spec.bits/8) + next64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", next64, next32) + return true, false, c.storeRegUnchecked(SP, "%"+next64) + } + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %d\n", next, address, spec.bits/8) + return true, false, c.storeRegUnchecked(SP, "%"+next) +} diff --git a/amd64_lower_legacy_mmx.go b/amd64_lower_legacy_mmx.go new file mode 100644 index 00000000..bb8ffc54 --- /dev/null +++ b/amd64_lower_legacy_mmx.go @@ -0,0 +1,146 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64LegacyMMXOperandClass uint8 + +const ( + amd64LegacyMMXMMX amd64LegacyMMXOperandClass = 1 << iota + amd64LegacyMMXXMM + amd64LegacyMMXMemory +) + +type amd64LegacyMMXMoveSpec struct { + source amd64LegacyMMXOperandClass + destination amd64LegacyMMXOperandClass + transferBits int + zeroExtend bool + nonTemporal bool +} + +// amd64LegacyMMXMoveSpecs describes the complete Go 1.27 legacy cross-domain +// and non-temporal MMX move grammar. Operand classes and transfer semantics are +// data; one parser validates all four opcode spellings. +var amd64LegacyMMXMoveSpecs = map[Op]amd64LegacyMMXMoveSpec{ + "MOVQOZX": {source: amd64LegacyMMXMMX | amd64LegacyMMXXMM | amd64LegacyMMXMemory, destination: amd64LegacyMMXXMM, transferBits: 64, zeroExtend: true}, + "MOVDQ2Q": {source: amd64LegacyMMXXMM, destination: amd64LegacyMMXMMX, transferBits: 64}, + "MOVNTQ": {source: amd64LegacyMMXMMX, destination: amd64LegacyMMXMemory, transferBits: 64, nonTemporal: true}, + "MOVNTDQ": {source: amd64LegacyMMXXMM, destination: amd64LegacyMMXMemory, transferBits: 128, nonTemporal: true}, +} + +type amd64LegacyMMXMoveForm struct { + source Operand + destination Operand +} + +func (c *amd64Ctx) lowerLegacyMMXMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64LegacyMMXMoveSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + form, err := c.parseLegacyMMXMoveForm(baseOp, spec, ins) + if err != nil { + return true, false, err + } + return c.emitLegacyMMXMove(spec, form) +} + +func (c *amd64Ctx) parseLegacyMMXMoveForm(op string, spec amd64LegacyMMXMoveSpec, ins Instr) (amd64LegacyMMXMoveForm, error) { + var form amd64LegacyMMXMoveForm + if len(ins.Args) != 2 { + return form, fmt.Errorf("%s %s expects exactly two operands: %q", c.goarch, op, ins.Raw) + } + sourceClass := c.legacyMMXOperandClass(ins.Args[0]) + destinationClass := c.legacyMMXOperandClass(ins.Args[1]) + if sourceClass&spec.source == 0 || destinationClass&spec.destination == 0 { + return form, fmt.Errorf("%s %s operands are outside its Go 1.27 legacy MMX table: %q", c.goarch, op, ins.Raw) + } + for _, operand := range ins.Args { + if operand.Kind == OpMem && !x86MemoryRegistersValidForArch(operand.Mem, c.goarch) { + return form, fmt.Errorf("%s %s memory address uses an out-of-range register: %q", c.goarch, op, ins.Raw) + } + } + return amd64LegacyMMXMoveForm{source: ins.Args[0], destination: ins.Args[1]}, nil +} + +func (c *amd64Ctx) legacyMMXOperandClass(operand Operand) amd64LegacyMMXOperandClass { + if operand.Kind == OpReg { + if _, ok := amd64ParseMReg(operand.Reg); ok { + return amd64LegacyMMXMMX + } + if c.isGoLegacyXReg(operand.Reg) { + return amd64LegacyMMXXMM + } + return 0 + } + if isAMD64MemoryOperand(operand) { + return amd64LegacyMMXMemory + } + return 0 +} + +func (c *amd64Ctx) emitLegacyMMXMove(spec amd64LegacyMMXMoveSpec, form amd64LegacyMMXMoveForm) (bool, bool, error) { + if spec.destination == amd64LegacyMMXXMM { + bits, err := c.loadLegacyMMXMoveLow64(form.source) + if err != nil { + return true, false, err + } + words := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> zeroinitializer, i64 %s, i32 0\n", words, bits) + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", bytes, words) + return true, false, c.storeX(form.destination.Reg, "%"+bytes) + } + + if spec.destination == amd64LegacyMMXMMX { + bits, err := c.loadLegacyMMXMoveLow64(form.source) + if err != nil { + return true, false, err + } + return true, false, c.storeReg(form.destination.Reg, bits) + } + + if spec.transferBits == 64 { + bits, err := c.evalIntSized(form.source, I64) + if err != nil { + return true, false, err + } + return true, false, c.storeMOVNTIMemory(form.destination, I64, bits) + } + bytes, err := c.loadX(form.source.Reg) + if err != nil { + return true, false, err + } + return true, false, c.storeVectorBytesOperandWithMetadata(form.destination, 16, bytes, x86NonTemporalMetadata) +} + +func (c *amd64Ctx) loadLegacyMMXMoveLow64(source Operand) (string, error) { + if source.Kind == OpReg { + if _, ok := amd64ParseMReg(source.Reg); ok { + return c.loadReg(source.Reg) + } + if c.isGoLegacyXReg(source.Reg) { + value, err := c.loadX(source.Reg) + if err != nil { + return "", err + } + words := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", words, value) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 0\n", low, words) + return "%" + low, nil + } + } + return c.evalIntSized(source, I64) +} diff --git a/amd64_lower_legacy_mmx_test.go b/amd64_lower_legacy_mmx_test.go new file mode 100644 index 00000000..c9840e14 --- /dev/null +++ b/amd64_lower_legacy_mmx_test.go @@ -0,0 +1,223 @@ +package plan9asm + +import ( + "reflect" + "runtime" + "strings" + "testing" +) + +func TestAMD64LegacyMMXMoveGrammarIsComplete(t *testing.T) { + want := map[Op]amd64LegacyMMXMoveSpec{ + "MOVQOZX": {source: amd64LegacyMMXMMX | amd64LegacyMMXXMM | amd64LegacyMMXMemory, destination: amd64LegacyMMXXMM, transferBits: 64, zeroExtend: true}, + "MOVDQ2Q": {source: amd64LegacyMMXXMM, destination: amd64LegacyMMXMMX, transferBits: 64}, + "MOVNTQ": {source: amd64LegacyMMXMMX, destination: amd64LegacyMMXMemory, transferBits: 64, nonTemporal: true}, + "MOVNTDQ": {source: amd64LegacyMMXXMM, destination: amd64LegacyMMXMemory, transferBits: 128, nonTemporal: true}, + } + if !reflect.DeepEqual(amd64LegacyMMXMoveSpecs, want) { + t.Fatalf("legacy MMX move grammar = %+v, want %+v", amd64LegacyMMXMoveSpecs, want) + } +} + +func TestTranslateX86LegacyMMXCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + base := "BX" + xreg := "X7" + if target.goarch == "amd64" { + base = "R11" + xreg = "X15" + } + source := `TEXT legacymmxforms(SB),$0-0 + PSHUFW $-128, M1, M2 + PSHUFW $127, 8(BX), M3 + MOVQOZX M2, X2 + MOVQOZX X1, X3 + MOVQOZX 16(BX), X4 + MOVNTQ M2, 24(BX) +` + "\tMOVQOZX M3, " + xreg + "\n" + + "\tMOVNTQ M3, 32(" + base + ")\n\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"legacymmxforms": {Name: "legacymmxforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"!nontemporal !0", "!0 = !{i32 1}"} { + if !strings.Contains(ir, want) { + t.Errorf("IR is missing %s:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "legacy-mmx-"+target.name+".ll", "legacy-mmx-"+target.name+".o", ir) + }) + } +} + +func TestAMD64LegacyMMXRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT legacymmxsemantics(SB),NOSPLIT,$0-16 + MOVQ value+0(FP), AX + MOVQ AX, M1 + MOVQ out+8(FP), DI + PSHUFW $0x1b, M1, M2 + MOVNTQ M2, 0(DI) + MOVQOZX M2, X1 + MOVDQ2Q X1, M3 + MOVNTQ M3, 8(DI) + MOVNTDQ X1, 16(DI) + SFENCE + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"legacymmxsemantics": { + Name: "legacymmxsemantics", Args: []LLVMType{I64, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void legacymmxsemantics(uint64_t, uint8_t *); +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + __attribute__((aligned(16))) uint8_t out[32] = {0xff}; + legacymmxsemantics(UINT64_C(0x1122334455667788), out); + const uint64_t shuffled = UINT64_C(0x7788556633441122); + if (load64(out) != shuffled) return 10; + if (load64(out + 8) != shuffled) return 11; + if (load64(out + 16) != shuffled) return 12; + if (load64(out + 24) != 0) return 13; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "legacy_mmx_semantics", triple, ir, mainC, runPrefix) +} + +func TestTranslateX86LegacyMMXEncoderAliases(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + const source = `TEXT encoderaliases(SB),$0-0 + MOVDQ2Q X1, M1 + MOVNTDQ X2, 8(BX) + RET +` + // Go accepts these Intel decoder names in addition to the MOVQ and + // MOVNTO spellings used by its primary optab entries. + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"encoderaliases": {Name: "encoderaliases", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "legacy-mmx-alias-"+target.name+".ll", "legacy-mmx-alias-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86LegacyMMXRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "PSHUFW $-129, M1, M2"}, + {goarch: "amd64", instruction: "PSHUFW $128, M1, M2"}, + {goarch: "amd64", instruction: "PSHUFW $1, X1, M2"}, + {goarch: "amd64", instruction: "PSHUFW $1, M1, X2"}, + {goarch: "amd64", instruction: "PSHUFW.Z $1, M1, M2"}, + {goarch: "amd64", instruction: "MOVQOZX M1, M2"}, + {goarch: "amd64", instruction: "MOVQOZX $1, X2"}, + {goarch: "amd64", instruction: "MOVNTQ X1, 8(BX)"}, + {goarch: "amd64", instruction: "MOVNTQ M1, M2"}, + {goarch: "amd64", instruction: "MOVDQ2Q M1, X1"}, + {goarch: "amd64", instruction: "MOVNTDQ 8(BX), X1"}, + {goarch: "386", instruction: "MOVQOZX M1, X8"}, + {goarch: "386", instruction: "MOVNTQ M1, 8(R11)"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "$", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside the legacy MMX grammar", test.instruction) + } + }) + } +} diff --git a/amd64_lower_legacy_packed_logical_test.go b/amd64_lower_legacy_packed_logical_test.go new file mode 100644 index 00000000..21f1a9e7 --- /dev/null +++ b/amd64_lower_legacy_packed_logical_test.go @@ -0,0 +1,188 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86LegacyPackedLogicalCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastX := 15 + if target.goarch == "386" { + lastX = 7 + } + var source strings.Builder + source.WriteString("TEXT legacypackedlogicalforms(SB),$0-0\n") + for _, op := range []string{"PAND", "PANDN", "POR", "PXOR"} { + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s M0, M7\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), M7\n", op) + } + fmt.Fprintf(&source, "\t%s X0, X%d\n", op, lastX) + fmt.Fprintf(&source, "\t%s 16(AX), X%d\n", op, lastX) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"legacypackedlogicalforms": {Name: "legacypackedlogicalforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + wantIR := []string{"and <16 x i8>", "or <16 x i8>", "xor <16 x i8>"} + if target.goarch == "amd64" { + wantIR = append(wantIR, "and i64", "or i64", "xor i64") + } + for _, want := range wantIR { + if !strings.Contains(ir, want) { + t.Fatalf("legacy packed logical lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "legacy-packed-logical-"+target.name+".ll", "legacy-packed-logical-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86LegacyPackedLogicalRejectsFormsOutsideGo127Table(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "PAND M0, X1"}, + {goarch: "amd64", instruction: "POR X0, M1"}, + {goarch: "amd64", instruction: "PXOR Y0, Y1"}, + {goarch: "amd64", instruction: "PAND.Z X0, X1"}, + {goarch: "amd64", instruction: "PAND M0"}, + {goarch: "amd64", instruction: "POR M0, M1, M2"}, + {goarch: "386", instruction: "PXOR X0, X8"}, + {goarch: "386", instruction: "PAND 8(R9), X0"}, + {goarch: "386", instruction: "PAND M0, M1"}, + {goarch: "386", instruction: "PANDN M0, M1"}, + {goarch: "386", instruction: "POR M0, M1"}, + {goarch: "386", instruction: "PXOR M0, M1"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed logical table for %s", test.instruction, test.goarch) + } + }) + } +} + +func TestAMD64LegacyPackedLogicalMMXRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT legacypackedlogicalsemantics(SB),$0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), M0 + MOVQ b+16(FP), M1 + STC + PAND M0, M1 + MOVQ M1, 0(AX) + MOVQ a+8(FP), M0 + MOVQ b+16(FP), M1 + PANDN M0, M1 + MOVQ M1, 8(AX) + MOVQ a+8(FP), M0 + MOVQ b+16(FP), M1 + POR M0, M1 + MOVQ M1, 16(AX) + MOVQ a+8(FP), M0 + MOVQ b+16(FP), M1 + PXOR M0, M1 + MOVQ M1, 24(AX) + SETCS 32(AX) + EMMS + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "legacypackedlogicalsemantics": { + Name: "legacypackedlogicalsemantics", Args: []LLVMType{Ptr, I64, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void legacypackedlogicalsemantics(uint8_t *, uint64_t, uint64_t); +static uint64_t load64(const uint8_t *p) { uint64_t v; memcpy(&v, p, 8); return v; } +int main(void) { + uint8_t out[33] = {0}; + uint64_t a = UINT64_C(0x0ff00ff0a55aa55a); + uint64_t b = UINT64_C(0x33cc55aa5aa5f00f); + legacypackedlogicalsemantics(out, a, b); + if (load64(out+0) != (a & b)) return 10; + if (load64(out+8) != ((~b) & a)) return 11; + if (load64(out+16) != (a | b)) return 12; + if (load64(out+24) != (a ^ b)) return 13; + if (out[32] != 1) return 14; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "legacy_packed_logical_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_lods_test.go b/amd64_lower_lods_test.go new file mode 100644 index 00000000..4e26c280 --- /dev/null +++ b/amd64_lower_lods_test.go @@ -0,0 +1,225 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86LODSCompleteFormsSource(goarch string) string { + widths := []string{"B", "W", "L"} + if goarch == "amd64" { + widths = append(widths, "Q") + } + var source strings.Builder + source.WriteString("TEXT lodsforms(SB),$0-0\n") + for _, width := range widths { + op := "LODS" + width + fmt.Fprintf(&source, "\t%s\n", op) + fmt.Fprintf(&source, "\tCLD; REP; %s\n", op) + fmt.Fprintf(&source, "\tSTD; REPN; %s\n", op) + source.WriteString("\tCLD\n") + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86LODSCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86LODSCompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"lodsforms": {Name: "lodsforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, width := range []string{"b", "w", "l"} { + if want := "@__plan9asm_rep_lods" + width; !strings.Contains(ir, want) { + t.Fatalf("LODS lowering omitted %q:\n%s", want, ir) + } + } + if target.goarch == "amd64" && !strings.Contains(ir, "@__plan9asm_rep_lodsq") { + t.Fatalf("LODSQ lowering omitted qword helper:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "lods-"+target.name+".ll", "lods-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86LODSRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "LODSB AX"}, + {goarch: "amd64", instruction: "LODSW AX, BX"}, + {goarch: "amd64", instruction: "LODSL.Z"}, + {goarch: "386", instruction: "LODSQ"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's LODS ynone table", test.instruction) + } + }) + } +} + +func TestAMD64LODSRuntimeSemanticsWidthsPrefixesAndDirection(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT lodssemantics(SB),NOSPLIT,$0-16 + MOVQ out+0(FP), R8 + MOVQ data+8(FP), R9 + CLD + + MOVQ R9, SI + MOVQ $0x1122334455667788, AX + LODSB + MOVQ AX, 0(R8) + MOVQ SI, 8(R8) + + MOVQ R9, SI + ADDQ $8, SI + MOVQ $0x1122334455667788, AX + LODSW + MOVQ AX, 16(R8) + + MOVQ R9, SI + ADDQ $16, SI + MOVQ $-1, AX + LODSL + MOVQ AX, 24(R8) + + MOVQ R9, SI + ADDQ $24, SI + LODSQ + MOVQ AX, 32(R8) + + MOVQ R9, SI + ADDQ $32, SI + MOVQ $3, CX + REP; LODSB + MOVQ AX, 40(R8) + MOVQ SI, 48(R8) + MOVQ CX, 56(R8) + + MOVQ R9, SI + ADDQ $40, SI + MOVQ $3, CX + REPN; LODSW + MOVQ AX, 64(R8) + MOVQ SI, 72(R8) + MOVQ CX, 80(R8) + + MOVQ R9, SI + ADDQ $52, SI + MOVQ $2, CX + STD + REP; LODSL + CLD + MOVQ AX, 88(R8) + MOVQ SI, 96(R8) + MOVQ CX, 104(R8) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "lodssemantics": { + Name: "lodssemantics", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void lodssemantics(uint8_t *, uint8_t *); +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + uint8_t data[64] = {0}; + data[0] = 0xaa; + const uint16_t w = UINT16_C(0xbbcc); memcpy(data+8, &w, sizeof(w)); + const uint32_t l = UINT32_C(0x89abcdef); memcpy(data+16, &l, sizeof(l)); + const uint64_t q = UINT64_C(0x0123456789abcdef); memcpy(data+24, &q, sizeof(q)); + data[32] = 1; data[33] = 2; data[34] = 3; + const uint16_t ws[3] = {0x1111,0x2222,0x3333}; memcpy(data+40, ws, sizeof(ws)); + const uint32_t ls[2] = {0x44444444,0x55555555}; memcpy(data+48, ls, sizeof(ls)); + uint8_t out[112] = {0}; + lodssemantics(out, data); + if (load64(out+0) != UINT64_C(0x11223344556677aa) || load64(out+8) != (uintptr_t)(data+1)) return 10; + if (load64(out+16) != UINT64_C(0x112233445566bbcc)) return 11; + if (load64(out+24) != UINT64_C(0x89abcdef)) return 12; + if (load64(out+32) != q) return 13; + if ((load64(out+40) & 0xff) != 3 || load64(out+48) != (uintptr_t)(data+35) || load64(out+56) != 0) return 14; + if ((load64(out+64) & 0xffff) != 0x3333 || load64(out+72) != (uintptr_t)(data+46) || load64(out+80) != 0) return 15; + if (load64(out+88) != UINT64_C(0x44444444) || load64(out+96) != (uintptr_t)(data+44) || load64(out+104) != 0) return 16; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "lods_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_logical_shift.go b/amd64_lower_logical_shift.go new file mode 100644 index 00000000..3637b053 --- /dev/null +++ b/amd64_lower_logical_shift.go @@ -0,0 +1,251 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedLogicalShiftSpec struct { + laneBits int + left bool + vector bool +} + +// amd64PackedLogicalShiftSpecs covers all Go 1.27 uniform packed logical +// shifts. Legacy operations use yps (MMX/XMM, immediate or packed count), and +// V-prefixed operations use _yvpslld (X/Y/Z data and an immediate or X/m128 +// count, with the table's EVEX mask and D/Q broadcast forms). +var amd64PackedLogicalShiftSpecs = map[Op]amd64PackedLogicalShiftSpec{ + "PSLLW": {laneBits: 16, left: true}, + "PSLLL": {laneBits: 32, left: true}, + "PSLLQ": {laneBits: 64, left: true}, + "PSRLW": {laneBits: 16}, + "PSRLL": {laneBits: 32}, + "PSRLQ": {laneBits: 64}, + "VPSLLW": {laneBits: 16, left: true, vector: true}, + "VPSLLD": {laneBits: 32, left: true, vector: true}, + "VPSLLQ": {laneBits: 64, left: true, vector: true}, + "VPSRLW": {laneBits: 16, vector: true}, + "VPSRLD": {laneBits: 32, vector: true}, + "VPSRLQ": {laneBits: 64, vector: true}, +} + +func (c *amd64Ctx) lowerPackedLogicalShift(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64PackedLogicalShiftSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if spec.vector { + return c.lowerVectorPackedLogicalShift(baseOp, suffix, spec, ins) + } + return c.lowerLegacyPackedLogicalShift(baseOp, suffix, spec, ins) +} + +func (c *amd64Ctx) lowerLegacyPackedLogicalShift(baseOp, suffix string, spec amd64PackedLogicalShiftSpec, ins Instr) (bool, bool, error) { + if suffix != "" { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects count and packed destination: %q", c.goarch, baseOp, ins.Raw) + } + countArg, destination := ins.Args[0], ins.Args[1].Reg + if countArg.Kind == OpImm && (countArg.Imm < -128 || countArg.Imm > 127) { + return true, false, fmt.Errorf("%s %s immediate count is outside Go's Yi8 class: %q", c.goarch, baseOp, ins.Raw) + } + if _, mmx := amd64ParseMReg(destination); mmx { + if countArg.Kind == OpReg { + if _, ok := amd64ParseMReg(countArg.Reg); !ok { + return true, false, fmt.Errorf("%s %s MMX form requires an immediate, MMX, or memory count: %q", c.goarch, baseOp, ins.Raw) + } + } else if countArg.Kind != OpImm && !isAMD64MemoryOperand(countArg) { + return true, false, fmt.Errorf("%s %s MMX form requires an immediate, MMX, or memory count: %q", c.goarch, baseOp, ins.Raw) + } + dataBits, err := c.loadReg(destination) + if err != nil { + return true, false, err + } + lanes := 64 / spec.laneBits + data := c.bitcastI64ToIntegerLanes(lanes, spec.laneBits, dataBits) + count, err := c.loadPackedUniformLogicalShiftCount(countArg, true) + if err != nil { + return true, false, err + } + result := c.emitPackedLogicalShift(spec, lanes, data, count) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to i64\n", bits, lanes, spec.laneBits, result) + return true, false, c.storeReg(destination, "%"+bits) + } + + if !c.isGoLegacyXReg(destination) { + return true, false, fmt.Errorf("%s %s destination must be an in-range MMX or X register: %q", c.goarch, baseOp, ins.Raw) + } + if countArg.Kind == OpReg { + if !c.isGoLegacyXReg(countArg.Reg) { + return true, false, fmt.Errorf("%s %s XMM form requires an immediate, X, or memory count: %q", c.goarch, baseOp, ins.Raw) + } + } else if countArg.Kind != OpImm && !isAMD64MemoryOperand(countArg) { + return true, false, fmt.Errorf("%s %s XMM form requires an immediate, X, or memory count: %q", c.goarch, baseOp, ins.Raw) + } + dataBytes, err := c.loadX(destination) + if err != nil { + return true, false, err + } + lanes := 128 / spec.laneBits + data := c.bitcastVectorBytesToIntegerLanes(16, lanes, spec.laneBits, dataBytes) + count, err := c.loadPackedUniformLogicalShiftCount(countArg, false) + if err != nil { + return true, false, err + } + result := c.emitPackedLogicalShift(spec, lanes, data, count) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, lanes, spec.laneBits, result) + return true, false, c.storeX(destination, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedLogicalShift(baseOp, suffix string, spec amd64PackedLogicalShiftSpec, ins Instr) (bool, bool, error) { + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix || properties.sae || properties.rounding != "" { + return true, false, fmt.Errorf("%s %s suffix is absent from its Go 1.27 table: %q", c.goarch, baseOp, ins.Raw) + } + if properties.broadcast && spec.laneBits == 16 { + return true, false, fmt.Errorf("%s %s does not enable EVEX broadcast: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects count, source, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7 as its third operand: %q", c.goarch, baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoPackedVectorMoveRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + + countArg, dataArg := ins.Args[0], ins.Args[1] + immediate := countArg.Kind == OpImm + if immediate { + if countArg.Imm < -128 || countArg.Imm > 255 { + return true, false, fmt.Errorf("%s %s immediate count is outside Go's signed/unsigned byte classes: %q", c.goarch, baseOp, ins.Raw) + } + if properties.broadcast { + if !isAMD64MemoryOperand(dataArg) { + return true, false, fmt.Errorf("%s %s.BCST requires an immediate count and scalar memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else if dataArg.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(dataArg, byteWidth) { + return true, false, fmt.Errorf("%s %s source register must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(dataArg) { + return true, false, fmt.Errorf("%s %s immediate form requires matching vector or memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else { + if properties.broadcast { + return true, false, fmt.Errorf("%s %s.BCST is absent from variable-count rows: %q", c.goarch, baseOp, ins.Raw) + } + if countArg.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(countArg, 16) { + return true, false, fmt.Errorf("%s %s variable count must be X/m128: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(countArg) { + return true, false, fmt.Errorf("%s %s variable count must be X/m128: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoPackedVectorMoveRegister(dataArg, byteWidth) { + return true, false, fmt.Errorf("%s %s variable-count data must be a matching vector register: %q", c.goarch, baseOp, ins.Raw) + } + } + + lanes := byteWidth * 8 / spec.laneBits + var data string + if properties.broadcast { + scalar, err := c.evalIntSized(dataArg, amd64IntegerTypeForBits(spec.laneBits)) + if err != nil { + return true, false, err + } + data = amd64SplatInteger(c, lanes, spec.laneBits, scalar) + } else { + bytesValue, err := c.loadPackedCompareBytes(dataArg, byteWidth) + if err != nil { + return true, false, err + } + data = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, bytesValue) + } + count, err := c.loadPackedUniformLogicalShiftCount(countArg, false) + if err != nil { + return true, false, err + } + result := c.emitPackedLogicalShift(spec, lanes, data, count) + if masked { + mask, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) loadPackedUniformLogicalShiftCount(count Operand, mmx bool) (string, error) { + if count.Kind == OpImm { + return fmt.Sprintf("%d", uint8(count.Imm)), nil + } + if mmx { + return c.loadLegacyMMXPackedSource(count) + } + countBytes, err := c.loadXVecOperand(count) + if err != nil { + return "", err + } + countWords := c.newTmp() + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", countWords, countBytes) + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 0\n", low, countWords) + return "%" + low, nil +} + +func (c *amd64Ctx) emitPackedLogicalShift(spec amd64PackedLogicalShiftSpec, lanes int, data, count64 string) string { + inRange := c.newTmp() + safe64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i64 %s, %d\n", inRange, count64, spec.laneBits) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %s, i64 0\n", safe64, inRange, count64) + count := "%" + safe64 + if spec.laneBits < 64 { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrow, count, spec.laneBits) + count = "%" + narrow + } + counts := amd64SplatInteger(c, lanes, spec.laneBits, count) + shifted := c.newTmp() + operation := "lshr" + if spec.left { + operation = "shl" + } + typeName := fmt.Sprintf("<%d x i%d>", lanes, spec.laneBits) + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", shifted, operation, typeName, data, counts) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s zeroinitializer\n", result, inRange, typeName, shifted, typeName) + return "%" + result +} diff --git a/amd64_lower_logical_shift_test.go b/amd64_lower_logical_shift_test.go new file mode 100644 index 00000000..bf9394e7 --- /dev/null +++ b/amd64_lower_logical_shift_test.go @@ -0,0 +1,140 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedLogicalShiftCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast, zLast := 15, 22 + if target.goarch == "386" { + legacyLast, zLast = 7, 7 + } + var source strings.Builder + source.WriteString("TEXT packedlogicalshiftforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PSLLW", "PSLLL", "PSLLQ", "PSRLW", "PSRLL", "PSRLQ"} { + fmt.Fprintf(&source, "\t%s $-1, M1\n", op) + fmt.Fprintf(&source, "\t%s M0, M1\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), M1\n", op) + fmt.Fprintf(&source, "\t%s $3, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s X0, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, legacyLast) + } + for _, op := range []string{"VPSLLW", "VPSLLD", "VPSLLQ", "VPSRLW", "VPSRLD", "VPSRLQ"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&source, "\t%s $-1, %s20, %s21\n", op, width, width) + fmt.Fprintf(&source, "\t%s $255, 8(AX), %s21\n", op, width) + fmt.Fprintf(&source, "\t%s X0, %s20, %s21\n", op, width, width) + fmt.Fprintf(&source, "\t%s 8(AX), %s20, %s21\n", op, width, width) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s $3, %s20, K1, %s22\n", op, width, width) + fmt.Fprintf(&source, "\t%s.Z X0, %s20, K7, %s22\n", op, width, width) + } + } + fmt.Fprintf(&source, "\t%s $3, Z6, Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s $3, 8(AX), Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s X0, Z6, Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s 8(AX), Z6, Z%d\n", op, zLast) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s $3, Z20, K2, Z22\n", op) + fmt.Fprintf(&source, "\t%s.Z 8(AX), Z20, K6, Z22\n", op) + } + if strings.HasSuffix(op, "D") || strings.HasSuffix(op, "Q") { + fmt.Fprintf(&source, "\t%s.BCST $3, 8(AX), X21\n", op) + fmt.Fprintf(&source, "\t%s.BCST $3, 8(AX), Y21\n", op) + fmt.Fprintf(&source, "\t%s.BCST $3, 8(AX), Z%d\n", op, zLast) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.BCST.Z $3, 8(AX), K5, Z22\n", op) + } + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedlogicalshiftforms": {Name: "packedlogicalshiftforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-logical-shift-"+target.name+".ll", "packed-logical-shift-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedLogicalShiftRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PSLLW.Z $3, X0", + "PSLLL $3", + "PSLLQ $-129, X0", + "PSRLW $128, X0", + "PSRLL M0, X1", + "PSRLQ X0, M1", + "VPSLLW $-129, X0, X1", + "VPSLLD $256, X0, X1", + "VPSLLQ Y0, X1, X2", + "VPSRLW X0, 8(AX), X2", + "VPSRLD Y0, X1, X2", + "VPSRLQ.BCST X0, X1, X2", + "VPSLLW.BCST $3, 8(AX), X2", + "VPSLLD.BCST $3, X1, X2", + "VPSRLQ.Z $3, X1, X2", + "VPSLLQ $3, X1, K0, X2", + "VPSRLD $3, X1, K1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedLogicalShiftRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PSLLQ X8, X0", + "PSRLQ X0, X8", + "VPSLLQ $3, Z8, Z1", + "VPSRLQ X0, Z1, Z8", + "VPSLLD $3, X1, K1, X2", + "VPSRLD.Z X0, X1, K1, X2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedLogicalShiftRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedLogicalShiftRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed logical-shift forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_lzcnt.go b/amd64_lower_lzcnt.go new file mode 100644 index 00000000..ae9f9dd8 --- /dev/null +++ b/amd64_lower_lzcnt.go @@ -0,0 +1,53 @@ +package plan9asm + +import "fmt" + +// lowerLeadingZeroCount implements the complete LZCNTW/L/Q yml_rl family. +func (c *amd64Ctx) lowerLeadingZeroCount(op Op, ins Instr) (ok bool, terminated bool, err error) { + bits := 0 + switch op { + case "LZCNTW": + bits = 16 + case "LZCNTL": + bits = 32 + case "LZCNTQ": + bits = 64 + default: + return false, false, nil + } + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", op, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects register/memory source and register destination: %q", c.goarch, op, ins.Raw) + } + source, destination := ins.Args[0], ins.Args[1] + if source.Kind == OpReg { + if !isX86YrlRegisterForArch(source.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yrl class: %q", c.goarch, op, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + value, err := c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + count := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.ctlz.%s(%s %s, i1 false)\n", count, typ, typ, typ, value) + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, 0\n", carry, typ, value) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carry, c.flagsCFSlot) + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, 0\n", zero, typ, count) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + if err := c.storeRegSized(destination.Reg, typ, "%"+count); err != nil { + return true, false, err + } + return true, false, nil +} diff --git a/amd64_lower_lzcnt_test.go b/amd64_lower_lzcnt_test.go new file mode 100644 index 00000000..6cd9add7 --- /dev/null +++ b/amd64_lower_lzcnt_test.go @@ -0,0 +1,192 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86LZCNTCompleteFormsSource(goarch string) string { + var source strings.Builder + symbol := "lzcntdata" + size := 8 + if goarch == "386" { + symbol = "lzcntdata386" + size = 4 + } + fmt.Fprintf(&source, "DATA %s+0(SB)/%d, $1\n", symbol, size) + fmt.Fprintf(&source, "GLOBL %s(SB), $%d\n", symbol, size) + source.WriteString("TEXT lzcntforms(SB),$0-0\n") + widths := []string{"W", "L"} + if goarch == "amd64" { + widths = append(widths, "Q") + } + for _, width := range widths { + fmt.Fprintf(&source, "\tLZCNT%s AX, BX\n", width) + fmt.Fprintf(&source, "\tLZCNT%s 8(BX), CX\n", width) + fmt.Fprintf(&source, "\tLZCNT%s %s(SB), DX\n", width, symbol) + if goarch == "amd64" { + fmt.Fprintf(&source, "\tLZCNT%s R11, R12\n", width) + } else { + fmt.Fprintf(&source, "\tLZCNT%s AX, SP\n", width) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86LZCNTCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86LZCNTCompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"lzcntforms": {Name: "lzcntforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"@llvm.ctlz.i16", "@llvm.ctlz.i32", `"target-features"="+lzcnt"`} { + if !strings.Contains(ll, want) { + t.Fatalf("LZCNT lowering omitted %q:\n%s", want, ll) + } + } + if target.goarch == "amd64" && !strings.Contains(ll, "@llvm.ctlz.i64") { + t.Fatalf("LZCNTQ lowering omitted llvm.ctlz.i64:\n%s", ll) + } + compileLLVMToObject(t, llc, target.triple, "lzcnt-"+target.name+".ll", "lzcnt-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86LZCNTRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "LZCNTW AL, BX"}, + {goarch: "amd64", instruction: "LZCNTL AX, AH"}, + {goarch: "amd64", instruction: "LZCNTQ X0, AX"}, + {goarch: "amd64", instruction: "LZCNTW AX, 0(BX)"}, + {goarch: "amd64", instruction: "LZCNTL $1, AX"}, + {goarch: "amd64", instruction: "LZCNTQ AX"}, + {goarch: "amd64", instruction: "LZCNTW.Z AX, BX"}, + {goarch: "386", instruction: "LZCNTL R8, AX"}, + {goarch: "386", instruction: "LZCNTQ AX, BX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's LZCNT yml_rl table", test.instruction) + } + }) + } +} + +func TestAMD64LZCNTRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT lzcntsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVQ $0x1122334455660000, AX + MOVQ $0xaabbccddeeff1234, BX + LZCNTW AX, BX + MOVQ BX, 0(DI) + SETCS 8(DI) + SETEQ 9(DI) + MOVQ $0x80000000, AX + MOVQ $0x1122334455667788, CX + LZCNTL AX, CX + MOVQ CX, 16(DI) + SETCS 24(DI) + SETEQ 25(DI) + MOVQ $1, 32(DI) + LZCNTQ 32(DI), DX + MOVQ DX, 40(DI) + SETCS 48(DI) + SETEQ 49(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "lzcntsemantics": { + Name: "lzcntsemantics", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void lzcntsemantics(uint8_t *); +int main(void) { + uint8_t out[56] = {0}; + lzcntsemantics(out); + if (*(uint64_t *)(out+0) != UINT64_C(0xaabbccddeeff0010)) return 10; + if (out[8] != 1 || out[9] != 0) return 11; + if (*(uint64_t *)(out+16) != 0) return 12; + if (out[24] != 0 || out[25] != 1) return 13; + if (*(uint64_t *)(out+40) != 63) return 14; + if (out[48] != 0 || out[49] != 0) return 15; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "lzcnt_semantics", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_lzcnt_vector_test.go b/amd64_lower_lzcnt_vector_test.go new file mode 100644 index 00000000..91106217 --- /dev/null +++ b/amd64_lower_lzcnt_vector_test.go @@ -0,0 +1,219 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64PackedBitCountGrammarCoversCompleteGoFamilies(t *testing.T) { + expected := map[Op]amd64PackedBitCountSpec{ + "VPOPCNTB": {laneBits: 8, kind: amd64PackedPopulationCount}, + "VPOPCNTW": {laneBits: 16, kind: amd64PackedPopulationCount}, + "VPOPCNTD": {laneBits: 32, kind: amd64PackedPopulationCount, broadcast: true}, + "VPOPCNTQ": {laneBits: 64, kind: amd64PackedPopulationCount, broadcast: true}, + "VPLZCNTD": {laneBits: 32, kind: amd64PackedLeadingZeroCount, broadcast: true}, + "VPLZCNTQ": {laneBits: 64, kind: amd64PackedLeadingZeroCount, broadcast: true}, + } + if len(amd64PackedBitCountSpecs) != len(expected) { + t.Fatalf("packed-bit-count grammar has %d entries, want %d", len(amd64PackedBitCountSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64PackedBitCountSpecs[op]; !ok { + t.Errorf("packed-bit-count grammar omitted %s", op) + } else if got != want { + t.Errorf("packed-bit-count grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86PackedLeadingZeroCountCompleteGoFormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT packedlzcntforms(SB),$0-0\n") + for _, op := range []string{"VPLZCNTD", "VPLZCNTQ"} { + for _, width := range []string{"X", "Y", "Z"} { + last := 31 + if target.goarch == "386" && width == "Z" { + last = 7 + } + fmt.Fprintf(&source, "\t%s %s0, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s 8(R9), %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s %s1, K1, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s.Z 16(R9), K7, %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST 24(R9), %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST.Z 32(R9), K2, %s%d\n", op, width, last) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"packedlzcntforms": {Name: "packedlzcntforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"@llvm.ctlz.v4i32", "@llvm.ctlz.v8i64", "select i1"} { + if !strings.Contains(ir, want) { + t.Fatalf("packed-LZCNT lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "packed-lzcnt-"+target.name+".ll", "packed-lzcnt-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86PackedLeadingZeroCountRejectsFormsOutsideGoTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VPLZCNTD X0, Y1"}, + {goarch: "amd64", instruction: "VPLZCNTQ Y0, Z1"}, + {goarch: "amd64", instruction: "VPLZCNTD X0, K0, X1"}, + {goarch: "amd64", instruction: "VPLZCNTQ.Z X0, X1"}, + {goarch: "amd64", instruction: "VPLZCNTD.BCST X0, X1"}, + {goarch: "amd64", instruction: "VPLZCNTQ.SAE X0, X1"}, + {goarch: "amd64", instruction: "VPLZCNTD X0, 0(AX)"}, + {goarch: "amd64", instruction: "VPLZCNTQ AX, X1"}, + {goarch: "amd64", instruction: "VPLZCNTD X0, K1, K2, X1"}, + {goarch: "386", instruction: "VPLZCNTD Z8, Z0"}, + {goarch: "386", instruction: "VPLZCNTQ Z0, K1, Z8"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VPLZCNT _yvexpandpd grammar", test.instruction) + } + }) + } +} + +func TestAMD64PackedLeadingZeroCountRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT packedlzcntsemantics(SB),$0-32 + MOVQ out+0(FP), AX + MOVQ source+8(FP), BX + MOVQ old+16(FP), CX + MOVQ mask+24(FP), DX + KMOVQ DX, K1 + VMOVDQU64 0(BX), Z0 + VMOVDQU64 0(CX), Z1 + VPLZCNTD Z0, Z2 + VMOVDQU64 Z2, 0(AX) + VPLZCNTQ 0(BX), Z2 + VMOVDQU64 Z2, 64(AX) + VPLZCNTD Z0, K1, Z1 + VMOVDQU64 Z1, 128(AX) + VMOVDQU64 0(CX), Z1 + VPLZCNTQ.Z 0(BX), K1, Z1 + VMOVDQU64 Z1, 192(AX) + VPLZCNTD.BCST 0(BX), Z2 + VMOVDQU64 Z2, 256(AX) + VPLZCNTQ.BCST.Z 0(BX), K1, Z1 + VMOVDQU64 Z1, 320(AX) + STC + VPLZCNTD Z0, Z2 + SETCS 384(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"packedlzcntsemantics": { + Name: "packedlzcntsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: I64, Index: 3, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void packedlzcntsemantics(uint8_t *, const uint8_t *, const uint8_t *, uint64_t); +static unsigned lz32(uint32_t v) { unsigned n = 0; if (!v) return 32; while (!(v & UINT32_C(0x80000000))) { n++; v <<= 1; } return n; } +static unsigned lz64(uint64_t v) { unsigned n = 0; if (!v) return 64; while (!(v & UINT64_C(0x8000000000000000))) { n++; v <<= 1; } return n; } +int main(void) { + uint32_t source32[16], old32[16]; uint8_t out[385] = {0}; + const uint64_t mask = UINT64_C(0xa55a); + for (int i = 0; i < 16; i++) { source32[i] = i ? (UINT32_C(1) << ((i*7)%32)) : 0; old32[i] = UINT32_C(0x90000000) + i; } + packedlzcntsemantics(out, (const uint8_t *)source32, (const uint8_t *)old32, mask); + uint32_t *plain32=(uint32_t *)(out+0), *merge32=(uint32_t *)(out+128), *broadcast32=(uint32_t *)(out+256); + for (int i=0;i<16;i++) { + if (plain32[i] != lz32(source32[i])) return 10+i; + uint32_t want = (mask>>i)&1 ? lz32(source32[i]) : old32[i]; + if (merge32[i] != want) return 30+i; + if (broadcast32[i] != lz32(source32[0])) return 50+i; + } + uint64_t source64[8], old64[8], plain64[8], zero64[8], broadcast64[8]; + memcpy(source64, source32, 64); memcpy(old64, old32, 64); + memcpy(plain64,out+64,64); memcpy(zero64,out+192,64); memcpy(broadcast64,out+320,64); + for (int i=0;i<8;i++) { + if (plain64[i] != lz64(source64[i])) return 70+i; + uint64_t want = (mask>>i)&1 ? lz64(source64[i]) : 0; + if (zero64[i] != want) return 80+i; + want = (mask>>i)&1 ? lz64(source64[0]) : 0; + if (broadcast64[i] != want) return 90+i; + } + if (out[384] != 1) return 100; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_lzcnt_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_machine_register.go b/amd64_lower_machine_register.go new file mode 100644 index 00000000..8fef3a57 --- /dev/null +++ b/amd64_lower_machine_register.go @@ -0,0 +1,224 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +// lowerMachineRegisterMove covers the complete machine-state-register portion +// of Go 1.27's x86 ymovtab: CR, DR, and TR registers plus the descriptor-state +// aliases GDTR, IDTR, LDTR, MSW, and TASK. Segment and TLS moves are a separate +// family. +func (c *amd64Ctx) lowerMachineRegisterMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + if baseOp != "MOVW" && baseOp != "MOVL" && baseOp != "MOVQ" { + return false, false, nil + } + if len(ins.Args) != 2 { + return false, false, nil + } + sourceClass, sourceIndex, sourceSpecial := x86MachineRegisterOperand(ins.Args[0]) + destinationClass, destinationIndex, destinationSpecial := x86MachineRegisterOperand(ins.Args[1]) + if !sourceSpecial && !destinationSpecial { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s machine-register %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if sourceSpecial == destinationSpecial { + return true, false, fmt.Errorf("%s %s machine-register form expects exactly one special register: %q", c.goarch, baseOp, ins.Raw) + } + + specialClass, specialIndex := sourceClass, sourceIndex + other := ins.Args[1] + readSpecial := sourceSpecial + if destinationSpecial { + specialClass, specialIndex = destinationClass, destinationIndex + other = ins.Args[0] + } + + switch specialClass { + case "cr": + return true, false, c.lowerControlDebugRegisterMove(baseOp, "cr", specialIndex, other, readSpecial, ins) + case "dr": + return true, false, c.lowerControlDebugRegisterMove(baseOp, "dr", specialIndex, other, readSpecial, ins) + case "tr": + return true, false, c.lowerTestRegisterMove(baseOp, specialIndex, other, readSpecial, ins) + case "gdtr", "idtr", "ldtr", "msw", "task": + return true, false, c.lowerDescriptorRegisterAlias(baseOp, specialClass, other, readSpecial, ins) + default: + panic("machine-register classifier drift") + } +} + +func x86MachineRegisterOperand(operand Operand) (class string, index int, ok bool) { + if operand.Kind != OpReg { + return "", 0, false + } + return x86MachineRegister(operand.Reg) +} + +func x86MachineRegister(reg Reg) (class string, index int, ok bool) { + name := strings.ToUpper(string(reg)) + switch name { + case "GDTR", "IDTR", "LDTR", "MSW", "TASK": + return strings.ToLower(name), 0, true + } + if len(name) < 3 { + return "", 0, false + } + prefix := strings.ToLower(name[:2]) + if prefix != "cr" && prefix != "dr" && prefix != "tr" { + return "", 0, false + } + index, err := strconv.Atoi(name[2:]) + if err != nil { + return "", 0, false + } + return prefix, index, true +} + +func (c *amd64Ctx) lowerControlDebugRegisterMove(op, class string, index int, other Operand, readSpecial bool, ins Instr) error { + if op != "MOVL" && op != "MOVQ" { + return fmt.Errorf("%s %s %s register form is absent from Go 1.27's ymovtab: %q", c.goarch, op, strings.ToUpper(class), ins.Raw) + } + allowed := false + switch class { + case "cr": + allowed = index == 0 || index == 2 || index == 3 || index == 4 || index == 8 + if index == 8 && c.goarch == "386" { + allowed = false + } + case "dr": + if op == "MOVL" { + allowed = index == 0 || index == 6 || index == 7 + } else { + allowed = index == 0 || index == 2 || index == 3 || index == 6 || index == 7 + } + } + if !allowed { + return fmt.Errorf("%s %s %s%d form is absent from Go 1.27's ymovtab: %q", c.goarch, op, strings.ToUpper(class), index, ins.Raw) + } + if other.Kind != OpReg || !isX86YrlRegisterForArch(other.Reg, c.goarch) { + return fmt.Errorf("%s %s %s%d expects a Go 1.27 Yrl GP register: %q", c.goarch, op, strings.ToUpper(class), index, ins.Raw) + } + + special := fmt.Sprintf("%%%s%d", class, index) + hardwareType := I64 + if c.goarch == "386" { + hardwareType = I32 + } + constraints := "~{memory},~{dirflag},~{fpsr},~{flags}" + if readSpecial { + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q()\n", + call, hardwareType, "mov "+special+", $0", "=r,"+constraints) + value := "%" + call + resultType := hardwareType + if op == "MOVL" && hardwareType == I64 { + value = c.truncI64(value, I32) + resultType = I32 + } + return c.storeRegSized(other.Reg, resultType, value) + } + + value, err := c.loadReg(other.Reg) + if err != nil { + return err + } + if hardwareType == I32 { + value = c.truncI64(value, I32) + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s %s)\n", + "mov $0, "+special, "r,"+constraints, hardwareType, value) + return nil +} + +func (c *amd64Ctx) lowerTestRegisterMove(op string, index int, other Operand, readSpecial bool, ins Instr) error { + if op != "MOVL" || (index != 6 && index != 7) { + return fmt.Errorf("%s %s TR%d form is absent from Go 1.27's ymovtab: %q", c.goarch, op, index, ins.Raw) + } + if other.Kind == OpReg { + if !isX86YrlRegisterForArch(other.Reg, c.goarch) { + return fmt.Errorf("%s MOVL TR%d operand is outside Go 1.27's Yml class: %q", c.goarch, index, ins.Raw) + } + } else if !isAMD64MemoryOperand(other) { + return fmt.Errorf("%s MOVL TR%d expects a Go 1.27 Yml register or memory: %q", c.goarch, index, ins.Raw) + } + modRM := 0xc0 | byte(index<<3) + constraints := "~{memory},~{dirflag},~{fpsr},~{flags}" + if readSpecial { + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 asm sideeffect %q, %q()\n", + call, fmt.Sprintf(".byte 0x0f, 0x24, 0x%02x", modRM), "={ax},"+constraints) + return c.storeScalarIntegerOperand(other, I32, "%"+call) + } + value, err := c.evalIntSized(other, I32) + if err != nil { + return err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(i32 %s)\n", + fmt.Sprintf(".byte 0x0f, 0x26, 0x%02x", modRM), "{ax},"+constraints, value) + return nil +} + +func (c *amd64Ctx) lowerDescriptorRegisterAlias(op, class string, other Operand, readSpecial bool, ins Instr) error { + directOp := "" + switch class { + case "gdtr": + if op != "MOVL" && op != "MOVQ" { + break + } + if readSpecial { + directOp = "SGDT" + } else { + directOp = "LGDT" + } + case "idtr": + if op != "MOVL" && op != "MOVQ" { + break + } + if readSpecial { + directOp = "SIDT" + } else { + directOp = "LIDT" + } + case "ldtr": + if op == "MOVW" { + if readSpecial { + directOp = "SLDTW" + } else { + directOp = "LLDT" + } + } + case "msw": + if op == "MOVW" { + if readSpecial { + directOp = "SMSWW" + } else { + directOp = "LMSW" + } + } + case "task": + if op == "MOVW" { + if readSpecial { + directOp = "STRW" + } else { + directOp = "LTR" + } + } + } + if directOp == "" { + return fmt.Errorf("%s %s %s form is absent from Go 1.27's ymovtab: %q", c.goarch, op, strings.ToUpper(class), ins.Raw) + } + ok, _, err := c.lowerDescriptorTable(Op(directOp), Instr{Op: Op(directOp), Args: []Operand{other}, Raw: ins.Raw}) + if !ok { + panic("descriptor MOV alias lowering drift") + } + return err +} diff --git a/amd64_lower_maddubsw_test.go b/amd64_lower_maddubsw_test.go new file mode 100644 index 00000000..0d47b427 --- /dev/null +++ b/amd64_lower_maddubsw_test.go @@ -0,0 +1,115 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateX86PackedUnsignedSignedByteMultiplyAddCompleteGoAssemblerForms(t *testing.T) { + amd64Source := `TEXT packedmaddubswforms(SB),NOSPLIT,$0-0 + PMADDUBSW X0, X1 + PMADDUBSW (AX), X15 + VPMADDUBSW X0, X1, X2 + VPMADDUBSW (AX), X1, X2 + VPMADDUBSW Y0, Y1, Y2 + VPMADDUBSW (AX), Y1, Y2 + VPMADDUBSW Z0, Z1, Z2 + VPMADDUBSW (AX), Z1, Z2 + VPMADDUBSW X20, X21, X22 + VPMADDUBSW Y20, Y21, Y22 + VPMADDUBSW Z20, Z21, Z22 + VPMADDUBSW X20, X21, K1, X22 + VPMADDUBSW.Z (AX), X21, K2, X22 + VPMADDUBSW Y20, Y21, K3, Y22 + VPMADDUBSW.Z (AX), Y21, K4, Y22 + VPMADDUBSW Z20, Z21, K5, Z22 + VPMADDUBSW.Z (AX), Z21, K6, Z22 + RET +` + ll := translateAMD64EcosystemCase(t, amd64Source, "packedmaddubswforms") + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "packed-maddubsw-amd64.ll", "packed-maddubsw-amd64.o", ll) + + file, err := Parse(ArchAMD64, `TEXT packedmaddubswforms386(SB),NOSPLIT,$0-0 + PMADDUBSW X0, X1 + PMADDUBSW (AX), X7 + VPMADDUBSW X0, X1, X2 + VPMADDUBSW (AX), X1, X2 + VPMADDUBSW Y0, Y1, Y2 + VPMADDUBSW (AX), Y1, Y2 + VPMADDUBSW Z0, Z1, Z7 + VPMADDUBSW (AX), Z6, Z7 + VPMADDUBSW X20, X21, X22 + VPMADDUBSW Y20, Y21, Y22 + RET +`) + if err != nil { + t.Fatal(err) + } + ll386, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{ + "packedmaddubswforms386": {Name: "packedmaddubswforms386", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, "i386-unknown-linux-gnu", "packed-maddubsw-386.ll", "packed-maddubsw-386.o", ll386) +} + +func TestTranslateX86PackedUnsignedSignedByteMultiplyAddRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PMADDUBSW.Z X0, X1", + "PMADDUBSW X0", + "PMADDUBSW M0, M1", + "PMADDUBSW Y0, Y1", + "PMADDUBSW X0, (AX)", + "VPMADDUBSW X0, X1", + "VPMADDUBSW X0, Y1, Y2", + "VPMADDUBSW X0, X1, (AX)", + "VPMADDUBSW.BCST (AX), X1, X2", + "VPMADDUBSW.Z X0, X1, X2", + "VPMADDUBSW X0, X1, K0, X2", + "VPMADDUBSW X0, X1, K1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's PMADDUBSW/VPMADDUBSW tables", instruction) + } + }) + } + + for _, instruction := range []string{ + "PMADDUBSW X8, X0", + "PMADDUBSW X0, X8", + "VPMADDUBSW Z8, Z1, Z2", + "VPMADDUBSW Z0, Z1, Z8", + "VPMADDUBSW X0, X1, K1, X2", + "VPMADDUBSW.Z X0, X1, K1, X2", + } { + file, err := Parse(ArchAMD64, "TEXT bad386(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad386": {Name: "bad386", Ret: Void}}, + }); err == nil { + t.Fatalf("386 Translate accepted architecture-restricted %q", instruction) + } + } +} diff --git a/amd64_lower_maddword.go b/amd64_lower_maddword.go new file mode 100644 index 00000000..5843e129 --- /dev/null +++ b/amd64_lower_maddword.go @@ -0,0 +1,263 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedWordMultiplyAdd implements both complete packed multiply-add +// families in Go 1.27: PMADDWL/VPMADDWD and PMADDUBSW/VPMADDUBSW. +func (c *amd64Ctx) lowerPackedWordMultiplyAdd(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + switch baseOp { + case "PMADDWL": + return c.lowerLegacyPackedWordMultiplyAdd(suffix, ins) + case "PMADDUBSW": + return c.lowerLegacyPackedUnsignedSignedByteMultiplyAdd(suffix, ins) + case "VPMADDWD": + return c.lowerVectorPackedMultiplyAdd(baseOp, suffix, ins, false) + case "VPMADDUBSW": + return c.lowerVectorPackedMultiplyAdd(baseOp, suffix, ins, true) + default: + return false, false, nil + } +} + +func (c *amd64Ctx) lowerLegacyPackedUnsignedSignedByteMultiplyAdd(suffix string, ins Instr) (bool, bool, error) { + if suffix != "" { + return true, false, fmt.Errorf("%s PMADDUBSW does not accept instruction suffixes: %q", c.goarch, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg || !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("%s PMADDUBSW expects X/m128, X: %q", c.goarch, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s PMADDUBSW source is outside Go 1.27's legacy X class: %q", c.goarch, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s PMADDUBSW source must be X or memory: %q", c.goarch, ins.Raw) + } + // Intel's first encoded source is the legacy destination and supplies + // unsigned bytes. Plan 9 lists the signed r/m source first. + signedBytes, err := c.loadPackedCompareBytes(ins.Args[0], 16) + if err != nil { + return true, false, err + } + unsignedBytes, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + signed := c.bitcastVectorBytesToIntegerLanes(16, 16, 8, signedBytes) + unsigned := c.bitcastVectorBytesToIntegerLanes(16, 16, 8, unsignedBytes) + result := c.emitPackedUnsignedSignedByteMultiplyAdd(16, signed, unsigned) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <8 x i16> %s to <16 x i8>\n", out, result) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) +} + +func (c *amd64Ctx) lowerLegacyPackedWordMultiplyAdd(suffix string, ins Instr) (bool, bool, error) { + if suffix != "" { + return true, false, fmt.Errorf("%s PMADDWL does not accept instruction suffixes: %q", c.goarch, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s PMADDWL expects MMX/m64, MMX or X/m128, X: %q", c.goarch, ins.Raw) + } + destination := ins.Args[1].Reg + if _, mmx := amd64ParseMReg(destination); mmx { + if c.goarch == "386" { + return true, false, fmt.Errorf("386 PMADDWL MMX form is illegal in 32-bit mode: %q", ins.Raw) + } + firstBits, err := c.loadLegacyMMXPackedSource(ins.Args[0]) + if err != nil { + return true, false, fmt.Errorf("amd64 PMADDWL MMX source: %w", err) + } + secondBits, err := c.loadReg(destination) + if err != nil { + return true, false, err + } + first := c.bitcastI64ToIntegerLanes(4, 16, firstBits) + second := c.bitcastI64ToIntegerLanes(4, 16, secondBits) + result := c.emitPackedWordMultiplyAdd(4, first, second) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i32> %s to i64\n", bits, result) + return true, false, c.storeReg(destination, "%"+bits) + } + + if !c.isGoLegacyXReg(destination) { + return true, false, fmt.Errorf("%s PMADDWL destination is outside Go 1.27's legacy X class: %q", c.goarch, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s PMADDWL source is outside Go 1.27's legacy X class: %q", c.goarch, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s PMADDWL source must be X or memory: %q", c.goarch, ins.Raw) + } + firstBytes, err := c.loadPackedCompareBytes(ins.Args[0], 16) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(destination) + if err != nil { + return true, false, err + } + first := c.bitcastVectorBytesToIntegerLanes(16, 8, 16, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(16, 8, 16, secondBytes) + result := c.emitPackedWordMultiplyAdd(8, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %s to <16 x i8>\n", out, result) + return true, false, c.storeX(destination, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedMultiplyAdd(baseOp, suffix string, ins Instr, unsignedSignedBytes bool) (bool, bool, error) { + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("%s %s has a suffix absent from its Go 1.27 optab: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects src1, src2, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects a vector-register destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s expects an X, Y, or Z destination: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoPackedVectorMoveRegister(destination, byteWidth) || !c.isGoPackedVectorMoveRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s second source and destination must be same-width vector registers: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match its destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + var err error + mask, err = c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + } + firstBytes, err := c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + inputLaneBits := 16 + resultLaneBits := 32 + if unsignedSignedBytes { + inputLaneBits = 8 + resultLaneBits = 16 + } + inputLanes := byteWidth * 8 / inputLaneBits + first := c.bitcastVectorBytesToIntegerLanes(byteWidth, inputLanes, inputLaneBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(byteWidth, inputLanes, inputLaneBits, secondBytes) + var result string + if unsignedSignedBytes { + // Plan 9's r/m source (first argument) supplies signed bytes; the + // encoded V source (second argument) supplies unsigned bytes. + result = c.emitPackedUnsignedSignedByteMultiplyAdd(inputLanes, first, second) + } else { + result = c.emitPackedWordMultiplyAdd(inputLanes, first, second) + } + resultLanes := inputLanes / 2 + if masked { + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, resultLanes, resultLaneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, resultLanes, resultLaneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, resultLanes, resultLaneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPackedWordMultiplyAdd(wordLanes int, first, second string) string { + wordType := fmt.Sprintf("<%d x i16>", wordLanes) + wideType := fmt.Sprintf("<%d x i32>", wordLanes) + firstWide := c.newTmp() + secondWide := c.newTmp() + products := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", firstWide, wordType, first, wideType) + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", secondWide, wordType, second, wideType) + fmt.Fprintf(c.b, " %%%s = mul %s %%%s, %%%s\n", products, wideType, firstWide, secondWide) + resultLanes := wordLanes / 2 + result := "zeroinitializer" + for lane := 0; lane < resultLanes; lane++ { + low := c.newTmp() + high := c.newTmp() + sum := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", low, wideType, products, lane*2) + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", high, wideType, products, lane*2+1) + fmt.Fprintf(c.b, " %%%s = add i32 %%%s, %%%s\n", sum, low, high) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i32> %s, i32 %%%s, i32 %d\n", inserted, resultLanes, result, sum, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) emitPackedUnsignedSignedByteMultiplyAdd(byteLanes int, signedBytes, unsignedBytes string) string { + byteType := fmt.Sprintf("<%d x i8>", byteLanes) + wideType := fmt.Sprintf("<%d x i32>", byteLanes) + signedWide := c.newTmp() + unsignedWide := c.newTmp() + products := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", signedWide, byteType, signedBytes, wideType) + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", unsignedWide, byteType, unsignedBytes, wideType) + fmt.Fprintf(c.b, " %%%s = mul %s %%%s, %%%s\n", products, wideType, signedWide, unsignedWide) + resultLanes := byteLanes / 2 + result := "zeroinitializer" + for lane := 0; lane < resultLanes; lane++ { + low := c.newTmp() + high := c.newTmp() + sum := c.newTmp() + below := c.newTmp() + lowerClamped := c.newTmp() + above := c.newTmp() + clamped := c.newTmp() + narrow := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", low, wideType, products, lane*2) + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", high, wideType, products, lane*2+1) + fmt.Fprintf(c.b, " %%%s = add i32 %%%s, %%%s\n", sum, low, high) + fmt.Fprintf(c.b, " %%%s = icmp slt i32 %%%s, -32768\n", below, sum) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 -32768, i32 %%%s\n", lowerClamped, below, sum) + fmt.Fprintf(c.b, " %%%s = icmp sgt i32 %%%s, 32767\n", above, lowerClamped) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 32767, i32 %%%s\n", clamped, above, lowerClamped) + fmt.Fprintf(c.b, " %%%s = trunc i32 %%%s to i16\n", narrow, clamped) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i16> %s, i16 %%%s, i32 %d\n", inserted, resultLanes, result, narrow, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_mask_arithmetic.go b/amd64_lower_mask_arithmetic.go new file mode 100644 index 00000000..681fb582 --- /dev/null +++ b/amd64_lower_mask_arithmetic.go @@ -0,0 +1,63 @@ +package plan9asm + +import "fmt" + +type amd64MaskArithmeticSpec struct { + bits int + shift string +} + +// amd64MaskArithmeticSpecs covers Go 1.27's complete KADD and KSHIFT +// families. KADD wraps at the named mask width; KSHIFT produces zero when the +// unsigned byte count is greater than or equal to that width. +var amd64MaskArithmeticSpecs = map[Op]amd64MaskArithmeticSpec{ + "KADDB": {bits: 8}, "KADDW": {bits: 16}, "KADDD": {bits: 32}, "KADDQ": {bits: 64}, + "KSHIFTLB": {bits: 8, shift: "shl"}, "KSHIFTLW": {bits: 16, shift: "shl"}, + "KSHIFTLD": {bits: 32, shift: "shl"}, "KSHIFTLQ": {bits: 64, shift: "shl"}, + "KSHIFTRB": {bits: 8, shift: "lshr"}, "KSHIFTRW": {bits: 16, shift: "lshr"}, + "KSHIFTRD": {bits: 32, shift: "lshr"}, "KSHIFTRQ": {bits: 64, shift: "lshr"}, +} + +func (c *amd64Ctx) lowerMaskArithmetic(op Op, ins Instr) error { + spec := amd64MaskArithmeticSpecs[op] + if spec.shift == "" { + if len(ins.Args) != 3 { + return fmt.Errorf("%s %s expects three K-register operands: %q", c.goarch, op, ins.Raw) + } + for _, arg := range ins.Args { + if !amd64IsKOperand(arg) { + return fmt.Errorf("%s %s expects only K0..K7 operands: %q", c.goarch, op, ins.Raw) + } + } + first, err := c.loadK(ins.Args[0].Reg) + if err != nil { + return err + } + second, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return err + } + first = c.maskMoveI64(first, spec.bits) + second = c.maskMoveI64(second, spec.bits) + added := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", added, first, second) + return c.storeK(ins.Args[2].Reg, c.maskMoveI64("%"+added, spec.bits)) + } + + if len(ins.Args) != 3 || !amd64UnsignedImmediate(ins.Args[0], 8) || !amd64IsKOperand(ins.Args[1]) || !amd64IsKOperand(ins.Args[2]) { + return fmt.Errorf("%s %s expects $u8, K0..K7, K0..K7: %q", c.goarch, op, ins.Raw) + } + source, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return err + } + source = c.maskMoveI64(source, spec.bits) + result := "0" + count := int(uint8(ins.Args[0].Imm)) + if count < spec.bits { + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s i64 %s, %d\n", shifted, spec.shift, source, count) + result = c.maskMoveI64("%"+shifted, spec.bits) + } + return c.storeK(ins.Args[2].Reg, result) +} diff --git a/amd64_lower_mask_arithmetic_test.go b/amd64_lower_mask_arithmetic_test.go new file mode 100644 index 00000000..a6eb7a3b --- /dev/null +++ b/amd64_lower_mask_arithmetic_test.go @@ -0,0 +1,168 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86MaskArithmeticCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT maskArithmeticForms(SB),$0-0\n") + for _, width := range []string{"B", "W", "D", "Q"} { + fmt.Fprintf(&source, "\tKADD%s K0, K7, K3\n", width) + fmt.Fprintf(&source, "\tKSHIFTL%s $0, K3, K4\n", width) + fmt.Fprintf(&source, "\tKSHIFTR%s $255, K4, K7\n", width) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "maskArithmeticForms": {Name: "maskArithmeticForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "mask-arithmetic-"+target.name+".ll", "mask-arithmetic-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86MaskArithmeticRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "KADDB K1, K2", + "KADDW K1, AX, K2", + "KADDD K1, K2, K8", + "KADDQ.Z K1, K2, K3", + "KSHIFTLB K1, K2", + "KSHIFTLW $-1, K1, K2", + "KSHIFTLD $1, AX, K2", + "KSHIFTRQ $1, K1, K8", + "KSHIFTRB.Z $1, K1, K2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + for _, goarch := range []string{"amd64", "386"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, goarch, source, false) + assertX86MaskArithmeticRejected(t, goarch, instruction) + } + }) + } +} + +func assertX86MaskArithmeticRejected(t *testing.T, goarch, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %s %q outside Go 1.27's KADD/KSHIFT tables", goarch, instruction) + } +} + +func TestAMD64MaskArithmeticRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT maskArithmetic(SB),$0-24 + MOVQ out+0(FP), AX + KMOVQ a+8(FP), K1 + KMOVQ b+16(FP), K2 + KADDB K1, K2, K3 + KADDW K1, K2, K4 + KSHIFTLW $3, K1, K5 + KSHIFTRW $4, K2, K6 + KSHIFTRB $9, K2, K7 + KMOVQ K3, 0(AX) + KMOVQ K4, 8(AX) + KMOVQ K5, 16(AX) + KMOVQ K6, 24(AX) + KMOVQ K7, 32(AX) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }} + triple := "x86_64-apple-darwin" + if runtime.GOOS != "darwin" { + triple = testTargetTriple(runtime.GOOS, "amd64") + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "maskArithmetic": {Name: "maskArithmetic", Args: []LLVMType{Ptr, I64, I64}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void maskArithmetic(uint64_t *, uint64_t, uint64_t); +int main(void) { + uint64_t out[5] = {0}; + uint64_t a = 0x123456789abcdef5ULL; + uint64_t b = 0xfedcba98765432f0ULL; + maskArithmetic(out, a, b); + if (out[0] != ((a + b) & 0xff)) return 1; + if (out[1] != ((a + b) & 0xffff)) return 2; + if (out[2] != ((a & 0xffff) << 3 & 0xffff)) return 3; + if (out[3] != ((b & 0xffff) >> 4)) return 4; + if (out[4] != 0) return 5; + return 0; +} +` + var runPrefix []string + if crossRosetta { + runPrefix = []string{"arch", "-x86_64"} + } + compileAndRunRuntimeTestForTarget(t, llc, clang, "mask_arithmetic", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_mask_logical.go b/amd64_lower_mask_logical.go new file mode 100644 index 00000000..e63a7eef --- /dev/null +++ b/amd64_lower_mask_logical.go @@ -0,0 +1,155 @@ +package plan9asm + +import "fmt" + +type amd64MaskLogicalKind uint8 + +const ( + amd64MaskAnd amd64MaskLogicalKind = iota + amd64MaskAndNot + amd64MaskOr + amd64MaskXNOR + amd64MaskXOR + amd64MaskNot + amd64MaskTest + amd64MaskOrTest +) + +type amd64MaskLogicalSpec struct { + kind amd64MaskLogicalKind + bits int +} + +// amd64MaskLogicalSpecs is the complete Go 1.27 x86 mask-register logical +// family. Binary forms use _ykaddb (K,K,K); unary and flag-setting forms use +// _yknotb (K,K). Go accepts every listed form in both amd64 and 386 mode. +var amd64MaskLogicalSpecs = map[Op]amd64MaskLogicalSpec{ + "KANDB": {amd64MaskAnd, 8}, "KANDW": {amd64MaskAnd, 16}, "KANDD": {amd64MaskAnd, 32}, "KANDQ": {amd64MaskAnd, 64}, + "KANDNB": {amd64MaskAndNot, 8}, "KANDNW": {amd64MaskAndNot, 16}, "KANDND": {amd64MaskAndNot, 32}, "KANDNQ": {amd64MaskAndNot, 64}, + "KORB": {amd64MaskOr, 8}, "KORW": {amd64MaskOr, 16}, "KORD": {amd64MaskOr, 32}, "KORQ": {amd64MaskOr, 64}, + "KXNORB": {amd64MaskXNOR, 8}, "KXNORW": {amd64MaskXNOR, 16}, "KXNORD": {amd64MaskXNOR, 32}, "KXNORQ": {amd64MaskXNOR, 64}, + "KXORB": {amd64MaskXOR, 8}, "KXORW": {amd64MaskXOR, 16}, "KXORD": {amd64MaskXOR, 32}, "KXORQ": {amd64MaskXOR, 64}, + "KNOTB": {amd64MaskNot, 8}, "KNOTW": {amd64MaskNot, 16}, "KNOTD": {amd64MaskNot, 32}, "KNOTQ": {amd64MaskNot, 64}, + "KTESTB": {amd64MaskTest, 8}, "KTESTW": {amd64MaskTest, 16}, "KTESTD": {amd64MaskTest, 32}, "KTESTQ": {amd64MaskTest, 64}, + "KORTESTB": {amd64MaskOrTest, 8}, "KORTESTW": {amd64MaskOrTest, 16}, "KORTESTD": {amd64MaskOrTest, 32}, "KORTESTQ": {amd64MaskOrTest, 64}, +} + +func (c *amd64Ctx) lowerMaskLogical(op Op, ins Instr) error { + spec := amd64MaskLogicalSpecs[op] + wantArgs := 3 + if spec.kind == amd64MaskNot || spec.kind == amd64MaskTest || spec.kind == amd64MaskOrTest { + wantArgs = 2 + } + if len(ins.Args) != wantArgs { + return fmt.Errorf("amd64 %s expects %d K-register operands: %q", op, wantArgs, ins.Raw) + } + for _, arg := range ins.Args { + if arg.Kind != OpReg { + return fmt.Errorf("amd64 %s expects only K-register operands: %q", op, ins.Raw) + } + if _, ok := amd64ParseKReg(arg.Reg); !ok { + return fmt.Errorf("amd64 %s operand is not K0..K7: %q", op, ins.Raw) + } + } + + load := func(arg Operand) (string, error) { + value, err := c.loadK(arg.Reg) + if err != nil { + return "", err + } + if spec.bits == 64 { + return value, nil + } + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %s\n", masked, value, amd64MaskWidthLiteral(spec.bits)) + return "%" + masked, nil + } + + first, err := load(ins.Args[0]) + if err != nil { + return err + } + second, err := load(ins.Args[1]) + if err != nil { + return err + } + if spec.kind == amd64MaskTest || spec.kind == amd64MaskOrTest { + return c.lowerMaskLogicalFlags(spec, first, second) + } + + var result string + switch spec.kind { + case amd64MaskNot: + not := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i64 %s, %s\n", not, first, amd64MaskWidthLiteral(spec.bits)) + result = "%" + not + case amd64MaskAnd, amd64MaskOr, amd64MaskXOR, amd64MaskXNOR, amd64MaskAndNot: + operation := "and" + lhs, rhs := first, second + switch spec.kind { + case amd64MaskOr: + operation = "or" + case amd64MaskXOR, amd64MaskXNOR: + operation = "xor" + case amd64MaskAndNot: + // Go's first source is the r/m operand and its second source is + // VEX.vvvv, so KANDN computes first & ~second. + notSecond := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i64 %s, %s\n", notSecond, second, amd64MaskWidthLiteral(spec.bits)) + rhs = "%" + notSecond + } + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s i64 %s, %s\n", combined, operation, lhs, rhs) + result = "%" + combined + if spec.kind == amd64MaskXNOR { + not := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i64 %s, %s\n", not, result, amd64MaskWidthLiteral(spec.bits)) + result = "%" + not + } + default: + return fmt.Errorf("amd64 %s has unknown mask logical operation", op) + } + if spec.bits != 64 { + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %s\n", masked, result, amd64MaskWidthLiteral(spec.bits)) + result = "%" + masked + } + return c.storeK(ins.Args[wantArgs-1].Reg, result) +} + +func (c *amd64Ctx) lowerMaskLogicalFlags(spec amd64MaskLogicalSpec, first, second string) error { + operation := "and" + if spec.kind == amd64MaskOrTest { + operation = "or" + } + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s i64 %s, %s\n", combined, operation, first, second) + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i64 %%%s, 0\n", zero, combined) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + + carry := c.newTmp() + if spec.kind == amd64MaskTest { + notSecond := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i64 %s, %s\n", notSecond, second, amd64MaskWidthLiteral(spec.bits)) + andNot := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %%%s\n", andNot, first, notSecond) + fmt.Fprintf(c.b, " %%%s = icmp eq i64 %%%s, 0\n", carry, andNot) + } else { + and := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %s\n", and, first, second) + fmt.Fprintf(c.b, " %%%s = icmp eq i64 %%%s, %s\n", carry, and, amd64MaskWidthLiteral(spec.bits)) + } + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carry, c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsSltSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsPFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + return nil +} + +func amd64MaskWidthLiteral(bits int) string { + if bits == 64 { + return "-1" + } + return fmt.Sprintf("%d", uint64(1)<memory, K->GP, +// K-or-memory->K, and GP->K rows. Go accepts these rows in amd64 and 386 mode. +var amd64MaskMoveSpecs = map[Op]int{ + "KMOVB": 8, + "KMOVW": 16, + "KMOVD": 32, + "KMOVQ": 64, +} + +func (c *amd64Ctx) lowerMaskMove(op Op, ins Instr) error { + if len(ins.Args) != 2 { + return fmt.Errorf("amd64 %s expects two operands from Go 1.27's _ykmovb table: %q", op, ins.Raw) + } + bits := amd64MaskMoveSpecs[op] + src, dst := ins.Args[0], ins.Args[1] + srcK := amd64IsKOperand(src) + dstK := amd64IsKOperand(dst) + srcGP := amd64IsYrlOperand(src, c.goarch) + dstGP := amd64IsYrlOperand(dst, c.goarch) + srcMem := isAMD64MemoryOperand(src) + dstMem := isAMD64MemoryOperand(dst) + + valid := (srcK && (dstMem || dstGP || dstK)) || ((srcMem || srcGP) && dstK) + if !valid { + return fmt.Errorf("amd64 %s operands are outside Go 1.27's _ykmovb table: %q", op, ins.Raw) + } + + value, err := c.loadMaskMoveValue(src, bits, srcK) + if err != nil { + return err + } + switch { + case dstK: + return c.storeK(dst.Reg, value) + case dstGP: + // The GP-destination encodings zero-extend B/W/D results. Store the + // already-masked value as the complete modeled register value. + base, _ := amd64FullRegBase(dst.Reg) + return c.storeReg(base, value) + case dstMem: + return c.storeMaskMoveMemory(dst, bits, value) + default: + return fmt.Errorf("amd64 %s has unsupported destination: %q", op, ins.Raw) + } +} + +func amd64IsKOperand(operand Operand) bool { + if operand.Kind != OpReg { + return false + } + _, ok := amd64ParseKReg(operand.Reg) + return ok +} + +func amd64IsYrlOperand(operand Operand, goarch string) bool { + return operand.Kind == OpReg && isX86YrlRegisterForArch(operand.Reg, goarch) +} + +func (c *amd64Ctx) loadMaskMoveValue(src Operand, bits int, sourceIsK bool) (string, error) { + if sourceIsK { + value, err := c.loadK(src.Reg) + if err != nil { + return "", err + } + return c.maskMoveI64(value, bits), nil + } + + typ := amd64IntegerTypeForBits(bits) + value, err := c.evalIntSized(src, typ) + if err != nil { + return "", err + } + if bits == 64 { + return value, nil + } + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to i64\n", extended, typ, value) + return "%" + extended, nil +} + +func (c *amd64Ctx) maskMoveI64(value string, bits int) string { + if bits == 64 { + return value + } + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %s\n", masked, value, amd64MaskWidthLiteral(bits)) + return "%" + masked +} + +func (c *amd64Ctx) storeMaskMoveMemory(dst Operand, bits int, value string) error { + typ := amd64IntegerTypeForBits(bits) + stored := value + if bits != 64 { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to %s\n", truncated, value, typ) + stored = "%" + truncated + } + switch dst.Kind { + case OpFP: + return c.storeFPResult(dst.FPOffset, typ, stored) + case OpMem: + ptr, ptrType, err := c.ptrFromMem(dst.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, %s %s, align 1\n", typ, stored, ptrType, ptr) + return nil + case OpSym: + ptr, err := c.ptrFromSB(dst.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, ptr %s, align 1\n", typ, stored, ptr) + return nil + default: + return fmt.Errorf("amd64 mask move expected a memory destination, got %s", dst.String()) + } +} diff --git a/amd64_lower_mask_to_vector.go b/amd64_lower_mask_to_vector.go new file mode 100644 index 00000000..188c3473 --- /dev/null +++ b/amd64_lower_mask_to_vector.go @@ -0,0 +1,115 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var amd64MaskToVectorLaneBits = map[Op]int{ + "VPMOVM2B": 8, + "VPMOVM2W": 16, + "VPMOVM2D": 32, + "VPMOVM2Q": 64, +} + +var amd64VectorToMaskLaneBits = map[Op]int{ + "VPMOVB2M": 8, + "VPMOVW2M": 16, + "VPMOVD2M": 32, + "VPMOVQ2M": 64, +} + +// lowerMaskToVector implements the AVX-512 mask-to-vector family. Each mask +// bit becomes an all-zero or all-one element in the selected B/W/D/Q vector; +// the result is materialized in the same byte-backed register model as other +// packed operations. +func (c *amd64Ctx) lowerMaskToVector(op Op, ins Instr) (ok bool, terminated bool, err error) { + laneBits, handled := amd64MaskToVectorLaneBits[op] + if !handled { + return false, false, nil + } + if len(ins.Args) != 2 || !amd64IsKOperand(ins.Args[0]) || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects K0-K7 and X/Y/Z destination operands: %q", op, ins.Raw) + } + destination := strings.ToUpper(string(ins.Args[1].Reg)) + vectorBits := 0 + store := func(string) error { return nil } + var vectorType string + switch { + case strings.HasPrefix(destination, "X"): + vectorBits = 128 + vectorType = fmt.Sprintf("<%d x i%d>", vectorBits/laneBits, laneBits) + store = func(value string) error { return c.storeX(ins.Args[1].Reg, value) } + case strings.HasPrefix(destination, "Y"): + vectorBits = 256 + vectorType = fmt.Sprintf("<%d x i%d>", vectorBits/laneBits, laneBits) + store = func(value string) error { return c.storeY(ins.Args[1].Reg, value) } + case strings.HasPrefix(destination, "Z"): + vectorBits = 512 + vectorType = fmt.Sprintf("<%d x i%d>", vectorBits/laneBits, laneBits) + store = func(value string) error { return c.storeZ(ins.Args[1].Reg, value) } + default: + return true, false, fmt.Errorf("amd64 %s destination must be X, Y, or Z vector register: %q", op, ins.Raw) + } + mask, err := c.loadK(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + lanes := vectorBits / laneBits + vector := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i64 %s, %d\n", shifted, mask, lane) + bit := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i1\n", bit, shifted) + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d -1, i%d 0\n", element, bit, laneBits, laneBits) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %%%s, i32 %d\n", inserted, vectorType, vector, laneBits, element, lane) + vector = "%" + inserted + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", bytes, vectorType, vector, vectorBits/8) + return true, false, store("%" + bytes) +} + +// lowerVectorToMask implements the reverse AVX-512 family. Each result mask +// bit is the most significant bit of its corresponding B/W/D/Q vector lane. +func (c *amd64Ctx) lowerVectorToMask(op Op, ins Instr) (ok bool, terminated bool, err error) { + laneBits, handled := amd64VectorToMaskLaneBits[op] + if !handled { + return false, false, nil + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects X/Y/Z source and K0-K7 destination operands: %q", c.goarch, op, ins.Raw) + } + source := ins.Args[0] + byteWidth, validWidth := amd64PackedCompareWidth(source) + if !validWidth || !c.isGoPackedVectorMoveRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source must be an in-range X, Y, or Z register: %q", c.goarch, op, ins.Raw) + } + destination := ins.Args[1] + if !amd64IsKOperand(destination) { + return true, false, fmt.Errorf("%s %s destination must be K0-K7: %q", c.goarch, op, ins.Raw) + } + bytes, err := c.loadPackedCompareBytes(source, byteWidth) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / laneBits + vectorType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + vector := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", vector, byteWidth, bytes, vectorType) + signBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt %s %%%s, zeroinitializer\n", signBits, vectorType, vector) + packedType := fmt.Sprintf("i%d", lanes) + packed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i1> %%%s to %s\n", packed, lanes, signBits, packedType) + result := "%" + packed + if lanes < 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to i64\n", wide, packedType, result) + result = "%" + wide + } + return true, false, c.storeK(destination.Reg, result) +} diff --git a/amd64_lower_mask_to_vector_test.go b/amd64_lower_mask_to_vector_test.go new file mode 100644 index 00000000..8aa9cd0e --- /dev/null +++ b/amd64_lower_mask_to_vector_test.go @@ -0,0 +1,148 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86MaskToVectorMoveCompleteForms(t *testing.T) { + for _, target := range []struct { + name, goarch, triple string + }{ + {"darwin-amd64", "amd64", "x86_64-apple-darwin"}, + {"linux-amd64", "amd64", "x86_64-unknown-linux-gnu"}, + {"windows-amd64", "amd64", "x86_64-pc-windows-msvc"}, + {"linux-386", "386", "i386-unknown-linux-gnu"}, + {"windows-386", "386", "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT maskvectorforms(SB),$0-0\n") + index := 0 + for _, lane := range []string{"B", "W", "D", "Q"} { + for _, width := range []string{"X", "Y", "Z"} { + vector := index%7 + 1 + mask := index % 8 + fmt.Fprintf(&source, "\tVPMOVM2%s K%d, %s%d\n", lane, mask, width, vector) + fmt.Fprintf(&source, "\tVPMOV%s2M %s%d, K%d\n", lane, width, vector, mask) + index++ + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: target.goarch, TargetTriple: target.triple, Sigs: map[string]FuncSig{"maskvectorforms": {Name: "maskvectorforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, fmt.Sprintf("mask-to-vector-%s.ll", target.name), fmt.Sprintf("mask-to-vector-%s.o", target.name), ir) + }) + } +} + +func TestTranslateX86MaskVectorMoveRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPMOVM2B X0, X1", + "VPMOVM2W K0, 0(AX)", + "VPMOVM2D.Z K0, Z1", + "VPMOVM2Q K8, Z1", + "VPMOVB2M K0, K1", + "VPMOVW2M 0(AX), K1", + "VPMOVD2M.Z Z0, K1", + "VPMOVQ2M Z0, K8", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + for _, goarch := range []string{"amd64", "386"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + continue + } + triple := "x86_64-unknown-linux-gnu" + if goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{Goarch: goarch, TargetTriple: triple, Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %s %q outside Go 1.27's mask/vector move table", goarch, instruction) + } + } + }) + } +} + +func TestAMD64MaskVectorMoveRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT maskVectorMoves(SB),NOSPLIT,$0-16 + MOVQ out+0(FP), AX + KMOVQ mask+8(FP), K1 + VPMOVM2B K1, Z0 + VPMOVB2M Z0, K2 + KMOVQ K2, 0(AX) + VPMOVM2W K1, Z1 + VPMOVW2M Z1, K3 + KMOVQ K3, 8(AX) + VPMOVM2D K1, Z2 + VPMOVD2M Z2, K4 + KMOVQ K4, 16(AX) + VPMOVM2Q K1, Z3 + VPMOVQ2M Z3, K5 + KMOVQ K5, 24(AX) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "maskVectorMoves": {Name: "maskVectorMoves", Args: []LLVMType{Ptr, I64}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void maskVectorMoves(uint64_t *, uint64_t); +int main(void) { + uint64_t out[4] = {0}; + uint64_t mask = 0xd6a539c7f04b821dULL; + maskVectorMoves(out, mask); + if (out[0] != mask) return 1; + if (out[1] != (mask & 0xffffffffULL)) return 2; + if (out[2] != (mask & 0xffffULL)) return 3; + if (out[3] != (mask & 0xffULL)) return 4; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "mask_vector_moves", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_mask_unpack.go b/amd64_lower_mask_unpack.go new file mode 100644 index 00000000..a4902553 --- /dev/null +++ b/amd64_lower_mask_unpack.go @@ -0,0 +1,44 @@ +package plan9asm + +import "fmt" + +// amd64MaskUnpackBits covers Go 1.27's complete KUNPCK family. The Plan 9 +// first source is the encoded r/m operand and becomes the low half; the second +// source is VEX.vvvv and becomes the high half of the destination mask. +var amd64MaskUnpackBits = map[Op]int{ + "KUNPCKBW": 8, + "KUNPCKWD": 16, + "KUNPCKDQ": 32, +} + +func (c *amd64Ctx) lowerMaskUnpack(op Op, ins Instr) error { + bits := amd64MaskUnpackBits[op] + if len(ins.Args) != 3 { + return fmt.Errorf("%s %s expects three K-register operands: %q", c.goarch, op, ins.Raw) + } + for _, arg := range ins.Args { + if !amd64IsKOperand(arg) { + return fmt.Errorf("%s %s expects only K0..K7 operands: %q", c.goarch, op, ins.Raw) + } + } + + low, err := c.loadK(ins.Args[0].Reg) + if err != nil { + return err + } + high, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return err + } + low = c.maskMoveI64(low, bits) + high = c.maskMoveI64(high, bits) + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i64 %s, %d\n", shifted, high, bits) + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %s\n", combined, shifted, low) + result := "%" + combined + if bits < 32 { + result = c.maskMoveI64(result, bits*2) + } + return c.storeK(ins.Args[2].Reg, result) +} diff --git a/amd64_lower_mask_unpack_test.go b/amd64_lower_mask_unpack_test.go new file mode 100644 index 00000000..ffa85ac0 --- /dev/null +++ b/amd64_lower_mask_unpack_test.go @@ -0,0 +1,158 @@ +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateX86MaskUnpackCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + const source = `TEXT maskunpackforms(SB),$0-0 + KUNPCKBW K0, K7, K3 + KUNPCKBW K2, K4, K4 + KUNPCKWD K7, K5, K3 + KUNPCKDQ K1, K6, K0 + KUNPCKDQ K5, K5, K5 + RET +` + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"maskunpackforms": {Name: "maskunpackforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"shl i64", "or i64", "255", "65535", "4294967295"} { + if !strings.Contains(ir, want) { + t.Fatalf("mask unpack lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "mask-unpack-"+target.name+".ll", "mask-unpack-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86MaskUnpackRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "KUNPCKBW K1, K2", + "KUNPCKWD K1, K2, K3, K4", + "KUNPCKDQ AX, K2, K3", + "KUNPCKBW K1, K8, K3", + "KUNPCKWD K1, K2, K8", + "KUNPCKDQ.Z K1, K2, K3", + } { + for _, goarch := range []string{"amd64", "386"} { + t.Run(goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's KUNPCK table for %s", instruction, goarch) + } + }) + } + } +} + +func TestAMD64MaskUnpackRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT maskunpacksemantics(SB),$0-24 + MOVQ out+0(FP), AX + KMOVQ a+8(FP), K1 + KMOVQ b+16(FP), K2 + STC + KUNPCKBW K1, K2, K3 + KMOVQ K3, 0(AX) + SETCS 24(AX) + KUNPCKWD K1, K2, K4 + KMOVQ K4, 8(AX) + KUNPCKDQ K1, K2, K2 + KMOVQ K2, 16(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "maskunpacksemantics": { + Name: "maskunpacksemantics", Args: []LLVMType{Ptr, I64, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void maskunpacksemantics(uint8_t *, uint64_t, uint64_t); +int main(void) { + uint8_t storage[25] = {0}; + uint64_t *out = (uint64_t *)storage; + uint64_t a = UINT64_C(0x0123456789abcdef); + uint64_t b = UINT64_C(0xfedcba9876543210); + maskunpacksemantics(storage, a, b); + if (out[0] != ((b & 0xff) << 8 | (a & 0xff))) return 10; + if (out[1] != ((b & 0xffff) << 16 | (a & 0xffff))) return 11; + if (out[2] != ((b & UINT64_C(0xffffffff)) << 32 | (a & UINT64_C(0xffffffff)))) return 12; + if (storage[24] != 1) return 13; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "mask_unpack_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_minmax.go b/amd64_lower_minmax.go new file mode 100644 index 00000000..d46c1a04 --- /dev/null +++ b/amd64_lower_minmax.go @@ -0,0 +1,126 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedIntegerMinMaxSpec struct { + laneBits int + signed bool + minimum bool + broadcast bool +} + +// lowerPackedIntegerMinMax implements the complete 16-opcode min/max family +// in Go 1.27. B/W/D forms use _yvandnpd, Q forms use _yvblendmpd, and only +// D/Q encodings enable scalar-memory broadcast. +func (c *amd64Ctx) lowerPackedIntegerMinMax(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, found := amd64PackedIntegerMinMaxSpecs[baseOp] + if !found { + return false, false, nil + } + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix || properties.sae || properties.rounding != "" { + return true, false, fmt.Errorf("%s %s suffix is absent from its Go 1.27 encodings: %q", c.goarch, baseOp, ins.Raw) + } + if properties.broadcast && !spec.broadcast { + return true, false, fmt.Errorf("%s %s does not enable EVEX broadcast: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects source2, source1, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7 as its third operand: %q", baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || + !c.isGoPackedVectorMoveRegister(destination, byteWidth) || + !c.isGoPackedVectorMoveRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s source1 and destination must be matching Go vector registers: %q", c.goarch, baseOp, ins.Raw) + } + first := ins.Args[0] + if properties.broadcast { + if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory source2: %q", c.goarch, baseOp, ins.Raw) + } + } else if first.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(first, byteWidth) { + return true, false, fmt.Errorf("%s %s source2 register must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("%s %s source2 must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := byteWidth * 8 / spec.laneBits + firstValue, err := c.loadPackedCompareLanes(first, byteWidth, spec.laneBits, properties.broadcast) + if err != nil { + return true, false, err + } + secondValue, err := c.loadPackedCompareLanes(ins.Args[1], byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + predicate := "ult" + if spec.signed { + predicate = "slt" + } + if !spec.minimum { + predicate = strings.Replace(predicate, "lt", "gt", 1) + } + compared := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %s <%d x i%d> %s, %s\n", compared, predicate, lanes, spec.laneBits, secondValue, firstValue) + computed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, <%d x i%d> %s, <%d x i%d> %s\n", computed, lanes, compared, lanes, spec.laneBits, secondValue, lanes, spec.laneBits, firstValue) + result := "%" + computed + if masked { + mask, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +var amd64PackedIntegerMinMaxSpecs = map[string]amd64PackedIntegerMinMaxSpec{ + "VPMINSB": {laneBits: 8, signed: true, minimum: true}, + "VPMINUB": {laneBits: 8, minimum: true}, + "VPMAXSB": {laneBits: 8, signed: true}, + "VPMAXUB": {laneBits: 8}, + "VPMINSW": {laneBits: 16, signed: true, minimum: true}, + "VPMINUW": {laneBits: 16, minimum: true}, + "VPMAXSW": {laneBits: 16, signed: true}, + "VPMAXUW": {laneBits: 16}, + "VPMINSD": {laneBits: 32, signed: true, minimum: true, broadcast: true}, + "VPMINUD": {laneBits: 32, minimum: true, broadcast: true}, + "VPMAXSD": {laneBits: 32, signed: true, broadcast: true}, + "VPMAXUD": {laneBits: 32, broadcast: true}, + "VPMINSQ": {laneBits: 64, signed: true, minimum: true, broadcast: true}, + "VPMINUQ": {laneBits: 64, minimum: true, broadcast: true}, + "VPMAXSQ": {laneBits: 64, signed: true, broadcast: true}, + "VPMAXUQ": {laneBits: 64, broadcast: true}, +} diff --git a/amd64_lower_minmax_test.go b/amd64_lower_minmax_test.go new file mode 100644 index 00000000..f63361cd --- /dev/null +++ b/amd64_lower_minmax_test.go @@ -0,0 +1,137 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedIntegerMinMaxCompleteGoAssemblerForms(t *testing.T) { + type operation struct { + name string + broadcast bool + } + operations := []operation{ + {name: "VPMINSB"}, {name: "VPMINUB"}, {name: "VPMAXSB"}, {name: "VPMAXUB"}, + {name: "VPMINSW"}, {name: "VPMINUW"}, {name: "VPMAXSW"}, {name: "VPMAXUW"}, + {name: "VPMINSD", broadcast: true}, {name: "VPMINUD", broadcast: true}, + {name: "VPMAXSD", broadcast: true}, {name: "VPMAXUD", broadcast: true}, + {name: "VPMINSQ", broadcast: true}, {name: "VPMINUQ", broadcast: true}, + {name: "VPMAXSQ", broadcast: true}, {name: "VPMAXUQ", broadcast: true}, + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + zLast := 22 + if target.goarch == "386" { + zLast = 7 + } + var source strings.Builder + source.WriteString("TEXT packedintegerminmaxforms(SB),NOSPLIT,$0-0\n") + for _, operation := range operations { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&source, "\t%s %s0, %s1, %s2\n", operation.name, width, width, width) + fmt.Fprintf(&source, "\t%s 8(AX), %s20, %s21\n", operation.name, width, width) + if operation.broadcast { + fmt.Fprintf(&source, "\t%s.BCST 16(AX), %s20, %s22\n", operation.name, width, width) + } + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s %s20, %s21, K1, %s22\n", operation.name, width, width, width) + fmt.Fprintf(&source, "\t%s.Z 8(AX), %s21, K7, %s22\n", operation.name, width, width) + if operation.broadcast { + fmt.Fprintf(&source, "\t%s.BCST.Z 16(AX), %s21, K2, %s22\n", operation.name, width, width) + } + } + } + fmt.Fprintf(&source, "\t%s Z0, Z6, Z%d\n", operation.name, zLast) + fmt.Fprintf(&source, "\t%s 8(AX), Z6, Z%d\n", operation.name, zLast) + if operation.broadcast { + fmt.Fprintf(&source, "\t%s.BCST 16(AX), Z6, Z%d\n", operation.name, zLast) + } + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s Z20, Z21, K3, Z22\n", operation.name) + fmt.Fprintf(&source, "\t%s.Z 8(AX), Z21, K4, Z22\n", operation.name) + if operation.broadcast { + fmt.Fprintf(&source, "\t%s.BCST.Z 16(AX), Z21, K5, Z22\n", operation.name) + } + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedintegerminmaxforms": {Name: "packedintegerminmaxforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-integer-minmax-"+target.name+".ll", "packed-integer-minmax-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedIntegerMinMaxRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "VPMINUB X0, X1", + "VPMAXUB X0, X1, (AX)", + "VPMINSW X0, Y1, X2", + "VPMAXUW Z0, Z1, Y2", + "VPMINSD X0, X1, K0, X2", + "VPMAXUD X0, K1, X1, X2", + "VPMINSQ.Z X0, X1, X2", + "VPMAXUQ.SAE X0, X1, X2", + "VPMINUB.BCST 8(AX), X1, X2", + "VPMAXSW.BCST 8(AX), X1, X2", + "VPMINUD.BCST X0, X1, X2", + "VPMAXSQ.BCST 8(AX), Y1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedIntegerMinMaxRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "VPMINUB Z8, Z0, Z1", + "VPMAXUW Z0, Z8, Z1", + "VPMINSD Z0, Z1, Z8", + "VPMAXUQ X0, X1, K1, X2", + "VPMINSQ.Z X0, X1, K1, X2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedIntegerMinMaxRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedIntegerMinMaxRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed min/max forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_minpos.go b/amd64_lower_minpos.go new file mode 100644 index 00000000..7d48384f --- /dev/null +++ b/amd64_lower_minpos.go @@ -0,0 +1,81 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// Keep the complete opcode set in a package-level Op map so corpus coverage +// extraction sees this family without depending on spelling tests in the +// lowering body. +var amd64PackedUnsignedWordMinimumPositionVector = map[Op]bool{ + "PHMINPOSUW": false, + "VPHMINPOSUW": true, +} + +// lowerPackedUnsignedWordMinimumPosition implements every Go 1.27 form of +// PHMINPOSUW (yxm_q4) and VPHMINPOSUW (_yvaesimc). Both tables are restricted +// to a single X/m128 source and an X destination; the VEX spelling is also a +// two-operand, destructive-looking Plan 9 form. +func (c *amd64Ctx) lowerPackedUnsignedWordMinimumPosition(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + vector, recognized := amd64PackedUnsignedWordMinimumPositionVector[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed forms in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects X/m128, X: %q", c.goarch, baseOp, ins.Raw) + } + validRegister := func(arg Operand, allowMemory bool) bool { + if vector { + return c.isGoVEXVectorRegister(arg, 16, allowMemory) + } + if allowMemory && isAMD64MemoryOperand(arg) { + return true + } + return arg.Kind == OpReg && c.isGoLegacyXReg(arg.Reg) + } + if !validRegister(ins.Args[0], true) || !validRegister(ins.Args[1], false) { + return true, false, fmt.Errorf("%s %s requires an in-range X/m128 source and X destination: %q", c.goarch, baseOp, ins.Raw) + } + bytesValue, err := c.loadPackedCompareBytes(ins.Args[0], 16) + if err != nil { + return true, false, err + } + words := c.bitcastVectorBytesToIntegerLanes(16, 8, 16, bytesValue) + result := c.emitPackedUnsignedWordMinimumPosition(words) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <8 x i16> %s to <16 x i8>\n", out, result) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) +} + +func (c *amd64Ctx) emitPackedUnsignedWordMinimumPosition(words string) string { + minimum := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <8 x i16> %s, i32 0\n", minimum, words) + minimumValue := "%" + minimum + indexValue := "0" + for lane := 1; lane < 8; lane++ { + value := c.newTmp() + less := c.newTmp() + selectedMinimum := c.newTmp() + selectedIndex := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <8 x i16> %s, i32 %d\n", value, words, lane) + fmt.Fprintf(c.b, " %%%s = icmp ult i16 %%%s, %s\n", less, value, minimumValue) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i16 %%%s, i16 %s\n", selectedMinimum, less, value, minimumValue) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i16 %d, i16 %s\n", selectedIndex, less, lane, indexValue) + minimumValue = "%" + selectedMinimum + indexValue = "%" + selectedIndex + } + withMinimum := c.newTmp() + withIndex := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <8 x i16> zeroinitializer, i16 %s, i32 0\n", withMinimum, minimumValue) + fmt.Fprintf(c.b, " %%%s = insertelement <8 x i16> %%%s, i16 %s, i32 1\n", withIndex, withMinimum, indexValue) + return "%" + withIndex +} diff --git a/amd64_lower_minpos_test.go b/amd64_lower_minpos_test.go new file mode 100644 index 00000000..955ba8af --- /dev/null +++ b/amd64_lower_minpos_test.go @@ -0,0 +1,99 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedUnsignedWordMinimumPositionCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 15 + if target.goarch == "386" { + last = 7 + } + source := fmt.Sprintf("TEXT packedminimumpositionforms(SB),NOSPLIT,$0-0\n"+ + "\tPHMINPOSUW X0, X%d\n"+ + "\tPHMINPOSUW 8(AX), X%d\n"+ + "\tVPHMINPOSUW X0, X%d\n"+ + "\tVPHMINPOSUW 8(AX), X%d\n"+ + "\tRET\n", last, last, last, last) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedminimumpositionforms": {Name: "packedminimumpositionforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-minimum-position-"+target.name+".ll", "packed-minimum-position-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedUnsignedWordMinimumPositionRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PHMINPOSUW.Z X0, X1", + "PHMINPOSUW X0", + "PHMINPOSUW M0, M1", + "PHMINPOSUW Y0, Y1", + "PHMINPOSUW X0, (AX)", + "VPHMINPOSUW.Z X0, X1", + "VPHMINPOSUW X0", + "VPHMINPOSUW X0, X1, X2", + "VPHMINPOSUW Y0, Y1", + "VPHMINPOSUW Z0, Z1", + "VPHMINPOSUW X0, K1, X1", + "VPHMINPOSUW X0, (AX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedUnsignedWordMinimumPositionRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PHMINPOSUW X8, X0", + "PHMINPOSUW X0, X8", + "VPHMINPOSUW X8, X0", + "VPHMINPOSUW X0, X8", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedUnsignedWordMinimumPositionRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedUnsignedWordMinimumPositionRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's PHMINPOSUW forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_mov.go b/amd64_lower_mov.go index 82de66eb..9ab984f5 100644 --- a/amd64_lower_mov.go +++ b/amd64_lower_mov.go @@ -6,8 +6,17 @@ import ( ) func (c *amd64Ctx) lowerMov(op Op, ins Instr) (ok bool, terminated bool, err error) { + if ok, terminated, err := c.lowerMOVNTI(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerMOVBE(op, ins); ok { + return ok, terminated, err + } switch op { - case "MOVQ", "MOVD", "MOVL", "MOVLQZX", "MOVLQSX", "MOVBQZX", "MOVBLZX", "MOVB", "MOVW", "MOVWLZX", "MOVWQZX", "MOVWQSX", "CMOVQLT": + case "MOVQ", "MOVD", "MOVL", "MOVB", "MOVW", "CMOVQLT", + "MOVBWSX", "MOVBWZX", "MOVBLSX", "MOVBLZX", "MOVBQSX", "MOVBQZX", + "MOVWLSX", "MOVWLZX", "MOVWQSX", "MOVWQZX", "MOVLQSX", "MOVLQZX", + "MOVSWW", "MOVZWW": // ok default: return false, false, nil @@ -15,71 +24,13 @@ func (c *amd64Ctx) lowerMov(op Op, ins Instr) (ok bool, terminated bool, err err if len(ins.Args) != 2 { return true, false, fmt.Errorf("amd64 %s expects 2 operands: %q", op, ins.Raw) } - src, dst := ins.Args[0], ins.Args[1] - zeroExtendSmallDst := false - if op == "MOVLQZX" { - op = "MOVL" + if _, ok := amd64ScalarExtensionMoveSpecs[op]; ok { + return true, false, c.lowerScalarExtensionMove(op, ins) } + src, dst := ins.Args[0], ins.Args[1] if op == "MOVD" { op = "MOVQ" } - if op == "MOVBQZX" || op == "MOVBLZX" { - op = "MOVB" - zeroExtendSmallDst = true - } - if op == "MOVWQZX" || op == "MOVWLZX" { - op = "MOVW" - zeroExtendSmallDst = true - } - if op == "MOVLQSX" || op == "MOVWQSX" { - // Sign-extend i32/i16 source to i64 destination register. - if dst.Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects dst reg: %q", op, ins.Raw) - } - srcTy := I32 - if op == "MOVWQSX" { - srcTy = I16 - } - var sv string - switch src.Kind { - case OpImm: - switch srcTy { - case I16: - sv = fmt.Sprintf("%d", int16(src.Imm)) - default: - sv = fmt.Sprintf("%d", int32(src.Imm)) - } - case OpReg, OpFP: - v64, err := c.evalI64(src) - if err != nil { - return true, false, err - } - tr := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to %s\n", tr, v64, srcTy) - sv = "%" + tr - case OpMem: - p, ptrType, err := c.ptrFromMem(src.Mem) - if err != nil { - return true, false, err - } - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load %s, %s %s, align 1\n", ld, srcTy, ptrType, p) - sv = "%" + ld - case OpSym: - p, err := c.ptrFromSB(src.Sym) - if err != nil { - return true, false, err - } - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", ld, srcTy, p) - sv = "%" + ld - default: - return true, false, fmt.Errorf("amd64 %s unsupported src: %q", op, ins.Raw) - } - se := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sext %s %s to i64\n", se, srcTy, sv) - return true, false, c.storeReg(dst.Reg, "%"+se) - } // Vector moves are handled in lowerVec. if dst.Kind == OpReg { @@ -123,6 +74,17 @@ func (c *amd64Ctx) lowerMov(op Op, ins Instr) (ok bool, terminated bool, err err widthTy := I8 if op == "MOVW" { widthTy = I16 + } else { + // ymovb uses Yrb for register operands on both sides. The + // compatibility closure through Ymb is identical for registers, + // including Go's synthesized BP/SI/DI support on 386, but excludes + // the amd64-only explicit low-byte aliases when translating 386. + if src.Kind == OpReg && !isGoYmbRegisterForArch(src.Reg, c.goarch) { + return true, false, fmt.Errorf("amd64 MOVB source register is outside its Go 1.27 class: %q", ins.Raw) + } + if dst.Kind == OpReg && !isGoYmbRegisterForArch(dst.Reg, c.goarch) { + return true, false, fmt.Errorf("amd64 MOVB destination register is outside its Go 1.27 class: %q", ins.Raw) + } } var small string switch src.Kind { @@ -165,11 +127,6 @@ func (c *amd64Ctx) lowerMov(op Op, ins Instr) (ok bool, terminated bool, err err } switch dst.Kind { case OpReg: - if zeroExtendSmallDst { - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext %s %s to i64\n", z, widthTy, small) - return true, false, c.storeReg(dst.Reg, "%"+z) - } return true, false, c.storeRegSized(dst.Reg, widthTy, small) case OpFP: return true, false, c.storeFPResult(dst.FPOffset, widthTy, small) @@ -274,16 +231,11 @@ func (c *amd64Ctx) lowerMov(op Op, ins Instr) (ok bool, terminated bool, err err case "MOVL": // MOVL src, dst - if c.goarch != "386" && dst.Kind == OpFP { - // Preserve the established amd64 ABI result-slot lowering. - if src.Kind != OpReg { - return true, false, fmt.Errorf("amd64 MOVL expects reg, fp for stores: %q", ins.Raw) - } - v64, err := c.loadReg(src.Reg) - if err != nil { - return true, false, err - } - return true, false, c.storeFPResult(dst.FPOffset, I64, v64) + // FP result slots are memory operands in Go's ymovl table, so only a + // GP register or a 32-bit immediate can write them. Vector-register + // rows are handled by lowerVec before this scalar lowerer. + if dst.Kind == OpFP && src.Kind != OpReg && src.Kind != OpImm { + return true, false, fmt.Errorf("%s MOVL does not allow memory-to-result-memory: %q", c.goarch, ins.Raw) } i32v, err := c.evalIntSized(src, I32) diff --git a/amd64_lower_mov_extension.go b/amd64_lower_mov_extension.go new file mode 100644 index 00000000..407bb6d7 --- /dev/null +++ b/amd64_lower_mov_extension.go @@ -0,0 +1,70 @@ +package plan9asm + +import "fmt" + +type amd64ScalarExtensionMoveSpec struct { + sourceBits int + destinationBits int + signed bool + rejectedOn386 bool +} + +// amd64ScalarExtensionMoveSpecs is the complete Go 1.27 x86 scalar +// sign/zero-extension family from the ymb_rl and yml_rl tables. +var amd64ScalarExtensionMoveSpecs = map[Op]amd64ScalarExtensionMoveSpec{ + "MOVBWSX": {sourceBits: 8, destinationBits: 16, signed: true}, + "MOVBWZX": {sourceBits: 8, destinationBits: 16}, + "MOVBLSX": {sourceBits: 8, destinationBits: 32, signed: true}, + "MOVBLZX": {sourceBits: 8, destinationBits: 32}, + "MOVBQSX": {sourceBits: 8, destinationBits: 64, signed: true, rejectedOn386: true}, + "MOVBQZX": {sourceBits: 8, destinationBits: 64, rejectedOn386: true}, + "MOVWLSX": {sourceBits: 16, destinationBits: 32, signed: true}, + "MOVWLZX": {sourceBits: 16, destinationBits: 32}, + "MOVWQSX": {sourceBits: 16, destinationBits: 64, signed: true, rejectedOn386: true}, + "MOVWQZX": {sourceBits: 16, destinationBits: 64, rejectedOn386: true}, + "MOVLQSX": {sourceBits: 32, destinationBits: 64, signed: true, rejectedOn386: true}, + // Go 1.27 accepts MOVLQZX in 386 mode because it is encoded as MOVL. + "MOVLQZX": {sourceBits: 32, destinationBits: 64}, + "MOVSWW": {sourceBits: 16, destinationBits: 16, signed: true}, + "MOVZWW": {sourceBits: 16, destinationBits: 16}, +} + +func (c *amd64Ctx) lowerScalarExtensionMove(op Op, ins Instr) error { + spec := amd64ScalarExtensionMoveSpecs[op] + if c.goarch == "386" && spec.rejectedOn386 { + return fmt.Errorf("386 %s is outside Go 1.27's scalar extension tables: %q", op, ins.Raw) + } + + src, dst := ins.Args[0], ins.Args[1] + if dst.Kind != OpReg || !isX86YrlRegisterForArch(dst.Reg, c.goarch) { + return fmt.Errorf("amd64 %s expects a Yrl destination register: %q", op, ins.Raw) + } + if src.Kind == OpReg { + valid := isX86YrlRegisterForArch(src.Reg, c.goarch) + if spec.sourceBits == 8 { + valid = isGoYmbRegisterForArch(src.Reg, c.goarch) + } + if !valid { + return fmt.Errorf("amd64 %s source register is outside its Go 1.27 class: %q", op, ins.Raw) + } + } else if !isAMD64MemoryOperand(src) { + return fmt.Errorf("amd64 %s expects a register or memory source: %q", op, ins.Raw) + } + + sourceType := amd64IntegerTypeForBits(spec.sourceBits) + destinationType := amd64IntegerTypeForBits(spec.destinationBits) + value, err := c.evalIntSized(src, sourceType) + if err != nil { + return err + } + if spec.sourceBits < spec.destinationBits { + extended := c.newTmp() + extension := "zext" + if spec.signed { + extension = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", extended, extension, sourceType, value, destinationType) + value = "%" + extended + } + return c.storeRegSized(dst.Reg, destinationType, value) +} diff --git a/amd64_lower_movbe.go b/amd64_lower_movbe.go new file mode 100644 index 00000000..36dd23fb --- /dev/null +++ b/amd64_lower_movbe.go @@ -0,0 +1,67 @@ +package plan9asm + +import "fmt" + +// lowerMOVBE implements both rows of Go 1.27's ymovbe table: memory to +// general register and general register to memory, for W/L/Q widths. +func (c *amd64Ctx) lowerMOVBE(op Op, ins Instr) (ok bool, terminated bool, err error) { + typ := LLVMType("") + switch op { + case "MOVBEW": + typ = I16 + case "MOVBEL": + typ = I32 + case "MOVBEQ": + if c.goarch == "386" { + return true, false, fmt.Errorf("386 MOVBEQ is illegal in 32-bit mode: %q", ins.Raw) + } + typ = I64 + default: + return false, false, nil + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects one memory and one general-register operand: %q", c.goarch, op, ins.Raw) + } + source, destination := ins.Args[0], ins.Args[1] + sourceRegister := source.Kind == OpReg && isX86YrlRegisterForArch(source.Reg, c.goarch) + destinationRegister := destination.Kind == OpReg && isX86YrlRegisterForArch(destination.Reg, c.goarch) + sourceMemory := isAMD64MemoryOperand(source) + destinationMemory := isAMD64MemoryOperand(destination) + if !((sourceMemory && destinationRegister) || (sourceRegister && destinationMemory)) { + return true, false, fmt.Errorf("%s %s operands are outside Go 1.27's Ym,Yrl/Yrl,Ym rows: %q", c.goarch, op, ins.Raw) + } + + value, err := c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + swapped := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.bswap.%s(%s %s)\n", swapped, typ, typ, typ, value) + if destinationRegister { + return true, false, c.storeRegSized(destination.Reg, typ, "%"+swapped) + } + return true, false, c.storeMOVBEMemory(destination, typ, "%"+swapped) +} + +func (c *amd64Ctx) storeMOVBEMemory(destination Operand, typ LLVMType, value string) error { + switch destination.Kind { + case OpMem: + pointer, pointerType, err := c.ptrFromMem(destination.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, %s %s, align 1\n", typ, value, pointerType, pointer) + return nil + case OpFP: + return c.storeFPResult(destination.FPOffset, typ, value) + case OpSym: + pointer, err := c.ptrFromSB(destination.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, ptr %s, align 1\n", typ, value, pointer) + return nil + default: + return fmt.Errorf("MOVBE destination is not memory: %s", destination.String()) + } +} diff --git a/amd64_lower_movbe_test.go b/amd64_lower_movbe_test.go new file mode 100644 index 00000000..fea32c0b --- /dev/null +++ b/amd64_lower_movbe_test.go @@ -0,0 +1,199 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86MOVBECompleteFormsSource(goarch string) string { + var source strings.Builder + source.WriteString("DATA movedata+0(SB)/8, $1\n") + source.WriteString("GLOBL movedata(SB), $8\n") + source.WriteString("TEXT moveforms(SB),$0-0\n") + widths := []string{"W", "L"} + if goarch == "amd64" { + widths = append(widths, "Q") + } + for _, width := range widths { + op := "MOVBE" + width + fmt.Fprintf(&source, "\t%s 8(BX), AX\n", op) + fmt.Fprintf(&source, "\t%s AX, 16(BX)\n", op) + fmt.Fprintf(&source, "\t%s movedata(SB), CX\n", op) + fmt.Fprintf(&source, "\t%s DX, movedata(SB)\n", op) + if goarch == "amd64" { + fmt.Fprintf(&source, "\t%s 24(R11), R12\n", op) + fmt.Fprintf(&source, "\t%s R13, 32(R14)\n", op) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86MOVBECompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86MOVBECompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"moveforms": {Name: "moveforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"@llvm.bswap.i16", "@llvm.bswap.i32", `"target-features"="+movbe"`} { + if !strings.Contains(ir, want) { + t.Fatalf("MOVBE lowering omitted %q:\n%s", want, ir) + } + } + if target.goarch == "amd64" && !strings.Contains(ir, "@llvm.bswap.i64") { + t.Fatalf("MOVBEQ lowering omitted i64 byte swap:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "movbe-"+target.name+".ll", "movbe-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86MOVBERejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "MOVBEW AX, BX"}, + {goarch: "amd64", instruction: "MOVBEL 0(AX), 0(BX)"}, + {goarch: "amd64", instruction: "MOVBEQ $1, 0(BX)"}, + {goarch: "amd64", instruction: "MOVBEW AL, 0(BX)"}, + {goarch: "amd64", instruction: "MOVBEL 0(AX), X0"}, + {goarch: "amd64", instruction: "MOVBEQ AX"}, + {goarch: "amd64", instruction: "MOVBEL.Z 0(AX), BX"}, + {goarch: "386", instruction: "MOVBEQ 0(AX), BX"}, + {goarch: "386", instruction: "MOVBEL R8, 0(AX)"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's MOVBE ymovbe table", test.instruction) + } + }) + } +} + +func TestAMD64MOVBERuntimeSemanticsWidthsDirectionsAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT movesemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVL $0x7fffffff, R8 + ADDL $1, R8 + STC + + MOVW $0x3412, 0(DI) + MOVQ $0x1122334455667788, AX + MOVBEW 0(DI), AX + MOVQ AX, 8(DI) + + MOVL $0x78563412, 16(DI) + MOVBEL 16(DI), BX + MOVQ BX, 24(DI) + + MOVQ $0xefcdab8967452301, 32(DI) + MOVBEQ 32(DI), CX + MOVQ CX, 40(DI) + + MOVQ $0x1122334455667788, AX + MOVBEW AX, 48(DI) + MOVBEL AX, 50(DI) + MOVBEQ AX, 54(DI) + + SETCS 62(DI) + SETOS 63(DI) + SETEQ 64(DI) + SETMI 65(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "movesemantics": { + Name: "movesemantics", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void movesemantics(uint8_t *); +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + uint8_t out[72] = {0}; + movesemantics(out); + if (load64(out+8) != UINT64_C(0x1122334455661234)) return 10; + if (load64(out+24) != UINT64_C(0x12345678)) return 11; + if (load64(out+40) != UINT64_C(0x0123456789abcdef)) return 12; + const uint8_t stores[14] = {0x77,0x88, 0x55,0x66,0x77,0x88, 0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88}; + if (memcmp(out+48, stores, sizeof(stores)) != 0) return 13; + if (out[62] != 1 || out[63] != 1 || out[64] != 0 || out[65] != 1) return 14; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "movbe_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_move_half_test.go b/amd64_lower_move_half_test.go new file mode 100644 index 00000000..dc58f25b --- /dev/null +++ b/amd64_lower_move_half_test.go @@ -0,0 +1,77 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86MoveHalfCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + goarch string + triple string + last int + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", last: 15}, + {goarch: "386", triple: "i386-unknown-linux-gnu", last: 7}, + } { + t.Run(target.goarch, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT movehalfforms(SB),$0-0\n") + for _, op := range []string{"MOVLPS", "MOVHPS", "MOVLPD", "MOVHPD"} { + fmt.Fprintf(&source, "\t%s X1, X%d\n", op, target.last) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, target.last) + fmt.Fprintf(&source, "\t%s X%d, 16(BX)\n", op, target.last) + } + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"movehalfforms": {Name: "movehalfforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, "extractelement <2 x i64>") || !strings.Contains(ll, "insertelement <2 x i64>") { + t.Fatalf("translation omitted half-vector lane operations:\n%s", ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "move-half-"+target.goarch+".ll", "move-half-"+target.goarch+".o", ll) + }) + } +} + +func TestTranslateX86MoveHalfRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "MOVHPS Y0, X1", + "MOVLPS X0, Y1", + "MOVHPD (AX), (BX)", + "MOVLPD $1, X0", + "MOVHPS.Z X0, X1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's yxmov table", instruction) + } + }) + } +} diff --git a/amd64_lower_move_packed_float.go b/amd64_lower_move_packed_float.go new file mode 100644 index 00000000..413c4a6b --- /dev/null +++ b/amd64_lower_move_packed_float.go @@ -0,0 +1,119 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedVectorMove implements the complete Go 1.27 packed vector-move +// tables. VMOVAPD/APS/UPD/UPS share _yvmovapd, while VMOVDQA32/DQA64 and +// VMOVDQU8/DQU16/DQU32/DQU64 share _yvmovdqa32. All have bit-preserving move +// semantics; the element width only controls the granularity of an EVEX mask. +func (c *amd64Ctx) lowerPackedVectorMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + elemBits := 0 + switch baseOp { + case "VMOVAPD", "VMOVUPD": + elemBits = 64 + case "VMOVAPS", "VMOVUPS": + elemBits = 32 + case "VMOVDQA32", "VMOVDQU32": + elemBits = 32 + case "VMOVDQA64", "VMOVDQU64": + elemBits = 64 + case "VMOVDQU8": + elemBits = 8 + case "VMOVDQU16": + elemBits = 16 + default: + return false, false, nil + } + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("%s %s %s suffix is absent from its Go 1.27 packed-move encodings: %q", c.goarch, baseOp, suffix, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects source, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7 in the middle: %q", c.goarch, baseOp, ins.Raw) + } + + src := ins.Args[0] + dst := ins.Args[len(ins.Args)-1] + byteWidth := 0 + switch { + case src.Kind == OpReg: + byteWidth = amd64VectorByteWidth(src.Reg) + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(src, byteWidth) { + return true, false, fmt.Errorf("%s %s source must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + if dst.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(dst, byteWidth) { + return true, false, fmt.Errorf("%s %s register widths must match: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(dst) { + return true, false, fmt.Errorf("%s %s register source requires a matching vector or memory destination: %q", c.goarch, baseOp, ins.Raw) + } + case isAMD64MemoryOperand(src): + if dst.Kind != OpReg { + return true, false, fmt.Errorf("%s %s memory source requires a vector destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth = amd64VectorByteWidth(dst.Reg) + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(dst, byteWidth) { + return true, false, fmt.Errorf("%s %s destination must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + default: + return true, false, fmt.Errorf("%s %s source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + value, err := c.loadPackedCompareBytes(src, byteWidth) + if err != nil { + return true, false, err + } + if !masked { + return true, false, c.storeVectorBytesOperand(dst, byteWidth, value) + } + mask, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(dst, byteWidth) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / elemBits + computed := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, elemBits, value) + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, elemBits, oldBytes) + // EVEX zeroing only changes a register destination. For a masked memory + // store, inactive lanes remain untouched even though Go accepts the .Z + // spelling for this table. + result := amd64ApplyIntegerLaneMask(c, lanes, elemBits, computed, old, mask, zeroing && dst.Kind == OpReg) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, elemBits, result, byteWidth) + return true, false, c.storeVectorBytesOperand(dst, byteWidth, "%"+out) +} + +func (c *amd64Ctx) isGoPackedVectorMoveRegister(arg Operand, byteWidth int) bool { + if !amd64EVEXVectorRegister(arg, byteWidth) { + return false + } + if c.goarch == "386" && byteWidth == 64 { + index, _ := amd64VectorRegisterIndex(arg.Reg, byteWidth) + return index < 8 + } + return true +} diff --git a/amd64_lower_move_sign_extend.go b/amd64_lower_move_sign_extend.go new file mode 100644 index 00000000..e10fea48 --- /dev/null +++ b/amd64_lower_move_sign_extend.go @@ -0,0 +1,222 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedExtendMove struct { + inputBits int + outputBits int + vector bool + zeroExtend bool +} + +// lowerPackedExtendMove implements all six signed and all six unsigned legacy +// and vector widening instructions exposed by Go 1.27. Ratio-two V forms use +// _yvcvtdq2pd; ratio-four and ratio-eight forms use _yvbroadcastss. +func (c *amd64Ctx) lowerPackedExtendMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + properties, ok := amd64PackedExtendMoveProperties(baseOp) + if !ok { + return false, false, nil + } + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("%s %s %s suffix is absent from Go 1.27's widening-move encodings: %q", c.goarch, baseOp, suffix, ins.Raw) + } + if !properties.vector && suffix != "" { + return true, false, fmt.Errorf("%s %s legacy yxm_q4 form does not accept suffixes: %q", c.goarch, baseOp, ins.Raw) + } + wantArgs := 2 + if len(ins.Args) == 3 { + wantArgs = 3 + } + if len(ins.Args) != wantArgs || (!properties.vector && len(ins.Args) != 2) { + return true, false, fmt.Errorf("%s %s expects source, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7 in the middle: %q", c.goarch, baseOp, ins.Raw) + } + + src := ins.Args[0] + dst := ins.Args[len(ins.Args)-1] + if dst.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be a vector register: %q", c.goarch, baseOp, ins.Raw) + } + outputBytes := amd64VectorByteWidth(dst.Reg) + if properties.vector { + if !c.isGoPackedExtendDestination(dst, outputBytes) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's EVEX vector range: %q", c.goarch, baseOp, ins.Raw) + } + } else if outputBytes != 16 || !c.isGoLegacyPackedExtendX(dst) { + return true, false, fmt.Errorf("%s %s legacy destination must be an in-range X register: %q", c.goarch, baseOp, ins.Raw) + } + + sourceRegisterBytes := 16 + if properties.vector && outputBytes == 64 && properties.outputBits == properties.inputBits*2 { + sourceRegisterBytes = 32 + } + if src.Kind == OpReg { + if properties.vector { + if !amd64EVEXVectorRegister(src, sourceRegisterBytes) { + return true, false, fmt.Errorf("%s %s source register width does not match its Go 1.27 table: %q", c.goarch, baseOp, ins.Raw) + } + } else if !c.isGoLegacyPackedExtendX(src) { + return true, false, fmt.Errorf("%s %s legacy source must be an in-range X register or memory: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(src) { + return true, false, fmt.Errorf("%s %s source must be the table's vector register class or memory: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := outputBytes * 8 / properties.outputBits + inputs, err := c.loadPackedExtendInputs(src, sourceRegisterBytes, lanes, properties.inputBits) + if err != nil { + return true, false, err + } + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + input := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", input, lanes, properties.inputBits, inputs, lane) + extended := c.newTmp() + extension := "sext" + if properties.zeroExtend { + extension = "zext" + } + fmt.Fprintf(c.b, " %%%s = %s i%d %%%s to i%d\n", extended, extension, properties.inputBits, input, properties.outputBits) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", inserted, lanes, properties.outputBits, result, properties.outputBits, extended, lane) + result = "%" + inserted + } + if masked { + mask, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(dst, outputBytes) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(outputBytes, lanes, properties.outputBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, properties.outputBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, properties.outputBits, result, outputBytes) + return true, false, c.storeVectorBytes(dst.Reg, outputBytes, "%"+out) +} + +func amd64PackedExtendMoveProperties(op string) (amd64PackedExtendMove, bool) { + vector := strings.HasPrefix(op, "V") + properties := amd64PackedExtendMove{vector: vector, zeroExtend: strings.Contains(op, "MOVZX")} + switch op { + case "PMOVSXBW", "VPMOVSXBW", "PMOVZXBW", "VPMOVZXBW": + properties.inputBits, properties.outputBits = 8, 16 + case "PMOVSXBD", "VPMOVSXBD", "PMOVZXBD", "VPMOVZXBD": + properties.inputBits, properties.outputBits = 8, 32 + case "PMOVSXBQ", "VPMOVSXBQ", "PMOVZXBQ", "VPMOVZXBQ": + properties.inputBits, properties.outputBits = 8, 64 + case "PMOVSXWD", "VPMOVSXWD", "PMOVZXWD", "VPMOVZXWD": + properties.inputBits, properties.outputBits = 16, 32 + case "PMOVSXWQ", "VPMOVSXWQ", "PMOVZXWQ", "VPMOVZXWQ": + properties.inputBits, properties.outputBits = 16, 64 + case "PMOVSXDQ", "VPMOVSXDQ", "PMOVZXDQ", "VPMOVZXDQ": + properties.inputBits, properties.outputBits = 32, 64 + default: + return amd64PackedExtendMove{}, false + } + return properties, true +} + +func (c *amd64Ctx) isGoLegacyPackedExtendX(arg Operand) bool { + index, ok := amd64VectorRegisterIndex(arg.Reg, 16) + if !ok || index >= 16 { + return false + } + return c.goarch != "386" || index < 8 +} + +func (c *amd64Ctx) isGoPackedExtendDestination(arg Operand, outputBytes int) bool { + if outputBytes != 16 && outputBytes != 32 && outputBytes != 64 { + return false + } + if !amd64EVEXVectorRegister(arg, outputBytes) { + return false + } + if c.goarch == "386" && outputBytes == 64 { + index, _ := amd64VectorRegisterIndex(arg.Reg, outputBytes) + return index < 8 + } + return true +} + +func (c *amd64Ctx) loadPackedExtendInputs(src Operand, registerBytes, lanes, inputBits int) (string, error) { + if src.Kind == OpReg { + bytesValue, err := c.loadPackedCompareBytes(src, registerBytes) + if err != nil { + return "", err + } + fullLanes := registerBytes * 8 / inputBits + full := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i%d>\n", full, registerBytes, bytesValue, fullLanes, inputBits) + if fullLanes == lanes { + return "%" + full, nil + } + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %%%s, i32 %d\n", value, fullLanes, inputBits, full, lane) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", inserted, lanes, inputBits, result, inputBits, value, lane) + result = "%" + inserted + } + return result, nil + } + vectorType := fmt.Sprintf("<%d x i%d>", lanes, inputBits) + switch src.Kind { + case OpMem: + ptr, ptrType, err := c.ptrFromMem(src.Mem) + if err != nil { + return "", err + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, %s %s, align 1\n", loaded, vectorType, ptrType, ptr) + return "%" + loaded, nil + case OpSym: + ptr, err := c.ptrFromSB(src.Sym) + if err != nil { + return "", err + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", loaded, vectorType, ptr) + return "%" + loaded, nil + case OpFP: + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + laneOperand := src + laneOperand.FPOffset += int64(lane * inputBits / 8) + value, err := c.evalIntSized(laneOperand, amd64IntegerTypeForBits(inputBits)) + if err != nil { + return "", err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %s, i32 %d\n", inserted, vectorType, result, inputBits, value, lane) + result = "%" + inserted + } + return result, nil + default: + return "", fmt.Errorf("expected packed extension register or memory source, got %s", src.String()) + } +} diff --git a/amd64_lower_move_zero_extend_test.go b/amd64_lower_move_zero_extend_test.go new file mode 100644 index 00000000..9ea38254 --- /dev/null +++ b/amd64_lower_move_zero_extend_test.go @@ -0,0 +1,123 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedZeroExtendMoveCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast, zLast := 15, 21 + if target.goarch == "386" { + legacyLast, zLast = 7, 7 + } + var source strings.Builder + source.WriteString("TEXT packedzeroextendmoveforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PMOVZXBW", "PMOVZXBD", "PMOVZXBQ", "PMOVZXWD", "PMOVZXWQ", "PMOVZXDQ"} { + fmt.Fprintf(&source, "\t%s X0, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, legacyLast) + } + for _, op := range []string{"VPMOVZXBW", "VPMOVZXWD", "VPMOVZXDQ"} { + fmt.Fprintf(&source, "\t%s X0, X1\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), X21\n", op) + fmt.Fprintf(&source, "\t%s X20, Y21\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), Y21\n", op) + fmt.Fprintf(&source, "\t%s Y20, Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s 8(AX), Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s X20, K1, X21\n", op) + fmt.Fprintf(&source, "\t%s.Z 8(AX), K2, Y21\n", op) + fmt.Fprintf(&source, "\t%s.Z Y20, K7, Z%d\n", op, zLast) + } + for _, op := range []string{"VPMOVZXBD", "VPMOVZXBQ", "VPMOVZXWQ"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&source, "\t%s X20, %s21\n", op, width) + fmt.Fprintf(&source, "\t%s 8(AX), %s21\n", op, width) + fmt.Fprintf(&source, "\t%s.Z X20, K3, %s21\n", op, width) + } + fmt.Fprintf(&source, "\t%s X20, Z%d\n", op, zLast) + fmt.Fprintf(&source, "\t%s.Z 8(AX), K4, Z%d\n", op, zLast) + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedzeroextendmoveforms": {Name: "packedzeroextendmoveforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-zero-extend-move-"+target.name+".ll", "packed-zero-extend-move-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedZeroExtendMoveRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PMOVZXBW.Z X0, X1", + "PMOVZXBD X0", + "PMOVZXBQ M0, X1", + "PMOVZXWD Y0, X1", + "PMOVZXWQ X0, Y1", + "PMOVZXDQ X0, K1, X1", + "VPMOVZXBW Y0, Y1", + "VPMOVZXWD X0, Z1", + "VPMOVZXDQ Z0, Z1", + "VPMOVZXBD Y0, Z1", + "VPMOVZXBQ X0, K0, X1", + "VPMOVZXWQ.Z X0, X1", + "VPMOVZXBD.BCST 8(AX), X1", + "VPMOVZXWQ X0, (AX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedZeroExtendMoveRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PMOVZXBW X8, X0", + "PMOVZXDQ X0, X8", + "VPMOVZXBW Y20, Z8", + "VPMOVZXBQ X20, Z8", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedZeroExtendMoveRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedZeroExtendMoveRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed zero-extension forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_movemask.go b/amd64_lower_movemask.go new file mode 100644 index 00000000..d9d1af81 --- /dev/null +++ b/amd64_lower_movemask.go @@ -0,0 +1,155 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedMoveMask implements Go 1.27's complete packed move-mask family: +// PMOVMSKB, VPMOVMSKB, MOVMSKPS/PD, and VMOVMSKPS/PD. None of their tables +// contains EVEX, mask-register, suffix, or memory-source forms. +func (c *amd64Ctx) lowerPackedMoveMask(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + vector := false + floatingLaneBits := 0 + switch baseOp { + case "PMOVMSKB": + case "VPMOVMSKB": + vector = true + case "MOVMSKPS": + floatingLaneBits = 32 + case "MOVMSKPD": + floatingLaneBits = 64 + case "VMOVMSKPS": + vector = true + floatingLaneBits = 32 + case "VMOVMSKPD": + vector = true + floatingLaneBits = 64 + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s has no instruction suffixes in Go 1.27's optab: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects vector-or-MMX source and GP destination: %q", baseOp, ins.Raw) + } + if !isX86YrlRegisterForArch(ins.Args[1].Reg, c.goarch) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's Yrl class: %q", baseOp, ins.Raw) + } + + if floatingLaneBits != 0 { + byteWidth := 0 + if xIndex, x := amd64ParseXReg(ins.Args[0].Reg); x { + limit := 15 + if !vector && c.goarch == "386" { + limit = 7 + } + if xIndex > limit { + return true, false, fmt.Errorf("amd64 %s source is outside its Go 1.27 register class: %q", baseOp, ins.Raw) + } + byteWidth = 16 + } else if yIndex, y := amd64ParseYReg(ins.Args[0].Reg); vector && y && yIndex <= 15 { + byteWidth = 32 + } else { + return true, false, fmt.Errorf("amd64 %s source is outside its Go 1.27 table: %q", baseOp, ins.Raw) + } + value, err := c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err != nil { + return true, false, err + } + mask32 := c.floatingMoveMask(value, byteWidth, floatingLaneBits) + return true, false, c.storeRegSized(ins.Args[1].Reg, I32, mask32) + } + + var mask32 string + if xIndex, x := amd64ParseXReg(ins.Args[0].Reg); x && xIndex <= 15 { + value, err := c.loadX(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + mask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %s)\n", mask, value) + mask32 = "%" + mask + } else if yIndex, y := amd64ParseYReg(ins.Args[0].Reg); vector && y && yIndex <= 15 { + value, err := c.loadY(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <32 x i8> %s, <32 x i8> zeroinitializer, <16 x i32> %s\n", low, value, llvmI32RangeMask(0, 16)) + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <32 x i8> %s, <32 x i8> zeroinitializer, <16 x i32> %s\n", high, value, llvmI32RangeMask(16, 16)) + lowMask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %%%s)\n", lowMask, low) + highMask := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %%%s)\n", highMask, high) + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i32 %%%s, 16\n", shifted, highMask) + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i32 %%%s, %%%s\n", combined, shifted, lowMask) + mask32 = "%" + combined + } else if _, mmx := amd64ParseMReg(ins.Args[0].Reg); !vector && mmx { + value, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to <8 x i8>\n", bytes, value) + signBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt <8 x i8> %%%s, zeroinitializer\n", signBits, bytes) + mask8 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <8 x i1> %%%s to i8\n", mask8, signBits) + widened := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i32\n", widened, mask8) + mask32 = "%" + widened + } else { + return true, false, fmt.Errorf("amd64 %s source is outside its Go 1.27 table: %q", baseOp, ins.Raw) + } + + return true, false, c.storeRegSized(ins.Args[1].Reg, I32, mask32) +} + +func (c *amd64Ctx) floatingMoveMask(value string, byteWidth, laneBits int) string { + lanes := byteWidth * 8 / laneBits + integerLanes := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, value) + mask := "0" + for lane := 0; lane < lanes; lane++ { + laneValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", laneValue, lanes, laneBits, integerLanes, lane) + sign := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i%d %%%s, 0\n", sign, laneBits, laneValue) + bit := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to i32\n", bit, sign) + positioned := "%" + bit + if lane != 0 { + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i32 %%%s, %d\n", shifted, bit, lane) + positioned = "%" + shifted + } + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i32 %s, %s\n", combined, mask, positioned) + mask = "%" + combined + } + return mask +} + +func isX86YrlRegisterForArch(r Reg, goarch string) bool { + if !isAMD64YrlRegister(r) { + return false + } + if goarch != "386" { + return true + } + switch r { + case AX, BX, CX, DX, SP, BP, SI, DI: + return true + default: + return false + } +} diff --git a/amd64_lower_movhlps.go b/amd64_lower_movhlps.go new file mode 100644 index 00000000..34a82f4d --- /dev/null +++ b/amd64_lower_movhlps.go @@ -0,0 +1,74 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerMoveHighLowPackedSingle implements all forms in Go 1.27's legacy yxr +// and AVX _yvmovhlps tables for the HLPS/LHPS register-only move family. +func (c *amd64Ctx) lowerMoveHighLowPackedSingle(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + vector := false + switch baseOp { + case "MOVHLPS", "MOVLHPS": + case "VMOVHLPS", "VMOVLHPS": + vector = true + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s has no instruction suffixes in Go 1.27's optab: %q", baseOp, ins.Raw) + } + + wantOperands := 2 + if vector { + wantOperands = 3 + } + if len(ins.Args) != wantOperands { + return true, false, fmt.Errorf("amd64 %s expects %d X-register operands: %q", baseOp, wantOperands, ins.Raw) + } + for _, operand := range ins.Args { + if operand.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s is register-only in Go 1.27's optab: %q", baseOp, ins.Raw) + } + index, ok := amd64ParseXReg(operand.Reg) + if !ok || (!vector && index > 15) { + return true, false, fmt.Errorf("amd64 %s operand is outside its Go 1.27 X-register class: %q", baseOp, ins.Raw) + } + } + + first, err := c.loadXAsI64x2(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + if !vector { + destination, err := c.loadXAsI64x2(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + mask := "" + if baseOp == "MOVHLPS" { + mask = "" + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <2 x i64> %s, <2 x i64> %s, <2 x i32> %s\n", result, destination, first, mask) + return true, false, c.storeXFromI64x2(ins.Args[1].Reg, "%"+result) + } + + second, err := c.loadXAsI64x2(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + mask := "" + if baseOp == "VMOVHLPS" { + mask = "" + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <2 x i64> %s, <2 x i64> %s, <2 x i32> %s\n", result, first, second, mask) + return true, false, c.storeXFromI64x2(ins.Args[2].Reg, "%"+result) +} diff --git a/amd64_lower_movnti.go b/amd64_lower_movnti.go new file mode 100644 index 00000000..21f0c336 --- /dev/null +++ b/amd64_lower_movnti.go @@ -0,0 +1,111 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +const x86NonTemporalMetadata = ", !nontemporal !0" + +// lowerMOVNTI implements Go 1.27's complete yrl_ml row for MOVNTIL/Q. Yrl is +// a general-register source and Yml accepts ordinary, symbol, and FP memory. +// Go's compatibility closure also accepts a general-register destination; +// Intel defines only a memory destination for that ModRM encoding, so model +// the Go-accepted register form as an explicit undefined-instruction trap +// rather than silently treating it as an ordinary register move. +func (c *amd64Ctx) lowerMOVNTI(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + typ := LLVMType("") + switch baseOp { + case "MOVNTIL": + typ = I32 + case "MOVNTIQ": + if c.goarch == "386" { + return true, false, fmt.Errorf("386 MOVNTIQ is illegal in 32-bit mode: %q", ins.Raw) + } + typ = I64 + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed forms in Go 1.27's yrl_ml table: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects exactly two operands: %q", c.goarch, baseOp, ins.Raw) + } + source, destination := ins.Args[0], ins.Args[1] + if source.Kind != OpReg || !isX86YrlRegisterForArch(source.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s source must be an in-range general register: %q", c.goarch, baseOp, ins.Raw) + } + if destination.Kind == OpReg { + if !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yml compatibility closure: %q", c.goarch, baseOp, ins.Raw) + } + c.b.WriteString(" call void asm sideeffect \"ud2\", \"~{memory}\"()\n") + c.b.WriteString(" unreachable\n") + return true, true, nil + } + if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s %s destination must be Yml memory or a Go-compatible general register: %q", c.goarch, baseOp, ins.Raw) + } + if destination.Kind == OpMem && !x86MemoryRegistersValidForArch(destination.Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s destination uses an out-of-range address register: %q", c.goarch, baseOp, ins.Raw) + } + value, err := c.evalIntSized(source, typ) + if err != nil { + return true, false, err + } + return true, false, c.storeMOVNTIMemory(destination, typ, value) +} + +func x86MemoryRegistersValidForArch(memory MemRef, goarch string) bool { + for _, register := range []Reg{memory.Base, memory.Index} { + if register != "" && !isX86YrlRegisterForArch(register, goarch) { + return false + } + } + return true +} + +func (c *amd64Ctx) storeMOVNTIMemory(destination Operand, typ LLVMType, value string) error { + switch destination.Kind { + case OpMem: + pointer, pointerType, err := c.ptrFromMem(destination.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, %s %s, align 1%s\n", typ, value, pointerType, pointer, x86NonTemporalMetadata) + return nil + case OpFP: + return c.storeFPResultWithMetadata(destination.FPOffset, typ, value, x86NonTemporalMetadata) + case OpSym: + pointer, err := c.ptrFromSB(destination.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, ptr %s, align 1%s\n", typ, value, pointer, x86NonTemporalMetadata) + return nil + default: + return fmt.Errorf("MOVNTI destination is not memory: %s", destination.String()) + } +} + +func fileUsesX86NonTemporalMetadata(file *File) bool { + if file == nil || file.Arch != ArchAMD64 { + return false + } + for _, function := range file.Funcs { + for _, instruction := range function.Instrs { + op := strings.ToUpper(string(instruction.Op)) + switch op { + case "MOVNTIL", "MOVNTIQ", "MOVNTQ", "MOVNTDQ", "MOVNTO", "MOVNTPD", "MOVNTPS", "VMOVNTDQ", "VMOVNTPD", "VMOVNTPS": + return true + } + } + } + return false +} diff --git a/amd64_lower_movnti_test.go b/amd64_lower_movnti_test.go new file mode 100644 index 00000000..d162f74e --- /dev/null +++ b/amd64_lower_movnti_test.go @@ -0,0 +1,217 @@ +package plan9asm + +import ( + "fmt" + "os/exec" + "runtime" + "strings" + "testing" +) + +func x86MOVNTICompleteFormsSource(goarch string) (string, map[string]FuncSig) { + var source strings.Builder + source.WriteString("DATA movntidata+0(SB)/8, $1\n") + source.WriteString("GLOBL movntidata(SB), $8\n") + source.WriteString("TEXT movntiforms(SB),$0-0\n") + source.WriteString("\tMOVNTIL AX, 8(BX)\n") + source.WriteString("\tMOVNTIL CX, movntidata(SB)\n") + if goarch == "amd64" { + source.WriteString("\tMOVNTIL R11, 16(R12)\n") + source.WriteString("\tMOVNTIQ AX, 24(BX)\n") + source.WriteString("\tMOVNTIQ CX, movntidata(SB)\n") + source.WriteString("\tMOVNTIQ R13, 32(R14)\n") + } + source.WriteString("\tRET\n") + + source.WriteString("TEXT movntiframe(SB),$0-4\n") + source.WriteString("\tMOVNTIL AX, ret+0(FP)\n") + source.WriteString("\tRET\n") + if goarch == "amd64" { + source.WriteString("TEXT movntiframeq(SB),$0-8\n") + source.WriteString("\tMOVNTIQ AX, ret+0(FP)\n") + source.WriteString("\tRET\n") + } + + // Yml's Go compatibility closure includes registers even though the ISA + // defines only memory destinations for MOVNTI. Keep this Go-accepted source + // form visible and require the translated function to trap explicitly. + source.WriteString("TEXT movntiregtrap(SB),$0-0\n") + source.WriteString("\tMOVNTIL AX, BX\n") + source.WriteString("\tRET\n") + + sigs := map[string]FuncSig{ + "movntiforms": {Name: "movntiforms", Ret: Void}, + "movntiframe": {Name: "movntiframe", Ret: I32, Frame: FrameLayout{Results: []FrameSlot{{Offset: 0, Type: I32, Index: 0, Field: -1}}}}, + "movntiregtrap": {Name: "movntiregtrap", Ret: Void}, + } + if goarch == "amd64" { + sigs["movntiframeq"] = FuncSig{Name: "movntiframeq", Ret: I64, Frame: FrameLayout{Results: []FrameSlot{{Offset: 0, Type: I64, Index: 0, Field: -1}}}} + } + return source.String(), sigs +} + +func TestTranslateX86MOVNTICompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source, sigs := x86MOVNTICompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: target.goarch, TargetTriple: target.triple, Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`store i32`, `!nontemporal !0`, `!0 = !{i32 1}`, `"target-features"="+sse2"`, `asm sideeffect "ud2"`, "unreachable"} { + if !strings.Contains(ir, want) { + t.Fatalf("MOVNTI lowering omitted %q:\n%s", want, ir) + } + } + if target.goarch == "amd64" && !strings.Contains(ir, "store i64") { + t.Fatalf("MOVNTIQ lowering omitted i64 store:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "movnti-"+target.name+".ll", "movnti-"+target.name+".o", ir) + command := exec.Command(llc, "-mtriple="+target.triple, "-filetype=asm", "-o=-", "-") + command.Stdin = strings.NewReader(ir) + assembly, err := command.CombinedOutput() + if err != nil { + t.Fatalf("llc MOVNTI assembly failed: %v\n%s", err, assembly) + } + if !strings.Contains(strings.ToLower(string(assembly)), "movnti") { + t.Fatalf("LLVM 22 did not preserve the non-temporal integer store:\n%s", assembly) + } + }) + } +} + +func TestTranslateX86MOVNTIRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "MOVNTIL 0(AX), BX"}, + {goarch: "amd64", instruction: "MOVNTIL 0(AX), 8(BX)"}, + {goarch: "amd64", instruction: "MOVNTIL $1, 8(BX)"}, + {goarch: "amd64", instruction: "MOVNTIL X0, 8(BX)"}, + {goarch: "amd64", instruction: "MOVNTIL AX"}, + {goarch: "amd64", instruction: "MOVNTIL AX, 0(BX), CX"}, + {goarch: "amd64", instruction: "MOVNTIL.Z AX, 8(BX)"}, + {goarch: "386", instruction: "MOVNTIQ AX, 8(BX)"}, + {goarch: "386", instruction: "MOVNTIL R8, 8(BX)"}, + {goarch: "386", instruction: "MOVNTIL AX, 8(R9)"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's MOVNTI yrl_ml table", test.instruction) + } + }) + } +} + +func TestAMD64MOVNTIRuntimeSemanticsAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT movntisemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVL $0x7fffffff, R8 + ADDL $1, R8 + STC + MOVQ $0x1122334455667788, AX + MOVQ $0x8877665544332211, BX + MOVNTIL AX, 0(DI) + MOVNTIQ BX, 8(DI) + SFENCE + SETCS 16(DI) + SETOS 17(DI) + SETEQ 18(DI) + SETMI 19(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "movntisemantics": { + Name: "movntisemantics", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void movntisemantics(uint8_t *); +static uint64_t load64(const uint8_t *p) { + uint64_t value; + memcpy(&value, p, sizeof(value)); + return value; +} +int main(void) { + uint8_t out[24] = {0}; + movntisemantics(out); + if (load64(out) != UINT64_C(0x0000000055667788)) return 10; + if (load64(out+8) != UINT64_C(0x8877665544332211)) return 11; + if (out[16] != 1 || out[17] != 1 || out[18] != 0 || out[19] != 1) return 12; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "movnti_semantics", triple, ir, mainC, runPrefix) +} + +func TestX86MOVNTIGoAssemblerCompatibilityClosure(t *testing.T) { + for _, goarch := range []string{"amd64", "386"} { + for _, instruction := range []string{"MOVNTIL AX, 8(BX)", "MOVNTIL AX, BX", "MOVNTIL AX, ret+0(FP)"} { + t.Run(fmt.Sprintf("%s/%s", goarch, strings.NewReplacer(" ", "_", ",", "").Replace(instruction)), func(t *testing.T) { + requireX86GoAssemblerResult(t, goarch, "TEXT compat(SB),$0-8\n\t"+instruction+"\n\tRET\n", true) + }) + } + } +} diff --git a/amd64_lower_mpsadbw_test.go b/amd64_lower_mpsadbw_test.go new file mode 100644 index 00000000..04cd064e --- /dev/null +++ b/amd64_lower_mpsadbw_test.go @@ -0,0 +1,379 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64PackedSADGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64PackedSADSpec{ + "PSADBW": {kind: amd64PackedSADBlockSum, form: amd64PackedSADLegacyX}, + "VPSADBW": {kind: amd64PackedSADBlockSum, form: amd64PackedSADEVEXXYZ}, + "MPSADBW": {kind: amd64PackedSADMultiple, form: amd64PackedSADLegacyX}, + "VMPSADBW": {kind: amd64PackedSADMultiple, form: amd64PackedSADVEXXY}, + "VDBPSADBW": {kind: amd64PackedSADDoubleBlock, form: amd64PackedSADEVEXXYZ}, + } + if len(amd64PackedSADSpecs) != len(expected) { + t.Fatalf("packed SAD grammar has %d entries, want %d", len(amd64PackedSADSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64PackedSADSpecs[op]; !ok { + t.Errorf("packed SAD grammar omitted %s", op) + } else if got != want { + t.Errorf("packed SAD grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86MultipleSADCompleteFormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 15 + if target.goarch == "386" { + last = 7 + } + var source strings.Builder + source.WriteString("TEXT mpsadforms(SB),$0-0\n") + fmt.Fprintf(&source, "\tMPSADBW $7, X0, X%d\n", last) + fmt.Fprintf(&source, "\tMPSADBW $7, 0(AX), X%d\n", last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\tVMPSADBW $7, X0, X1, X%d\n", last) + fmt.Fprintf(&source, "\tVMPSADBW $7, 16(AX), X1, X%d\n", last) + fmt.Fprintf(&source, "\tVMPSADBW $7, Y0, Y1, Y%d\n", last) + fmt.Fprintf(&source, "\tVMPSADBW $7, 32(AX), Y1, Y%d\n", last) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"mpsadforms": {Name: "mpsadforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "call <8 x i16> @llvm.x86.sse41.mpsadbw") { + t.Fatalf("MPSADBW lowering omitted the SSE4.1 intrinsic:\n%s", ir) + } + if target.goarch == "amd64" && !strings.Contains(ir, "call <16 x i16> @llvm.x86.avx2.mpsadbw") { + t.Fatalf("VMPSADBW Y lowering omitted the AVX2 intrinsic:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "mpsadbw-"+target.name+".ll", "mpsadbw-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86DoubleSADCompleteFormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 23 + var source strings.Builder + source.WriteString("TEXT dbpsadforms(SB),$0-0\n") + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&source, "\tVDBPSADBW $0, %s0, %s1, %s%d\n", width, width, width, last) + fmt.Fprintf(&source, "\tVDBPSADBW $85, 0(AX), %s1, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVDBPSADBW $170, %s2, %s1, K1, %s%d\n", width, width, width, last) + fmt.Fprintf(&source, "\tVDBPSADBW.Z $255, 64(AX), %s1, K2, %s%d\n", width, width, last) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"dbpsadforms": {Name: "dbpsadforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "dbpsadbw-"+target.name+".ll", "dbpsadbw-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86DoubleSADRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VDBPSADBW $-1, X0, X1, X2"}, + {goarch: "amd64", instruction: "VDBPSADBW $256, X0, X1, X2"}, + {goarch: "amd64", instruction: "VDBPSADBW.Z $1, X0, X1, X2"}, + {goarch: "amd64", instruction: "VDBPSADBW.BCST $1, 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VDBPSADBW $1, X0, Y1, Y2"}, + {goarch: "amd64", instruction: "VDBPSADBW $1, X0, X1, K0, X2"}, + {goarch: "amd64", instruction: "VDBPSADBW $1, X0, X1, K1, X2, X3"}, + {goarch: "386", instruction: "VDBPSADBW $1, X0, X1, X2"}, + {goarch: "386", instruction: "VDBPSADBW.Z $1, X0, X1, K1, X2"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VDBPSADBW table", test.instruction) + } + }) + } +} + +func TestTranslateX86MultipleSADRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "MPSADBW $-1, X0, X1"}, + {goarch: "amd64", instruction: "MPSADBW $256, X0, X1"}, + {goarch: "amd64", instruction: "MPSADBW.Z $1, X0, X1"}, + {goarch: "amd64", instruction: "MPSADBW $1, Y0, Y1"}, + {goarch: "amd64", instruction: "VMPSADBW $1, Z0, Z1, Z2"}, + {goarch: "amd64", instruction: "VMPSADBW $1, X0, Y1, Y2"}, + {goarch: "386", instruction: "MPSADBW $1, X0, X8"}, + {goarch: "386", instruction: "VMPSADBW $1, X0, X1, X2"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{Goarch: test.goarch, TargetTriple: triple, Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside the Go table for %s", test.instruction, test.goarch) + } + }) + } +} + +func TestTranslateX86PackedSADRejects386OutOfRangeForms(t *testing.T) { + for _, instruction := range []string{ + "PSADBW X0, X8", + "PSADBW 8(R9), X0", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "386", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + Goarch: "386", + TargetTriple: "i386-unknown-linux-gnu", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside the Go 386 SAD tables", instruction) + } + }) + } +} + +func TestAMD64MultipleSADRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT mpsadsemantics(SB),$0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), CX + MOVQ b+16(FP), DX + MOVUPS 0(CX), X1 + MOVUPS 0(DX), X0 + STC + MPSADBW $0, X0, X1 + MOVUPS X1, 0(AX) + SETCS 16(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{"mpsadsemantics": { + Name: "mpsadsemantics", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void mpsadsemantics(uint8_t *, const uint8_t *, const uint8_t *); +int main(void) { + uint8_t out[17] = {0}; + const uint8_t a[16] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; + const uint8_t b[16] = {0}; + const uint16_t want[8] = {6, 10, 14, 18, 22, 26, 30, 34}; + uint16_t got[8]; + mpsadsemantics(out, a, b); + memcpy(got, out, 16); + for (int i = 0; i < 8; i++) if (got[i] != want[i]) return 10 + i; + if (out[16] != 1) return 20; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "multiple_sad_semantics", triple, ir, mainC, runPrefix) +} + +func TestAMD64DoubleSADRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT dbpsadsemantics(SB),$0-40 + MOVQ out+0(FP), AX + MOVQ a+8(FP), CX + MOVQ b+16(FP), DX + MOVQ old+24(FP), R8 + MOVQ mask+32(FP), R9 + KMOVQ R9, K1 + VMOVDQU8 0(CX), Z1 + VMOVDQU8 0(DX), Z0 + VMOVDQU16 0(R8), Z2 + STC + VDBPSADBW $27, Z0, Z1, K1, Z2 + VMOVDQU16 Z2, 0(AX) + VDBPSADBW.Z $228, Z0, Z1, K1, Z3 + VMOVDQU16 Z3, 64(AX) + SETCS 128(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"dbpsadsemantics": { + Name: "dbpsadsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: I64, Index: 4, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void dbpsadsemantics(uint8_t *, const uint8_t *, const uint8_t *, const uint16_t *, uint64_t); +static void oracle(uint16_t *out, const uint8_t *src1, const uint8_t *src2, const uint16_t *old, unsigned imm, uint64_t mask, int zeroing) { + uint8_t shuffled[64]; + for (int lane = 0; lane < 64; lane += 16) + for (int dword = 0; dword < 4; dword++) + for (int byte = 0; byte < 4; byte++) + shuffled[lane + dword * 4 + byte] = src2[lane + ((imm >> (2 * dword)) & 3) * 4 + byte]; + for (int block = 0; block < 64; block += 8) { + for (int word = 0; word < 4; word++) { + unsigned sum = 0; + int src1_base = block + (word >= 2 ? 4 : 0); + int shuffled_base = block + word; + for (int byte = 0; byte < 4; byte++) { + int difference = (int)src1[src1_base + byte] - (int)shuffled[shuffled_base + byte]; + sum += difference < 0 ? -difference : difference; + } + int index = block / 2 + word; + out[index] = (mask >> index) & 1 ? (uint16_t)sum : (zeroing ? 0 : old[index]); + } + } +} +int main(void) { + uint8_t a[64], b[64], bytes[129] = {0}; uint16_t old[32], got[64], want[64]; + for (int i = 0; i < 64; i++) { a[i] = (uint8_t)(i * 7 + 3); b[i] = (uint8_t)(255 - i * 5); } + for (int i = 0; i < 32; i++) old[i] = (uint16_t)(1000 + i); + uint64_t mask = UINT64_C(0xa55aa55a); + dbpsadsemantics(bytes, a, b, old, mask); + memcpy(got, bytes, 128); + oracle(want, a, b, old, 27, mask, 0); + oracle(want + 32, a, b, old, 228, mask, 1); + for (int i = 0; i < 64; i++) if (got[i] != want[i]) return 10 + i; + if (bytes[128] != 1) return 80; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "double_sad_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_msr.go b/amd64_lower_msr.go new file mode 100644 index 00000000..d19eaa06 --- /dev/null +++ b/amd64_lower_msr.go @@ -0,0 +1,60 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerMSRAccess implements the complete RDMSR/WRMSR instruction family. +// Go 1.27 uses the operand-free ynone optab entry for both instructions on +// amd64 and 386; the architectural operands are ECX and EDX:EAX. +func (c *amd64Ctx) lowerMSRAccess(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + switch baseOp { + case "RDMSR", "WRMSR": + // handled below + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, baseOp, ins.Raw) + } + + cx, err := c.loadReg(CX) + if err != nil { + return true, false, err + } + cx32 := c.truncI64(cx, I32) + if baseOp == "RDMSR" { + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call { i32, i32 } asm sideeffect \"rdmsr\", \"={ax},={dx},{cx},~{dirflag},~{fpsr},~{flags}\"(i32 %s)\n", call, cx32) + for index, reg := range []Reg{AX, DX} { + part := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue { i32, i32 } %%%s, %d\n", part, call, index) + if err := c.storeRegSized(reg, I32, "%"+part); err != nil { + return true, false, err + } + } + return true, false, nil + } + + ax, err := c.loadReg(AX) + if err != nil { + return true, false, err + } + dx, err := c.loadReg(DX) + if err != nil { + return true, false, err + } + ax32 := c.truncI64(ax, I32) + dx32 := c.truncI64(dx, I32) + fmt.Fprintf(c.b, " call void asm sideeffect \"wrmsr\", \"{ax},{dx},{cx},~{dirflag},~{fpsr},~{flags}\"(i32 %s, i32 %s, i32 %s)\n", ax32, dx32, cx32) + return true, false, nil +} diff --git a/amd64_lower_mul_dword_qword.go b/amd64_lower_mul_dword_qword.go new file mode 100644 index 00000000..ab155d93 --- /dev/null +++ b/amd64_lower_mul_dword_qword.go @@ -0,0 +1,231 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerDwordToQwordMultiply implements PMULDQ, PMULULQ, VPMULDQ, and +// VPMULUDQ across their complete Go 1.27 yxm_q4/ymm/_yvandnpd forms. +func (c *amd64Ctx) lowerDwordToQwordMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + signed := false + vector := false + switch baseOp { + case "PMULDQ": + signed = true + case "PMULULQ": + case "VPMULDQ": + signed, vector = true, true + case "VPMULUDQ": + vector = true + default: + return false, false, nil + } + + broadcast, zeroing := false, false + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + for i, suffix := range strings.Split(rawOp[dot+1:], ".") { + switch suffix { + case "BCST": + if !vector || broadcast || zeroing { + return true, false, fmt.Errorf("amd64 %s has invalid .BCST suffix: %q", baseOp, ins.Raw) + } + broadcast = true + case "Z": + if !vector || zeroing || i != len(strings.Split(rawOp[dot+1:], "."))-1 { + return true, false, fmt.Errorf("amd64 %s has invalid .Z suffix: %q", baseOp, ins.Raw) + } + zeroing = true + default: + return true, false, fmt.Errorf("amd64 %s has unsupported suffix .%s: %q", baseOp, suffix, ins.Raw) + } + } + } + if !vector { + return c.lowerLegacyDwordToQwordMultiply(baseOp, signed, ins) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 %s expects source, source, [K mask,] destination: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z requires K1-K7: %q", baseOp, ins.Raw) + } + if broadcast && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s .BCST requires a memory first source: %q", baseOp, ins.Raw) + } + dst := ins.Args[len(ins.Args)-1] + if dst.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects a vector destination: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dst.Reg) + if byteWidth == 0 { + return true, false, fmt.Errorf("amd64 %s expects an X, Y, or Z destination: %q", baseOp, ins.Raw) + } + if ins.Args[1].Kind != OpReg || amd64VectorByteWidth(ins.Args[1].Reg) != byteWidth { + return true, false, fmt.Errorf("amd64 %s second source must match destination width: %q", baseOp, ins.Raw) + } + if !broadcast && ins.Args[0].Kind == OpReg && amd64VectorByteWidth(ins.Args[0].Reg) != byteWidth { + return true, false, fmt.Errorf("amd64 %s first source must match destination width: %q", baseOp, ins.Raw) + } + if !broadcast && ins.Args[0].Kind != OpReg && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s first source must be vector or memory: %q", baseOp, ins.Raw) + } + + lhs, err := c.loadDwordMultiplyEvenLanes(ins.Args[0], byteWidth, broadcast) + if err != nil { + return true, false, err + } + rhs, err := c.loadDwordMultiplyEvenLanes(ins.Args[1], byteWidth, false) + if err != nil { + return true, false, err + } + qwordLanes := byteWidth / 8 + lhs = c.extendDwordMultiplyLanes(lhs, qwordLanes, signed) + rhs = c.extendDwordMultiplyLanes(rhs, qwordLanes, signed) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul <%d x i64> %s, %s\n", product, qwordLanes, lhs, rhs) + result := "%" + product + + if masked { + maskArg := ins.Args[2] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, ok := amd64ParseKReg(maskArg.Reg) + if !ok || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err := c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(dst, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, qwordLanes, 64, oldBytes) + result = amd64ApplyIntegerLaneMask(c, qwordLanes, 64, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", out, qwordLanes, result, byteWidth) + return true, false, c.storeVectorBytes(dst.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) lowerLegacyDwordToQwordMultiply(op string, signed bool, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects source and X/MMX destination: %q", op, ins.Raw) + } + dst := ins.Args[1] + if isAMD64XReg(dst.Reg) { + if ins.Args[0].Kind == OpReg && !isAMD64XReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("amd64 %s X form requires X-or-memory source: %q", op, ins.Raw) + } + if !isAMD64XRegOperand(ins.Args[0]) && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s X form requires X-or-memory source: %q", op, ins.Raw) + } + lhs, err := c.loadDwordMultiplyEvenLanes(ins.Args[0], 16, false) + if err != nil { + return true, false, err + } + rhs, err := c.loadDwordMultiplyEvenLanes(dst, 16, false) + if err != nil { + return true, false, err + } + lhs = c.extendDwordMultiplyLanes(lhs, 2, signed) + rhs = c.extendDwordMultiplyLanes(rhs, 2, signed) + product := c.newTmp() + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul <2 x i64> %s, %s\n", product, lhs, rhs) + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", out, product) + return true, false, c.storeX(dst.Reg, "%"+out) + } + if _, ok := amd64ParseMReg(dst.Reg); !ok || op != "PMULULQ" { + return true, false, fmt.Errorf("amd64 %s destination is outside its Go 1.27 table: %q", op, ins.Raw) + } + if c.goarch == "386" { + return true, false, fmt.Errorf("386 PMULULQ MMX form is illegal in 32-bit mode: %q", ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if _, ok := amd64ParseMReg(ins.Args[0].Reg); !ok { + return true, false, fmt.Errorf("amd64 PMULULQ MMX form requires MMX-or-memory source: %q", ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 PMULULQ MMX form requires MMX-or-memory source: %q", ins.Raw) + } + source, err := c.evalIntSized(ins.Args[0], I64) + if err != nil { + return true, false, err + } + destination, err := c.evalIntSized(dst, I64) + if err != nil { + return true, false, err + } + sourceLow := c.lowDwordFromI64(source) + destinationLow := c.lowDwordFromI64(destination) + sourceWide := c.extendDwordScalar(sourceLow, false) + destinationWide := c.extendDwordScalar(destinationLow, false) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i64 %s, %s\n", product, sourceWide, destinationWide) + return true, false, c.storeReg(dst.Reg, "%"+product) +} + +func isAMD64XRegOperand(op Operand) bool { + return op.Kind == OpReg && isAMD64XReg(op.Reg) +} + +func (c *amd64Ctx) loadDwordMultiplyEvenLanes(op Operand, byteWidth int, broadcast bool) (string, error) { + qwordLanes := byteWidth / 8 + if broadcast { + value, err := c.evalIntSized(op, I64) + if err != nil { + return "", err + } + low := c.lowDwordFromI64(value) + return amd64SplatInteger(c, qwordLanes, 32, low), nil + } + bytesValue, err := c.loadPackedCompareBytes(op, byteWidth) + if err != nil { + return "", err + } + dwordLanes := byteWidth / 4 + all := c.bitcastVectorBytesToIntegerLanes(byteWidth, dwordLanes, 32, bytesValue) + mask := make([]string, qwordLanes) + for i := range mask { + mask[i] = fmt.Sprintf("i32 %d", i*2) + } + even := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i32> %s, <%d x i32> zeroinitializer, <%d x i32> <%s>\n", even, dwordLanes, all, dwordLanes, qwordLanes, strings.Join(mask, ", ")) + return "%" + even, nil +} + +func (c *amd64Ctx) extendDwordMultiplyLanes(value string, lanes int, signed bool) string { + extended := c.newTmp() + op := "zext" + if signed { + op = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s <%d x i32> %s to <%d x i64>\n", extended, op, lanes, value, lanes) + return "%" + extended +} + +func (c *amd64Ctx) lowDwordFromI64(value string) string { + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", low, value) + return "%" + low +} + +func (c *amd64Ctx) extendDwordScalar(value string, signed bool) string { + extended := c.newTmp() + op := "zext" + if signed { + op = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s i32 %s to i64\n", extended, op, value) + return "%" + extended +} diff --git a/amd64_lower_mul_qword.go b/amd64_lower_mul_qword.go new file mode 100644 index 00000000..02e1ac09 --- /dev/null +++ b/amd64_lower_mul_qword.go @@ -0,0 +1,97 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedQwordMultiply implements every Go 1.27 VPMULLQ form from the +// shared _yvblendmpd table, including scalar broadcast and EVEX masking. +func (c *amd64Ctx) lowerPackedQwordMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + if baseOp != "VPMULLQ" { + return false, false, nil + } + suffixes, err := amd64ParseTwoSourcePermuteSuffixes(rawOp, baseOp) + if err != nil { + return true, false, fmt.Errorf("%w: %q", err, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 VPMULLQ expects first source, second source, [K mask,] destination: %q", ins.Raw) + } + masked := len(ins.Args) == 4 + if masked && c.goarch == "386" { + return true, false, fmt.Errorf("386 VPMULLQ masked form exceeds the Go assembler frontend's operand limit: %q", ins.Raw) + } + if suffixes.zeroing && !masked { + return true, false, fmt.Errorf("amd64 VPMULLQ .Z requires a K1-K7 mask: %q", ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + byteWidth := 0 + if destination.Kind == OpReg { + byteWidth = amd64VectorByteWidth(destination.Reg) + } + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 VPMULLQ expects an in-range X, Y, or Z destination: %q", ins.Raw) + } + second := ins.Args[1] + if !c.isGoPackedVectorMoveRegister(second, byteWidth) { + return true, false, fmt.Errorf("amd64 VPMULLQ second source must match the destination width: %q", ins.Raw) + } + first := ins.Args[0] + if first.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(first, byteWidth) { + return true, false, fmt.Errorf("amd64 VPMULLQ first source register must match the destination width: %q", ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 VPMULLQ first source must be a matching vector register or memory: %q", ins.Raw) + } + if suffixes.broadcast && !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 VPMULLQ.BCST requires a memory first source: %q", ins.Raw) + } + + mask := "" + if masked { + maskArg := ins.Args[2] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 VPMULLQ masked form expects K1-K7: %q", ins.Raw) + } + maskIndex, validMask := amd64ParseKReg(maskArg.Reg) + if !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 VPMULLQ masked form expects K1-K7: %q", ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + lanes := byteWidth / 8 + firstValue, err := c.loadPackedCompareLanes(first, byteWidth, 64, suffixes.broadcast) + if err != nil { + return true, false, err + } + secondValue, err := c.loadPackedCompareLanes(second, byteWidth, 64, false) + if err != nil { + return true, false, err + } + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul <%d x i64> %s, %s\n", product, lanes, secondValue, firstValue) + result := "%" + product + if masked { + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 64, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, 64, result, old, mask, suffixes.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", out, lanes, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} diff --git a/amd64_lower_mul_qword_test.go b/amd64_lower_mul_qword_test.go new file mode 100644 index 00000000..0fa1fe8c --- /dev/null +++ b/amd64_lower_mul_qword_test.go @@ -0,0 +1,94 @@ +package plan9asm + +import ( + "fmt" + "testing" +) + +func TestTranslateX86PackedQwordMultiplyCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastZ := 20 + if target.goarch == "386" { + lastZ = 7 + } + source := fmt.Sprintf(` +TEXT packedqwordmultiplyforms(SB),NOSPLIT,$0-0 + VPMULLQ X1, X20, X21 + VPMULLQ 8(AX), Y20, Y21 + VPMULLQ Z1, Z2, Z%d + VPMULLQ.BCST 40(AX), X20, X21 + VPMULLQ.BCST 48(AX), Y20, Y21 + VPMULLQ.BCST 56(AX), Z2, Z%d +`, lastZ, lastZ) + if target.goarch == "amd64" { + source += ` + VPMULLQ X1, X20, K1, X21 + VPMULLQ.Z Y1, Y20, K2, Y21 + VPMULLQ.BCST.Z 104(AX), Z20, K3, Z21 +` + } + source += "\tRET\n" + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"packedqwordmultiplyforms": {Name: "packedqwordmultiplyforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-qword-multiply-"+target.name+".ll", "packed-qword-multiply-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedQwordMultiplyRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPMULLQ X0, X1", + "VPMULLQ X0, Y1, Y2", + "VPMULLQ X0, (AX), X2", + "VPMULLQ X0, X1, K0, X2", + "VPMULLQ X0, X1, AX", + "VPMULLQ.Z X0, X1, X2", + "VPMULLQ.BCST X0, X1, X2", + "VPMULLQ.Z.BCST (AX), X1, K1, X2", + "VPMULLQ.RN_SAE X0, X1, X2", + } { + assertX86PackedQwordMultiplyRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + } + assertX86PackedQwordMultiplyRejected(t, "386", "i386-unknown-linux-gnu", "VPMULLQ X0, X1, K1, X2") + assertX86PackedQwordMultiplyRejected(t, "386", "i386-unknown-linux-gnu", "VPMULLQ Z0, Z1, Z8") +} + +func assertX86PackedQwordMultiplyRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VPMULLQ forms", instruction) + } +} diff --git a/amd64_lower_muldiv_scalar.go b/amd64_lower_muldiv_scalar.go new file mode 100644 index 00000000..d354e7e0 --- /dev/null +++ b/amd64_lower_muldiv_scalar.go @@ -0,0 +1,350 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerScalarMultiplyDivide implements the complete scalar x86 multiply and +// divide families described by Go 1.27's ydivb, ydivl, yimul, and yimul3 +// tables. The one-operand forms use the architectural accumulator pairs; +// IMULW/L/Q also have the table's explicit two- and three-operand forms. +func (c *amd64Ctx) lowerScalarMultiplyDivide(op Op, ins Instr) (ok bool, terminated bool, err error) { + name := strings.ToUpper(string(op)) + stem, bits, threeOperandName, recognized := x86ScalarMultiplyDivideProperties(name) + if !recognized { + return false, false, nil + } + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", name, ins.Raw) + } + + if threeOperandName { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects immediate, source, destination register: %q", c.goarch, name, ins.Raw) + } + if err := validateX86ExplicitIMUL(c.goarch, name, bits, ins, true); err != nil { + return true, false, err + } + return true, false, c.emitX86ExplicitIMUL(bits, ins.Args[0], ins.Args[1], ins.Args[2]) + } + + if stem == "IMUL" && bits != 8 && len(ins.Args) != 1 { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects one or two operands: %q", c.goarch, name, ins.Raw) + } + if err := validateX86ExplicitIMUL(c.goarch, name, bits, ins, false); err != nil { + return true, false, err + } + return true, false, c.emitX86ExplicitIMUL(bits, Operand{}, ins.Args[0], ins.Args[1]) + } + + if len(ins.Args) != 1 { + return true, false, fmt.Errorf("%s %s expects one GP-or-memory source: %q", c.goarch, name, ins.Raw) + } + if !isX86ScalarMultiplyDivideSource(ins.Args[0], bits, c.goarch) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's %s class: %q", c.goarch, name, x86ScalarMultiplyDivideSourceClass(bits), ins.Raw) + } + + switch stem { + case "MUL": + return true, false, c.emitX86ImplicitMultiply(bits, false, ins.Args[0]) + case "IMUL": + return true, false, c.emitX86ImplicitMultiply(bits, true, ins.Args[0]) + case "DIV": + return true, false, c.emitX86ImplicitDivide(bits, false, ins.Args[0]) + case "IDIV": + return true, false, c.emitX86ImplicitDivide(bits, true, ins.Args[0]) + default: + panic("unreachable scalar multiply/divide stem") + } +} + +func x86ScalarMultiplyDivideProperties(op string) (stem string, bits int, threeOperandName bool, ok bool) { + switch op { + case "MULB": + return "MUL", 8, false, true + case "MULW": + return "MUL", 16, false, true + case "MULL": + return "MUL", 32, false, true + case "MULQ": + return "MUL", 64, false, true + case "IMULB": + return "IMUL", 8, false, true + case "IMULW": + return "IMUL", 16, false, true + case "IMULL": + return "IMUL", 32, false, true + case "IMULQ": + return "IMUL", 64, false, true + case "IMUL3W": + return "IMUL", 16, true, true + case "IMUL3L": + return "IMUL", 32, true, true + case "IMUL3Q": + return "IMUL", 64, true, true + case "DIVB": + return "DIV", 8, false, true + case "DIVW": + return "DIV", 16, false, true + case "DIVL": + return "DIV", 32, false, true + case "DIVQ": + return "DIV", 64, false, true + case "IDIVB": + return "IDIV", 8, false, true + case "IDIVW": + return "IDIV", 16, false, true + case "IDIVL": + return "IDIV", 32, false, true + case "IDIVQ": + return "IDIV", 64, false, true + default: + return "", 0, false, false + } +} + +func x86ScalarMultiplyDivideSourceClass(bits int) string { + if bits == 8 { + return "Ymb" + } + return "Yml" +} + +func isX86ScalarMultiplyDivideSource(operand Operand, bits int, goarch string) bool { + if operand.Kind == OpReg { + if bits == 8 { + return isGoYmbRegisterForArch(operand.Reg, goarch) + } + return isX86YrlRegisterForArch(operand.Reg, goarch) + } + if operand.Kind == OpSym && strings.HasPrefix(strings.TrimSpace(operand.Sym), "$") { + return false + } + return isAMD64MemoryOperand(operand) +} + +func validateX86ExplicitIMUL(goarch, op string, bits int, ins Instr, threeOperands bool) error { + immediate := Operand{} + source := ins.Args[0] + destination := ins.Args[1] + if threeOperands { + immediate = ins.Args[0] + source = ins.Args[1] + destination = ins.Args[2] + } + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, goarch) { + return fmt.Errorf("%s %s destination is outside Go 1.27's Yrl class: %q", goarch, op, ins.Raw) + } + if threeOperands { + if !isX86IMULImmediate(immediate, goarch) { + return fmt.Errorf("%s %s immediate is outside Go 1.27's Yi8/Yi32 classes: %q", goarch, op, ins.Raw) + } + if !isX86ScalarMultiplyDivideSource(source, bits, goarch) { + return fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", goarch, op, ins.Raw) + } + return nil + } + if source.Kind == OpImm { + if !isX86IMULImmediate(source, goarch) { + return fmt.Errorf("%s %s immediate is outside Go 1.27's Yi8/Yi32 classes: %q", goarch, op, ins.Raw) + } + return nil + } + if !isX86ScalarMultiplyDivideSource(source, bits, goarch) { + return fmt.Errorf("%s %s source is outside Go 1.27's Yml class: %q", goarch, op, ins.Raw) + } + return nil +} + +func isX86IMULImmediate(operand Operand, goarch string) bool { + if operand.Kind != OpImm { + return false + } + // The 386 assembler classifies constants after truncating them to int32. + // In amd64 mode Yi32 covers signed int32 through unsigned uint32. + return goarch == "386" || (operand.Imm >= -2147483648 && operand.Imm <= 4294967295) +} + +func (c *amd64Ctx) emitX86ImplicitMultiply(bits int, signed bool, source Operand) error { + narrow := amd64IntegerTypeForBits(bits) + wide := x86ScalarMultiplyDivideWideType(bits) + src, err := c.evalIntSized(source, narrow) + if err != nil { + return err + } + acc, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, narrow) + if err != nil { + return err + } + lhs := c.extendX86MulDivValue(acc, narrow, wide, signed) + rhs := c.extendX86MulDivValue(src, narrow, wide, signed) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul %s %s, %s\n", product, wide, lhs, rhs) + + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", low, wide, product, narrow) + if bits == 8 { + if err := c.storeRegSized(AX, I16, "%"+product); err != nil { + return err + } + } else { + shifted := c.newTmp() + shift := "lshr" + if signed { + shift = "ashr" + } + fmt.Fprintf(c.b, " %%%s = %s %s %%%s, %d\n", shifted, shift, wide, product, bits) + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", high, wide, shifted, narrow) + if err := c.storeRegSized(AX, narrow, "%"+low); err != nil { + return err + } + if err := c.storeRegSized(DX, narrow, "%"+high); err != nil { + return err + } + } + c.setX86MultiplyOverflowFlags(narrow, wide, "%"+low, "%"+product, signed) + return nil +} + +func (c *amd64Ctx) emitX86ExplicitIMUL(bits int, immediate, source, destination Operand) error { + typ := amd64IntegerTypeForBits(bits) + wide := x86ScalarMultiplyDivideWideType(bits) + right, err := c.evalIntSized(source, typ) + if err != nil { + return err + } + left := "" + if immediate.Kind == OpImm { + left = x86IMULImmediateValue(immediate.Imm, bits) + } else { + left, err = c.evalIntSized(destination, typ) + if err != nil { + return err + } + } + lhs := c.extendX86MulDivValue(left, typ, wide, true) + rhs := c.extendX86MulDivValue(right, typ, wide, true) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul %s %s, %s\n", product, wide, lhs, rhs) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", low, wide, product, typ) + if err := c.storeRegSized(destination.Reg, typ, "%"+low); err != nil { + return err + } + c.setX86MultiplyOverflowFlags(typ, wide, "%"+low, "%"+product, true) + return nil +} + +func x86IMULImmediateValue(value int64, bits int) string { + switch bits { + case 16: + return fmt.Sprintf("%d", uint16(value)) + case 32: + return fmt.Sprintf("%d", uint32(value)) + case 64: + // x86-64 IMUL encodes this table's immediate as imm32 and sign + // extends it to the qword operand width. + return fmt.Sprintf("%d", int64(int32(value))) + default: + panic("unsupported explicit IMUL width") + } +} + +func (c *amd64Ctx) emitX86ImplicitDivide(bits int, signed bool, source Operand) error { + narrow := amd64IntegerTypeForBits(bits) + wide := x86ScalarMultiplyDivideWideType(bits) + divisorNarrow, err := c.evalIntSized(source, narrow) + if err != nil { + return err + } + divisor := c.extendX86MulDivValue(divisorNarrow, narrow, wide, signed) + + var dividend string + if bits == 8 { + dividend, err = c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, I16) + if err != nil { + return err + } + } else { + low, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, narrow) + if err != nil { + return err + } + high, err := c.evalIntSized(Operand{Kind: OpReg, Reg: DX}, narrow) + if err != nil { + return err + } + lowWide := c.extendX86MulDivValue(low, narrow, wide, false) + highWide := c.extendX86MulDivValue(high, narrow, wide, signed) + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl %s %s, %d\n", shifted, wide, highWide, bits) + joined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %s\n", joined, wide, shifted, lowWide) + dividend = "%" + joined + } + + divide := "udiv" + remainder := "urem" + if signed { + divide = "sdiv" + remainder = "srem" + } + quotientWide := c.newTmp() + remainderWide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", quotientWide, divide, wide, dividend, divisor) + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", remainderWide, remainder, wide, dividend, divisor) + quotient := c.newTmp() + remainderValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", quotient, wide, quotientWide, narrow) + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", remainderValue, wide, remainderWide, narrow) + if bits == 8 { + q16 := c.extendX86MulDivValue("%"+quotient, I8, I16, false) + r16 := c.extendX86MulDivValue("%"+remainderValue, I8, I16, false) + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i16 %s, 8\n", shifted, r16) + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i16 %%%s, %s\n", combined, shifted, q16) + return c.storeRegSized(AX, I16, "%"+combined) + } + if err := c.storeRegSized(AX, narrow, "%"+quotient); err != nil { + return err + } + return c.storeRegSized(DX, narrow, "%"+remainderValue) +} + +func (c *amd64Ctx) extendX86MulDivValue(value string, from, to LLVMType, signed bool) string { + tmp := c.newTmp() + op := "zext" + if signed { + op = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", tmp, op, from, value, to) + return "%" + tmp +} + +func x86ScalarMultiplyDivideWideType(bits int) LLVMType { + if bits == 64 { + return LLVMType("i128") + } + return amd64IntegerTypeForBits(bits * 2) +} + +func (c *amd64Ctx) setX86MultiplyOverflowFlags(narrow, wide LLVMType, low, product string, signed bool) { + var overflow string + if signed { + extended := c.extendX86MulDivValue(low, narrow, wide, true) + cmp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne %s %s, %s\n", cmp, wide, product, extended) + overflow = "%" + cmp + } else { + extended := c.extendX86MulDivValue(low, narrow, wide, false) + cmp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne %s %s, %s\n", cmp, wide, product, extended) + overflow = "%" + cmp + } + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", overflow, c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", overflow, c.flagsOFSlot) +} diff --git a/amd64_lower_mulvec.go b/amd64_lower_mulvec.go new file mode 100644 index 00000000..5b5a498a --- /dev/null +++ b/amd64_lower_mulvec.go @@ -0,0 +1,162 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedDwordMultiply implements every operand shape in Go 1.27's +// PMULLD yxm_q4 and VPMULLD _yvandnpd tables, including EVEX masks and +// the memory broadcast enabled by evexBcstN4. +func (c *amd64Ctx) lowerPackedDwordMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := string(op) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + switch baseOp { + case "PMULLD", "VPMULLD": + // handled below + default: + return false, false, nil + } + zeroMasking := false + broadcast := false + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + suffixes := strings.Split(rawOp[dot+1:], ".") + for i, suffix := range suffixes { + switch suffix { + case "BCST": + if broadcast || zeroMasking { + return true, false, fmt.Errorf("amd64 %s has invalid suffix order or duplicate .BCST: %q", baseOp, ins.Raw) + } + broadcast = true + case "Z": + if zeroMasking || i != len(suffixes)-1 { + return true, false, fmt.Errorf("amd64 %s has invalid or duplicate .Z suffix: %q", baseOp, ins.Raw) + } + zeroMasking = true + default: + return true, false, fmt.Errorf("amd64 %s has unsupported suffix .%s: %q", baseOp, suffix, ins.Raw) + } + } + } + vectorForm := baseOp == "VPMULLD" + if (!vectorForm && len(ins.Args) != 2) || (vectorForm && len(ins.Args) != 3 && len(ins.Args) != 4) { + return true, false, fmt.Errorf("amd64 %s expects src, [src, K mask,] vector dst: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if !vectorForm && (broadcast || zeroMasking) { + return true, false, fmt.Errorf("amd64 PMULLD does not accept EVEX suffixes: %q", ins.Raw) + } + if zeroMasking && !masked { + return true, false, fmt.Errorf("amd64 VPMULLD .Z form requires a K mask: %q", ins.Raw) + } + if broadcast && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 VPMULLD .BCST requires a memory source: %q", ins.Raw) + } + + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects vector destination: %q", baseOp, ins.Raw) + } + byteWidth := 0 + var loadOperand func(Operand) (string, error) + var loadDst func() (string, error) + var storeDst func(string) error + switch { + case isAMD64XReg(dstArg.Reg): + byteWidth = 16 + loadOperand = c.loadXVecOperand + loadDst = func() (string, error) { return c.loadX(dstArg.Reg) } + storeDst = func(value string) error { return c.storeX(dstArg.Reg, value) } + case vectorForm && isAMD64YReg(dstArg.Reg): + byteWidth = 32 + loadOperand = c.loadYVecOperand + loadDst = func() (string, error) { return c.loadY(dstArg.Reg) } + storeDst = func(value string) error { return c.storeY(dstArg.Reg, value) } + case vectorForm && isAMD64ZReg(dstArg.Reg): + byteWidth = 64 + loadOperand = c.loadZVecOperand + loadDst = func() (string, error) { return c.loadZ(dstArg.Reg) } + storeDst = func(value string) error { return c.storeZ(dstArg.Reg, value) } + default: + return true, false, fmt.Errorf("amd64 %s has mismatched or non-vector destination: %q", baseOp, ins.Raw) + } + lanes := byteWidth / 4 + + loadI32Lanes := func(arg Operand, allowBroadcast bool) (string, error) { + if allowBroadcast && broadcast { + value, err := c.evalIntSized(arg, I32) + if err != nil { + return "", err + } + return amd64SplatInteger(c, lanes, 32, value), nil + } + bytesValue, err := loadOperand(arg) + if err != nil { + return "", err + } + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i32>\n", cast, byteWidth, bytesValue, lanes) + return "%" + cast, nil + } + + lhs, err := loadI32Lanes(ins.Args[0], true) + if err != nil { + return true, false, err + } + var rhs string + if vectorForm { + rhs, err = loadI32Lanes(ins.Args[1], false) + } else { + dstBytes, loadErr := loadDst() + if loadErr != nil { + return true, false, loadErr + } + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", cast, dstBytes) + rhs = "%" + cast + } + if err != nil { + return true, false, err + } + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul <%d x i32> %s, %s\n", product, lanes, lhs, rhs) + result := "%" + product + + if masked { + maskArg := ins.Args[2] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 VPMULLD masked form expects K1-K7: %q", ins.Raw) + } + maskIndex, ok := amd64ParseKReg(maskArg.Reg) + if !ok || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 VPMULLD masked form expects K1-K7: %q", ins.Raw) + } + mask, err := c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + oldBytes, err := loadDst() + if err != nil { + return true, false, err + } + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i32>\n", old, byteWidth, oldBytes, lanes) + result = amd64ApplyI32LaneMask(c, lanes, result, "%"+old, mask, zeroMasking) + } + + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i32> %s to <%d x i8>\n", out, lanes, result, byteWidth) + return true, false, storeDst("%" + out) +} + +func isAMD64MemoryOperand(op Operand) bool { + switch op.Kind { + case OpFP, OpMem, OpSym: + return true + default: + return false + } +} diff --git a/amd64_lower_mulword.go b/amd64_lower_mulword.go new file mode 100644 index 00000000..c57d9a57 --- /dev/null +++ b/amd64_lower_mulword.go @@ -0,0 +1,230 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedWordMultiplyMode uint8 + +const ( + amd64PackedWordMultiplyLow amd64PackedWordMultiplyMode = iota + amd64PackedWordMultiplySignedHigh + amd64PackedWordMultiplyUnsignedHigh + amd64PackedWordMultiplyRoundedSignedHigh +) + +// lowerPackedWordMultiply implements every Go 1.27 form of PMULLW, +// PMULHW, PMULHUW, PMULHRSW and their VEX/EVEX counterparts. +func (c *amd64Ctx) lowerPackedWordMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + mode, vector, recognized := amd64PackedWordMultiplyProperties(baseOp) + if !recognized { + return false, false, nil + } + if !vector { + return c.lowerLegacyPackedWordMultiply(baseOp, suffix, mode, ins) + } + return c.lowerVectorPackedWordMultiply(baseOp, suffix, mode, ins) +} + +func amd64PackedWordMultiplyProperties(op string) (mode amd64PackedWordMultiplyMode, vector, ok bool) { + switch op { + case "PMULLW": + return amd64PackedWordMultiplyLow, false, true + case "PMULHW": + return amd64PackedWordMultiplySignedHigh, false, true + case "PMULHUW": + return amd64PackedWordMultiplyUnsignedHigh, false, true + case "PMULHRSW": + return amd64PackedWordMultiplyRoundedSignedHigh, false, true + case "VPMULLW": + return amd64PackedWordMultiplyLow, true, true + case "VPMULHW": + return amd64PackedWordMultiplySignedHigh, true, true + case "VPMULHUW": + return amd64PackedWordMultiplyUnsignedHigh, true, true + case "VPMULHRSW": + return amd64PackedWordMultiplyRoundedSignedHigh, true, true + default: + return 0, false, false + } +} + +func (c *amd64Ctx) lowerLegacyPackedWordMultiply(baseOp, suffix string, mode amd64PackedWordMultiplyMode, ins Instr) (bool, bool, error) { + if suffix != "" { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects packed source, packed destination: %q", c.goarch, baseOp, ins.Raw) + } + dst := ins.Args[1].Reg + if _, mmx := amd64ParseMReg(dst); mmx { + if c.goarch != "amd64" { + return true, false, fmt.Errorf("386 %s MMX form is illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + if mode == amd64PackedWordMultiplyRoundedSignedHigh { + return true, false, fmt.Errorf("amd64 PMULHRSW has no MMX row in Go 1.27's yxm_q4 table: %q", ins.Raw) + } + firstBits, err := c.loadLegacyMMXPackedSource(ins.Args[0]) + if err != nil { + return true, false, fmt.Errorf("amd64 %s MMX source: %w", baseOp, err) + } + secondBits, err := c.loadReg(dst) + if err != nil { + return true, false, err + } + first := c.bitcastI64ToIntegerLanes(4, 16, firstBits) + second := c.bitcastI64ToIntegerLanes(4, 16, secondBits) + result := c.emitPackedWordMultiply(4, first, second, mode) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i16> %s to i64\n", bits, result) + return true, false, c.storeReg(dst, "%"+bits) + } + + if !c.isGoLegacyXReg(dst) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s XMM source is outside Go 1.27's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s source must be X or memory: %q", c.goarch, baseOp, ins.Raw) + } + firstBytes, err := c.loadPackedCompareBytes(ins.Args[0], 16) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(dst) + if err != nil { + return true, false, err + } + first := c.bitcastVectorBytesToIntegerLanes(16, 8, 16, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(16, 8, 16, secondBytes) + result := c.emitPackedWordMultiply(8, first, second, mode) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <8 x i16> %s to <16 x i8>\n", out, result) + return true, false, c.storeX(dst, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedWordMultiply(baseOp, suffix string, mode amd64PackedWordMultiplyMode, ins Instr) (bool, bool, error) { + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("%s %s has a suffix absent from its Go 1.27 optab: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects src1, src2, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects a vector-register destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s expects an X, Y, or Z destination: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && byteWidth == 64 { + return true, false, fmt.Errorf("386 %s has no Z-width form in Go 1.27's assembler frontend: %q", baseOp, ins.Raw) + } + if !amd64EVEXVectorRegister(dstArg, byteWidth) || !amd64EVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s second source and destination must be same-width vector registers: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !amd64EVEXVectorRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match its destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + var err error + mask, err = c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + } + firstBytes, err := c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + lanes := byteWidth / 2 + first := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 16, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 16, secondBytes) + result := c.emitPackedWordMultiply(lanes, first, second, mode) + if masked { + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 16, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, 16, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i16> %s to <%d x i8>\n", out, lanes, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPackedWordMultiply(lanes int, first, second string, mode amd64PackedWordMultiplyMode) string { + wordType := fmt.Sprintf("<%d x i16>", lanes) + if mode == amd64PackedWordMultiplyLow { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul %s %s, %s\n", result, wordType, second, first) + return "%" + result + } + + wideType := fmt.Sprintf("<%d x i32>", lanes) + extend := "sext" + shift := int64(16) + if mode == amd64PackedWordMultiplyUnsignedHigh { + extend = "zext" + } + firstWide := c.newTmp() + secondWide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", firstWide, extend, wordType, first, wideType) + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", secondWide, extend, wordType, second, wideType) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul %s %%%s, %%%s\n", product, wideType, secondWide, firstWide) + value := "%" + product + if mode == amd64PackedWordMultiplyRoundedSignedHigh { + rounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", rounded, wideType, value, llvmSplatSignedInteger(lanes, 32, 16384)) + value = "%" + rounded + shift = 15 + } + shifted := c.newTmp() + shiftOp := "ashr" + if mode == amd64PackedWordMultiplyUnsignedHigh { + shiftOp = "lshr" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", shifted, shiftOp, wideType, value, llvmSplatSignedInteger(lanes, 32, shift)) + value = "%" + shifted + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", result, wideType, value, wordType) + return "%" + result +} diff --git a/amd64_lower_mxcsr.go b/amd64_lower_mxcsr.go new file mode 100644 index 00000000..0fab1b24 --- /dev/null +++ b/amd64_lower_mxcsr.go @@ -0,0 +1,71 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *amd64Ctx) lowerMXCSR(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + switch baseOp { + case "LDMXCSR", "VLDMXCSR", "STMXCSR", "VSTMXCSR": + // handled below + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 1 || !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s expects one memory operand: %q", baseOp, ins.Raw) + } + slot := c.newTmp() + fmt.Fprintf(c.b, " %%%s = alloca i32\n", slot) + switch baseOp { + case "LDMXCSR", "VLDMXCSR": + value, err := c.evalIntSized(ins.Args[0], I32) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store i32 %s, ptr %%%s\n", value, slot) + fmt.Fprintf(c.b, " call void @llvm.x86.sse.ldmxcsr(ptr %%%s)\n", slot) + return true, false, nil + case "STMXCSR", "VSTMXCSR": + value := c.newTmp() + fmt.Fprintf(c.b, " call void @llvm.x86.sse.stmxcsr(ptr %%%s)\n", slot) + fmt.Fprintf(c.b, " %%%s = load i32, ptr %%%s\n", value, slot) + if err := c.storeMXCSRMemory(ins.Args[0], "%"+value); err != nil { + return true, false, err + } + return true, false, nil + default: + panic("MXCSR opcode precheck drift") + } +} + +func (c *amd64Ctx) storeMXCSRMemory(dst Operand, value string) error { + switch dst.Kind { + case OpMem: + ptr, ptrType, err := c.ptrFromMem(dst.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store i32 %s, %s %s, align 1\n", value, ptrType, ptr) + return nil + case OpSym: + ptr, err := c.ptrFromSB(dst.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store i32 %s, ptr %s, align 1\n", value, ptr) + return nil + case OpFP: + return c.storeFPResult(dst.FPOffset, I32, value) + default: + return fmt.Errorf("amd64: unsupported MXCSR memory operand %s", dst.String()) + } +} diff --git a/amd64_lower_narrow_single_source.go b/amd64_lower_narrow_single_source.go new file mode 100644 index 00000000..6143bacd --- /dev/null +++ b/amd64_lower_narrow_single_source.go @@ -0,0 +1,218 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64SingleSourceNarrowSpec struct { + inputBits int + outputBits int + saturating bool + mode amd64PackedNarrowMode +} + +var amd64SingleSourceNarrowSpecs = map[string]amd64SingleSourceNarrowSpec{ + "VPMOVDB": {inputBits: 32, outputBits: 8}, + "VPMOVDW": {inputBits: 32, outputBits: 16}, + "VPMOVQB": {inputBits: 64, outputBits: 8}, + "VPMOVQD": {inputBits: 64, outputBits: 32}, + "VPMOVQW": {inputBits: 64, outputBits: 16}, + "VPMOVWB": {inputBits: 16, outputBits: 8}, + "VPMOVSDB": {inputBits: 32, outputBits: 8, saturating: true, mode: amd64PackedNarrowSigned}, + "VPMOVSDW": {inputBits: 32, outputBits: 16, saturating: true, mode: amd64PackedNarrowSigned}, + "VPMOVSQB": {inputBits: 64, outputBits: 8, saturating: true, mode: amd64PackedNarrowSigned}, + "VPMOVSQD": {inputBits: 64, outputBits: 32, saturating: true, mode: amd64PackedNarrowSigned}, + "VPMOVSQW": {inputBits: 64, outputBits: 16, saturating: true, mode: amd64PackedNarrowSigned}, + "VPMOVSWB": {inputBits: 16, outputBits: 8, saturating: true, mode: amd64PackedNarrowSigned}, + "VPMOVUSDB": {inputBits: 32, outputBits: 8, saturating: true, mode: amd64PackedNarrowUnsigned}, + "VPMOVUSDW": {inputBits: 32, outputBits: 16, saturating: true, mode: amd64PackedNarrowUnsigned}, + "VPMOVUSQB": {inputBits: 64, outputBits: 8, saturating: true, mode: amd64PackedNarrowUnsigned}, + "VPMOVUSQD": {inputBits: 64, outputBits: 32, saturating: true, mode: amd64PackedNarrowUnsigned}, + "VPMOVUSQW": {inputBits: 64, outputBits: 16, saturating: true, mode: amd64PackedNarrowUnsigned}, + "VPMOVUSWB": {inputBits: 16, outputBits: 8, saturating: true, mode: amd64PackedNarrowUnsigned}, +} + +// lowerSingleSourceIntegerNarrow implements the complete Go 1.27 +// _yvpmovdb/_yvpmovdw family: truncating, signed-saturating, and +// signed-to-unsigned-saturating conversions from X/Y/Z into X/Y or memory. +func (c *amd64Ctx) lowerSingleSourceIntegerNarrow(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, handled := amd64SingleSourceNarrowSpecs[baseOp] + if !handled { + return false, false, nil + } + if suffix != "" && suffix != "Z" { + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's _yvpmovdb/_yvpmovdw tables: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects vector source, [K1-K7 mask,] vector or memory destination: %q", c.goarch, baseOp, ins.Raw) + } + + source := ins.Args[0] + inputBytes := amd64VectorByteWidth(source.Reg) + if source.Kind != OpReg || inputBytes != 16 && inputBytes != 32 && inputBytes != 64 || !c.isGoEVEXVectorRegister(source, inputBytes) { + return true, false, fmt.Errorf("%s %s source must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if suffix == "Z" && !masked { + return true, false, fmt.Errorf("%s %s.Z requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + var mask string + if masked { + maskArg := ins.Args[1] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + index, valid := amd64ParseKReg(maskArg.Reg) + if !valid || index == 0 { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + destination := ins.Args[len(ins.Args)-1] + lanes := inputBytes * 8 / spec.inputBits + outputBytes := lanes * spec.outputBits / 8 + destinationBytes := 16 + if outputBytes > 16 { + destinationBytes = 32 + } + if destination.Kind == OpReg { + if amd64VectorByteWidth(destination.Reg) != destinationBytes || !c.isGoEVEXVectorRegister(destination, destinationBytes) { + return true, false, fmt.Errorf("%s %s destination must be an in-range %s register for a %s source: %q", c.goarch, baseOp, map[int]string{16: "X", 32: "Y"}[destinationBytes], strings.ToUpper(string(source.Reg))[0:1], ins.Raw) + } + } else if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s %s destination must be the matching X/Y register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + sourceBytes, err := c.loadPackedCompareBytes(source, inputBytes) + if err != nil { + return true, false, err + } + sourceLanes := c.bitcastVectorBytesToIntegerLanes(inputBytes, lanes, spec.inputBits, sourceBytes) + narrowed := c.emitSingleSourceIntegerNarrow(spec, lanes, sourceLanes) + zeroing := suffix == "Z" + if destination.Kind == OpReg { + return true, false, c.storeSingleSourceNarrowRegister(destination.Reg, destinationBytes, lanes, spec.outputBits, narrowed, mask, zeroing) + } + return true, false, c.storeSingleSourceNarrowMemory(destination, outputBytes, lanes, spec.outputBits, narrowed, mask, zeroing) +} + +func (c *amd64Ctx) emitSingleSourceIntegerNarrow(spec amd64SingleSourceNarrowSpec, lanes int, source string) string { + inputType := fmt.Sprintf("<%d x i%d>", lanes, spec.inputBits) + outputType := fmt.Sprintf("<%d x i%d>", lanes, spec.outputBits) + if !spec.saturating { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", result, inputType, source, outputType) + return "%" + result + } + result := "poison" + for lane := 0; lane < lanes; lane++ { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", value, inputType, source, lane) + narrowed := c.saturatePackedInteger("%"+value, spec.inputBits, spec.outputBits, spec.mode) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %s, i32 %d\n", inserted, outputType, result, spec.outputBits, narrowed, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) storeSingleSourceNarrowRegister(destination Reg, destinationBytes, lanes, outputBits int, narrowed, mask string, zeroing bool) error { + physicalLanes := destinationBytes * 8 / outputBits + result := "zeroinitializer" + var old string + if mask != "" && !zeroing { + oldBytes, err := c.loadPackedCompareBytes(Operand{Kind: OpReg, Reg: destination}, destinationBytes) + if err != nil { + return err + } + old = c.bitcastVectorBytesToIntegerLanes(destinationBytes, physicalLanes, outputBits, oldBytes) + } + for lane := 0; lane < lanes; lane++ { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", value, lanes, outputBits, narrowed, lane) + selected := "%" + value + if mask != "" { + fallback := "0" + if !zeroing { + oldValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", oldValue, physicalLanes, outputBits, old, lane) + fallback = "%" + oldValue + } + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %s, i%d %s\n", masked, amd64MaskBitI1(c, mask, lane), outputBits, selected, outputBits, fallback) + selected = "%" + masked + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %s, i32 %d\n", inserted, physicalLanes, outputBits, result, outputBits, selected, lane) + result = "%" + inserted + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, physicalLanes, outputBits, result, destinationBytes) + return c.storeVectorBytes(destination, destinationBytes, "%"+out) +} + +func (c *amd64Ctx) storeSingleSourceNarrowMemory(destination Operand, outputBytes, lanes, outputBits int, narrowed, mask string, zeroing bool) error { + result := narrowed + if mask != "" { + var old string + if !zeroing { + oldBytes, err := c.loadNarrowMemoryBytes(destination, outputBytes) + if err != nil { + return err + } + old = c.bitcastVectorBytesToIntegerLanes(outputBytes, lanes, outputBits, oldBytes) + } + result = "poison" + for lane := 0; lane < lanes; lane++ { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", value, lanes, outputBits, narrowed, lane) + fallback := "0" + if !zeroing { + oldValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", oldValue, lanes, outputBits, old, lane) + fallback = "%" + oldValue + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %s\n", selected, amd64MaskBitI1(c, mask, lane), outputBits, value, outputBits, fallback) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", inserted, lanes, outputBits, result, outputBits, selected, lane) + result = "%" + inserted + } + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, outputBits, result, outputBytes) + return c.storeNarrowMemoryBytes(destination, outputBytes, "%"+out) +} + +func (c *amd64Ctx) loadNarrowMemoryBytes(source Operand, byteWidth int) (string, error) { + if byteWidth >= 16 { + return c.loadPackedCompareBytes(source, byteWidth) + } + typ := amd64IntegerTypeForBits(byteWidth * 8) + value, err := c.evalIntSized(source, typ) + if err != nil { + return "", err + } + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", bytesValue, typ, value, byteWidth) + return "%" + bytesValue, nil +} + +func (c *amd64Ctx) storeNarrowMemoryBytes(destination Operand, byteWidth int, value string) error { + if byteWidth >= 16 { + return c.storeVectorBytesOperand(destination, byteWidth, value) + } + typ := amd64IntegerTypeForBits(byteWidth * 8) + integer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", integer, byteWidth, value, typ) + return c.storeVectorScalarMemory(destination, byteWidth*8, "%"+integer, "") +} diff --git a/amd64_lower_narrow_single_source_test.go b/amd64_lower_narrow_single_source_test.go new file mode 100644 index 00000000..90075f0f --- /dev/null +++ b/amd64_lower_narrow_single_source_test.go @@ -0,0 +1,129 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86SingleSourceIntegerNarrowCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 31 + if target.goarch == "386" { + last = 7 + } + var source strings.Builder + source.WriteString("TEXT singlesourcenarrowforms(SB),$0-0\n") + for _, op := range []string{ + "VPMOVDB", "VPMOVDW", "VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVWB", + "VPMOVSDB", "VPMOVSDW", "VPMOVSQB", "VPMOVSQD", "VPMOVSQW", "VPMOVSWB", + "VPMOVUSDB", "VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW", "VPMOVUSWB", + } { + inputBits, outputBits := x86SingleSourceNarrowTestBits(op) + for _, width := range []struct { + name string + bytes int + }{ + {name: "X", bytes: 16}, + {name: "Y", bytes: 32}, + {name: "Z", bytes: 64}, + } { + outputBytes := width.bytes * outputBits / inputBits + destinationWidth := "X" + if outputBytes > 16 { + destinationWidth = "Y" + } + fmt.Fprintf(&source, "\t%s %s%d, %s%d\n", op, width.name, last, destinationWidth, last) + fmt.Fprintf(&source, "\t%s %s%d, K1, %s%d\n", op, width.name, last, destinationWidth, last) + fmt.Fprintf(&source, "\t%s.Z %s%d, K2, %s%d\n", op, width.name, last, destinationWidth, last) + fmt.Fprintf(&source, "\t%s %s%d, 8(AX)\n", op, width.name, last) + fmt.Fprintf(&source, "\t%s %s%d, K3, 16(AX)\n", op, width.name, last) + fmt.Fprintf(&source, "\t%s.Z %s%d, K4, 24(AX)\n", op, width.name, last) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "singlesourcenarrowforms": {Name: "singlesourcenarrowforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "single-source-integer-narrow.ll", "single-source-integer-narrow.o", ll) + }) + } +} + +func x86SingleSourceNarrowTestBits(op string) (inputBits, outputBits int) { + pair := strings.TrimPrefix(strings.TrimPrefix(strings.TrimPrefix(op, "VPMOV"), "US"), "S") + bits := func(letter byte) int { + switch letter { + case 'B': + return 8 + case 'W': + return 16 + case 'D': + return 32 + case 'Q': + return 64 + default: + panic("bad narrow element letter") + } + } + return bits(pair[0]), bits(pair[1]) +} + +func TestTranslateX86SingleSourceIntegerNarrowRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPMOVSDB 8(AX), X0", + "VPMOVSDB X0, Y0", + "VPMOVSDW Z0, X0", + "VPMOVSDB X0, K0, X1", + "VPMOVSDB.Z X0, X1", + "VPMOVSDB.BCST X0, X1", + "VPMOVSDB X0, K1, K2, X1", + "VPMOVSDB X0, AX", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yvpmovdb/_yvpmovdw tables", instruction) + } + }) + } +} diff --git a/amd64_lower_neg.go b/amd64_lower_neg.go new file mode 100644 index 00000000..3870aeff --- /dev/null +++ b/amd64_lower_neg.go @@ -0,0 +1,63 @@ +package plan9asm + +import "fmt" + +// Both complete unary families use Go's yscond(Ymb) grammar, including +// byte-register spellings of wide operations. Only NEG changes flags. +type x86UnaryYmbSpec struct { + bits int + negate bool +} + +var x86UnaryYmbSpecs = map[Op]x86UnaryYmbSpec{ + "NEGB": {bits: 8, negate: true}, + "NEGW": {bits: 16, negate: true}, + "NEGL": {bits: 32, negate: true}, + "NEGQ": {bits: 64, negate: true}, + "NOTB": {bits: 8}, + "NOTW": {bits: 16}, + "NOTL": {bits: 32}, + "NOTQ": {bits: 64}, +} + +func (c *amd64Ctx) lowerScalarUnaryYmb(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, recognized := x86UnaryYmbSpecs[op] + if !recognized { + return false, false, nil + } + bits := spec.bits + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", op, ins.Raw) + } + if len(ins.Args) != 1 { + return true, false, fmt.Errorf("%s %s expects one register/memory operand: %q", c.goarch, op, ins.Raw) + } + destination := ins.Args[0] + if destination.Kind == OpReg { + if !isGoYmbRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s register is outside Go 1.27's Ymb class: %q", c.goarch, op, ins.Raw) + } + destination.Reg = amd64YmbEffectiveRegister(destination.Reg, bits) + } else if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s %s operand is outside Go 1.27's Ymb class: %q", c.goarch, op, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + value, store, err := c.loadIntDestination(destination, typ) + if err != nil { + return true, false, err + } + result := c.newTmp() + if !spec.negate { + fmt.Fprintf(c.b, " %%%s = xor %s %s, -1\n", result, typ, value) + return true, false, store("%" + result) + } + fmt.Fprintf(c.b, " %%%s = sub %s 0, %s\n", result, typ, value) + if err := store("%" + result); err != nil { + return true, false, err + } + // NEG has the same arithmetic flags as subtraction from zero: CF is set + // exactly for nonzero inputs and OF is set only for the signed minimum. + c.setScalarAddSubFlags(typ, false, "0", value, "%"+result) + return true, false, nil +} diff --git a/amd64_lower_neg_test.go b/amd64_lower_neg_test.go new file mode 100644 index 00000000..7ab2773f --- /dev/null +++ b/amd64_lower_neg_test.go @@ -0,0 +1,294 @@ +package plan9asm + +import ( + "fmt" + "os" + "path/filepath" + "regexp" + "runtime" + "strings" + "testing" +) + +func TestX86UnaryYmbGrammarMatchesGoEncoder(t *testing.T) { + data, err := os.ReadFile(filepath.Join(runtime.GOROOT(), "src/cmd/internal/obj/x86/asm6.go")) + if err != nil { + t.Fatal(err) + } + rows := regexp.MustCompile(`\{A((?:NEG|NOT)[BWLQ]),\s*yscond,`).FindAllStringSubmatch(string(data), -1) + if len(rows) != len(x86UnaryYmbSpecs) || len(rows) != 8 { + t.Fatalf("Go encoder has %d NEG/NOT Ymb rows; grammar has %d", len(rows), len(x86UnaryYmbSpecs)) + } + for _, row := range rows { + name := row[1] + spec, ok := x86UnaryYmbSpecs[Op(name)] + width := map[byte]int{'B': 8, 'W': 16, 'L': 32, 'Q': 64}[name[len(name)-1]] + if !ok || spec.bits != width || spec.negate != strings.HasPrefix(name, "NEG") { + t.Errorf("Go %s encoder row disagrees with grammar: %+v, present=%v", name, spec, ok) + } + } +} + +func x86NEGCompleteFormsSource(goarch string) string { + var source strings.Builder + symbol := "negdata" + size := 8 + if goarch == "386" { + symbol = "negdata386" + size = 4 + } + fmt.Fprintf(&source, "DATA %s+0(SB)/%d, $1\n", symbol, size) + fmt.Fprintf(&source, "GLOBL %s(SB), $%d\n", symbol, size) + source.WriteString("TEXT negforms(SB),$0-0\n") + if goarch == "amd64" { + source.WriteString("\tNEGB AH\n\tNEGB R11\n") + } else { + source.WriteString("\tNEGB AH\n\tNEGB BP\n") + } + source.WriteString("\tNEGB 8(BX)\n\tNEGB " + symbol + "(SB)\n") + widths := []string{"W", "L"} + if goarch == "amd64" { + widths = append(widths, "Q") + } + for _, width := range widths { + // yscond uses Ymb even for wide opcodes. Byte spellings therefore + // select the full register with the same raw ModRM number. + for _, reg := range []string{"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH"} { + fmt.Fprintf(&source, "\tNEG%s %s\n", width, reg) + } + fmt.Fprintf(&source, "\tNEG%s DX\n", width) + if goarch == "amd64" { + for _, reg := range []string{"SP", "BPB", "SIB", "DIB", "R8", "R15", "R8B", "R15B"} { + fmt.Fprintf(&source, "\tNEG%s %s\n", width, reg) + } + } else { + fmt.Fprintf(&source, "\tNEG%s SI\n", width) + } + fmt.Fprintf(&source, "\tNEG%s 8(BX)\n\tNEG%s %s(SB)\n", width, width, symbol) + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86NEGCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86NEGCompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"negforms": {Name: "negforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sub i8 0", "sub i16 0", "sub i32 0", "store i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("NEG lowering omitted %q:\n%s", want, ll) + } + } + if target.goarch == "amd64" && !strings.Contains(ll, "sub i64 0") { + t.Fatalf("NEGQ lowering omitted sub i64:\n%s", ll) + } + compileLLVMToObject(t, llc, target.triple, "neg-"+target.name+".ll", "neg-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86NEGRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "NEGB X0"}, + {goarch: "amd64", instruction: "NEGW $1"}, + {goarch: "amd64", instruction: "NEGL AX, BX"}, + {goarch: "amd64", instruction: "NEGQ"}, + {goarch: "amd64", instruction: "NEGQ.Z AX"}, + {goarch: "386", instruction: "NEGB SP"}, + {goarch: "386", instruction: "NEGW SP"}, + {goarch: "386", instruction: "NEGL SP"}, + {goarch: "386", instruction: "NEGL R8"}, + {goarch: "386", instruction: "NEGQ AX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's NEG yscond table", test.instruction) + } + }) + } +} + +func TestAMD64NEGRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT negsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVQ $0x1122, AX + NEGB AH + MOVQ AX, 0(DI) + MOVQ $0x1122334455660001, AX + NEGW AX + MOVQ AX, 8(DI) + MOVQ $0x1122334480000000, AX + NEGL AX + MOVQ AX, 16(DI) + SETCS 32(DI) + SETOS 33(DI) + SETEQ 34(DI) + SETMI 35(DI) + SETPS 36(DI) + MOVQ $5, 24(DI) + NEGQ 24(DI) + MOVB $0, 40(DI) + NEGB 40(DI) + SETCS 41(DI) + SETOS 42(DI) + SETEQ 43(DI) + SETMI 44(DI) + SETPS 45(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "negsemantics": { + Name: "negsemantics", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void negsemantics(uint8_t *); +int main(void) { + uint8_t out[48] = {0}; + negsemantics(out); + if (*(uint64_t *)(out+0) != UINT64_C(0xef22)) return 10; + if (*(uint64_t *)(out+8) != UINT64_C(0x112233445566ffff)) return 11; + if (*(uint64_t *)(out+16) != UINT64_C(0x80000000)) return 12; + if (*(uint64_t *)(out+24) != UINT64_C(0xfffffffffffffffb)) return 13; + if (out[32] != 1 || out[33] != 1 || out[34] != 0 || out[35] != 1 || out[36] != 1) return 14; + if (out[40] != 0 || out[41] != 0 || out[42] != 0 || out[43] != 1 || out[44] != 0 || out[45] != 1) return 15; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "neg_semantics", triple, ll, mainC, runPrefix) +} + +func TestAMD64UnaryYmbAliasesRuntime(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + var source, checks strings.Builder + source.WriteString("TEXT unaryaliases(SB),$0-8\n\tMOVQ out+0(FP), R14\n") + index := 0 + for _, family := range []string{"NEG", "NOT"} { + for _, width := range []struct { + suffix string + bits uint + }{{"W", 16}, {"L", 32}, {"Q", 64}} { + for _, reg := range []struct{ spelling, effective string }{ + {"AL", "AX"}, {"CL", "CX"}, {"DL", "DX"}, {"BL", "BX"}, + {"AH", "SP"}, {"CH", "BP"}, {"DH", "SI"}, {"BH", "DI"}, + {"BPB", "BP"}, {"SIB", "SI"}, {"DIB", "DI"}, {"R8B", "R8"}, {"R15B", "R15"}, + } { + const input uint64 = 0x1122334455667701 + want := ^input + if family == "NEG" { + want++ + } + if width.bits == 16 { + want = (input &^ 0xffff) | (want & 0xffff) + } + if width.bits == 32 { + want &= 0xffffffff + } + fmt.Fprintf(&source, "\tMOVQ $%#x, %s\n\t%s%s %s\n\tMOVQ %s, %d(R14)\n", input, reg.effective, family, width.suffix, reg.spelling, reg.effective, index*8) + fmt.Fprintf(&checks, " if (out[%d] != UINT64_C(%#x)) return %d;\n", index, want, index+1) + index++ + } + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, "amd64", source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple, runPrefix = "x86_64-apple-macosx", []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: triple, Sigs: map[string]FuncSig{ + "unaryaliases": {Name: "unaryaliases", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}}, + }}) + if err != nil { + t.Fatal(err) + } + mainC := fmt.Sprintf("#include \nextern void unaryaliases(uint64_t *);\nint main(void) {\n uint64_t out[%d] = {0};\n unaryaliases(out);\n%s return 0;\n}\n", index, checks.String()) + compileAndRunRuntimeTestForTarget(t, llc, clang, "unary_aliases", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_non_temporal_move.go b/amd64_lower_non_temporal_move.go new file mode 100644 index 00000000..59320c09 --- /dev/null +++ b/amd64_lower_non_temporal_move.go @@ -0,0 +1,104 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerNonTemporalVectorMove implements Go 1.27's complete vector +// non-temporal move family. The VEX/EVEX store table is shared by VMOVNTDQ, +// VMOVNTPD, and VMOVNTPS and accepts X/Y/Z register-to-memory forms. Its +// VMOVNTDQA counterpart accepts the inverse memory-to-X/Y/Z forms. The legacy +// instructions are the same directions at X width; Go spells MOVNTDQ as +// MOVNTO so that VMOVNTDQ remains available for the VEX/EVEX instruction. +func (c *amd64Ctx) lowerNonTemporalVectorMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + vectorStore, vectorLoad := false, false + legacyStore := false + switch baseOp { + case "VMOVNTDQ", "VMOVNTPD", "VMOVNTPS": + vectorStore = true + case "VMOVNTDQA": + vectorLoad = true + case "MOVNTO", "MOVNTPD", "MOVNTPS": + legacyStore = true + case "MOVNTDQA": + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed forms in Go 1.27's non-temporal vector-move tables: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects exactly two operands: %q", c.goarch, baseOp, ins.Raw) + } + + if vectorStore { + source, destination := ins.Args[0], ins.Args[1] + byteWidth := 0 + if source.Kind == OpReg { + byteWidth = amd64VectorByteWidth(source.Reg) + } + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s %s destination must be memory: %q", c.goarch, baseOp, ins.Raw) + } + value, loadErr := c.loadPackedCompareBytes(source, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + return true, false, c.storeVectorBytesOperandWithMetadata(destination, byteWidth, value, x86NonTemporalMetadata) + } + + if vectorLoad { + source, destination := ins.Args[0], ins.Args[1] + if !isAMD64MemoryOperand(source) || destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects a memory source and X, Y, or Z destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + value, loadErr := c.loadPackedCompareBytes(source, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + return true, false, c.storeVectorBytesOperand(destination, byteWidth, value) + } + + if legacyStore { + source, destination := ins.Args[0], ins.Args[1] + if !c.isGoLegacyNonTemporalVectorRegister(source) || !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s %s expects an in-range X source and memory destination: %q", c.goarch, baseOp, ins.Raw) + } + value, loadErr := c.loadPackedCompareBytes(source, 16) + if loadErr != nil { + return true, false, loadErr + } + return true, false, c.storeVectorBytesOperandWithMetadata(destination, 16, value, x86NonTemporalMetadata) + } + + source, destination := ins.Args[0], ins.Args[1] + if !isAMD64MemoryOperand(source) || !c.isGoLegacyNonTemporalVectorRegister(destination) { + return true, false, fmt.Errorf("%s %s expects a memory source and in-range X destination: %q", c.goarch, baseOp, ins.Raw) + } + value, loadErr := c.loadPackedCompareBytes(source, 16) + if loadErr != nil { + return true, false, loadErr + } + return true, false, c.storeVectorBytesOperand(destination, 16, value) +} + +func (c *amd64Ctx) isGoLegacyNonTemporalVectorRegister(operand Operand) bool { + if !amd64VEXVectorRegister(operand, 16) { + return false + } + index, _ := amd64ParseXReg(operand.Reg) + return c.goarch != "386" || index < 8 +} diff --git a/amd64_lower_non_temporal_move_test.go b/amd64_lower_non_temporal_move_test.go new file mode 100644 index 00000000..40b254f1 --- /dev/null +++ b/amd64_lower_non_temporal_move_test.go @@ -0,0 +1,147 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86NonTemporalVectorMoveCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 uses _yvmovntdq for VMOVNTDQ/PD/PS register-to-memory + // stores and _yvmovntdqa for the inverse aligned memory loads. Both + // tables cover VEX/EVEX X, Y, and Z widths. The legacy table covers the + // corresponding X-only forms (with MOVNTO as Go's MOVNTDQ spelling). + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastZ := 31 + if target.goarch == "386" { + lastZ = 7 + } + var source strings.Builder + source.WriteString("TEXT nontemporalmoveforms(SB),$0-0\n") + for index, op := range []string{"VMOVNTDQ", "VMOVNTPD", "VMOVNTPS"} { + fmt.Fprintf(&source, "\t%s X%d, %d(AX)\n", op, 20+index, index*256) + fmt.Fprintf(&source, "\t%s Y%d, %d(AX)\n", op, 20+index, index*256+64) + fmt.Fprintf(&source, "\t%s Z%d, %d(AX)\n", op, lastZ, index*256+128) + } + source.WriteString("\tVMOVNTDQA 1024(AX), X20\n") + source.WriteString("\tVMOVNTDQA 1088(AX), Y21\n") + fmt.Fprintf(&source, "\tVMOVNTDQA 1152(AX), Z%d\n", lastZ) + source.WriteString("\tMOVNTO X1, 1216(AX)\n") + source.WriteString("\tMOVNTPD X2, 1280(AX)\n") + source.WriteString("\tMOVNTPS X3, 1344(AX)\n") + source.WriteString("\tMOVNTDQA 1408(AX), X4\n") + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "nontemporalmoveforms": {Name: "nontemporalmoveforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, vectorType := range []string{"<16 x i8>", "<32 x i8>", "<64 x i8>"} { + if !strings.Contains(ir, "load "+vectorType) || !strings.Contains(ir, "store "+vectorType) { + t.Fatalf("translation omitted %s load/store forms:\n%s", vectorType, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "non-temporal-move-"+target.name+".ll", "non-temporal-move-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86NonTemporalVectorMoveRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VMOVNTDQ 8(AX), X0"}, + {goarch: "amd64", instruction: "VMOVNTPD X0, X1"}, + {goarch: "amd64", instruction: "VMOVNTPS X0, K1, 8(AX)"}, + {goarch: "amd64", instruction: "VMOVNTDQ.Z Z0, 8(AX)"}, + {goarch: "amd64", instruction: "VMOVNTDQA X0, X1"}, + {goarch: "amd64", instruction: "VMOVNTDQA 8(AX), K1, X0"}, + {goarch: "amd64", instruction: "MOVNTPD 8(AX), X0"}, + {goarch: "amd64", instruction: "MOVNTPS X0, X1"}, + {goarch: "amd64", instruction: "MOVNTDQA X0, 8(AX)"}, + {goarch: "386", instruction: "VMOVNTDQ Z8, 8(AX)"}, + {goarch: "386", instruction: "VMOVNTDQA 8(AX), Z8"}, + {goarch: "386", instruction: "MOVNTO X8, 8(AX)"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's non-temporal vector-move tables for %s", test.instruction, test.goarch) + } + }) + } +} + +func TestX86RawDecoderRecoversVEXNonTemporalVectorMoveWidths(t *testing.T) { + for _, test := range []struct { + name string + code []byte + op Op + from string + to string + }{ + {name: "vmovntdq x store", code: []byte{0xc5, 0xf9, 0xe7, 0x03}, op: "VMOVNTDQ", from: "X0", to: "0(BX)"}, + {name: "vmovntdq y store", code: []byte{0xc5, 0xfd, 0xe7, 0x03}, op: "VMOVNTDQ", from: "Y0", to: "0(BX)"}, + {name: "vmovntdq y sib store", code: []byte{0xc4, 0xa1, 0x7d, 0xe7, 0x04, 0x03}, op: "VMOVNTDQ", from: "Y0", to: "0(BX)(R8*1)"}, + {name: "vmovntpd x store", code: []byte{0xc5, 0xf9, 0x2b, 0x03}, op: "VMOVNTPD", from: "X0", to: "0(BX)"}, + {name: "vmovntpd y store", code: []byte{0xc5, 0xfd, 0x2b, 0x03}, op: "VMOVNTPD", from: "Y0", to: "0(BX)"}, + {name: "vmovntps x store", code: []byte{0xc5, 0xf8, 0x2b, 0x03}, op: "VMOVNTPS", from: "X0", to: "0(BX)"}, + {name: "vmovntps y store", code: []byte{0xc5, 0xfc, 0x2b, 0x03}, op: "VMOVNTPS", from: "Y0", to: "0(BX)"}, + {name: "vmovntdqa x load", code: []byte{0xc4, 0xe2, 0x79, 0x2a, 0x03}, op: "VMOVNTDQA", from: "0(BX)", to: "X0"}, + {name: "vmovntdqa y load", code: []byte{0xc4, 0xe2, 0x7d, 0x2a, 0x03}, op: "VMOVNTDQA", from: "0(BX)", to: "Y0"}, + } { + t.Run(test.name, func(t *testing.T) { + fn := Func{} + for _, value := range test.code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || got.Instrs[0].Op != test.op || len(got.Instrs[0].Args) != 2 || got.Instrs[0].Args[0].String() != test.from || got.Instrs[0].Args[1].String() != test.to { + t.Fatalf("decoded %#x as %#v, want %s %s, %s", test.code, got.Instrs, test.op, test.from, test.to) + } + }) + } +} diff --git a/amd64_lower_nop_width_test.go b/amd64_lower_nop_width_test.go new file mode 100644 index 00000000..1d086651 --- /dev/null +++ b/amd64_lower_nop_width_test.go @@ -0,0 +1,160 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86SizedNOPCompleteFormsSource(goarch string) string { + var source strings.Builder + source.WriteString("DATA nopdata+0(SB)/8, $1\n") + source.WriteString("GLOBL nopdata(SB), $8\n") + source.WriteString("TEXT sizednopforms(SB),$0-0\n") + for _, op := range []string{"NOPW", "NOPL"} { + fmt.Fprintf(&source, "\t%s AX\n", op) + fmt.Fprintf(&source, "\t%s SP\n", op) + fmt.Fprintf(&source, "\t%s 8(BX)\n", op) + fmt.Fprintf(&source, "\t%s nopdata(SB)\n", op) + if goarch == "amd64" { + fmt.Fprintf(&source, "\t%s R11\n", op) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86SizedNOPCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86SizedNOPCompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"sizednopforms": {Name: "sizednopforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "sized-nop-"+target.name+".ll", "sized-nop-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86SizedNOPRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "NOPW"}, + {goarch: "amd64", instruction: "NOPL $1"}, + {goarch: "amd64", instruction: "NOPW X0"}, + {goarch: "amd64", instruction: "NOPL AX, BX"}, + {goarch: "amd64", instruction: "NOPL.Z AX"}, + {goarch: "386", instruction: "NOPW R8"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's NOPW/NOPL ydivl table", test.instruction) + } + }) + } +} + +func TestAMD64SizedNOPRuntimePreservesState(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT sizednopsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVQ $0x123456789abcdef, AX + MOVL $0x7fffffff, R8 + ADDL $1, R8 + STC + NOPW AX + NOPL 4096(DI) + MOVQ AX, 0(DI) + SETCS 8(DI) + SETOS 9(DI) + SETEQ 10(DI) + SETMI 11(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "sizednopsemantics": { + Name: "sizednopsemantics", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void sizednopsemantics(uint8_t *); +int main(void) { + uint8_t out[16] = {0}; + sizednopsemantics(out); + uint64_t value; + memcpy(&value, out, sizeof(value)); + if (value != UINT64_C(0x123456789abcdef)) return 10; + if (out[8] != 1 || out[9] != 1 || out[10] != 0 || out[11] != 1) return 11; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "sized_nop_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_pack.go b/amd64_lower_pack.go new file mode 100644 index 00000000..d37ff4cd --- /dev/null +++ b/amd64_lower_pack.go @@ -0,0 +1,292 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedNarrowMode uint8 + +const ( + amd64PackedNarrowSigned amd64PackedNarrowMode = iota + amd64PackedNarrowUnsigned +) + +// lowerPackedSaturatingNarrow implements Go 1.27's complete saturating pack +// family. The legacy dword-to-word spelling is PACKSSLW; its VEX/EVEX +// counterpart follows Intel spelling and is VPACKSSDW. +func (c *amd64Ctx) lowerPackedSaturatingNarrow(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + inputBits, outputBits, mode, vector, recognized := amd64PackedNarrowProperties(baseOp) + if !recognized { + return false, false, nil + } + if !vector { + return c.lowerLegacyPackedSaturatingNarrow(baseOp, suffix, inputBits, outputBits, mode, ins) + } + return c.lowerVectorPackedSaturatingNarrow(baseOp, suffix, inputBits, outputBits, mode, ins) +} + +func amd64PackedNarrowProperties(op string) (inputBits, outputBits int, mode amd64PackedNarrowMode, vector, ok bool) { + switch op { + case "PACKSSLW": + return 32, 16, amd64PackedNarrowSigned, false, true + case "PACKSSWB": + return 16, 8, amd64PackedNarrowSigned, false, true + case "PACKUSDW": + return 32, 16, amd64PackedNarrowUnsigned, false, true + case "PACKUSWB": + return 16, 8, amd64PackedNarrowUnsigned, false, true + case "VPACKSSDW": + return 32, 16, amd64PackedNarrowSigned, true, true + case "VPACKSSWB": + return 16, 8, amd64PackedNarrowSigned, true, true + case "VPACKUSDW": + return 32, 16, amd64PackedNarrowUnsigned, true, true + case "VPACKUSWB": + return 16, 8, amd64PackedNarrowUnsigned, true, true + default: + return 0, 0, 0, false, false + } +} + +func (c *amd64Ctx) lowerLegacyPackedSaturatingNarrow(baseOp, suffix string, inputBits, outputBits int, mode amd64PackedNarrowMode, ins Instr) (bool, bool, error) { + if suffix != "" { + return true, false, fmt.Errorf("amd64 %s has no instruction suffixes in Go 1.27's legacy optab: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects packed source, packed destination: %q", baseOp, ins.Raw) + } + dst := ins.Args[1].Reg + if _, mmx := amd64ParseMReg(dst); mmx { + if baseOp == "PACKUSDW" { + return true, false, fmt.Errorf("amd64 PACKUSDW has no MMX form in Go 1.27's yxm_q4 table: %q", ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if _, ok := amd64ParseMReg(ins.Args[0].Reg); !ok { + return true, false, fmt.Errorf("amd64 %s MMX form requires an MMX source: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s MMX form requires MMX or memory source: %q", baseOp, ins.Raw) + } + firstBits, err := c.loadLegacyMMXPackedSource(ins.Args[0]) + if err != nil { + return true, false, err + } + secondBits, err := c.loadReg(dst) + if err != nil { + return true, false, err + } + inputLanes := 64 / inputBits + first := c.bitcastI64ToIntegerLanes(inputLanes, inputBits, firstBits) + second := c.bitcastI64ToIntegerLanes(inputLanes, inputBits, secondBits) + result := c.emitPackedSaturatingNarrow(8, inputBits, outputBits, mode, first, second) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to i64\n", bits, 64/outputBits, outputBits, result) + return true, false, c.storeReg(dst, "%"+bits) + } + + if !c.isGoLegacyXReg(dst) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's X-register class for %s: %q", baseOp, c.goarch, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("amd64 %s XMM form requires an X source valid for %s: %q", baseOp, c.goarch, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s XMM form requires X or memory source: %q", baseOp, ins.Raw) + } + firstBytes, err := c.loadPackedCompareBytes(ins.Args[0], 16) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(dst) + if err != nil { + return true, false, err + } + inputLanes := 128 / inputBits + first := c.bitcastVectorBytesToIntegerLanes(16, inputLanes, inputBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(16, inputLanes, inputBits, secondBytes) + result := c.emitPackedSaturatingNarrow(16, inputBits, outputBits, mode, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, 128/outputBits, outputBits, result) + return true, false, c.storeX(dst, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedSaturatingNarrow(baseOp, suffix string, inputBits, outputBits int, mode amd64PackedNarrowMode, ins Instr) (bool, bool, error) { + if c.goarch != "amd64" { + return true, false, fmt.Errorf("%s %s is absent from Go 1.27's 386 assembler forms: %q", c.goarch, baseOp, ins.Raw) + } + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("amd64 %s suffix is absent from its Go 1.27 VEX/EVEX table: %q", baseOp, ins.Raw) + } + if broadcast && inputBits != 32 { + return true, false, fmt.Errorf("amd64 %s does not enable EVEX broadcast: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 %s expects src1, src2, [K mask,] destination: %q", baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s destination must be X, Y, or Z: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("amd64 %s destination must be X, Y, or Z: %q", baseOp, ins.Raw) + } + if !amd64EVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("amd64 %s second source must match the destination width: %q", baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !amd64EVEXVectorRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("amd64 %s first source must match the destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s first source must be a vector register or memory: %q", baseOp, ins.Raw) + } + if broadcast && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory first source: %q", baseOp, ins.Raw) + } + + masked := len(ins.Args) == 4 + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s zeroing requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + var mask string + if masked { + maskArg := ins.Args[2] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + index, ok := amd64ParseKReg(maskArg.Reg) + if !ok || index == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + var err error + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + evex := masked || suffix != "" || byteWidth == 64 || !amd64VEXVectorRegister(dstArg, byteWidth) || !amd64VEXVectorRegister(ins.Args[1], byteWidth) + if ins.Args[0].Kind == OpReg && !amd64VEXVectorRegister(ins.Args[0], byteWidth) { + evex = true + } + if !evex { + if byteWidth == 64 { + return true, false, fmt.Errorf("amd64 %s has no 512-bit VEX form: %q", baseOp, ins.Raw) + } + } else if !amd64EVEXVectorRegister(dstArg, byteWidth) { + return true, false, fmt.Errorf("amd64 %s EVEX destination is invalid: %q", baseOp, ins.Raw) + } + + inputLanes := byteWidth * 8 / inputBits + var first string + var err error + if broadcast { + first, err = c.evalIntSized(ins.Args[0], amd64IntegerTypeForBits(inputBits)) + if err == nil { + first = amd64SplatInteger(c, inputLanes, inputBits, first) + } + } else { + var firstBytes string + firstBytes, err = c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err == nil { + first = c.bitcastVectorBytesToIntegerLanes(byteWidth, inputLanes, inputBits, firstBytes) + } + } + if err != nil { + return true, false, err + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + second := c.bitcastVectorBytesToIntegerLanes(byteWidth, inputLanes, inputBits, secondBytes) + result := c.emitPackedSaturatingNarrow(byteWidth, inputBits, outputBits, mode, first, second) + outputLanes := byteWidth * 8 / outputBits + if masked { + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, outputLanes, outputBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, outputLanes, outputBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, outputLanes, outputBits, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPackedSaturatingNarrow(byteWidth, inputBits, outputBits int, mode amd64PackedNarrowMode, first, second string) string { + inputLanes := byteWidth * 8 / inputBits + outputLanes := byteWidth * 8 / outputBits + chunkBits := 128 + if byteWidth < 16 { + chunkBits = byteWidth * 8 + } + inputLanesPerChunk := chunkBits / inputBits + outputLanesPerChunk := chunkBits / outputBits + chunks := byteWidth * 8 / chunkBits + result := "zeroinitializer" + for chunk := 0; chunk < chunks; chunk++ { + for sourceHalf, source := range []string{second, first} { + for lane := 0; lane < inputLanesPerChunk; lane++ { + inputIndex := chunk*inputLanesPerChunk + lane + outputIndex := chunk*outputLanesPerChunk + sourceHalf*inputLanesPerChunk + lane + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", value, inputLanes, inputBits, source, inputIndex) + narrowed := c.saturatePackedInteger("%"+value, inputBits, outputBits, mode) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %s, i32 %d\n", inserted, outputLanes, outputBits, result, outputBits, narrowed, outputIndex) + result = "%" + inserted + } + } + } + return result +} + +func (c *amd64Ctx) saturatePackedInteger(value string, inputBits, outputBits int, mode amd64PackedNarrowMode) string { + minValue := -(int64(1) << (outputBits - 1)) + maxValue := (int64(1) << (outputBits - 1)) - 1 + clamped := value + if mode == amd64PackedNarrowUnsigned { + minValue = 0 + maxValue = (int64(1) << outputBits) - 1 + below := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i%d %s, 0\n", below, inputBits, clamped) + nonnegative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d 0, i%d %s\n", nonnegative, below, inputBits, inputBits, clamped) + clamped = "%" + nonnegative + } + above := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp sgt i%d %s, %d\n", above, inputBits, clamped, maxValue) + capped := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d %s\n", capped, above, inputBits, maxValue, inputBits, clamped) + clamped = "%" + capped + if mode == amd64PackedNarrowSigned { + below := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i%d %s, %d\n", below, inputBits, clamped, minValue) + floored := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d %s\n", floored, below, inputBits, minValue, inputBits, clamped) + clamped = "%" + floored + } + narrowed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i%d %s to i%d\n", narrowed, inputBits, clamped, outputBits) + return "%" + narrowed +} diff --git a/amd64_lower_packed_float_logical.go b/amd64_lower_packed_float_logical.go new file mode 100644 index 00000000..3d4fa5da --- /dev/null +++ b/amd64_lower_packed_float_logical.go @@ -0,0 +1,179 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedFloatingLogicalSpec struct { + laneBits int + mode amd64PackedLogicalMode + vector bool +} + +// amd64PackedFloatingLogicalSpecs is the complete Go 1.27 packed floating +// logical family. The eight legacy instructions use yxm. Their V-prefixed +// counterparts use _yvandnpd, which provides the common VEX/EVEX X/Y/Z, +// masking, zeroing, and scalar-broadcast forms. +var amd64PackedFloatingLogicalSpecs = map[Op]amd64PackedFloatingLogicalSpec{ + "ANDPS": {laneBits: 32, mode: amd64PackedLogicalAnd}, + "ANDPD": {laneBits: 64, mode: amd64PackedLogicalAnd}, + "ANDNPS": {laneBits: 32, mode: amd64PackedLogicalAndNot}, + "ANDNPD": {laneBits: 64, mode: amd64PackedLogicalAndNot}, + "ORPS": {laneBits: 32, mode: amd64PackedLogicalOr}, + "ORPD": {laneBits: 64, mode: amd64PackedLogicalOr}, + "XORPS": {laneBits: 32, mode: amd64PackedLogicalXor}, + "XORPD": {laneBits: 64, mode: amd64PackedLogicalXor}, + "VANDPS": {laneBits: 32, mode: amd64PackedLogicalAnd, vector: true}, + "VANDPD": {laneBits: 64, mode: amd64PackedLogicalAnd, vector: true}, + "VANDNPS": {laneBits: 32, mode: amd64PackedLogicalAndNot, vector: true}, + "VANDNPD": {laneBits: 64, mode: amd64PackedLogicalAndNot, vector: true}, + "VORPS": {laneBits: 32, mode: amd64PackedLogicalOr, vector: true}, + "VORPD": {laneBits: 64, mode: amd64PackedLogicalOr, vector: true}, + "VXORPS": {laneBits: 32, mode: amd64PackedLogicalXor, vector: true}, + "VXORPD": {laneBits: 64, mode: amd64PackedLogicalXor, vector: true}, +} + +func (c *amd64Ctx) lowerPackedFloatingLogical(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64PackedFloatingLogicalSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if !spec.vector { + if suffix != "" { + return true, false, fmt.Errorf("%s %s has a suffix absent from Go 1.27's yxm table: %q", c.goarch, baseOp, ins.Raw) + } + return c.lowerLegacyPackedFloatingLogical(baseOp, spec, ins) + } + return c.lowerVectorPackedFloatingLogical(baseOp, suffix, spec, ins) +} + +func (c *amd64Ctx) lowerLegacyPackedFloatingLogical(baseOp string, spec amd64PackedFloatingLogicalSpec, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg || !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("%s %s expects X/m128, X using Go 1.27's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s source must be X or memory: %q", c.goarch, baseOp, ins.Raw) + } + + firstBytes, err := c.loadPackedCompareBytes(ins.Args[0], 16) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + lanes := 128 / spec.laneBits + first := c.bitcastVectorBytesToIntegerLanes(16, lanes, spec.laneBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(16, lanes, spec.laneBits, secondBytes) + result := c.emitPackedLogical(lanes, amd64PackedLogicalSpec{laneBits: spec.laneBits, mode: spec.mode}, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, lanes, spec.laneBits, result) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedFloatingLogical(baseOp, suffix string, spec amd64PackedFloatingLogicalSpec, ins Instr) (bool, bool, error) { + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s has a suffix absent from Go 1.27's _yvandnpd table: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects src1, src2, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed Go 1.27's assembler operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be an X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if (byteWidth != 16 && byteWidth != 32 && byteWidth != 64) || !c.isGoEVEXVectorRegister(dstArg, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's EVEX vector class: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoEVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s second source must be a same-width EVEX vector register: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast { + if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory first source: %q", c.goarch, baseOp, ins.Raw) + } + } else if ins.Args[0].Kind == OpReg { + if !c.isGoEVEXVectorRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match the destination width and register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + loadedMask, loadErr := c.loadK(ins.Args[2].Reg) + if loadErr != nil { + return true, false, loadErr + } + mask = loadedMask + } + + lanes := byteWidth * 8 / spec.laneBits + loadLanes := func(arg Operand, allowBroadcast bool) (string, error) { + if allowBroadcast && broadcast { + scalar, loadErr := c.evalIntSized(arg, amd64IntegerTypeForBits(spec.laneBits)) + if loadErr != nil { + return "", loadErr + } + return amd64SplatInteger(c, lanes, spec.laneBits, scalar), nil + } + bytesValue, loadErr := c.loadPackedCompareBytes(arg, byteWidth) + if loadErr != nil { + return "", loadErr + } + return c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, bytesValue), nil + } + first, err := loadLanes(ins.Args[0], true) + if err != nil { + return true, false, err + } + second, err := loadLanes(ins.Args[1], false) + if err != nil { + return true, false, err + } + result := c.emitPackedLogical(lanes, amd64PackedLogicalSpec{laneBits: spec.laneBits, mode: spec.mode}, first, second) + if masked { + oldBytes, loadErr := c.loadPackedCompareBytes(dstArg, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} diff --git a/amd64_lower_packed_logical.go b/amd64_lower_packed_logical.go new file mode 100644 index 00000000..7a005ccc --- /dev/null +++ b/amd64_lower_packed_logical.go @@ -0,0 +1,169 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedLogicalMode uint8 + +const ( + amd64PackedLogicalAnd amd64PackedLogicalMode = iota + amd64PackedLogicalAndNot + amd64PackedLogicalOr + amd64PackedLogicalXor +) + +type amd64PackedLogicalSpec struct { + laneBits int + mode amd64PackedLogicalMode +} + +// amd64EVEXPackedLogicalSpecs is the complete Go 1.27 _yvblendmpd logical +// family. All eight instructions have identical X/Y/Z operand rows and differ +// only in lane width and Boolean operation. +var amd64EVEXPackedLogicalSpecs = map[Op]amd64PackedLogicalSpec{ + "VPANDD": {laneBits: 32, mode: amd64PackedLogicalAnd}, + "VPANDQ": {laneBits: 64, mode: amd64PackedLogicalAnd}, + "VPANDND": {laneBits: 32, mode: amd64PackedLogicalAndNot}, + "VPANDNQ": {laneBits: 64, mode: amd64PackedLogicalAndNot}, + "VPORD": {laneBits: 32, mode: amd64PackedLogicalOr}, + "VPORQ": {laneBits: 64, mode: amd64PackedLogicalOr}, + "VPXORD": {laneBits: 32, mode: amd64PackedLogicalXor}, + "VPXORQ": {laneBits: 64, mode: amd64PackedLogicalXor}, +} + +func (c *amd64Ctx) lowerEVEXPackedLogical(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64EVEXPackedLogicalSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s has a suffix absent from Go 1.27's EVEX encoding: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects src1, src2, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed Go 1.27's assembler operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be an X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if (byteWidth != 16 && byteWidth != 32 && byteWidth != 64) || !c.isGoEVEXVectorRegister(dstArg, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's EVEX vector class: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoEVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s second source must be a same-width EVEX vector register: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast { + if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory first source: %q", c.goarch, baseOp, ins.Raw) + } + } else if ins.Args[0].Kind == OpReg { + if !c.isGoEVEXVectorRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match the destination width and register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + } + + lanes := byteWidth * 8 / spec.laneBits + loadLanes := func(arg Operand, allowBroadcast bool) (string, error) { + if allowBroadcast && broadcast { + scalar, loadErr := c.evalIntSized(arg, amd64IntegerTypeForBits(spec.laneBits)) + if loadErr != nil { + return "", loadErr + } + return amd64SplatInteger(c, lanes, spec.laneBits, scalar), nil + } + bytesValue, loadErr := c.loadPackedCompareBytes(arg, byteWidth) + if loadErr != nil { + return "", loadErr + } + return c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, bytesValue), nil + } + first, err := loadLanes(ins.Args[0], true) + if err != nil { + return true, false, err + } + second, err := loadLanes(ins.Args[1], false) + if err != nil { + return true, false, err + } + result := c.emitPackedLogical(lanes, spec, first, second) + if masked { + oldBytes, loadErr := c.loadPackedCompareBytes(dstArg, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPackedLogical(lanes int, spec amd64PackedLogicalSpec, first, second string) string { + vectorType := fmt.Sprintf("<%d x i%d>", lanes, spec.laneBits) + if spec.mode == amd64PackedLogicalAndNot { + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, %s\n", inverted, vectorType, second, llvmSplatInteger(lanes, spec.laneBits, ^uint64(0))) + second = "%" + inverted + } + result := c.newTmp() + llvmOp := "and" + switch spec.mode { + case amd64PackedLogicalOr: + llvmOp = "or" + case amd64PackedLogicalXor: + llvmOp = "xor" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", result, llvmOp, vectorType, second, first) + return "%" + result +} + +func (c *amd64Ctx) isGoEVEXVectorRegister(op Operand, byteWidth int) bool { + if !amd64EVEXVectorRegister(op, byteWidth) { + return false + } + if c.goarch != "386" || byteWidth != 64 { + return true + } + index, _ := amd64VectorRegisterIndex(op.Reg, byteWidth) + return index < 8 +} diff --git a/amd64_lower_packed_numeric_conversion.go b/amd64_lower_packed_numeric_conversion.go new file mode 100644 index 00000000..b84f3ba9 --- /dev/null +++ b/amd64_lower_packed_numeric_conversion.go @@ -0,0 +1,428 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedNumericKind uint8 + +const ( + amd64PackedNumericFloat amd64PackedNumericKind = iota + amd64PackedNumericSigned + amd64PackedNumericUnsigned +) + +type amd64PackedNumericShape struct { + sourceBytes int + destinationBytes int + lanes int +} + +type amd64PackedNumericConversionSpec struct { + sourceKind amd64PackedNumericKind + destinationKind amd64PackedNumericKind + sourceBits int + destinationBits int + truncate bool + explicit string + shapes []amd64PackedNumericShape +} + +var ( + amd64PackedNumericSame32 = []amd64PackedNumericShape{ + {sourceBytes: 16, destinationBytes: 16, lanes: 4}, + {sourceBytes: 32, destinationBytes: 32, lanes: 8}, + {sourceBytes: 64, destinationBytes: 64, lanes: 16}, + } + amd64PackedNumericSame64 = []amd64PackedNumericShape{ + {sourceBytes: 16, destinationBytes: 16, lanes: 2}, + {sourceBytes: 32, destinationBytes: 32, lanes: 4}, + {sourceBytes: 64, destinationBytes: 64, lanes: 8}, + } + amd64PackedNumericWiden32To64 = []amd64PackedNumericShape{ + {sourceBytes: 16, destinationBytes: 16, lanes: 2}, + {sourceBytes: 16, destinationBytes: 32, lanes: 4}, + {sourceBytes: 32, destinationBytes: 64, lanes: 8}, + } +) + +// amd64PackedNumericConversionSpecs describes the complete Go 1.27 EVEX +// packed numeric-conversion family not covered by the legacy/VEX conversion +// handlers. Source/destination element types and physical width shapes remain +// independent axes, avoiding one lowerer per mnemonic and register width. +var amd64PackedNumericConversionSpecs = map[Op]amd64PackedNumericConversionSpec{ + "VCVTPD2QQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericSigned, sourceBits: 64, destinationBits: 64, explicit: "round", shapes: amd64PackedNumericSame64}, + "VCVTPD2UQQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 64, destinationBits: 64, explicit: "round", shapes: amd64PackedNumericSame64}, + "VCVTTPD2QQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericSigned, sourceBits: 64, destinationBits: 64, truncate: true, explicit: "sae", shapes: amd64PackedNumericSame64}, + "VCVTTPD2UQQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 64, destinationBits: 64, truncate: true, explicit: "sae", shapes: amd64PackedNumericSame64}, + "VCVTPS2UDQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 32, destinationBits: 32, explicit: "round", shapes: amd64PackedNumericSame32}, + "VCVTTPS2UDQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 32, destinationBits: 32, truncate: true, explicit: "sae", shapes: amd64PackedNumericSame32}, + "VCVTUDQ2PS": {sourceKind: amd64PackedNumericUnsigned, destinationKind: amd64PackedNumericFloat, sourceBits: 32, destinationBits: 32, explicit: "round", shapes: amd64PackedNumericSame32}, + "VCVTQQ2PD": {sourceKind: amd64PackedNumericSigned, destinationKind: amd64PackedNumericFloat, sourceBits: 64, destinationBits: 64, explicit: "round", shapes: amd64PackedNumericSame64}, + "VCVTUQQ2PD": {sourceKind: amd64PackedNumericUnsigned, destinationKind: amd64PackedNumericFloat, sourceBits: 64, destinationBits: 64, explicit: "round", shapes: amd64PackedNumericSame64}, + "VCVTPS2QQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericSigned, sourceBits: 32, destinationBits: 64, explicit: "round", shapes: amd64PackedNumericWiden32To64}, + "VCVTPS2UQQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 32, destinationBits: 64, explicit: "round", shapes: amd64PackedNumericWiden32To64}, + "VCVTTPS2QQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericSigned, sourceBits: 32, destinationBits: 64, truncate: true, explicit: "sae", shapes: amd64PackedNumericWiden32To64}, + "VCVTTPS2UQQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 32, destinationBits: 64, truncate: true, explicit: "sae", shapes: amd64PackedNumericWiden32To64}, + "VCVTUDQ2PD": {sourceKind: amd64PackedNumericUnsigned, destinationKind: amd64PackedNumericFloat, sourceBits: 32, destinationBits: 64, shapes: amd64PackedNumericWiden32To64}, + "VCVTPD2UDQX": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 64, destinationBits: 32, shapes: []amd64PackedNumericShape{{sourceBytes: 16, destinationBytes: 16, lanes: 2}}}, + "VCVTPD2UDQY": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 64, destinationBits: 32, shapes: []amd64PackedNumericShape{{sourceBytes: 32, destinationBytes: 16, lanes: 4}}}, + "VCVTPD2UDQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 64, destinationBits: 32, explicit: "round", shapes: []amd64PackedNumericShape{{sourceBytes: 64, destinationBytes: 32, lanes: 8}}}, + "VCVTTPD2UDQX": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 64, destinationBits: 32, truncate: true, shapes: []amd64PackedNumericShape{{sourceBytes: 16, destinationBytes: 16, lanes: 2}}}, + "VCVTTPD2UDQY": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 64, destinationBits: 32, truncate: true, shapes: []amd64PackedNumericShape{{sourceBytes: 32, destinationBytes: 16, lanes: 4}}}, + "VCVTTPD2UDQ": {sourceKind: amd64PackedNumericFloat, destinationKind: amd64PackedNumericUnsigned, sourceBits: 64, destinationBits: 32, truncate: true, explicit: "sae", shapes: []amd64PackedNumericShape{{sourceBytes: 64, destinationBytes: 32, lanes: 8}}}, + "VCVTQQ2PSX": {sourceKind: amd64PackedNumericSigned, destinationKind: amd64PackedNumericFloat, sourceBits: 64, destinationBits: 32, shapes: []amd64PackedNumericShape{{sourceBytes: 16, destinationBytes: 16, lanes: 2}}}, + "VCVTQQ2PSY": {sourceKind: amd64PackedNumericSigned, destinationKind: amd64PackedNumericFloat, sourceBits: 64, destinationBits: 32, shapes: []amd64PackedNumericShape{{sourceBytes: 32, destinationBytes: 16, lanes: 4}}}, + "VCVTQQ2PS": {sourceKind: amd64PackedNumericSigned, destinationKind: amd64PackedNumericFloat, sourceBits: 64, destinationBits: 32, explicit: "round", shapes: []amd64PackedNumericShape{{sourceBytes: 64, destinationBytes: 32, lanes: 8}}}, + "VCVTUQQ2PSX": {sourceKind: amd64PackedNumericUnsigned, destinationKind: amd64PackedNumericFloat, sourceBits: 64, destinationBits: 32, shapes: []amd64PackedNumericShape{{sourceBytes: 16, destinationBytes: 16, lanes: 2}}}, + "VCVTUQQ2PSY": {sourceKind: amd64PackedNumericUnsigned, destinationKind: amd64PackedNumericFloat, sourceBits: 64, destinationBits: 32, shapes: []amd64PackedNumericShape{{sourceBytes: 32, destinationBytes: 16, lanes: 4}}}, + "VCVTUQQ2PS": {sourceKind: amd64PackedNumericUnsigned, destinationKind: amd64PackedNumericFloat, sourceBits: 64, destinationBits: 32, explicit: "round", shapes: []amd64PackedNumericShape{{sourceBytes: 64, destinationBytes: 32, lanes: 8}}}, +} + +type amd64PackedNumericForm struct { + properties amd64BinaryFloatingSuffix + shape amd64PackedNumericShape + source Operand + destination Operand + mask string +} + +func (c *amd64Ctx) lowerPackedNumericConversion(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64PackedNumericConversionSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + form, err := c.parsePackedNumericConversionForm(baseOp, suffix, spec, ins) + if err != nil { + return true, false, err + } + source, err := c.loadPackedNumericConversionSource(spec, form) + if err != nil { + return true, false, err + } + computed := c.emitPackedNumericConversion(spec, form.shape.lanes, source, form.properties.rounding) + if form.mask != "" { + oldBytes, loadErr := c.loadPackedCompareBytes(form.destination, form.shape.destinationBytes) + if loadErr != nil { + return true, false, loadErr + } + physicalLanes := form.shape.destinationBytes * 8 / spec.destinationBits + old := c.bitcastVectorBytesToIntegerLanes(form.shape.destinationBytes, physicalLanes, spec.destinationBits, oldBytes) + if physicalLanes != form.shape.lanes { + old = c.lowIntegerLanes(old, physicalLanes, form.shape.lanes, spec.destinationBits) + } + computed = amd64ApplyIntegerLaneMask(c, form.shape.lanes, spec.destinationBits, computed, old, form.mask, form.properties.zeroing) + } + return true, false, c.storePackedNumericConversionResult(form.destination.Reg, form.shape.destinationBytes, form.shape.lanes, spec.destinationBits, computed) +} + +func (c *amd64Ctx) parsePackedNumericConversionForm(baseOp, suffix string, spec amd64PackedNumericConversionSpec, ins Instr) (amd64PackedNumericForm, error) { + var form amd64PackedNumericForm + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix { + return form, fmt.Errorf("%s %s has a suffix absent from Go 1.27's packed conversion optabs: %q", c.goarch, baseOp, ins.Raw) + } + if properties.rounding != "" && spec.explicit != "round" { + return form, fmt.Errorf("%s %s does not enable explicit rounding: %q", c.goarch, baseOp, ins.Raw) + } + if properties.sae && spec.explicit != "sae" { + return form, fmt.Errorf("%s %s does not enable SAE: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return form, fmt.Errorf("%s %s expects source, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if properties.zeroing && !masked { + return form, fmt.Errorf("%s %s zeroing requires K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[1]) { + return form, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return form, fmt.Errorf("%s %s destination must be a vector register: %q", c.goarch, baseOp, ins.Raw) + } + destinationBytes := amd64VectorByteWidth(destination.Reg) + var shape amd64PackedNumericShape + shapeFound := false + for _, candidate := range spec.shapes { + if candidate.destinationBytes == destinationBytes { + shape, shapeFound = candidate, true + break + } + } + if !shapeFound || !c.isGoEVEXVectorRegister(destination, destinationBytes) { + return form, fmt.Errorf("%s %s destination does not match its typed width shapes: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[0] + if properties.broadcast { + if !isAMD64MemoryOperand(source) { + return form, fmt.Errorf("%s %s.BCST requires scalar memory: %q", c.goarch, baseOp, ins.Raw) + } + } else if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, shape.sourceBytes) { + return form, fmt.Errorf("%s %s source register does not match its typed width shape: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return form, fmt.Errorf("%s %s source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + explicit := properties.rounding != "" || properties.sae + if explicit && (source.Kind != OpReg || shape != spec.shapes[len(spec.shapes)-1]) { + return form, fmt.Errorf("%s %s explicit rounding/SAE requires its maximum-width register form: %q", c.goarch, baseOp, ins.Raw) + } + mask := "" + if masked { + loadedMask, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return form, err + } + mask = loadedMask + } + return amd64PackedNumericForm{properties: properties, shape: shape, source: source, destination: destination, mask: mask}, nil +} + +func (c *amd64Ctx) loadPackedNumericConversionSource(spec amd64PackedNumericConversionSpec, form amd64PackedNumericForm) (string, error) { + if form.properties.broadcast { + value, err := c.evalIntSized(form.source, amd64IntegerTypeForBits(spec.sourceBits)) + if err != nil { + return "", err + } + return amd64SplatInteger(c, form.shape.lanes, spec.sourceBits, value), nil + } + return c.loadPackedExtendInputs(form.source, form.shape.sourceBytes, form.shape.lanes, spec.sourceBits) +} + +func (c *amd64Ctx) emitPackedNumericConversion(spec amd64PackedNumericConversionSpec, lanes int, source, rounding string) string { + if spec.destinationKind == amd64PackedNumericFloat { + return c.emitPackedIntegerToFloating(spec, lanes, source, rounding) + } + return c.emitPackedFloatingToInteger(spec, lanes, source, rounding) +} + +func (c *amd64Ctx) emitPackedIntegerToFloating(spec amd64PackedNumericConversionSpec, lanes int, source, rounding string) string { + sourceType := fmt.Sprintf("<%d x i%d>", lanes, spec.sourceBits) + roundingMode := c.packedNumericRoundingMode(rounding) + result := "poison" + for lane := 0; lane < lanes; lane++ { + value, inserted := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", value, sourceType, source, lane) + bits := c.emitPackedIntegerToFloatingLane(spec, "%"+value, roundingMode) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %s, i32 %d\n", inserted, lanes, spec.destinationBits, result, spec.destinationBits, bits, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) packedNumericRoundingMode(rounding string) string { + switch rounding { + case "RN_SAE": + return "0" + case "RD_SAE": + return "1" + case "RU_SAE": + return "2" + case "RZ_SAE": + return "3" + default: + mxcsr := c.loadMXCSR() + shifted, mode := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i32 %s, 13\n", shifted, mxcsr) + fmt.Fprintf(c.b, " %%%s = and i32 %%%s, 3\n", mode, shifted) + return "%" + mode + } +} + +// emitPackedIntegerToFloatingLane constructs IEEE-754 bits directly. LLVM 22 +// lowers constrained integer-to-floating conversions to instructions that use +// MXCSR even when fixed rounding metadata is present, so relying on those +// intrinsics would silently miscompile EVEX {rn,rd,ru,rz}-sae forms. +func (c *amd64Ctx) emitPackedIntegerToFloatingLane(spec amd64PackedNumericConversionSpec, value, roundingMode string) string { + negative := "false" + magnitudeSource := value + if spec.sourceKind == amd64PackedNumericSigned { + isNegative, negated, magnitude := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i%d %s, 0\n", isNegative, spec.sourceBits, value) + fmt.Fprintf(c.b, " %%%s = sub i%d 0, %s\n", negated, spec.sourceBits, value) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %s\n", magnitude, isNegative, spec.sourceBits, negated, spec.sourceBits, value) + negative = "%" + isNegative + magnitudeSource = "%" + magnitude + } + magnitude := magnitudeSource + if spec.sourceBits != 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i%d %s to i64\n", wide, spec.sourceBits, magnitudeSource) + magnitude = "%" + wide + } + + zero, leadingZeros, highest := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i64 %s, 0\n", zero, magnitude) + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.ctlz.i64(i64 %s, i1 false)\n", leadingZeros, magnitude) + fmt.Fprintf(c.b, " %%%s = sub i64 63, %%%s\n", highest, leadingZeros) + + mantissaBits := 23 + bias := 127 + if spec.destinationBits == 64 { + mantissaBits = 52 + bias = 1023 + } + needsRound, rightShiftRaw, safeRightShift := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp sgt i64 %%%s, %d\n", needsRound, highest, mantissaBits) + fmt.Fprintf(c.b, " %%%s = sub i64 %%%s, %d\n", rightShiftRaw, highest, mantissaBits) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 0\n", safeRightShift, needsRound, rightShiftRaw) + leftShiftRaw, safeLeftShift := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i64 %d, %%%s\n", leftShiftRaw, mantissaBits, highest) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 0, i64 %%%s\n", safeLeftShift, needsRound, leftShiftRaw) + shiftedRight, shiftedLeft, unrounded := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i64 %s, %%%s\n", shiftedRight, magnitude, safeRightShift) + fmt.Fprintf(c.b, " %%%s = shl i64 %s, %%%s\n", shiftedLeft, magnitude, safeLeftShift) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 %%%s\n", unrounded, needsRound, shiftedRight, shiftedLeft) + + oneShifted, remainderMask, remainder, remainderPresent := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i64 1, %%%s\n", oneShifted, safeRightShift) + fmt.Fprintf(c.b, " %%%s = sub i64 %%%s, 1\n", remainderMask, oneShifted) + fmt.Fprintf(c.b, " %%%s = and i64 %s, %%%s\n", remainder, magnitude, remainderMask) + fmt.Fprintf(c.b, " %%%s = icmp ne i64 %%%s, 0\n", remainderPresent, remainder) + nonzero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", nonzero, needsRound, remainderPresent) + halfShiftRaw, safeHalfShift, half := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i64 %%%s, 1\n", halfShiftRaw, safeRightShift) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 0\n", safeHalfShift, needsRound, halfShiftRaw) + fmt.Fprintf(c.b, " %%%s = shl i64 1, %%%s\n", half, safeHalfShift) + aboveHalf, equalHalf, lowBit, odd, tiedOdd := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ugt i64 %%%s, %%%s\n", aboveHalf, remainder, half) + fmt.Fprintf(c.b, " %%%s = icmp eq i64 %%%s, %%%s\n", equalHalf, remainder, half) + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, 1\n", lowBit, unrounded) + fmt.Fprintf(c.b, " %%%s = icmp ne i64 %%%s, 0\n", odd, lowBit) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", tiedOdd, equalHalf, odd) + nearestRaw, nearest := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", nearestRaw, aboveHalf, tiedOdd) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", nearest, needsRound, nearestRaw) + increment := c.emitScaledRoundIncrement(roundingMode, negative, "%"+nonzero, "%"+nearest) + increment64, rounded := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %s to i64\n", increment64, increment) + fmt.Fprintf(c.b, " %%%s = add i64 %%%s, %%%s\n", rounded, unrounded, increment64) + + carryThreshold := uint64(1) << (mantissaBits + 1) + carry, carried, significand := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i64 %%%s, %d\n", carry, rounded, carryThreshold) + fmt.Fprintf(c.b, " %%%s = lshr i64 %%%s, 1\n", carried, rounded) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 %%%s\n", significand, carry, carried, rounded) + carry64, effectiveHighest, biasedExponent, exponentBits := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to i64\n", carry64, carry) + fmt.Fprintf(c.b, " %%%s = add i64 %%%s, %%%s\n", effectiveHighest, highest, carry64) + fmt.Fprintf(c.b, " %%%s = add i64 %%%s, %d\n", biasedExponent, effectiveHighest, bias) + fmt.Fprintf(c.b, " %%%s = shl i64 %%%s, %d\n", exponentBits, biasedExponent, mantissaBits) + mantissaMask := (uint64(1) << mantissaBits) - 1 + fraction, magnitudeBits := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, %d\n", fraction, significand, mantissaMask) + fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", magnitudeBits, exponentBits, fraction) + assembled := "%" + magnitudeBits + if spec.sourceKind == amd64PackedNumericSigned { + signBits, signedBits := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i64 %d, i64 0\n", signBits, negative, uint64(1)<<(spec.destinationBits-1)) + fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", signedBits, magnitudeBits, signBits) + assembled = "%" + signedBits + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 0, i64 %s\n", selected, zero, assembled) + if spec.destinationBits == 64 { + return "%" + selected + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", result, selected) + return "%" + result +} + +func (c *amd64Ctx) emitPackedFloatingToInteger(spec amd64PackedNumericConversionSpec, lanes int, source, rounding string) string { + sourceIntegerType := fmt.Sprintf("<%d x i%d>", lanes, spec.sourceBits) + sourceFloatType := amd64FloatingVectorType(lanes, spec.sourceBits) + floating := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", floating, sourceIntegerType, source, sourceFloatType) + result := "poison" + floatType := amd64FloatingScalarType(spec.sourceBits) + for lane := 0; lane < lanes; lane++ { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", value, sourceFloatType, floating, lane) + rounded := c.emitPackedNumericRoundedValue(floatType, spec.sourceBits, "%"+value, spec.truncate, rounding) + conversion := "fptosi" + if spec.destinationKind == amd64PackedNumericUnsigned { + conversion = "fptoui" + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i%d @llvm.%s.sat.i%d.f%d(%s %s)\n", converted, spec.destinationBits, conversion, spec.destinationBits, spec.sourceBits, floatType, rounded) + valid := c.emitPackedNumericIntegerRangeCheck(spec, floatType, rounded) + indefinite := uint64(1) << (spec.destinationBits - 1) + if spec.destinationKind == amd64PackedNumericUnsigned { + if spec.destinationBits == 64 { + indefinite = ^uint64(0) + } else { + indefinite = (uint64(1) << spec.destinationBits) - 1 + } + } + selected, inserted := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %d\n", selected, valid, spec.destinationBits, converted, spec.destinationBits, indefinite) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", inserted, lanes, spec.destinationBits, result, spec.destinationBits, selected, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) emitPackedNumericRoundedValue(floatType string, sourceBits int, value string, truncate bool, rounding string) string { + intrinsic := "rint" + switch { + case truncate || rounding == "RZ_SAE": + intrinsic = "trunc" + case rounding == "RN_SAE": + intrinsic = "roundeven" + case rounding == "RD_SAE": + intrinsic = "floor" + case rounding == "RU_SAE": + intrinsic = "ceil" + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.f%d(%s %s)\n", result, floatType, intrinsic, sourceBits, floatType, value) + return "%" + result +} + +func (c *amd64Ctx) emitPackedNumericIntegerRangeCheck(spec amd64PackedNumericConversionSpec, floatType, rounded string) string { + lowerBound, upperBound := "0.000000e+00", "4.294967296000000e+09" + if spec.destinationBits == 64 { + upperBound = "1.8446744073709552e+19" + } + if spec.destinationKind == amd64PackedNumericSigned { + lowerBound, upperBound = "-2.147483648000000e+09", "2.147483648000000e+09" + if spec.destinationBits == 64 { + lowerBound, upperBound = "-9.2233720368547758e+18", "9.2233720368547758e+18" + } + } + lower, upper, valid := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp oge %s %s, %s\n", lower, floatType, rounded, lowerBound) + fmt.Fprintf(c.b, " %%%s = fcmp olt %s %s, %s\n", upper, floatType, rounded, upperBound) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", valid, lower, upper) + return "%" + valid +} + +func (c *amd64Ctx) storePackedNumericConversionResult(destination Reg, destinationBytes, resultLanes, laneBits int, result string) error { + physicalLanes := destinationBytes * 8 / laneBits + if physicalLanes != resultLanes { + widened := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %s, <%d x i%d> zeroinitializer, <%d x i32> <", widened, resultLanes, laneBits, result, resultLanes, laneBits, physicalLanes) + for lane := 0; lane < physicalLanes; lane++ { + if lane != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", lane) + } + c.b.WriteString(">\n") + result = "%" + widened + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, physicalLanes, laneBits, result, destinationBytes) + return c.storeVectorBytes(destination, destinationBytes, "%"+out) +} diff --git a/amd64_lower_packed_numeric_conversion_test.go b/amd64_lower_packed_numeric_conversion_test.go new file mode 100644 index 00000000..43742d3f --- /dev/null +++ b/amd64_lower_packed_numeric_conversion_test.go @@ -0,0 +1,312 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +type packedNumericConversionTestShape struct { + source string + destination string +} + +type packedNumericConversionTestSpec struct { + op string + shapes []packedNumericConversionTestShape + explicit string +} + +func go127PackedNumericConversionSpecs() []packedNumericConversionTestSpec { + same := []packedNumericConversionTestShape{{"X", "X"}, {"Y", "Y"}, {"Z", "Z"}} + widen := []packedNumericConversionTestShape{{"X", "X"}, {"X", "Y"}, {"Y", "Z"}} + return []packedNumericConversionTestSpec{ + {op: "VCVTPD2QQ", shapes: same, explicit: "round"}, + {op: "VCVTPD2UQQ", shapes: same, explicit: "round"}, + {op: "VCVTTPD2QQ", shapes: same, explicit: "sae"}, + {op: "VCVTTPD2UQQ", shapes: same, explicit: "sae"}, + {op: "VCVTPS2UDQ", shapes: same, explicit: "round"}, + {op: "VCVTTPS2UDQ", shapes: same, explicit: "sae"}, + {op: "VCVTUDQ2PS", shapes: same, explicit: "round"}, + {op: "VCVTQQ2PD", shapes: same, explicit: "round"}, + {op: "VCVTUQQ2PD", shapes: same, explicit: "round"}, + {op: "VCVTPS2QQ", shapes: widen, explicit: "round"}, + {op: "VCVTPS2UQQ", shapes: widen, explicit: "round"}, + {op: "VCVTTPS2QQ", shapes: widen, explicit: "sae"}, + {op: "VCVTTPS2UQQ", shapes: widen, explicit: "sae"}, + {op: "VCVTUDQ2PD", shapes: widen}, + {op: "VCVTPD2UDQX", shapes: []packedNumericConversionTestShape{{"X", "X"}}}, + {op: "VCVTPD2UDQY", shapes: []packedNumericConversionTestShape{{"Y", "X"}}}, + {op: "VCVTPD2UDQ", shapes: []packedNumericConversionTestShape{{"Z", "Y"}}, explicit: "round"}, + {op: "VCVTTPD2UDQX", shapes: []packedNumericConversionTestShape{{"X", "X"}}}, + {op: "VCVTTPD2UDQY", shapes: []packedNumericConversionTestShape{{"Y", "X"}}}, + {op: "VCVTTPD2UDQ", shapes: []packedNumericConversionTestShape{{"Z", "Y"}}, explicit: "sae"}, + {op: "VCVTQQ2PSX", shapes: []packedNumericConversionTestShape{{"X", "X"}}}, + {op: "VCVTQQ2PSY", shapes: []packedNumericConversionTestShape{{"Y", "X"}}}, + {op: "VCVTQQ2PS", shapes: []packedNumericConversionTestShape{{"Z", "Y"}}, explicit: "round"}, + {op: "VCVTUQQ2PSX", shapes: []packedNumericConversionTestShape{{"X", "X"}}}, + {op: "VCVTUQQ2PSY", shapes: []packedNumericConversionTestShape{{"Y", "X"}}}, + {op: "VCVTUQQ2PS", shapes: []packedNumericConversionTestShape{{"Z", "Y"}}, explicit: "round"}, + } +} + +func TestAMD64PackedNumericConversionGrammarCoversCompleteGoFamily(t *testing.T) { + expected := go127PackedNumericConversionSpecs() + if len(amd64PackedNumericConversionSpecs) != len(expected) { + t.Fatalf("packed numeric conversion grammar has %d entries, want %d", len(amd64PackedNumericConversionSpecs), len(expected)) + } + for _, want := range expected { + if _, ok := amd64PackedNumericConversionSpecs[Op(want.op)]; !ok { + t.Errorf("packed numeric conversion grammar omitted %s", want.op) + } + } +} + +func TestTranslateX86PackedNumericConversionCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + last := 23 + if target.goarch == "386" { + last = 7 + } + var source strings.Builder + source.WriteString("TEXT packednumericconversionforms(SB),$0-0\n") + for index, spec := range go127PackedNumericConversionSpecs() { + for _, shape := range spec.shapes { + fmt.Fprintf(&source, "\t%s %s1, %s%d\n", spec.op, shape.source, shape.destination, last) + fmt.Fprintf(&source, "\t%s %d(AX), %s%d\n", spec.op, 8+index*8, shape.destination, last) + fmt.Fprintf(&source, "\t%s.BCST %d(AX), %s%d\n", spec.op, 16+index*8, shape.destination, last) + fmt.Fprintf(&source, "\t%s %s2, K1, %s%d\n", spec.op, shape.source, shape.destination, last) + fmt.Fprintf(&source, "\t%s.Z %d(AX), K2, %s%d\n", spec.op, 24+index*8, shape.destination, last) + fmt.Fprintf(&source, "\t%s.BCST.Z %d(AX), K3, %s%d\n", spec.op, 32+index*8, shape.destination, last) + } + if spec.explicit == "round" { + shape := spec.shapes[len(spec.shapes)-1] + for _, rounding := range []string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"} { + fmt.Fprintf(&source, "\t%s.%s %s3, %s%d\n", spec.op, rounding, shape.source, shape.destination, last) + } + fmt.Fprintf(&source, "\t%s.RN_SAE.Z %s4, K4, %s%d\n", spec.op, shape.source, shape.destination, last) + } else if spec.explicit == "sae" { + shape := spec.shapes[len(spec.shapes)-1] + fmt.Fprintf(&source, "\t%s.SAE %s3, %s%d\n", spec.op, shape.source, shape.destination, last) + fmt.Fprintf(&source, "\t%s.SAE.Z %s4, K4, %s%d\n", spec.op, shape.source, shape.destination, last) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"packednumericconversionforms": {Name: "packednumericconversionforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-numeric-conversion-"+target.name+".ll", "packed-numeric-conversion-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86PackedNumericConversionRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VCVTPD2QQ X0"}, + {goarch: "amd64", instruction: "VCVTPD2QQ X0, Y1"}, + {goarch: "amd64", instruction: "VCVTPS2QQ Y0, Y1"}, + {goarch: "amd64", instruction: "VCVTUDQ2PD Y0, Y1"}, + {goarch: "amd64", instruction: "VCVTPD2UDQX Y0, X1"}, + {goarch: "amd64", instruction: "VCVTPD2UDQY X0, X1"}, + {goarch: "amd64", instruction: "VCVTPD2UDQ Z0, Z1"}, + {goarch: "amd64", instruction: "VCVTQQ2PSX X0, Y1"}, + {goarch: "amd64", instruction: "VCVTQQ2PSY X0, X1"}, + {goarch: "amd64", instruction: "VCVTQQ2PS Z0, Z1"}, + {goarch: "amd64", instruction: "VCVTUDQ2PS.Z X0, X1"}, + {goarch: "amd64", instruction: "VCVTUDQ2PS X0, K0, X1"}, + {goarch: "amd64", instruction: "VCVTUDQ2PS.BCST X0, X1"}, + {goarch: "amd64", instruction: "VCVTPD2QQ.RN_SAE Y0, Y1"}, + {goarch: "amd64", instruction: "VCVTPD2QQ.RN_SAE 0(AX), Z1"}, + {goarch: "amd64", instruction: "VCVTTPD2QQ.RN_SAE Z0, Z1"}, + {goarch: "amd64", instruction: "VCVTPD2UDQX.RN_SAE X0, X1"}, + {goarch: "386", instruction: "VCVTPD2QQ Z8, Z1"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed numeric conversion tables", test.instruction) + } + }) + } +} + +func TestAMD64PackedNumericConversionRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT packednumericconversionsemantics(SB),$0-64 + MOVQ out+0(FP), AX + MOVQ f64+8(FP), BX + MOVQ f32+16(FP), CX + MOVQ u32+24(FP), DX + MOVQ i64+32(FP), R8 + MOVQ u64+40(FP), R9 + MOVQ old64+48(FP), R10 + MOVQ mask+56(FP), R11 + KMOVQ R11, K1 + VMOVDQU64 0(BX), Z0 + VCVTPD2QQ Z0, Z1 + VMOVDQU64 Z1, 0(AX) + VCVTPD2UQQ Z0, Z2 + VMOVDQU64 Z2, 64(AX) + VCVTPD2QQ.RU_SAE Z0, Z1 + VMOVDQU64 Z1, 128(AX) + VCVTTPD2UQQ.SAE Z0, Z2 + VMOVDQU64 Z2, 192(AX) + VMOVDQU32 0(CX), Y3 + VCVTPS2QQ Y3, Z4 + VMOVDQU64 Z4, 256(AX) + VCVTTPS2UQQ Y3, Z5 + VMOVDQU64 Z5, 320(AX) + VMOVDQU32 0(CX), Z6 + VCVTPS2UDQ.BCST 0(CX), Z7 + VMOVDQU32 Z7, 384(AX) + VCVTTPS2UDQ Z6, Z7 + VMOVDQU32 Z7, 448(AX) + VMOVDQU32 0(DX), Z8 + VCVTUDQ2PS Z8, Z9 + VMOVDQU32 Z9, 512(AX) + VCVTUDQ2PS.RD_SAE Z8, Z9 + VMOVDQU32 Z9, 576(AX) + VCVTUDQ2PD 0(DX), Z10 + VMOVDQU64 Z10, 640(AX) + VMOVDQU64 0(R8), Z11 + VCVTQQ2PD Z11, Z12 + VMOVDQU64 Z12, 704(AX) + VMOVDQU64 0(R9), Z13 + VCVTUQQ2PD Z13, Z14 + VMOVDQU64 Z14, 768(AX) + VCVTQQ2PS Z11, Y15 + VMOVDQU32 Y15, 832(AX) + VCVTUQQ2PS.RU_SAE Z13, Y16 + VMOVDQU32 Y16, 864(AX) + VMOVDQU64 0(R10), Z17 + VCVTPD2QQ.Z Z0, K1, Z17 + VMOVDQU64 Z17, 896(AX) + VMOVDQU64 0(BX), X0 + VCVTPD2UDQX X0, X18 + VMOVDQU32 X18, 960(AX) + VMOVDQU64 0(BX), Y0 + VCVTTPD2UDQY Y0, X19 + VMOVDQU32 X19, 976(AX) + STC + SETCS 992(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"packednumericconversionsemantics": { + Name: "packednumericconversionsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + {Offset: 48, Type: Ptr, Index: 6, Field: -1}, + {Offset: 56, Type: I64, Index: 7, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#pragma STDC FENV_ACCESS ON +#include +#include +#include +#include +#include +#include +extern void packednumericconversionsemantics(uint8_t *, const double *, const float *, const uint32_t *, const int64_t *, const uint64_t *, const uint64_t *, uint64_t); +static uint32_t u32(const uint8_t *p){uint32_t v;memcpy(&v,p,4);return v;} static uint64_t u64(const uint8_t *p){uint64_t v;memcpy(&v,p,8);return v;} +static double rd(double x,int truncating,int fixed){if(truncating)return trunc(x);if(fixed==1)return nearbyint(x);int rc=fegetround();return rc==FE_DOWNWARD?floor(x):(rc==FE_UPWARD?ceil(x):(rc==FE_TOWARDZERO?trunc(x):nearbyint(x)));} +static float rf(float x,int truncating){if(truncating)return truncf(x);int rc=fegetround();return rc==FE_DOWNWARD?floorf(x):(rc==FE_UPWARD?ceilf(x):(rc==FE_TOWARDZERO?truncf(x):nearbyintf(x)));} +static uint64_t f64i(double x,int uns,int truncating,int fixed){double r=rd(x,truncating,fixed);if(uns){if(!(r>=0.0&&r<18446744073709551616.0))return UINT64_MAX;return (uint64_t)r;}if(!(r>=-9223372036854775808.0&&r<9223372036854775808.0))return UINT64_C(0x8000000000000000);return (uint64_t)(int64_t)r;} +static uint64_t f32i64(float x,int uns,int truncating){float r=rf(x,truncating);if(uns){if(!(r>=0.0f&&r<18446744073709551616.0f))return UINT64_MAX;return (uint64_t)r;}if(!(r>=-9223372036854775808.0f&&r<9223372036854775808.0f))return UINT64_C(0x8000000000000000);return (uint64_t)(int64_t)r;} +static uint32_t f32u32(float x,int truncating){float r=rf(x,truncating);if(!(r>=0.0f&&r<4294967296.0f))return UINT32_MAX;return (uint32_t)r;} +static uint32_t fb(float x){uint32_t u;memcpy(&u,&x,4);return u;} static uint64_t db(double x){uint64_t u;memcpy(&u,&x,8);return u;} +static float cu32f(uint32_t x){volatile uint32_t v=x;return (float)v;} static double cu32d(uint32_t x){volatile uint32_t v=x;return (double)v;} +static float ci64f(int64_t x){volatile int64_t v=x;return (float)v;} static double ci64d(int64_t x){volatile int64_t v=x;return (double)v;} +static float cu64f(uint64_t x){volatile uint64_t v=x;return (float)v;} static double cu64d(uint64_t x){volatile uint64_t v=x;return (double)v;} +int main(void){ + const double d[8]={1.5,2.5,-1.5,-2.5,9223372036854775808.0,-9223372036854775808.0,18446744073709551616.0,NAN}; + const float f[16]={1.5f,2.5f,-1.5f,-2.5f,0.0f,-0.0f,4294967296.0f,NAN,16777217.0f,2147483648.0f,-2147483904.0f,3.75f,INFINITY,-INFINITY,0x1p-149f,0x1.fffffep127f}; + const uint32_t ui32[16]={0,1,16777215,16777217,UINT32_MAX,2147483648u,3,5,7,9,11,13,15,17,19,21}; + const int64_t si64[8]={0,1,-1,INT64_C(9007199254740993),-INT64_C(9007199254740993),INT64_MAX,INT64_MIN,123456789}; + const uint64_t ui64[8]={0,1,UINT64_C(9007199254740993),UINT64_C(16777217),UINT64_MAX,UINT64_C(1)<<63,3,123456789}; + const uint64_t old[8]={10,11,12,13,14,15,16,17},mask=UINT64_C(0xa5); unsigned original=_mm_getcsr(); const int modes[4]={FE_TONEAREST,FE_DOWNWARD,FE_UPWARD,FE_TOWARDZERO}; + for(int rc=0;rc<4;rc++){uint8_t out[993]={0};fesetround(modes[rc]);packednumericconversionsemantics(out,d,f,ui32,si64,ui64,old,mask); + for(int i=0;i<8;i++){if(u64(out+i*8)!=f64i(d[i],0,0,0))return 10+rc;if(u64(out+64+i*8)!=f64i(d[i],1,0,0))return 20+rc; + int save=fegetround();fesetround(FE_UPWARD);uint64_t ru=f64i(d[i],0,0,0);fesetround(save);if(u64(out+128+i*8)!=ru)return 30+rc;if(u64(out+192+i*8)!=f64i(d[i],1,1,0))return 40+rc; + if(u64(out+256+i*8)!=f32i64(f[i],0,0))return 50+rc;if(u64(out+320+i*8)!=f32i64(f[i],1,1))return 60+rc;} + for(int i=0;i<16;i++){if(u32(out+384+i*4)!=f32u32(f[0],0))return 70+rc;if(u32(out+448+i*4)!=f32u32(f[i],1))return 80+rc;if(u32(out+512+i*4)!=fb(cu32f(ui32[i])))return 90+rc; + int save=fegetround();fesetround(FE_DOWNWARD);uint32_t down=fb(cu32f(ui32[i]));fesetround(save);if(u32(out+576+i*4)!=down){fprintf(stderr,"rd rc=%d i=%d got=%08x want=%08x\n",rc,i,u32(out+576+i*4),down);return 100+i;}} + for(int i=0;i<8;i++){if(u64(out+640+i*8)!=db(cu32d(ui32[i])))return 110+rc;if(u64(out+704+i*8)!=db(ci64d(si64[i])))return 120+rc;if(u64(out+768+i*8)!=db(cu64d(ui64[i])))return 130+rc;if(u32(out+832+i*4)!=fb(ci64f(si64[i])))return 140+rc; + int save=fegetround();fesetround(FE_UPWARD);uint32_t up=fb(cu64f(ui64[i]));fesetround(save);if(u32(out+864+i*4)!=up)return 150+rc;if(u64(out+896+i*8)!=(((mask>>i)&1)?f64i(d[i],0,0,0):0))return 160+rc;} + if(u32(out+960)!=f32u32((float)d[0],0)||u32(out+964)!=f32u32((float)d[1],0)||u64(out+968)!=0){fprintf(stderr,"narrow rc=%d got=%08x,%08x,%016llx want=%08x,%08x,0\n",rc,u32(out+960),u32(out+964),(unsigned long long)u64(out+968),f32u32((float)d[0],0),f32u32((float)d[1],0));return 170+rc;} + for(int i=0;i<4;i++)if(u32(out+976+i*4)!=f32u32((float)d[i],1))return 180+rc;if(out[992]!=1)return 190+rc; + } + _mm_setcsr(original);fesetround(FE_TONEAREST);return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_numeric_conversion_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_packed_rotate.go b/amd64_lower_packed_rotate.go new file mode 100644 index 00000000..c4b58a79 --- /dev/null +++ b/amd64_lower_packed_rotate.go @@ -0,0 +1,178 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +type amd64PackedRotateSpec struct { + laneBits int + left bool + variable bool +} + +// amd64PackedRotateSpecs covers Go 1.27's complete _yvprold immediate and +// _yvblendmpd per-lane variable rotate families. +var amd64PackedRotateSpecs = map[Op]amd64PackedRotateSpec{ + "VPROLD": {laneBits: 32, left: true}, + "VPROLQ": {laneBits: 64, left: true}, + "VPRORD": {laneBits: 32}, + "VPRORQ": {laneBits: 64}, + "VPROLVD": {laneBits: 32, left: true, variable: true}, + "VPROLVQ": {laneBits: 64, left: true, variable: true}, + "VPRORVD": {laneBits: 32, variable: true}, + "VPRORVQ": {laneBits: 64, variable: true}, +} + +func (c *amd64Ctx) lowerPackedRotate(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64PackedRotateSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s has a suffix absent from Go 1.27's EVEX encoding: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s has an operand count absent from its Go 1.27 table: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed Go 1.27's assembler operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + + firstIndex := 0 + if !spec.variable { + if ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("%s %s first operand must be Go 1.27's unsigned-imm8 class: %q", c.goarch, baseOp, ins.Raw) + } + firstIndex = 1 + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be an X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if (byteWidth != 16 && byteWidth != 32 && byteWidth != 64) || !c.isGoEVEXVectorRegister(dstArg, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's EVEX vector class: %q", c.goarch, baseOp, ins.Raw) + } + + firstArg := ins.Args[firstIndex] + if broadcast { + if !isAMD64MemoryOperand(firstArg) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory first source: %q", c.goarch, baseOp, ins.Raw) + } + } else if firstArg.Kind == OpReg { + if !c.isGoEVEXVectorRegister(firstArg, byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match the destination width and register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(firstArg) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if spec.variable && !c.isGoEVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s data source must be a same-width EVEX vector register: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + } + + return c.emitPackedRotateInstruction(baseOp, spec, ins, firstArg, dstArg, mask, broadcast, zeroing) +} + +func (c *amd64Ctx) emitPackedRotateInstruction(baseOp string, spec amd64PackedRotateSpec, ins Instr, firstArg, dstArg Operand, mask string, broadcast, zeroing bool) (bool, bool, error) { + byteWidth := amd64VectorByteWidth(dstArg.Reg) + lanes := byteWidth * 8 / spec.laneBits + loadLanes := func(arg Operand, allowBroadcast bool) (string, error) { + if allowBroadcast && broadcast { + scalar, err := c.evalIntSized(arg, amd64IntegerTypeForBits(spec.laneBits)) + if err != nil { + return "", err + } + return amd64SplatInteger(c, lanes, spec.laneBits, scalar), nil + } + bytesValue, err := c.loadPackedCompareBytes(arg, byteWidth) + if err != nil { + return "", err + } + return c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, bytesValue), nil + } + + var data, counts string + var err error + if spec.variable { + counts, err = loadLanes(firstArg, true) + if err == nil { + data, err = loadLanes(ins.Args[1], false) + } + } else { + data, err = loadLanes(firstArg, true) + counts = amd64SplatInteger(c, lanes, spec.laneBits, strconv.Itoa(int(ins.Args[0].Imm)&(spec.laneBits-1))) + } + if err != nil { + return true, false, err + } + result := c.emitPackedRotate(lanes, spec.laneBits, data, counts, spec.left) + if mask != "" { + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + if err := c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out); err != nil { + return true, false, fmt.Errorf("%s %s destination: %w", c.goarch, baseOp, err) + } + return true, false, nil +} + +func (c *amd64Ctx) emitPackedRotate(lanes, laneBits int, data, counts string, left bool) string { + vectorType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + laneMask := amd64SplatInteger(c, lanes, laneBits, strconv.Itoa(laneBits-1)) + normalized := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", normalized, vectorType, counts, laneMask) + negated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s zeroinitializer, %%%s\n", negated, vectorType, normalized) + inverse := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %s\n", inverse, vectorType, negated, laneMask) + + low, high := c.newTmp(), c.newTmp() + if left { + fmt.Fprintf(c.b, " %%%s = shl %s %s, %%%s\n", low, vectorType, data, normalized) + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %%%s\n", high, vectorType, data, inverse) + } else { + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %%%s\n", low, vectorType, data, normalized) + fmt.Fprintf(c.b, " %%%s = shl %s %s, %%%s\n", high, vectorType, data, inverse) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %%%s\n", result, vectorType, low, high) + return "%" + result +} diff --git a/amd64_lower_packed_testmask.go b/amd64_lower_packed_testmask.go new file mode 100644 index 00000000..b028ae91 --- /dev/null +++ b/amd64_lower_packed_testmask.go @@ -0,0 +1,129 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedTestMaskSpec struct { + laneBits int + testZero bool +} + +var amd64PackedTestMaskSpecs = map[string]amd64PackedTestMaskSpec{ + "VPTESTMB": {laneBits: 8}, + "VPTESTMW": {laneBits: 16}, + "VPTESTMD": {laneBits: 32}, + "VPTESTMQ": {laneBits: 64}, + "VPTESTNMB": {laneBits: 8, testZero: true}, + "VPTESTNMW": {laneBits: 16, testZero: true}, + "VPTESTNMD": {laneBits: 32, testZero: true}, + "VPTESTNMQ": {laneBits: 64, testZero: true}, +} + +// lowerPackedTestMask implements the complete Go 1.27 _yvpshufbitqmb +// operand table shared by VPTESTM{B,W,D,Q} and VPTESTNM{B,W,D,Q}. +// VPTESTM sets each K bit when the corresponding source-lane intersection is +// nonzero; VPTESTNM sets it when that intersection is zero. +func (c *amd64Ctx) lowerPackedTestMask(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, ok := amd64PackedTestMaskSpecs[baseOp] + if !ok { + return false, false, nil + } + broadcast := suffix == "BCST" + if suffix != "" && !broadcast { + return true, false, fmt.Errorf("%s %s accepts only the .BCST suffix supported by Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects first source, second source, [K mask,] K destination: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && len(ins.Args) == 4 { + return true, false, fmt.Errorf("386 %s write-mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + + second := ins.Args[1] + byteWidth, validWidth := amd64PackedCompareWidth(second) + if !validWidth || !c.isGoPackedVectorMoveRegister(second, byteWidth) { + return true, false, fmt.Errorf("%s %s second source must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + first := ins.Args[0] + if first.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(first, byteWidth) { + return true, false, fmt.Errorf("%s %s register sources must have matching widths and be in range: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("%s %s first source must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast { + if spec.laneBits != 32 && spec.laneBits != 64 { + return true, false, fmt.Errorf("%s %s does not enable broadcast in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory first source: %q", c.goarch, baseOp, ins.Raw) + } + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be K0-K7: %q", c.goarch, baseOp, ins.Raw) + } + if _, validDestination := amd64ParseKReg(destination.Reg); !validDestination { + return true, false, fmt.Errorf("%s %s destination must be K0-K7: %q", c.goarch, baseOp, ins.Raw) + } + + writeMask := "" + if len(ins.Args) == 4 { + mask := ins.Args[2] + if mask.Kind != OpReg { + return true, false, fmt.Errorf("%s %s write mask must be K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + maskIndex, validMask := amd64ParseKReg(mask.Reg) + if !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("%s %s write mask must be K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + writeMask, err = c.loadK(mask.Reg) + if err != nil { + return true, false, err + } + } + + firstValue, err := c.loadPackedCompareLanes(first, byteWidth, spec.laneBits, broadcast) + if err != nil { + return true, false, err + } + secondValue, err := c.loadPackedCompareLanes(second, byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / spec.laneBits + vectorType := fmt.Sprintf("<%d x i%d>", lanes, spec.laneBits) + intersection := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", intersection, vectorType, firstValue, secondValue) + predicate := "ne" + if spec.testZero { + predicate = "eq" + } + tested := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %s %s %%%s, zeroinitializer\n", tested, predicate, vectorType, intersection) + packedType := fmt.Sprintf("i%d", lanes) + packed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i1> %%%s to %s\n", packed, lanes, tested, packedType) + result := "%" + packed + if lanes < 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to i64\n", wide, packedType, result) + result = "%" + wide + } + if writeMask != "" { + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %s\n", masked, result, writeMask) + result = "%" + masked + } + return true, false, c.storeK(destination.Reg, result) +} diff --git a/amd64_lower_packed_testmask_test.go b/amd64_lower_packed_testmask_test.go new file mode 100644 index 00000000..1ecee0a6 --- /dev/null +++ b/amd64_lower_packed_testmask_test.go @@ -0,0 +1,126 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedTestMaskCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 gives VPTESTM{B,W,D,Q} and VPTESTNM{B,W,D,Q} the same + // _yvpshufbitqmb operand table: X/Y/Z r/m first source, a matching + // vector second source, an optional K1-K7 write mask, and a K + // destination. D/Q additionally enable scalar-memory broadcast. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT packedtestmaskforms(SB),$0-0\n") + for _, op := range []string{ + "VPTESTMB", "VPTESTMW", "VPTESTMD", "VPTESTMQ", + "VPTESTNMB", "VPTESTNMW", "VPTESTNMD", "VPTESTNMQ", + } { + zLast := 31 + if target.goarch == "386" { + zLast = 7 + } + fmt.Fprintf(&source, "\t%s X1, X31, K0\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), X31, K2\n", op) + fmt.Fprintf(&source, "\t%s Y1, Y31, K3\n", op) + fmt.Fprintf(&source, "\t%s 40(AX), Y31, K5\n", op) + fmt.Fprintf(&source, "\t%s Z1, Z%d, K6\n", op, zLast) + fmt.Fprintf(&source, "\t%s 104(AX), Z%d, K0\n", op, zLast) + fmt.Fprintf(&source, "\t%s 0, Z%d, K0\n", op, zLast) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s 112(AX), X31, K1, K2\n", op) + fmt.Fprintf(&source, "\t%s 120(AX), Y31, K4, K5\n", op) + fmt.Fprintf(&source, "\t%s 128(AX), Z31, K7, K0\n", op) + } + if strings.HasSuffix(op, "D") || strings.HasSuffix(op, "Q") { + fmt.Fprintf(&source, "\t%s.BCST 168(AX), X31, K1\n", op) + fmt.Fprintf(&source, "\t%s.BCST 176(AX), Y31, K3\n", op) + fmt.Fprintf(&source, "\t%s.BCST 184(AX), Z%d, K4\n", op, zLast) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.BCST 192(AX), Y31, K2, K3\n", op) + } + } + } + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedtestmaskforms": {Name: "packedtestmaskforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"icmp ne", "icmp eq", "store i64"} { + if !strings.Contains(ll, want) { + t.Fatalf("translation omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-test-mask-"+target.name+".ll", "packed-test-mask-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedTestMaskRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VPTESTMD X0, X1"}, + {goarch: "amd64", instruction: "VPTESTMD X0, Y1, K1"}, + {goarch: "amd64", instruction: "VPTESTMD X0, (AX), K1"}, + {goarch: "amd64", instruction: "VPTESTMD X0, X1, K0, K1"}, + {goarch: "amd64", instruction: "VPTESTMD X0, X1, AX"}, + {goarch: "amd64", instruction: "VPTESTMD.Z X0, X1, K1"}, + {goarch: "amd64", instruction: "VPTESTMB.BCST (AX), X1, K1"}, + {goarch: "amd64", instruction: "VPTESTMW.BCST (AX), X1, K1"}, + {goarch: "amd64", instruction: "VPTESTMD.BCST X0, X1, K1"}, + {goarch: "amd64", instruction: "VPTESTNMQ X32, X1, K1"}, + {goarch: "386", instruction: "VPTESTMD X1, X2, K1, K2"}, + {goarch: "386", instruction: "VPTESTMD Z8, Z0, K1"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed test-mask forms for %s", test.instruction, test.goarch) + } + }) + } +} diff --git a/amd64_lower_paddd_alias_test.go b/amd64_lower_paddd_alias_test.go new file mode 100644 index 00000000..897c2f90 --- /dev/null +++ b/amd64_lower_paddd_alias_test.go @@ -0,0 +1,199 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64PackedAddGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64PackedAddSpec{ + "PADDB": {canonical: "PADDB", form: amd64PackedAddLegacyYMM, laneBits: 8, mode: amd64PackedAddWrap}, + "PADDW": {canonical: "PADDW", form: amd64PackedAddLegacyYMM, laneBits: 16, mode: amd64PackedAddWrap}, + "PADDL": {canonical: "PADDL", form: amd64PackedAddLegacyYMM, laneBits: 32, mode: amd64PackedAddWrap}, + "PADDD": {canonical: "PADDL", form: amd64PackedAddLegacyYMM, laneBits: 32, mode: amd64PackedAddWrap}, + "PADDQ": {canonical: "PADDQ", form: amd64PackedAddLegacyYXM, laneBits: 64, mode: amd64PackedAddWrap}, + "PADDSB": {canonical: "PADDSB", form: amd64PackedAddLegacyYMM, laneBits: 8, mode: amd64PackedAddSignedSaturating}, + "PADDSW": {canonical: "PADDSW", form: amd64PackedAddLegacyYMM, laneBits: 16, mode: amd64PackedAddSignedSaturating}, + "PADDUSB": {canonical: "PADDUSB", form: amd64PackedAddLegacyYMM, laneBits: 8, mode: amd64PackedAddUnsignedSaturating}, + "PADDUSW": {canonical: "PADDUSW", form: amd64PackedAddLegacyYMM, laneBits: 16, mode: amd64PackedAddUnsignedSaturating}, + "VPADDB": {canonical: "VPADDB", form: amd64PackedAddVEXEVEX, laneBits: 8, mode: amd64PackedAddWrap}, + "VPADDW": {canonical: "VPADDW", form: amd64PackedAddVEXEVEX, laneBits: 16, mode: amd64PackedAddWrap}, + "VPADDD": {canonical: "VPADDD", form: amd64PackedAddVEXEVEX, laneBits: 32, mode: amd64PackedAddWrap, allowBroadcast: true}, + "VPADDQ": {canonical: "VPADDQ", form: amd64PackedAddVEXEVEX, laneBits: 64, mode: amd64PackedAddWrap, allowBroadcast: true}, + "VPADDSB": {canonical: "VPADDSB", form: amd64PackedAddVEXEVEX, laneBits: 8, mode: amd64PackedAddSignedSaturating}, + "VPADDSW": {canonical: "VPADDSW", form: amd64PackedAddVEXEVEX, laneBits: 16, mode: amd64PackedAddSignedSaturating}, + "VPADDUSB": {canonical: "VPADDUSB", form: amd64PackedAddVEXEVEX, laneBits: 8, mode: amd64PackedAddUnsignedSaturating}, + "VPADDUSW": {canonical: "VPADDUSW", form: amd64PackedAddVEXEVEX, laneBits: 16, mode: amd64PackedAddUnsignedSaturating}, + } + if len(amd64PackedAddSpecs) != len(expected) { + t.Fatalf("packed-add grammar has %d entries, want %d", len(amd64PackedAddSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64PackedAddSpecs[op]; !ok { + t.Errorf("packed-add grammar omitted %s", op) + } else if got != want { + t.Errorf("packed-add grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86PADDDGoAliasCompleteFormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastX := 15 + if target.goarch == "386" { + lastX = 7 + } + var source strings.Builder + source.WriteString("TEXT padddaliasforms(SB),$0-0\n") + for _, op := range []string{"PADDL", "PADDD"} { + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s M0, M7\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), M7\n", op) + } + fmt.Fprintf(&source, "\t%s X0, X%d\n", op, lastX) + fmt.Fprintf(&source, "\t%s 16(AX), X%d\n", op, lastX) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"padddaliasforms": {Name: "padddaliasforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "add <4 x i32>") { + t.Fatalf("PADDL/PADDD lowering omitted dword addition:\n%s", ir) + } + if target.goarch == "amd64" && !strings.Contains(ir, "bitcast i64") { + t.Fatalf("PADDL/PADDD lowering omitted MMX forms:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "paddd-alias-"+target.name+".ll", "paddd-alias-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86PADDDGoAliasRejectsFormsOutsidePADDLTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "PADDD M0, X1"}, + {goarch: "amd64", instruction: "PADDD X0, M1"}, + {goarch: "amd64", instruction: "PADDD Y0, Y1"}, + {goarch: "amd64", instruction: "PADDD.Z X0, X1"}, + {goarch: "386", instruction: "PADDD M0, M1"}, + {goarch: "386", instruction: "PADDL M0, M1"}, + {goarch: "386", instruction: "PADDD X0, X8"}, + {goarch: "386", instruction: "PADDD 8(R9), X0"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside PADDD/PADDL's Go table for %s", test.instruction, test.goarch) + } + }) + } +} + +func TestAMD64PADDDGoAliasRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT padddaliassemantics(SB),$0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), M0 + MOVQ b+16(FP), M1 + STC + PADDD M0, M1 + MOVQ M1, 0(AX) + SETCS 8(AX) + EMMS + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "padddaliassemantics": { + Name: "padddaliassemantics", Args: []LLVMType{Ptr, I64, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void padddaliassemantics(uint8_t *, uint64_t, uint64_t); +int main(void) { + uint8_t out[9] = {0}; + uint64_t a = UINT64_C(0xffffffff00000002); + uint64_t b = UINT64_C(0x0000000200000003); + padddaliassemantics(out, a, b); + uint64_t got; + memcpy(&got, out, 8); + if (got != UINT64_C(0x0000000100000005)) return 10; + if (out[8] != 1) return 11; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "paddd_alias_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_parallel_bits.go b/amd64_lower_parallel_bits.go new file mode 100644 index 00000000..79ed7ad7 --- /dev/null +++ b/amd64_lower_parallel_bits.go @@ -0,0 +1,97 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerParallelBitDepositExtract implements the complete Go 1.27 PDEP/PEXT +// family. All four instructions share _yandnl's single Yml, Yrl, Yrl row. +func (c *amd64Ctx) lowerParallelBitDepositExtract(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + bits := 0 + switch baseOp { + case "PDEPL", "PEXTL": + bits = 32 + case "PDEPQ", "PEXTQ": + bits = 64 + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s has no instruction suffixes in Go 1.27's optab: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("amd64 %s expects mask, source, destination: %q", baseOp, ins.Raw) + } + maskOperand := ins.Args[0] + if maskOperand.Kind == OpReg { + if !isX86YrlRegisterForArch(maskOperand.Reg, c.goarch) { + return true, false, fmt.Errorf("amd64 %s first operand is outside Go 1.27's Yml class: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(maskOperand) { + return true, false, fmt.Errorf("amd64 %s first operand is outside Go 1.27's Yml class: %q", baseOp, ins.Raw) + } + if ins.Args[1].Kind != OpReg || !isX86YrlRegisterForArch(ins.Args[1].Reg, c.goarch) { + return true, false, fmt.Errorf("amd64 %s second operand is outside Go 1.27's Yrl class: %q", baseOp, ins.Raw) + } + if ins.Args[2].Kind != OpReg || !isX86YrlRegisterForArch(ins.Args[2].Reg, c.goarch) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's Yrl class: %q", baseOp, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + mask, err := c.evalIntSized(maskOperand, typ) + if err != nil { + return true, false, err + } + source, err := c.evalIntSized(ins.Args[1], typ) + if err != nil { + return true, false, err + } + result := c.emitParallelBitOperation(strings.HasPrefix(baseOp, "PDEP"), bits, mask, source) + return true, false, c.storeRegSized(ins.Args[2].Reg, typ, result) +} + +// emitParallelBitOperation emits target-independent LLVM so translated code +// retains PDEP/PEXT semantics even when the LLVM execution host lacks BMI2. +// cursor is at most bit before each iteration, so every variable shift stays +// strictly below the integer width and cannot produce LLVM poison. +func (c *amd64Ctx) emitParallelBitOperation(deposit bool, bits int, mask, source string) string { + typ := fmt.Sprintf("i%d", bits) + result := "0" + cursor := "0" + for bit := 0; bit < bits; bit++ { + shiftedMask := c.newTmp() + maskBit := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %d\n", shiftedMask, typ, mask, bit) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, 1\n", maskBit, typ, shiftedMask) + + sourceShift := cursor + destinationShift := fmt.Sprintf("%d", bit) + if !deposit { + sourceShift = fmt.Sprintf("%d", bit) + destinationShift = cursor + } + shiftedSource := c.newTmp() + sourceBit := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %s\n", shiftedSource, typ, source, sourceShift) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, 1\n", sourceBit, typ, shiftedSource) + placed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl %s %%%s, %s\n", placed, typ, sourceBit, destinationShift) + enabledMask := c.newTmp() + enabled := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s 0, %%%s\n", enabledMask, typ, maskBit) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", enabled, typ, placed, enabledMask) + nextResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %s, %%%s\n", nextResult, typ, result, enabled) + result = "%" + nextResult + nextCursor := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %%%s\n", nextCursor, typ, cursor, maskBit) + cursor = "%" + nextCursor + } + return result +} diff --git a/amd64_lower_permute.go b/amd64_lower_permute.go new file mode 100644 index 00000000..7aa226b0 --- /dev/null +++ b/amd64_lower_permute.go @@ -0,0 +1,148 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerVariableDwordPermute implements the complete Go 1.27 _yvpermd +// operand family shared by VPERMD and VPERMPS. +func (c *amd64Ctx) lowerVariableDwordPermute(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + switch baseOp { + case "VPERMD", "VPERMPS": + default: + return false, false, nil + } + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's _yvpermd encodings: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects data, indices, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be Y or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s destination must be Y or Z: %q", c.goarch, baseOp, ins.Raw) + } + validRegister := func(arg Operand) bool { + if !amd64EVEXVectorRegister(arg, byteWidth) { + return false + } + if c.goarch == "386" && byteWidth == 64 { + index, _ := amd64VectorRegisterIndex(arg.Reg, byteWidth) + return index < 8 + } + return true + } + if !validRegister(dstArg) || !validRegister(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s indices and destination must be matching Y or Z registers: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !validRegister(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s data register must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s data must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast && !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory data source: %q", c.goarch, baseOp, ins.Raw) + } + + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + var mask string + if masked { + maskArg := ins.Args[2] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + index, ok := amd64ParseKReg(maskArg.Reg) + if !ok || index == 0 { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + evex := masked || suffix != "" || byteWidth == 64 || !amd64VEXVectorRegister(dstArg, byteWidth) || !amd64VEXVectorRegister(ins.Args[1], byteWidth) + if ins.Args[0].Kind == OpReg && !amd64VEXVectorRegister(ins.Args[0], byteWidth) { + evex = true + } + if !evex && byteWidth != 32 { + return true, false, fmt.Errorf("%s %s VEX form is Y-only in Go 1.27's _yvpermd table: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := byteWidth / 4 + var data string + if broadcast { + scalar, err := c.evalIntSized(ins.Args[0], I32) + if err != nil { + return true, false, err + } + data = amd64SplatInteger(c, lanes, 32, scalar) + } else { + dataBytes, err := c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err != nil { + return true, false, err + } + data = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 32, dataBytes) + } + indicesBytes, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + indices := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 32, indicesBytes) + result := c.emitVariableDwordPermute(data, indices, lanes) + if masked { + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 32, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, 32, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i32> %s to <%d x i8>\n", out, lanes, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitVariableDwordPermute(data, indices string, lanes int) string { + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + index := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i32> %s, i32 %d\n", index, lanes, indices, lane) + maskedIndex := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i32 %%%s, %d\n", maskedIndex, index, lanes-1) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i32> %s, i32 %%%s\n", value, lanes, data, maskedIndex) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i32> %s, i32 %%%s, i32 %d\n", inserted, lanes, result, value, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_permute128_test.go b/amd64_lower_permute128_test.go new file mode 100644 index 00000000..07783490 --- /dev/null +++ b/amd64_lower_permute128_test.go @@ -0,0 +1,162 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateX86Permute128CompleteGoAssemblerForms(t *testing.T) { + const source = `TEXT permute128forms(SB),$0-0 + VPERM2F128 $0, Y0, Y1, Y2 + VPERM2F128 $255, 8(AX), Y15, Y15 + VPERM2I128 $0, Y0, Y1, Y2 + VPERM2I128 $255, 8(AX), Y15, Y15 + RET +` + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "permute128forms": {Name: "permute128forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "permute-128-"+target.name+".ll", "permute-128-"+target.name+".o", ll) + }) + } + requireX86GoAssemblerResult(t, "386", source, false) +} + +func TestTranslateX86Permute128RejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPERM2F128 $-1, Y0, Y1, Y2", + "VPERM2F128 $256, Y0, Y1, Y2", + "VPERM2I128 $-1, Y0, Y1, Y2", + "VPERM2I128 $256, Y0, Y1, Y2", + "VPERM2I128 $1, X0, Y1, Y2", + "VPERM2I128 $1, Y0, 8(AX), Y2", + "VPERM2I128 $1, Y0, X1, Y2", + "VPERM2I128 $1, Y0, Y1, X2", + "VPERM2I128.Z $1, Y0, Y1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + requireX86GoAssemblerResult(t, "amd64", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + assertX86Permute128Rejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + assertX86Permute128Rejected(t, "386", "i386-unknown-linux-gnu", "VPERM2I128 $1, Y0, Y1, Y2") +} + +func assertX86Permute128Rejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VPERM2F128/VPERM2I128 table for %s", instruction, goarch) + } +} + +func TestAMD64Permute128RuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT permute128integer(SB),NOSPLIT,$0-24 + MOVQ out+0(FP), AX + MOVQ first+8(FP), BX + MOVQ second+16(FP), CX + VMOVDQU (BX), Y0 + VMOVDQU (CX), Y1 + VPERM2I128 $0x21, Y0, Y1, Y2 + VMOVDQU Y2, (AX) + VZEROUPPER + RET +TEXT permute128float(SB),NOSPLIT,$0-24 + MOVQ out+0(FP), AX + MOVQ first+8(FP), BX + MOVQ second+16(FP), CX + VMOVDQU (BX), Y0 + VMOVDQU (CX), Y1 + VPERM2F128 $0x12, Y0, Y1, Y2 + VMOVDQU Y2, (AX) + VZEROUPPER + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "permute128integer": {Name: "permute128integer", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, Frame: frame}, + "permute128float": {Name: "permute128float", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void permute128integer(uint8_t *, const uint8_t *, const uint8_t *); +extern void permute128float(uint8_t *, const uint8_t *, const uint8_t *); +int main(void) { + uint8_t first[32], second[32], out[32]; + for (int i = 0; i < 32; i++) { first[i] = (uint8_t)i; second[i] = (uint8_t)(100+i); out[i] = 0; } + permute128integer(out, first, second); + for (int i = 0; i < 16; i++) if (out[i] != second[i+16]) return 10+i; + for (int i = 16; i < 32; i++) if (out[i] != first[i-16]) return 50+i; + permute128float(out, first, second); + for (int i = 0; i < 16; i++) if (out[i] != first[i]) return 90+i; + for (int i = 16; i < 32; i++) if (out[i] != second[i]) return 130+i; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "permute_128", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_permute_index_family_test.go b/amd64_lower_permute_index_family_test.go new file mode 100644 index 00000000..7fbb0ec0 --- /dev/null +++ b/amd64_lower_permute_index_family_test.go @@ -0,0 +1,274 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64IndexedPermuteGrammarCoversCompleteGoFamilies(t *testing.T) { + expected := map[Op]amd64IndexedPermuteSpec{ + "VPERMB": {laneBits: 8, mode: amd64IndexedPermuteSingle}, + "VPERMW": {laneBits: 16, mode: amd64IndexedPermuteSingle}, + "VPERMI2B": {laneBits: 8, mode: amd64IndexedPermuteI2}, + "VPERMI2W": {laneBits: 16, mode: amd64IndexedPermuteI2}, + "VPERMI2D": {laneBits: 32, mode: amd64IndexedPermuteI2, broadcast: true}, + "VPERMI2PS": {laneBits: 32, mode: amd64IndexedPermuteI2, broadcast: true}, + "VPERMI2Q": {laneBits: 64, mode: amd64IndexedPermuteI2, broadcast: true}, + "VPERMI2PD": {laneBits: 64, mode: amd64IndexedPermuteI2, broadcast: true}, + "VPERMT2B": {laneBits: 8, mode: amd64IndexedPermuteT2}, + "VPERMT2W": {laneBits: 16, mode: amd64IndexedPermuteT2}, + "VPERMT2D": {laneBits: 32, mode: amd64IndexedPermuteT2, broadcast: true}, + "VPERMT2PS": {laneBits: 32, mode: amd64IndexedPermuteT2, broadcast: true}, + "VPERMT2Q": {laneBits: 64, mode: amd64IndexedPermuteT2, broadcast: true}, + "VPERMT2PD": {laneBits: 64, mode: amd64IndexedPermuteT2, broadcast: true}, + } + if len(amd64IndexedPermuteSpecs) != len(expected) { + t.Fatalf("indexed-permute grammar has %d entries, want %d", len(amd64IndexedPermuteSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64IndexedPermuteSpecs[op]; !ok { + t.Errorf("indexed-permute grammar omitted %s", op) + } else if got != want { + t.Errorf("indexed-permute grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86IndexedPermuteCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT indexedpermuteforms(SB),$0-0\n") + for _, family := range []struct { + op string + broadcast bool + }{ + {op: "VPERMB"}, {op: "VPERMW"}, + {op: "VPERMI2B"}, {op: "VPERMI2W"}, + {op: "VPERMI2D", broadcast: true}, {op: "VPERMI2Q", broadcast: true}, + {op: "VPERMI2PS", broadcast: true}, {op: "VPERMI2PD", broadcast: true}, + {op: "VPERMT2B"}, {op: "VPERMT2W"}, + {op: "VPERMT2D", broadcast: true}, {op: "VPERMT2Q", broadcast: true}, + {op: "VPERMT2PS", broadcast: true}, {op: "VPERMT2PD", broadcast: true}, + } { + for _, width := range []string{"X", "Y", "Z"} { + last := 31 + if target.goarch == "386" && width == "Z" { + last = 7 + } + fmt.Fprintf(&source, "\t%s %s1, %s2, %s%d\n", family.op, width, width, width, last) + fmt.Fprintf(&source, "\t%s 8(AX), %s2, %s%d\n", family.op, width, width, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s %s1, %s2, K1, %s%d\n", family.op, width, width, width, last) + fmt.Fprintf(&source, "\t%s.Z 16(AX), %s2, K2, %s%d\n", family.op, width, width, last) + } + if family.broadcast { + fmt.Fprintf(&source, "\t%s.BCST 24(AX), %s2, %s%d\n", family.op, width, width, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.BCST.Z 32(AX), %s2, K3, %s%d\n", family.op, width, width, last) + } + } + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"indexedpermuteforms": {Name: "indexedpermuteforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "indexed-permute-"+target.name+".ll", "indexed-permute-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86IndexedPermuteRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VPERMB X0, Y1, Y2"}, + {goarch: "amd64", instruction: "VPERMW.BCST 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VPERMT2B.BCST 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VPERMT2D.BCST X0, X1, X2"}, + {goarch: "amd64", instruction: "VPERMT2D.Z X0, X1, X2"}, + {goarch: "amd64", instruction: "VPERMI2Q X0, X1, K0, X2"}, + {goarch: "amd64", instruction: "VPERMT2PS X0, X1, 0(AX)"}, + {goarch: "amd64", instruction: "VPERMI2D.Z.BCST 0(AX), X1, K1, X2"}, + {goarch: "amd64", instruction: "VPERMB X0, X1"}, + {goarch: "386", instruction: "VPERMT2D X0, X1, K1, X2"}, + {goarch: "386", instruction: "VPERMW Z0, Z1, Z8"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's indexed-permute table", test.instruction) + } + }) + } +} + +func TestAMD64IndexedPermuteRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT indexedpermutesemantics(SB),$0-48 + MOVQ out+0(FP), AX + MOVQ tableA+8(FP), BX + MOVQ tableB+16(FP), CX + MOVQ indices+24(FP), DX + MOVQ old+32(FP), R8 + MOVQ mask+40(FP), R9 + KMOVQ R9, K1 + VMOVDQU64 0(BX), Z0 + VMOVDQU64 0(CX), Z1 + VMOVDQU64 0(DX), Z2 + VMOVDQU64 0(R8), Z3 + STC + VPERMB Z0, Z2, Z4 + VMOVDQU64 Z4, 0(AX) + VPERMW Z0, Z2, Z4 + VMOVDQU64 Z4, 64(AX) + VPERMI2B Z0, Z1, Z2 + VMOVDQU64 Z2, 128(AX) + VMOVDQU64 0(DX), Z2 + VPERMT2B Z0, Z2, Z3 + VMOVDQU64 Z3, 192(AX) + VMOVDQU64 0(R8), Z3 + VPERMB Z0, Z2, K1, Z3 + VMOVDQU64 Z3, 256(AX) + VMOVDQU64 0(R8), Z3 + VPERMT2W.Z Z0, Z2, K1, Z3 + VMOVDQU64 Z3, 320(AX) + VMOVDQU64 0(DX), Z2 + VPERMI2Q.BCST 0(BX), Z1, K1, Z2 + VMOVDQU64 Z2, 384(AX) + VMOVDQU64 0(DX), Z2 + VMOVDQU64 0(R8), Z3 + VPERMT2D.BCST 0(BX), Z2, K1, Z3 + VMOVDQU64 Z3, 448(AX) + SETCS 512(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"indexedpermutesemantics": { + Name: "indexedpermutesemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: I64, Index: 5, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void indexedpermutesemantics(uint8_t *, const uint8_t *, const uint8_t *, const uint8_t *, const uint8_t *, uint64_t); +static uint16_t u16(const uint8_t *p) { uint16_t v; memcpy(&v,p,2); return v; } +static uint32_t u32(const uint8_t *p) { uint32_t v; memcpy(&v,p,4); return v; } +static uint64_t u64(const uint8_t *p) { uint64_t v; memcpy(&v,p,8); return v; } +int main(void) { + uint64_t a64[8], b64[8], indices64[8], old64[8], output64[65] = {0}; + uint8_t *a=(uint8_t *)a64, *b=(uint8_t *)b64, *indices=(uint8_t *)indices64; + uint8_t *old=(uint8_t *)old64, *out=(uint8_t *)output64; + const uint64_t mask=UINT64_C(0xa55af00ff00fa55a); + for (int i=0;i<64;i++) { + a[i]=(uint8_t)(0x11u+3u*(unsigned)i); + b[i]=(uint8_t)(0x80u+5u*(unsigned)i); + indices[i]=(uint8_t)(7u+13u*(unsigned)i); + old[i]=(uint8_t)(0xe0u-(unsigned)i); + } + indexedpermutesemantics(out,a,b,indices,old,mask); + for (int i=0;i<64;i++) { + unsigned index=indices[i]&63u; + if (out[i]!=a[index]) return 10; + unsigned two=indices[i]&127u; + uint8_t want=two<64u ? b[two] : a[two-64u]; + if (out[128+i]!=want) return 11; + want=two<64u ? old[two] : a[two-64u]; + if (out[192+i]!=want) return 12; + want=(mask>>i)&1u ? a[index] : old[i]; + if (out[256+i]!=want) return 13; + } + for (int i=0;i<32;i++) { + unsigned index=u16(indices+2*i)&31u; + if (u16(out+64+2*i)!=u16(a+2*index)) return 20; + unsigned two=u16(indices+2*i)&63u; + uint16_t want=two<32u ? u16(old+2*two) : u16(a+2*(two-32u)); + if (u16(out+320+2*i)!=(((mask>>i)&1u)?want:0)) return 21; + } + for (int i=0;i<8;i++) { + unsigned index=(unsigned)(u64(indices+8*i)&15u); + uint64_t value=index<8u ? u64(b+8*index) : u64(a); + uint64_t want=(mask>>i)&1u ? value : u64(indices+8*i); + if (u64(out+384+8*i)!=want) return 30; + } + for (int i=0;i<16;i++) { + unsigned index=u32(indices+4*i)&31u; + uint32_t value=index<16u ? u32(old+4*index) : u32(a); + uint32_t want=(mask>>i)&1u ? value : u32(old+4*i); + if (u32(out+448+4*i)!=want) return 31; + } + if (out[512]!=1) return 40; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "indexed_permute_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_permute_inlane.go b/amd64_lower_permute_inlane.go new file mode 100644 index 00000000..d7b48b61 --- /dev/null +++ b/amd64_lower_permute_inlane.go @@ -0,0 +1,218 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerInLaneFloatingPermute implements the complete Go 1.27 _yvpermilpd +// operand family shared by VPERMILPD and VPERMILPS. The permutation preserves +// element bits and never selects across a 128-bit lane. +func (c *amd64Ctx) lowerInLaneFloatingPermute(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits := 0 + switch baseOp { + case "VPERMILPD": + laneBits = 64 + case "VPERMILPS": + laneBits = 32 + default: + return false, false, nil + } + + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's _yvpermilpd encodings: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects control/data, data, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + immediate := ins.Args[0].Kind == OpImm + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoInLanePermuteRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's vector-register class: %q", c.goarch, baseOp, ins.Raw) + } + + rmArg := ins.Args[0] + dataArg := ins.Args[1] + var imm uint8 + if immediate { + rmArg = ins.Args[1] + value := ins.Args[0].Imm + if value < -128 || value > 255 { + return true, false, fmt.Errorf("%s %s immediate is outside Go 1.27's signed-or-unsigned imm8 classes: %q", c.goarch, baseOp, ins.Raw) + } + imm = uint8(value) + if value < 0 { + vex := !masked && suffix == "" && byteWidth != 64 && amd64VEXVectorRegister(destination, byteWidth) + if rmArg.Kind == OpReg { + vex = vex && amd64VEXVectorRegister(rmArg, byteWidth) + } + if !vex { + return true, false, fmt.Errorf("%s %s signed imm8 exists only in its VEX X/Y rows: %q", c.goarch, baseOp, ins.Raw) + } + } + } else if !c.isGoInLanePermuteRegister(dataArg, byteWidth) { + return true, false, fmt.Errorf("%s %s data source must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + + if broadcast { + if !isAMD64MemoryOperand(rmArg) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory r/m source: %q", c.goarch, baseOp, ins.Raw) + } + } else if rmArg.Kind == OpReg { + if !c.isGoInLanePermuteRegister(rmArg, byteWidth) { + return true, false, fmt.Errorf("%s %s r/m register must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(rmArg) { + return true, false, fmt.Errorf("%s %s r/m source must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := byteWidth * 8 / laneBits + var data, control string + if immediate { + if broadcast { + scalar, err := c.evalIntSized(rmArg, amd64IntegerTypeForBits(laneBits)) + if err != nil { + return true, false, err + } + data = amd64SplatInteger(c, lanes, laneBits, scalar) + } else { + bytes, err := c.loadPackedCompareBytes(rmArg, byteWidth) + if err != nil { + return true, false, err + } + data = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, bytes) + } + } else { + dataBytes, err := c.loadPackedCompareBytes(dataArg, byteWidth) + if err != nil { + return true, false, err + } + data = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, dataBytes) + if broadcast { + scalar, err := c.evalIntSized(rmArg, amd64IntegerTypeForBits(laneBits)) + if err != nil { + return true, false, err + } + control = amd64SplatInteger(c, lanes, laneBits, scalar) + } else { + controlBytes, err := c.loadPackedCompareBytes(rmArg, byteWidth) + if err != nil { + return true, false, err + } + control = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, controlBytes) + } + } + + var result string + if immediate { + result = c.emitImmediateInLanePermute(data, lanes, laneBits, imm) + } else { + result = c.emitVariableInLanePermute(data, control, lanes, laneBits) + } + if masked { + mask, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) isGoInLanePermuteRegister(arg Operand, byteWidth int) bool { + if !amd64EVEXVectorRegister(arg, byteWidth) { + return false + } + if c.goarch == "386" && byteWidth == 64 { + index, _ := amd64VectorRegisterIndex(arg.Reg, byteWidth) + return index < 8 + } + return true +} + +func (c *amd64Ctx) emitImmediateInLanePermute(data string, lanes, laneBits int, imm uint8) string { + result := "poison" + for lane := 0; lane < lanes; lane++ { + var sourceLane int + if laneBits == 32 { + groupBase := lane / 4 * 4 + sourceLane = groupBase + int(imm>>uint(2*(lane%4)))&3 + } else { + groupBase := lane / 2 * 2 + sourceLane = groupBase + int(imm>>uint(lane))&1 + } + value := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", value, lanes, laneBits, data, sourceLane) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", inserted, lanes, laneBits, result, laneBits, value, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) emitVariableInLanePermute(data, control string, lanes, laneBits int) string { + result := "poison" + groupLanes := 128 / laneBits + for lane := 0; lane < lanes; lane++ { + controlLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", controlLane, lanes, laneBits, control, lane) + selectorValue := "%" + controlLane + if laneBits == 64 { + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i64 %%%s, 1\n", shifted, controlLane) + selectorValue = "%" + shifted + } + selector := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %s, %d\n", selector, laneBits, selectorValue, groupLanes-1) + index := "%" + selector + groupBase := lane / groupLanes * groupLanes + if groupBase != 0 { + withBase := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i%d %%%s, %d\n", withBase, laneBits, selector, groupBase) + index = "%" + withBase + } + value := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i%d %s\n", value, lanes, laneBits, data, laneBits, index) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", inserted, lanes, laneBits, result, laneBits, value, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_permute_inlane_test.go b/amd64_lower_permute_inlane_test.go new file mode 100644 index 00000000..e3942caf --- /dev/null +++ b/amd64_lower_permute_inlane_test.go @@ -0,0 +1,123 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86InLaneFloatingPermuteCompleteGoAssemblerForms(t *testing.T) { + // VPERMILPD and VPERMILPS share Go 1.27's 18-row _yvpermilpd table: + // immediate and variable-control VEX X/Y forms, EVEX X/Y/Z forms, + // scalar-memory broadcast, and K1-K7 merge/zero masking. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + zLast := 21 + if target.goarch == "386" { + zLast = 7 + } + var src strings.Builder + src.WriteString("TEXT inlanefloatingpermuteforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VPERMILPD", "VPERMILPS"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&src, "\t%s $-128, %s0, %s1\n", op, width, width) + fmt.Fprintf(&src, "\t%s $255, (AX), %s2\n", op, width) + fmt.Fprintf(&src, "\t%s %s0, %s1, %s2\n", op, width, width, width) + fmt.Fprintf(&src, "\t%s (AX), %s20, %s21\n", op, width, width) + fmt.Fprintf(&src, "\t%s $7, %s20, %s21\n", op, width, width) + } + fmt.Fprintf(&src, "\t%s $255, Z0, Z%d\n", op, zLast) + fmt.Fprintf(&src, "\t%s Z0, Z6, Z%d\n", op, zLast) + fmt.Fprintf(&src, "\t%s.BCST $7, (AX), Z%d\n", op, zLast) + fmt.Fprintf(&src, "\t%s.BCST (AX), Z6, Z%d\n", op, zLast) + if target.goarch == "amd64" { + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&src, "\t%s $7, %s20, K1, %s21\n", op, width, width) + fmt.Fprintf(&src, "\t%s.Z $7, (AX), K2, %s22\n", op, width) + fmt.Fprintf(&src, "\t%s %s20, %s21, K3, %s22\n", op, width, width, width) + fmt.Fprintf(&src, "\t%s.BCST.Z (AX), %s21, K4, %s22\n", op, width, width) + } + } + } + src.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "inlanefloatingpermuteforms": {Name: "inlanefloatingpermuteforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "in-lane-floating-permute-"+target.name+".ll", "in-lane-floating-permute-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86InLaneFloatingPermuteRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPERMILPS $-129, X0, X1", + "VPERMILPD $256, X0, X1", + "VPERMILPS $-1, X20, X21", + "VPERMILPD $-1, Z0, Z1", + "VPERMILPS X0, X1", + "VPERMILPD X0, Y1, Y2", + "VPERMILPS X0, X1, (AX)", + "VPERMILPD.BCST X0, X1, X2", + "VPERMILPS.BCST $7, X0, X1", + "VPERMILPD.Z $7, X0, X1", + "VPERMILPS X0, X1, K0, X2", + "VPERMILPD.SAE X0, X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86InLaneFloatingPermuteRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + + for _, instruction := range []string{ + "VPERMILPS $7, Z8, Z0", + "VPERMILPD Z0, Z1, Z8", + "VPERMILPS $-1, X20, X21", + "VPERMILPD X0, X1, K1, X2", + "VPERMILPS.Z $7, X0, K1, X2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86InLaneFloatingPermuteRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86InLaneFloatingPermuteRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yvpermilpd forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_permute_qword.go b/amd64_lower_permute_qword.go new file mode 100644 index 00000000..d726af93 --- /dev/null +++ b/amd64_lower_permute_qword.go @@ -0,0 +1,180 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerQwordPermute implements the complete Go 1.27 _yvpermq operand family +// shared by VPERMQ and VPERMPD. It includes immediate-control VEX/EVEX forms +// and variable-control EVEX forms; both preserve qword bits. +func (c *amd64Ctx) lowerQwordPermute(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + switch baseOp { + case "VPERMQ", "VPERMPD": + default: + return false, false, nil + } + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's _yvpermq encodings: %q", c.goarch, baseOp, ins.Raw) + } + immediate := len(ins.Args) != 0 && ins.Args[0].Kind == OpImm + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects immediate/data, control, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be Y or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s destination must be Y or Z: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoQwordPermuteVector(dstArg, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's vector range: %q", c.goarch, baseOp, ins.Raw) + } + + dataArg := ins.Args[0] + controlArg := ins.Args[1] + var imm uint8 + if immediate { + dataArg = ins.Args[1] + value := ins.Args[0].Imm + if value < -128 || value > 255 { + return true, false, fmt.Errorf("%s %s immediate is outside Go 1.27's signed-or-unsigned imm8 classes: %q", c.goarch, baseOp, ins.Raw) + } + imm = uint8(value) + if value < 0 { + if masked || suffix != "" || byteWidth != 32 || !amd64VEXVectorRegister(dstArg, byteWidth) { + return true, false, fmt.Errorf("%s %s signed imm8 exists only in the VEX Y form: %q", c.goarch, baseOp, ins.Raw) + } + if dataArg.Kind == OpReg && !amd64VEXVectorRegister(dataArg, byteWidth) { + return true, false, fmt.Errorf("%s %s signed imm8 source is outside the VEX Y range: %q", c.goarch, baseOp, ins.Raw) + } + } + } else if !c.isGoQwordPermuteVector(controlArg, byteWidth) { + return true, false, fmt.Errorf("%s %s variable control and destination must be matching Y or Z registers: %q", c.goarch, baseOp, ins.Raw) + } + + if broadcast { + if !isAMD64MemoryOperand(dataArg) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory data source: %q", c.goarch, baseOp, ins.Raw) + } + } else if dataArg.Kind == OpReg { + if !c.isGoQwordPermuteVector(dataArg, byteWidth) { + return true, false, fmt.Errorf("%s %s data register must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(dataArg) { + return true, false, fmt.Errorf("%s %s data must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + } + lanes := byteWidth / 8 + var data string + if broadcast { + scalar, err := c.evalIntSized(dataArg, I64) + if err != nil { + return true, false, err + } + data = amd64SplatInteger(c, lanes, 64, scalar) + } else { + dataBytes, err := c.loadPackedCompareBytes(dataArg, byteWidth) + if err != nil { + return true, false, err + } + data = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 64, dataBytes) + } + var result string + if immediate { + result = c.emitImmediateQwordPermute(data, lanes, imm) + } else { + controlBytes, err := c.loadPackedCompareBytes(controlArg, byteWidth) + if err != nil { + return true, false, err + } + control := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 64, controlBytes) + result = c.emitVariableQwordPermute(data, control, lanes) + } + if masked { + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 64, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, 64, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", out, lanes, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) isGoQwordPermuteVector(arg Operand, byteWidth int) bool { + if !amd64EVEXVectorRegister(arg, byteWidth) { + return false + } + if c.goarch == "386" && byteWidth == 64 { + index, _ := amd64VectorRegisterIndex(arg.Reg, byteWidth) + return index < 8 + } + return true +} + +func (c *amd64Ctx) emitImmediateQwordPermute(data string, lanes int, imm uint8) string { + result := "poison" + for lane := 0; lane < lanes; lane++ { + groupBase := lane / 4 * 4 + selector := int(imm>>uint(2*(lane%4))) & 3 + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %s, i32 %d\n", value, lanes, data, groupBase+selector) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i64> %s, i64 %%%s, i32 %d\n", inserted, lanes, result, value, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) emitVariableQwordPermute(data, control string, lanes int) string { + result := "poison" + for lane := 0; lane < lanes; lane++ { + index := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %s, i32 %d\n", index, lanes, control, lane) + maskedIndex := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, %d\n", maskedIndex, index, lanes-1) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %s, i64 %%%s\n", value, lanes, data, maskedIndex) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i64> %s, i64 %%%s, i32 %d\n", inserted, lanes, result, value, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_permute_two_source.go b/amd64_lower_permute_two_source.go new file mode 100644 index 00000000..66b7c3e0 --- /dev/null +++ b/amd64_lower_permute_two_source.go @@ -0,0 +1,238 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64IndexedPermuteMode uint8 + +const ( + amd64IndexedPermuteSingle amd64IndexedPermuteMode = iota + amd64IndexedPermuteI2 + amd64IndexedPermuteT2 +) + +type amd64IndexedPermuteSpec struct { + laneBits int + mode amd64IndexedPermuteMode + broadcast bool +} + +// amd64IndexedPermuteSpecs models the complete Go 1.27 _yvblendmpd grammar +// for the single-table VPERMB/W and both two-table VPERMI2*/VPERMT2* +// families. Broadcast capability is an opcode property, not a consequence of +// lane width alone. +var amd64IndexedPermuteSpecs = map[Op]amd64IndexedPermuteSpec{ + "VPERMB": {laneBits: 8, mode: amd64IndexedPermuteSingle}, + "VPERMW": {laneBits: 16, mode: amd64IndexedPermuteSingle}, + "VPERMI2B": {laneBits: 8, mode: amd64IndexedPermuteI2}, + "VPERMI2W": {laneBits: 16, mode: amd64IndexedPermuteI2}, + "VPERMI2D": {laneBits: 32, mode: amd64IndexedPermuteI2, broadcast: true}, + "VPERMI2PS": {laneBits: 32, mode: amd64IndexedPermuteI2, broadcast: true}, + "VPERMI2Q": {laneBits: 64, mode: amd64IndexedPermuteI2, broadcast: true}, + "VPERMI2PD": {laneBits: 64, mode: amd64IndexedPermuteI2, broadcast: true}, + "VPERMT2B": {laneBits: 8, mode: amd64IndexedPermuteT2}, + "VPERMT2W": {laneBits: 16, mode: amd64IndexedPermuteT2}, + "VPERMT2D": {laneBits: 32, mode: amd64IndexedPermuteT2, broadcast: true}, + "VPERMT2PS": {laneBits: 32, mode: amd64IndexedPermuteT2, broadcast: true}, + "VPERMT2Q": {laneBits: 64, mode: amd64IndexedPermuteT2, broadcast: true}, + "VPERMT2PD": {laneBits: 64, mode: amd64IndexedPermuteT2, broadcast: true}, +} + +type amd64TwoSourcePermuteSuffixes struct { + broadcast bool + zeroing bool +} + +func amd64ParseTwoSourcePermuteSuffixes(rawOp, baseOp string) (amd64TwoSourcePermuteSuffixes, error) { + var suffixes amd64TwoSourcePermuteSuffixes + dot := strings.IndexByte(rawOp, '.') + if dot < 0 { + return suffixes, nil + } + parts := strings.Split(rawOp[dot+1:], ".") + for index, part := range parts { + switch part { + case "BCST": + if suffixes.broadcast || suffixes.zeroing || index != 0 { + return suffixes, fmt.Errorf("amd64 %s has invalid or duplicate .BCST suffix", baseOp) + } + suffixes.broadcast = true + case "Z": + if suffixes.zeroing || index != len(parts)-1 { + return suffixes, fmt.Errorf("amd64 %s has invalid or duplicate .Z suffix", baseOp) + } + suffixes.zeroing = true + default: + return suffixes, fmt.Errorf("amd64 %s has unsupported suffix .%s", baseOp, part) + } + } + return suffixes, nil +} + +// lowerIndexedPermute implements Go 1.27's complete single- and two-table +// indexed-permute family. +func (c *amd64Ctx) lowerIndexedPermute(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, ok := amd64IndexedPermuteSpecs[Op(baseOp)] + if !ok { + return false, false, nil + } + suffixes, err := amd64ParseTwoSourcePermuteSuffixes(rawOp, baseOp) + if err != nil { + return true, false, fmt.Errorf("%w: %q", err, ins.Raw) + } + if suffixes.broadcast && !spec.broadcast { + return true, false, fmt.Errorf("amd64 %s does not enable broadcast in Go 1.27: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 %s expects first source, second source, [K mask,] destination: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if masked && c.goarch == "386" { + return true, false, fmt.Errorf("386 %s masked form exceeds the Go assembler frontend's operand limit: %q", baseOp, ins.Raw) + } + if suffixes.zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + byteWidth := 0 + if destination.Kind == OpReg { + byteWidth = amd64VectorByteWidth(destination.Reg) + } + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s expects an in-range X, Y, or Z destination: %q", baseOp, ins.Raw) + } + second := ins.Args[1] + if !c.isGoPackedVectorMoveRegister(second, byteWidth) { + return true, false, fmt.Errorf("amd64 %s second source must match the destination width: %q", baseOp, ins.Raw) + } + first := ins.Args[0] + if first.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(first, byteWidth) { + return true, false, fmt.Errorf("amd64 %s first source register must match the destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 %s first source must be a matching vector register or memory: %q", baseOp, ins.Raw) + } + if suffixes.broadcast && !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory first source: %q", baseOp, ins.Raw) + } + + mask := "" + if masked { + maskArg := ins.Args[2] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, validMask := amd64ParseKReg(maskArg.Reg) + if !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + lanes := byteWidth * 8 / spec.laneBits + firstValue, err := c.loadPackedCompareLanes(first, byteWidth, spec.laneBits, suffixes.broadcast) + if err != nil { + return true, false, err + } + secondValue, err := c.loadPackedCompareLanes(second, byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + computed := "" + switch spec.mode { + case amd64IndexedPermuteSingle: + // Plan 9 lists Intel's r/m table first and its index vector second. + computed = c.emitSingleTablePermute(lanes, spec.laneBits, firstValue, secondValue) + case amd64IndexedPermuteI2: + // VPERMI2 gets indices from the old destination. Intel calls the + // Plan 9 second operand table 0 and the first operand table 1. + computed = c.emitTwoTablePermute(lanes, spec.laneBits, secondValue, firstValue, old) + case amd64IndexedPermuteT2: + // VPERMT2 gets indices from the Plan 9 second operand. The old + // destination is table 0 and the Plan 9 first operand is table 1. + computed = c.emitTwoTablePermute(lanes, spec.laneBits, old, firstValue, secondValue) + } + if masked { + computed = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, computed, old, mask, suffixes.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, computed, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitSingleTablePermute(lanes, laneBits int, table, indices string) string { + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + indexValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", indexValue, lanes, laneBits, indices, lane) + bounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", bounded, laneBits, indexValue, lanes-1) + indexI32 := "%" + bounded + if laneBits < 32 { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i%d %%%s to i32\n", converted, laneBits, bounded) + indexI32 = "%" + converted + } else if laneBits > 32 { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i%d %%%s to i32\n", converted, laneBits, bounded) + indexI32 = "%" + converted + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %s\n", selected, lanes, laneBits, table, indexI32) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", inserted, lanes, laneBits, result, laneBits, selected, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) emitTwoTablePermute(lanes, laneBits int, table0, table1, indices string) string { + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + indexValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", indexValue, lanes, laneBits, indices, lane) + bounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", bounded, laneBits, indexValue, 2*lanes-1) + useTable1 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp uge i%d %%%s, %d\n", useTable1, laneBits, bounded, lanes) + withinTable := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", withinTable, laneBits, bounded, lanes-1) + indexI32 := "%" + withinTable + if laneBits < 32 { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i%d %%%s to i32\n", converted, laneBits, withinTable) + indexI32 = "%" + converted + } else if laneBits > 32 { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i%d %%%s to i32\n", converted, laneBits, withinTable) + indexI32 = "%" + converted + } + fromTable0 := c.newTmp() + fromTable1 := c.newTmp() + selected := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %s\n", fromTable0, lanes, laneBits, table0, indexI32) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %s\n", fromTable1, lanes, laneBits, table1, indexI32) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", selected, useTable1, laneBits, fromTable1, laneBits, fromTable0) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", inserted, lanes, laneBits, result, laneBits, selected, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_permute_two_source_test.go b/amd64_lower_permute_two_source_test.go new file mode 100644 index 00000000..f81d75b0 --- /dev/null +++ b/amd64_lower_permute_two_source_test.go @@ -0,0 +1,109 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86TwoSourcePermuteCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 shares _yvblendmpd across VPERMI2{B,W,D,Q,PS,PD}: matching + // X/Y/Z sources and destination, optional K1-K7 masking, and .Z. The + // D/Q/PS/PD forms also accept .BCST on a memory first source. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastZ := 20 + if target.goarch == "386" { + lastZ = 7 + } + var source strings.Builder + source.WriteString("TEXT twosourcepermuteforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VPERMI2B", "VPERMI2W", "VPERMI2D", "VPERMI2Q", "VPERMI2PS", "VPERMI2PD"} { + fmt.Fprintf(&source, "\t%s X1, X20, X21\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), Y20, Y21\n", op) + fmt.Fprintf(&source, "\t%s Z1, Z2, Z%d\n", op, lastZ) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s X1, X20, K1, X21\n", op) + fmt.Fprintf(&source, "\t%s.Z Y1, Y20, K2, Y21\n", op) + fmt.Fprintf(&source, "\t%s.Z 40(AX), Z20, K3, Z21\n", op) + } + if strings.HasSuffix(op, "D") || strings.HasSuffix(op, "Q") || strings.HasSuffix(op, "PS") || strings.HasSuffix(op, "PD") { + fmt.Fprintf(&source, "\t%s.BCST 104(AX), X20, X21\n", op) + fmt.Fprintf(&source, "\t%s.BCST 112(AX), Y20, Y21\n", op) + fmt.Fprintf(&source, "\t%s.BCST 120(AX), Z2, Z%d\n", op, lastZ) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.BCST.Z 128(AX), Z20, K4, Z21\n", op) + } + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "twosourcepermuteforms": {Name: "twosourcepermuteforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "two-source-permute-"+target.name+".ll", "two-source-permute-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86TwoSourcePermuteRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPERMI2D X0, X1", + "VPERMI2D X0, Y1, Y2", + "VPERMI2D X0, (AX), X2", + "VPERMI2D X0, X1, K0, X2", + "VPERMI2D X0, X1, AX", + "VPERMI2D.Z X0, X1, X2", + "VPERMI2D.BCST X0, X1, X2", + "VPERMI2B.BCST (AX), X1, X2", + "VPERMI2W.BCST (AX), X1, X2", + "VPERMI2D.Z.BCST (AX), X1, K1, X2", + "VPERMI2D.RN_SAE X0, X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86TwoSourcePermuteRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + assertX86TwoSourcePermuteRejected(t, "386", "i386-unknown-linux-gnu", "VPERMI2D X0, X1, K1, X2") + assertX86TwoSourcePermuteRejected(t, "386", "i386-unknown-linux-gnu", "VPERMI2D Z0, Z1, Z8") +} + +func assertX86TwoSourcePermuteRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VPERMI2 forms", instruction) + } +} diff --git a/amd64_lower_popcount_vector.go b/amd64_lower_popcount_vector.go new file mode 100644 index 00000000..fd08c8f8 --- /dev/null +++ b/amd64_lower_popcount_vector.go @@ -0,0 +1,122 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedBitCountKind uint8 + +const ( + amd64PackedPopulationCount amd64PackedBitCountKind = iota + amd64PackedLeadingZeroCount +) + +type amd64PackedBitCountSpec struct { + laneBits int + kind amd64PackedBitCountKind + broadcast bool +} + +// amd64PackedBitCountSpecs models the complete Go 1.27 _yvexpandpd grammar +// for packed population-count and leading-zero-count instructions. +var amd64PackedBitCountSpecs = map[Op]amd64PackedBitCountSpec{ + "VPOPCNTB": {laneBits: 8, kind: amd64PackedPopulationCount}, + "VPOPCNTW": {laneBits: 16, kind: amd64PackedPopulationCount}, + "VPOPCNTD": {laneBits: 32, kind: amd64PackedPopulationCount, broadcast: true}, + "VPOPCNTQ": {laneBits: 64, kind: amd64PackedPopulationCount, broadcast: true}, + "VPLZCNTD": {laneBits: 32, kind: amd64PackedLeadingZeroCount, broadcast: true}, + "VPLZCNTQ": {laneBits: 64, kind: amd64PackedLeadingZeroCount, broadcast: true}, +} + +// lowerPackedBitCount implements X/Y/Z register or memory sources, K1-K7 +// merge and .Z, and each opcode's scalar-memory broadcast forms. +func (c *amd64Ctx) lowerPackedBitCount(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, ok := amd64PackedBitCountSpecs[Op(baseOp)] + if !ok { + return false, false, nil + } + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s has a suffix outside Go 1.27's _yvexpandpd form: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast && !spec.broadcast { + return true, false, fmt.Errorf("%s %s has no broadcast form: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects source, [K1-K7,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s.Z requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s requires an X, Y, or Z destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth == 0 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go's EVEX register range: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[0] + if broadcast { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) && !c.isGoEVEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source must be matching X/Y/Z register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + mask := "" + if masked { + maskArg := ins.Args[1] + maskIndex, valid := amd64ParseKReg(maskArg.Reg) + if maskArg.Kind != OpReg || !valid || maskIndex == 0 { + return true, false, fmt.Errorf("%s %s masked form requires K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + lanes := byteWidth * 8 / spec.laneBits + sourceValue, err := c.loadPackedCompareLanes(source, byteWidth, spec.laneBits, broadcast) + if err != nil { + return true, false, err + } + computed := c.newTmp() + if spec.kind == amd64PackedLeadingZeroCount { + fmt.Fprintf(c.b, " %%%s = call <%d x i%d> @llvm.ctlz.v%di%d(<%d x i%d> %s, i1 false)\n", + computed, lanes, spec.laneBits, lanes, spec.laneBits, lanes, spec.laneBits, sourceValue) + } else { + fmt.Fprintf(c.b, " %%%s = call <%d x i%d> @llvm.ctpop.v%di%d(<%d x i%d> %s)\n", + computed, lanes, spec.laneBits, lanes, spec.laneBits, lanes, spec.laneBits, sourceValue) + } + result := "%" + computed + if masked { + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} diff --git a/amd64_lower_popcount_vector_test.go b/amd64_lower_popcount_vector_test.go new file mode 100644 index 00000000..11d6d9d4 --- /dev/null +++ b/amd64_lower_popcount_vector_test.go @@ -0,0 +1,212 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86PackedPopcountCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT packedpopcountforms(SB),$0-0\n") + for _, op := range []string{"VPOPCNTB", "VPOPCNTW", "VPOPCNTD", "VPOPCNTQ"} { + for _, width := range []string{"X", "Y", "Z"} { + last := 22 + if target.goarch == "386" && width == "Z" { + last = 7 + } + fmt.Fprintf(&source, "\t%s %s0, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s 8(AX), %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s %s0, K1, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s.Z 8(AX), K7, %s%d\n", op, width, last) + if op == "VPOPCNTD" || op == "VPOPCNTQ" { + fmt.Fprintf(&source, "\t%s.BCST 8(AX), %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST.Z 8(AX), K2, %s%d\n", op, width, last) + } + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedpopcountforms": {Name: "packedpopcountforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-popcount-"+target.name+".ll", "packed-popcount-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedPopcountRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPOPCNTB.BCST 8(AX), X1", + "VPOPCNTW.BCST 8(AX), Z1", + "VPOPCNTD.BCST X0, X1", + "VPOPCNTQ X0, Y1", + "VPOPCNTB X0, K0, X1", + "VPOPCNTW.Z X0, X1", + "VPOPCNTD.SAE X0, X1", + "VPOPCNTQ X0, 8(AX)", + "VPOPCNTB AX, X1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + if currentGoMinorAtLeast(27) { + requireX86GoAssemblerResult(t, "amd64", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + } + assertX86PackedPopcountRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "VPOPCNTD Z8, K1, Z0", + "VPOPCNTQ Z0, Z8", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + if currentGoMinorAtLeast(27) { + requireX86GoAssemblerResult(t, "386", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + } + assertX86PackedPopcountRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedPopcountRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yvexpandpd forms for %s", instruction, goarch) + } +} + +func TestAMD64PackedPopcountRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT packedpopcount(SB),$0-32 + MOVQ out+0(FP), AX + MOVQ source+8(FP), BX + MOVQ old+16(FP), CX + MOVQ mask+24(FP), DX + KMOVQ DX, K1 + VMOVDQU64 (BX), Z0 + VMOVDQU64 (CX), Z1 + VPOPCNTB Z0, Z2 + VMOVDQU64 Z2, 0(AX) + VPOPCNTW Z0, K1, Z1 + VMOVDQU64 Z1, 64(AX) + VPOPCNTD.Z Z0, K1, Z1 + VMOVDQU64 Z1, 128(AX) + VPOPCNTQ (BX), Z2 + VMOVDQU64 Z2, 192(AX) + VPOPCNTD.BCST (BX), Z2 + VMOVDQU64 Z2, 256(AX) + VPOPCNTQ.BCST.Z (BX), K1, Z1 + VMOVDQU64 Z1, 320(AX) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: I64, Index: 3, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "packedpopcount": {Name: "packedpopcount", Args: []LLVMType{Ptr, Ptr, Ptr, I64}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +#include +extern void packedpopcount(uint8_t *, const uint8_t *, const uint8_t *, uint64_t); +static unsigned pop64(uint64_t v) { + unsigned n = 0; + while (v) { n += v & 1; v >>= 1; } + return n; +} +int main(void) { + uint8_t source[64], old[64], out[384]; + const uint64_t mask = 0xa55a5aa5ULL; + for (int i = 0; i < 64; i++) { source[i] = (uint8_t)(i * 37 + 11); old[i] = (uint8_t)(0xe0 - i); } + memset(out, 0xcc, sizeof(out)); + packedpopcount(out, source, old, mask); + for (int i = 0; i < 64; i++) if (out[i] != pop64(source[i])) return 10 + i; + for (int i = 0; i < 32; i++) { + uint16_t src, prior, got; memcpy(&src, source+2*i, 2); memcpy(&prior, old+2*i, 2); memcpy(&got, out+64+2*i, 2); + uint16_t want = (mask >> i) & 1 ? (uint16_t)pop64(src) : prior; + if (got != want) return 80 + i; + } + for (int i = 0; i < 16; i++) { + uint32_t src, got; memcpy(&src, source+4*i, 4); memcpy(&got, out+128+4*i, 4); + uint32_t want = (mask >> i) & 1 ? pop64(src) : 0; + if (got != want) return 120 + i; + } + for (int i = 0; i < 8; i++) { + uint64_t src, got; memcpy(&src, source+8*i, 8); memcpy(&got, out+192+8*i, 8); + if (got != pop64(src)) return 150 + i; + } + uint32_t first32; memcpy(&first32, source, 4); + for (int i = 0; i < 16; i++) { uint32_t got; memcpy(&got, out+256+4*i, 4); if (got != pop64(first32)) return 170 + i; } + uint64_t first64; memcpy(&first64, source, 8); + for (int i = 0; i < 8; i++) { uint64_t got; memcpy(&got, out+320+8*i, 8); uint64_t want = (mask >> i) & 1 ? pop64(first64) : 0; if (got != want) return 190 + i; } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_popcount", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_portio.go b/amd64_lower_portio.go new file mode 100644 index 00000000..c48177ec --- /dev/null +++ b/amd64_lower_portio.go @@ -0,0 +1,159 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func x86PortScalarProperties(op Op) (input bool, typ LLVMType, ok bool) { + switch strings.ToUpper(string(op)) { + case "INB": + return true, I8, true + case "INW": + return true, I16, true + case "INL": + return true, I32, true + case "OUTB": + return false, I8, true + case "OUTW": + return false, I16, true + case "OUTL": + return false, I32, true + default: + return false, "", false + } +} + +func x86PortStringProperties(op Op) (input bool, width int, ok bool) { + switch strings.ToUpper(string(op)) { + case "INSB": + return true, 1, true + case "INSW": + return true, 2, true + case "INSL": + return true, 4, true + case "OUTSB": + return false, 1, true + case "OUTSW": + return false, 2, true + case "OUTSL": + return false, 4, true + default: + return false, 0, false + } +} + +// lowerPortIO implements the complete x86 port-I/O rows in Go's yin and +// ynone operand tables. These instructions are inherently target-specific, so +// preserving them as constrained LLVM inline assembly is both more accurate +// and safer than pretending that they are ordinary memory accesses. +func (c *amd64Ctx) lowerPortIO(op Op, ins Instr) (ok bool, terminated bool, err error) { + if input, typ, scalar := x86PortScalarProperties(op); scalar { + if c.repeatPrefix != "" { + prefix := c.repeatPrefix + c.repeatPrefix = "" + return true, false, fmt.Errorf("%s %s prefix is unsupported for %s", c.goarch, prefix, op) + } + if len(ins.Args) > 1 || (len(ins.Args) == 1 && ins.Args[0].Kind != OpImm) { + return true, false, fmt.Errorf("%s %s expects no operand or one immediate: %q", c.goarch, op, ins.Raw) + } + if len(ins.Args) == 1 && (ins.Args[0].Imm < -1<<31 || ins.Args[0].Imm > 1<<32-1) { + return true, false, fmt.Errorf("%s %s immediate is outside the Go assembler's 32-bit form: %q", c.goarch, op, ins.Raw) + } + return true, false, c.lowerScalarPortIO(strings.ToLower(string(op)), input, typ, ins.Args) + } + + input, _, stringOp := x86PortStringProperties(op) + if !stringOp { + return false, false, nil + } + prefix := c.repeatPrefix + c.repeatPrefix = "" + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, op, ins.Raw) + } + return true, false, c.lowerStringPortIO(strings.ToLower(string(op)), input, prefix) +} + +func (c *amd64Ctx) lowerScalarPortIO(asm string, input bool, typ LLVMType, args []Operand) error { + constraints := "~{dirflag},~{fpsr},~{flags}" + if input { + call := c.newTmp() + if len(args) == 0 { + port, err := c.evalIntSized(Operand{Kind: OpReg, Reg: DX}, I16) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(i16 %s)\n", call, typ, asm+" $1, $0", "={ax},{dx},"+constraints, port) + } else { + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q()\n", call, typ, fmt.Sprintf("%s $$%d, $0", asm, int64(args[0].Imm)), "={ax},"+constraints) + } + return c.storeRegSized(AX, typ, "%"+call) + } + + value, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, typ) + if err != nil { + return err + } + if len(args) == 0 { + port, err := c.evalIntSized(Operand{Kind: OpReg, Reg: DX}, I16) + if err != nil { + return err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s %s, i16 %s)\n", asm+" $0, $1", "{ax},{dx},"+constraints, typ, value, port) + return nil + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s %s)\n", fmt.Sprintf("%s $0, $$%d", asm, int64(args[0].Imm)), "{ax},"+constraints, typ, value) + return nil +} + +func (c *amd64Ctx) lowerStringPortIO(asm string, input bool, prefix string) error { + indexReg := SI + indexConstraint := "{si}" + if input { + indexReg = DI + indexConstraint = "{di}" + } + index, err := c.loadReg(indexReg) + if err != nil { + return err + } + port, err := c.evalIntSized(Operand{Kind: OpReg, Reg: DX}, I16) + if err != nil { + return err + } + wordType := I64 + if c.goarch == "386" { + wordType = I32 + index = c.truncI64(index, I32) + } + clobbers := "~{memory},~{dirflag},~{fpsr},~{flags}" + if prefix == "" { + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(i16 %s, %s %s)\n", call, wordType, asm, "="+indexConstraint+",{dx},0,"+clobbers, port, wordType, index) + return c.storeRegSized(indexReg, wordType, "%"+call) + } + + count, err := c.loadReg(CX) + if err != nil { + return err + } + if c.goarch == "386" { + count = c.truncI64(count, I32) + } + call := c.newTmp() + resultType := fmt.Sprintf("{ %s, %s }", wordType, wordType) + asmPrefix := "rep" + if prefix == "REPN" { + asmPrefix = "repne" + } + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(i16 %s, %s %s, %s %s)\n", call, resultType, asmPrefix+"; "+asm, "="+indexConstraint+",={cx},{dx},0,1,"+clobbers, port, wordType, index, wordType, count) + nextIndex := c.newTmp() + nextCount := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 0\n", nextIndex, resultType, call) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 1\n", nextCount, resultType, call) + if err := c.storeRegSized(indexReg, wordType, "%"+nextIndex); err != nil { + return err + } + return c.storeRegSized(CX, wordType, "%"+nextCount) +} diff --git a/amd64_lower_qword_bit_lookup.go b/amd64_lower_qword_bit_lookup.go new file mode 100644 index 00000000..dd957582 --- /dev/null +++ b/amd64_lower_qword_bit_lookup.go @@ -0,0 +1,189 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64QwordBitLookupOutput uint8 + +const ( + amd64QwordBitLookupBytes amd64QwordBitLookupOutput = iota + amd64QwordBitLookupMask +) + +type amd64QwordBitLookupSpec struct { + output amd64QwordBitLookupOutput + broadcast bool +} + +// amd64QwordBitLookupSpecs groups the two AVX-512 byte-control operations +// that select bits inside corresponding qword lanes. They share the same core +// rotate/lookup grammar but produce either bytes or a packed K mask. +var amd64QwordBitLookupSpecs = map[Op]amd64QwordBitLookupSpec{ + "VPMULTISHIFTQB": {output: amd64QwordBitLookupBytes, broadcast: true}, + "VPSHUFBITQMB": {output: amd64QwordBitLookupMask}, +} + +func (c *amd64Ctx) lowerQwordBitLookup(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64QwordBitLookupSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + + suffixes, err := amd64ParseTwoSourcePermuteSuffixes(rawOp, baseOp) + if err != nil { + return true, false, fmt.Errorf("%w: %q", err, ins.Raw) + } + if spec.output == amd64QwordBitLookupMask && (suffixes.broadcast || suffixes.zeroing) { + return true, false, fmt.Errorf("%s %s has no instruction suffixes in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if suffixes.broadcast && !spec.broadcast { + return true, false, fmt.Errorf("%s %s does not support broadcast: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects first source, second source, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s masked form exceeds the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if suffixes.zeroing && !masked { + return true, false, fmt.Errorf("%s %s.Z requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("%s %s masked form requires K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + + first, second := ins.Args[0], ins.Args[1] + destination := ins.Args[len(ins.Args)-1] + byteWidth := 0 + switch spec.output { + case amd64QwordBitLookupBytes: + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth = amd64VectorByteWidth(destination.Reg) + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's vector class: %q", c.goarch, baseOp, ins.Raw) + } + case amd64QwordBitLookupMask: + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be K0-K7: %q", c.goarch, baseOp, ins.Raw) + } + if _, valid := amd64ParseKReg(destination.Reg); !valid { + return true, false, fmt.Errorf("%s %s destination must be K0-K7: %q", c.goarch, baseOp, ins.Raw) + } + if second.Kind == OpReg { + byteWidth = amd64VectorByteWidth(second.Reg) + } + } + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(second, byteWidth) { + return true, false, fmt.Errorf("%s %s second source must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + if first.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(first, byteWidth) { + return true, false, fmt.Errorf("%s %s first source register must match the vector width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("%s %s first source must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if suffixes.broadcast && !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory qword source: %q", c.goarch, baseOp, ins.Raw) + } + + var dataQwords, controls string + switch spec.output { + case amd64QwordBitLookupBytes: + dataQwords, err = c.loadPackedCompareLanes(first, byteWidth, 64, suffixes.broadcast) + if err == nil { + controls, err = c.loadPackedCompareBytes(second, byteWidth) + } + case amd64QwordBitLookupMask: + dataQwords, err = c.loadPackedCompareLanes(second, byteWidth, 64, false) + if err == nil { + controls, err = c.loadPackedCompareBytes(first, byteWidth) + } + } + if err != nil { + return true, false, err + } + selectedBytes := c.emitQwordBitLookupBytes(byteWidth, dataQwords, controls) + + var writeMask string + if masked { + writeMask, err = c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + } + if spec.output == amd64QwordBitLookupBytes { + if masked { + old, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + selectedBytes = amd64ApplyIntegerLaneMask(c, byteWidth, 8, selectedBytes, old, writeMask, suffixes.zeroing) + } + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, selectedBytes) + } + + ones := c.newTmp() + predicates := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and <%d x i8> %s, %s\n", ones, byteWidth, selectedBytes, llvmSplatInteger(byteWidth, 8, 1)) + fmt.Fprintf(c.b, " %%%s = icmp ne <%d x i8> %%%s, zeroinitializer\n", predicates, byteWidth, ones) + packedType := fmt.Sprintf("i%d", byteWidth) + packed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i1> %%%s to %s\n", packed, byteWidth, predicates, packedType) + result := "%" + packed + if byteWidth < 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to i64\n", wide, packedType, result) + result = "%" + wide + } + if masked { + maskedResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %s\n", maskedResult, result, writeMask) + result = "%" + maskedResult + } + return true, false, c.storeK(destination.Reg, result) +} + +// emitQwordBitLookupBytes rotates each corresponding data qword right by the +// low six bits of a control byte. Its low byte is VPMULTISHIFTQB's result; +// its low bit is VPSHUFBITQMB's gathered mask bit. +func (c *amd64Ctx) emitQwordBitLookupBytes(byteWidth int, dataQwords, controls string) string { + result := "zeroinitializer" + qwords := byteWidth / 8 + for lane := 0; lane < byteWidth; lane++ { + data := c.newTmp() + controlByte := c.newTmp() + controlWide := c.newTmp() + control := c.newTmp() + right := c.newTmp() + negated := c.newTmp() + wrappedLeftCount := c.newTmp() + left := c.newTmp() + rotated := c.newTmp() + selected := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %s, i32 %d\n", data, qwords, dataQwords, lane/8) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i8> %s, i32 %d\n", controlByte, byteWidth, controls, lane) + fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i64\n", controlWide, controlByte) + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, 63\n", control, controlWide) + fmt.Fprintf(c.b, " %%%s = lshr i64 %%%s, %%%s\n", right, data, control) + fmt.Fprintf(c.b, " %%%s = sub i64 0, %%%s\n", negated, control) + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, 63\n", wrappedLeftCount, negated) + fmt.Fprintf(c.b, " %%%s = shl i64 %%%s, %%%s\n", left, data, wrappedLeftCount) + fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", rotated, right, left) + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i8\n", selected, rotated) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i8> %s, i8 %%%s, i32 %d\n", inserted, byteWidth, result, selected, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_qword_bit_lookup_test.go b/amd64_lower_qword_bit_lookup_test.go new file mode 100644 index 00000000..b94e5e10 --- /dev/null +++ b/amd64_lower_qword_bit_lookup_test.go @@ -0,0 +1,219 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64QwordBitLookupGrammarCoversCompleteGoFamilies(t *testing.T) { + expected := map[Op]amd64QwordBitLookupSpec{ + "VPMULTISHIFTQB": {output: amd64QwordBitLookupBytes, broadcast: true}, + "VPSHUFBITQMB": {output: amd64QwordBitLookupMask}, + } + if len(amd64QwordBitLookupSpecs) != len(expected) { + t.Fatalf("qword-bit-lookup grammar has %d entries, want %d", len(amd64QwordBitLookupSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64QwordBitLookupSpecs[op]; !ok { + t.Errorf("qword-bit-lookup grammar omitted %s", op) + } else if got != want { + t.Errorf("qword-bit-lookup grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86QwordBitLookupCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT qwordbitlookupforms(SB),$0-0\n") + for _, width := range []string{"X", "Y", "Z"} { + last := 31 + if target.goarch == "386" && width == "Z" { + last = 7 + } + fmt.Fprintf(&source, "\tVPMULTISHIFTQB %s1, %s2, %s%d\n", width, width, width, last) + fmt.Fprintf(&source, "\tVPMULTISHIFTQB 8(AX), %s2, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVPMULTISHIFTQB.BCST 16(AX), %s2, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVPSHUFBITQMB %s1, %s2, K0\n", width, width) + fmt.Fprintf(&source, "\tVPSHUFBITQMB 24(AX), %s2, K7\n", width) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\tVPMULTISHIFTQB %s1, %s2, K1, %s%d\n", width, width, width, last) + fmt.Fprintf(&source, "\tVPMULTISHIFTQB.Z 32(AX), %s2, K2, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVPMULTISHIFTQB.BCST.Z 40(AX), %s2, K3, %s%d\n", width, width, last) + fmt.Fprintf(&source, "\tVPSHUFBITQMB %s1, %s2, K4, K7\n", width, width) + fmt.Fprintf(&source, "\tVPSHUFBITQMB 48(AX), %s2, K5, K6\n", width) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"qwordbitlookupforms": {Name: "qwordbitlookupforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "qword-bit-lookup-"+target.name+".ll", "qword-bit-lookup-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86QwordBitLookupRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VPMULTISHIFTQB X0, Y1, Y2"}, + {goarch: "amd64", instruction: "VPMULTISHIFTQB.BCST X0, X1, X2"}, + {goarch: "amd64", instruction: "VPMULTISHIFTQB.Z X0, X1, X2"}, + {goarch: "amd64", instruction: "VPMULTISHIFTQB X0, X1, K0, X2"}, + {goarch: "amd64", instruction: "VPMULTISHIFTQB X0, X1, 0(AX)"}, + {goarch: "amd64", instruction: "VPSHUFBITQMB.Z X0, X1, K2"}, + {goarch: "amd64", instruction: "VPSHUFBITQMB.BCST 0(AX), X1, K2"}, + {goarch: "amd64", instruction: "VPSHUFBITQMB X0, Y1, K2"}, + {goarch: "amd64", instruction: "VPSHUFBITQMB X0, X1, K0, K2"}, + {goarch: "amd64", instruction: "VPSHUFBITQMB X0, X1, AX"}, + {goarch: "386", instruction: "VPMULTISHIFTQB X0, X1, K1, X2"}, + {goarch: "386", instruction: "VPSHUFBITQMB X0, X1, K1, K2"}, + {goarch: "386", instruction: "VPMULTISHIFTQB Z0, Z1, Z8"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's qword-bit-lookup table", test.instruction) + } + }) + } +} + +func TestAMD64QwordBitLookupRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT qwordbitlookupsemantics(SB),$0-40 + MOVQ out+0(FP), AX + MOVQ data+8(FP), BX + MOVQ controls+16(FP), CX + MOVQ old+24(FP), DX + MOVQ mask+32(FP), R8 + KMOVQ R8, K1 + VMOVDQU64 0(BX), Z0 + VMOVDQU64 0(CX), Z1 + VMOVDQU64 0(DX), Z2 + STC + VPMULTISHIFTQB Z0, Z1, Z3 + VMOVDQU64 Z3, 0(AX) + VPMULTISHIFTQB Z0, Z1, K1, Z2 + VMOVDQU64 Z2, 64(AX) + VPMULTISHIFTQB.Z Z0, Z1, K1, Z3 + VMOVDQU64 Z3, 128(AX) + VPMULTISHIFTQB.BCST 0(BX), Z1, Z3 + VMOVDQU64 Z3, 192(AX) + VPSHUFBITQMB Z1, Z0, K2 + KMOVQ K2, 256(AX) + VPSHUFBITQMB Z1, Z0, K1, K3 + KMOVQ K3, 264(AX) + SETCS 272(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"qwordbitlookupsemantics": { + Name: "qwordbitlookupsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: I64, Index: 4, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void qwordbitlookupsemantics(uint8_t *, const uint8_t *, const uint8_t *, const uint8_t *, uint64_t); +static uint64_t ror64(uint64_t value, unsigned count) { + count &= 63u; + return (value >> count) | (value << ((0u-count)&63u)); +} +static uint64_t load64(const uint8_t *p) { uint64_t v; memcpy(&v,p,8); return v; } +int main(void) { + uint64_t data64[8], controls64[8], old64[8], output64[35] = {0}; + uint8_t *data=(uint8_t *)data64, *controls=(uint8_t *)controls64; + uint8_t *old=(uint8_t *)old64, *out=(uint8_t *)output64; + const uint64_t mask=UINT64_C(0xa55af00ff00fa55a); + for (int q=0;q<8;q++) data64[q]=UINT64_C(0x0123456789abcdef)^((uint64_t)q*UINT64_C(0x11100f0e0d0c0b0a)); + for (int i=0;i<64;i++) { controls[i]=(uint8_t)(13u*(unsigned)i+((unsigned)i>>2)); old[i]=(uint8_t)(0xe0u-(unsigned)i); } + qwordbitlookupsemantics(out,data,controls,old,mask); + uint64_t gathered=0; + for (int i=0;i<64;i++) { + uint64_t qword=data64[i/8]; + uint8_t selected=(uint8_t)ror64(qword,controls[i]); + if (out[i]!=selected) return 10; + if (out[64+i]!=(((mask>>i)&1u)?selected:old[i])) return 11; + if (out[128+i]!=(((mask>>i)&1u)?selected:0)) return 12; + uint8_t broadcast=(uint8_t)ror64(data64[0],controls[i]); + if (out[192+i]!=broadcast) return 13; + gathered|=((qword>>(controls[i]&63u))&1u)<= 0 { + baseOp = rawOp[:dot] + } + + family := "" + bits := 0 + for _, candidate := range []string{"RDRAND", "RDSEED"} { + if !strings.HasPrefix(baseOp, candidate) { + continue + } + family = strings.ToLower(candidate) + switch strings.TrimPrefix(baseOp, candidate) { + case "W": + bits = 16 + case "L": + bits = 32 + case "Q": + bits = 64 + default: + return true, false, fmt.Errorf("%s %s requires a W, L, or Q width suffix: %q", c.goarch, candidate, ins.Raw) + } + break + } + if family == "" { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 1 || ins.Args[0].Kind != OpReg || !isX86YrlRegisterForArch(ins.Args[0].Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s expects one general register: %q", c.goarch, baseOp, ins.Raw) + } + + typ := amd64IntegerTypeForBits(bits) + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call { %s, i32 } @llvm.x86.%s.%d()\n", call, typ, family, bits) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue { %s, i32 } %%%s, 0\n", value, typ, call) + status := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue { %s, i32 } %%%s, 1\n", status, typ, call) + + // SP is a legal Yrl destination in Go's 386 table. This instruction is the + // modeled write itself, so permit storeRegSized to update the virtual SP. + previousAllowSPWrite := c.allowSPWrite + if c.goarch == "386" && ins.Args[0].Reg == SP { + c.allowSPWrite = true + } + err = c.storeRegSized(ins.Args[0].Reg, typ, "%"+value) + c.allowSPWrite = previousAllowSPWrite + if err != nil { + return true, false, err + } + + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne i32 %%%s, 0\n", carry, status) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", carry, c.flagsCFSlot) + for _, slot := range []string{c.flagsOFSlot, c.flagsSltSlot, c.flagsZSlot, c.flagsPFSlot} { + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", slot) + } + return true, false, nil +} diff --git a/amd64_lower_random_test.go b/amd64_lower_random_test.go new file mode 100644 index 00000000..7bf8c294 --- /dev/null +++ b/amd64_lower_random_test.go @@ -0,0 +1,149 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86RandomCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + goarch string + triple string + widths []string + registers []string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu", widths: []string{"W", "L"}, registers: []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}}, + {goarch: "386", triple: "i686-pc-windows-msvc", widths: []string{"W", "L"}, registers: []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}}, + {goarch: "amd64", triple: "x86_64-apple-darwin", widths: []string{"W", "L", "Q"}, registers: []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", widths: []string{"W", "L", "Q"}, registers: []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}}, + {goarch: "amd64", triple: "x86_64-pc-windows-msvc", widths: []string{"W", "L", "Q"}, registers: []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}}, + } { + t.Run(target.goarch+"/"+target.triple, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT randomforms(SB),$0-0\n") + for _, family := range []string{"RDRAND", "RDSEED"} { + for _, width := range target.widths { + for _, register := range target.registers { + fmt.Fprintf(&source, "\t%s%s %s\n", family, width, register) + } + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "randomforms": {Name: "randomforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "@llvm.x86.rdrand.16()", "@llvm.x86.rdrand.32()", + "@llvm.x86.rdseed.16()", "@llvm.x86.rdseed.32()", + `"target-features"="+rdrnd,+rdseed"`, + } { + if !strings.Contains(ll, want) { + t.Fatalf("random lowering omitted %q:\n%s", want, ll) + } + } + if target.goarch == "amd64" { + for _, want := range []string{"@llvm.x86.rdrand.64()", "@llvm.x86.rdseed.64()"} { + if !strings.Contains(ll, want) { + t.Fatalf("random lowering omitted %q:\n%s", want, ll) + } + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "x86-random.ll", "x86-random.o", ll) + }) + } +} + +func TestTranslateX86RandomRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "386", instruction: "RDRANDQ AX"}, + {goarch: "386", instruction: "RDSEEDQ AX"}, + {goarch: "386", instruction: "RDRANDL R8"}, + {goarch: "386", instruction: "RDSEEDW R8"}, + {goarch: "amd64", instruction: "RDRANDB AL"}, + {goarch: "amd64", instruction: "RDSEEDB AL"}, + {goarch: "amd64", instruction: "RDRANDQ 0(AX)"}, + {goarch: "amd64", instruction: "RDSEEDQ 0(AX)"}, + {goarch: "amd64", instruction: "RDRANDQ AX, DX"}, + {goarch: "amd64", instruction: "RDSEEDQ"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT badrandom(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{"badrandom": {Name: "badrandom", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go's RDRAND/RDSEED optab", test.instruction) + } + }) + } +} + +func TestX86RawDecoderNormalizesCompleteRandomFamily(t *testing.T) { + tests := []struct { + name string + code []byte + want Op + reg Reg + }{ + {name: "rdrand word low", code: []byte{0x66, 0x0f, 0xc7, 0xf2}, want: "RDRANDW", reg: DX}, + {name: "rdrand word extended", code: []byte{0x66, 0x41, 0x0f, 0xc7, 0xf3}, want: "RDRANDW", reg: Reg("R11")}, + {name: "rdrand long low", code: []byte{0x0f, 0xc7, 0xf2}, want: "RDRANDL", reg: DX}, + {name: "rdrand long extended", code: []byte{0x41, 0x0f, 0xc7, 0xf3}, want: "RDRANDL", reg: Reg("R11")}, + {name: "rdrand quad low", code: []byte{0x48, 0x0f, 0xc7, 0xf2}, want: "RDRANDQ", reg: DX}, + {name: "rdrand quad extended", code: []byte{0x49, 0x0f, 0xc7, 0xf3}, want: "RDRANDQ", reg: Reg("R11")}, + {name: "rdseed word low", code: []byte{0x66, 0x0f, 0xc7, 0xfa}, want: "RDSEEDW", reg: DX}, + {name: "rdseed word extended", code: []byte{0x66, 0x41, 0x0f, 0xc7, 0xfb}, want: "RDSEEDW", reg: Reg("R11")}, + {name: "rdseed long low", code: []byte{0x0f, 0xc7, 0xfa}, want: "RDSEEDL", reg: DX}, + {name: "rdseed long extended", code: []byte{0x41, 0x0f, 0xc7, 0xfb}, want: "RDSEEDL", reg: Reg("R11")}, + {name: "rdseed quad low", code: []byte{0x48, 0x0f, 0xc7, 0xfa}, want: "RDSEEDQ", reg: DX}, + {name: "rdseed quad extended", code: []byte{0x49, 0x0f, 0xc7, 0xfb}, want: "RDSEEDQ", reg: Reg("R11")}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + fn := Func{} + for _, value := range test.code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || got.Instrs[0].Op != test.want || len(got.Instrs[0].Args) != 1 || got.Instrs[0].Args[0].Reg != test.reg { + t.Fatalf("decoded %#x as %#v, want %s %s", test.code, got.Instrs, test.want, test.reg) + } + }) + } +} diff --git a/amd64_lower_range.go b/amd64_lower_range.go new file mode 100644 index 00000000..7952c946 --- /dev/null +++ b/amd64_lower_range.go @@ -0,0 +1,281 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64FloatingRangeSpec struct { + laneBits int + scalar bool +} + +// amd64FloatingRangeSpecs is the complete Go 1.27 VRANGE grammar. The +// immediate supplies the comparison and sign modes, so those orthogonal +// dimensions stay data instead of expanding into opcode-specific handlers. +var amd64FloatingRangeSpecs = map[Op]amd64FloatingRangeSpec{ + "VRANGEPS": {laneBits: 32}, + "VRANGEPD": {laneBits: 64}, + "VRANGESS": {laneBits: 32, scalar: true}, + "VRANGESD": {laneBits: 64, scalar: true}, +} + +func (c *amd64Ctx) lowerFloatingRange(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64FloatingRangeSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if c.goarch == "386" { + return true, false, fmt.Errorf("386 %s exceeds the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix || properties.rounding != "" { + return true, false, fmt.Errorf("%s %s has a suffix absent from Go 1.27's range optab: %q", c.goarch, baseOp, ins.Raw) + } + if spec.scalar && properties.broadcast { + return true, false, fmt.Errorf("%s %s scalar forms do not support broadcast: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 4 && len(ins.Args) != 5 { + return true, false, fmt.Errorf("%s %s expects immediate, source2, source1, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("%s %s immediate must be an unsigned byte: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 5 + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[3]) { + return true, false, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + + first, second := ins.Args[1], ins.Args[2] + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be a vector register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if spec.scalar { + if byteWidth != 16 { + return true, false, fmt.Errorf("%s %s scalar destination must be an X register: %q", c.goarch, baseOp, ins.Raw) + } + } else if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s packed destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoEVEXVectorRegister(destination, byteWidth) || !c.isGoEVEXVectorRegister(second, byteWidth) { + return true, false, fmt.Errorf("%s %s source1 and destination must be same-width Go vector registers: %q", c.goarch, baseOp, ins.Raw) + } + if properties.sae && !spec.scalar && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s packed SAE is available only for Z registers: %q", c.goarch, baseOp, ins.Raw) + } + if properties.broadcast { + if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory source2: %q", c.goarch, baseOp, ins.Raw) + } + } else if first.Kind == OpReg { + if !c.isGoEVEXVectorRegister(first, byteWidth) { + return true, false, fmt.Errorf("%s %s source2 register must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("%s %s source2 must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if properties.sae && first.Kind != OpReg { + return true, false, fmt.Errorf("%s %s.SAE requires a register source2: %q", c.goarch, baseOp, ins.Raw) + } + + mask := "" + if masked { + mask, err = c.loadK(ins.Args[3].Reg) + if err != nil { + return true, false, err + } + } + if spec.scalar { + return c.lowerScalarFloatingRange(spec, properties, ins, first, second, destination, mask) + } + return c.lowerPackedFloatingRange(spec, properties, ins, first, second, destination, byteWidth, mask) +} + +func (c *amd64Ctx) lowerPackedFloatingRange(spec amd64FloatingRangeSpec, properties amd64BinaryFloatingSuffix, ins Instr, first, second, destination Operand, byteWidth int, mask string) (bool, bool, error) { + lanes := byteWidth * 8 / spec.laneBits + source2, err := c.loadPackedCompareLanes(first, byteWidth, spec.laneBits, properties.broadcast) + if err != nil { + return true, false, err + } + source1, err := c.loadPackedCompareLanes(second, byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + result := c.emitFloatingRangeBits(lanes, spec.laneBits, source1, source2, uint8(ins.Args[0].Imm)) + if mask != "" { + oldBytes, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) lowerScalarFloatingRange(spec amd64FloatingRangeSpec, properties amd64BinaryFloatingSuffix, ins Instr, first, second, destination Operand, mask string) (bool, bool, error) { + source2, err := c.loadFloatingScalarBits(first, spec.laneBits) + if err != nil { + return true, false, err + } + source1, err := c.loadFloatingScalarBits(second, spec.laneBits) + if err != nil { + return true, false, err + } + source2Vector := c.newTmp() + source1Vector := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", source2Vector, spec.laneBits, spec.laneBits, source2) + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", source1Vector, spec.laneBits, spec.laneBits, source1) + result := c.emitFloatingRangeBits(1, spec.laneBits, "%"+source1Vector, "%"+source2Vector, uint8(ins.Args[0].Imm)) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i%d> %s, i32 0\n", low, spec.laneBits, result) + secondBytes, err := c.loadX(second.Reg) + if err != nil { + return true, false, err + } + base := c.bitcastVectorBytesToIntegerLanes(16, 128/spec.laneBits, spec.laneBits, secondBytes) + return true, false, c.storeVectorScalarRegister(destination.Reg, spec.laneBits, "%"+low, base, mask, properties.zeroing) +} + +func (c *amd64Ctx) loadFloatingScalarBits(operand Operand, laneBits int) (string, error) { + value, err := c.loadFloatingScalarOperand(operand, laneBits) + if err != nil { + return "", err + } + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to i%d\n", bits, amd64FloatingScalarType(laneBits), value, laneBits) + return "%" + bits, nil +} + +// emitFloatingRangeBits follows Intel's range operation in integer bit space +// around one ordered floating comparison. This preserves NaN payloads, quiets +// signaling NaNs, and handles signed zero and equal-magnitude opposite signs. +func (c *amd64Ctx) emitFloatingRangeBits(lanes, laneBits int, source1, source2 string, immediate uint8) string { + integerType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + floatType := amd64FloatingVectorType(lanes, laneBits) + predicateType := fmt.Sprintf("<%d x i1>", lanes) + signBit := uint64(1) << (laneBits - 1) + absMask := signBit - 1 + quietBit := uint64(0x00400000) + infinity := uint64(0x7f800000) + if laneBits == 64 { + quietBit = uint64(0x0008000000000000) + infinity = uint64(0x7ff0000000000000) + } + signVector := llvmSplatInteger(lanes, laneBits, signBit) + absVector := llvmSplatInteger(lanes, laneBits, absMask) + quietVector := llvmSplatInteger(lanes, laneBits, quietBit) + infinityVector := llvmSplatInteger(lanes, laneBits, infinity) + + abs1, abs2 := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", abs1, integerType, source1, absVector) + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", abs2, integerType, source2, absVector) + + compareLeft, compareRight := source1, source2 + if immediate&3 >= 2 { + compareLeft, compareRight = "%"+abs1, "%"+abs2 + } + leftFloat, rightFloat := c.newTmp(), c.newTmp() + ordered := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", leftFloat, integerType, compareLeft, floatType) + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", rightFloat, integerType, compareRight, floatType) + fmt.Fprintf(c.b, " %%%s = fcmp ole %s %%%s, %%%s\n", ordered, floatType, leftFloat, rightFloat) + selected := c.newTmp() + if immediate&1 == 0 { + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %s, %s %s\n", selected, predicateType, ordered, integerType, source1, integerType, source2) + } else { + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %s, %s %s\n", selected, predicateType, ordered, integerType, source2, integerType, source1) + } + result := "%" + selected + + signXor, signDifference, oppositeSigns := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, %s\n", signXor, integerType, source1, source2) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %s\n", signDifference, integerType, signXor, signVector) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, zeroinitializer\n", oppositeSigns, integerType, signDifference) + if immediate&3 < 2 { + zero1, zero2, bothZero, oppositeZero := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, zeroinitializer\n", zero1, integerType, abs1) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, zeroinitializer\n", zero2, integerType, abs2) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", bothZero, predicateType, zero1, zero2) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", oppositeZero, predicateType, bothZero, oppositeSigns) + zeroResult := "zeroinitializer" + if immediate&1 == 0 { + zeroResult = signVector + } + overridden := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %s, %s %s\n", overridden, predicateType, oppositeZero, integerType, zeroResult, integerType, result) + result = "%" + overridden + } else { + equalMagnitude, equalOpposite := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, %%%s\n", equalMagnitude, integerType, abs1, abs2) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", equalOpposite, predicateType, equalMagnitude, oppositeSigns) + tieResult := "%" + abs1 + if immediate&1 == 0 { + negative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %s\n", negative, integerType, abs1, signVector) + tieResult = "%" + negative + } + overridden := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %s, %s %s\n", overridden, predicateType, equalOpposite, integerType, tieResult, integerType, result) + result = "%" + overridden + } + + isNaN1, isNaN2 := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ugt %s %%%s, %s\n", isNaN1, integerType, abs1, infinityVector) + fmt.Fprintf(c.b, " %%%s = icmp ugt %s %%%s, %s\n", isNaN2, integerType, abs2, infinityVector) + withoutNaN1 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %s, %s %s\n", withoutNaN1, predicateType, isNaN1, integerType, source2, integerType, result) + withoutQuietNaNs := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %s, %s %%%s\n", withoutQuietNaNs, predicateType, isNaN2, integerType, source1, integerType, withoutNaN1) + result = "%" + withoutQuietNaNs + + signMode := immediate >> 2 & 3 + if signMode != 1 { + magnitude := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", magnitude, integerType, result, absVector) + switch signMode { + case 0: + sourceSign := c.newTmp() + signed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", sourceSign, integerType, source1, signVector) + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %%%s\n", signed, integerType, magnitude, sourceSign) + result = "%" + signed + case 2: + result = "%" + magnitude + case 3: + signed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %s\n", signed, integerType, magnitude, signVector) + result = "%" + signed + } + } + + quiet1, quiet2 := c.newTmp(), c.newTmp() + quietField1, quietField2 := c.newTmp(), c.newTmp() + quietClear1, quietClear2 := c.newTmp(), c.newTmp() + signaling1, signaling2 := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %s, %s\n", quiet1, integerType, source1, quietVector) + fmt.Fprintf(c.b, " %%%s = or %s %s, %s\n", quiet2, integerType, source2, quietVector) + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", quietField1, integerType, source1, quietVector) + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", quietField2, integerType, source2, quietVector) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, zeroinitializer\n", quietClear1, integerType, quietField1) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, zeroinitializer\n", quietClear2, integerType, quietField2) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", signaling1, predicateType, isNaN1, quietClear1) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", signaling2, predicateType, isNaN2, quietClear2) + withSecondSignaling := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %%%s, %s %s\n", withSecondSignaling, predicateType, signaling2, integerType, quiet2, integerType, result) + withFirstSignaling := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %%%s, %s %%%s\n", withFirstSignaling, predicateType, signaling1, integerType, quiet1, integerType, withSecondSignaling) + return "%" + withFirstSignaling +} diff --git a/amd64_lower_range_test.go b/amd64_lower_range_test.go new file mode 100644 index 00000000..001bad7e --- /dev/null +++ b/amd64_lower_range_test.go @@ -0,0 +1,373 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64FloatingRangeGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64FloatingRangeSpec{ + "VRANGEPS": {laneBits: 32}, + "VRANGEPD": {laneBits: 64}, + "VRANGESS": {laneBits: 32, scalar: true}, + "VRANGESD": {laneBits: 64, scalar: true}, + } + if len(amd64FloatingRangeSpecs) != len(expected) { + t.Fatalf("floating-range grammar has %d entries, want %d", len(amd64FloatingRangeSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64FloatingRangeSpecs[op]; !ok { + t.Errorf("floating-range grammar omitted %s", op) + } else if got != want { + t.Errorf("floating-range grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86FloatingRangeCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT floatingrangeforms(SB),$0-0\n") + for _, op := range []string{"VRANGEPS", "VRANGEPD"} { + for _, width := range []string{"X", "Y", "Z"} { + last := 31 + if target.goarch == "386" { + last = 7 + } + fmt.Fprintf(&source, "\t%s $0, %s1, %s2, %s%d\n", op, width, width, width, last) + fmt.Fprintf(&source, "\t%s $255, 8(AX), %s2, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s.BCST $2, 16(AX), %s2, %s%d\n", op, width, width, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s $3, %s1, %s2, K1, %s%d\n", op, width, width, width, last) + fmt.Fprintf(&source, "\t%s.Z $4, 24(AX), %s2, K2, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s.BCST.Z $5, 32(AX), %s2, K3, %s%d\n", op, width, width, last) + if width == "Z" { + fmt.Fprintf(&source, "\t%s.SAE $6, Z1, Z2, Z%d\n", op, last) + fmt.Fprintf(&source, "\t%s.SAE.Z $7, Z1, Z2, K4, Z%d\n", op, last) + } + } + } + } + for _, op := range []string{"VRANGESS", "VRANGESD"} { + last := 31 + if target.goarch == "386" { + last = 7 + } + fmt.Fprintf(&source, "\t%s $8, X1, X2, X%d\n", op, last) + fmt.Fprintf(&source, "\t%s $9, 40(AX), X2, X%d\n", op, last) + fmt.Fprintf(&source, "\t%s.SAE $10, X1, X2, X%d\n", op, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s $11, X1, X2, K5, X%d\n", op, last) + fmt.Fprintf(&source, "\t%s.Z $12, 48(AX), X2, K6, X%d\n", op, last) + fmt.Fprintf(&source, "\t%s.SAE.Z $13, X1, X2, K7, X%d\n", op, last) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"floatingrangeforms": {Name: "floatingrangeforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "floating-range-"+target.name+".ll", "floating-range-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86FloatingRangeRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VRANGEPS $-1, X0, X1, X2"}, + {goarch: "amd64", instruction: "VRANGEPS $256, X0, X1, X2"}, + {goarch: "amd64", instruction: "VRANGEPS X0, X1, X2"}, + {goarch: "amd64", instruction: "VRANGEPS $0, X0, Y1, Y2"}, + {goarch: "amd64", instruction: "VRANGEPS.BCST $0, X0, X1, X2"}, + {goarch: "amd64", instruction: "VRANGEPS.SAE $0, X0, X1, X2"}, + {goarch: "amd64", instruction: "VRANGESD.SAE $0, 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VRANGEPS.RN_SAE $0, Z0, Z1, Z2"}, + {goarch: "amd64", instruction: "VRANGEPS.Z $0, X0, X1, X2"}, + {goarch: "amd64", instruction: "VRANGEPS $0, X0, X1, K0, X2"}, + {goarch: "amd64", instruction: "VRANGESS $0, Y0, X1, X2"}, + {goarch: "amd64", instruction: "VRANGESS.BCST $0, 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VRANGESD $0, X0, X1, Y2"}, + {goarch: "386", instruction: "VRANGEPS $0, X0, X1, X2"}, + {goarch: "386", instruction: "VRANGEPS $0, X0, X1, K1, X2"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's floating-range table", test.instruction) + } + }) + } +} + +func TestAMD64FloatingRangeRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + var source strings.Builder + source.WriteString(`TEXT floatingrangesemantics(SB),$0-40 + MOVQ out+0(FP), AX + MOVQ source2+8(FP), BX + MOVQ source1+16(FP), CX + MOVQ old+24(FP), DX + MOVQ mask+32(FP), R8 + KMOVQ R8, K1 + VMOVDQU32 0(BX), Z0 + VMOVDQU32 0(CX), Z1 + STC +`) + for immediate := 0; immediate < 16; immediate++ { + fmt.Fprintf(&source, "\tVRANGEPS $%d, Z0, Z1, Z2\n", immediate) + fmt.Fprintf(&source, "\tVMOVDQU32 Z2, %d(AX)\n", immediate*64) + } + source.WriteString(` VMOVDQU32 0(DX), Z2 + VRANGEPS $2, Z0, Z1, K1, Z2 + VMOVDQU32 Z2, 1024(AX) + VRANGEPS.Z $3, Z0, Z1, K1, Z2 + VMOVDQU32 Z2, 1088(AX) + VRANGEPS.BCST $2, 0(BX), Z1, Z2 + VMOVDQU32 Z2, 1152(AX) + SETCS 1216(AX) + RET +`) + requireX86GoAssemblerResult(t, "amd64", source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"floatingrangesemantics": { + Name: "floatingrangesemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: I64, Index: 4, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void floatingrangesemantics(uint8_t *, const uint32_t *, const uint32_t *, const uint32_t *, uint64_t); +static float f32(uint32_t u) { float f; memcpy(&f,&u,4); return f; } +static uint32_t range32(uint32_t a, uint32_t b, unsigned imm) { + const uint32_t sign=UINT32_C(0x80000000), absMask=UINT32_C(0x7fffffff); + const uint32_t quiet=UINT32_C(0x00400000), inf=UINT32_C(0x7f800000); + uint32_t aa=a&absMask, ab=b&absMask, tmp; + int nanA=aa>inf, nanB=ab>inf, snanA=nanA && !(a&quiet), snanB=nanB && !(b&quiet); + unsigned op=imm&3, signs=(imm>>2)&3; + if (nanB) tmp=a; + else if (nanA) tmp=b; + else if (((a^b)&sign) && aa==0 && ab==0) tmp=(op&1)?0:sign; + else if (((a^b)&sign) && aa==ab && op>=2) tmp=(op&1)?aa:(aa|sign); + else { + int le=op>=2 ? f32(aa)<=f32(ab) : f32(a)<=f32(b); + tmp=(op&1) ? (le?b:a) : (le?a:b); + } + if (signs==0) tmp=(tmp&absMask)|(a&sign); + else if (signs==2) tmp&=absMask; + else if (signs==3) tmp|=sign; + if (snanB) tmp=b|quiet; + if (snanA) tmp=a|quiet; + return tmp; +} +int main(void) { + const uint32_t source1[16]={ + 0x00000000,0x80000000,0x3f800000,0xbf800000, + 0x40000000,0xc0000000,0x40400000,0xc0800000, + 0x7f800000,0xff800000,0x7fc12345,0xffc23456, + 0x7f812345,0xff823456,0x3f000000,0xbf400000}; + const uint32_t source2[16]={ + 0x80000000,0x00000000,0xbf800000,0x3f800000, + 0xc0400000,0x3f000000,0xc0400000,0x40a00000, + 0x7f000000,0xff000000,0x3f800000,0x7fc34567, + 0x40000000,0x7f834567,0xbf000000,0x3fc00000}; + uint32_t old[16], out[305]; + const uint64_t mask=UINT64_C(0xa55a); + for (int i=0;i<16;i++) old[i]=UINT32_C(0x41000000)+(uint32_t)i; + memset(out,0,sizeof(out)); + floatingrangesemantics((uint8_t*)out,source2,source1,old,mask); + for (unsigned imm=0;imm<16;imm++) for (int i=0;i<16;i++) + if (out[imm*16+i]!=range32(source1[i],source2[i],imm)) return 10+(int)imm; + for (int i=0;i<16;i++) { + uint32_t r2=range32(source1[i],source2[i],2); + uint32_t r3=range32(source1[i],source2[i],3); + if (out[256+i]!=(((mask>>i)&1)?r2:old[i])) return 40; + if (out[272+i]!=(((mask>>i)&1)?r3:0)) return 41; + if (out[288+i]!=range32(source1[i],source2[0],2)) return 42; + } + if (((uint8_t*)out)[1216]!=1) return 43; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "floating_range_semantics", triple, ir, mainC, runPrefix) +} + +func TestAMD64FloatingRangeDoubleAndScalarRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + var source strings.Builder + source.WriteString(`TEXT floatingrangedoublesemantics(SB),$0-40 + MOVQ out+0(FP), AX + MOVQ source2+8(FP), BX + MOVQ source1+16(FP), CX + MOVQ old+24(FP), DX + MOVQ mask+32(FP), R8 + KMOVQ R8, K1 + VMOVDQU64 0(BX), Z0 + VMOVDQU64 0(CX), Z1 + STC +`) + for immediate := 0; immediate < 16; immediate++ { + fmt.Fprintf(&source, "\tVRANGEPD $%d, Z0, Z1, Z2\n", immediate) + fmt.Fprintf(&source, "\tVMOVDQU64 Z2, %d(AX)\n", immediate*64) + } + source.WriteString(` VMOVDQU64 0(BX), X0 + VMOVDQU64 0(CX), X1 + VMOVDQU64 0(DX), X2 + VRANGESD $2, X0, X1, X2 + VMOVDQU64 X2, 1024(AX) + VMOVDQU64 0(DX), X2 + VRANGESD $2, X0, X1, K1, X2 + VMOVDQU64 X2, 1040(AX) + VRANGESD.Z $2, X0, X1, K1, X2 + VMOVDQU64 X2, 1056(AX) + SETCS 1072(AX) + RET +`) + requireX86GoAssemblerResult(t, "amd64", source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"floatingrangedoublesemantics": { + Name: "floatingrangedoublesemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: I64, Index: 4, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void floatingrangedoublesemantics(uint8_t *, const uint64_t *, const uint64_t *, const uint64_t *, uint64_t); +static double f64(uint64_t u) { double f; memcpy(&f,&u,8); return f; } +static uint64_t range64(uint64_t a, uint64_t b, unsigned imm) { + const uint64_t sign=UINT64_C(0x8000000000000000), absMask=UINT64_C(0x7fffffffffffffff); + const uint64_t quiet=UINT64_C(0x0008000000000000), inf=UINT64_C(0x7ff0000000000000); + uint64_t aa=a&absMask, ab=b&absMask, tmp; + int nanA=aa>inf, nanB=ab>inf, snanA=nanA && !(a&quiet), snanB=nanB && !(b&quiet); + unsigned op=imm&3, signs=(imm>>2)&3; + if (nanB) tmp=a; + else if (nanA) tmp=b; + else if (((a^b)&sign) && aa==0 && ab==0) tmp=(op&1)?0:sign; + else if (((a^b)&sign) && aa==ab && op>=2) tmp=(op&1)?aa:(aa|sign); + else { + int le=op>=2 ? f64(aa)<=f64(ab) : f64(a)<=f64(b); + tmp=(op&1) ? (le?b:a) : (le?a:b); + } + if (signs==0) tmp=(tmp&absMask)|(a&sign); + else if (signs==2) tmp&=absMask; + else if (signs==3) tmp|=sign; + if (snanB) tmp=b|quiet; + if (snanA) tmp=a|quiet; + return tmp; +} +int main(void) { + const uint64_t source1[8]={ + UINT64_C(0),UINT64_C(0x8000000000000000),UINT64_C(0x3ff0000000000000),UINT64_C(0xbff0000000000000), + UINT64_C(0x7ff8123456789abc),UINT64_C(0xfff823456789abcd),UINT64_C(0x7ff0123456789abc),UINT64_C(0xfff023456789abcd)}; + const uint64_t source2[8]={ + UINT64_C(0x8000000000000000),UINT64_C(0),UINT64_C(0xbff0000000000000),UINT64_C(0x3ff0000000000000), + UINT64_C(0x4000000000000000),UINT64_C(0x7ff83456789abcde),UINT64_C(0x4008000000000000),UINT64_C(0x7ff0456789abcdef)}; + const uint64_t old[8]={UINT64_C(0x4020000000000000),UINT64_C(0x4030000000000000),0,0,0,0,0,0}; + uint64_t out[135]; + memset(out,0,sizeof(out)); + floatingrangedoublesemantics((uint8_t*)out,source2,source1,old,0); + for (unsigned imm=0;imm<16;imm++) for (int i=0;i<8;i++) + if (out[imm*8+i]!=range64(source1[i],source2[i],imm)) return 10+(int)imm; + if (out[128]!=range64(source1[0],source2[0],2)) return 40; + if (out[129]!=source1[1]) return 44; + if (out[130]!=old[0] || out[131]!=source1[1]) return 41; + if (out[132]!=0 || out[133]!=source1[1]) return 42; + if (((uint8_t*)out)[1072]!=1) return 43; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "floating_range_double_scalar_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_rdpid_test.go b/amd64_lower_rdpid_test.go new file mode 100644 index 00000000..fafc0f40 --- /dev/null +++ b/amd64_lower_rdpid_test.go @@ -0,0 +1,94 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86RDPIDCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + goarch string + triple string + registers []string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu", registers: []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}}, + {goarch: "386", triple: "i686-pc-windows-msvc", registers: []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}}, + {goarch: "amd64", triple: "x86_64-apple-darwin", registers: []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", registers: []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}}, + {goarch: "amd64", triple: "x86_64-pc-windows-msvc", registers: []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}}, + } { + t.Run(target.goarch+"/"+target.triple, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rdpidforms(SB),$0-0\n") + for _, register := range target.registers { + fmt.Fprintf(&source, "\tRDPID %s\n", register) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "rdpidforms": {Name: "rdpidforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"@llvm.x86.rdpid()", `"target-features"="+rdpid"`} { + if !strings.Contains(ll, want) { + t.Fatalf("RDPID lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "x86-rdpid.ll", "x86-rdpid.o", ll) + }) + } +} + +func TestTranslateX86RDPIDRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "386", instruction: "RDPID AL"}, + {goarch: "386", instruction: "RDPID 0(AX)"}, + {goarch: "386", instruction: "RDPID R8"}, + {goarch: "amd64", instruction: "RDPID AL"}, + {goarch: "amd64", instruction: "RDPID 0(AX)"}, + {goarch: "amd64", instruction: "RDPID AX, DX"}, + {goarch: "amd64", instruction: "RDPID.Z AX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT badrdpid(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{ + "badrdpid": {Name: "badrdpid", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go's RDPID optab", test.instruction) + } + }) + } +} diff --git a/amd64_lower_reciprocal.go b/amd64_lower_reciprocal.go new file mode 100644 index 00000000..64e84fd6 --- /dev/null +++ b/amd64_lower_reciprocal.go @@ -0,0 +1,367 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64Reciprocal14Spec struct { + laneBits int + scalar bool + rsqr bool +} + +// amd64Reciprocal14Specs covers every opcode backed by Go 1.27's +// _yvexpandpd and _yvgetexpsd reciprocal-estimate tables. +var amd64Reciprocal14Specs = map[Op]amd64Reciprocal14Spec{ + "VRCP14PS": {laneBits: 32}, + "VRCP14PD": {laneBits: 64}, + "VRCP14SS": {laneBits: 32, scalar: true}, + "VRCP14SD": {laneBits: 64, scalar: true}, + "VRSQRT14PS": {laneBits: 32, rsqr: true}, + "VRSQRT14PD": {laneBits: 64, rsqr: true}, + "VRSQRT14SS": {laneBits: 32, scalar: true, rsqr: true}, + "VRSQRT14SD": {laneBits: 64, scalar: true, rsqr: true}, +} + +// lowerReciprocal14 implements the complete Go 1.27 RCP14/RSQRT14 family. +// Packed PS/PD forms accept X/Y/Z register or memory sources, scalar-memory +// broadcast, and K1-K7 merge/.Z masking. Scalar SS/SD forms accept an X or +// scalar-memory source, an X passthrough, and the same masking on amd64; the +// four-operand masked scalar form exceeds the 386 assembler's operand limit. +func (c *amd64Ctx) lowerReciprocal14(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, found := amd64Reciprocal14Specs[Op(baseOp)] + if !found { + return false, false, nil + } + properties, validSuffix := parseAMD64BinaryFloatingSuffix(suffix) + if !validSuffix || properties.sae || properties.rounding != "" || spec.scalar && properties.broadcast { + return true, false, fmt.Errorf("%s %s suffix is absent from its Go 1.27 encoding: %q", c.goarch, baseOp, ins.Raw) + } + if spec.scalar { + return c.lowerScalarReciprocal14(baseOp, spec, properties, ins) + } + return c.lowerPackedReciprocal14(baseOp, spec, properties, ins) +} + +func (c *amd64Ctx) lowerPackedReciprocal14(baseOp string, spec amd64Reciprocal14Spec, properties amd64BinaryFloatingSuffix, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects source, [K1-K7,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 3 + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s.Z requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s masked form requires K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be X, Y, or Z: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's EVEX vector class: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[0] + if properties.broadcast { + if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s.BCST requires a scalar memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source register must match its destination: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := byteWidth * 8 / spec.laneBits + llvmType := amd64FloatingVectorType(lanes, spec.laneBits) + var sourceValue string + if properties.broadcast { + scalar, err := c.loadFloatingScalarOperand(source, spec.laneBits) + if err != nil { + return true, false, err + } + sourceValue = c.splatFloatingScalar(scalar, lanes, spec.laneBits) + } else { + var err error + sourceValue, err = c.loadFloatingVectorOperand(source, byteWidth, lanes, spec.laneBits) + if err != nil { + return true, false, err + } + } + + passthrough := "zeroinitializer" + mask := "-1" + maskBits := 8 + if spec.laneBits == 32 && byteWidth == 64 { + maskBits = 16 + } + if masked { + loadedMask, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + mask = c.truncateReciprocal14Mask(loadedMask, maskBits) + if !properties.zeroing { + passthrough, err = c.loadFloatingVectorOperand(destination, byteWidth, lanes, spec.laneBits) + if err != nil { + return true, false, err + } + } + } + family := "rcp14" + if spec.rsqr { + family = "rsqrt14" + } + intrinsic := fmt.Sprintf("llvm.x86.avx512.%s.%s.%d", family, map[int]string{32: "ps", 64: "pd"}[spec.laneBits], byteWidth*8) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %s, %s %s, i%d %s)\n", result, llvmType, intrinsic, llvmType, sourceValue, llvmType, passthrough, maskBits, mask) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <%d x i8>\n", out, llvmType, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) lowerScalarReciprocal14(baseOp string, spec amd64Reciprocal14Spec, properties amd64BinaryFloatingSuffix, ins Instr) (bool, bool, error) { + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects source, passthrough, [K1-K7,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return true, false, fmt.Errorf("%s %s.Z requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("%s %s masked form requires K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + passthroughArg := ins.Args[1] + if !c.isGoEVEXVectorRegister(destination, 16) || !c.isGoEVEXVectorRegister(passthroughArg, 16) { + return true, false, fmt.Errorf("%s %s passthrough and destination must be X registers: %q", c.goarch, baseOp, ins.Raw) + } + source := ins.Args[0] + if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, 16) { + return true, false, fmt.Errorf("%s %s source must be an X register or scalar memory: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be an X register or scalar memory: %q", c.goarch, baseOp, ins.Raw) + } + + lanes := 128 / spec.laneBits + llvmType := amd64FloatingVectorType(lanes, spec.laneBits) + scalar, err := c.loadFloatingScalarOperand(source, spec.laneBits) + if err != nil { + return true, false, err + } + sourceValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s zeroinitializer, %s %s, i32 0\n", sourceValue, llvmType, amd64FloatingScalarType(spec.laneBits), scalar) + passthrough, err := c.loadFloatingVectorOperand(passthroughArg, 16, lanes, spec.laneBits) + if err != nil { + return true, false, err + } + merge := "zeroinitializer" + mask := "-1" + if masked { + loadedMask, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + mask = c.truncateReciprocal14Mask(loadedMask, 8) + if !properties.zeroing { + merge, err = c.loadFloatingVectorOperand(destination, 16, lanes, spec.laneBits) + if err != nil { + return true, false, err + } + } + } + family := "rcp14" + if spec.rsqr { + family = "rsqrt14" + } + intrinsic := fmt.Sprintf("llvm.x86.avx512.%s.%s", family, map[int]string{32: "ss", 64: "sd"}[spec.laneBits]) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %s, %s %%%s, %s %s, i8 %s)\n", result, llvmType, intrinsic, llvmType, passthrough, llvmType, sourceValue, llvmType, merge, mask) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", out, llvmType, result) + return true, false, c.storeVectorBytes(destination.Reg, 16, "%"+out) +} + +func (c *amd64Ctx) truncateReciprocal14Mask(mask string, bits int) string { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", truncated, mask, bits) + return "%" + truncated +} + +// lowerReciprocalEstimate implements the complete Go 1.27 legacy and VEX +// RCP/RSQRT estimate family: packed RCPPS/RSQRTPS/VRCPPS/VRSQRTPS plus scalar +// RCPSS/RSQRTSS/VRCPSS/VRSQRTSS. LLVM's target intrinsics preserve the +// instructions' approximate semantics instead of replacing them with exact +// generic floating-point operations. +func (c *amd64Ctx) lowerReciprocalEstimate(rawOp Op, ins Instr) (ok bool, terminated bool, err error) { + raw := strings.ToUpper(string(rawOp)) + base := raw + if dot := strings.IndexByte(raw, '.'); dot >= 0 { + base = raw[:dot] + } + switch base { + case "RCPPS", "RSQRTPS", "VRCPPS", "VRSQRTPS", + "RCPSS", "RSQRTSS", "VRCPSS", "VRSQRTSS": + default: + return false, false, nil + } + if raw != base { + return true, false, fmt.Errorf("%s %s has no suffixed form in Go 1.27: %q", c.goarch, base, ins.Raw) + } + if strings.HasSuffix(base, "SS") { + return c.lowerScalarReciprocalEstimate(base, ins) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects vector-or-memory source and vector destination: %q", c.goarch, base, ins.Raw) + } + + source, destination := ins.Args[0], ins.Args[1] + byteWidth := amd64VectorByteWidth(destination.Reg) + legacy := base == "RCPPS" || base == "RSQRTPS" + if legacy { + if destination.Kind != OpReg || byteWidth != 16 || !c.isGoLegacyXReg(destination.Reg) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's legacy X register class: %q", c.goarch, base, ins.Raw) + } + if source.Kind == OpReg && !c.isGoLegacyXReg(source.Reg) { + return true, false, fmt.Errorf("%s %s source must be an in-range X register or memory: %q", c.goarch, base, ins.Raw) + } + } else { + if destination.Kind != OpReg || byteWidth != 16 && byteWidth != 32 || !amd64VEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's VEX X/Y register classes: %q", c.goarch, base, ins.Raw) + } + if source.Kind == OpReg && !amd64VEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source must match the destination width: %q", c.goarch, base, ins.Raw) + } + } + if source.Kind != OpReg && !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be a matching vector register or memory: %q", c.goarch, base, ins.Raw) + } + + lanes := byteWidth / 4 + value, err := c.loadPackedReciprocalSource(source, byteWidth, lanes) + if err != nil { + return true, false, err + } + intrinsic := "llvm.x86.sse.rcp.ps" + if strings.Contains(base, "RSQRT") { + intrinsic = "llvm.x86.sse.rsqrt.ps" + } + if byteWidth == 32 { + intrinsic = "llvm.x86.avx.rcp.ps.256" + if strings.Contains(base, "RSQRT") { + intrinsic = "llvm.x86.avx.rsqrt.ps.256" + } + } + vectorType := fmt.Sprintf("<%d x float>", lanes) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %s)\n", result, vectorType, intrinsic, vectorType, value) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <%d x i8>\n", bytesValue, vectorType, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+bytesValue) +} + +func (c *amd64Ctx) lowerScalarReciprocalEstimate(base string, ins Instr) (bool, bool, error) { + legacy := base == "RCPSS" || base == "RSQRTSS" + wantArgs := 3 + if legacy { + wantArgs = 2 + } + if len(ins.Args) != wantArgs { + return true, false, fmt.Errorf("%s %s expects %d operands from its Go 1.27 table: %q", c.goarch, base, wantArgs, ins.Raw) + } + + source := ins.Args[0] + destination := ins.Args[len(ins.Args)-1] + passthrough := destination + if !legacy { + passthrough = ins.Args[1] + } + if legacy { + if destination.Kind != OpReg || !c.isGoLegacyXReg(destination.Reg) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's legacy X register class: %q", c.goarch, base, ins.Raw) + } + if source.Kind == OpReg && !c.isGoLegacyXReg(source.Reg) { + return true, false, fmt.Errorf("%s %s source must be an in-range X register or scalar memory: %q", c.goarch, base, ins.Raw) + } + if source.Kind == OpMem && !x86MemoryRegistersValidForArch(source.Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s source uses an out-of-range legacy address register: %q", c.goarch, base, ins.Raw) + } + } else { + if !amd64VEXVectorRegister(passthrough, 16) || !amd64VEXVectorRegister(destination, 16) { + return true, false, fmt.Errorf("%s %s passthrough and destination must be VEX X registers: %q", c.goarch, base, ins.Raw) + } + if source.Kind == OpReg && !amd64VEXVectorRegister(source, 16) { + return true, false, fmt.Errorf("%s %s source must be a VEX X register or scalar memory: %q", c.goarch, base, ins.Raw) + } + } + if source.Kind != OpReg && !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be an X register or scalar memory: %q", c.goarch, base, ins.Raw) + } + + scalar, err := c.loadScalarReciprocalSource(source) + if err != nil { + return true, false, err + } + input := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <4 x float> zeroinitializer, float %s, i32 0\n", input, scalar) + intrinsic := "llvm.x86.sse.rcp.ps" + if strings.Contains(base, "RSQRT") { + intrinsic = "llvm.x86.sse.rsqrt.ps" + } + estimates := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <4 x float> @%s(<4 x float> %%%s)\n", estimates, intrinsic, input) + estimate := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x float> %%%s, i32 0\n", estimate, estimates) + upper, err := c.loadFloatingVectorOperand(passthrough, 16, 4, 32) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <4 x float> %s, float %%%s, i32 0\n", result, upper, estimate) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x float> %%%s to <16 x i8>\n", bytesValue, result) + return true, false, c.storeVectorBytes(destination.Reg, 16, "%"+bytesValue) +} + +func (c *amd64Ctx) loadScalarReciprocalSource(source Operand) (string, error) { + if source.Kind == OpSym { + // A bare integer is absolute memory in the Go assembler; '$' is the + // immediate spelling and is intentionally rejected by this family. + if address, err := parseInt(source.Sym); err == nil { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load float, ptr %s, align 1\n", value, c.ptrFromAddrI64(fmt.Sprintf("%d", address))) + return "%" + value, nil + } + } + return c.loadFloatingScalarOperand(source, 32) +} + +func (c *amd64Ctx) loadPackedReciprocalSource(source Operand, byteWidth, lanes int) (string, error) { + if source.Kind == OpSym { + // As in Go's x86 assembler, a bare integer is an absolute memory + // operand. '$' is required for an immediate. + if address, parseErr := parseInt(source.Sym); parseErr == nil { + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load <%d x i8>, ptr %s, align 1\n", bytesValue, byteWidth, c.ptrFromAddrI64(fmt.Sprintf("%d", address))) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %%%s to <%d x float>\n", value, byteWidth, bytesValue, lanes) + return "%" + value, nil + } + } + return c.loadFloatingVectorOperand(source, byteWidth, lanes, 32) +} diff --git a/amd64_lower_reciprocal14_test.go b/amd64_lower_reciprocal14_test.go new file mode 100644 index 00000000..97349dea --- /dev/null +++ b/amd64_lower_reciprocal14_test.go @@ -0,0 +1,131 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86Reciprocal14CompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's _yvexpandpd table accepts EVEX X/Y/Z register or memory + // sources, optional scalar-memory broadcast, and optional K1-K7 merge/.Z + // masking. _yvgetexpsd accepts scalar memory/X sources, an X passthrough, + // and the same optional mask. The 386 frontend accepts the unmasked EVEX + // forms but not mask operands, and limits Z registers to Z0-Z7. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastZ := 31 + if target.goarch == "386" { + lastZ = 7 + } + var source strings.Builder + source.WriteString("TEXT reciprocal14forms(SB),$0-0\n") + for _, op := range []string{"VRCP14PS", "VRCP14PD", "VRSQRT14PS", "VRSQRT14PD"} { + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&source, "\t%s %s1, %s20\n", op, width, width) + fmt.Fprintf(&source, "\t%s 8(AX), %s20\n", op, width) + fmt.Fprintf(&source, "\t%s.BCST 16(AX), %s20\n", op, width) + } + fmt.Fprintf(&source, "\t%s Z1, Z%d\n", op, lastZ) + fmt.Fprintf(&source, "\t%s 24(AX), Z%d\n", op, lastZ) + fmt.Fprintf(&source, "\t%s.BCST 32(AX), Z%d\n", op, lastZ) + fmt.Fprintf(&source, "\t%s X1, K1, X20\n", op) + fmt.Fprintf(&source, "\t%s.Z 40(AX), K2, Y20\n", op) + fmt.Fprintf(&source, "\t%s.BCST.Z 48(AX), K3, Z%d\n", op, lastZ) + } + for _, op := range []string{"VRCP14SS", "VRCP14SD", "VRSQRT14SS", "VRSQRT14SD"} { + fmt.Fprintf(&source, "\t%s X1, X20, X21\n", op) + fmt.Fprintf(&source, "\t%s 56(AX), X20, X21\n", op) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s X1, X20, K4, X21\n", op) + fmt.Fprintf(&source, "\t%s.Z 64(AX), X20, K5, X21\n", op) + } + } + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "reciprocal14forms": {Name: "reciprocal14forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{ + "@llvm.x86.avx512.rcp14.ps.128", "@llvm.x86.avx512.rcp14.ps.256", "@llvm.x86.avx512.rcp14.ps.512", + "@llvm.x86.avx512.rcp14.pd.128", "@llvm.x86.avx512.rcp14.pd.256", "@llvm.x86.avx512.rcp14.pd.512", + "@llvm.x86.avx512.rsqrt14.ps.128", "@llvm.x86.avx512.rsqrt14.ps.256", "@llvm.x86.avx512.rsqrt14.ps.512", + "@llvm.x86.avx512.rsqrt14.pd.128", "@llvm.x86.avx512.rsqrt14.pd.256", "@llvm.x86.avx512.rsqrt14.pd.512", + "@llvm.x86.avx512.rcp14.ss", "@llvm.x86.avx512.rcp14.sd", + "@llvm.x86.avx512.rsqrt14.ss", "@llvm.x86.avx512.rsqrt14.sd", + } { + if !strings.Contains(ll, intrinsic) { + t.Fatalf("translation omitted %s:\n%s", intrinsic, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "reciprocal14-"+target.name+".ll", "reciprocal14-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86Reciprocal14RejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VRCP14PS X0, Y1"}, + {goarch: "amd64", instruction: "VRSQRT14PD.Z Z0, Z1"}, + {goarch: "amd64", instruction: "VRCP14PS.BCST X0, X1"}, + {goarch: "amd64", instruction: "VRCP14PD.SAE Z0, Z1"}, + {goarch: "amd64", instruction: "VRSQRT14PS Z0, K0, Z1"}, + {goarch: "amd64", instruction: "VRCP14SS X0, X1"}, + {goarch: "amd64", instruction: "VRCP14SD Y0, X1, X2"}, + {goarch: "amd64", instruction: "VRSQRT14SS.BCST 8(AX), X1, X2"}, + {goarch: "amd64", instruction: "VRSQRT14SD.SAE X0, X1, X2"}, + {goarch: "amd64", instruction: "VRCP14SS.Z X0, X1, X2"}, + {goarch: "amd64", instruction: "VRCP14SS X0, X1, K0, X2"}, + {goarch: "386", instruction: "VRCP14SS X0, X1, K1, X2"}, + {goarch: "386", instruction: "VRSQRT14PD Z0, Z8"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's reciprocal14 tables for %s", test.instruction, test.goarch) + } + }) + } +} diff --git a/amd64_lower_reciprocal_scalar_test.go b/amd64_lower_reciprocal_scalar_test.go new file mode 100644 index 00000000..680548bb --- /dev/null +++ b/amd64_lower_reciprocal_scalar_test.go @@ -0,0 +1,230 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86ScalarReciprocalCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast := 15 + if target.goarch == "386" { + legacyLast = 7 + } + const vexLast = 15 + var source strings.Builder + source.WriteString("DATA scalarreciprocaldata+0(SB)/4, $0\n") + source.WriteString("GLOBL scalarreciprocaldata(SB), $4\n") + source.WriteString("TEXT scalarreciprocalforms(SB),$0-4\n") + for _, op := range []string{"RCPSS", "RSQRTSS"} { + fmt.Fprintf(&source, "\t%s X1, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s scalarreciprocaldata(SB), X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s arg+0(FP), X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s 0, X%d\n", op, legacyLast) + } + for _, op := range []string{"VRCPSS", "VRSQRTSS"} { + fmt.Fprintf(&source, "\t%s X1, X2, X%d\n", op, vexLast) + fmt.Fprintf(&source, "\t%s 8(AX), X2, X%d\n", op, vexLast) + fmt.Fprintf(&source, "\t%s scalarreciprocaldata(SB), X2, X%d\n", op, vexLast) + fmt.Fprintf(&source, "\t%s arg+0(FP), X2, X%d\n", op, vexLast) + fmt.Fprintf(&source, "\t%s 0, X2, X%d\n", op, vexLast) + if target.goarch == "386" { + // Go's VEX register classes retain their 16-register + // compatibility closure even in 32-bit mode. + fmt.Fprintf(&source, "\t%s 16(R9), X13, X14\n", op) + } + } + if target.goarch == "amd64" { + for _, op := range []string{"RCPSS", "RSQRTSS"} { + fmt.Fprintf(&source, "\t%s 16(R11)(R12*2), X13\n", op) + } + for _, op := range []string{"VRCPSS", "VRSQRTSS"} { + fmt.Fprintf(&source, "\t%s 16(R11)(R12*2), X13, X14\n", op) + } + } + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "scalarreciprocalforms": { + Name: "scalarreciprocalforms", Args: []LLVMType{LLVMType("float")}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: LLVMType("float"), Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "@llvm.x86.sse.rcp.ps", "@llvm.x86.sse.rsqrt.ps", + "extractelement <4 x float>", "insertelement <4 x float>", + `"target-features"="+avx,+sse"`, + } { + if !strings.Contains(ir, want) { + t.Fatalf("scalar reciprocal lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "scalar-reciprocal-"+target.name+".ll", "scalar-reciprocal-"+target.name+".o", ir) + }) + } +} + +func TestAMD64ScalarReciprocalRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT scalarreciprocalsemantics(SB),$0-24 + MOVQ out+0(FP), DI + MOVQ source+8(FP), AX + MOVQ upper+16(FP), BX + + MOVUPS (BX), X0 + STC + RCPSS (AX), X0 + MOVUPS X0, 0(DI) + SETCS 64(DI) + + MOVUPS (BX), X1 + STC + RSQRTSS (AX), X1 + MOVUPS X1, 16(DI) + SETCS 65(DI) + + MOVUPS (BX), X2 + STC + VRCPSS (AX), X2, X3 + MOVUPS X3, 32(DI) + SETCS 66(DI) + + MOVUPS (BX), X4 + STC + VRSQRTSS (AX), X4, X5 + MOVUPS X5, 48(DI) + SETCS 67(DI) + VZEROUPPER + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "scalarreciprocalsemantics": { + Name: "scalarreciprocalsemantics", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void scalarreciprocalsemantics(uint8_t *, const float *, const float *); +static int close_enough(float got, float want) { + float delta = got - want; + if (delta < 0) delta = -delta; + return delta < 0.01f; +} +int main(void) { + float source[4] = {4.0f, 100.0f, 200.0f, 300.0f}; + float upper[4] = {99.0f, 10.0f, 20.0f, 30.0f}; + uint8_t out[68] = {0}; + scalarreciprocalsemantics(out, source, upper); + const float *values = (const float *)out; + for (int vector = 0; vector < 4; ++vector) { + float want = (vector & 1) ? 0.5f : 0.25f; + if (!close_enough(values[4*vector], want)) return 10+vector; + if (values[4*vector+1] != 10.0f || values[4*vector+2] != 20.0f || values[4*vector+3] != 30.0f) return 20+vector; + if (out[64+vector] != 1) return 30+vector; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "scalar_reciprocal_semantics", triple, ir, mainC, runPrefix) +} + +func TestTranslateX86ScalarReciprocalRejectsFormsOutsideGo127Tables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "RCPSS X0"}, + {goarch: "amd64", instruction: "RSQRTSS X0, X1, X2"}, + {goarch: "amd64", instruction: "RCPSS Y0, X1"}, + {goarch: "amd64", instruction: "RCPSS X0, X16"}, + {goarch: "amd64", instruction: "VRCPSS X0, X1"}, + {goarch: "amd64", instruction: "VRSQRTSS X0, X1, Y2"}, + {goarch: "amd64", instruction: "VRCPSS Y0, X1, X2"}, + {goarch: "amd64", instruction: "VRCPSS.Z X0, X1, X2"}, + {goarch: "amd64", instruction: "VRSQRTSS X0, X1, K1, X2"}, + {goarch: "386", instruction: "RCPSS X0, X8"}, + {goarch: "386", instruction: "RSQRTSS 8(R9), X0"}, + {goarch: "386", instruction: "VRCPSS X16, X1, X2"}, + {goarch: "386", instruction: "VRSQRTSS X0, X1, X16"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scalar reciprocal tables for %s", test.instruction, test.goarch) + } + }) + } +} diff --git a/amd64_lower_reciprocal_test.go b/amd64_lower_reciprocal_test.go new file mode 100644 index 00000000..55831835 --- /dev/null +++ b/amd64_lower_reciprocal_test.go @@ -0,0 +1,110 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedReciprocalCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's legacy yxm table accepts X/m128 -> X, while the VEX + // _yvptest table accepts both X/m128 -> X and Y/m256 -> Y. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast := 15 + if target.goarch == "386" { + legacyLast = 7 + } + const vexLast = 15 + var source strings.Builder + source.WriteString("TEXT packedreciprocalforms(SB),$0-0\n") + for _, op := range []string{"RCPPS", "RSQRTPS"} { + fmt.Fprintf(&source, "\t%s X1, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s 0, X%d\n", op, legacyLast) + } + for _, op := range []string{"VRCPPS", "VRSQRTPS"} { + fmt.Fprintf(&source, "\t%s X1, X%d\n", op, vexLast) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, vexLast) + fmt.Fprintf(&source, "\t%s Y1, Y%d\n", op, vexLast) + fmt.Fprintf(&source, "\t%s 16(AX), Y%d\n", op, vexLast) + fmt.Fprintf(&source, "\t%s 0, Y%d\n", op, vexLast) + } + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedreciprocalforms": {Name: "packedreciprocalforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{"@llvm.x86.sse.rcp.ps", "@llvm.x86.sse.rsqrt.ps", "@llvm.x86.avx.rcp.ps.256", "@llvm.x86.avx.rsqrt.ps.256"} { + if !strings.Contains(ll, intrinsic) { + t.Fatalf("translation omitted %s:\n%s", intrinsic, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-reciprocal-"+target.name+".ll", "packed-reciprocal-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedReciprocalRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "RCPPS Y0, X1"}, + {goarch: "amd64", instruction: "RSQRTPS X0, X16"}, + {goarch: "amd64", instruction: "VRCPPS X16, X1"}, + {goarch: "amd64", instruction: "VRCPPS Y0, X1"}, + {goarch: "amd64", instruction: "VRSQRTPS Z0, Z1"}, + {goarch: "amd64", instruction: "VRCPPS.Z X0, X1"}, + {goarch: "amd64", instruction: "VRSQRTPS X0, K1, X1"}, + {goarch: "386", instruction: "RCPPS X0, X8"}, + {goarch: "386", instruction: "VRCPPS X16, X0"}, + {goarch: "386", instruction: "VRCPPS Y16, Y0"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's reciprocal tables for %s", test.instruction, test.goarch) + } + }) + } +} diff --git a/amd64_lower_rorx_test.go b/amd64_lower_rorx_test.go new file mode 100644 index 00000000..898241ce --- /dev/null +++ b/amd64_lower_rorx_test.go @@ -0,0 +1,230 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestX86RawRORXReportedEncoding(t *testing.T) { + const source = ` +TEXT rawRORX(SB),$0-0 + BYTE $0xc4 + BYTE $0xe3 + BYTE $0x7b + BYTE $0xf0 + BYTE $0xe8 + BYTE $0x19 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + {goarch: "386", triple: "i686-pc-windows-msvc"}, + {goarch: "amd64", triple: "x86_64-apple-darwin"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"rawRORX": {Name: "rawRORX", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, `"target-features"="+bmi2"`) { + t.Fatalf("raw RORX did not infer BMI2 target feature:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "raw-rorx.ll", "raw-rorx.o", ir) + }) + } +} + +func TestX86RORXGo127CompleteNamedForms(t *testing.T) { + const source = ` +TEXT rorxforms(SB),$0-0 + RORXL $7, (BX), DX + RORXL $31, R11, R12 + RORXQ $7, 16(BX)(SI*2), DX + RORXQ $63, R11, R12 + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"rorxforms": {Name: "rorxforms", Ret: Void}}, + }); err != nil { + t.Fatal(err) + } +} + +func TestX86RORXCompleteGo127FormsAcrossTargets(t *testing.T) { + registers386 := []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"} + registersAMD64 := append(append([]string{}, registers386...), "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15") + targets := []struct { + name string + goarch string + triple string + registers []string + }{ + {name: "386-linux", goarch: "386", triple: "i386-unknown-linux-gnu", registers: registers386}, + {name: "386-windows", goarch: "386", triple: "i686-pc-windows-msvc", registers: registers386}, + {name: "amd64-darwin", goarch: "amd64", triple: "x86_64-apple-darwin", registers: registersAMD64}, + {name: "amd64-linux", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", registers: registersAMD64}, + {name: "amd64-windows", goarch: "amd64", triple: "x86_64-pc-windows-msvc", registers: registersAMD64}, + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range targets { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rorxall(SB),$0-0\n") + for _, width := range []string{"L", "Q"} { + for index, sourceRegister := range target.registers { + destination := target.registers[(index+3)%len(target.registers)] + fmt.Fprintf(&source, "\tRORX%s $%d, %s, %s\n", width, index*17&255, sourceRegister, destination) + } + fmt.Fprintf(&source, "\tRORX%s $-1, 8(AX), DX\n", width) + fmt.Fprintf(&source, "\tRORX%s $63, 16(AX)(CX*4), BX\n", width) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"rorxall": {Name: "rorxall", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, `"target-features"="+bmi2"`) { + t.Fatalf("RORX family did not infer BMI2 target feature:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "rorx-family.ll", "rorx-family.o", ir) + }) + } +} + +func TestX86RawRORXCompleteRegisterFields(t *testing.T) { + for _, mode := range []int{32, 64} { + registerCount := 8 + if mode == 64 { + registerCount = 16 + } + for _, width64 := range []bool{false, true} { + for source := 0; source < registerCount; source++ { + for destination := 0; destination < registerCount; destination++ { + for _, immediate := range []byte{0, 1, 31, 32, 63, 255} { + p0 := byte((^destination>>3)&1)<<7 | 1<<6 | byte((^source>>3)&1)<<5 | 3 + p1 := byte(0x7b) + if width64 { + p1 |= 0x80 + } + modRM := byte(0xc0 | destination&7<<3 | source&7) + encoding := []byte{0xc4, p0, p1, 0xf0, modRM, immediate} + instruction, length, ok, err := decodedX86RORXInstruction(encoding, mode) + if !ok || err != nil || length != len(encoding) { + t.Fatalf("mode=%d width64=%v source=%d destination=%d immediate=%d: ok=%v length=%d err=%v", mode, width64, source, destination, immediate, ok, length, err) + } + wantOp := Op("RORXL") + if width64 && mode == 64 { + wantOp = "RORXQ" + } + wantSource, _ := decodedX86GeneralRegister(source) + wantDestination, _ := decodedX86GeneralRegister(destination) + if instruction.Op != wantOp || len(instruction.Args) != 3 || instruction.Args[0].Imm != int64(immediate) || instruction.Args[1].Reg != wantSource || instruction.Args[2].Reg != wantDestination { + t.Fatalf("encoding %x decoded as %#v", encoding, instruction) + } + } + } + } + } + } +} + +func TestX86RawRORXMemoryForms(t *testing.T) { + for _, test := range []struct { + name string + encoding []byte + }{ + {name: "direct", encoding: []byte{0xc4, 0xe3, 0x7b, 0xf0, 0x13, 0x07}}, + {name: "extended base", encoding: []byte{0xc4, 0xc3, 0x7b, 0xf0, 0x13, 0x07}}, + {name: "sib disp8", encoding: []byte{0xc4, 0x83, 0xfb, 0xf0, 0x54, 0x88, 0x10, 0xff}}, + {name: "base less", encoding: []byte{0xc4, 0xe3, 0x7b, 0xf0, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, 0x1f}}, + {name: "segment", encoding: []byte{0x64, 0xc4, 0xe3, 0x7b, 0xf0, 0x54, 0x48, 0x08, 0x1f}}, + } { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86RORXInstruction(test.encoding, 64) + if !ok || err != nil || length != len(test.encoding) || len(instruction.Args) != 3 || instruction.Args[1].Kind != OpMem { + t.Fatalf("encoding %x: instruction=%#v ok=%v length=%d err=%v", test.encoding, instruction, ok, length, err) + } + }) + } +} + +func TestX86RawRORXRejectsReservedAndUnsafeForms(t *testing.T) { + for _, test := range []struct { + name string + mode int + encoding []byte + }{ + {name: "vex l", mode: 64, encoding: []byte{0xc4, 0xe3, 0x7f, 0xf0, 0xd2, 0x07}}, + {name: "vex pp", mode: 64, encoding: []byte{0xc4, 0xe3, 0x79, 0xf0, 0xd2, 0x07}}, + {name: "vex vvvv", mode: 64, encoding: []byte{0xc4, 0xe3, 0x73, 0xf0, 0xd2, 0x07}}, + {name: "missing modrm", mode: 64, encoding: []byte{0xc4, 0xe3, 0x7b, 0xf0}}, + {name: "missing immediate", mode: 64, encoding: []byte{0xc4, 0xe3, 0x7b, 0xf0, 0xd2}}, + {name: "address override", mode: 64, encoding: []byte{0x67, 0xc4, 0xe3, 0x7b, 0xf0, 0xd2, 0x07}}, + {name: "rip relative", mode: 64, encoding: []byte{0xc4, 0xe3, 0x7b, 0xf0, 0x15, 0, 0, 0, 0, 0x07}}, + {name: "extended source 386", mode: 32, encoding: []byte{0xc4, 0xc3, 0x7b, 0xf0, 0xc0, 0x07}}, + {name: "extended destination 386", mode: 32, encoding: []byte{0xc4, 0x63, 0x7b, 0xf0, 0xc0, 0x07}}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86RORXInstruction(test.encoding, test.mode) + if !ok || err == nil { + t.Fatalf("encoding %x: ok=%v err=%v, want recognized rejection", test.encoding, ok, err) + } + }) + } +} + +func TestX86RORXGo127ModeOracle(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + want bool + }{ + {goarch: "386", instruction: "RORXL $7, (BX), DX", want: true}, + {goarch: "386", instruction: "RORXQ $7, (BX), DX", want: true}, + {goarch: "386", instruction: "RORXL $7, R8, DX", want: false}, + {goarch: "amd64", instruction: "RORXQ $7, R8, R15", want: true}, + } { + t.Run(fmt.Sprintf("%s/%s", test.goarch, test.instruction), func(t *testing.T) { + requireX86GoAssemblerResult(t, test.goarch, "TEXT oracle(SB),$0-0\n\t"+test.instruction+"\n\tRET\n", test.want) + }) + } +} diff --git a/amd64_lower_round.go b/amd64_lower_round.go new file mode 100644 index 00000000..dea3e412 --- /dev/null +++ b/amd64_lower_round.go @@ -0,0 +1,153 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64RoundSpec struct { + laneBits int + scalar bool + vector bool +} + +// amd64RoundSpecs mirrors Go 1.27's yxshuf, _yvroundpd, and _yvdppd tables. +// The legacy family is X-only, the packed VEX family is X/Y, and the scalar +// VEX family has an explicit upper-lane source. +var amd64RoundSpecs = map[Op]amd64RoundSpec{ + "ROUNDPS": {laneBits: 32}, + "ROUNDPD": {laneBits: 64}, + "ROUNDSS": {laneBits: 32, scalar: true}, + "ROUNDSD": {laneBits: 64, scalar: true}, + "VROUNDPS": {laneBits: 32, vector: true}, + "VROUNDPD": {laneBits: 64, vector: true}, + "VROUNDSS": {laneBits: 32, scalar: true, vector: true}, + "VROUNDSD": {laneBits: 64, scalar: true, vector: true}, +} + +func (c *amd64Ctx) lowerRound(rawOp Op, ins Instr) (ok bool, terminated bool, err error) { + raw := strings.ToUpper(string(rawOp)) + if strings.Contains(raw, ".") { + base := Op(strings.SplitN(raw, ".", 2)[0]) + if _, recognized := amd64RoundSpecs[base]; recognized { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, base, ins.Raw) + } + return false, false, nil + } + spec, recognized := amd64RoundSpecs[Op(raw)] + if !recognized { + return false, false, nil + } + wantArgs := 3 + if spec.vector && spec.scalar { + wantArgs = 4 + } + if len(ins.Args) != wantArgs { + return true, false, fmt.Errorf("%s %s expects immediate, source, %sdestination: %q", c.goarch, raw, map[bool]string{true: "upper-lane source, "}[spec.vector && spec.scalar], ins.Raw) + } + if ins.Args[0].Kind != OpImm { + return true, false, fmt.Errorf("%s %s expects an 8-bit immediate: %q", c.goarch, raw, ins.Raw) + } + imm := ins.Args[0].Imm + if (!spec.vector && (imm < 0 || imm > 255)) || (spec.vector && (imm < -128 || imm > 255)) { + return true, false, fmt.Errorf("%s %s immediate is outside Go 1.27's table: %q", c.goarch, raw, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s %s destination must be a vector register: %q", c.goarch, raw, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if spec.scalar { + if byteWidth != 16 || !c.isGoVEXVectorRegister(destination, 16, false) { + return true, false, fmt.Errorf("%s %s destination must be an X register in the Go VEX class: %q", c.goarch, raw, ins.Raw) + } + } else if (!spec.vector && byteWidth != 16) || (spec.vector && byteWidth != 16 && byteWidth != 32) || !c.isGoVEXVectorRegister(destination, byteWidth, false) { + return true, false, fmt.Errorf("%s %s destination has a width outside Go 1.27's table: %q", c.goarch, raw, ins.Raw) + } + source := ins.Args[1] + if !c.isGoVEXVectorRegister(source, byteWidth, true) { + return true, false, fmt.Errorf("%s %s source must be same-width X/Y or memory: %q", c.goarch, raw, ins.Raw) + } + if spec.vector && spec.scalar { + upper := ins.Args[2] + if !c.isGoVEXVectorRegister(upper, 16, false) { + return true, false, fmt.Errorf("%s %s upper-lane source must be an X register: %q", c.goarch, raw, ins.Raw) + } + } + intrinsic := amd64RoundIntrinsic(uint8(imm)) + if spec.scalar { + return c.lowerScalarRound(spec, ins, destination, intrinsic) + } + return c.lowerPackedRound(spec, source, destination, byteWidth, intrinsic) +} + +func amd64RoundIntrinsic(imm uint8) string { + if imm&4 != 0 { + return "rint" + } + switch imm & 3 { + case 0: + return "roundeven" + case 1: + return "floor" + case 2: + return "ceil" + default: + return "trunc" + } +} + +func (c *amd64Ctx) lowerScalarRound(spec amd64RoundSpec, ins Instr, destination Operand, intrinsic string) (bool, bool, error) { + value, err := c.evalScalarFloatForInteger(ins.Args[1], spec.laneBits) + if err != nil { + return true, false, err + } + rounded := c.emitScalarFloatRound(value, spec.laneBits, intrinsic) + bits := c.newTmp() + floatingType := amd64FloatingTypeForBits(spec.laneBits) + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to i%d\n", bits, floatingType, rounded, spec.laneBits) + baseReg := destination.Reg + if spec.vector { + baseReg = ins.Args[2].Reg + } + baseBytes, err := c.loadX(baseReg) + if err != nil { + return true, false, err + } + base := c.bitcastVectorBytesToIntegerLanes(16, 128/spec.laneBits, spec.laneBits, baseBytes) + return true, false, c.storeVectorScalarRegister(destination.Reg, spec.laneBits, "%"+bits, base, "", false) +} + +func (c *amd64Ctx) lowerPackedRound(spec amd64RoundSpec, source, destination Operand, byteWidth int, intrinsic string) (bool, bool, error) { + bytesValue, err := c.loadPackedCompareBytes(source, byteWidth) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / spec.laneBits + floatingType := fmt.Sprintf("<%d x %s>", lanes, amd64FloatingTypeForBits(spec.laneBits)) + floating := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", floating, byteWidth, bytesValue, floatingType) + result := "poison" + for lane := 0; lane < lanes; lane++ { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", value, floatingType, floating, lane) + rounded := c.emitScalarFloatRound("%"+value, spec.laneBits, intrinsic) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, %s %s, i32 %d\n", inserted, floatingType, result, amd64FloatingTypeForBits(spec.laneBits), rounded, lane) + result = "%" + inserted + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", out, floatingType, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitScalarFloatRound(value string, bits int, intrinsic string) string { + typeName := amd64FloatingTypeForBits(bits) + intrinsicSuffix := "f64" + if bits == 32 { + intrinsicSuffix = "f32" + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.%s(%s %s)\n", result, typeName, intrinsic, intrinsicSuffix, typeName, value) + return "%" + result +} diff --git a/amd64_lower_round_test.go b/amd64_lower_round_test.go new file mode 100644 index 00000000..f2683856 --- /dev/null +++ b/amd64_lower_round_test.go @@ -0,0 +1,211 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86RoundCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT roundforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"ROUNDPS", "ROUNDPD", "ROUNDSS", "ROUNDSD"} { + fmt.Fprintf(&source, "\t%s $0, X0, X1\n", op) + fmt.Fprintf(&source, "\t%s $255, 8(BX), X2\n", op) + } + for _, op := range []string{"VROUNDPS", "VROUNDPD"} { + fmt.Fprintf(&source, "\t%s $0, X0, X1\n", op) + fmt.Fprintf(&source, "\t%s $-1, 16(BX), X2\n", op) + fmt.Fprintf(&source, "\t%s $255, Y0, Y1\n", op) + fmt.Fprintf(&source, "\t%s $2, 32(BX), Y2\n", op) + } + for _, op := range []string{"VROUNDSS", "VROUNDSD"} { + fmt.Fprintf(&source, "\t%s $0, X0, X1, X2\n", op) + fmt.Fprintf(&source, "\t%s $-1, 8(BX), X1, X2\n", op) + fmt.Fprintf(&source, "\t%s $255, X0, X1, X2\n", op) + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"roundforms": {Name: "roundforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "round-"+target.name+".ll", "round-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86RoundRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + tests := []struct { + goarch string + triple string + instruction string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "ROUNDSD $-1, X0, X1"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "ROUNDSS $256, X0, X1"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "ROUNDPD $0, Y0, Y1"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "ROUNDPS $0, X0, Y1"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "ROUNDSS.Z $0, X0, X1"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VROUNDPS $-129, X0, X1"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VROUNDPD $256, Y0, Y1"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VROUNDPS $0, X0, Y1"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VROUNDSS $0, X0, X1"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VROUNDSD $0, X0, Y1, X2"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VROUNDSS $0, X0, X1, Y2"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "ROUNDSS $0, X8, X0"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "VROUNDPS $0, Y8, Y0"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "VROUNDSD $0, X0, X8, X1"}, + } + for _, test := range tests { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+test.instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: test.triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ROUND tables for %s", test.instruction, test.goarch) + } + }) + } +} + +func TestAMD64RoundRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT roundsemantics(SB),NOSPLIT,$0-40 + MOVQ out+0(FP), AX + MOVQ a32+8(FP), BX + MOVQ a64+16(FP), CX + MOVQ upper32+24(FP), DX + MOVQ upper64+32(FP), SI + ROUNDPS $0, (BX), X0 + MOVUPS X0, 0(AX) + ROUNDPS $1, (BX), X0 + MOVUPS X0, 16(AX) + ROUNDPS $2, (BX), X0 + MOVUPS X0, 32(AX) + ROUNDPS $3, (BX), X0 + MOVUPS X0, 48(AX) + ROUNDPS $4, (BX), X0 + MOVUPS X0, 64(AX) + MOVUPS (DX), X1 + VROUNDSS $1, (BX), X1, X2 + MOVUPS X2, 80(AX) + ROUNDPD $0, (CX), X0 + MOVUPD X0, 96(AX) + ROUNDPD $1, (CX), X0 + MOVUPD X0, 112(AX) + ROUNDPD $2, (CX), X0 + MOVUPD X0, 128(AX) + ROUNDPD $3, (CX), X0 + MOVUPD X0, 144(AX) + ROUNDPD $4, (CX), X0 + MOVUPD X0, 160(AX) + MOVUPD (SI), X1 + VROUNDSD $2, (CX), X1, X2 + MOVUPD X2, 176(AX) + VZEROUPPER + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "roundsemantics": {Name: "roundsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +extern void roundsemantics(uint8_t *, const float *, const double *, const float *, const double *); +static int check32(const float *got, const float *want, int base) { + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return base+i; + return 0; +} +static int check64(const double *got, const double *want, int base) { + for (int i = 0; i < 2; i++) if (got[i] != want[i]) return base+i; + return 0; +} +int main(void) { + float a32[4] = {1.5f, -1.5f, 2.75f, -2.75f}; + double a64[2] = {2.5, -2.5}; + float upper32[4] = {99.0f, 10.0f, 20.0f, 30.0f}; + double upper64[2] = {99.0, 40.0}; + float want32[6][4] = { + {2, -2, 3, -3}, {1, -2, 2, -3}, {2, -1, 3, -2}, + {1, -1, 2, -2}, {2, -2, 3, -3}, {1, 10, 20, 30}, + }; + double want64[6][2] = { + {2, -2}, {2, -3}, {3, -2}, {2, -2}, {2, -2}, {3, 40}, + }; + uint8_t out[192] = {0}; + roundsemantics(out, a32, a64, upper32, upper64); + for (int i = 0; i < 6; i++) { + int failed = check32((const float *)(out + 16*i), want32[i], 10+4*i); + if (failed) return failed; + } + for (int i = 0; i < 6; i++) { + int failed = check64((const double *)(out + 96 + 16*i), want64[i], 40+2*i); + if (failed) return failed; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "round_semantics", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_rtm.go b/amd64_lower_rtm.go new file mode 100644 index 00000000..92c78529 --- /dev/null +++ b/amd64_lower_rtm.go @@ -0,0 +1,173 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64RTMKind uint8 + +const ( + amd64RTMBegin amd64RTMKind = iota + amd64RTMAbort + amd64RTMEnd + amd64RTMTest +) + +type amd64RTMOperand uint8 + +const ( + amd64RTMNoOperand amd64RTMOperand = iota + amd64RTMBranch + amd64RTMUnsignedByte +) + +type amd64RTMSpec struct { + kind amd64RTMKind + operand amd64RTMOperand + outputAX bool +} + +// amd64RTMSpecs is the complete Go 1.27 Restricted Transactional Memory +// grammar. XBEGIN is included even though Go's positive encoder corpus keeps +// its cases as TODOs: the optab accepts one Ybr target and writes abort status +// to EAX. XABORT accepts the complete Yu8 immediate domain. +var amd64RTMSpecs = map[Op]amd64RTMSpec{ + "XBEGIN": {kind: amd64RTMBegin, operand: amd64RTMBranch, outputAX: true}, + "XABORT": {kind: amd64RTMAbort, operand: amd64RTMUnsignedByte}, + "XEND": {kind: amd64RTMEnd}, + "XTEST": {kind: amd64RTMTest}, +} + +type amd64RTMForm struct { + branch Operand + immediate uint8 +} + +func (c *amd64Ctx) lowerRTM(bi int, ii int, op Op, ins Instr, emitCondBr amd64EmitCondBr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64RTMSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + form, err := c.parseRTMForm(baseOp, spec, ins) + if err != nil { + return true, false, err + } + return c.emitRTM(bi, ii, baseOp, spec, form, emitCondBr) +} + +func (c *amd64Ctx) parseRTMForm(op string, spec amd64RTMSpec, ins Instr) (amd64RTMForm, error) { + var form amd64RTMForm + switch spec.operand { + case amd64RTMNoOperand: + if len(ins.Args) != 0 { + return form, fmt.Errorf("%s %s takes no operands: %q", c.goarch, op, ins.Raw) + } + case amd64RTMBranch: + if len(ins.Args) != 1 { + return form, fmt.Errorf("%s %s expects one Go 1.27 Ybr target: %q", c.goarch, op, ins.Raw) + } + form.branch = ins.Args[0] + case amd64RTMUnsignedByte: + if len(ins.Args) != 1 || ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return form, fmt.Errorf("%s %s expects one Go 1.27 Yu8 immediate: %q", c.goarch, op, ins.Raw) + } + form.immediate = uint8(ins.Args[0].Imm) + default: + panic("unknown amd64 RTM operand kind") + } + return form, nil +} + +func (c *amd64Ctx) rtmBranchTarget(bi int, ii int, operand Operand) (string, error) { + knownBlock := func(name string) bool { + for _, block := range c.blocks { + if block.name == name { + return true + } + } + return false + } + var target string + switch operand.Kind { + case OpIdent: + target = operand.Ident + case OpReg: + target = string(operand.Reg) + if !knownBlock(target) { + return "", fmt.Errorf("%s XBEGIN register is not a local branch target: %q", c.goarch, target) + } + case OpSym: + target = strings.TrimSpace(operand.Sym) + if strings.HasSuffix(target, "(SB)") { + return "", fmt.Errorf("%s XBEGIN target must be local: %q", c.goarch, target) + } + target = strings.TrimSuffix(target, "<>") + case OpMem: + if !strings.EqualFold(string(operand.Mem.Base), "PC") { + return "", fmt.Errorf("%s XBEGIN expects a label or PC-relative target", c.goarch) + } + current := c.blockBase[bi] + ii + index := current + int(operand.Mem.Off) + targetBlock, ok := c.blockByIdx[index] + if !ok || targetBlock < 0 || targetBlock >= len(c.blocks) { + return "", fmt.Errorf("%s XBEGIN invalid PC-relative target %d(PC)", c.goarch, operand.Mem.Off) + } + target = c.blocks[targetBlock].name + default: + return "", fmt.Errorf("%s XBEGIN expects one Go 1.27 Ybr target", c.goarch) + } + if target == "" || !knownBlock(target) { + return "", fmt.Errorf("%s XBEGIN unknown local target %q", c.goarch, target) + } + return target, nil +} + +func (c *amd64Ctx) emitRTM(bi int, ii int, op string, spec amd64RTMSpec, form amd64RTMForm, emitCondBr amd64EmitCondBr) (bool, bool, error) { + switch spec.kind { + case amd64RTMBegin: + if bi+1 >= len(c.blocks) { + return true, false, fmt.Errorf("%s XBEGIN has no success fallthrough", c.goarch) + } + target, err := c.rtmBranchTarget(bi, ii, form.branch) + if err != nil { + return true, false, err + } + status := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.x86.xbegin()\n", status) + if err := c.storeRegSized(AX, I32, "%"+status); err != nil { + return true, false, err + } + success := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %%%s, -1\n", success, status) + if err := emitCondBr("%"+success, c.blocks[bi+1].name, target); err != nil { + return true, false, err + } + return true, true, nil + case amd64RTMAbort: + fmt.Fprintf(c.b, " call void @llvm.x86.xabort(i8 %d)\n", form.immediate) + case amd64RTMEnd: + c.b.WriteString(" call void @llvm.x86.xend()\n") + case amd64RTMTest: + active := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.x86.xtest()\n", active) + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %%%s, 0\n", zero, active) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsSltSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsPFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + default: + panic("unknown amd64 RTM kind") + } + return true, false, nil +} diff --git a/amd64_lower_rtm_test.go b/amd64_lower_rtm_test.go new file mode 100644 index 00000000..82ff3d13 --- /dev/null +++ b/amd64_lower_rtm_test.go @@ -0,0 +1,122 @@ +package plan9asm + +import ( + "reflect" + "strings" + "testing" +) + +func TestAMD64RTMGrammarIsComplete(t *testing.T) { + want := map[Op]amd64RTMSpec{ + "XBEGIN": {kind: amd64RTMBegin, operand: amd64RTMBranch, outputAX: true}, + "XABORT": {kind: amd64RTMAbort, operand: amd64RTMUnsignedByte}, + "XEND": {kind: amd64RTMEnd}, + "XTEST": {kind: amd64RTMTest}, + } + if !reflect.DeepEqual(amd64RTMSpecs, want) { + t.Fatalf("RTM grammar = %+v, want %+v", amd64RTMSpecs, want) + } +} + +func TestTranslateX86RTMCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := `TEXT rtmforms(SB),$0-0 + XBEGIN fallback + XTEST + XEND + RET +fallback: + XABORT $0 + XABORT $255 + RET +TEXT rtmpcrel(SB),$0-0 + XBEGIN 2(PC) + XEND + RET +` + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "rtmforms": {Name: "rtmforms", Ret: Void}, + "rtmpcrel": {Name: "rtmpcrel", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+rtm"`, + `call i32 @llvm.x86.xbegin()`, + `call i32 @llvm.x86.xtest()`, + `call void @llvm.x86.xend()`, + `call void @llvm.x86.xabort(i8 0)`, + `call void @llvm.x86.xabort(i8 -1)`, + `icmp eq i32`, + `store i1 %`, + `br i1 %`, + } { + if !strings.Contains(ir, want) { + t.Errorf("IR is missing %s:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "rtm-"+target.name+".ll", "rtm-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86RTMRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "XBEGIN AX"}, + {goarch: "amd64", instruction: "XBEGIN (BX)"}, + {goarch: "amd64", instruction: "XABORT"}, + {goarch: "amd64", instruction: "XABORT $-1"}, + {goarch: "amd64", instruction: "XABORT $256"}, + {goarch: "amd64", instruction: "XABORT AX"}, + {goarch: "amd64", instruction: "XEND AX"}, + {goarch: "amd64", instruction: "XTEST.P"}, + {goarch: "386", instruction: "XABORT $256"}, + {goarch: "386", instruction: "XTEST AX"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's RTM tables", test.instruction) + } + }) + } +} diff --git a/amd64_lower_sad.go b/amd64_lower_sad.go new file mode 100644 index 00000000..268e9f56 --- /dev/null +++ b/amd64_lower_sad.go @@ -0,0 +1,343 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedSADKind uint8 + +const ( + amd64PackedSADBlockSum amd64PackedSADKind = iota + amd64PackedSADMultiple + amd64PackedSADDoubleBlock +) + +type amd64PackedSADForm uint8 + +const ( + amd64PackedSADLegacyX amd64PackedSADForm = iota + amd64PackedSADVEXXY + amd64PackedSADEVEXXYZ +) + +type amd64PackedSADSpec struct { + kind amd64PackedSADKind + form amd64PackedSADForm +} + +// amd64PackedSADSpecs is the complete Go 1.27 byte-SAD grammar. PSADBW uses +// fixed eight-byte block sums, MPSADBW uses one immediate-selected four-byte +// block and sliding windows, and VDBPSADBW independently selects four dwords +// before its sliding SAD. Their vector spellings intentionally differ: +// VPSADBW has EVEX X/Y/Z rows, VMPSADBW is VEX X/Y only, and VDBPSADBW adds +// EVEX writemasking to X/Y/Z. +var amd64PackedSADSpecs = map[Op]amd64PackedSADSpec{ + "PSADBW": {kind: amd64PackedSADBlockSum, form: amd64PackedSADLegacyX}, + "VPSADBW": {kind: amd64PackedSADBlockSum, form: amd64PackedSADEVEXXYZ}, + "MPSADBW": {kind: amd64PackedSADMultiple, form: amd64PackedSADLegacyX}, + "VMPSADBW": {kind: amd64PackedSADMultiple, form: amd64PackedSADVEXXY}, + "VDBPSADBW": {kind: amd64PackedSADDoubleBlock, form: amd64PackedSADEVEXXYZ}, +} + +// lowerPackedSumAbsoluteDifferences implements Go 1.27's complete byte-SAD +// family. Only VDBPSADBW has masking and a suffix form. +func (c *amd64Ctx) lowerPackedSumAbsoluteDifferences(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64PackedSADSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if spec.kind == amd64PackedSADDoubleBlock { + return c.lowerDoubleBlockSumAbsoluteDifferences(baseOp, rawOp, ins) + } + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + if spec.kind == amd64PackedSADMultiple { + return c.lowerMultipleSumAbsoluteDifferences(baseOp, spec, ins) + } + if spec.form == amd64PackedSADLegacyX { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg || !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("%s PSADBW expects X/m source and an in-range X destination: %q", c.goarch, ins.Raw) + } + if ins.Args[0].Kind == OpReg && !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s PSADBW register source must be an in-range X register: %q", c.goarch, ins.Raw) + } + if ins.Args[0].Kind == OpMem && !x86MemoryRegistersValidForArch(ins.Args[0].Mem, c.goarch) { + return true, false, fmt.Errorf("%s PSADBW source uses an out-of-range address register: %q", c.goarch, ins.Raw) + } + first, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + second, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + result := c.emitPackedSumAbsoluteByteDifferences(16, first, second) + return true, false, c.storeX(ins.Args[1].Reg, result) + } + + if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("amd64 VPSADBW expects src1, src2, destination: %q", ins.Raw) + } + byteWidth := amd64VectorByteWidth(ins.Args[2].Reg) + if byteWidth == 0 { + return true, false, fmt.Errorf("amd64 VPSADBW destination must be X, Y, or Z: %q", ins.Raw) + } + if !amd64VectorRegisterHasWidth(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("amd64 VPSADBW second source must match its destination width: %q", ins.Raw) + } + if ins.Args[0].Kind == OpReg && !amd64VectorRegisterHasWidth(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("amd64 VPSADBW first source must match its destination width: %q", ins.Raw) + } + first, err := c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err != nil { + return true, false, err + } + second, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + result := c.emitPackedSumAbsoluteByteDifferences(byteWidth, first, second) + return true, false, c.storeVectorBytes(ins.Args[2].Reg, byteWidth, result) +} + +// lowerDoubleBlockSumAbsoluteDifferences implements the EVEX VDBPSADBW table. +// Go's Plan 9 order is imm8, SRC2, SRC1, [K,] destination. The shared x86 +// encoder table exists on 386, but cmd/asm cannot represent its four- and +// five-operand forms there. +func (c *amd64Ctx) lowerDoubleBlockSumAbsoluteDifferences(baseOp, rawOp string, ins Instr) (bool, bool, error) { + zeroing := rawOp == baseOp+".Z" + if rawOp != baseOp && !zeroing { + return true, false, fmt.Errorf("amd64 %s accepts only the optional .Z suffix: %q", baseOp, ins.Raw) + } + if c.goarch == "386" { + return true, false, fmt.Errorf("386 %s is outside Go 1.27's accepted instruction forms: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 5 + if len(ins.Args) != 4 && !masked || !amd64UnsignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("amd64 %s expects $imm8, X|Y|Z/mem, X|Y|Z, [K,] X|Y|Z: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s.Z requires K1-K7: %q", baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + byteWidth := amd64VectorByteWidth(destination.Reg) + if destination.Kind != OpReg || byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's X/Y/Z register classes: %q", baseOp, ins.Raw) + } + source2, source1 := ins.Args[1], ins.Args[2] + if source2.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source2, byteWidth) { + return true, false, fmt.Errorf("amd64 %s SRC2 register must match its destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source2) { + return true, false, fmt.Errorf("amd64 %s SRC2 must be a matching vector register or memory: %q", baseOp, ins.Raw) + } + if !c.isGoEVEXVectorRegister(source1, byteWidth) { + return true, false, fmt.Errorf("amd64 %s SRC1 must match its destination width: %q", baseOp, ins.Raw) + } + maskValue := "" + if masked { + mask := ins.Args[3] + if !amd64NonzeroKOperand(mask) { + return true, false, fmt.Errorf("amd64 %s masked form requires K1-K7: %q", baseOp, ins.Raw) + } + loaded, err := c.loadK(mask.Reg) + if err != nil { + return true, false, err + } + maskValue = loaded + } + source2Bytes, err := c.loadPackedCompareBytes(source2, byteWidth) + if err != nil { + return true, false, err + } + source1Bytes, err := c.loadPackedCompareBytes(source1, byteWidth) + if err != nil { + return true, false, err + } + lanes := byteWidth / 2 + result := c.emitDoubleBlockSumAbsoluteDifferences(byteWidth, source1Bytes, source2Bytes, uint8(ins.Args[0].Imm)) + if masked { + oldBytes, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, 16, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, 16, result, old, maskValue, zeroing) + } + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i16> %s to <%d x i8>\n", bytesValue, lanes, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+bytesValue) +} + +func (c *amd64Ctx) emitDoubleBlockSumAbsoluteDifferences(byteWidth int, source1, source2 string, immediate uint8) string { + shuffled := "poison" + for laneBase := 0; laneBase < byteWidth; laneBase += 16 { + for destinationDWord := 0; destinationDWord < 4; destinationDWord++ { + sourceDWord := int(immediate>>(2*destinationDWord)) & 3 + for byteInDWord := 0; byteInDWord < 4; byteInDWord++ { + sourceIndex := laneBase + sourceDWord*4 + byteInDWord + destinationIndex := laneBase + destinationDWord*4 + byteInDWord + value, inserted := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i8> %s, i32 %d\n", value, byteWidth, source2, sourceIndex) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i8> %s, i8 %%%s, i32 %d\n", inserted, byteWidth, shuffled, value, destinationIndex) + shuffled = "%" + inserted + } + } + } + + lanes := byteWidth / 2 + result := "poison" + for blockBase := 0; blockBase < byteWidth; blockBase += 8 { + for outputInBlock := 0; outputInBlock < 4; outputInBlock++ { + source1Base := blockBase + if outputInBlock >= 2 { + source1Base += 4 + } + tmpBase := blockBase + outputInBlock + sum := "" + for byteInDWord := 0; byteInDWord < 4; byteInDWord++ { + firstByte, secondByte := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i8> %s, i32 %d\n", firstByte, byteWidth, source1, source1Base+byteInDWord) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i8> %s, i32 %d\n", secondByte, byteWidth, shuffled, tmpBase+byteInDWord) + firstWide, secondWide := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i16\n", firstWide, firstByte) + fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i16\n", secondWide, secondByte) + firstMinusSecond, secondMinusFirst, firstGreater, difference := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i16 %%%s, %%%s\n", firstMinusSecond, firstWide, secondWide) + fmt.Fprintf(c.b, " %%%s = sub i16 %%%s, %%%s\n", secondMinusFirst, secondWide, firstWide) + fmt.Fprintf(c.b, " %%%s = icmp uge i16 %%%s, %%%s\n", firstGreater, firstWide, secondWide) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i16 %%%s, i16 %%%s\n", difference, firstGreater, firstMinusSecond, secondMinusFirst) + if sum == "" { + sum = "%" + difference + } else { + added := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i16 %s, %%%s\n", added, sum, difference) + sum = "%" + added + } + } + outputLane := blockBase/2 + outputInBlock + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i16> %s, i16 %s, i32 %d\n", inserted, lanes, result, sum, outputLane) + result = "%" + inserted + } + } + return result +} + +func (c *amd64Ctx) lowerMultipleSumAbsoluteDifferences(baseOp string, spec amd64PackedSADSpec, ins Instr) (bool, bool, error) { + if len(ins.Args) == 0 || ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("%s %s expects a Yu8 immediate: %q", c.goarch, baseOp, ins.Raw) + } + immediate := uint8(ins.Args[0].Imm) + if spec.form == amd64PackedSADLegacyX { + if len(ins.Args) != 3 || !c.isGoVEXVectorRegister(ins.Args[2], 16, false) { + return true, false, fmt.Errorf("%s %s expects imm8, X/m128, X: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoVEXVectorRegister(ins.Args[1], 16, true) { + return true, false, fmt.Errorf("%s %s source must be X/m128: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[1].Kind == OpMem && !x86MemoryRegistersValidForArch(ins.Args[1].Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s source uses an out-of-range address register: %q", c.goarch, baseOp, ins.Raw) + } + first, err := c.loadPackedCompareBytes(ins.Args[1], 16) + if err != nil { + return true, false, err + } + second, err := c.loadPackedCompareBytes(ins.Args[2], 16) + if err != nil { + return true, false, err + } + result := c.emitMultipleSumAbsoluteDifferences(16, first, second, immediate) + return true, false, c.storeX(ins.Args[2].Reg, result) + } + + if c.goarch == "386" { + return true, false, fmt.Errorf("386 %s exceeds the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 4 || ins.Args[3].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects imm8, source1, source2, destination: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(ins.Args[3].Reg) + if byteWidth != 16 && byteWidth != 32 { + return true, false, fmt.Errorf("amd64 %s destination must be a VEX X or Y register: %q", baseOp, ins.Raw) + } + if !c.isGoVEXVectorRegister(ins.Args[3], byteWidth, false) || !c.isGoVEXVectorRegister(ins.Args[2], byteWidth, false) { + return true, false, fmt.Errorf("amd64 %s second source and destination must be matching VEX registers: %q", baseOp, ins.Raw) + } + if !c.isGoVEXVectorRegister(ins.Args[1], byteWidth, true) { + return true, false, fmt.Errorf("amd64 %s first source must be a matching VEX register or memory: %q", baseOp, ins.Raw) + } + first, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + second, err := c.loadPackedCompareBytes(ins.Args[2], byteWidth) + if err != nil { + return true, false, err + } + result := c.emitMultipleSumAbsoluteDifferences(byteWidth, first, second, immediate) + return true, false, c.storeVectorBytes(ins.Args[3].Reg, byteWidth, result) +} + +func (c *amd64Ctx) emitMultipleSumAbsoluteDifferences(byteWidth int, first, second string, immediate uint8) string { + intrinsic := "llvm.x86.sse41.mpsadbw" + lanes := 8 + if byteWidth == 32 { + intrinsic = "llvm.x86.avx2.mpsadbw" + lanes = 16 + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <%d x i16> @%s(<%d x i8> %s, <%d x i8> %s, i8 %d)\n", result, lanes, intrinsic, byteWidth, second, byteWidth, first, immediate) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i16> %%%s to <%d x i8>\n", bytesValue, lanes, result, byteWidth) + return "%" + bytesValue +} + +func (c *amd64Ctx) emitPackedSumAbsoluteByteDifferences(byteWidth int, first, second string) string { + firstWide := c.newTmp() + secondWide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext <%d x i8> %s to <%d x i16>\n", firstWide, byteWidth, first, byteWidth) + fmt.Fprintf(c.b, " %%%s = zext <%d x i8> %s to <%d x i16>\n", secondWide, byteWidth, second, byteWidth) + firstMinusSecond := c.newTmp() + secondMinusFirst := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub <%d x i16> %%%s, %%%s\n", firstMinusSecond, byteWidth, firstWide, secondWide) + fmt.Fprintf(c.b, " %%%s = sub <%d x i16> %%%s, %%%s\n", secondMinusFirst, byteWidth, secondWide, firstWide) + firstGreater := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp uge <%d x i16> %%%s, %%%s\n", firstGreater, byteWidth, firstWide, secondWide) + differences := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, <%d x i16> %%%s, <%d x i16> %%%s\n", differences, byteWidth, firstGreater, byteWidth, firstMinusSecond, byteWidth, secondMinusFirst) + + groups := byteWidth / 8 + result := "zeroinitializer" + for group := 0; group < groups; group++ { + sum := "" + for lane := group * 8; lane < (group+1)*8; lane++ { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i16> %%%s, i32 %d\n", value, byteWidth, differences, lane) + if sum == "" { + sum = "%" + value + continue + } + added := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i16 %s, %%%s\n", added, sum, value) + sum = "%" + added + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i16 %s to i64\n", wide, sum) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i64> %s, i64 %%%s, i32 %d\n", inserted, groups, result, wide, group) + result = "%" + inserted + } + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i64> %s to <%d x i8>\n", bytesValue, groups, result, byteWidth) + return "%" + bytesValue +} diff --git a/amd64_lower_scalar_float_to_int.go b/amd64_lower_scalar_float_to_int.go new file mode 100644 index 00000000..0e729e25 --- /dev/null +++ b/amd64_lower_scalar_float_to_int.go @@ -0,0 +1,148 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64ScalarFloatToIntSpec struct { + inputBits int + outputBits int + truncating bool + unsigned bool + vector bool +} + +var amd64ScalarFloatToIntSpecs = map[Op]amd64ScalarFloatToIntSpec{ + "CVTSS2SL": {inputBits: 32, outputBits: 32}, + "CVTSS2SQ": {inputBits: 32, outputBits: 64}, + "CVTSD2SL": {inputBits: 64, outputBits: 32}, + "CVTSD2SQ": {inputBits: 64, outputBits: 64}, + "CVTTSS2SL": {inputBits: 32, outputBits: 32, truncating: true}, + "CVTTSS2SQ": {inputBits: 32, outputBits: 64, truncating: true}, + "CVTTSD2SL": {inputBits: 64, outputBits: 32, truncating: true}, + "CVTTSD2SQ": {inputBits: 64, outputBits: 64, truncating: true}, + + "VCVTSS2SI": {inputBits: 32, outputBits: 32, vector: true}, + "VCVTSS2SIQ": {inputBits: 32, outputBits: 64, vector: true}, + "VCVTSD2SI": {inputBits: 64, outputBits: 32, vector: true}, + "VCVTSD2SIQ": {inputBits: 64, outputBits: 64, vector: true}, + "VCVTTSS2SI": {inputBits: 32, outputBits: 32, truncating: true, vector: true}, + "VCVTTSS2SIQ": {inputBits: 32, outputBits: 64, truncating: true, vector: true}, + "VCVTTSD2SI": {inputBits: 64, outputBits: 32, truncating: true, vector: true}, + "VCVTTSD2SIQ": {inputBits: 64, outputBits: 64, truncating: true, vector: true}, + + "VCVTSS2USIL": {inputBits: 32, outputBits: 32, unsigned: true, vector: true}, + "VCVTSS2USIQ": {inputBits: 32, outputBits: 64, unsigned: true, vector: true}, + "VCVTSD2USIL": {inputBits: 64, outputBits: 32, unsigned: true, vector: true}, + "VCVTSD2USIQ": {inputBits: 64, outputBits: 64, unsigned: true, vector: true}, + "VCVTTSS2USIL": {inputBits: 32, outputBits: 32, truncating: true, unsigned: true, vector: true}, + "VCVTTSS2USIQ": {inputBits: 32, outputBits: 64, truncating: true, unsigned: true, vector: true}, + "VCVTTSD2USIL": {inputBits: 64, outputBits: 32, truncating: true, unsigned: true, vector: true}, + "VCVTTSD2USIQ": {inputBits: 64, outputBits: 64, truncating: true, unsigned: true, vector: true}, +} + +// lowerScalarFloatToInteger implements Go 1.27's complete signed legacy/VEX/ +// EVEX scalar float-to-integer family and its EVEX unsigned counterparts. +func (c *amd64Ctx) lowerScalarFloatToInteger(rawOp Op, ins Instr) (ok bool, terminated bool, err error) { + raw := strings.ToUpper(string(rawOp)) + parts := strings.Split(raw, ".") + baseOp := Op(parts[0]) + spec, recognized := amd64ScalarFloatToIntSpecs[baseOp] + if !recognized { + return false, false, nil + } + if len(parts) > 2 { + return true, false, fmt.Errorf("amd64 %s has multiple suffixes outside Go 1.27's scalar conversion table: %q", baseOp, ins.Raw) + } + suffix := "" + if len(parts) == 2 { + suffix = parts[1] + } + if !spec.vector && suffix != "" { + return true, false, fmt.Errorf("amd64 legacy %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + if spec.vector { + if spec.truncating { + if suffix != "" && suffix != "SAE" { + return true, false, fmt.Errorf("amd64 %s accepts only .SAE: %q", baseOp, ins.Raw) + } + } else { + switch suffix { + case "", "RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE": + default: + return true, false, fmt.Errorf("amd64 %s has invalid rounding suffix: %q", baseOp, ins.Raw) + } + } + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("amd64 %s expects scalar-X/memory source and GP destination: %q", baseOp, ins.Raw) + } + source, destination := ins.Args[0], ins.Args[1] + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's Yrl GP class: %q", baseOp, ins.Raw) + } + if c.goarch == "386" && spec.outputBits == 64 { + return true, false, fmt.Errorf("386 %s cannot encode a 64-bit GP destination: %q", baseOp, ins.Raw) + } + if !spec.vector { + if !c.isGoVEXVectorRegister(source, 16, true) { + return true, false, fmt.Errorf("amd64 %s source is outside Go 1.27's legacy X/memory class: %q", baseOp, ins.Raw) + } + } else { + if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, 16) { + return true, false, fmt.Errorf("amd64 %s source is outside Go 1.27's X register class: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s source must be X or memory: %q", baseOp, ins.Raw) + } + } + if suffix != "" && source.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s embedded rounding/SAE requires a register source: %q", baseOp, ins.Raw) + } + value, err := c.evalScalarFloatForInteger(source, spec.inputBits) + if err != nil { + return true, false, err + } + value = c.roundScalarFloatForInteger(value, spec.inputBits, spec.truncating, suffix) + outputType := amd64IntegerTypeForBits(spec.outputBits) + converted := c.newTmp() + operation := "fptosi" + if spec.unsigned { + operation = "fptoui" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", converted, operation, amd64FloatingTypeForBits(spec.inputBits), value, outputType) + return true, false, c.storeRegSized(destination.Reg, outputType, "%"+converted) +} + +func (c *amd64Ctx) evalScalarFloatForInteger(source Operand, bits int) (string, error) { + if bits == 32 { + return c.evalF32(source) + } + return c.evalF64(source) +} + +func amd64FloatingTypeForBits(bits int) LLVMType { + if bits == 32 { + return LLVMType("float") + } + return LLVMType("double") +} + +func (c *amd64Ctx) roundScalarFloatForInteger(value string, bits int, truncating bool, suffix string) string { + intrinsic := "rint" + if truncating || suffix == "RZ_SAE" || suffix == "SAE" { + intrinsic = "trunc" + } else { + switch suffix { + case "RN_SAE": + intrinsic = "roundeven" + case "RD_SAE": + intrinsic = "floor" + case "RU_SAE": + intrinsic = "ceil" + } + } + return c.emitScalarFloatRound(value, bits, intrinsic) +} diff --git a/amd64_lower_scalar_float_to_int_test.go b/amd64_lower_scalar_float_to_int_test.go new file mode 100644 index 00000000..62442753 --- /dev/null +++ b/amd64_lower_scalar_float_to_int_test.go @@ -0,0 +1,145 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86ScalarFloatToIntegerCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT scalarfloattointforms(SB),NOSPLIT,$0-0\n") + for _, precision := range []string{"SS", "SD"} { + for _, truncating := range []bool{false, true} { + prefix := "CVT" + if truncating { + prefix = "CVTT" + } + for _, width := range []string{"L", "Q"} { + if target.goarch == "386" && width == "Q" { + continue + } + op := prefix + precision + "2S" + width + fmt.Fprintf(&source, "\t%s X0, AX\n", op) + fmt.Fprintf(&source, "\t%s 8(BX), DI\n", op) + vop := "V" + prefix + precision + "2SI" + if width == "Q" { + vop += "Q" + } + fmt.Fprintf(&source, "\t%s X0, AX\n", vop) + fmt.Fprintf(&source, "\t%s 16(BX), DI\n", vop) + if truncating { + fmt.Fprintf(&source, "\t%s.SAE X16, AX\n", vop) + } else { + for _, rounding := range []string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"} { + fmt.Fprintf(&source, "\t%s.%s X16, AX\n", vop, rounding) + } + } + } + } + for _, truncating := range []bool{false, true} { + prefix := "VCVT" + if truncating { + prefix = "VCVTT" + } + for _, width := range []string{"L", "Q"} { + if target.goarch == "386" && width == "Q" { + continue + } + op := prefix + precision + "2USI" + width + fmt.Fprintf(&source, "\t%s X16, AX\n", op) + fmt.Fprintf(&source, "\t%s 24(BX), DI\n", op) + if truncating { + fmt.Fprintf(&source, "\t%s.SAE X16, AX\n", op) + } else { + for _, rounding := range []string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"} { + fmt.Fprintf(&source, "\t%s.%s X16, AX\n", op, rounding) + } + } + } + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"scalarfloattointforms": {Name: "scalarfloattointforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "scalar-float-to-int-"+target.name+".ll", "scalar-float-to-int-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86ScalarFloatToIntegerRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "CVTSS2SL Y0, AX", + "CVTTSD2SQ X16, AX", + "CVTSS2SL X0, X1", + "CVTSS2SL.Z X0, AX", + "VCVTSS2SI Y0, AX", + "VCVTSS2SI X0, X1", + "VCVTSS2SI.SAE X0, AX", + "VCVTTSS2SI.RN_SAE X0, AX", + "VCVTSD2SI.RD_SAE 8(BX), AX", + "VCVTTSD2SI.SAE 8(BX), AX", + "VCVTSS2USIL X0, X1", + "VCVTSS2USIL.Z X0, AX", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86ScalarFloatToIntegerRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "CVTSS2SQ X0, AX", + "CVTTSD2SQ 8(BX), AX", + "VCVTSS2SIQ X0, AX", + "VCVTTSD2SIQ.SAE X16, AX", + "VCVTSS2USIQ X16, AX", + "VCVTTSD2USIQ.SAE X16, AX", + "CVTSS2SL X8, AX", + } { + t.Run("386_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86ScalarFloatToIntegerRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86ScalarFloatToIntegerRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scalar float-to-integer tables for %s", instruction, goarch) + } +} diff --git a/amd64_lower_scalar_integer_float.go b/amd64_lower_scalar_integer_float.go new file mode 100644 index 00000000..ef9fdd36 --- /dev/null +++ b/amd64_lower_scalar_integer_float.go @@ -0,0 +1,237 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64ScalarIntegerFloatSpec struct { + sourceBits int + resultBits int + unsigned bool + rounding bool +} + +// This is the complete Go 1.27 scalar integer-to-floating-point family from +// _yvcvtsi2sdl and _yvcvtusi2sdl. It is also the source of truth used by the +// supported-opcode extractor. +var amd64ScalarIntegerFloatOps = map[string]amd64ScalarIntegerFloatSpec{ + "VCVTSI2SDL": {sourceBits: 32, resultBits: 64}, + "VCVTSI2SDQ": {sourceBits: 64, resultBits: 64, rounding: true}, + "VCVTSI2SSL": {sourceBits: 32, resultBits: 32, rounding: true}, + "VCVTSI2SSQ": {sourceBits: 64, resultBits: 32, rounding: true}, + "VCVTUSI2SDL": {sourceBits: 32, resultBits: 64, unsigned: true}, + "VCVTUSI2SDQ": {sourceBits: 64, resultBits: 64, unsigned: true, rounding: true}, + "VCVTUSI2SSL": {sourceBits: 32, resultBits: 32, unsigned: true, rounding: true}, + "VCVTUSI2SSQ": {sourceBits: 64, resultBits: 32, unsigned: true, rounding: true}, +} + +func (c *amd64Ctx) lowerScalarIntegerToFloat(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64ScalarIntegerFloatOps[baseOp] + if !recognized { + return false, false, nil + } + rounding := "" + switch suffix { + case "": + case "RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE": + if !spec.rounding { + return true, false, fmt.Errorf("%s %s does not enable explicit rounding: %q", c.goarch, baseOp, ins.Raw) + } + rounding = suffix + default: + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's scalar integer-to-float tables: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects integer source, X passthrough, X destination: %q", c.goarch, baseOp, ins.Raw) + } + source, passthrough, destination := ins.Args[0], ins.Args[1], ins.Args[2] + if source.Kind == OpReg { + if !c.isGoYrlRegister(source) { + return true, false, fmt.Errorf("%s %s integer source is outside Go 1.27's GP-register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s integer source must be a GP register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if rounding != "" && source.Kind != OpReg { + return true, false, fmt.Errorf("%s %s explicit rounding requires a GP-register source: %q", c.goarch, baseOp, ins.Raw) + } + if !c.isGoEVEXVectorRegister(passthrough, 16) || !c.isGoEVEXVectorRegister(destination, 16) { + return true, false, fmt.Errorf("%s %s passthrough and destination must be Go 1.27 X registers: %q", c.goarch, baseOp, ins.Raw) + } + + integerType := amd64IntegerTypeForBits(spec.sourceBits) + integer, err := c.evalIntSized(source, integerType) + if err != nil { + return true, false, err + } + floatType := LLVMType("float") + if spec.resultBits == 64 { + floatType = LLVMType("double") + } + conversion := "sitofp" + if spec.unsigned { + conversion = "uitofp" + } + var low string + if rounding == "" { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", converted, conversion, integerType, integer, floatType) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to i%d\n", bits, floatType, converted, spec.resultBits) + low = "%" + bits + } else { + low = c.emitRoundedScalarIntegerToFloatBits(integer, spec, rounding) + } + passthroughBytes, err := c.loadX(passthrough.Reg) + if err != nil { + return true, false, err + } + base := c.bitcastVectorBytesToIntegerLanes(16, 128/spec.resultBits, spec.resultBits, passthroughBytes) + return true, false, c.storeVectorScalarRegister(destination.Reg, spec.resultBits, low, base, "", false) +} + +// emitRoundedScalarIntegerToFloatBits converts through an explicit integer +// significand so embedded rounding remains correct even when LLVM 22 lowers a +// constrained conversion to an instruction controlled by the ambient MXCSR. +func (c *amd64Ctx) emitRoundedScalarIntegerToFloatBits(integer string, spec amd64ScalarIntegerFloatSpec, rounding string) string { + integerType := amd64IntegerTypeForBits(spec.sourceBits) + precision := 24 + bias := 127 + if spec.resultBits == 64 { + precision = 53 + bias = 1023 + } + + negative := "false" + magnitude := integer + if !spec.unsigned { + isNegative := c.newTmp() + negated := c.newTmp() + absolute := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt %s %s, 0\n", isNegative, integerType, integer) + fmt.Fprintf(c.b, " %%%s = sub %s 0, %s\n", negated, integerType, integer) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s %s\n", absolute, isNegative, integerType, negated, integerType, integer) + negative = "%" + isNegative + magnitude = "%" + absolute + } + + isZero := c.newTmp() + safeMagnitude := c.newTmp() + leadingZeros := c.newTmp() + msb := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, 0\n", isZero, integerType, magnitude) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s 1, %s %s\n", safeMagnitude, isZero, integerType, integerType, magnitude) + fmt.Fprintf(c.b, " %%%s = call %s @llvm.ctlz.i%d(%s %%%s, i1 false)\n", leadingZeros, integerType, spec.sourceBits, integerType, safeMagnitude) + fmt.Fprintf(c.b, " %%%s = sub %s %d, %%%s\n", msb, integerType, spec.sourceBits-1, leadingZeros) + + needsRightShift := c.newTmp() + rawRightShift := c.newTmp() + rightShift := c.newTmp() + rawLeftShift := c.newTmp() + leftShift := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp uge %s %%%s, %d\n", needsRightShift, integerType, msb, precision-1) + fmt.Fprintf(c.b, " %%%s = sub %s %%%s, %d\n", rawRightShift, integerType, msb, precision-1) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s 0\n", rightShift, needsRightShift, integerType, rawRightShift, integerType) + fmt.Fprintf(c.b, " %%%s = sub %s %d, %%%s\n", rawLeftShift, integerType, precision-1, msb) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s 0, %s %%%s\n", leftShift, needsRightShift, integerType, integerType, rawLeftShift) + + shiftedRight := c.newTmp() + shiftedLeft := c.newTmp() + significand := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %%%s\n", shiftedRight, integerType, magnitude, rightShift) + fmt.Fprintf(c.b, " %%%s = shl %s %s, %%%s\n", shiftedLeft, integerType, magnitude, leftShift) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s %%%s\n", significand, needsRightShift, integerType, shiftedRight, integerType, shiftedLeft) + + oneAtShift := c.newTmp() + remainderMask := c.newTmp() + remainder := c.newTmp() + inexact := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl %s 1, %%%s\n", oneAtShift, integerType, rightShift) + fmt.Fprintf(c.b, " %%%s = sub %s %%%s, 1\n", remainderMask, integerType, oneAtShift) + fmt.Fprintf(c.b, " %%%s = and %s %s, %%%s\n", remainder, integerType, magnitude, remainderMask) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, 0\n", inexact, integerType, remainder) + + increment := "false" + switch rounding { + case "RN_SAE": + hasShift := c.newTmp() + rawHalfShift := c.newTmp() + halfShift := c.newTmp() + half := c.newTmp() + aboveHalf := c.newTmp() + equalHalf := c.newTmp() + lowBit := c.newTmp() + odd := c.newTmp() + tieAndOdd := c.newTmp() + roundNearest := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, 0\n", hasShift, integerType, rightShift) + fmt.Fprintf(c.b, " %%%s = sub %s %%%s, 1\n", rawHalfShift, integerType, rightShift) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s 0\n", halfShift, hasShift, integerType, rawHalfShift, integerType) + fmt.Fprintf(c.b, " %%%s = shl %s 1, %%%s\n", half, integerType, halfShift) + fmt.Fprintf(c.b, " %%%s = icmp ugt %s %%%s, %%%s\n", aboveHalf, integerType, remainder, half) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, %%%s\n", equalHalf, integerType, remainder, half) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, 1\n", lowBit, integerType, significand) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, 0\n", odd, integerType, lowBit) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", tieAndOdd, equalHalf, odd) + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", roundNearest, aboveHalf, tieAndOdd) + increment = "%" + roundNearest + case "RD_SAE": + if !spec.unsigned { + roundDown := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %s, %%%s\n", roundDown, negative, inexact) + increment = "%" + roundDown + } + case "RU_SAE": + if spec.unsigned { + increment = "%" + inexact + } else { + positive := c.newTmp() + roundUp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", positive, negative) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", roundUp, positive, inexact) + increment = "%" + roundUp + } + } + + incrementInteger := c.newTmp() + roundedSignificand := c.newTmp() + overflow := c.newTmp() + normalizedOverflow := c.newTmp() + normalized := c.newTmp() + exponentIncrement := c.newTmp() + exponent := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %s to %s\n", incrementInteger, increment, integerType) + fmt.Fprintf(c.b, " %%%s = add %s %%%s, %%%s\n", roundedSignificand, integerType, significand, incrementInteger) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, %d\n", overflow, integerType, roundedSignificand, uint64(1)< +#include +extern void scalarintegerfloat(uint8_t *, const int32_t *, const int64_t *, const uint32_t *, const uint64_t *, const float *, const double *); +int main(void) { + const int32_t signed32 = -16777217; + const int64_t signed64 = -16777217; + const uint32_t unsigned32 = UINT32_MAX; + const uint64_t unsigned64 = UINT64_MAX; + const float passthrough32[4] = {200.0f, 201.0f, 202.0f, 203.0f}; + const double passthrough64[2] = {100.0, 101.0}; + union { uint8_t bytes[128]; double d64[16]; float f32[32]; } out = {0}; + scalarintegerfloat(out.bytes, &signed32, &signed64, &unsigned32, &unsigned64, passthrough32, passthrough64); + if (out.d64[0] != -16777217.0 || out.d64[1] != 101.0) return 1; + if (out.d64[2] != -16777217.0 || out.d64[3] != 101.0) return 2; + if (out.f32[8] != -16777218.0f || out.f32[9] != 201.0f || out.f32[10] != 202.0f || out.f32[11] != 203.0f) return 3; + if (out.f32[12] != -16777216.0f || out.f32[13] != 201.0f || out.f32[14] != 202.0f || out.f32[15] != 203.0f) return 4; + if (out.d64[8] != 4294967295.0 || out.d64[9] != 101.0) return 5; + if (out.d64[10] != 18446744073709549568.0 || out.d64[11] != 101.0) return 6; + if (out.f32[24] != 4294967040.0f || out.f32[25] != 201.0f || out.f32[26] != 202.0f || out.f32[27] != 203.0f) { + fprintf(stderr, "unsigned32 RD result=%a upper={%a,%a,%a}\n", out.f32[24], out.f32[25], out.f32[26], out.f32[27]); + return 7; + } + if (out.f32[28] != 18446744073709551616.0f || out.f32[29] != 201.0f || out.f32[30] != 202.0f || out.f32[31] != 203.0f) return 8; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "scalar_integer_float", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_scaled_round.go b/amd64_lower_scaled_round.go new file mode 100644 index 00000000..dfc3b3a2 --- /dev/null +++ b/amd64_lower_scaled_round.go @@ -0,0 +1,277 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64ScaledRoundMode uint8 + +const ( + amd64RoundScale amd64ScaledRoundMode = iota + amd64Reduce +) + +type amd64ScaledRoundSpec struct { + laneBits int + scalar bool + mode amd64ScaledRoundMode +} + +var amd64ScaledRoundSpecs = map[Op]amd64ScaledRoundSpec{ + "VRNDSCALEPS": {laneBits: 32}, + "VRNDSCALEPD": {laneBits: 64}, + "VRNDSCALESS": {laneBits: 32, scalar: true}, + "VRNDSCALESD": {laneBits: 64, scalar: true}, + "VREDUCEPS": {laneBits: 32, mode: amd64Reduce}, + "VREDUCEPD": {laneBits: 64, mode: amd64Reduce}, + "VREDUCESS": {laneBits: 32, scalar: true, mode: amd64Reduce}, + "VREDUCESD": {laneBits: 64, scalar: true, mode: amd64Reduce}, +} + +func (c *amd64Ctx) lowerScaledRound(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp, suffix := rawOp, "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + spec, recognized := amd64ScaledRoundSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + shape := amd64UnaryImmediateFloatingShape{laneBits: spec.laneBits, scalar: spec.scalar} + form, err := c.parseUnaryImmediateFloatingForm(baseOp, suffix, shape, ins) + if err != nil { + return true, false, err + } + mxcsr := c.loadMXCSR() + dazBits, daz := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i32 %s, 64\n", dazBits, mxcsr) + fmt.Fprintf(c.b, " %%%s = icmp ne i32 %%%s, 0\n", daz, dazBits) + roundingMode := fmt.Sprintf("%d", form.immediate&3) + if form.immediate&4 != 0 { + shifted, extracted := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i32 %s, 13\n", shifted, mxcsr) + fmt.Fprintf(c.b, " %%%s = and i32 %%%s, 3\n", extracted, shifted) + roundingMode = "%" + extracted + } + if spec.scalar { + return c.lowerScalarScaledRound(spec, form.properties, form.source, form.passthrough, form.destination, form.mask, "%"+daz, roundingMode, form.immediate) + } + return c.lowerPackedScaledRound(spec, form.properties, form.source, form.destination, form.byteWidth, form.mask, "%"+daz, roundingMode, form.immediate) +} + +func (c *amd64Ctx) lowerPackedScaledRound(spec amd64ScaledRoundSpec, properties amd64BinaryFloatingSuffix, source, destination Operand, byteWidth int, mask, daz, roundingMode string, immediate uint8) (bool, bool, error) { + lanes := byteWidth * 8 / spec.laneBits + input, err := c.loadPackedCompareLanes(source, byteWidth, spec.laneBits, properties.broadcast) + if err != nil { + return true, false, err + } + result := c.emitScaledRoundBits(lanes, spec.laneBits, input, daz, roundingMode, immediate>>4, spec.mode) + if mask != "" { + oldBytes, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) lowerScalarScaledRound(spec amd64ScaledRoundSpec, properties amd64BinaryFloatingSuffix, source, passthrough, destination Operand, mask, daz, roundingMode string, immediate uint8) (bool, bool, error) { + sourceBits, err := c.loadFloatingScalarBits(source, spec.laneBits) + if err != nil { + return true, false, err + } + input := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", input, spec.laneBits, spec.laneBits, sourceBits) + result := c.emitScaledRoundBits(1, spec.laneBits, "%"+input, daz, roundingMode, immediate>>4, spec.mode) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i%d> %s, i32 0\n", low, spec.laneBits, result) + passthroughBytes, err := c.loadX(passthrough.Reg) + if err != nil { + return true, false, err + } + base := c.bitcastVectorBytesToIntegerLanes(16, 128/spec.laneBits, spec.laneBits, passthroughBytes) + return true, false, c.storeVectorScalarRegister(destination.Reg, spec.laneBits, "%"+low, base, mask, properties.zeroing) +} + +func (c *amd64Ctx) emitScaledRoundBits(lanes, laneBits int, input, daz, roundingMode string, scale uint8, mode amd64ScaledRoundMode) string { + vectorType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + mantissaBits, bias := 23, 127 + exponentMask := uint64(0x7f800000) + mantissaMask := uint64(0x007fffff) + quietBit := uint64(0x00400000) + signBit := uint64(0x80000000) + if laneBits == 64 { + mantissaBits, bias = 52, 1023 + exponentMask = uint64(0x7ff0000000000000) + mantissaMask = uint64(0x000fffffffffffff) + quietBit = uint64(0x0008000000000000) + signBit = uint64(0x8000000000000000) + } + implicitBit := uint64(1) << mantissaBits + alreadyThreshold := bias + mantissaBits - int(scale) + regularThreshold := bias - int(scale) + stepBits := uint64(bias-int(scale)) << mantissaBits + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + bits, exponent, mantissa, sign := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", bits, vectorType, input, lane) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", exponent, laneBits, bits, exponentMask) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", mantissa, laneBits, bits, mantissaMask) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", sign, laneBits, bits, signBit) + exponentZero, exponentOnes, mantissaZero := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", exponentZero, laneBits, exponent) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, %d\n", exponentOnes, laneBits, exponent, exponentMask) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", mantissaZero, laneBits, mantissa) + mantissaNonzero, negative := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", mantissaNonzero, mantissaZero) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", negative, laneBits, sign) + isNaN, isInfinity := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isNaN, exponentOnes, mantissaNonzero) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isInfinity, exponentOnes, mantissaZero) + effectiveZeroPart, effectiveZero := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %s\n", effectiveZeroPart, mantissaZero, daz) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", effectiveZero, exponentZero, effectiveZeroPart) + + exponentField := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i%d %%%s, %d\n", exponentField, laneBits, exponent, mantissaBits) + already, regularLower, regularUpper, regular := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp uge i%d %%%s, %d\n", already, laneBits, exponentField, alreadyThreshold) + fmt.Fprintf(c.b, " %%%s = icmp uge i%d %%%s, %d\n", regularLower, laneBits, exponentField, regularThreshold) + fmt.Fprintf(c.b, " %%%s = icmp ult i%d %%%s, %d\n", regularUpper, laneBits, exponentField, alreadyThreshold) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", regular, regularLower, regularUpper) + half := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, %d\n", half, laneBits, exponentField, regularThreshold-1) + + safeExponent, drop := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %d\n", safeExponent, regular, laneBits, exponentField, laneBits, alreadyThreshold-1) + fmt.Fprintf(c.b, " %%%s = sub i%d %d, %%%s\n", drop, laneBits, mantissaBits+bias-int(scale), safeExponent) + significand := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %d\n", significand, laneBits, mantissa, implicitBit) + quotient, oneAtDrop, remainderMask, remainder := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i%d %%%s, %%%s\n", quotient, laneBits, significand, drop) + fmt.Fprintf(c.b, " %%%s = shl i%d 1, %%%s\n", oneAtDrop, laneBits, drop) + fmt.Fprintf(c.b, " %%%s = sub i%d %%%s, 1\n", remainderMask, laneBits, oneAtDrop) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %%%s\n", remainder, laneBits, significand, remainderMask) + halfRemainder, aboveHalf, equalHalf := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i%d %%%s, 1\n", halfRemainder, laneBits, oneAtDrop) + fmt.Fprintf(c.b, " %%%s = icmp ugt i%d %%%s, %%%s\n", aboveHalf, laneBits, remainder, halfRemainder) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, %%%s\n", equalHalf, laneBits, remainder, halfRemainder) + quotientOddValue, quotientOdd, tiedOdd := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, 1\n", quotientOddValue, laneBits, quotient) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", quotientOdd, laneBits, quotientOddValue) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", tiedOdd, equalHalf, quotientOdd) + nearestRegular := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", nearestRegular, aboveHalf, tiedOdd) + remainderNonzero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", remainderNonzero, laneBits, remainder) + incrementRegular := c.emitScaledRoundIncrement(roundingMode, "%"+negative, "%"+remainderNonzero, "%"+nearestRegular) + incrementValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %s to i%d\n", incrementValue, incrementRegular, laneBits) + roundedQuotient, roundedSignificand := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i%d %%%s, %%%s\n", roundedQuotient, laneBits, quotient, incrementValue) + fmt.Fprintf(c.b, " %%%s = shl i%d %%%s, %%%s\n", roundedSignificand, laneBits, roundedQuotient, drop) + carryValue, carry, carryInteger := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", carryValue, laneBits, roundedSignificand, implicitBit<<1) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", carry, laneBits, carryValue) + fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to i%d\n", carryInteger, carry, laneBits) + roundedExponentField, roundedExponent := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i%d %%%s, %%%s\n", roundedExponentField, laneBits, exponentField, carryInteger) + fmt.Fprintf(c.b, " %%%s = shl i%d %%%s, %d\n", roundedExponent, laneBits, roundedExponentField, mantissaBits) + roundedFraction, roundedMagnitude, roundedRegular := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", roundedFraction, laneBits, roundedSignificand, mantissaMask) + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %%%s\n", roundedMagnitude, laneBits, roundedExponent, roundedFraction) + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %%%s\n", roundedRegular, laneBits, roundedMagnitude, sign) + + halfAbove := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ugt i%d %%%s, %d\n", halfAbove, laneBits, significand, implicitBit) + nonzero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", nonzero, effectiveZero) + incrementHalf := c.emitScaledRoundIncrement(roundingMode, "%"+negative, "%"+nonzero, "%"+halfAbove) + incrementSmall := c.emitScaledRoundIncrement(roundingMode, "%"+negative, "%"+nonzero, "false") + incrementNonRegular := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i1 %s, i1 %s\n", incrementNonRegular, half, incrementHalf, incrementSmall) + signedStep, stepOrZero := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %d\n", signedStep, laneBits, sign, stepBits) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", stepOrZero, incrementNonRegular, laneBits, signedStep, laneBits, sign) + roundedNeeded, roundedFinite, zeroAdjusted := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", roundedNeeded, regular, laneBits, roundedRegular, laneBits, stepOrZero) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", roundedFinite, already, laneBits, bits, laneBits, roundedNeeded) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", zeroAdjusted, effectiveZero, laneBits, sign, laneBits, roundedFinite) + withInfinity := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", withInfinity, isInfinity, laneBits, bits, laneBits, zeroAdjusted) + quietNaN := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %d\n", quietNaN, laneBits, bits, quietBit) + roundedFinal := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", roundedFinal, isNaN, laneBits, quietNaN, laneBits, withInfinity) + laneResult := "%" + roundedFinal + if mode == amd64Reduce { + effectiveSource := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", effectiveSource, effectiveZero, laneBits, sign, laneBits, bits) + laneResult = c.emitReduceResult(laneBits, "%"+effectiveSource, "%"+zeroAdjusted, "%"+isNaN, "%"+isInfinity, roundingMode, quietBit, signBit) + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %s, i32 %d\n", inserted, vectorType, result, laneBits, laneResult, lane) + result = "%" + inserted + } + return result +} + +func (c *amd64Ctx) emitScaledRoundIncrement(roundingMode, negative, nonzero, nearest string) string { + isNearest, isDown, isUp := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 0\n", isNearest, roundingMode) + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 1\n", isDown, roundingMode) + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 2\n", isUp, roundingMode) + nearestIncrement, downIncrement := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %s\n", nearestIncrement, isNearest, nearest) + fmt.Fprintf(c.b, " %%%s = and i1 %s, %s\n", downIncrement, negative, nonzero) + downSelected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", downSelected, isDown, downIncrement) + nonnegative, upIncrement, upSelected := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", nonnegative, negative) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %s\n", upIncrement, nonnegative, nonzero) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", upSelected, isUp, upIncrement) + combined, result := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", combined, nearestIncrement, downSelected) + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", result, combined, upSelected) + return "%" + result +} + +func (c *amd64Ctx) emitReduceResult(laneBits int, sourceBits, finiteRoundedBits, isNaN, isInfinity, roundingMode string, quietBit, signBit uint64) string { + floatType := "float" + if laneBits == 64 { + floatType = "double" + } + special := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %s, %s\n", special, isNaN, isInfinity) + safeSourceBits, safeRoundedBits := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d 0, i%d %s\n", safeSourceBits, special, laneBits, laneBits, sourceBits) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d 0, i%d %s\n", safeRoundedBits, special, laneBits, laneBits, finiteRoundedBits) + sourceFloat, roundedFloat := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i%d %%%s to %s\n", sourceFloat, laneBits, safeSourceBits, floatType) + fmt.Fprintf(c.b, " %%%s = bitcast i%d %%%s to %s\n", roundedFloat, laneBits, safeRoundedBits, floatType) + reducedFloat, reducedBits := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = fsub %s %%%s, %%%s\n", reducedFloat, floatType, sourceFloat, roundedFloat) + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to i%d\n", reducedBits, floatType, reducedFloat, laneBits) + reducedMagnitude, reducedZero := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", reducedMagnitude, laneBits, reducedBits, signBit-1) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", reducedZero, laneBits, reducedMagnitude) + isDown := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 1\n", isDown, roundingMode) + zeroBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %d, i%d 0\n", zeroBits, isDown, laneBits, signBit, laneBits) + zeroAdjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", zeroAdjusted, reducedZero, laneBits, zeroBits, laneBits, reducedBits) + withInfinity := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d 0, i%d %%%s\n", withInfinity, isInfinity, laneBits, laneBits, zeroAdjusted) + quietNaNBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %s, %d\n", quietNaNBits, laneBits, sourceBits, quietBit) + final := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %%%s\n", final, isNaN, laneBits, quietNaNBits, laneBits, withInfinity) + return "%" + final +} diff --git a/amd64_lower_scaled_round_test.go b/amd64_lower_scaled_round_test.go new file mode 100644 index 00000000..c315d268 --- /dev/null +++ b/amd64_lower_scaled_round_test.go @@ -0,0 +1,305 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateAMD64ScaledRoundRepresentativeForms(t *testing.T) { + const source = `TEXT scaledroundforms(SB),$0-0 + VREDUCEPS $3, Z1, K2, Z3 + VRNDSCALESD $20, X4, X5, K6, X7 + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"scaledroundforms": {Name: "scaledroundforms", Ret: Void}}, + }); err != nil { + t.Fatal(err) + } +} + +func TestAMD64ScaledRoundGrammarCoversCompleteGoFamilies(t *testing.T) { + expected := map[Op]amd64ScaledRoundSpec{ + "VRNDSCALEPS": {laneBits: 32}, + "VRNDSCALEPD": {laneBits: 64}, + "VRNDSCALESS": {laneBits: 32, scalar: true}, + "VRNDSCALESD": {laneBits: 64, scalar: true}, + "VREDUCEPS": {laneBits: 32, mode: amd64Reduce}, + "VREDUCEPD": {laneBits: 64, mode: amd64Reduce}, + "VREDUCESS": {laneBits: 32, scalar: true, mode: amd64Reduce}, + "VREDUCESD": {laneBits: 64, scalar: true, mode: amd64Reduce}, + } + if len(amd64ScaledRoundSpecs) != len(expected) { + t.Fatalf("scaled-round grammar has %d entries, want %d", len(amd64ScaledRoundSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64ScaledRoundSpecs[op]; !ok { + t.Errorf("scaled-round grammar omitted %s", op) + } else if got != want { + t.Errorf("scaled-round grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86ScaledRoundCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT scaledroundallforms(SB),$0-0\n") + for _, op := range []string{"VRNDSCALEPS", "VRNDSCALEPD", "VREDUCEPS", "VREDUCEPD"} { + for _, width := range []string{"X", "Y", "Z"} { + last := 31 + if target.goarch == "386" && width == "Z" { + last = 7 + } + fmt.Fprintf(&source, "\t%s $0, %s1, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s $255, 8(AX), %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST $1, 16(AX), %s%d\n", op, width, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s $2, %s1, K1, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s.Z $3, 24(AX), K2, %s%d\n", op, width, last) + fmt.Fprintf(&source, "\t%s.BCST.Z $4, 32(AX), K3, %s%d\n", op, width, last) + } + if width == "Z" { + fmt.Fprintf(&source, "\t%s.SAE $5, Z1, Z%d\n", op, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.SAE.Z $6, Z1, K4, Z%d\n", op, last) + } + } + } + } + if target.goarch == "amd64" { + for _, op := range []string{"VRNDSCALESS", "VRNDSCALESD", "VREDUCESS", "VREDUCESD"} { + fmt.Fprintf(&source, "\t%s $0, X1, X2, X31\n", op) + fmt.Fprintf(&source, "\t%s $255, 40(AX), X2, X31\n", op) + fmt.Fprintf(&source, "\t%s.SAE $1, X1, X2, X31\n", op) + fmt.Fprintf(&source, "\t%s $2, X1, X2, K5, X31\n", op) + fmt.Fprintf(&source, "\t%s.Z $3, 48(AX), X2, K6, X31\n", op) + fmt.Fprintf(&source, "\t%s.SAE.Z $4, X1, X2, K7, X31\n", op) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"scaledroundallforms": {Name: "scaledroundallforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "scaled-round-"+target.name+".ll", "scaled-round-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86ScaledRoundRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VREDUCEPS $-1, X0, X1"}, + {goarch: "amd64", instruction: "VRNDSCALEPD $256, X0, X1"}, + {goarch: "amd64", instruction: "VREDUCEPS X0, X1"}, + {goarch: "amd64", instruction: "VRNDSCALEPS $0, X0, Y1"}, + {goarch: "amd64", instruction: "VREDUCEPS.BCST $0, X0, X1"}, + {goarch: "amd64", instruction: "VRNDSCALEPS.SAE $0, Z0, X1"}, + {goarch: "amd64", instruction: "VREDUCEPD.SAE $0, 0(AX), Z1"}, + {goarch: "amd64", instruction: "VRNDSCALEPS.RN_SAE $0, Z0, Z1"}, + {goarch: "amd64", instruction: "VREDUCEPS.Z $0, X0, X1"}, + {goarch: "amd64", instruction: "VRNDSCALEPS $0, X0, K0, X1"}, + {goarch: "amd64", instruction: "VREDUCESS $0, Y0, X1, X2"}, + {goarch: "amd64", instruction: "VRNDSCALESD.BCST $0, 0(AX), X1, X2"}, + {goarch: "amd64", instruction: "VREDUCESD $0, X0, X1, Y2"}, + {goarch: "386", instruction: "VRNDSCALESS $0, X0, X1, X2"}, + {goarch: "386", instruction: "VREDUCEPS $0, X0, K1, X2"}, + {goarch: "386", instruction: "VRNDSCALEPS $0, Z8, Z0"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scaled-round tables", test.instruction) + } + }) + } +} + +func TestAMD64ScaledRoundRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + var source strings.Builder + source.WriteString(`TEXT scaledroundsemantics(SB),$0-56 + MOVQ out+0(FP), AX + MOVQ source32+8(FP), BX + MOVQ source64+16(FP), CX + MOVQ old32+24(FP), DX + MOVQ old64+32(FP), R8 + MOVQ upper+40(FP), R9 + MOVQ mask+48(FP), R10 + KMOVQ R10, K1 + VMOVDQU64 0(R9), X4 + STC +`) + for scale := 0; scale < 16; scale++ { + for rounding := 0; rounding < 4; rounding++ { + index := scale*4 + rounding + immediate := scale<<4 | rounding + fmt.Fprintf(&source, "\tVRNDSCALESS $%d, %d(BX), X4, X5\n", immediate, index%16*4) + fmt.Fprintf(&source, "\tVMOVSS X5, %d(AX)\n", index*4) + fmt.Fprintf(&source, "\tVREDUCESS $%d, %d(BX), X4, X5\n", immediate, index%16*4) + fmt.Fprintf(&source, "\tVMOVSS X5, %d(AX)\n", 256+index*4) + fmt.Fprintf(&source, "\tVRNDSCALESD $%d, %d(CX), X4, X5\n", immediate, index%16*8) + fmt.Fprintf(&source, "\tVMOVSD X5, %d(AX)\n", 512+index*8) + fmt.Fprintf(&source, "\tVREDUCESD $%d, %d(CX), X4, X5\n", immediate, index%16*8) + fmt.Fprintf(&source, "\tVMOVSD X5, %d(AX)\n", 1024+index*8) + } + } + source.WriteString(` VMOVDQU32 0(DX), Z2 + VRNDSCALEPS $35, 0(BX), K1, Z2 + VMOVDQU32 Z2, 1536(AX) + VREDUCEPS.Z $35, 0(BX), K1, Z2 + VMOVDQU32 Z2, 1600(AX) + VRNDSCALEPS.BCST $35, 0(BX), Z2 + VMOVDQU32 Z2, 1664(AX) + VMOVDQU64 0(R8), Z3 + VRNDSCALEPD $35, 0(CX), K1, Z3 + VMOVDQU64 Z3, 1728(AX) + VREDUCEPD.Z $35, 0(CX), K1, Z3 + VMOVDQU64 Z3, 1792(AX) + VRNDSCALEPD.BCST $35, 0(CX), Z3 + VMOVDQU64 Z3, 1856(AX) + VRNDSCALESS $0, 0(BX), X4, X5 + VMOVDQU64 X5, 1920(AX) + VREDUCESD $0, 0(CX), X4, X6 + VMOVDQU64 X6, 1936(AX) + VRNDSCALESS $36, 0(BX), X4, X5 + VMOVSS X5, 1952(AX) + VREDUCESS $36, 8(BX), X4, X5 + VMOVSS X5, 1956(AX) + VRNDSCALESD $36, 0(CX), X4, X5 + VMOVSD X5, 1960(AX) + VREDUCESD $36, 16(CX), X4, X5 + VMOVSD X5, 1968(AX) + SETCS 1976(AX) + RET +`) + requireX86GoAssemblerResult(t, "amd64", source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"scaledroundsemantics": { + Name: "scaledroundsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + {Offset: 48, Type: I64, Index: 6, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +#include +extern void scaledroundsemantics(uint8_t *, const uint32_t *, const uint64_t *, const uint32_t *, const uint64_t *, const uint64_t *, uint64_t); +static int inc(unsigned rc,int neg,int nonzero,int nearest) { return rc==0?nearest:(rc==1?neg&&nonzero:(rc==2?!neg&&nonzero:0)); } +static uint32_t round32(uint32_t u,unsigned scale,unsigned rc,int daz) { + const uint32_t em=0x7f800000,fm=0x007fffff,qb=0x00400000,sb=0x80000000,ib=0x00800000; + uint32_t e=(u&em)>>23,f=u&fm,s=u&sb; if(e==255) return f?(u|qb):u; + if(e==0&&(f==0||daz)) return s; + unsigned already=127+23-scale, regular=127-scale; + if(e>=already) return u; + uint32_t sig=f|ib; + if(e>=regular) { unsigned drop=23+127-scale-e; uint32_t q=sig>>drop, rem=sig&((UINT32_C(1)<half||(rem==half&&(q&1)); q+=(uint32_t)inc(rc,s!=0,rem!=0,n); uint32_t rs=q<ib; return s|(inc(rc,s!=0,1,n)?((127-scale)<<23):0); +} +static uint64_t round64(uint64_t u,unsigned scale,unsigned rc,int daz) { + const uint64_t em=UINT64_C(0x7ff0000000000000),fm=UINT64_C(0x000fffffffffffff),qb=UINT64_C(0x0008000000000000),sb=UINT64_C(0x8000000000000000),ib=UINT64_C(0x0010000000000000); + uint64_t e=(u&em)>>52,f=u&fm,s=u&sb; if(e==2047) return f?(u|qb):u; + if(e==0&&(f==0||daz)) return s; + unsigned already=1023+52-scale, regular=1023-scale; + if(e>=already) return u; + uint64_t sig=f|ib; + if(e>=regular) { unsigned drop=52+1023-scale-(unsigned)e; uint64_t q=sig>>drop, rem=sig&((UINT64_C(1)<half||(rem==half&&(q&1)); q+=(uint64_t)inc(rc,s!=0,rem!=0,n); uint64_t rs=q<ib; return s|(inc(rc,s!=0,1,n)?((uint64_t)(1023-scale)<<52):0); +} +static uint32_t reduce32(uint32_t u,unsigned scale,unsigned rc,int daz) { uint32_t e=u&0x7f800000,f=u&0x007fffff,s=u&0x80000000; if(e==0x7f800000) return f?(u|0x00400000):0; uint32_t effective=(e==0&&(f==0||daz))?s:u, rounded=round32(u,scale,rc,daz), r; float a,b,c; memcpy(&a,&effective,4); memcpy(&b,&rounded,4); c=a-b; memcpy(&r,&c,4); return (r&0x7fffffff)?r:(rc==1?0x80000000:0); } +static uint64_t reduce64(uint64_t u,unsigned scale,unsigned rc,int daz) { uint64_t e=u&UINT64_C(0x7ff0000000000000),f=u&UINT64_C(0x000fffffffffffff),s=u&UINT64_C(0x8000000000000000); if(e==UINT64_C(0x7ff0000000000000)) return f?(u|UINT64_C(0x0008000000000000)):0; uint64_t effective=(e==0&&(f==0||daz))?s:u, rounded=round64(u,scale,rc,daz), r; double a,b,c; memcpy(&a,&effective,8); memcpy(&b,&rounded,8); c=a-b; memcpy(&r,&c,8); return (r&UINT64_C(0x7fffffffffffffff))?r:(rc==1?UINT64_C(0x8000000000000000):0); } +static uint32_t u32(const uint8_t *p) { uint32_t v; memcpy(&v,p,4); return v; } +static uint64_t u64(const uint8_t *p) { uint64_t v; memcpy(&v,p,8); return v; } +int main(void) { + const uint32_t s32[16]={0x3fc00000,0x40200000,0xbfc00000,0xc0200000,0x3fb00000,0xbfb00000,0,0x80000000,0x7f800000,0xff800000,0x7fc12345,0xff812345,1,0x80000001,0x4e800000,0x3f800001}; + const uint64_t s64[16]={UINT64_C(0x3ff8000000000000),UINT64_C(0x4004000000000000),UINT64_C(0xbff8000000000000),UINT64_C(0xc004000000000000),UINT64_C(0x3ff6000000000000),UINT64_C(0xbff6000000000000),0,UINT64_C(0x8000000000000000),UINT64_C(0x7ff0000000000000),UINT64_C(0xfff0000000000000),UINT64_C(0x7ff8123456789abc),UINT64_C(0xfff0123456789abc),1,UINT64_C(0x8000000000000001),UINT64_C(0x41d0000000000000),UINT64_C(0x3ff0000000000001)}; + uint32_t old32[16]; uint64_t old64[8]; const uint64_t upper[2]={UINT64_C(0x1122334455667788),UINT64_C(0x99aabbccddeeff00)}; const uint64_t mask=UINT64_C(0xa55a); + uint8_t out[1977]={0},outDaz[1977]={0},dynamic[4][1977]; for(int i=0;i<16;i++)old32[i]=UINT32_C(0x41000000)+i; for(int i=0;i<8;i++)old64[i]=UINT64_C(0x4020000000000000)+i; + unsigned csr=_mm_getcsr(); scaledroundsemantics(out,s32,s64,old32,old64,upper,mask); _mm_setcsr(csr|0x40); scaledroundsemantics(outDaz,s32,s64,old32,old64,upper,mask); _mm_setcsr(csr); + for(unsigned rc=0;rc<4;rc++){_mm_setcsr((csr&~(3u<<13))|(rc<<13));scaledroundsemantics(dynamic[rc],s32,s64,old32,old64,upper,mask);} _mm_setcsr(csr); + for(unsigned scale=0;scale<16;scale++)for(unsigned rc=0;rc<4;rc++){unsigned i=scale*4+rc,j=i&15;if(u32(out+i*4)!=round32(s32[j],scale,rc,0)||u32(out+256+i*4)!=reduce32(s32[j],scale,rc,0))return 10;if(u64(out+512+i*8)!=round64(s64[j],scale,rc,0)||u64(out+1024+i*8)!=reduce64(s64[j],scale,rc,0))return 11;if(u32(outDaz+i*4)!=round32(s32[j],scale,rc,1)||u32(outDaz+256+i*4)!=reduce32(s32[j],scale,rc,1))return 12;if(u64(outDaz+512+i*8)!=round64(s64[j],scale,rc,1)||u64(outDaz+1024+i*8)!=reduce64(s64[j],scale,rc,1))return 13;} + for(int i=0;i<16;i++){uint32_t r=round32(s32[i],2,3,0),d=reduce32(s32[i],2,3,0);if(u32(out+1536+i*4)!=(((mask>>i)&1)?r:old32[i]))return 20;if(u32(out+1600+i*4)!=(((mask>>i)&1)?d:0))return 21;if(u32(out+1664+i*4)!=round32(s32[0],2,3,0))return 22;} + for(int i=0;i<8;i++){uint64_t r=round64(s64[i],2,3,0),d=reduce64(s64[i],2,3,0);if(u64(out+1728+i*8)!=(((mask>>i)&1)?r:old64[i]))return 23;if(u64(out+1792+i*8)!=(((mask>>i)&1)?d:0))return 24;if(u64(out+1856+i*8)!=round64(s64[0],2,3,0))return 25;} + if(u32(out+1920)!=round32(s32[0],0,0,0)||memcmp(out+1924,(const uint8_t*)upper+4,12))return 30;if(u64(out+1936)!=reduce64(s64[0],0,0,0)||memcmp(out+1944,(const uint8_t*)upper+8,8))return 31;if(out[1976]!=1)return 32; + for(unsigned rc=0;rc<4;rc++){if(u32(dynamic[rc]+1952)!=round32(s32[0],2,rc,0)||u32(dynamic[rc]+1956)!=reduce32(s32[2],2,rc,0)||u64(dynamic[rc]+1960)!=round64(s64[0],2,rc,0)||u64(dynamic[rc]+1968)!=reduce64(s64[2],2,rc,0))return 40+rc;} + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "scaled_round_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_scalef.go b/amd64_lower_scalef.go new file mode 100644 index 00000000..b9637367 --- /dev/null +++ b/amd64_lower_scalef.go @@ -0,0 +1,383 @@ +package plan9asm + +import "fmt" + +type amd64ScaleFControls struct { + daz string + ftz string + rounding string +} + +func (c *amd64Ctx) scaleFControls(rounding string) amd64ScaleFControls { + mxcsr := c.loadMXCSR() + dazBits, daz := c.newTmp(), c.newTmp() + ftzBits, ftz := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i32 %s, 64\n", dazBits, mxcsr) + fmt.Fprintf(c.b, " %%%s = icmp ne i32 %%%s, 0\n", daz, dazBits) + fmt.Fprintf(c.b, " %%%s = and i32 %s, 32768\n", ftzBits, mxcsr) + fmt.Fprintf(c.b, " %%%s = icmp ne i32 %%%s, 0\n", ftz, ftzBits) + mode := "" + switch rounding { + case "RN_SAE": + mode = "0" + case "RD_SAE": + mode = "1" + case "RU_SAE": + mode = "2" + case "RZ_SAE": + mode = "3" + default: + shifted, extracted := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i32 %s, 13\n", shifted, mxcsr) + fmt.Fprintf(c.b, " %%%s = and i32 %%%s, 3\n", extracted, shifted) + mode = "%" + extracted + } + return amd64ScaleFControls{daz: "%" + daz, ftz: "%" + ftz, rounding: mode} +} + +func (c *amd64Ctx) lowerPackedScaleF(spec amd64BinaryFloatingSpec, properties amd64BinaryFloatingSuffix, source2, source1, destination Operand, byteWidth int, mask string) (bool, bool, error) { + lanes := byteWidth * 8 / spec.laneBits + scale, err := c.loadPackedCompareLanes(source2, byteWidth, spec.laneBits, properties.broadcast) + if err != nil { + return true, false, err + } + value, err := c.loadPackedCompareLanes(source1, byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + result := c.emitScaleFBits(lanes, spec.laneBits, value, scale, c.scaleFControls(properties.rounding)) + if mask != "" { + oldBytes, loadErr := c.loadPackedCompareBytes(destination, byteWidth) + if loadErr != nil { + return true, false, loadErr + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, properties.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) lowerScalarScaleF(spec amd64BinaryFloatingSpec, properties amd64BinaryFloatingSuffix, source2, source1, destination Operand, mask string) (bool, bool, error) { + scaleBits, err := c.loadFloatingScalarBits(source2, spec.laneBits) + if err != nil { + return true, false, err + } + valueBits, err := c.loadFloatingScalarBits(source1, spec.laneBits) + if err != nil { + return true, false, err + } + scale, value := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", scale, spec.laneBits, spec.laneBits, scaleBits) + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", value, spec.laneBits, spec.laneBits, valueBits) + result := c.emitScaleFBits(1, spec.laneBits, "%"+value, "%"+scale, c.scaleFControls(properties.rounding)) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i%d> %s, i32 0\n", low, spec.laneBits, result) + passthroughBytes, err := c.loadX(source1.Reg) + if err != nil { + return true, false, err + } + base := c.bitcastVectorBytesToIntegerLanes(16, 128/spec.laneBits, spec.laneBits, passthroughBytes) + return true, false, c.storeVectorScalarRegister(destination.Reg, spec.laneBits, "%"+low, base, mask, properties.zeroing) +} + +func (c *amd64Ctx) emitScaleFBits(lanes, laneBits int, source1, source2 string, controls amd64ScaleFControls) string { + vectorType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + mantissaBits, bias, exponentMax, scaleClamp := 23, 127, 255, 512 + exponentMask := uint64(0x7f800000) + mantissaMask := uint64(0x007fffff) + quietBit := uint64(0x00400000) + signBit := uint64(0x80000000) + indefinite := uint64(0xffc00000) + if laneBits == 64 { + mantissaBits, bias, exponentMax, scaleClamp = 52, 1023, 2047, 4096 + exponentMask = uint64(0x7ff0000000000000) + mantissaMask = uint64(0x000fffffffffffff) + quietBit = uint64(0x0008000000000000) + signBit = uint64(0x8000000000000000) + indefinite = uint64(0xfff8000000000000) + } + implicitBit := uint64(1) << mantissaBits + result := "zeroinitializer" + for lane := 0; lane < lanes; lane++ { + x, y := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", x, vectorType, source1, lane) + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", y, vectorType, source2, lane) + laneResult := c.emitScaleFLane(laneBits, mantissaBits, bias, exponentMax, scaleClamp, + exponentMask, mantissaMask, quietBit, signBit, indefinite, implicitBit, + "%"+x, "%"+y, controls) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %s, i32 %d\n", inserted, vectorType, result, laneBits, laneResult, lane) + result = "%" + inserted + } + return result +} + +type amd64ScaleFClass struct { + bits, sign, fraction, exponent string + zero, nan, snan, infinity string + positiveInfinity, negativeInfinity string +} + +func (c *amd64Ctx) classifyScaleFValue(laneBits, mantissaBits, exponentMax int, exponentMask, mantissaMask, quietBit, signBit uint64, bits, daz string) amd64ScaleFClass { + sign, fraction, exponentField := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %s, %d\n", sign, laneBits, bits, signBit) + fmt.Fprintf(c.b, " %%%s = and i%d %s, %d\n", fraction, laneBits, bits, mantissaMask) + fmt.Fprintf(c.b, " %%%s = and i%d %s, %d\n", exponentField, laneBits, bits, exponentMask) + exponentZero, fractionNonzero, denormal := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", exponentZero, laneBits, exponentField) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", fractionNonzero, laneBits, fraction) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", denormal, exponentZero, fractionNonzero) + flush := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %s\n", flush, denormal, daz) + effective := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %s\n", effective, flush, laneBits, sign, laneBits, bits) + + effectiveFraction, shiftedExponent, effectiveExponent := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", effectiveFraction, laneBits, effective, mantissaMask) + fmt.Fprintf(c.b, " %%%s = lshr i%d %%%s, %d\n", shiftedExponent, laneBits, effective, mantissaBits) + if laneBits == 32 { + fmt.Fprintf(c.b, " %%%s = and i32 %%%s, %d\n", effectiveExponent, shiftedExponent, exponentMax) + } else { + exponentWide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, %d\n", exponentWide, shiftedExponent, exponentMax) + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", effectiveExponent, exponentWide) + } + abs, isZero, isExponentMax, isFractionNonzero := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", abs, laneBits, effective, signBit-1) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", isZero, laneBits, abs) + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %%%s, %d\n", isExponentMax, effectiveExponent, exponentMax) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", isFractionNonzero, laneBits, effectiveFraction) + isNaN, isInfinity := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isNaN, isExponentMax, isFractionNonzero) + fractionQuiet, quietClear, isSNaN := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", fractionQuiet, laneBits, effectiveFraction, quietBit) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", quietClear, laneBits, fractionQuiet) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isSNaN, isNaN, quietClear) + fractionZero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, 0\n", fractionZero, laneBits, effectiveFraction) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isInfinity, isExponentMax, fractionZero) + isNegative, positiveInfinity, negativeInfinity := c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", isNegative, laneBits, sign) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", negativeInfinity, isInfinity, isNegative) + notNegative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", notNegative, isNegative) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", positiveInfinity, isInfinity, notNegative) + return amd64ScaleFClass{ + bits: "%" + effective, sign: "%" + sign, fraction: "%" + effectiveFraction, exponent: "%" + effectiveExponent, + zero: "%" + isZero, nan: "%" + isNaN, snan: "%" + isSNaN, infinity: "%" + isInfinity, + positiveInfinity: "%" + positiveInfinity, negativeInfinity: "%" + negativeInfinity, + } +} + +func (c *amd64Ctx) emitScaleFLane(laneBits, mantissaBits, bias, exponentMax, scaleClamp int, exponentMask, mantissaMask, quietBit, signBit, indefinite, implicitBit uint64, source1, source2 string, controls amd64ScaleFControls) string { + x := c.classifyScaleFValue(laneBits, mantissaBits, exponentMax, exponentMask, mantissaMask, quietBit, signBit, source1, controls.daz) + y := c.classifyScaleFValue(laneBits, mantissaBits, exponentMax, exponentMask, mantissaMask, quietBit, signBit, source2, controls.daz) + + yNegative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %s, 0\n", yNegative, laneBits, y.sign) + yExponentNegative, yExponentLarge := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i32 %s, %d\n", yExponentNegative, y.exponent, bias) + largeExponent := 9 + if laneBits == 64 { + largeExponent = 12 + } + fmt.Fprintf(c.b, " %%%s = icmp sge i32 %s, %d\n", yExponentLarge, y.exponent, bias+largeExponent) + yUnbiased, yShift := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 %s, %d\n", yUnbiased, y.exponent, bias) + fmt.Fprintf(c.b, " %%%s = sub i32 %d, %%%s\n", yShift, mantissaBits, yUnbiased) + yExponentOutOfRange := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", yExponentOutOfRange, yExponentNegative, yExponentLarge) + safeYShift := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %d, i32 %%%s\n", safeYShift, yExponentOutOfRange, mantissaBits, yShift) + yShiftLane := "%" + safeYShift + if laneBits == 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, safeYShift) + yShiftLane = "%" + wide + } + ySignificand := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %s, %d\n", ySignificand, laneBits, y.fraction, implicitBit) + yIntegerWide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i%d %%%s, %s\n", yIntegerWide, laneBits, ySignificand, yShiftLane) + yInteger := "%" + yIntegerWide + if laneBits == 64 { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", narrow, yIntegerWide) + yInteger = "%" + narrow + } + oneShifted, remainderMask, remainder, remainderNonzero := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i%d 1, %s\n", oneShifted, laneBits, yShiftLane) + fmt.Fprintf(c.b, " %%%s = sub i%d %%%s, 1\n", remainderMask, laneBits, oneShifted) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %%%s\n", remainder, laneBits, ySignificand, remainderMask) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", remainderNonzero, laneBits, remainder) + negativeInteger, negativeFloor := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 0, %s\n", negativeInteger, yInteger) + remainderAdjust := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to i32\n", remainderAdjust, remainderNonzero) + fmt.Fprintf(c.b, " %%%s = sub i32 %%%s, %%%s\n", negativeFloor, negativeInteger, remainderAdjust) + signedInteger := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %%%s, i32 %s\n", signedInteger, yNegative, negativeFloor, yInteger) + smallScale := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 -1, i32 0\n", smallScale, yNegative) + clampedScale := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 -%d, i32 %d\n", clampedScale, yNegative, scaleClamp, scaleClamp) + nonzeroScale := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %%%s, i32 %%%s\n", nonzeroScale, yExponentLarge, clampedScale, signedInteger) + finiteScale := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %%%s, i32 %%%s\n", finiteScale, yExponentNegative, smallScale, nonzeroScale) + scale := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i32 0, i32 %%%s\n", scale, y.zero, finiteScale) + + xExponentZero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 0\n", xExponentZero, x.exponent) + xSignificandNormal := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %s, %d\n", xSignificandNormal, laneBits, x.fraction, implicitBit) + xSignificand := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %s, i%d %%%s\n", xSignificand, xExponentZero, laneBits, x.fraction, laneBits, xSignificandNormal) + leadingZeros := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i%d @llvm.ctlz.i%d(i%d %%%s, i1 false)\n", leadingZeros, laneBits, laneBits, laneBits, xSignificand) + leadingZeros32 := "%" + leadingZeros + if laneBits == 64 { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", narrow, leadingZeros) + leadingZeros32 = "%" + narrow + } + normalizeShift := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 %s, %d\n", normalizeShift, leadingZeros32, laneBits-1-mantissaBits) + normalizeShiftLane := "%" + normalizeShift + if laneBits == 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, normalizeShift) + normalizeShiftLane = "%" + wide + } + normalizedSignificand := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i%d %%%s, %s\n", normalizedSignificand, laneBits, xSignificand, normalizeShiftLane) + xBaseExponentNormal, xBaseExponent := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 %s, %d\n", xBaseExponentNormal, x.exponent, bias) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %d, i32 %%%s\n", xBaseExponent, xExponentZero, 1-bias, xBaseExponentNormal) + xNormalizedExponent := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 %%%s, %%%s\n", xNormalizedExponent, xBaseExponent, normalizeShift) + targetExponent := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %%%s, %%%s\n", targetExponent, xNormalizedExponent, scale) + + overflow, normal := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp sgt i32 %%%s, %d\n", overflow, targetExponent, bias) + fmt.Fprintf(c.b, " %%%s = icmp sge i32 %%%s, %d\n", normal, targetExponent, 1-bias) + normalExponent32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %%%s, %d\n", normalExponent32, targetExponent, bias) + normalExponent := "%" + normalExponent32 + if laneBits == 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, normalExponent32) + normalExponent = "%" + wide + } + normalExponentBits, normalFraction, normalMagnitude, normalBits := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i%d %s, %d\n", normalExponentBits, laneBits, normalExponent, mantissaBits) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %d\n", normalFraction, laneBits, normalizedSignificand, mantissaMask) + fmt.Fprintf(c.b, " %%%s = or i%d %%%s, %%%s\n", normalMagnitude, laneBits, normalExponentBits, normalFraction) + fmt.Fprintf(c.b, " %%%s = or i%d %s, %%%s\n", normalBits, laneBits, x.sign, normalMagnitude) + + subnormalShiftRaw, subnormalShiftHigh := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 %d, %%%s\n", subnormalShiftRaw, 1-bias, targetExponent) + fmt.Fprintf(c.b, " %%%s = icmp sgt i32 %%%s, %d\n", subnormalShiftHigh, subnormalShiftRaw, mantissaBits+2) + subnormalShiftMax := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %d, i32 %%%s\n", subnormalShiftMax, subnormalShiftHigh, mantissaBits+2, subnormalShiftRaw) + subnormalShiftLow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i32 %%%s, 1\n", subnormalShiftLow, subnormalShiftMax) + subnormalShift := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 1, i32 %%%s\n", subnormalShift, subnormalShiftLow, subnormalShiftMax) + subnormalShiftLane := "%" + subnormalShift + if laneBits == 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, subnormalShift) + subnormalShiftLane = "%" + wide + } + quotient, subOneShifted, subRemainderMask, subRemainder := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i%d %%%s, %s\n", quotient, laneBits, normalizedSignificand, subnormalShiftLane) + fmt.Fprintf(c.b, " %%%s = shl i%d 1, %s\n", subOneShifted, laneBits, subnormalShiftLane) + fmt.Fprintf(c.b, " %%%s = sub i%d %%%s, 1\n", subRemainderMask, laneBits, subOneShifted) + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, %%%s\n", subRemainder, laneBits, normalizedSignificand, subRemainderMask) + subRemainderNonzero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", subRemainderNonzero, laneBits, subRemainder) + halfShift32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 %%%s, 1\n", halfShift32, subnormalShift) + halfShift := "%" + halfShift32 + if laneBits == 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, halfShift32) + halfShift = "%" + wide + } + half, aboveHalf, equalHalf, quotientOdd, tieOdd, nearest := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i%d 1, %s\n", half, laneBits, halfShift) + fmt.Fprintf(c.b, " %%%s = icmp ugt i%d %%%s, %%%s\n", aboveHalf, laneBits, subRemainder, half) + fmt.Fprintf(c.b, " %%%s = icmp eq i%d %%%s, %%%s\n", equalHalf, laneBits, subRemainder, half) + quotientLowBit := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i%d %%%s, 1\n", quotientLowBit, laneBits, quotient) + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %%%s, 0\n", quotientOdd, laneBits, quotientLowBit) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", tieOdd, equalHalf, quotientOdd) + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", nearest, aboveHalf, tieOdd) + xNegative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne i%d %s, 0\n", xNegative, laneBits, x.sign) + increment := c.emitScaledRoundIncrement(controls.rounding, "%"+xNegative, "%"+subRemainderNonzero, "%"+nearest) + incrementBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %s to i%d\n", incrementBits, increment, laneBits) + roundedSubnormal, subnormalBits := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i%d %%%s, %%%s\n", roundedSubnormal, laneBits, quotient, incrementBits) + fmt.Fprintf(c.b, " %%%s = or i%d %s, %%%s\n", subnormalBits, laneBits, x.sign, roundedSubnormal) + isSubnormal := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i%d %%%s, %d\n", isSubnormal, laneBits, roundedSubnormal, implicitBit) + flushInexact, flushSubnormal := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %s, %%%s\n", flushInexact, controls.ftz, subRemainderNonzero) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", flushSubnormal, flushInexact, isSubnormal) + underflowBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %s, i%d %%%s\n", underflowBits, flushSubnormal, laneBits, x.sign, laneBits, subnormalBits) + + toInfinity := c.emitScaledRoundIncrement(controls.rounding, "%"+xNegative, "true", "true") + overflowInfinity := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %d, i%d %d\n", overflowInfinity, toInfinity, laneBits, exponentMask, laneBits, exponentMask-1) + overflowBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %s, %%%s\n", overflowBits, laneBits, x.sign, overflowInfinity) + finiteNonOverflow, finiteBits := c.newTmp(), c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", finiteNonOverflow, normal, laneBits, normalBits, laneBits, underflowBits) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", finiteBits, overflow, laneBits, overflowBits, laneBits, finiteNonOverflow) + + yInfinityResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %d, i%d %s\n", yInfinityResult, y.positiveInfinity, laneBits, exponentMask, laneBits, x.sign) + yInfinitySigned := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %s, %%%s\n", yInfinitySigned, laneBits, x.sign, yInfinityResult) + general := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %%%s\n", general, y.infinity, laneBits, yInfinitySigned, laneBits, finiteBits) + xZeroInfinity := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %d, i%d %s\n", xZeroInfinity, y.positiveInfinity, laneBits, indefinite, laneBits, x.bits) + xZeroResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %s\n", xZeroResult, y.infinity, laneBits, xZeroInfinity, laneBits, x.bits) + withZero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %%%s\n", withZero, x.zero, laneBits, xZeroResult, laneBits, general) + xInfinityResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %d, i%d %s\n", xInfinityResult, y.negativeInfinity, laneBits, indefinite, laneBits, x.bits) + withInfinity := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %%%s\n", withInfinity, x.infinity, laneBits, xInfinityResult, laneBits, withZero) + quietY := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %s, %d\n", quietY, laneBits, y.bits, quietBit) + withYNaN := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %%%s\n", withYNaN, y.nan, laneBits, quietY, laneBits, withInfinity) + quietX := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i%d %s, %d\n", quietX, laneBits, x.bits, quietBit) + xQNaNInfinity := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %d, i%d 0\n", xQNaNInfinity, y.positiveInfinity, laneBits, exponentMask, laneBits) + xQNaNResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %%%s\n", xQNaNResult, y.infinity, laneBits, xQNaNInfinity, laneBits, quietX) + xQNaN := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %s, true\n", xQNaN, x.nan) + notSNaN := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", notSNaN, x.snan) + isQNaN := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isQNaN, xQNaN, notSNaN) + withXQNaN := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", withXQNaN, isQNaN, laneBits, xQNaNResult, laneBits, withYNaN) + final := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %%%s\n", final, x.snan, laneBits, quietX, laneBits, withXQNaN) + return "%" + final +} diff --git a/amd64_lower_scalef_test.go b/amd64_lower_scalef_test.go new file mode 100644 index 00000000..b570aa95 --- /dev/null +++ b/amd64_lower_scalef_test.go @@ -0,0 +1,292 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64ScaleFGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64BinaryFloatingSpec{ + "VSCALEFPS": {laneBits: 32, mode: amd64BinaryFloatingScale}, + "VSCALEFPD": {laneBits: 64, mode: amd64BinaryFloatingScale}, + "VSCALEFSS": {laneBits: 32, mode: amd64BinaryFloatingScale, scalar: true}, + "VSCALEFSD": {laneBits: 64, mode: amd64BinaryFloatingScale, scalar: true}, + } + for op, want := range expected { + if got, ok := amd64BinaryFloatingSpecs[op]; !ok { + t.Errorf("SCALEF grammar omitted %s", op) + } else if got != want { + t.Errorf("SCALEF grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86ScaleFCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT scalefforms(SB),$0-0\n") + for _, op := range []string{"VSCALEFPS", "VSCALEFPD"} { + for _, width := range []string{"X", "Y", "Z"} { + last := 31 + if target.goarch == "386" { + last = 7 + } + fmt.Fprintf(&source, "\t%s %s1, %s2, %s%d\n", op, width, width, width, last) + fmt.Fprintf(&source, "\t%s 8(AX), %s2, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s.BCST 16(AX), %s2, %s%d\n", op, width, width, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s %s1, %s2, K1, %s%d\n", op, width, width, width, last) + fmt.Fprintf(&source, "\t%s.Z 24(AX), %s2, K2, %s%d\n", op, width, width, last) + fmt.Fprintf(&source, "\t%s.BCST.Z 32(AX), %s2, K3, %s%d\n", op, width, width, last) + } + if width == "Z" { + for _, rounding := range []string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"} { + fmt.Fprintf(&source, "\t%s.%s Z1, Z2, Z%d\n", op, rounding, last) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.%s.Z Z1, Z2, K4, Z%d\n", op, rounding, last) + } + } + } + } + } + for _, op := range []string{"VSCALEFSS", "VSCALEFSD"} { + fmt.Fprintf(&source, "\t%s X1, X2, X7\n", op) + fmt.Fprintf(&source, "\t%s 40(AX), X2, X7\n", op) + for _, rounding := range []string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"} { + fmt.Fprintf(&source, "\t%s.%s X1, X2, X7\n", op, rounding) + } + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s X1, X2, K5, X31\n", op) + fmt.Fprintf(&source, "\t%s.Z 48(AX), X2, K6, X31\n", op) + fmt.Fprintf(&source, "\t%s.RN_SAE.Z X1, X2, K7, X31\n", op) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"scalefforms": {Name: "scalefforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "scalef-"+target.name+".ll", "scalef-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86ScaleFRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VSCALEFPS X0, X1"}, + {goarch: "amd64", instruction: "VSCALEFPS X0, X1, X2, X3, X4"}, + {goarch: "amd64", instruction: "VSCALEFPS X0, Y1, Y2"}, + {goarch: "amd64", instruction: "VSCALEFPS X0, 8(AX), X2"}, + {goarch: "amd64", instruction: "VSCALEFPS X0, X1, K0, X2"}, + {goarch: "amd64", instruction: "VSCALEFPS.Z X0, X1, X2"}, + {goarch: "amd64", instruction: "VSCALEFPS.BCST X0, X1, X2"}, + {goarch: "amd64", instruction: "VSCALEFPS.RN_SAE 8(AX), Z1, Z2"}, + {goarch: "amd64", instruction: "VSCALEFPS.SAE Z0, Z1, Z2"}, + {goarch: "amd64", instruction: "VSCALEFPS.RN_SAE Y0, Y1, Y2"}, + {goarch: "amd64", instruction: "VSCALEFSS Y0, X1, X2"}, + {goarch: "amd64", instruction: "VSCALEFSS.BCST 8(AX), X1, X2"}, + {goarch: "amd64", instruction: "VSCALEFSS.RN_SAE 8(AX), X1, X2"}, + {goarch: "amd64", instruction: "VSCALEFSS X0, Y1, X2"}, + {goarch: "386", instruction: "VSCALEFPS X0, X1, K1, X2"}, + {goarch: "386", instruction: "VSCALEFPS Z8, Z1, Z2"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SCALEF tables", test.instruction) + } + }) + } +} + +func TestAMD64ScaleFRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT scalefsemantics(SB),$0-72 + MOVQ out+0(FP), AX + MOVQ value32+8(FP), BX + MOVQ scale32+16(FP), CX + MOVQ value64+24(FP), DX + MOVQ scale64+32(FP), R8 + MOVQ old32+40(FP), R9 + MOVQ old64+48(FP), R10 + MOVQ upper+56(FP), R11 + MOVQ mask+64(FP), R12 + KMOVQ R12, K1 + VMOVDQU32 0(BX), Z1 + VMOVDQU32 0(CX), Z2 + VSCALEFPS Z2, Z1, Z3 + VMOVDQU32 Z3, 0(AX) + VSCALEFPS.RN_SAE Z2, Z1, Z3 + VMOVDQU32 Z3, 64(AX) + VMOVDQU32 0(R9), Z3 + VSCALEFPS Z2, Z1, K1, Z3 + VMOVDQU32 Z3, 128(AX) + VSCALEFPS.BCST 0(CX), Z1, Z3 + VMOVDQU32 Z3, 192(AX) + VMOVDQU64 0(DX), Z4 + VMOVDQU64 0(R8), Z5 + VSCALEFPD Z5, Z4, Z6 + VMOVDQU64 Z6, 256(AX) + VSCALEFPD.RN_SAE Z5, Z4, Z6 + VMOVDQU64 Z6, 320(AX) + VMOVDQU64 0(R10), Z6 + VSCALEFPD.Z Z5, Z4, K1, Z6 + VMOVDQU64 Z6, 384(AX) + VSCALEFPD.BCST 0(R8), Z4, Z6 + VMOVDQU64 Z6, 448(AX) + VMOVDQU64 0(R11), X7 + VSCALEFSS 60(CX), X7, X8 + VMOVDQU64 X8, 512(AX) + VSCALEFSD 56(R8), X7, X9 + VMOVDQU64 X9, 528(AX) + STC + SETCS 544(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"scalefsemantics": { + Name: "scalefsemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + {Offset: 48, Type: Ptr, Index: 6, Field: -1}, + {Offset: 56, Type: Ptr, Index: 7, Field: -1}, + {Offset: 64, Type: I64, Index: 8, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +#include +#include +#include +extern void scalefsemantics(uint8_t *, const uint32_t *, const uint32_t *, const uint64_t *, const uint64_t *, const uint32_t *, const uint64_t *, const uint64_t *, uint64_t); +static uint32_t u32(const uint8_t *p) { uint32_t v; memcpy(&v,p,4); return v; } +static uint64_t u64(const uint8_t *p) { uint64_t v; memcpy(&v,p,8); return v; } +static uint32_t scale32(uint32_t x, uint32_t y, int daz) { + const uint32_t em=UINT32_C(0x7f800000), fm=UINT32_C(0x007fffff), qb=UINT32_C(0x00400000), sb=UINT32_C(0x80000000), ind=UINT32_C(0xffc00000); + if(daz && !(x&em) && (x&fm)) x&=sb; if(daz && !(y&em) && (y&fm)) y&=sb; + uint32_t xf=x&fm,yf=y&fm; int xn=(x&em)==em&&xf, xs=xn&&!(xf&qb), xi=(x&~sb)==em, xz=(x&~sb)==0; + int yn=(y&em)==em&&yf, yi=(y&~sb)==em, yp=yi&&!(y&sb), ym=yi&&(y&sb); + if(xs) return x|qb; + if(xn) return yi?(yp?em:0):(x|qb); + if(yn) return y|qb; + if(xi) return ym?ind:x; + if(xz) return yp?ind:x; + if(yp) return (x&sb)|em; if(ym) return x&sb; + float a,b,r; memcpy(&a,&x,4); memcpy(&b,&y,4); int n=b>=512?512:(b<=-512?-512:(int)floorf(b)); r=scalbnf(a,n); memcpy(&x,&r,4); return x; +} +static uint64_t scale64(uint64_t x, uint64_t y, int daz) { + const uint64_t em=UINT64_C(0x7ff0000000000000), fm=UINT64_C(0x000fffffffffffff), qb=UINT64_C(0x0008000000000000), sb=UINT64_C(0x8000000000000000), ind=UINT64_C(0xfff8000000000000); + if(daz && !(x&em) && (x&fm)) x&=sb; if(daz && !(y&em) && (y&fm)) y&=sb; + uint64_t xf=x&fm,yf=y&fm; int xn=(x&em)==em&&xf, xs=xn&&!(xf&qb), xi=(x&~sb)==em, xz=(x&~sb)==0; + int yn=(y&em)==em&&yf, yi=(y&~sb)==em, yp=yi&&!(y&sb), ym=yi&&(y&sb); + if(xs) return x|qb; + if(xn) return yi?(yp?em:0):(x|qb); + if(yn) return y|qb; + if(xi) return ym?ind:x; + if(xz) return yp?ind:x; + if(yp) return (x&sb)|em; if(ym) return x&sb; + double a,b,r; memcpy(&a,&x,8); memcpy(&b,&y,8); int n=b>=4096?4096:(b<=-4096?-4096:(int)floor(b)); r=scalbn(a,n); memcpy(&x,&r,8); return x; +} +int main(void) { + const uint32_t v32[16]={0x3f800000,0xbf800000,0x7f7fffff,0xff7fffff,0x00800000,0x80800000,1,0x80000001,0,0x80000000,0x7f800000,0xff800000,0x7fc12345,0x7f812345,0x3fc00000,0xbfc00000}; + const uint32_t s32[16]={0x3ff33333,0xbf8ccccd,0x3f800000,0x3f800000,0xbf800000,0xbf800000,0x3f800000,0x3f800000,0x7f800000,0xff800000,0xff800000,0x7f800000,0x7f800000,0,0xc3160000,0xc3160000}; + const uint64_t v64[8]={UINT64_C(0x3ff0000000000000),UINT64_C(0xbff0000000000000),UINT64_C(0x7fefffffffffffff),UINT64_C(0xffefffffffffffff),UINT64_C(0x0010000000000000),1,UINT64_C(0x7ff8123456789abc),UINT64_C(0x7ff0123456789abc)}; + const uint64_t s64[8]={UINT64_C(0x3ffe666666666666),UINT64_C(0xbff199999999999a),UINT64_C(0x3ff0000000000000),UINT64_C(0x3ff0000000000000),UINT64_C(0xbff0000000000000),UINT64_C(0x3ff0000000000000),UINT64_C(0x7ff0000000000000),0}; + uint32_t old32[16]; uint64_t old64[8]; + uint64_t upper[2]={UINT64_C(0x112233443fc00000),UINT64_C(0x99aabbccddeeff00)}; + for(int i=0;i<16;i++)old32[i]=UINT32_C(0x41000000)+(uint32_t)i; for(int i=0;i<8;i++)old64[i]=UINT64_C(0x4020000000000000)+(uint64_t)i; + const uint64_t mask=UINT64_C(0xa55a); unsigned original=_mm_getcsr(); + const int fes[4]={FE_TONEAREST,FE_DOWNWARD,FE_UPWARD,FE_TOWARDZERO}; + for(unsigned rc=0;rc<4;rc++) for(unsigned daz=0;daz<2;daz++) { + uint8_t out[545]={0}; unsigned csr=(original&~UINT32_C(0xe040))|(rc<<13)|(daz?UINT32_C(0x40):0); _mm_setcsr(csr); fesetround(fes[rc]); + scalefsemantics(out,v32,s32,v64,s64,old32,old64,upper,mask); + for(int i=0;i<16;i++) { + uint32_t want=scale32(v32[i],s32[i],daz); if(u32(out+i*4)!=want)return 10+rc; + int saved=fegetround(); fesetround(FE_TONEAREST); uint32_t rn=scale32(v32[i],s32[i],daz); fesetround(saved); if(u32(out+64+i*4)!=rn)return 20+rc; + if(u32(out+128+i*4)!=(((mask>>i)&1)?want:old32[i]))return 30+rc; + if(u32(out+192+i*4)!=scale32(v32[i],s32[0],daz))return 40+rc; + } + for(int i=0;i<8;i++) { + uint64_t want=scale64(v64[i],s64[i],daz); if(u64(out+256+i*8)!=want)return 50+rc; + int saved=fegetround(); fesetround(FE_TONEAREST); uint64_t rn=scale64(v64[i],s64[i],daz); fesetround(saved); if(u64(out+320+i*8)!=rn)return 60+rc; + if(u64(out+384+i*8)!=(((mask>>i)&1)?want:0))return 70+rc; + if(u64(out+448+i*8)!=scale64(v64[i],s64[0],daz))return 80+rc; + } + if(u32(out+512)!=scale32((uint32_t)upper[0],s32[15],daz)||memcmp(out+516,(uint8_t*)upper+4,12))return 90+rc; + if(u64(out+528)!=scale64(upper[0],s64[7],daz)||u64(out+536)!=upper[1])return 100+rc; + if(out[544]!=1)return 110+rc; + } + _mm_setcsr(original); fesetround(FE_TONEAREST); return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "scalef_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_scatter.go b/amd64_lower_scatter.go new file mode 100644 index 00000000..9825f9d9 --- /dev/null +++ b/amd64_lower_scatter.go @@ -0,0 +1,127 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var amd64ScatterSpecs = map[string]amd64GatherSpec{ + "VPSCATTERDD": {table: amd64GatherDPS, elemBits: 32, indexBits: 32}, + "VPSCATTERQQ": {table: amd64GatherDPS, elemBits: 64, indexBits: 64}, + "VSCATTERDPS": {table: amd64GatherDPS, elemBits: 32, indexBits: 32}, + "VSCATTERQPD": {table: amd64GatherDPS, elemBits: 64, indexBits: 64}, + "VPSCATTERDQ": {table: amd64GatherDPD, elemBits: 64, indexBits: 32}, + "VSCATTERDPD": {table: amd64GatherDPD, elemBits: 64, indexBits: 32}, + "VPSCATTERQD": {table: amd64GatherQPS, elemBits: 32, indexBits: 64}, + "VSCATTERQPS": {table: amd64GatherQPS, elemBits: 32, indexBits: 64}, +} + +// lowerScatter implements all Go 1.27 packed integer and floating scatter +// spellings. Values are kept as integer bit patterns, which is exact for the +// floating variants as well. +func (c *amd64Ctx) lowerScatter(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + if strings.Contains(rawOp, ".") { + baseOp := strings.SplitN(rawOp, ".", 2)[0] + if _, known := amd64ScatterSpecs[baseOp]; known { + return true, false, fmt.Errorf("amd64 %s has no suffixes in its Go 1.27 table: %q", baseOp, ins.Raw) + } + return false, false, nil + } + spec, ok := amd64ScatterSpecs[rawOp] + if !ok { + return false, false, nil + } + if len(ins.Args) != 3 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpMem { + return true, false, fmt.Errorf("amd64 %s expects data vector, K1-K7, VSIB memory: %q", rawOp, ins.Raw) + } + data, mask, memory := ins.Args[0], ins.Args[1], ins.Args[2].Mem + maskIndex, validMask := amd64ParseKReg(mask.Reg) + if !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s requires K1-K7: %q", rawOp, ins.Raw) + } + + dataBytes := amd64VectorByteWidth(data.Reg) + indexBytes := amd64VectorByteWidth(memory.Index) + if dataBytes == 0 || indexBytes == 0 || !amd64GatherTableAllows(spec.table, true, dataBytes, indexBytes) { + return true, false, fmt.Errorf("amd64 %s data/index widths are outside its Go 1.27 table: %q", rawOp, ins.Raw) + } + if err := c.validateGatherMemory(memory, indexBytes, true); err != nil { + return true, false, fmt.Errorf("amd64 %s invalid VSIB memory: %q: %w", rawOp, ins.Raw, err) + } + if _, ok := amd64GatherRegisterIndex(data.Reg, dataBytes, true, c.goarch, false); !ok { + return true, false, fmt.Errorf("amd64 %s data register is outside its Go 1.27 class: %q", rawOp, ins.Raw) + } + if _, ok := amd64GatherRegisterIndex(memory.Index, indexBytes, true, c.goarch, true); !ok { + return true, false, fmt.Errorf("amd64 %s VSIB index is outside its Go 1.27 class: %q", rawOp, ins.Raw) + } + return true, false, c.emitScatter(spec, memory, mask.Reg, data.Reg, dataBytes, indexBytes) +} + +func (c *amd64Ctx) emitScatter(spec amd64GatherSpec, memory MemRef, mask, data Reg, dataBytes, indexBytes int) error { + dataValue, err := c.loadGatherVector(data, dataBytes) + if err != nil { + return err + } + dataLanes := dataBytes * 8 / spec.elemBits + dataType := fmt.Sprintf("<%d x i%d>", dataLanes, spec.elemBits) + dataValues := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", dataValues, dataBytes, dataValue, dataType) + + indexValue, err := c.loadGatherVector(memory.Index, indexBytes) + if err != nil { + return err + } + indexLanes := indexBytes * 8 / spec.indexBits + indexType := fmt.Sprintf("<%d x i%d>", indexLanes, spec.indexBits) + indexValues := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", indexValues, indexBytes, indexValue, indexType) + activeLanes := dataLanes + if indexLanes < activeLanes { + activeLanes = indexLanes + } + + maskValue, err := c.loadK(mask) + if err != nil { + return err + } + base, err := c.gatherBaseAddress(memory) + if err != nil { + return err + } + for lane := 0; lane < activeLanes; lane++ { + indexLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", indexLane, indexType, indexValues, lane) + wideIndex := "%" + indexLane + if spec.indexBits == 32 { + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext i32 %%%s to i64\n", extended, indexLane) + wideIndex = "%" + extended + } + if memory.Scale != 0 && memory.Scale != 1 { + scaled := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i64 %s, %d\n", scaled, wideIndex, memory.Scale) + wideIndex = "%" + scaled + } + address := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", address, base, wideIndex) + pointer, pointerType := c.gatherPointer(memory, "%"+address) + + condition := amd64MaskBitI1(c, maskValue, lane) + dataLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", dataLane, dataType, dataValues, lane) + storeLabel := c.newTmp() + "_scatter_store" + skipLabel := c.newTmp() + "_scatter_skip" + joinLabel := c.newTmp() + "_scatter_join" + fmt.Fprintf(c.b, " br i1 %s, label %%%s, label %%%s\n", condition, storeLabel, skipLabel) + fmt.Fprintf(c.b, "%s:\n", storeLabel) + fmt.Fprintf(c.b, " store i%d %%%s, %s %s, align 1\n", spec.elemBits, dataLane, pointerType, pointer) + fmt.Fprintf(c.b, " br label %%%s\n", joinLabel) + fmt.Fprintf(c.b, "%s:\n", skipLabel) + fmt.Fprintf(c.b, " br label %%%s\n", joinLabel) + fmt.Fprintf(c.b, "%s:\n", joinLabel) + } + // Like EVEX gather, scatter clears completed mask bits to support precise + // restart after a fault. A normally completed instruction leaves zero. + return c.storeK(mask, "0") +} diff --git a/amd64_lower_scatter_prefetch_test.go b/amd64_lower_scatter_prefetch_test.go new file mode 100644 index 00000000..252126a4 --- /dev/null +++ b/amd64_lower_scatter_prefetch_test.go @@ -0,0 +1,143 @@ +package plan9asm + +import ( + "fmt" + "sort" + "strings" + "testing" +) + +func TestAMD64VSIBPrefetchGrammarIsComplete(t *testing.T) { + got := make([]string, 0, len(amd64VSIBPrefetchSpecs)) + for op := range amd64VSIBPrefetchSpecs { + got = append(got, string(op)) + } + sort.Strings(got) + want := []string{ + "VGATHERPF0DPD", "VGATHERPF0DPS", "VGATHERPF0QPD", "VGATHERPF0QPS", + "VGATHERPF1DPD", "VGATHERPF1DPS", "VGATHERPF1QPD", "VGATHERPF1QPS", + "VSCATTERPF0DPD", "VSCATTERPF0DPS", "VSCATTERPF0QPD", "VSCATTERPF0QPS", + "VSCATTERPF1DPD", "VSCATTERPF1DPS", "VSCATTERPF1QPD", "VSCATTERPF1QPS", + } + if strings.Join(got, ",") != strings.Join(want, ",") { + t.Fatalf("VSIB-prefetch grammar opcodes = %v, want %v", got, want) + } + for op, spec := range amd64VSIBPrefetchSpecs { + name := string(op) + wantDirection := amd64VSIBPrefetchGather + if strings.HasPrefix(name, "VSCATTER") { + wantDirection = amd64VSIBPrefetchScatter + } + wantHint := 0 + if strings.Contains(name, "PF1") { + wantHint = 1 + } + shape := name[strings.Index(name, "PF")+3:] + wantIndexBits := 32 + if shape[0] == 'Q' { + wantIndexBits = 64 + } + wantElemBits := 32 + if shape[2] == 'D' { + wantElemBits = 64 + } + wantIndexBytes := 64 + if shape == "DPD" { + wantIndexBytes = 32 + } + if spec.direction != wantDirection || spec.hint != wantHint || spec.indexBits != wantIndexBits || + spec.elemBits != wantElemBits || spec.indexBytes != wantIndexBytes { + t.Errorf("VSIB-prefetch grammar %s = %+v, want direction=%d hint=%d elem=%d index=%d vector=%d", + op, spec, wantDirection, wantHint, wantElemBits, wantIndexBits, wantIndexBytes) + } + } +} + +func TestTranslateX86ScatterPrefetchCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT scatterprefetchforms(SB),$0-0\n") + for _, op := range []string{"VSCATTERPF0DPD", "VSCATTERPF1DPD"} { + fmt.Fprintf(&source, "\t%s K1, 8(SP)(Y2*8)\n", op) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s K7, 16(R11)(Y20*4)\n", op) + } + } + for _, op := range []string{ + "VSCATTERPF0DPS", "VSCATTERPF0QPD", "VSCATTERPF0QPS", + "VSCATTERPF1DPS", "VSCATTERPF1QPD", "VSCATTERPF1QPS", + } { + fmt.Fprintf(&source, "\t%s K2, 24(BX)(Z3*4)\n", op) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s K6, 32(SP)(Z20*8)\n", op) + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"scatterprefetchforms": {Name: "scatterprefetchforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "scatter-prefetch-"+target.name+".ll", "scatter-prefetch-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86ScatterPrefetchRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VSCATTERPF0DPD K0, (AX)(Y2*8)"}, + {goarch: "amd64", instruction: "VSCATTERPF1DPD K1, (AX)(Z2*8)"}, + {goarch: "amd64", instruction: "VSCATTERPF0DPS K1, (AX)(Y2*4)"}, + {goarch: "amd64", instruction: "VSCATTERPF0QPD K1, (AX)"}, + {goarch: "amd64", instruction: "VSCATTERPF0QPS (AX)(Z2*4), K1"}, + {goarch: "amd64", instruction: "VSCATTERPF1DPS.Z K1, (AX)(Z2*4)"}, + {goarch: "amd64", instruction: "VSCATTERPF1QPD K1, (AX)(Z2*4), Z3"}, + {goarch: "amd64", instruction: "VSCATTERPF1QPS X1, (AX)(Z2*4)"}, + {goarch: "386", instruction: "VSCATTERPF0DPD K1, (R8)(Y2*8)"}, + {goarch: "386", instruction: "VSCATTERPF1DPS K1, (AX)(Z8*4)"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scatter-prefetch tables", test.instruction) + } + }) + } +} diff --git a/amd64_lower_scatter_test.go b/amd64_lower_scatter_test.go new file mode 100644 index 00000000..9c4a0c4d --- /dev/null +++ b/amd64_lower_scatter_test.go @@ -0,0 +1,102 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86ScatterCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 exposes eight integer/floating spellings over three exact + // data/index width tables. Every form is data, K1-K7, VSIB memory. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastZ := 20 + if target.goarch == "386" { + lastZ = 7 + } + var source strings.Builder + source.WriteString("TEXT scatterforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VPSCATTERDD", "VPSCATTERQQ", "VSCATTERDPS", "VSCATTERQPD"} { + fmt.Fprintf(&source, "\t%s X20, K1, (AX)(X2*1)\n", op) + fmt.Fprintf(&source, "\t%s Y20, K2, 8(BX)(Y3*2)\n", op) + fmt.Fprintf(&source, "\t%s Z%d, K3, 16(CX)(Z4*4)\n", op, lastZ) + } + for _, op := range []string{"VPSCATTERDQ", "VSCATTERDPD"} { + fmt.Fprintf(&source, "\t%s X20, K4, 24(DX)(X5*8)\n", op) + fmt.Fprintf(&source, "\t%s Y20, K5, 32(SI)(X6*1)\n", op) + fmt.Fprintf(&source, "\t%s Z%d, K6, 40(DI)(Y7*2)\n", op, lastZ) + } + for _, op := range []string{"VPSCATTERQD", "VSCATTERQPS"} { + fmt.Fprintf(&source, "\t%s X20, K7, 48(AX)(X2*4)\n", op) + fmt.Fprintf(&source, "\t%s X20, K1, 56(BX)(Y3*8)\n", op) + fmt.Fprintf(&source, "\t%s Y20, K2, 64(CX)(Z4*1)\n", op) + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"scatterforms": {Name: "scatterforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "scatter-"+target.name+".ll", "scatter-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86ScatterRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "VPSCATTERDD X1, (AX)(X2*1)", + "VPSCATTERDD X1, K0, (AX)(X2*1)", + "VPSCATTERDD X1, K1, (AX)", + "VPSCATTERDD Y1, K1, (AX)(X2*1)", + "VPSCATTERDQ X1, K1, (AX)(Y2*1)", + "VPSCATTERQD Y1, K1, (AX)(Y2*1)", + "VPSCATTERDD X1, K1, (AX)(X2*3)", + "VPSCATTERDD.Z X1, K1, (AX)(X2*1)", + "VPSCATTERDD X1, K1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86ScatterRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + assertX86ScatterRejected(t, "386", "i386-unknown-linux-gnu", "VPSCATTERDD X1, K1, (R8)(X2*1)") + assertX86ScatterRejected(t, "386", "i386-unknown-linux-gnu", "VPSCATTERDD X1, K1, (AX)(X8*1)") + assertX86ScatterRejected(t, "386", "i386-unknown-linux-gnu", "VPSCATTERDD Z8, K1, (AX)(Z7*1)") +} + +func assertX86ScatterRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scatter forms", instruction) + } +} diff --git a/amd64_lower_segment_base.go b/amd64_lower_segment_base.go new file mode 100644 index 00000000..a56e91f8 --- /dev/null +++ b/amd64_lower_segment_base.go @@ -0,0 +1,123 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64SegmentBaseDirection uint8 + +const ( + amd64SegmentBaseRead amd64SegmentBaseDirection = iota + amd64SegmentBaseWrite +) + +type amd64SegmentBaseSpec struct { + segment Reg + direction amd64SegmentBaseDirection + bits int +} + +// amd64SegmentBaseSpecs is the complete Go 1.27 FSGSBASE grammar. Segment, +// transfer direction, and width are data; all eight opcodes share one Yrl +// register parser and one exact inline-assembly emitter. +var amd64SegmentBaseSpecs = map[Op]amd64SegmentBaseSpec{ + "RDFSBASEL": {segment: FS, direction: amd64SegmentBaseRead, bits: 32}, + "RDFSBASEQ": {segment: FS, direction: amd64SegmentBaseRead, bits: 64}, + "RDGSBASEL": {segment: GS, direction: amd64SegmentBaseRead, bits: 32}, + "RDGSBASEQ": {segment: GS, direction: amd64SegmentBaseRead, bits: 64}, + "WRFSBASEL": {segment: FS, direction: amd64SegmentBaseWrite, bits: 32}, + "WRFSBASEQ": {segment: FS, direction: amd64SegmentBaseWrite, bits: 64}, + "WRGSBASEL": {segment: GS, direction: amd64SegmentBaseWrite, bits: 32}, + "WRGSBASEQ": {segment: GS, direction: amd64SegmentBaseWrite, bits: 64}, +} + +type amd64SegmentBaseForm struct { + register Reg +} + +func (c *amd64Ctx) lowerSegmentBase(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64SegmentBaseSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && spec.bits == 64 { + return true, false, fmt.Errorf("386 %s is absent from Go 1.27's 32-bit encoding table: %q", baseOp, ins.Raw) + } + form, err := c.parseSegmentBaseForm(baseOp, ins) + if err != nil { + return true, false, err + } + return c.emitSegmentBase(spec, form) +} + +func (c *amd64Ctx) parseSegmentBaseForm(op string, ins Instr) (amd64SegmentBaseForm, error) { + var form amd64SegmentBaseForm + if len(ins.Args) != 1 { + return form, fmt.Errorf("%s %s expects one Go 1.27 Yrl register: %q", c.goarch, op, ins.Raw) + } + operand := ins.Args[0] + if operand.Kind != OpReg || !isX86YrlRegisterForArch(operand.Reg, c.goarch) { + return form, fmt.Errorf("%s %s expects a Go 1.27 Yrl register: %q", c.goarch, op, ins.Raw) + } + return amd64SegmentBaseForm{register: operand.Reg}, nil +} + +func (spec amd64SegmentBaseSpec) mnemonic() string { + prefix := "rd" + if spec.direction == amd64SegmentBaseWrite { + prefix = "wr" + } + width := "l" + if spec.bits == 64 { + width = "q" + } + return prefix + strings.ToLower(string(spec.segment)) + "base" + width +} + +func (c *amd64Ctx) emitSegmentBase(spec amd64SegmentBaseSpec, form amd64SegmentBaseForm) (bool, bool, error) { + typ := amd64IntegerTypeForBits(spec.bits) + constraints := "~{dirflag},~{fpsr},~{flags}" + assembly := spec.mnemonic() + " $0" + registerConstraint := "r" + if c.goarch == "386" { + // Intel defines FSGSBASE only in 64-bit mode, but Go 1.27's 386 + // assembler accepts the L spellings and emits their F3 0F AE /r + // encodings. LLVM intentionally rejects the mnemonic for i386. Emit + // Go's exact EAX encoding and use a fixed-register constraint so the + // object remains byte-compatible without claiming runtime viability. + modRM := byte(0xc0) + if spec.segment == GS { + modRM += 8 + } + if spec.direction == amd64SegmentBaseWrite { + modRM += 16 + } + assembly = fmt.Sprintf(".byte 0xf3, 0x0f, 0xae, 0x%02x", modRM) + registerConstraint = "{ax}" + } + if spec.direction == amd64SegmentBaseRead { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q()\n", + result, typ, assembly, "="+registerConstraint+","+constraints) + if err := c.storeRegSized(form.register, typ, "%"+result); err != nil { + return true, false, err + } + return true, false, nil + } + value, err := c.evalIntSized(Operand{Kind: OpReg, Reg: form.register}, typ) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s %s)\n", + assembly, registerConstraint+","+constraints, typ, value) + return true, false, nil +} diff --git a/amd64_lower_segment_base_test.go b/amd64_lower_segment_base_test.go new file mode 100644 index 00000000..f17f2432 --- /dev/null +++ b/amd64_lower_segment_base_test.go @@ -0,0 +1,147 @@ +package plan9asm + +import ( + "reflect" + "sort" + "strings" + "testing" +) + +func TestAMD64SegmentBaseGrammarIsComplete(t *testing.T) { + got := make([]string, 0, len(amd64SegmentBaseSpecs)) + for op := range amd64SegmentBaseSpecs { + got = append(got, string(op)) + } + sort.Strings(got) + want := []string{ + "RDFSBASEL", "RDFSBASEQ", "RDGSBASEL", "RDGSBASEQ", + "WRFSBASEL", "WRFSBASEQ", "WRGSBASEL", "WRGSBASEQ", + } + if !reflect.DeepEqual(got, want) { + t.Fatalf("segment-base grammar opcodes = %v, want %v", got, want) + } + for op, want := range map[Op]amd64SegmentBaseSpec{ + "RDFSBASEL": {segment: FS, direction: amd64SegmentBaseRead, bits: 32}, + "RDFSBASEQ": {segment: FS, direction: amd64SegmentBaseRead, bits: 64}, + "RDGSBASEL": {segment: GS, direction: amd64SegmentBaseRead, bits: 32}, + "RDGSBASEQ": {segment: GS, direction: amd64SegmentBaseRead, bits: 64}, + "WRFSBASEL": {segment: FS, direction: amd64SegmentBaseWrite, bits: 32}, + "WRFSBASEQ": {segment: FS, direction: amd64SegmentBaseWrite, bits: 64}, + "WRGSBASEL": {segment: GS, direction: amd64SegmentBaseWrite, bits: 32}, + "WRGSBASEQ": {segment: GS, direction: amd64SegmentBaseWrite, bits: 64}, + } { + if got := amd64SegmentBaseSpecs[op]; got != want { + t.Errorf("segment-base grammar %s = %+v, want %+v", op, got, want) + } + if got := want.mnemonic(); strings.ToUpper(got) != string(op) { + t.Errorf("segment-base grammar %s emits %q", op, got) + } + } +} + +func TestTranslateX86SegmentBaseCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := `TEXT segmentbaseforms(SB),$0-0 + RDFSBASEL AX + RDGSBASEL SP + WRFSBASEL CX + WRGSBASEL SP +` + if target.goarch == "amd64" { + source += ` RDFSBASEQ R11 + RDGSBASEQ R12 + WRFSBASEQ R13 + WRGSBASEQ R14 +` + } + source += "\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"segmentbaseforms": {Name: "segmentbaseforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if want := `"target-features"="+fsgsbase"`; !strings.Contains(ir, want) { + t.Errorf("IR is missing %s:\n%s", want, ir) + } + if target.goarch == "386" { + for _, encoding := range []string{ + ".byte 0xf3, 0x0f, 0xae, 0xc0", + ".byte 0xf3, 0x0f, 0xae, 0xc8", + ".byte 0xf3, 0x0f, 0xae, 0xd0", + ".byte 0xf3, 0x0f, 0xae, 0xd8", + } { + if !strings.Contains(ir, encoding) { + t.Errorf("386 IR is missing Go-compatible encoding %q:\n%s", encoding, ir) + } + } + } + compileLLVMToObject(t, llc, target.triple, "segment-base-"+target.name+".ll", "segment-base-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86SegmentBaseRejectsFormsOutsideGoTables(t *testing.T) { + tests := []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "RDFSBASEL $1"}, + {goarch: "amd64", instruction: "RDFSBASEQ (BX)"}, + {goarch: "amd64", instruction: "RDGSBASEL X0"}, + {goarch: "amd64", instruction: "RDGSBASEQ"}, + {goarch: "amd64", instruction: "WRFSBASEL $1"}, + {goarch: "amd64", instruction: "WRFSBASEQ (BX)"}, + {goarch: "amd64", instruction: "WRGSBASEL X0"}, + {goarch: "amd64", instruction: "WRGSBASEQ.Z AX"}, + } + for _, op := range []string{ + "RDFSBASEQ", "RDGSBASEQ", "WRFSBASEQ", "WRGSBASEQ", + } { + tests = append(tests, struct { + goarch string + instruction string + }{goarch: "386", instruction: op + " AX"}) + } + for _, test := range tests { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "$", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's segment-base tables", test.instruction) + } + }) + } +} diff --git a/amd64_lower_segment_query.go b/amd64_lower_segment_query.go new file mode 100644 index 00000000..d9f46ce3 --- /dev/null +++ b/amd64_lower_segment_query.go @@ -0,0 +1,151 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64SegmentQueryKind uint8 + +const ( + amd64SegmentQueryAccessRights amd64SegmentQueryKind = iota + amd64SegmentQueryLimit + amd64SegmentQueryReadable + amd64SegmentQueryWritable +) + +type amd64SegmentQuerySpec struct { + kind amd64SegmentQueryKind + bits int +} + +// amd64SegmentQuerySpecs is the complete Go 1.27 LAR/LSL/VERR/VERW grammar. +// The table records only query kind and optional destination width; all four +// families share one selector-source parser and one exact lowering mechanism. +var amd64SegmentQuerySpecs = map[Op]amd64SegmentQuerySpec{ + "LARW": {kind: amd64SegmentQueryAccessRights, bits: 16}, + "LARL": {kind: amd64SegmentQueryAccessRights, bits: 32}, + "LARQ": {kind: amd64SegmentQueryAccessRights, bits: 64}, + "LSLW": {kind: amd64SegmentQueryLimit, bits: 16}, + "LSLL": {kind: amd64SegmentQueryLimit, bits: 32}, + "LSLQ": {kind: amd64SegmentQueryLimit, bits: 64}, + "VERR": {kind: amd64SegmentQueryReadable}, + "VERW": {kind: amd64SegmentQueryWritable}, +} + +type amd64SegmentQueryForm struct { + selector Operand + destination Reg +} + +func (c *amd64Ctx) lowerSegmentQuery(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64SegmentQuerySpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && spec.bits == 64 { + return true, false, fmt.Errorf("386 %s is absent from Go 1.27's 32-bit encoding table: %q", baseOp, ins.Raw) + } + form, err := c.parseSegmentQueryForm(baseOp, spec, ins) + if err != nil { + return true, false, err + } + return c.emitSegmentQuery(spec, form) +} + +func (c *amd64Ctx) parseSegmentQueryForm(op string, spec amd64SegmentQuerySpec, ins Instr) (amd64SegmentQueryForm, error) { + var form amd64SegmentQueryForm + wantArgs := 2 + if spec.bits == 0 { + wantArgs = 1 + } + if len(ins.Args) != wantArgs { + if wantArgs == 1 { + return form, fmt.Errorf("%s %s expects one selector source: %q", c.goarch, op, ins.Raw) + } + return form, fmt.Errorf("%s %s expects selector source and GP destination: %q", c.goarch, op, ins.Raw) + } + selector := ins.Args[0] + if selector.Kind == OpReg { + if !isX86YrlRegisterForArch(selector.Reg, c.goarch) { + return form, fmt.Errorf("%s %s selector register is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(selector) { + return form, fmt.Errorf("%s %s selector must be a GP register or memory: %q", c.goarch, op, ins.Raw) + } + if selector.Kind == OpMem && !x86MemoryRegistersValidForArch(selector.Mem, c.goarch) { + return form, fmt.Errorf("%s %s selector address uses an out-of-range register: %q", c.goarch, op, ins.Raw) + } + form.selector = selector + if wantArgs == 1 { + return form, nil + } + destination := ins.Args[1] + if destination.Kind != OpReg || !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return form, fmt.Errorf("%s %s destination must be a Go 1.27 Yrl register: %q", c.goarch, op, ins.Raw) + } + form.destination = destination.Reg + return form, nil +} + +func (c *amd64Ctx) emitSegmentQuery(spec amd64SegmentQuerySpec, form amd64SegmentQueryForm) (bool, bool, error) { + selector, err := c.evalIntSized(form.selector, I16) + if err != nil { + return true, false, err + } + if spec.bits == 0 { + mnemonic := "verr" + if spec.kind == amd64SegmentQueryWritable { + mnemonic = "verw" + } + status := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i8 asm sideeffect %q, %q(i16 %s)\n", + status, mnemonic+" $1; sete $0", "=q,r,~{dirflag},~{fpsr},~{flags}", selector) + c.storeSegmentQueryZF("%" + status) + return true, false, nil + } + + typ := amd64IntegerTypeForBits(spec.bits) + previousDestination, err := c.evalIntSized(Operand{Kind: OpReg, Reg: form.destination}, typ) + if err != nil { + return true, false, err + } + + // Intel specifies that a failed descriptor check clears ZF but leaves the + // destination unchanged. Constraint 0 therefore ties the old destination + // value to the result instead of declaring a write-only output. SETE does + // not alter flags, so the second result captures the instruction's ZF while + // the translator's other virtual flag slots remain unchanged. + result := c.newTmp() + mnemonic := "lar" + if spec.kind == amd64SegmentQueryLimit { + mnemonic = "lsl" + } + width := map[int]string{16: "w", 32: "l", 64: "q"}[spec.bits] + assembly := mnemonic + width + " $3, $0; sete $1" + fmt.Fprintf(c.b, " %%%s = call { %s, i8 } asm sideeffect %q, %q(%s %s, i16 %s)\n", + result, typ, assembly, "=r,=q,0,r,~{dirflag},~{fpsr},~{flags}", typ, previousDestination, selector) + value := c.newTmp() + status := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue { %s, i8 } %%%s, 0\n", value, typ, result) + fmt.Fprintf(c.b, " %%%s = extractvalue { %s, i8 } %%%s, 1\n", status, typ, result) + c.storeSegmentQueryZF("%" + status) + if err := c.storeRegSized(form.destination, typ, "%"+value); err != nil { + return true, false, err + } + return true, false, nil +} + +func (c *amd64Ctx) storeSegmentQueryZF(status string) { + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ne i8 %s, 0\n", zero, status) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", zero, c.flagsZSlot) +} diff --git a/amd64_lower_segment_query_test.go b/amd64_lower_segment_query_test.go new file mode 100644 index 00000000..0ef04889 --- /dev/null +++ b/amd64_lower_segment_query_test.go @@ -0,0 +1,290 @@ +package plan9asm + +import ( + "reflect" + "runtime" + "sort" + "strings" + "testing" +) + +func TestAMD64SegmentQueryGrammarIsComplete(t *testing.T) { + got := make([]string, 0, len(amd64SegmentQuerySpecs)) + for op := range amd64SegmentQuerySpecs { + got = append(got, string(op)) + } + sort.Strings(got) + want := []string{"LARL", "LARQ", "LARW", "LSLL", "LSLQ", "LSLW", "VERR", "VERW"} + if !reflect.DeepEqual(got, want) { + t.Fatalf("segment-query grammar opcodes = %v, want %v", got, want) + } + for op, want := range map[Op]amd64SegmentQuerySpec{ + "LARW": {kind: amd64SegmentQueryAccessRights, bits: 16}, + "LARL": {kind: amd64SegmentQueryAccessRights, bits: 32}, + "LARQ": {kind: amd64SegmentQueryAccessRights, bits: 64}, + "LSLW": {kind: amd64SegmentQueryLimit, bits: 16}, + "LSLL": {kind: amd64SegmentQueryLimit, bits: 32}, + "LSLQ": {kind: amd64SegmentQueryLimit, bits: 64}, + "VERR": {kind: amd64SegmentQueryReadable}, + "VERW": {kind: amd64SegmentQueryWritable}, + } { + if got := amd64SegmentQuerySpecs[op]; got != want { + t.Errorf("segment-query grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86SegmentQueryCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := `TEXT segmentqueryforms(SB),$0-0 + LARW AX, DX + LARW 2(BX), CX + LARL CX, AX + LARL 4(BX), DX + LSLW DX, CX + LSLW 6(BX), AX + LSLL AX, DX + LSLL 8(BX), CX +` + if target.goarch == "386" { + source += "\tLARW AX, SP\n\tLARL AX, SP\n\tLSLW AX, SP\n\tLSLL AX, SP\n" + } + if target.goarch == "amd64" { + source += ` LARW R11, R12 + LARW 10(R13), R14 + LARQ R11, R12 + LARQ 12(R13), R14 + LSLW R11, R12 + LSLW 14(R13), R14 + LSLQ R11, R12 + LSLQ 16(R13), R14 +` + } + source += "\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"segmentqueryforms": {Name: "segmentqueryforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "segment-query-"+target.name+".ll", "segment-query-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86SegmentQueryRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "LARW $1, AX"}, + {goarch: "amd64", instruction: "LARL AX, (BX)"}, + {goarch: "amd64", instruction: "LSLQ X0, AX"}, + {goarch: "amd64", instruction: "LSLW AX, X0"}, + {goarch: "amd64", instruction: "LARW.Z AX, DX"}, + {goarch: "386", instruction: "LARQ AX, DX"}, + {goarch: "386", instruction: "LSLQ AX, DX"}, + {goarch: "386", instruction: "LARW R11, AX"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "$", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's segment-query tables", test.instruction) + } + }) + } +} + +func TestTranslateX86SegmentValidationCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + high := "DI" + if target.goarch == "amd64" { + high = "R11" + } + source := "TEXT segmentvalidationforms(SB),$0-0\n" + + "\tVERR AX\n\tVERR (BX)\n\tVERR " + high + "\n" + + "\tVERW DX\n\tVERW 2(BX)\n\tVERW " + high + "\n\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"segmentvalidationforms": {Name: "segmentvalidationforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "segment-validation-"+target.name+".ll", "segment-validation-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86SegmentValidationRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "VERR $1"}, + {goarch: "amd64", instruction: "VERW X0"}, + {goarch: "amd64", instruction: "VERR AX, DX"}, + {goarch: "amd64", instruction: "VERW.Z AX"}, + {goarch: "386", instruction: "VERR R11"}, + {goarch: "386", instruction: "VERW (R11)"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "$", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's segment-validation table", test.instruction) + } + }) + } +} + +func TestAMD64SegmentQueryRuntimeSemantics(t *testing.T) { + if runtime.GOARCH != "amd64" { + // Rosetta advertises amd64 execution but raises SIGILL for LAR/LSL. + // Object compilation remains covered above; execute the architectural + // descriptor checks only on native amd64 hardware. + t.Skip("LAR/LSL runtime semantics require native amd64 hardware") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT segmentquerysemantics(SB),NOSPLIT,$0-16 + MOVQ selector+0(FP), AX + MOVQ out+8(FP), DI + MOVQ $0x1122334455667788, CX + LARQ AX, CX + MOVQ CX, 0(DI) + SETEQ 8(DI) + MOVQ $0x2233445566778899, CX + XORQ AX, AX + LARQ AX, CX + MOVQ CX, 16(DI) + SETEQ 24(DI) + MOVQ selector+0(FP), AX + MOVQ $0x33445566778899aa, DX + LSLQ AX, DX + MOVQ DX, 32(DI) + SETEQ 40(DI) + MOVQ $0x445566778899aabb, DX + XORQ AX, AX + LSLQ AX, DX + MOVQ DX, 48(DI) + SETEQ 56(DI) + MOVQ selector+0(FP), AX + STC + VERR AX + SETEQ 57(DI) + SETCS 58(DI) + VERW AX + SETEQ 59(DI) + XORQ AX, AX + VERR AX + SETEQ 60(DI) + VERW AX + SETEQ 61(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"segmentquerysemantics": { + Name: "segmentquerysemantics", Args: []LLVMType{I64, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void segmentquerysemantics(uint64_t, uint8_t *); +static uint64_t load64(const uint8_t *p) { uint64_t v; memcpy(&v, p, 8); return v; } +int main(void) { + uint16_t cs; + uint8_t out[64] = {0}; + __asm__ volatile ("mov %%cs,%0" : "=r"(cs)); + segmentquerysemantics(cs, out); + if (out[8] != 1 || out[40] != 1) return 10; + if (out[24] != 0 || out[56] != 0) return 11; + if (load64(out + 16) != UINT64_C(0x2233445566778899)) return 12; + if (load64(out + 48) != UINT64_C(0x445566778899aabb)) return 13; + if (out[57] != 1 || out[58] != 1) return 14; + if (out[59] != 0 || out[60] != 0 || out[61] != 0) return 15; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "segment_query_semantics", triple, ir, mainC, nil) +} diff --git a/amd64_lower_segment_register.go b/amd64_lower_segment_register.go new file mode 100644 index 00000000..99c3db24 --- /dev/null +++ b/amd64_lower_segment_register.go @@ -0,0 +1,107 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *amd64Ctx) lowerSegmentRegisterMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + if (baseOp != "MOVW" && baseOp != "MOVL" && baseOp != "MOVQ") || len(ins.Args) != 2 { + return false, false, nil + } + sourceSegment := x86SegmentRegisterOperand(ins.Args[0]) + destinationSegment := x86SegmentRegisterOperand(ins.Args[1]) + if !sourceSegment && !destinationSegment { + return false, false, nil + } + if baseOp != "MOVW" { + return true, false, fmt.Errorf("%s segment-register moves use MOVW in Go 1.27's ymovtab: %q", c.goarch, ins.Raw) + } + if !x86SegmentMoveSuffixAccepted(rawOp) { + return true, false, fmt.Errorf("%s segment-register MOVW has an invalid x86 suffix: %q", c.goarch, ins.Raw) + } + if sourceSegment == destinationSegment { + return true, false, fmt.Errorf("%s MOVW segment-register form expects exactly one segment register: %q", c.goarch, ins.Raw) + } + if destinationSegment { + source := ins.Args[0] + if source.Kind == OpReg { + if !isX86YrlRegisterForArch(source.Reg, c.goarch) { + return true, false, fmt.Errorf("%s MOVW to a segment register expects a Yml source: %q", c.goarch, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s MOVW to a segment register expects a Yml source: %q", c.goarch, ins.Raw) + } + value, err := c.evalIntSized(source, I16) + if err != nil { + return true, false, err + } + return true, false, c.storeX86SegmentSelector(ins.Args[1].Reg, value) + } + + destination := ins.Args[1] + if destination.Kind == OpReg { + if !isX86YrlRegisterForArch(destination.Reg, c.goarch) { + return true, false, fmt.Errorf("%s MOVW from a segment register expects a Yml destination: %q", c.goarch, ins.Raw) + } + } else if !isAMD64MemoryOperand(destination) { + return true, false, fmt.Errorf("%s MOVW from a segment register expects a Yml destination: %q", c.goarch, ins.Raw) + } + call := c.loadX86SegmentSelector(ins.Args[0].Reg) + if destination.Kind == OpReg { + return true, false, c.storeRegSized(destination.Reg, I32, call) + } + selector := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i32 %s to i16\n", selector, call) + return true, false, c.storeScalarIntegerOperand(destination, I16, "%"+selector) +} + +func (c *amd64Ctx) loadX86SegmentSelector(segment Reg) string { + call := c.newTmp() + assembly := fmt.Sprintf("movl %%%s, ${0:k}", strings.ToLower(string(segment))) + fmt.Fprintf(c.b, " %%%s = call i32 asm sideeffect %q, %q()\n", + call, assembly, "=r,~{memory},~{dirflag},~{fpsr},~{flags}") + return "%" + call +} + +func (c *amd64Ctx) storeX86SegmentSelector(segment Reg, selector string) error { + assembly := fmt.Sprintf("movw $0, %%%s", strings.ToLower(string(segment))) + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(i16 %s)\n", + assembly, "r,~{memory},~{dirflag},~{fpsr},~{flags}", selector) + return nil +} + +func x86SegmentMoveSuffixAccepted(rawOp string) bool { + if rawOp == "MOVW" { + return true + } + suffix := strings.TrimPrefix(rawOp, "MOVW.") + switch suffix { + case "Z", "SAE", "SAE.Z", + "RN_SAE", "RZ_SAE", "RD_SAE", "RU_SAE", + "RN_SAE.Z", "RZ_SAE.Z", "RD_SAE.Z", "RU_SAE.Z", + "BCST", "BCST.Z": + // Go 1.27's ymovtab path accepts every syntactically valid x86 suffix + // here and emits the same 8C/8E bytes. Preserve that compatibility. + return true + default: + return false + } +} + +func x86SegmentRegisterOperand(operand Operand) bool { + if operand.Kind != OpReg { + return false + } + switch operand.Reg { + case ES, CS, SS, DS, FS, GS: + return true + default: + return false + } +} diff --git a/amd64_lower_segment_register_test.go b/amd64_lower_segment_register_test.go new file mode 100644 index 00000000..96f38a68 --- /dev/null +++ b/amd64_lower_segment_register_test.go @@ -0,0 +1,114 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86SegmentRegisterCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT segmentregisterforms(SB),$0-0\n") + for _, segment := range []string{"ES", "CS", "SS", "DS", "FS", "GS"} { + fmt.Fprintf(&source, "\tMOVW AX, %s\n", segment) + fmt.Fprintf(&source, "\tMOVW %s, AX\n", segment) + fmt.Fprintf(&source, "\tMOVW 8(BX), %s\n", segment) + fmt.Fprintf(&source, "\tMOVW %s, 16(BX)\n", segment) + } + for _, suffix := range []string{ + "Z", "SAE", "SAE.Z", + "RN_SAE", "RZ_SAE", "RD_SAE", "RU_SAE", + "RN_SAE.Z", "RZ_SAE.Z", "RD_SAE.Z", "RU_SAE.Z", + "BCST", "BCST.Z", + } { + fmt.Fprintf(&source, "\tMOVW.%s AX, DS\n", suffix) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "segmentregisterforms": {Name: "segmentregisterforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "segment-register-"+target.name+".ll", "segment-register-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86SegmentRegisterRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "MOVL AX, DS", + "MOVQ AX, DS", + "MOVW AL, DS", + "MOVW X0, DS", + "MOVW DS, X0", + "MOVW DS, FS", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + for _, goarch := range []string{"386", "amd64"} { + requireX86GoAssemblerResult(t, goarch, "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + triple := "i386-unknown-linux-gnu" + if goarch == "amd64" { + triple = "x86_64-unknown-linux-gnu" + } + assertX86SegmentRegisterRejected(t, goarch, triple, instruction) + } + }) + } +} + +func assertX86SegmentRegisterRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's segment-register MOVW table for %s", instruction, goarch) + } +} + +func TestX86SegmentRegistersDoNotShadowARM64Conditions(t *testing.T) { + file, err := Parse(ArchARM64, "TEXT select(SB),$0-0\n\tCSEL CS, R11, R3, R3\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if len(file.Funcs) != 1 || len(file.Funcs[0].Instrs) < 2 || len(file.Funcs[0].Instrs[1].Args) != 4 { + t.Fatalf("unexpected ARM64 parse: %+v", file) + } + condition := file.Funcs[0].Instrs[1].Args[0] + if condition.Kind == OpReg { + t.Fatalf("ARM64 CS condition was parsed as an x86 segment register: %+v", condition) + } +} diff --git a/amd64_lower_set.go b/amd64_lower_set.go new file mode 100644 index 00000000..5482a76f --- /dev/null +++ b/amd64_lower_set.go @@ -0,0 +1,71 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerConditionalSet implements the complete Go 1.27 SETcc family. All 16 +// names use yscond, whose single operand is the byte-register-or-memory Ymb +// class. +func (c *amd64Ctx) lowerConditionalSet(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + switch baseOp { + case "SETCC", "SETCS", "SETEQ", "SETGE", "SETGT", "SETHI", "SETLE", "SETLS", + "SETLT", "SETMI", "SETNE", "SETOC", "SETOS", "SETPC", "SETPL", "SETPS": + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 1 { + return true, false, fmt.Errorf("amd64 %s expects one Ymb destination: %q", baseOp, ins.Raw) + } + dst := ins.Args[0] + if dst.Kind == OpReg && !isGoYmbRegisterForArch(dst.Reg, c.goarch) { + return true, false, fmt.Errorf("amd64 %s register is outside Go 1.27's Ymb class for %s: %q", baseOp, c.goarch, ins.Raw) + } + if dst.Kind != OpReg && !isAMD64MemoryOperand(dst) { + return true, false, fmt.Errorf("amd64 %s expects a Ymb register or memory destination: %q", baseOp, ins.Raw) + } + condition, err := c.x86Condition(strings.TrimPrefix(baseOp, "SET")) + if err != nil { + return true, false, err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i8 1, i8 0\n", value, condition) + if err := c.storeConditionalSetByte(dst, "%"+value); err != nil { + return true, false, err + } + return true, false, nil +} + +func (c *amd64Ctx) storeConditionalSetByte(dst Operand, value string) error { + switch dst.Kind { + case OpReg: + return c.storeRegSized(dst.Reg, I8, value) + case OpMem: + ptr, ptrType, err := c.ptrFromMem(dst.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store i8 %s, %s %s, align 1\n", value, ptrType, ptr) + return nil + case OpSym: + ptr, err := c.ptrFromSB(dst.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store i8 %s, ptr %s, align 1\n", value, ptr) + return nil + case OpFP: + return c.storeFPResult(dst.FPOffset, I8, value) + default: + return fmt.Errorf("expected Ymb destination, got %s", dst.String()) + } +} diff --git a/amd64_lower_shiftrotate.go b/amd64_lower_shiftrotate.go new file mode 100644 index 00000000..34853d6b --- /dev/null +++ b/amd64_lower_shiftrotate.go @@ -0,0 +1,341 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerScalarShiftRotate implements the complete Go 1.27 yshb/yshl family: +// RCL/RCR/ROL/ROR/SAR/SAL/SHL/SHR at B/W/L/Q widths, plus the special +// three-operand SHL/SHR W/L/Q double-shift table. +func (c *amd64Ctx) lowerScalarShiftRotate(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + stem, bits, recognized := amd64ScalarShiftRotateProperties(baseOp) + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && bits == 64 { + return true, false, fmt.Errorf("386 %s is illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + if len(ins.Args) == 3 { + if (stem != "SHL" && stem != "SHR") || bits == 8 { + return true, false, fmt.Errorf("%s %s has no three-operand form in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + return c.lowerScalarDoubleShift(baseOp, stem == "SHL", bits, ins) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects count, destination: %q", c.goarch, baseOp, ins.Raw) + } + count, err := c.scalarShiftCount(ins.Args[0], bits, false) + if err != nil { + return true, false, fmt.Errorf("%s %s count: %w", c.goarch, baseOp, err) + } + dst := ins.Args[1] + if !c.scalarShiftDestination(dst, bits) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Ymb/Yml class: %q", c.goarch, baseOp, ins.Raw) + } + ty := amd64IntegerTypeForBits(bits) + value, err := c.evalIntSized(dst, ty) + if err != nil { + return true, false, err + } + var result string + if stem == "RCL" || stem == "RCR" { + result = c.emitScalarCarryRotate(stem, bits, value, count) + } else { + result = c.emitScalarShiftRotate(stem, bits, value, count) + } + if err := c.storeScalarIntegerOperand(dst, ty, result); err != nil { + return true, false, err + } + return true, false, nil +} + +func amd64ScalarShiftRotateProperties(op string) (stem string, bits int, ok bool) { + switch op { + case "RCLB", "RCRB", "ROLB", "RORB", "SARB", "SALB", "SHLB", "SHRB": + bits = 8 + case "RCLW", "RCRW", "ROLW", "RORW", "SARW", "SALW", "SHLW", "SHRW": + bits = 16 + case "RCLL", "RCRL", "ROLL", "RORL", "SARL", "SALL", "SHLL", "SHRL": + bits = 32 + case "RCLQ", "RCRQ", "ROLQ", "RORQ", "SARQ", "SALQ", "SHLQ", "SHRQ": + bits = 64 + default: + return "", 0, false + } + return op[:len(op)-1], bits, true +} + +func (c *amd64Ctx) emitScalarCarryRotate(stem string, bits int, value, count64 string) string { + // Model RCL/RCR as a rotate of the destination plus CF. Intel masks the + // count to five (six for Q) bits first; scalarShiftCount already did that. + // B/W then reduce it modulo 9/17, while L/Q values are already below 33/65. + totalBits := bits + 1 + effective64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = urem i64 %s, %d\n", effective64, count64, totalBits) + + wideType := LLVMType(fmt.Sprintf("i%d", totalBits)) + valueWide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", valueWide, amd64IntegerTypeForBits(bits), value, wideType) + oldCF := c.loadFlag(c.flagsCFSlot) + cfWide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %s to %s\n", cfWide, oldCF, wideType) + cfHigh := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl %s %%%s, %d\n", cfHigh, wideType, cfWide, bits) + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %%%s\n", combined, wideType, valueWide, cfHigh) + + toWideCount := func(value string) string { + converted := c.newTmp() + if totalBits <= 64 { + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to %s\n", converted, value, wideType) + } else { + fmt.Fprintf(c.b, " %%%s = zext i64 %s to %s\n", converted, value, wideType) + } + return "%" + converted + } + effective := toWideCount("%" + effective64) + inverseRaw := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i64 %d, %%%s\n", inverseRaw, totalBits, effective64) + inverse64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = urem i64 %%%s, %d\n", inverse64, inverseRaw, totalBits) + inverse := toWideCount("%" + inverse64) + + left := c.newTmp() + right := c.newTmp() + if stem == "RCL" { + fmt.Fprintf(c.b, " %%%s = shl %s %%%s, %s\n", left, wideType, combined, effective) + fmt.Fprintf(c.b, " %%%s = lshr %s %%%s, %s\n", right, wideType, combined, inverse) + } else { + fmt.Fprintf(c.b, " %%%s = lshr %s %%%s, %s\n", right, wideType, combined, effective) + fmt.Fprintf(c.b, " %%%s = shl %s %%%s, %s\n", left, wideType, combined, inverse) + } + rotated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %%%s\n", rotated, wideType, left, right) + + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", result, wideType, rotated, amd64IntegerTypeForBits(bits)) + cfShifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %%%s, %d\n", cfShifted, wideType, rotated, bits) + newCF := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to i1\n", newCF, wideType, cfShifted) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", newCF, c.flagsCFSlot) + + // OF is defined only for a one-bit rotate. Preserve its prior value for + // the architecturally undefined cases, including an effective count of 0. + msbShifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %%%s, %d\n", msbShifted, amd64IntegerTypeForBits(bits), result, bits-1) + msb := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to i1\n", msb, amd64IntegerTypeForBits(bits), msbShifted) + definedOF := c.newTmp() + if stem == "RCL" { + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, %%%s\n", definedOF, msb, newCF) + } else { + nextShifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %%%s, %d\n", nextShifted, amd64IntegerTypeForBits(bits), result, bits-2) + nextMSB := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to i1\n", nextMSB, amd64IntegerTypeForBits(bits), nextShifted) + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, %%%s\n", definedOF, msb, nextMSB) + } + isOne := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i64 %%%s, 1\n", isOne, effective64) + oldOF := c.loadFlag(c.flagsOFSlot) + newOF := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i1 %%%s, i1 %s\n", newOF, isOne, definedOF, oldOF) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", newOF, c.flagsOFSlot) + return "%" + result +} + +func (c *amd64Ctx) scalarShiftCount(count Operand, bits int, doubleShift bool) (string, error) { + mask := int64(31) + if bits == 64 { + mask = 63 + } + switch count.Kind { + case OpImm: + if doubleShift { + if count.Imm < -128 || count.Imm > 127 { + return "", fmt.Errorf("immediate is outside Go 1.27's signed-imm8 class") + } + } else if count.Imm < 0 || count.Imm > 255 { + return "", fmt.Errorf("immediate is outside Go 1.27's unsigned-imm8 class") + } + return fmt.Sprintf("%d", count.Imm&mask), nil + case OpReg: + if count.Reg != CL && count.Reg != CX { + return "", fmt.Errorf("register count must be CL or CX") + } + value, err := c.loadReg(count.Reg) + if err != nil { + return "", err + } + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %d\n", masked, value, mask) + return "%" + masked, nil + default: + return "", fmt.Errorf("count must be an immediate, CL, or CX") + } +} + +func (c *amd64Ctx) scalarShiftDestination(dst Operand, bits int) bool { + if dst.Kind == OpReg { + if bits == 8 { + return isGoYmbRegisterForArch(dst.Reg, c.goarch) + } + return isX86YrlRegisterForArch(dst.Reg, c.goarch) + } + return isAMD64MemoryOperand(dst) +} + +func (c *amd64Ctx) emitScalarShiftRotate(stem string, bits int, value, count64 string) string { + ty := amd64IntegerTypeForBits(bits) + amount64 := count64 + if stem == "ROL" || stem == "ROR" { + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %d\n", masked, count64, bits-1) + amount64 = "%" + masked + } + amount := amount64 + if bits != 64 { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to %s\n", truncated, amount64, ty) + amount = "%" + truncated + } + + if stem == "ROL" || stem == "ROR" { + inverseNeg := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s 0, %s\n", inverseNeg, ty, amount) + inverse := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %d\n", inverse, ty, inverseNeg, bits-1) + left := c.newTmp() + right := c.newTmp() + if stem == "ROL" { + fmt.Fprintf(c.b, " %%%s = shl %s %s, %s\n", left, ty, value, amount) + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %%%s\n", right, ty, value, inverse) + } else { + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %s\n", right, ty, value, amount) + fmt.Fprintf(c.b, " %%%s = shl %s %s, %%%s\n", left, ty, value, inverse) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %%%s\n", result, ty, left, right) + return "%" + result + } + + inRange := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i64 %s, %d\n", inRange, count64, bits) + safe64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %s, i64 %d\n", safe64, inRange, count64, bits-1) + safe := "%" + safe64 + if bits != 64 { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to %s\n", truncated, safe64, ty) + safe = "%" + truncated + } + shifted := c.newTmp() + switch stem { + case "SHL", "SAL": + fmt.Fprintf(c.b, " %%%s = shl %s %s, %s\n", shifted, ty, value, safe) + case "SHR": + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %s\n", shifted, ty, value, safe) + case "SAR": + fmt.Fprintf(c.b, " %%%s = ashr %s %s, %s\n", shifted, ty, value, safe) + return "%" + shifted + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s 0\n", result, inRange, ty, shifted, ty) + return "%" + result +} + +func (c *amd64Ctx) lowerScalarDoubleShift(baseOp string, left bool, bits int, ins Instr) (bool, bool, error) { + count, err := c.scalarShiftCount(ins.Args[0], bits, true) + if err != nil { + return true, false, fmt.Errorf("%s %s count: %w", c.goarch, baseOp, err) + } + if ins.Args[1].Kind != OpReg || !isX86YrlRegisterForArch(ins.Args[1].Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s source must be a Yrl GP register: %q", c.goarch, baseOp, ins.Raw) + } + if !c.scalarShiftDestination(ins.Args[2], bits) { + return true, false, fmt.Errorf("%s %s destination must be a Yml GP register or memory: %q", c.goarch, baseOp, ins.Raw) + } + ty := amd64IntegerTypeForBits(bits) + source, err := c.evalIntSized(ins.Args[1], ty) + if err != nil { + return true, false, err + } + destination, err := c.evalIntSized(ins.Args[2], ty) + if err != nil { + return true, false, err + } + + // W double shifts mask the hardware count to five bits, leaving counts + // 16-31 architecturally undefined. Reduce that undefined region modulo the + // lane width so generated LLVM never shifts by the type width. + effective64 := count + if bits == 16 { + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, 15\n", masked, count) + effective64 = "%" + masked + } + effective := effective64 + if bits != 64 { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to %s\n", truncated, effective64, ty) + effective = "%" + truncated + } + inverseNeg := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s 0, %s\n", inverseNeg, ty, effective) + inverse := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %d\n", inverse, ty, inverseNeg, bits-1) + first := c.newTmp() + second := c.newTmp() + if left { + fmt.Fprintf(c.b, " %%%s = shl %s %s, %s\n", first, ty, destination, effective) + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %%%s\n", second, ty, source, inverse) + } else { + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %s\n", first, ty, destination, effective) + fmt.Fprintf(c.b, " %%%s = shl %s %s, %%%s\n", second, ty, source, inverse) + } + merged := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %%%s\n", merged, ty, first, second) + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, 0\n", zero, ty, effective) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %s, %s %%%s\n", result, zero, ty, destination, ty, merged) + if err := c.storeScalarIntegerOperand(ins.Args[2], ty, "%"+result); err != nil { + return true, false, err + } + return true, false, nil +} + +func (c *amd64Ctx) storeScalarIntegerOperand(dst Operand, ty LLVMType, value string) error { + switch dst.Kind { + case OpReg: + return c.storeRegSized(dst.Reg, ty, value) + case OpMem: + ptr, ptrType, err := c.ptrFromMem(dst.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, %s %s, align 1\n", ty, value, ptrType, ptr) + return nil + case OpSym: + ptr, err := c.ptrFromSB(dst.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, ptr %s, align 1\n", ty, value, ptr) + return nil + case OpFP: + return c.storeFPResult(dst.FPOffset, ty, value) + default: + return fmt.Errorf("expected GP register or memory destination, got %s", dst.String()) + } +} diff --git a/amd64_lower_shuffle_blocks.go b/amd64_lower_shuffle_blocks.go new file mode 100644 index 00000000..56e51629 --- /dev/null +++ b/amd64_lower_shuffle_blocks.go @@ -0,0 +1,136 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var amd64Shuffle128BitBlockLaneBits = map[string]int{ + "VSHUFF32X4": 32, + "VSHUFI32X4": 32, + "VSHUFF64X2": 64, + "VSHUFI64X2": 64, +} + +// lowerShuffle128BitBlocks implements the complete Go 1.27 _yvshuff32x4 +// table. Floating and integer spellings have identical bit-level behavior. +func (c *amd64Ctx) lowerShuffle128BitBlocks(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + laneBits, ok := amd64Shuffle128BitBlockLaneBits[baseOp] + if !ok { + return false, false, nil + } + suffixes, err := amd64ParseTwoSourcePermuteSuffixes(rawOp, baseOp) + if err != nil { + return true, false, fmt.Errorf("%w: %q", err, ins.Raw) + } + if len(ins.Args) != 4 && len(ins.Args) != 5 { + return true, false, fmt.Errorf("amd64 %s expects $imm8, first source, second source, [K mask,] destination: %q", baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("amd64 %s expects an unsigned-byte immediate: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 5 + if masked && c.goarch == "386" { + return true, false, fmt.Errorf("386 %s masked form exceeds the Go assembler frontend's operand limit: %q", baseOp, ins.Raw) + } + if suffixes.zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + byteWidth := 0 + if destination.Kind == OpReg { + byteWidth = amd64VectorByteWidth(destination.Reg) + } + if byteWidth != 32 && byteWidth != 64 || !c.isGoPackedVectorMoveRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s expects an in-range Y or Z destination: %q", baseOp, ins.Raw) + } + second := ins.Args[2] + if !c.isGoPackedVectorMoveRegister(second, byteWidth) { + return true, false, fmt.Errorf("amd64 %s second source must match the destination width: %q", baseOp, ins.Raw) + } + first := ins.Args[1] + if first.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(first, byteWidth) { + return true, false, fmt.Errorf("amd64 %s first source register must match the destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 %s first source must be a matching vector register or memory: %q", baseOp, ins.Raw) + } + if suffixes.broadcast && !isAMD64MemoryOperand(first) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory first source: %q", baseOp, ins.Raw) + } + + mask := "" + if masked { + maskArg := ins.Args[3] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, validMask := amd64ParseKReg(maskArg.Reg) + if !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + firstValue, err := c.loadPackedCompareLanes(first, byteWidth, laneBits, suffixes.broadcast) + if err != nil { + return true, false, err + } + secondValue, err := c.loadPackedCompareLanes(second, byteWidth, laneBits, false) + if err != nil { + return true, false, err + } + lanes := byteWidth * 8 / laneBits + computed := c.emitShuffle128BitBlocks(lanes, laneBits, firstValue, secondValue, uint8(ins.Args[0].Imm)) + if masked { + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + computed = amd64ApplyIntegerLaneMask(c, lanes, laneBits, computed, old, mask, suffixes.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, computed, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitShuffle128BitBlocks(lanes, laneBits int, firstPlan9, secondPlan9 string, immediate uint8) string { + blockLanes := 128 / laneBits + blocks := lanes / blockLanes + indices := make([]string, 0, lanes) + for outputBlock := 0; outputBlock < blocks; outputBlock++ { + var sourceBlock int + secondOperandOffset := 0 + if blocks == 2 { + sourceBlock = int(immediate>>outputBlock) & 1 + if outputBlock == 1 { + secondOperandOffset = lanes + } + } else { + sourceBlock = int(immediate>>(2*outputBlock)) & 3 + if outputBlock >= 2 { + secondOperandOffset = lanes + } + } + for lane := 0; lane < blockLanes; lane++ { + indices = append(indices, fmt.Sprintf("i32 %d", secondOperandOffset+sourceBlock*blockLanes+lane)) + } + } + shuffled := c.newTmp() + // The second Plan 9 source is Intel SRC1 and therefore LLVM operand 0; + // the first Plan 9 (r/m) source is Intel SRC2 / LLVM operand 1. + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %s, <%d x i%d> %s, <%d x i32> <%s>\n", + shuffled, lanes, laneBits, secondPlan9, lanes, laneBits, firstPlan9, lanes, strings.Join(indices, ", ")) + return "%" + shuffled +} diff --git a/amd64_lower_shuffle_blocks_test.go b/amd64_lower_shuffle_blocks_test.go new file mode 100644 index 00000000..0c87a9d4 --- /dev/null +++ b/amd64_lower_shuffle_blocks_test.go @@ -0,0 +1,100 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86Shuffle128BitBlocksCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 shares _yvshuff32x4 across the floating and integer D/Q + // spellings. It has Y/Z rows, an unsigned-byte immediate, optional K + // masking/.Z, and scalar broadcast from the first Plan 9 memory source. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastZ := 20 + if target.goarch == "386" { + lastZ = 7 + } + var source strings.Builder + source.WriteString("TEXT shuffle128bitblockforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2"} { + fmt.Fprintf(&source, "\t%s $0, Y1, Y20, Y21\n", op) + fmt.Fprintf(&source, "\t%s $2, 8(AX), Y20, Y21\n", op) + fmt.Fprintf(&source, "\t%s $255, Z1, Z2, Z%d\n", op, lastZ) + fmt.Fprintf(&source, "\t%s.BCST $3, 40(AX), Z2, Z%d\n", op, lastZ) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s $4, Y1, Y20, K1, Y21\n", op) + fmt.Fprintf(&source, "\t%s.Z $5, Z1, Z20, K2, Z21\n", op) + fmt.Fprintf(&source, "\t%s.BCST.Z $6, 104(AX), Z20, K3, Z21\n", op) + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "shuffle128bitblockforms": {Name: "shuffle128bitblockforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "shuffle-128-bit-blocks-"+target.name+".ll", "shuffle-128-bit-blocks-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86Shuffle128BitBlocksRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VSHUFF64X2 $1, X0, X1, X2", + "VSHUFF64X2 $1, Y0, Z1, Z2", + "VSHUFF64X2 $1, Y0, (AX), Y2", + "VSHUFF64X2 $1, Y0, Y1, K0, Y2", + "VSHUFF64X2 $1, Y0, Y1, AX", + "VSHUFF64X2.Z $1, Y0, Y1, Y2", + "VSHUFF64X2.BCST $1, Y0, Y1, Y2", + "VSHUFF64X2.Z.BCST $1, (AX), Y1, K1, Y2", + "VSHUFF64X2 $256, Y0, Y1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86Shuffle128BitBlocksRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + assertX86Shuffle128BitBlocksRejected(t, "386", "i386-unknown-linux-gnu", "VSHUFF64X2 $1, Y0, Y1, K1, Y2") + assertX86Shuffle128BitBlocksRejected(t, "386", "i386-unknown-linux-gnu", "VSHUFF64X2 $1, Z0, Z1, Z8") +} + +func assertX86Shuffle128BitBlocksRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VSHUFF/VSHUFI forms", instruction) + } +} diff --git a/amd64_lower_shuffle_bytes.go b/amd64_lower_shuffle_bytes.go new file mode 100644 index 00000000..70f06682 --- /dev/null +++ b/amd64_lower_shuffle_bytes.go @@ -0,0 +1,159 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedByteShuffle implements all Go 1.27 PSHUFB/VPSHUFB forms. +// VPSHUFB applies the byte shuffle independently to each 128-bit lane; EVEX +// writemasks operate at byte granularity. +func (c *amd64Ctx) lowerPackedByteShuffle(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + switch baseOp { + case "PSHUFB": + return c.lowerLegacyPackedByteShuffle(suffix, ins) + case "VPSHUFB": + return c.lowerVectorPackedByteShuffle(suffix, ins) + default: + return false, false, nil + } +} + +func (c *amd64Ctx) lowerLegacyPackedByteShuffle(suffix string, ins Instr) (bool, bool, error) { + if suffix != "" { + return true, false, fmt.Errorf("%s PSHUFB has no instruction suffixes in Go 1.27's ymshufb table: %q", c.goarch, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg || !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("%s PSHUFB expects X/m128, X: %q", c.goarch, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s PSHUFB source is outside Go 1.27's legacy X class: %q", c.goarch, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s PSHUFB source must be X or memory: %q", c.goarch, ins.Raw) + } + control, err := c.loadPackedCompareBytes(ins.Args[0], 16) + if err != nil { + return true, false, err + } + data, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + result := c.emitPackedByteShuffle(16, data, control) + return true, false, c.storeX(ins.Args[1].Reg, result) +} + +func (c *amd64Ctx) lowerVectorPackedByteShuffle(suffix string, ins Instr) (bool, bool, error) { + zeroing := false + switch suffix { + case "": + case "Z": + zeroing = true + default: + return true, false, fmt.Errorf("%s VPSHUFB suffix is absent from Go 1.27's _yvandnpd table: %q", c.goarch, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s VPSHUFB expects control, data, [K mask,] destination: %q", c.goarch, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 VPSHUFB mask forms exceed the Go assembler frontend's three-operand limit: %q", ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s VPSHUFB zeroing requires a K1-K7 mask: %q", c.goarch, ins.Raw) + } + if masked && !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("%s VPSHUFB masked form expects K1-K7: %q", c.goarch, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s VPSHUFB destination must be X, Y, or Z: %q", c.goarch, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoVPSHUFBRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s VPSHUFB destination is outside Go 1.27's vector-register class: %q", c.goarch, ins.Raw) + } + if !c.isGoVPSHUFBRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s VPSHUFB data source must match the destination width: %q", c.goarch, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoVPSHUFBRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s VPSHUFB control source must match the destination width: %q", c.goarch, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s VPSHUFB control source must be a vector register or memory: %q", c.goarch, ins.Raw) + } + + control, err := c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err != nil { + return true, false, err + } + data, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + result := c.emitPackedByteShuffle(byteWidth, data, control) + if masked { + mask, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + old, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + result = amd64ApplyIntegerLaneMask(c, byteWidth, 8, result, old, mask, zeroing) + } + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, result) +} + +func (c *amd64Ctx) isGoVPSHUFBRegister(arg Operand, byteWidth int) bool { + if !amd64EVEXVectorRegister(arg, byteWidth) { + return false + } + if c.goarch == "386" && byteWidth == 64 { + index, _ := amd64VectorRegisterIndex(arg.Reg, byteWidth) + return index < 8 + } + return true +} + +func (c *amd64Ctx) emitPackedByteShuffle(byteWidth int, data, control string) string { + if byteWidth == 16 { + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %s, <16 x i8> %s)\n", call, data, control) + return "%" + call + } + + parts := make([]string, 0, byteWidth/16) + for lane := 0; lane < byteWidth/16; lane++ { + dataLane := c.newTmp() + controlLane := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i8> %s, <%d x i8> poison, <16 x i32> %s\n", dataLane, byteWidth, data, byteWidth, llvmI32RangeMask(lane*16, 16)) + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i8> %s, <%d x i8> poison, <16 x i32> %s\n", controlLane, byteWidth, control, byteWidth, llvmI32RangeMask(lane*16, 16)) + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %%%s, <16 x i8> %%%s)\n", call, dataLane, controlLane) + parts = append(parts, "%"+call) + } + partWidth := 16 + for len(parts) > 1 { + combined := make([]string, 0, len(parts)/2) + for i := 0; i < len(parts); i += 2 { + joined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i8> %s, <%d x i8> %s, <%d x i32> %s\n", joined, partWidth, parts[i], partWidth, parts[i+1], partWidth*2, llvmI32RangeMask(0, partWidth*2)) + combined = append(combined, "%"+joined) + } + parts = combined + partWidth *= 2 + } + return parts[0] +} diff --git a/amd64_lower_shuffle_bytes_test.go b/amd64_lower_shuffle_bytes_test.go new file mode 100644 index 00000000..80a7728a --- /dev/null +++ b/amd64_lower_shuffle_bytes_test.go @@ -0,0 +1,121 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedByteShuffleCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 uses ymshufb for PSHUFB and _yvandnpd for VPSHUFB. + // The legacy instruction accepts X/m128, X. The vector instruction has + // VEX X/Y forms and EVEX X/Y/Z forms, including K1-K7 merge/zero masks. + // In 386 mode the Go frontend still exposes EVEX X/Y0-31 and Z0-7, but + // cannot express the four-operand mask rows. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast := 15 + zLast := 21 + if target.goarch == "386" { + legacyLast = 7 + zLast = 7 + } + var src strings.Builder + src.WriteString("TEXT packedbyteshuffleforms(SB),NOSPLIT,$0-0\n") + fmt.Fprintf(&src, "\tPSHUFB X0, X%d\n", legacyLast) + fmt.Fprintf(&src, "\tPSHUFB (AX), X%d\n", legacyLast) + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&src, "\tVPSHUFB %s0, %s1, %s2\n", width, width, width) + fmt.Fprintf(&src, "\tVPSHUFB (AX), %s20, %s21\n", width, width) + } + fmt.Fprintf(&src, "\tVPSHUFB Z0, Z1, Z%d\n", zLast) + fmt.Fprintf(&src, "\tVPSHUFB (AX), Z6, Z%d\n", zLast) + if target.goarch == "amd64" { + for _, width := range []string{"X", "Y", "Z"} { + fmt.Fprintf(&src, "\tVPSHUFB %s20, %s21, K1, %s22\n", width, width, width) + fmt.Fprintf(&src, "\tVPSHUFB.Z (AX), %s21, K2, %s22\n", width, width) + } + } + src.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedbyteshuffleforms": {Name: "packedbyteshuffleforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-byte-shuffle-"+target.name+".ll", "packed-byte-shuffle-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedByteShuffleRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PSHUFB.Z X0, X1", + "PSHUFB X0", + "PSHUFB Y0, Y1", + "PSHUFB X0, (AX)", + "VPSHUFB X0, X1", + "VPSHUFB X0, Y1, Y2", + "VPSHUFB X0, X1, (AX)", + "VPSHUFB.BCST (AX), X1, X2", + "VPSHUFB.SAE X0, X1, X2", + "VPSHUFB.Z X0, X1, X2", + "VPSHUFB X0, X1, K0, X2", + "VPSHUFB X0, X1, K1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedByteShuffleRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + + for _, instruction := range []string{ + "PSHUFB X8, X0", + "PSHUFB X0, X8", + "VPSHUFB Z8, Z0, Z1", + "VPSHUFB Z0, Z1, Z8", + "VPSHUFB X0, X1, K1, X2", + "VPSHUFB.Z X0, X1, K1, X2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedByteShuffleRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedByteShuffleRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ymshufb/_yvandnpd forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_shuffle_float.go b/amd64_lower_shuffle_float.go new file mode 100644 index 00000000..41d1aed7 --- /dev/null +++ b/amd64_lower_shuffle_float.go @@ -0,0 +1,213 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedFloatShuffle implements the complete Go 1.27 SHUFPS/SHUFPD +// and VSHUFPS/VSHUFPD operand tables, using integer lanes to preserve bits. +func (c *amd64Ctx) lowerPackedFloatShuffle(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits, vector, recognized := amd64PackedFloatShuffleProperties(baseOp) + if !recognized { + return false, false, nil + } + if !vector { + return c.lowerLegacyPackedFloatShuffle(baseOp, suffix, laneBits, ins) + } + return c.lowerVectorPackedFloatShuffle(baseOp, suffix, laneBits, ins) +} + +func amd64PackedFloatShuffleProperties(op string) (laneBits int, vector, ok bool) { + switch op { + case "SHUFPS": + return 32, false, true + case "SHUFPD": + return 64, false, true + case "VSHUFPS": + return 32, true, true + case "VSHUFPD": + return 64, true, true + default: + return 0, false, false + } +} + +func amd64UnsignedImm8(arg Operand) (uint8, bool) { + if arg.Kind != OpImm || arg.Imm < 0 || arg.Imm > 255 { + return 0, false + } + return uint8(arg.Imm), true +} + +func (c *amd64Ctx) lowerLegacyPackedFloatShuffle(baseOp, suffix string, laneBits int, ins Instr) (bool, bool, error) { + if suffix != "" { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("%s %s expects $u8, X/m128, X: %q", c.goarch, baseOp, ins.Raw) + } + imm, ok := amd64UnsignedImm8(ins.Args[0]) + if !ok { + return true, false, fmt.Errorf("%s %s immediate is outside Go 1.27's unsigned-imm8 class: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[2].Kind != OpReg || !c.isGoLegacyXReg(ins.Args[2].Reg) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[1].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("%s %s source must be X or memory: %q", c.goarch, baseOp, ins.Raw) + } + firstBytes, err := c.loadPackedCompareBytes(ins.Args[1], 16) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + lanes := 128 / laneBits + first := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, secondBytes) + result := c.emitPackedFloatShuffle(laneBits, 16, imm, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, lanes, laneBits, result) + return true, false, c.storeX(ins.Args[2].Reg, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedFloatShuffle(baseOp, suffix string, laneBits int, ins Instr) (bool, bool, error) { + if c.goarch != "amd64" { + return true, false, fmt.Errorf("386 %s exceeds the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("amd64 %s has a suffix absent from its Go 1.27 optab: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 4 && len(ins.Args) != 5 { + return true, false, fmt.Errorf("amd64 %s expects $u8, src1, src2, [K mask,] destination: %q", baseOp, ins.Raw) + } + imm, ok := amd64UnsignedImm8(ins.Args[0]) + if !ok { + return true, false, fmt.Errorf("amd64 %s immediate is outside Go 1.27's unsigned-imm8 class: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 5 + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s zeroing requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects a vector-register destination: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("amd64 %s expects an X, Y, or Z destination: %q", baseOp, ins.Raw) + } + if !amd64EVEXVectorRegister(dstArg, byteWidth) || !amd64EVEXVectorRegister(ins.Args[2], byteWidth) { + return true, false, fmt.Errorf("amd64 %s second source and destination must be same-width vector registers: %q", baseOp, ins.Raw) + } + if broadcast { + if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory first source: %q", baseOp, ins.Raw) + } + } else if ins.Args[1].Kind == OpReg { + if !amd64EVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("amd64 %s first source must match its destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s first source must be a vector register or memory: %q", baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[3]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + var err error + mask, err = c.loadK(ins.Args[3].Reg) + if err != nil { + return true, false, err + } + } + lanes := byteWidth * 8 / laneBits + var first string + var err error + if broadcast { + first, err = c.evalIntSized(ins.Args[1], amd64IntegerTypeForBits(laneBits)) + if err == nil { + first = amd64SplatInteger(c, lanes, laneBits, first) + } + } else { + var firstBytes string + firstBytes, err = c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err == nil { + first = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, firstBytes) + } + } + if err != nil { + return true, false, err + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[2], byteWidth) + if err != nil { + return true, false, err + } + second := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, secondBytes) + result := c.emitPackedFloatShuffle(laneBits, byteWidth, imm, first, second) + if masked { + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPackedFloatShuffle(laneBits, byteWidth int, imm uint8, first, second string) string { + lanes := byteWidth * 8 / laneBits + groupLanes := 128 / laneBits + vecType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + result := "poison" + for lane := 0; lane < lanes; lane++ { + groupBase := lane / groupLanes * groupLanes + position := lane % groupLanes + source := second + selector := 0 + if laneBits == 32 { + selector = int(imm>>(2*position)) & 3 + if position >= 2 { + source = first + } + } else { + selector = int(imm>>lane) & 1 + if position == 1 { + source = first + } + } + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", extracted, vecType, source, groupBase+selector) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %%%s, i32 %d\n", inserted, vecType, result, laneBits, extracted, lane) + result = "%" + inserted + } + return result +} diff --git a/amd64_lower_shuffle_words.go b/amd64_lower_shuffle_words.go new file mode 100644 index 00000000..3b2244e7 --- /dev/null +++ b/amd64_lower_shuffle_words.go @@ -0,0 +1,199 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedWordShuffle implements the complete Go 1.27 PSHUFHW/PSHUFLW +// and VPSHUFHW/VPSHUFLW tables. The selected four-word half is shuffled +// independently in every 128-bit lane; the other half remains unchanged. +func (c *amd64Ctx) lowerPackedWordShuffle(rawOp Op, ins Instr) (ok bool, terminated bool, err error) { + raw := strings.ToUpper(string(rawOp)) + parts := strings.Split(raw, ".") + baseOp := Op(parts[0]) + switch baseOp { + case "PSHUFW", "PSHUFHW", "PSHUFLW", "VPSHUFHW", "VPSHUFLW": + // handled below + default: + return false, false, nil + } + if len(parts) > 2 || len(parts) == 2 && parts[1] != "Z" { + return true, false, fmt.Errorf("amd64 %s has a suffix outside Go 1.27's word-shuffle tables: %q", baseOp, ins.Raw) + } + zeroing := len(parts) == 2 + high := baseOp == "PSHUFHW" || baseOp == "VPSHUFHW" + if baseOp == "PSHUFW" { + if zeroing { + return true, false, fmt.Errorf("%s PSHUFW does not accept instruction suffixes: %q", c.goarch, ins.Raw) + } + if len(ins.Args) != 3 || !amd64SignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("%s PSHUFW expects $signed-imm8, M/m64, M: %q", c.goarch, ins.Raw) + } + source, destination := ins.Args[1], ins.Args[2] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("%s PSHUFW destination must be M0..M7: %q", c.goarch, ins.Raw) + } + if _, ok := amd64ParseMReg(destination.Reg); !ok { + return true, false, fmt.Errorf("%s PSHUFW destination must be M0..M7: %q", c.goarch, ins.Raw) + } + if source.Kind == OpReg { + if _, ok := amd64ParseMReg(source.Reg); !ok { + return true, false, fmt.Errorf("%s PSHUFW source must be M0..M7 or memory: %q", c.goarch, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s PSHUFW source must be M0..M7 or memory: %q", c.goarch, ins.Raw) + } + if source.Kind == OpMem && !x86MemoryRegistersValidForArch(source.Mem, c.goarch) { + return true, false, fmt.Errorf("%s PSHUFW source address uses an out-of-range register: %q", c.goarch, ins.Raw) + } + value, err := c.evalIntSized(source, I64) + if err != nil { + return true, false, err + } + result := c.emitMMXWordShuffle(value, uint8(ins.Args[0].Imm)) + return true, false, c.storeReg(destination.Reg, result) + } + + if baseOp == "PSHUFHW" || baseOp == "PSHUFLW" { + if zeroing { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 || !amd64UnsignedImmediate(ins.Args[0], 8) { + return true, false, fmt.Errorf("amd64 %s expects $unsigned-imm8, X/m128, X: %q", baseOp, ins.Raw) + } + source, destination := ins.Args[1], ins.Args[2] + if !c.isGoVEXVectorRegister(source, 16, true) || !c.isGoVEXVectorRegister(destination, 16, false) { + return true, false, fmt.Errorf("amd64 %s operands are outside Go 1.27's X/m128, X classes: %q", baseOp, ins.Raw) + } + value, err := c.loadPackedCompareBytes(source, 16) + if err != nil { + return true, false, err + } + result := c.emitPackedWordShuffle(16, value, uint8(ins.Args[0].Imm), high) + return true, false, c.storeX(destination.Reg, result) + } + + masked := len(ins.Args) == 4 + if len(ins.Args) != 3 && !masked || !amd64VectorByteShiftImmediate(ins.Args[0]) { + return true, false, fmt.Errorf("amd64 %s expects $imm8, X|Y|Z/mem, [K,] X|Y|Z: %q", baseOp, ins.Raw) + } + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed Go 1.27's assembler operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s.Z requires a writemask: %q", baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + byteWidth := amd64VectorByteWidth(destination.Reg) + if destination.Kind != OpReg || byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's X/Y/Z classes: %q", baseOp, ins.Raw) + } + source := ins.Args[1] + if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("amd64 %s source must match its destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("amd64 %s source must be a vector register or memory: %q", baseOp, ins.Raw) + } + if ins.Args[0].Imm < 0 && amd64PackedWordShuffleRequiresEVEX(source, destination, byteWidth, masked) { + return true, false, fmt.Errorf("amd64 %s EVEX form requires an unsigned imm8: %q", baseOp, ins.Raw) + } + + maskValue := "" + if masked { + mask := ins.Args[2] + maskIndex, validMask := amd64ParseKReg(mask.Reg) + if mask.Kind != OpReg || !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form requires K1..K7: %q", baseOp, ins.Raw) + } + maskValue, err = c.loadK(mask.Reg) + if err != nil { + return true, false, err + } + } + value, err := c.loadPackedCompareBytes(source, byteWidth) + if err != nil { + return true, false, err + } + result := c.emitPackedWordShuffle(byteWidth, value, uint8(ins.Args[0].Imm), high) + if masked { + old, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + words := byteWidth / 2 + computedWords := c.newTmp() + oldWords := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i16>\n", computedWords, byteWidth, result, words) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i16>\n", oldWords, byteWidth, old, words) + maskedWords := amd64ApplyIntegerLaneMask(c, words, 16, "%"+computedWords, "%"+oldWords, maskValue, zeroing) + maskedBytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i16> %s to <%d x i8>\n", maskedBytes, words, maskedWords, byteWidth) + result = "%" + maskedBytes + } + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, result) +} + +func (c *amd64Ctx) emitMMXWordShuffle(source string, immediate uint8) string { + sourceWords := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to <4 x i16>\n", sourceWords, source) + result := "zeroinitializer" + for destinationWord := 0; destinationWord < 4; destinationWord++ { + sourceWord := int(immediate >> (2 * destinationWord) & 3) + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x i16> %%%s, i32 %d\n", extracted, sourceWords, sourceWord) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <4 x i16> %s, i16 %%%s, i32 %d\n", inserted, result, extracted, destinationWord) + result = "%" + inserted + } + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i16> %s to i64\n", bits, result) + return "%" + bits +} + +func amd64PackedWordShuffleRequiresEVEX(source, destination Operand, byteWidth int, masked bool) bool { + if byteWidth == 64 || masked { + return true + } + for _, operand := range []Operand{source, destination} { + if operand.Kind != OpReg { + continue + } + index, ok := amd64VectorRegisterIndex(operand.Reg, byteWidth) + if !ok || index >= 16 { + return true + } + } + return false +} + +func (c *amd64Ctx) emitPackedWordShuffle(byteWidth int, source string, immediate uint8, high bool) string { + words := byteWidth / 2 + sourceWords := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i16>\n", sourceWords, byteWidth, source, words) + result := "zeroinitializer" + for destinationWord := 0; destinationWord < words; destinationWord++ { + laneWord := destinationWord % 8 + sourceWord := destinationWord + shuffle := laneWord < 4 && !high || laneWord >= 4 && high + if shuffle { + selector := laneWord + halfBase := destinationWord - laneWord + if high { + selector -= 4 + halfBase += 4 + } + sourceWord = halfBase + int(immediate>>(2*selector)&3) + } + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i16> %%%s, i32 %d\n", extracted, words, sourceWords, sourceWord) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i16> %s, i16 %%%s, i32 %d\n", inserted, words, result, extracted, destinationWord) + result = "%" + inserted + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i16> %s to <%d x i8>\n", bytes, words, result, byteWidth) + return "%" + bytes +} diff --git a/amd64_lower_shuffle_words_test.go b/amd64_lower_shuffle_words_test.go new file mode 100644 index 00000000..8350b3c4 --- /dev/null +++ b/amd64_lower_shuffle_words_test.go @@ -0,0 +1,121 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PackedWordShuffleCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast := 15 + zLast := 31 + if target.goarch == "386" { + legacyLast = 7 + zLast = 7 + } + var source strings.Builder + source.WriteString("TEXT packedwordshuffleforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"PSHUFHW", "PSHUFLW"} { + fmt.Fprintf(&source, "\t%s $0, X0, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s $255, 8(AX), X%d\n", op, legacyLast) + } + for _, op := range []string{"VPSHUFHW", "VPSHUFLW"} { + source.WriteString("\t" + op + " $-128, X0, X1\n") + source.WriteString("\t" + op + " $127, 8(AX), X1\n") + source.WriteString("\t" + op + " $255, Y0, Y1\n") + source.WriteString("\t" + op + " $1, 16(AX), Y2\n") + source.WriteString("\t" + op + " $2, X16, X31\n") + fmt.Fprintf(&source, "\t%s $3, Z0, Z%d\n", op, zLast) + if target.goarch == "amd64" { + source.WriteString("\t" + op + " $4, X20, K1, X21\n") + source.WriteString("\t" + op + ".Z $5, 24(AX), K2, Y22\n") + source.WriteString("\t" + op + " $6, Z16, K3, Z31\n") + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "packedwordshuffleforms": {Name: "packedwordshuffleforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "packed-word-shuffle-"+target.name+".ll", "packed-word-shuffle-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PackedWordShuffleRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "PSHUFHW $-1, X0, X1", + "PSHUFLW $256, X0, X1", + "PSHUFHW $1, X16, X1", + "PSHUFLW $1, Y0, Y1", + "PSHUFHW.Z $1, X0, X1", + "PSHUFLW $1, X0, (AX)", + "VPSHUFHW $-129, X0, X1", + "VPSHUFLW $256, X0, X1", + "VPSHUFHW $-1, X16, X1", + "VPSHUFLW $-1, Z0, Z1", + "VPSHUFHW $1, X0, Y1", + "VPSHUFLW $1, X0, K0, X1", + "VPSHUFHW.Z $1, X0, X1", + "VPSHUFLW.BCST $1, (AX), X1", + "VPSHUFHW $1, X0, (AX)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedWordShuffleRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "PSHUFHW $1, X8, X0", + "PSHUFLW $1, X0, X8", + "VPSHUFHW $1, X0, K1, X1", + "VPSHUFLW.Z $1, X0, K1, X1", + "VPSHUFHW $1, Z8, Z0", + } { + t.Run("386_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PackedWordShuffleRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86PackedWordShuffleRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's PSHUFHW/PSHUFLW tables for %s", instruction, goarch) + } +} diff --git a/amd64_lower_sqrt_scalar_test.go b/amd64_lower_sqrt_scalar_test.go new file mode 100644 index 00000000..1433991c --- /dev/null +++ b/amd64_lower_sqrt_scalar_test.go @@ -0,0 +1,198 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateX86ScalarSqrtCompleteGo127Forms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT scalarsqrtforms(SB),$0-0\n") + for _, op := range []string{"VSQRTSS", "VSQRTSD"} { + fmt.Fprintf(&source, "\t%s X0, X1, X2\n", op) + fmt.Fprintf(&source, "\t%s 8(BX), X3, X4\n", op) + fmt.Fprintf(&source, "\t%s X29, X30, X31\n", op) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s X5, X6, K1, X7\n", op) + fmt.Fprintf(&source, "\t%s.Z 16(BX), X8, K2, X9\n", op) + } + for _, rounding := range []string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"} { + fmt.Fprintf(&source, "\t%s.%s X10, X11, X12\n", op, rounding) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.%s.Z X13, X14, K3, X15\n", op, rounding) + } + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "scalarsqrtforms": {Name: "scalarsqrtforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "scalar-sqrt-"+target.name+".ll", "scalar-sqrt-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86ScalarSqrtRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "VSQRTSS X0, X1", + "VSQRTSD X0, X1, X2, X3, X4", + "VSQRTSS Y0, X1, X2", + "VSQRTSD X0, Y1, X2", + "VSQRTSS X0, X1, K0, X2", + "VSQRTSD.Z X0, X1, X2", + "VSQRTSS.BCST 8(BX), X1, X2", + "VSQRTSD.SAE X0, X1, X2", + "VSQRTSS.RN_SAE 8(BX), X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + requireX86GoAssemblerResult(t, "amd64", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + assertX86ScalarSqrtRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + assertX86ScalarSqrtRejected(t, "386", "i386-unknown-linux-gnu", "VSQRTSS X0, X1, K1, X2") +} + +func assertX86ScalarSqrtRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VSQRTSS/VSQRTSD _yvaddsd forms for %s", instruction, goarch) + } +} + +func TestAMD64ScalarSqrtRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT scalarsqrt(SB),NOSPLIT,$0-64 + MOVQ out+0(FP), AX + MOVQ source64+8(FP), BX + MOVQ passthrough64+16(FP), CX + MOVQ source32+24(FP), DX + MOVQ passthrough32+32(FP), SI + MOVQ old64+40(FP), DI + MOVQ old32+48(FP), R8 + MOVQ mask+56(FP), R9 + KMOVQ R9, K1 + + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VSQRTSD.RD_SAE X0, X1, X2 + VMOVUPD X2, 0(AX) + + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VSQRTSS.RU_SAE X0, X1, X2 + VMOVUPS X2, 16(AX) + + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DI), X4 + VSQRTSD X0, X1, K1, X4 + VMOVUPD X4, 32(AX) + + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VMOVUPS (R8), X4 + VSQRTSS.Z X0, X1, K1, X4 + VMOVUPS X4, 48(AX) + VZEROUPPER + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + {Offset: 48, Type: Ptr, Index: 6, Field: -1}, + {Offset: 56, Type: I64, Index: 7, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "scalarsqrt": {Name: "scalarsqrt", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +extern void scalarsqrt(uint8_t *, const double *, const double *, const float *, const float *, const double *, const float *, uint64_t); +int main(void) { + const double source64[2] = {9.0, 77.0}; + const double passthrough64[2] = {100.0, 101.0}; + const float source32[4] = {16.0f, 17.0f, 18.0f, 19.0f}; + const float passthrough32[4] = {200.0f, 201.0f, 202.0f, 203.0f}; + const double old64[2] = {300.0, 301.0}; + const float old32[4] = {400.0f, 401.0f, 402.0f, 403.0f}; + union { uint8_t bytes[64]; double d64[8]; float f32[16]; } out = {0}; + scalarsqrt(out.bytes, source64, passthrough64, source32, passthrough32, old64, old32, 0); + if (out.d64[0] != 3.0 || out.d64[1] != 101.0) return 1; + if (out.f32[4] != 4.0f || out.f32[5] != 201.0f || out.f32[6] != 202.0f || out.f32[7] != 203.0f) return 2; + if (out.d64[4] != 300.0 || out.d64[5] != 101.0) return 3; + if (out.f32[12] != 0.0f || out.f32[13] != 201.0f || out.f32[14] != 202.0f || out.f32[15] != 203.0f) return 4; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "scalar_sqrt", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_stack_width.go b/amd64_lower_stack_width.go new file mode 100644 index 00000000..5e57e1d6 --- /dev/null +++ b/amd64_lower_stack_width.go @@ -0,0 +1,305 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64StackWidthMode uint8 + +const ( + amd64StackPushValue amd64StackWidthMode = iota + amd64StackPopValue + amd64StackPushFlags + amd64StackPopFlags +) + +type amd64StackWidthSpec struct { + bits int + mode amd64StackWidthMode + segments amd64StackSegmentSet + segmentNativeWidth bool +} + +type amd64StackSegmentSet uint8 + +const ( + amd64StackSegmentES amd64StackSegmentSet = 1 << iota + amd64StackSegmentCS + amd64StackSegmentSS + amd64StackSegmentDS + amd64StackSegmentFS + amd64StackSegmentGS + + amd64StackPushSegments = amd64StackSegmentES | amd64StackSegmentCS | + amd64StackSegmentSS | amd64StackSegmentDS | amd64StackSegmentFS | + amd64StackSegmentGS + amd64StackPopSegments = amd64StackPushSegments &^ amd64StackSegmentCS + amd64StackLongSegments = amd64StackSegmentFS | amd64StackSegmentGS +) + +// amd64StackWidthSpecs models the value/flags, push/pop, width, and segment-set +// axes once for all Go x86 stack forms. Ordinary L spellings are 386-only and +// ordinary Q spellings are amd64-only. Go's separate ymovtab accepts its listed +// segment-register forms in both modes; L/Q use the target's native stack width. +var amd64StackWidthSpecs = map[Op]amd64StackWidthSpec{ + "PUSHW": {bits: 16, mode: amd64StackPushValue, segments: amd64StackPushSegments}, + "POPW": {bits: 16, mode: amd64StackPopValue, segments: amd64StackPopSegments}, + "PUSHL": {bits: 32, mode: amd64StackPushValue, segments: amd64StackPushSegments, segmentNativeWidth: true}, + "POPL": {bits: 32, mode: amd64StackPopValue, segments: amd64StackPopSegments, segmentNativeWidth: true}, + "PUSHQ": {bits: 64, mode: amd64StackPushValue, segments: amd64StackLongSegments, segmentNativeWidth: true}, + "POPQ": {bits: 64, mode: amd64StackPopValue, segments: amd64StackLongSegments, segmentNativeWidth: true}, + "PUSHFW": {bits: 16, mode: amd64StackPushFlags}, + "POPFW": {bits: 16, mode: amd64StackPopFlags}, + "PUSHFL": {bits: 32, mode: amd64StackPushFlags}, + "POPFL": {bits: 32, mode: amd64StackPopFlags}, + "PUSHFQ": {bits: 64, mode: amd64StackPushFlags}, + "POPFQ": {bits: 64, mode: amd64StackPopFlags}, +} + +func (c *amd64Ctx) lowerStackWidth(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64StackWidthSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed form in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + + switch spec.mode { + case amd64StackPushFlags: + if err := c.validateOrdinaryStackWidthMode(baseOp, spec.bits, ins); err != nil { + return true, false, err + } + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, baseOp, ins.Raw) + } + value := c.packX86Flags() + if spec.bits != 64 { + value = c.truncI64(value, amd64StackLLVMType(spec.bits)) + } + return true, false, c.pushStackWidth(spec.bits, value) + case amd64StackPopFlags: + if err := c.validateOrdinaryStackWidthMode(baseOp, spec.bits, ins); err != nil { + return true, false, err + } + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, baseOp, ins.Raw) + } + value, err := c.popStackWidth(spec.bits) + if err != nil { + return true, false, err + } + if spec.bits != 64 { + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to i64\n", extended, amd64StackLLVMType(spec.bits), value) + value = "%" + extended + } + c.unpackX86Flags(value) + return true, false, nil + case amd64StackPushValue, amd64StackPopValue: + if len(ins.Args) != 1 { + role := "src" + if spec.mode == amd64StackPopValue { + role = "dst" + } + return true, false, fmt.Errorf("%s %s expects %s: %q", c.goarch, baseOp, role, ins.Raw) + } + default: + panic("unknown x86 stack-width mode") + } + + operand := ins.Args[0] + segmentStack := x86SegmentRegisterOperand(operand) + if segmentStack { + if !spec.segments.contains(operand.Reg) { + return true, false, fmt.Errorf("%s %s does not accept segment register %s in Go 1.27's ymovtab: %q", c.goarch, baseOp, operand.Reg, ins.Raw) + } + bits := spec.bits + if spec.segmentNativeWidth { + bits = c.x86NativeStackBits() + } + if spec.mode == amd64StackPushValue { + selector := c.loadX86SegmentSelector(operand.Reg) + value := selector + switch bits { + case 16: + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i32 %s to i16\n", narrow, selector) + value = "%" + narrow + case 32: + case 64: + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, selector) + value = "%" + wide + default: + panic("invalid x86 segment stack width") + } + return true, false, c.pushStackWidth(bits, value) + } + value, err := c.popStackWidth(bits) + if err != nil { + return true, false, err + } + if bits != 16 { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to i16\n", narrow, amd64StackLLVMType(bits), value) + value = "%" + narrow + } + return true, false, c.storeX86SegmentSelector(operand.Reg, value) + } + if err := c.validateOrdinaryStackWidthMode(baseOp, spec.bits, ins); err != nil { + return true, false, err + } + if spec.mode == amd64StackPushValue { + if operand.Kind == OpReg { + if !isX86YrlRegisterForArch(operand.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s source is outside Go 1.27's Yrl class: %q", c.goarch, baseOp, ins.Raw) + } + } else if operand.Kind != OpImm && !isAMD64MemoryOperand(operand) { + return true, false, fmt.Errorf("%s %s expects Yrl/memory/immediate src: %q", c.goarch, baseOp, ins.Raw) + } + if operand.Kind == OpMem && !x86MemoryRegistersValidForArch(operand.Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s memory source uses an out-of-range address register: %q", c.goarch, baseOp, ins.Raw) + } + value, err := c.evalIntSized(operand, amd64StackLLVMType(spec.bits)) + if err != nil { + return true, false, err + } + return true, false, c.pushStackWidth(spec.bits, value) + } + + if operand.Kind == OpReg { + if !isX86YrlRegisterForArch(operand.Reg, c.goarch) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's Yrl class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(operand) { + return true, false, fmt.Errorf("%s %s expects reg/mem dst in the Yrl class: %q", c.goarch, baseOp, ins.Raw) + } + if operand.Kind == OpMem && !x86MemoryRegistersValidForArch(operand.Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s memory destination uses an out-of-range address register: %q", c.goarch, baseOp, ins.Raw) + } + value, err := c.popStackWidth(spec.bits) + if err != nil { + return true, false, err + } + return true, false, c.storeStackWidth(operand, spec.bits, value) +} + +func (c *amd64Ctx) validateOrdinaryStackWidthMode(op string, bits int, ins Instr) error { + if c.goarch == "386" && bits == 64 { + return fmt.Errorf("386 %s requires GOARCH=amd64: %q", op, ins.Raw) + } + if c.goarch != "386" && bits == 32 { + return fmt.Errorf("%s requires GOARCH=386: %q", op, ins.Raw) + } + return nil +} + +func (c *amd64Ctx) x86NativeStackBits() int { + if c.goarch == "386" { + return 32 + } + return 64 +} + +func (set amd64StackSegmentSet) contains(reg Reg) bool { + var bit amd64StackSegmentSet + switch reg { + case ES: + bit = amd64StackSegmentES + case CS: + bit = amd64StackSegmentCS + case SS: + bit = amd64StackSegmentSS + case DS: + bit = amd64StackSegmentDS + case FS: + bit = amd64StackSegmentFS + case GS: + bit = amd64StackSegmentGS + default: + return false + } + return set&bit != 0 +} + +func amd64StackLLVMType(bits int) LLVMType { + switch bits { + case 16: + return I16 + case 32: + return I32 + case 64: + return I64 + default: + panic("invalid x86 stack width") + } +} + +func (c *amd64Ctx) pushStackWidth(bits int, value string) error { + if c.goarch == "386" { + switch bits { + case 16: + return c.pushI16(value) + case 32: + return c.pushI32(value) + } + return fmt.Errorf("386 cannot push %d-bit stack values", bits) + } + if bits != 64 { + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to i64\n", extended, amd64StackLLVMType(bits), value) + value = "%" + extended + } + c.pushI64(value) + return nil +} + +func (c *amd64Ctx) popStackWidth(bits int) (string, error) { + if c.goarch == "386" { + switch bits { + case 16: + return c.popI16() + case 32: + return c.popI32() + } + return "", fmt.Errorf("386 cannot pop %d-bit stack values", bits) + } + value := c.popI64() + if bits == 64 { + return value, nil + } + return c.truncI64(value, amd64StackLLVMType(bits)), nil +} + +func (c *amd64Ctx) storeStackWidth(destination Operand, bits int, value string) error { + typ := amd64StackLLVMType(bits) + switch destination.Kind { + case OpReg: + return c.storeRegSized(destination.Reg, typ, value) + case OpMem: + ptr, ptrType, err := c.ptrFromMem(destination.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, %s %s, align 1\n", typ, value, ptrType, ptr) + return nil + case OpSym: + ptr, err := c.ptrFromSB(destination.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, ptr %s, align 1\n", typ, value, ptr) + return nil + case OpFP: + return c.storeFPResult(destination.FPOffset, typ, value) + default: + return fmt.Errorf("%s stack destination is not writable", destination.String()) + } +} diff --git a/amd64_lower_stack_width_test.go b/amd64_lower_stack_width_test.go new file mode 100644 index 00000000..63202b82 --- /dev/null +++ b/amd64_lower_stack_width_test.go @@ -0,0 +1,258 @@ +package plan9asm + +import ( + "reflect" + "runtime" + "strings" + "testing" +) + +func TestAMD64StackWidthGrammarIsComplete(t *testing.T) { + want := map[Op]amd64StackWidthSpec{ + "PUSHW": {bits: 16, mode: amd64StackPushValue, segments: amd64StackPushSegments}, + "POPW": {bits: 16, mode: amd64StackPopValue, segments: amd64StackPopSegments}, + "PUSHL": {bits: 32, mode: amd64StackPushValue, segments: amd64StackPushSegments, segmentNativeWidth: true}, + "POPL": {bits: 32, mode: amd64StackPopValue, segments: amd64StackPopSegments, segmentNativeWidth: true}, + "PUSHQ": {bits: 64, mode: amd64StackPushValue, segments: amd64StackLongSegments, segmentNativeWidth: true}, + "POPQ": {bits: 64, mode: amd64StackPopValue, segments: amd64StackLongSegments, segmentNativeWidth: true}, + "PUSHFW": {bits: 16, mode: amd64StackPushFlags}, + "POPFW": {bits: 16, mode: amd64StackPopFlags}, + "PUSHFL": {bits: 32, mode: amd64StackPushFlags}, + "POPFL": {bits: 32, mode: amd64StackPopFlags}, + "PUSHFQ": {bits: 64, mode: amd64StackPushFlags}, + "POPFQ": {bits: 64, mode: amd64StackPopFlags}, + } + if !reflect.DeepEqual(amd64StackWidthSpecs, want) { + t.Fatalf("stack-width grammar = %+v, want %+v", amd64StackWidthSpecs, want) + } +} + +func TestTranslateX86StackWidthCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + high := "R11" + if target.goarch == "386" { + high = "DX" + } + source := "TEXT stackwidthforms(SB),$0-0\n" + + "\tPUSHW AX\n\tPOPW " + high + "\n" + + "\tPUSHW $61731\n\tPOPW (BX)\n" + + "\tPUSHW (BX)\n\tPOPW AX\n" + + "\tPUSHFW\n\tPOPFW\n" + if target.goarch == "amd64" { + source += "\tPUSHQ R11\n\tPOPQ (BX)\n\tPUSHQ FS\n\tPUSHQ GS\n\tPOPQ FS\n\tPOPQ GS\n\tPUSHFQ\n\tPOPFQ\n" + } else { + source += "\tPUSHL DX\n\tPOPL (BX)\n\tPUSHFL\n\tPOPFL\n" + } + source += "\tRET\n" + + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"stackwidthforms": {Name: "stackwidthforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "stack-width-"+target.name+".ll", "stack-width-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86StackSegmentCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + const source = `TEXT stacksegmentforms(SB),$0-0 + PUSHW CS + PUSHW SS + PUSHW DS + PUSHW ES + PUSHW FS + PUSHW GS + POPW SS + POPW DS + POPW ES + POPW FS + POPW GS + PUSHL CS + PUSHL SS + PUSHL DS + PUSHL ES + PUSHL FS + PUSHL GS + POPL SS + POPL DS + POPL ES + POPL FS + POPL GS + PUSHQ FS + PUSHQ GS + POPQ FS + POPQ GS + POPW DS + POPL DS + RET +` + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"stacksegmentforms": {Name: "stacksegmentforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "stack-segment-"+target.name+".ll", "stack-segment-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86StackWidthRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "PUSHW X0"}, + {goarch: "amd64", instruction: "POPW $1"}, + {goarch: "amd64", instruction: "PUSHFW AX"}, + {goarch: "amd64", instruction: "POPQ X0"}, + {goarch: "amd64", instruction: "PUSHL AX"}, + {goarch: "amd64", instruction: "PUSHQ DS"}, + {goarch: "amd64", instruction: "POPQ ES"}, + {goarch: "amd64", instruction: "POPW CS"}, + {goarch: "amd64", instruction: "POPL CS"}, + {goarch: "386", instruction: "PUSHQ AX"}, + {goarch: "386", instruction: "POPW R11"}, + {goarch: "386", instruction: "POPFQ"}, + {goarch: "386", instruction: "PUSHQ DS"}, + {goarch: "386", instruction: "POPQ ES"}, + {goarch: "386", instruction: "POPW CS"}, + {goarch: "386", instruction: "POPL CS"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "$", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's stack tables", test.instruction) + } + }) + } +} + +func TestAMD64StackWidthRuntimeValuesAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT stackwidthsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVW $0x1234, AX + PUSHW AX + POPW CX + MOVW CX, 0(DI) + MOVW $0x5678, 2(DI) + PUSHW 2(DI) + POPW DX + MOVW DX, 4(DI) + PUSHW $61731 + POPW 6(DI) + MOVQ $0x123456789abcdef, AX + PUSHQ AX + POPQ 8(DI) + STC + PUSHFW + CLC + POPFW + SETCS 16(DI) + PUSHFQ + CLC + POPFQ + SETCS 17(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"stackwidthsemantics": { + Name: "stackwidthsemantics", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void stackwidthsemantics(uint8_t *); +static uint16_t load16(const uint8_t *p) { uint16_t v; memcpy(&v,p,2); return v; } +static uint64_t load64(const uint8_t *p) { uint64_t v; memcpy(&v,p,8); return v; } +int main(void) { + uint8_t out[24] = {0}; stackwidthsemantics(out); + if (load16(out) != 0x1234 || load16(out+4) != 0x5678 || load16(out+6) != 61731) return 10; + if (load64(out+8) != UINT64_C(0x123456789abcdef)) return 11; + if (out[16] != 1 || out[17] != 1) return 12; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "stack_width_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_string.go b/amd64_lower_string.go index 5ae46f59..39e6444d 100644 --- a/amd64_lower_string.go +++ b/amd64_lower_string.go @@ -1,50 +1,82 @@ package plan9asm -import "fmt" +import ( + "fmt" +) + +type x86StringSpec struct { + kind string + typ LLVMType + width int +} + +var x86StringSpecs = map[Op]x86StringSpec{ + "MOVSB": {kind: "movs", typ: I8, width: 1}, + "MOVSW": {kind: "movs", typ: I16, width: 2}, + "MOVSL": {kind: "movs", typ: I32, width: 4}, + "MOVSQ": {kind: "movs", typ: I64, width: 8}, + "STOSB": {kind: "stos", typ: I8, width: 1}, + "STOSW": {kind: "stos", typ: I16, width: 2}, + "STOSL": {kind: "stos", typ: I32, width: 4}, + "STOSQ": {kind: "stos", typ: I64, width: 8}, + "SCASB": {kind: "scas", typ: I8, width: 1}, + "SCASW": {kind: "scas", typ: I16, width: 2}, + "SCASL": {kind: "scas", typ: I32, width: 4}, + "SCASQ": {kind: "scas", typ: I64, width: 8}, + "CMPSB": {kind: "cmps", typ: I8, width: 1}, + "CMPSW": {kind: "cmps", typ: I16, width: 2}, + "CMPSL": {kind: "cmps", typ: I32, width: 4}, + "CMPSQ": {kind: "cmps", typ: I64, width: 8}, + "LODSB": {kind: "lods", typ: I8, width: 1}, + "LODSW": {kind: "lods", typ: I16, width: 2}, + "LODSL": {kind: "lods", typ: I32, width: 4}, + "LODSQ": {kind: "lods", typ: I64, width: 8}, +} + +func x86StringProperties(op Op) (kind string, typ LLVMType, width int, ok bool) { + spec, ok := x86StringSpecs[Op(normalizeInstructionOpcode(op))] + if !ok { + return "", "", 0, false + } + return spec.kind, spec.typ, spec.width, true +} func (c *amd64Ctx) lowerString(op Op, ins Instr) (ok bool, terminated bool, err error) { - if c.goarch != "386" { + kind, typ, width, ok := x86StringProperties(op) + if !ok { return false, false, nil } - switch op { - case "MOVSB", "MOVSL", "STOSL", "SCASB": - default: - return false, false, nil + if op != Op(normalizeInstructionOpcode(op)) { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, op, ins.Raw) } - prefix := c.repeatPrefix c.repeatPrefix = "" - if len(ins.Args) != 0 { - return true, false, fmt.Errorf("386 %s takes no operands: %q", op, ins.Raw) + if c.goarch == "386" && typ == I64 { + return true, false, fmt.Errorf("386 %s is not in the Go assembler's 32-bit instruction table", op) } - repeated := prefix != "" - if prefix == "REPN" && op != "SCASB" { - return true, false, fmt.Errorf("386 REPN is unsupported for %s", op) - } - if prefix == "REP" && op == "SCASB" { - return true, false, fmt.Errorf("386 REP SCASB is not yet supported") + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, op, ins.Raw) } count := "1" - if repeated { - cx32, err := c.evalIntSized(Operand{Kind: OpReg, Reg: CX}, I32) + if prefix != "" { + cx, err := c.loadReg(CX) if err != nil { return true, false, err } - wide := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, cx32) - count = "%" + wide + if c.goarch == "386" { + cx32 := c.truncI64(cx, I32) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, cx32) + count = "%" + wide + } else { + count = cx + } } direction := c.loadDirectionFlag() - switch op { - case "MOVSB", "MOVSL": - width := 1 - helper := "__plan9asm_movsb" - if op == "MOVSL" { - width = 4 - helper = "__plan9asm_movsl" - } + switch kind { + case "movs": si, err := c.loadReg(SI) if err != nil { return true, false, err @@ -53,7 +85,7 @@ func (c *amd64Ctx) lowerString(op Op, ins Instr) (ok bool, terminated bool, err if err != nil { return true, false, err } - fmt.Fprintf(c.b, " call void @%s(i64 %s, i64 %s, i64 %s, i1 %s)\n", helper, di, si, count, direction) + fmt.Fprintf(c.b, " call void @%s(i64 %s, i64 %s, i64 %s, i1 %s)\n", x86StringHelperName(kind, width), di, si, count, direction) bytes := c.newTmp() fmt.Fprintf(c.b, " %%%s = mul i64 %s, %d\n", bytes, count, width) if err := c.storeStringIndex(SI, si, "%"+bytes, direction); err != nil { @@ -63,33 +95,34 @@ func (c *amd64Ctx) lowerString(op Op, ins Instr) (ok bool, terminated bool, err return true, false, err } - case "STOSL": + case "stos": di, err := c.loadReg(DI) if err != nil { return true, false, err } - ax, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, I32) + value, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, typ) if err != nil { return true, false, err } - fmt.Fprintf(c.b, " call void @__plan9asm_rep_stosl(i64 %s, i32 %s, i64 %s, i1 %s)\n", di, ax, count, direction) + fmt.Fprintf(c.b, " call void @%s(i64 %s, %s %s, i64 %s, i1 %s)\n", x86StringHelperName(kind, width), di, typ, value, count, direction) bytes := c.newTmp() - fmt.Fprintf(c.b, " %%%s = mul i64 %s, 4\n", bytes, count) + fmt.Fprintf(c.b, " %%%s = mul i64 %s, %d\n", bytes, count, width) if err := c.storeStringIndex(DI, di, "%"+bytes, direction); err != nil { return true, false, err } - case "SCASB": + case "scas": di, err := c.loadReg(DI) if err != nil { return true, false, err } - needle, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AL}, I8) + needle, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, typ) if err != nil { return true, false, err } + whileEqual := prefix == "REP" call := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call { i64, i64, i1 } @__plan9asm_repne_scasb(i64 %s, i8 %s, i64 %s, i1 %s)\n", call, di, needle, count, direction) + fmt.Fprintf(c.b, " %%%s = call { i64, i64, i1 } @%s(i64 %s, %s %s, i64 %s, i1 %s, i1 %t)\n", call, x86StringHelperName(kind, width), di, typ, needle, count, direction, whileEqual) next := c.newTmp() remaining := c.newTmp() equal := c.newTmp() @@ -100,7 +133,7 @@ func (c *amd64Ctx) lowerString(op Op, ins Instr) (ok bool, terminated bool, err return true, false, err } zf := "%" + equal - if repeated { + if prefix != "" { oldZF := c.loadFlag(c.flagsZSlot) executed := c.newTmp() fmt.Fprintf(c.b, " %%%s = icmp ne i64 %s, 0\n", executed, count) @@ -109,21 +142,125 @@ func (c *amd64Ctx) lowerString(op Op, ins Instr) (ok bool, terminated bool, err zf = "%" + preserved } fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", zf, c.flagsZSlot) - if repeated { - if err := c.storeRegSized(CX, I32, c.truncI64("%"+remaining, I32)); err != nil { + if prefix != "" { + if err := c.storeStringCount("%" + remaining); err != nil { return true, false, err } } + + case "cmps": + si, err := c.loadReg(SI) + if err != nil { + return true, false, err + } + di, err := c.loadReg(DI) + if err != nil { + return true, false, err + } + whileEqual := prefix == "REP" + resultType := fmt.Sprintf("{ i64, i64, i64, %s, %s, i1 }", typ, typ) + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @%s(i64 %s, i64 %s, i64 %s, i1 %s, i1 %t)\n", call, resultType, x86StringHelperName(kind, width), si, di, count, direction, whileEqual) + nextSI := c.newTmp() + nextDI := c.newTmp() + remaining := c.newTmp() + left := c.newTmp() + right := c.newTmp() + executed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 0\n", nextSI, resultType, call) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 1\n", nextDI, resultType, call) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 2\n", remaining, resultType, call) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 3\n", left, resultType, call) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 4\n", right, resultType, call) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 5\n", executed, resultType, call) + if err := c.storeReg(SI, "%"+nextSI); err != nil { + return true, false, err + } + if err := c.storeReg(DI, "%"+nextDI); err != nil { + return true, false, err + } + if prefix != "" { + if err := c.storeStringCount("%" + remaining); err != nil { + return true, false, err + } + } + flagSlots := []string{c.flagsCFSlot, c.flagsZSlot, c.flagsSltSlot, c.flagsPFSlot, c.flagsOFSlot} + oldFlags := make([]string, len(flagSlots)) + if prefix != "" { + for index, slot := range flagSlots { + oldFlags[index] = c.loadFlag(slot) + } + } + c.setCmpFlagsSized(typ, "%"+left, "%"+right) + if prefix != "" { + for index, slot := range flagSlots { + current := c.loadFlag(slot) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i1 %s, i1 %s\n", selected, executed, current, oldFlags[index]) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", selected, slot) + } + } + + case "lods": + si, err := c.loadReg(SI) + if err != nil { + return true, false, err + } + resultType := fmt.Sprintf("{ i64, i64, %s, i1 }", typ) + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @%s(i64 %s, i64 %s, i1 %s)\n", call, resultType, x86StringHelperName(kind, width), si, count, direction) + nextSI := c.newTmp() + remaining := c.newTmp() + loaded := c.newTmp() + executed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 0\n", nextSI, resultType, call) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 1\n", remaining, resultType, call) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 2\n", loaded, resultType, call) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 3\n", executed, resultType, call) + if err := c.storeReg(SI, "%"+nextSI); err != nil { + return true, false, err + } + value := "%" + loaded + if prefix != "" { + old, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, typ) + if err != nil { + return true, false, err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s %s\n", selected, executed, typ, loaded, typ, old) + value = "%" + selected + if err := c.storeStringCount("%" + remaining); err != nil { + return true, false, err + } + } + if err := c.storeRegSized(AX, typ, value); err != nil { + return true, false, err + } } - if repeated && op != "SCASB" { - if err := c.storeRegSized(CX, I32, "0"); err != nil { + if prefix != "" && kind != "scas" && kind != "cmps" { + if err := c.storeStringCount("0"); err != nil { return true, false, err } } return true, false, nil } +func x86StringHelperName(kind string, width int) string { + suffix := map[int]string{1: "b", 2: "w", 4: "l", 8: "q"}[width] + if kind == "movs" { + return "__plan9asm_movs" + suffix + } + return "__plan9asm_rep_" + kind + suffix +} + +func (c *amd64Ctx) storeStringCount(value string) error { + if c.goarch == "386" { + return c.storeRegSized(CX, I32, c.truncI64(value, I32)) + } + return c.storeRegSized(CX, I64, value) +} + func (c *amd64Ctx) loadDirectionFlag() string { t := c.newTmp() fmt.Fprintf(c.b, " %%%s = load i1, ptr %s\n", t, c.directionSlot) diff --git a/amd64_lower_string_compare.go b/amd64_lower_string_compare.go new file mode 100644 index 00000000..2d9436b7 --- /dev/null +++ b/amd64_lower_string_compare.go @@ -0,0 +1,144 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedStringCompareSpec struct { + explicitLength bool + maskResult bool + vector bool +} + +// amd64PackedStringCompareSpecs models Go 1.27's complete SSE4.2 packed-string +// grammar as three independent axes: explicit/implicit lengths, index/mask +// result, and legacy/VEX encoding. Every spelling shares the same imm8 and +// X/m128 operand grammar and the same five architectural flag results. +var amd64PackedStringCompareSpecs = map[Op]amd64PackedStringCompareSpec{ + "PCMPESTRI": {explicitLength: true}, + "PCMPESTRM": {explicitLength: true, maskResult: true}, + "PCMPISTRI": {}, + "PCMPISTRM": {maskResult: true}, + "VPCMPESTRI": {explicitLength: true, vector: true}, + "VPCMPESTRM": {explicitLength: true, maskResult: true, vector: true}, + "VPCMPISTRI": {vector: true}, + "VPCMPISTRM": {maskResult: true, vector: true}, +} + +func (c *amd64Ctx) lowerPackedStringCompare(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64PackedStringCompareSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed form in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + minimumImmediate := int64(0) + if spec.vector { + // _yvaeskeygenassist has both Yu8 and Yi8 rows, while the legacy + // yxshuf table has only Yu8. + minimumImmediate = -128 + } + if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[0].Imm < minimumImmediate || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("%s %s immediate is outside its Go 1.27 byte domain, or operands are not imm8, X/m128, X: %q", c.goarch, baseOp, ins.Raw) + } + + source, destination := ins.Args[1], ins.Args[2] + if destination.Kind != OpReg || !c.packedStringCompareRegister(spec, destination) { + return true, false, fmt.Errorf("%s %s destination is outside its Go 1.27 X register class: %q", c.goarch, baseOp, ins.Raw) + } + if source.Kind == OpReg { + if !c.packedStringCompareRegister(spec, source) { + return true, false, fmt.Errorf("%s %s source is outside its Go 1.27 X register class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be X or m128: %q", c.goarch, baseOp, ins.Raw) + } + if !spec.vector && source.Kind == OpMem && !x86MemoryRegistersValidForArch(source.Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s memory source uses a register outside the legacy address class: %q", c.goarch, baseOp, ins.Raw) + } + + left, err := c.loadX(destination.Reg) + if err != nil { + return true, false, err + } + right, err := c.loadPackedCompareBytes(source, 16) + if err != nil { + return true, false, err + } + lengthLeft, lengthRight := "", "" + if spec.explicitLength { + lengthLeft, err = c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, I32) + if err != nil { + return true, false, err + } + lengthRight, err = c.evalIntSized(Operand{Kind: OpReg, Reg: DX}, I32) + if err != nil { + return true, false, err + } + } + imm := uint8(ins.Args[0].Imm) + stem := "pcmpi" + if spec.explicitLength { + stem = "pcmpe" + } + + if spec.maskResult { + result := c.emitPackedStringCompareIntrinsic(stem+"strm128", "<16 x i8>", left, right, lengthLeft, lengthRight, imm) + if err := c.storeX(Reg("X0"), result); err != nil { + return true, false, err + } + } else { + result := c.emitPackedStringCompareIntrinsic(stem+"stri128", "i32", left, right, lengthLeft, lengthRight, imm) + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", extended, result) + if err := c.storeReg(CX, "%"+extended); err != nil { + return true, false, err + } + } + + carry := c.emitPackedStringCompareFlag(stem+"stric128", left, right, lengthLeft, lengthRight, imm) + overflow := c.emitPackedStringCompareFlag(stem+"strio128", left, right, lengthLeft, lengthRight, imm) + sign := c.emitPackedStringCompareFlag(stem+"stris128", left, right, lengthLeft, lengthRight, imm) + zero := c.emitPackedStringCompareFlag(stem+"striz128", left, right, lengthLeft, lengthRight, imm) + signedLess := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %s, %s\n", signedLess, sign, overflow) + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", carry, c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", zero, c.flagsZSlot) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", signedLess, c.flagsSltSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsPFSlot) + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", overflow, c.flagsOFSlot) + return true, false, nil +} + +func (c *amd64Ctx) packedStringCompareRegister(spec amd64PackedStringCompareSpec, operand Operand) bool { + if spec.vector { + return amd64VEXVectorRegister(operand, 16) + } + return operand.Kind == OpReg && c.isGoLegacyXReg(operand.Reg) +} + +func (c *amd64Ctx) emitPackedStringCompareIntrinsic(name, resultType, left, right, lengthLeft, lengthRight string, imm uint8) string { + result := c.newTmp() + if lengthLeft == "" { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.x86.sse42.%s(<16 x i8> %s, <16 x i8> %s, i8 %d)\n", + result, resultType, name, left, right, imm) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.x86.sse42.%s(<16 x i8> %s, i32 %s, <16 x i8> %s, i32 %s, i8 %d)\n", + result, resultType, name, left, lengthLeft, right, lengthRight, imm) + } + return "%" + result +} + +func (c *amd64Ctx) emitPackedStringCompareFlag(name, left, right, lengthLeft, lengthRight string, imm uint8) string { + result := c.emitPackedStringCompareIntrinsic(name, "i32", left, right, lengthLeft, lengthRight, imm) + flag := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i32 %s to i1\n", flag, result) + return "%" + flag +} diff --git a/amd64_lower_string_compare_test.go b/amd64_lower_string_compare_test.go new file mode 100644 index 00000000..2d3660d0 --- /dev/null +++ b/amd64_lower_string_compare_test.go @@ -0,0 +1,253 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +type packedStringCompareTestSpec struct { + op string + explicit bool + mask bool + vector bool +} + +func go127PackedStringCompareSpecs() []packedStringCompareTestSpec { + return []packedStringCompareTestSpec{ + {op: "PCMPESTRI", explicit: true}, + {op: "PCMPESTRM", explicit: true, mask: true}, + {op: "PCMPISTRI"}, + {op: "PCMPISTRM", mask: true}, + {op: "VPCMPESTRI", explicit: true, vector: true}, + {op: "VPCMPESTRM", explicit: true, mask: true, vector: true}, + {op: "VPCMPISTRI", vector: true}, + {op: "VPCMPISTRM", mask: true, vector: true}, + } +} + +func TestAMD64PackedStringCompareGrammarCoversCompleteGoFamily(t *testing.T) { + expected := go127PackedStringCompareSpecs() + if len(amd64PackedStringCompareSpecs) != len(expected) { + t.Fatalf("packed-string grammar has %d entries, want %d", len(amd64PackedStringCompareSpecs), len(expected)) + } + for _, want := range expected { + got, ok := amd64PackedStringCompareSpecs[Op(want.op)] + if !ok { + t.Errorf("packed-string grammar omitted %s", want.op) + continue + } + if got.explicitLength != want.explicit || got.maskResult != want.mask || got.vector != want.vector { + t.Errorf("packed-string grammar %s = %+v, want explicit=%v mask=%v vector=%v", want.op, got, want.explicit, want.mask, want.vector) + } + } +} + +func TestTranslateX86PackedStringCompareCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT packedstringcompareforms(SB),$0-0\n") + for index, spec := range go127PackedStringCompareSpecs() { + last := 15 + if target.goarch == "386" && !spec.vector { + last = 7 + } + fmt.Fprintf(&source, "\t%s $0, X1, X%d\n", spec.op, last) + fmt.Fprintf(&source, "\t%s $255, %d(AX), X%d\n", spec.op, index*16, last) + if spec.vector { + fmt.Fprintf(&source, "\t%s $-128, X1, X%d\n", spec.op, last) + } + } + source.WriteString("\tRET\n") + + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"packedstringcompareforms": {Name: "packedstringcompareforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{ + "@llvm.x86.sse42.pcmpestri128", "@llvm.x86.sse42.pcmpestrm128", + "@llvm.x86.sse42.pcmpistri128", "@llvm.x86.sse42.pcmpistrm128", + "@llvm.x86.sse42.pcmpestric128", "@llvm.x86.sse42.pcmpistriz128", + } { + if !strings.Contains(ir, intrinsic) { + t.Fatalf("translation omitted %s:\n%s", intrinsic, ir) + } + } + wantFeatures := `"target-features"="+avx,+sse4.2"` + if !strings.Contains(ir, wantFeatures) { + t.Fatalf("translation omitted %s:\n%s", wantFeatures, ir) + } + compileLLVMToObject(t, llc, target.triple, "packed-string-compare-"+target.name+".ll", "packed-string-compare-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86PackedStringCompareRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "PCMPESTRI $-1, X0, X1"}, + {goarch: "amd64", instruction: "PCMPISTRM $256, X0, X1"}, + {goarch: "amd64", instruction: "VPCMPESTRI.Z $7, X0, X1"}, + {goarch: "amd64", instruction: "VPCMPESTRI $-129, X0, X1"}, + {goarch: "amd64", instruction: "PCMPISTRI $7, Y0, X1"}, + {goarch: "amd64", instruction: "VPCMPISTRM $7, X0, X16"}, + {goarch: "386", instruction: "PCMPESTRM $7, X0, X8"}, + {goarch: "386", instruction: "VPCMPESTRM $7, X0, X16"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", ",", "", "$", "", ".", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's packed-string tables", test.instruction) + } + }) + } +} + +func TestAMD64PackedStringCompareRuntimeSemanticsAndFlags(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT packedstringcomparesemantics(SB),NOSPLIT,$0-40 + MOVQ left+0(FP), SI + MOVOU (SI), X1 + MOVQ right+8(FP), DI + MOVOU (DI), X2 + MOVQ out+16(FP), BX + MOVQ lenLeft+24(FP), AX + MOVQ lenRight+32(FP), DX + + PCMPESTRI $12, X2, X1 + MOVQ CX, 0(BX) + SETCS 8(BX) + SETEQ 9(BX) + SETLT 10(BX) + SETOS 11(BX) + SETPS 12(BX) + + PCMPESTRM $64, X2, X1 + MOVOU X0, 16(BX) + SETCS 32(BX) + SETEQ 33(BX) + SETLT 34(BX) + SETOS 35(BX) + SETPS 36(BX) + + VPCMPISTRI $0, X2, X1 + MOVQ CX, 40(BX) + SETCS 48(BX) + SETEQ 49(BX) + SETLT 50(BX) + SETOS 51(BX) + SETPS 52(BX) + + VPCMPISTRM $64, X2, X1 + MOVOU X0, 56(BX) + SETCS 72(BX) + SETEQ 73(BX) + SETLT 74(BX) + SETOS 75(BX) + SETPS 76(BX) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"packedstringcomparesemantics": { + Name: "packedstringcomparesemantics", Args: []LLVMType{Ptr, Ptr, Ptr, I64, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: I64, Index: 3, Field: -1}, + {Offset: 32, Type: I64, Index: 4, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +#include +extern void packedstringcomparesemantics(const uint8_t *, const uint8_t *, uint8_t *, uint64_t, uint64_t); +static uint64_t load64(const uint8_t *p) { uint64_t v; memcpy(&v, p, 8); return v; } +static int flags_equal(const uint8_t *p, int c, int z, int s, int o) { + return p[0] == c && p[1] == z && p[2] == (s ^ o) && p[3] == o && p[4] == 0; +} +__attribute__((target("sse4.2"))) static int check(void) { + const uint8_t left[16] = {'a','b','c','d','e',0,'x','y','z',0,1,2,3,4,5,6}; + const uint8_t right[16] = {'q','q','a','b','c','d','e',0,'x',0,9,8,7,6,5,4}; + const int la = 5, lb = 9; + uint8_t out[80] = {0}, want[16]; + __m128i a = _mm_loadu_si128((const __m128i *)left); + __m128i b = _mm_loadu_si128((const __m128i *)right); + packedstringcomparesemantics(left, right, out, la, lb); + if (load64(out) != (uint64_t)_mm_cmpestri(a, la, b, lb, 12)) return 10; + if (!flags_equal(out + 8, _mm_cmpestrc(a,la,b,lb,12), _mm_cmpestrz(a,la,b,lb,12), _mm_cmpestrs(a,la,b,lb,12), _mm_cmpestro(a,la,b,lb,12))) return 11; + _mm_storeu_si128((__m128i *)want, _mm_cmpestrm(a,la,b,lb,64)); + if (memcmp(out + 16, want, 16)) return 12; + if (!flags_equal(out + 32, _mm_cmpestrc(a,la,b,lb,64), _mm_cmpestrz(a,la,b,lb,64), _mm_cmpestrs(a,la,b,lb,64), _mm_cmpestro(a,la,b,lb,64))) return 13; + if (load64(out + 40) != (uint64_t)_mm_cmpistri(a,b,0)) return 14; + if (!flags_equal(out + 48, _mm_cmpistrc(a,b,0), _mm_cmpistrz(a,b,0), _mm_cmpistrs(a,b,0), _mm_cmpistro(a,b,0))) return 15; + _mm_storeu_si128((__m128i *)want, _mm_cmpistrm(a,b,64)); + if (memcmp(out + 56, want, 16)) return 16; + if (!flags_equal(out + 72, _mm_cmpistrc(a,b,64), _mm_cmpistrz(a,b,64), _mm_cmpistrs(a,b,64), _mm_cmpistro(a,b,64))) return 17; + return 0; +} +int main(void) { return check(); } +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "packed_string_compare_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_subvec.go b/amd64_lower_subvec.go new file mode 100644 index 00000000..f6c6c59c --- /dev/null +++ b/amd64_lower_subvec.go @@ -0,0 +1,252 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PackedSubtractMode uint8 + +const ( + amd64PackedSubtractWrap amd64PackedSubtractMode = iota + amd64PackedSubtractSignedSaturating + amd64PackedSubtractUnsignedSaturating +) + +// lowerPackedIntegerSubtract implements the complete Go 1.27 packed-integer +// subtract family: legacy yxm XMM forms and the shared _yvandnpd VEX/EVEX +// forms, including the 386 frontend's narrower EVEX surface. +func (c *amd64Ctx) lowerPackedIntegerSubtract(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits, mode, vector, recognized := amd64PackedSubtractProperties(baseOp) + if !recognized { + return false, false, nil + } + if !vector { + if suffix != "" { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + return c.lowerLegacyPackedIntegerSubtract(baseOp, laneBits, mode, ins) + } + return c.lowerVectorPackedIntegerSubtract(baseOp, suffix, laneBits, mode, ins) +} + +func amd64PackedSubtractProperties(op string) (laneBits int, mode amd64PackedSubtractMode, vector, ok bool) { + switch op { + case "PSUBB": + return 8, amd64PackedSubtractWrap, false, true + case "PSUBW": + return 16, amd64PackedSubtractWrap, false, true + case "PSUBL": + return 32, amd64PackedSubtractWrap, false, true + case "PSUBQ": + return 64, amd64PackedSubtractWrap, false, true + case "PSUBSB": + return 8, amd64PackedSubtractSignedSaturating, false, true + case "PSUBSW": + return 16, amd64PackedSubtractSignedSaturating, false, true + case "PSUBUSB": + return 8, amd64PackedSubtractUnsignedSaturating, false, true + case "PSUBUSW": + return 16, amd64PackedSubtractUnsignedSaturating, false, true + case "VPSUBB": + return 8, amd64PackedSubtractWrap, true, true + case "VPSUBW": + return 16, amd64PackedSubtractWrap, true, true + case "VPSUBD": + return 32, amd64PackedSubtractWrap, true, true + case "VPSUBQ": + return 64, amd64PackedSubtractWrap, true, true + case "VPSUBSB": + return 8, amd64PackedSubtractSignedSaturating, true, true + case "VPSUBSW": + return 16, amd64PackedSubtractSignedSaturating, true, true + case "VPSUBUSB": + return 8, amd64PackedSubtractUnsignedSaturating, true, true + case "VPSUBUSW": + return 16, amd64PackedSubtractUnsignedSaturating, true, true + default: + return 0, 0, false, false + } +} + +func (c *amd64Ctx) lowerLegacyPackedIntegerSubtract(baseOp string, laneBits int, mode amd64PackedSubtractMode, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg || !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("%s %s expects X/m128, X: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s register source is outside the legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s source must be X or memory: %q", c.goarch, baseOp, ins.Raw) + } + firstBytes, err := c.loadPackedCompareBytes(ins.Args[0], 16) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + lanes := 128 / laneBits + first := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, secondBytes) + result := c.emitPackedIntegerSubtract(lanes, laneBits, first, second, mode) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, lanes, laneBits, result) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedIntegerSubtract(baseOp, suffix string, laneBits int, mode amd64PackedSubtractMode, ins Instr) (bool, bool, error) { + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s has a suffix absent from its Go 1.27 optab: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast && baseOp != "VPSUBD" && baseOp != "VPSUBQ" { + return true, false, fmt.Errorf("%s %s does not enable EVEX broadcast: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects src1, src2, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects a vector-register destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s expects an X, Y, or Z destination: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && byteWidth == 64 { + return true, false, fmt.Errorf("386 %s has no Z-width form in Go 1.27's assembler frontend: %q", baseOp, ins.Raw) + } + if !amd64EVEXVectorRegister(dstArg, byteWidth) || !amd64EVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s second source and destination must be same-width vector registers: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast { + if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory first source: %q", c.goarch, baseOp, ins.Raw) + } + } else if ins.Args[0].Kind == OpReg { + if !amd64EVEXVectorRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match its destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + maskArg := ins.Args[2] + if !amd64NonzeroKOperand(maskArg) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + var err error + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + lanes := byteWidth * 8 / laneBits + var first string + var err error + if broadcast { + first, err = c.evalIntSized(ins.Args[0], amd64IntegerTypeForBits(laneBits)) + if err == nil { + first = amd64SplatInteger(c, lanes, laneBits, first) + } + } else { + var firstBytes string + firstBytes, err = c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err == nil { + first = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, firstBytes) + } + } + if err != nil { + return true, false, err + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + second := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, secondBytes) + result := c.emitPackedIntegerSubtract(lanes, laneBits, first, second, mode) + if masked { + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +// emitPackedIntegerSubtract computes second-first, matching Go assembler's +// rm,v,destination operand order. +func (c *amd64Ctx) emitPackedIntegerSubtract(lanes, laneBits int, first, second string, mode amd64PackedSubtractMode) string { + vecType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + if mode == amd64PackedSubtractWrap { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s %s, %s\n", result, vecType, second, first) + return "%" + result + } + + wideBits := laneBits * 2 + wideType := fmt.Sprintf("<%d x i%d>", lanes, wideBits) + extend := "sext" + if mode == amd64PackedSubtractUnsignedSaturating { + extend = "zext" + } + firstWide := c.newTmp() + secondWide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", firstWide, extend, vecType, first, wideType) + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", secondWide, extend, vecType, second, wideType) + difference := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s %%%s, %%%s\n", difference, wideType, secondWide, firstWide) + + clamped := "%" + difference + minValue := int64(0) + if mode == amd64PackedSubtractSignedSaturating { + minValue = -int64(uint64(1) << (laneBits - 1)) + } + below := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt %s %s, %s\n", below, wideType, clamped, llvmSplatSignedInteger(lanes, wideBits, minValue)) + boundedBelow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %s\n", boundedBelow, lanes, below, wideType, llvmSplatSignedInteger(lanes, wideBits, minValue), wideType, clamped) + clamped = "%" + boundedBelow + if mode == amd64PackedSubtractSignedSaturating { + maxValue := int64((uint64(1) << (laneBits - 1)) - 1) + above := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp sgt %s %s, %s\n", above, wideType, clamped, llvmSplatSignedInteger(lanes, wideBits, maxValue)) + boundedAbove := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %s\n", boundedAbove, lanes, above, wideType, llvmSplatSignedInteger(lanes, wideBits, maxValue), wideType, clamped) + clamped = "%" + boundedAbove + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", result, wideType, clamped, vecType) + return "%" + result +} diff --git a/amd64_lower_svm.go b/amd64_lower_svm.go new file mode 100644 index 00000000..e8b3a015 --- /dev/null +++ b/amd64_lower_svm.go @@ -0,0 +1,85 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerAMDSystemManagement implements AMD's fixed no-operand 0F 01 D8-DF +// family. Their architectural operands are implicit: VMRUN/VMLOAD/VMSAVE use +// rAX, SKINIT uses EAX, INVLPGA uses rAX and ECX, and VMMCALL follows the common +// KVM hypercall convention with rAX as the result and rBX/rCX/rDX/rSI as input +// arguments. The remaining instructions have no general-register operands. +func (c *amd64Ctx) lowerAMDSystemManagement(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + switch baseOp { + case "VMRUN", "VMMCALL", "VMLOAD", "VMSAVE", "STGI", "CLGI", "SKINIT", "INVLPGA": + // handled below + default: + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, baseOp, ins.Raw) + } + + wordType := I64 + if c.goarch == "386" { + wordType = I32 + } + loadWordReg := func(reg Reg) (string, error) { + return c.evalIntSized(Operand{Kind: OpReg, Reg: reg}, wordType) + } + clobbers := "~{dirflag},~{fpsr},~{flags},~{memory}" + switch baseOp { + case "STGI", "CLGI": + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q()\n", strings.ToLower(baseOp), clobbers) + case "VMRUN", "VMLOAD", "VMSAVE": + ax, err := loadWordReg(AX) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s %s)\n", strings.ToLower(baseOp), "{ax},"+clobbers, wordType, ax) + case "SKINIT": + ax, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, I32) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect \"skinit\", %q(i32 %s)\n", "{ax},"+clobbers, ax) + case "INVLPGA": + ax, err := loadWordReg(AX) + if err != nil { + return true, false, err + } + cx, err := c.evalIntSized(Operand{Kind: OpReg, Reg: CX}, I32) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect \"invlpga\", %q(%s %s, i32 %s)\n", "{ax},{cx},"+clobbers, wordType, ax, cx) + case "VMMCALL": + regs := []Reg{AX, BX, CX, DX, SI} + args := make([]string, len(regs)) + for i, reg := range regs { + value, err := loadWordReg(reg) + if err != nil { + return true, false, err + } + args[i] = value + } + call := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect \"vmmcall\", %q(%s %s, %s %s, %s %s, %s %s, %s %s)\n", + call, wordType, "={ax},0,{bx},{cx},{dx},{si},"+clobbers, + wordType, args[0], wordType, args[1], wordType, args[2], wordType, args[3], wordType, args[4], + ) + if err := c.storeRegSized(AX, wordType, "%"+call); err != nil { + return true, false, err + } + } + return true, false, nil +} diff --git a/amd64_lower_syscall.go b/amd64_lower_syscall.go index 8fa1ce4a..0e8d68a8 100644 --- a/amd64_lower_syscall.go +++ b/amd64_lower_syscall.go @@ -7,6 +7,20 @@ import ( func (c *amd64Ctx) lowerSyscall(op Op, ins Instr) (ok bool, terminated bool, err error) { switch op { + case "HLT": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("x86 HLT expects no operands: %q", ins.Raw) + } + c.b.WriteString(" call void asm sideeffect \"hlt\", \"~{memory}\"()\n") + c.b.WriteString(" unreachable\n") + return true, true, nil + case "UD2": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("x86 UD2 expects no operands: %q", ins.Raw) + } + c.b.WriteString(" call void asm sideeffect \"ud2\", \"~{memory}\"()\n") + c.b.WriteString(" unreachable\n") + return true, true, nil case "INT": if c.goarch == "386" && (len(ins.Args) != 1 || ins.Args[0].Kind != OpImm) { return true, false, fmt.Errorf("386 INT expects an immediate vector: %q", ins.Raw) diff --git a/amd64_lower_system_address.go b/amd64_lower_system_address.go new file mode 100644 index 00000000..c5ed43fa --- /dev/null +++ b/amd64_lower_system_address.go @@ -0,0 +1,134 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64SystemAddressKind uint8 + +const ( + amd64SystemAddressInvalidatePage amd64SystemAddressKind = iota + amd64SystemAddressInvalidatePCID + amd64SystemAddressDemoteCacheLine +) + +type amd64SystemAddressSpec struct { + kind amd64SystemAddressKind + memoryBytes int + register bool +} + +// amd64SystemAddressSpecs is the complete Go 1.27 address-shaped system +// instruction grammar. The single-memory and memory-plus-register rows share +// memory/address validation; register compatibility closures are represented +// explicitly and trap just as their architecturally invalid ModRM encodings do. +var amd64SystemAddressSpecs = map[Op]amd64SystemAddressSpec{ + "INVLPG": {kind: amd64SystemAddressInvalidatePage, memoryBytes: 1}, + "INVPCID": {kind: amd64SystemAddressInvalidatePCID, memoryBytes: 16, register: true}, + "CLDEMOTE": {kind: amd64SystemAddressDemoteCacheLine, memoryBytes: 1}, +} + +type amd64SystemAddressForm struct { + memory Operand + register Reg + invalidModRM bool +} + +func (c *amd64Ctx) lowerSystemAddress(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64SystemAddressSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + form, err := c.parseSystemAddressForm(baseOp, spec, ins) + if err != nil { + return true, false, err + } + return c.emitSystemAddress(baseOp, spec, form) +} + +func (c *amd64Ctx) parseSystemAddressForm(op string, spec amd64SystemAddressSpec, ins Instr) (amd64SystemAddressForm, error) { + var form amd64SystemAddressForm + wantArgs := 1 + if spec.register { + wantArgs = 2 + } + if len(ins.Args) != wantArgs { + return form, fmt.Errorf("%s %s expects %d operand(s): %q", c.goarch, op, wantArgs, ins.Raw) + } + address := ins.Args[0] + if isAMD64MemoryOperand(address) { + if address.Kind == OpMem && !x86MemoryRegistersValidForArch(address.Mem, c.goarch) { + return form, fmt.Errorf("%s %s address uses an out-of-range register: %q", c.goarch, op, ins.Raw) + } + form.memory = address + } else if address.Kind == OpReg && spec.kind != amd64SystemAddressDemoteCacheLine { + valid := isX86YrlRegisterForArch(address.Reg, c.goarch) + if spec.kind == amd64SystemAddressInvalidatePage { + valid = isGoYmbRegisterForArch(address.Reg, c.goarch) + } + if !valid { + return form, fmt.Errorf("%s %s first operand is outside Go 1.27's compatibility class: %q", c.goarch, op, ins.Raw) + } + form.invalidModRM = true + } else { + return form, fmt.Errorf("%s %s expects Go 1.27 memory/address form: %q", c.goarch, op, ins.Raw) + } + if spec.register { + typeOperand := ins.Args[1] + if typeOperand.Kind != OpReg || !isX86YrlRegisterForArch(typeOperand.Reg, c.goarch) { + return form, fmt.Errorf("%s %s type operand must be a Go 1.27 Yrl register: %q", c.goarch, op, ins.Raw) + } + form.register = typeOperand.Reg + } + return form, nil +} + +func (c *amd64Ctx) emitSystemAddress(op string, spec amd64SystemAddressSpec, form amd64SystemAddressForm) (bool, bool, error) { + if form.invalidModRM { + c.b.WriteString(" call void asm sideeffect \"ud2\", \"~{memory}\"()\n") + c.b.WriteString(" unreachable\n") + return true, true, nil + } + pointer, pointerType, err := c.x86DescriptorMemoryPointer(form.memory) + if err != nil { + return true, false, err + } + clobbers := "~{memory},~{dirflag},~{fpsr},~{flags}" + if spec.kind != amd64SystemAddressInvalidatePCID { + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s elementtype([%d x i8]) %s)\n", + strings.ToLower(op)+" $0", "*m,"+clobbers, pointerType, spec.memoryBytes, pointer) + return true, false, nil + } + + if c.goarch == "386" { + // INVPCID is a 64-bit-mode instruction, but Go 1.27 accepts it for + // 386. Reproduce Go's 66 0F 38 82 /r encoding with the calculated + // address fixed in EBX and the type fixed in EAX. In 32-bit mode the + // bytes fault architecturally, but remain object-level compatible. + address := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ptrtoint %s %s to i32\n", address, pointerType, pointer) + typeValue, err := c.evalIntSized(Operand{Kind: OpReg, Reg: form.register}, I32) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(i32 %%%s, i32 %s)\n", + ".byte 0x66, 0x0f, 0x38, 0x82, 0x03", "{bx},{ax},"+clobbers, address, typeValue) + return true, false, nil + } + typeValue, err := c.evalIntSized(Operand{Kind: OpReg, Reg: form.register}, I64) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s elementtype([16 x i8]) %s, i64 %s)\n", + "invpcid $0, $1", "*m,r,"+clobbers, pointerType, pointer, typeValue) + return true, false, nil +} diff --git a/amd64_lower_system_address_test.go b/amd64_lower_system_address_test.go new file mode 100644 index 00000000..c18ffd91 --- /dev/null +++ b/amd64_lower_system_address_test.go @@ -0,0 +1,111 @@ +package plan9asm + +import ( + "reflect" + "strings" + "testing" +) + +func TestAMD64SystemAddressGrammarIsComplete(t *testing.T) { + want := map[Op]amd64SystemAddressSpec{ + "INVLPG": {kind: amd64SystemAddressInvalidatePage, memoryBytes: 1}, + "INVPCID": {kind: amd64SystemAddressInvalidatePCID, memoryBytes: 16, register: true}, + "CLDEMOTE": {kind: amd64SystemAddressDemoteCacheLine, memoryBytes: 1}, + } + if !reflect.DeepEqual(amd64SystemAddressSpecs, want) { + t.Fatalf("system-address grammar = %+v, want %+v", amd64SystemAddressSpecs, want) + } +} + +func TestTranslateX86SystemAddressCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + base := "BX" + if target.goarch == "amd64" { + base = "R11" + } + source := "TEXT systemaddressforms(SB),$0-0\n" + + "\tINVLPG 8(" + base + ")\n" + + "\tCLDEMOTE 16(" + base + ")\n" + + "\tINVPCID 32(" + base + "), AX\n" + + "\tRET\n" + + "TEXT invlpgcompat(SB),$0-0\n\tINVLPG AX\n" + + "TEXT invpcidcompat(SB),$0-0\n\tINVPCID AX, BX\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "systemaddressforms": {Name: "systemaddressforms", Ret: Void}, + "invlpgcompat": {Name: "invlpgcompat", Ret: Void}, + "invpcidcompat": {Name: "invpcidcompat", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+cldemote,+invpcid"`, `asm sideeffect "ud2"`, "unreachable"} { + if !strings.Contains(ir, want) { + t.Errorf("IR is missing %s:\n%s", want, ir) + } + } + if target.goarch == "386" && !strings.Contains(ir, ".byte 0x66, 0x0f, 0x38, 0x82, 0x03") { + t.Errorf("386 IR is missing Go-compatible INVPCID encoding:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "system-address-"+target.name+".ll", "system-address-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86SystemAddressRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "INVLPG X1"}, + {goarch: "amd64", instruction: "INVLPG.Z (BX)"}, + {goarch: "amd64", instruction: "CLDEMOTE AX"}, + {goarch: "amd64", instruction: "CLDEMOTE (BX), (CX)"}, + {goarch: "amd64", instruction: "INVPCID (BX), X1"}, + {goarch: "amd64", instruction: "INVPCID X1, BX"}, + {goarch: "amd64", instruction: "INVPCID (BX)"}, + {goarch: "386", instruction: "INVLPG (R11)"}, + {goarch: "386", instruction: "CLDEMOTE (R11)"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's system-address tables", test.instruction) + } + }) + } +} diff --git a/amd64_lower_system_transfer.go b/amd64_lower_system_transfer.go new file mode 100644 index 00000000..149b571e --- /dev/null +++ b/amd64_lower_system_transfer.go @@ -0,0 +1,117 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64SystemTransferKind uint8 + +const ( + amd64SystemEnter amd64SystemTransferKind = iota + amd64SystemExit + amd64SystemReturn +) + +type amd64SystemTransferInputs uint8 + +const ( + amd64SystemTransferCX amd64SystemTransferInputs = 1 << iota + amd64SystemTransferDX + amd64SystemTransferR11 +) + +type amd64SystemTransferSpec struct { + kind amd64SystemTransferKind + mode64 bool + inputs amd64SystemTransferInputs +} + +// amd64SystemTransferSpecs is the complete Go 1.27 SYSENTER/SYSEXIT/SYSRET +// grammar. SYSCALL is intentionally separate because plan9asm provides a +// hosted libc-backed syscall implementation for it. These raw architectural +// transfers retain exact Go bytes and explicitly materialize the GP registers +// consumed by their exit/return conventions. +var amd64SystemTransferSpecs = map[Op]amd64SystemTransferSpec{ + "SYSENTER": {kind: amd64SystemEnter}, + "SYSENTER64": {kind: amd64SystemEnter, mode64: true}, + "SYSEXIT": {kind: amd64SystemExit, inputs: amd64SystemTransferCX | amd64SystemTransferDX}, + "SYSEXIT64": {kind: amd64SystemExit, mode64: true, inputs: amd64SystemTransferCX | amd64SystemTransferDX}, + "SYSRET": {kind: amd64SystemReturn, inputs: amd64SystemTransferCX | amd64SystemTransferR11}, +} + +func (spec amd64SystemTransferSpec) terminates() bool { + return spec.kind != amd64SystemEnter +} + +func (spec amd64SystemTransferSpec) encoding() string { + var opcode byte + switch spec.kind { + case amd64SystemEnter: + opcode = 0x34 + case amd64SystemExit: + opcode = 0x35 + case amd64SystemReturn: + opcode = 0x07 + default: + panic("unknown amd64 system-transfer kind") + } + if spec.mode64 { + return fmt.Sprintf(".byte 0x48, 0x0f, 0x%02x", opcode) + } + return fmt.Sprintf(".byte 0x0f, 0x%02x", opcode) +} + +func (c *amd64Ctx) lowerSystemTransfer(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64SystemTransferSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && spec.mode64 { + return true, false, fmt.Errorf("386 %s is absent from Go 1.27's 32-bit encoding table: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, baseOp, ins.Raw) + } + constraints := make([]string, 0, 7) + arguments := make([]string, 0, 3) + for _, input := range []struct { + bit amd64SystemTransferInputs + reg Reg + constraint string + }{ + {bit: amd64SystemTransferCX, reg: CX, constraint: "{cx}"}, + {bit: amd64SystemTransferDX, reg: DX, constraint: "{dx}"}, + {bit: amd64SystemTransferR11, reg: Reg("R11"), constraint: "{r11}"}, + } { + if spec.inputs&input.bit == 0 || (c.goarch == "386" && input.bit == amd64SystemTransferR11) { + continue + } + typ := I32 + if spec.mode64 || spec.kind == amd64SystemReturn { + typ = I64 + } + value, err := c.evalIntSized(Operand{Kind: OpReg, Reg: input.reg}, typ) + if err != nil { + return true, false, err + } + constraints = append(constraints, input.constraint) + arguments = append(arguments, fmt.Sprintf("%s %s", typ, value)) + } + constraints = append(constraints, "~{memory}", "~{dirflag}", "~{fpsr}", "~{flags}") + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s)\n", + spec.encoding(), strings.Join(constraints, ","), strings.Join(arguments, ", ")) + if !spec.terminates() { + return true, false, nil + } + c.b.WriteString(" unreachable\n") + return true, true, nil +} diff --git a/amd64_lower_system_transfer_test.go b/amd64_lower_system_transfer_test.go new file mode 100644 index 00000000..58823da9 --- /dev/null +++ b/amd64_lower_system_transfer_test.go @@ -0,0 +1,135 @@ +package plan9asm + +import ( + "reflect" + "strings" + "testing" +) + +func TestAMD64SystemTransferGrammarIsComplete(t *testing.T) { + want := map[Op]amd64SystemTransferSpec{ + "SYSENTER": {kind: amd64SystemEnter}, + "SYSENTER64": {kind: amd64SystemEnter, mode64: true}, + "SYSEXIT": {kind: amd64SystemExit, inputs: amd64SystemTransferCX | amd64SystemTransferDX}, + "SYSEXIT64": {kind: amd64SystemExit, mode64: true, inputs: amd64SystemTransferCX | amd64SystemTransferDX}, + "SYSRET": {kind: amd64SystemReturn, inputs: amd64SystemTransferCX | amd64SystemTransferR11}, + } + if !reflect.DeepEqual(amd64SystemTransferSpecs, want) { + t.Fatalf("system-transfer grammar = %+v, want %+v", amd64SystemTransferSpecs, want) + } +} + +func TestTranslateX86SystemTransferCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := `TEXT sysenterform(SB),$0-0 + SYSENTER + RET +TEXT sysexitform(SB),$0-0 + SYSEXIT +TEXT sysretform(SB),$0-0 + SYSRET +` + sigs := map[string]FuncSig{ + "sysenterform": {Name: "sysenterform", Ret: Void}, + "sysexitform": {Name: "sysexitform", Ret: Void}, + "sysretform": {Name: "sysretform", Ret: Void}, + } + if target.goarch == "amd64" { + source += `TEXT sysenter64form(SB),$0-0 + SYSENTER64 + RET +TEXT sysexit64form(SB),$0-0 + SYSEXIT64 +` + sigs["sysenter64form"] = FuncSig{Name: "sysenter64form", Ret: Void} + sigs["sysexit64form"] = FuncSig{Name: "sysexit64form", Ret: Void} + } + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: target.goarch, TargetTriple: target.triple, Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `.byte 0x0f, 0x34`, + `.byte 0x0f, 0x35`, + `.byte 0x0f, 0x07`, + `{cx},{dx},~{memory}`, + } { + if !strings.Contains(ir, want) { + t.Errorf("IR is missing %s:\n%s", want, ir) + } + } + wantUnreachable := 2 + if target.goarch == "amd64" { + wantUnreachable = 3 + for _, want := range []string{ + `.byte 0x48, 0x0f, 0x34`, + `.byte 0x48, 0x0f, 0x35`, + `{cx},{r11},~{memory}`, + } { + if !strings.Contains(ir, want) { + t.Errorf("amd64 IR is missing %s:\n%s", want, ir) + } + } + } + if got := strings.Count(ir, "unreachable"); got != wantUnreachable { + t.Errorf("unreachable count = %d, want %d", got, wantUnreachable) + } + compileLLVMToObject(t, llc, target.triple, "system-transfer-"+target.name+".ll", "system-transfer-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86SystemTransferRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "SYSENTER AX"}, + {goarch: "amd64", instruction: "SYSENTER64.P"}, + {goarch: "amd64", instruction: "SYSEXIT AX"}, + {goarch: "amd64", instruction: "SYSEXIT64 AX"}, + {goarch: "amd64", instruction: "SYSRET AX"}, + {goarch: "386", instruction: "SYSENTER64"}, + {goarch: "386", instruction: "SYSEXIT64"}, + {goarch: "386", instruction: "SYSRET.P"}, + } { + t.Run(test.goarch+"_"+strings.ReplaceAll(test.instruction, " ", "_"), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's system-transfer tables", test.instruction) + } + }) + } +} diff --git a/amd64_lower_ternary_logic.go b/amd64_lower_ternary_logic.go new file mode 100644 index 00000000..991a1d45 --- /dev/null +++ b/amd64_lower_ternary_logic.go @@ -0,0 +1,200 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// amd64TernaryLogicSpecs is the complete Go 1.27 VPTERNLOG family. Both +// opcodes use _yvalignd; the only difference is the D/Q mask-lane and +// broadcast width. +var amd64TernaryLogicSpecs = map[Op]int{ + "VPTERNLOGD": 32, + "VPTERNLOGQ": 64, +} + +func (c *amd64Ctx) lowerTernaryLogic(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits, recognized := amd64TernaryLogicSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + // The 386 obj assembler rejects this family's required four/five source + // operands before it reaches _yvalignd. Mirror that frontend behavior. + if c.goarch != "amd64" { + return true, false, fmt.Errorf("%s %s is rejected by Go 1.27's x86 assembler operand limit: %q", c.goarch, baseOp, ins.Raw) + } + + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("amd64 %s has a suffix absent from Go 1.27's EVEX encoding: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 4 && len(ins.Args) != 5 { + return true, false, fmt.Errorf("amd64 %s expects unsigned-imm8, src1, src2, [K mask,] destination: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 5 + if zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s zeroing requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("amd64 %s first operand must be Go 1.27's unsigned-imm8 class: %q", baseOp, ins.Raw) + } + + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s destination must be an X, Y, or Z register: %q", baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !amd64EVEXVectorRegister(dstArg, byteWidth) { + return true, false, fmt.Errorf("amd64 %s destination is outside Go 1.27's EVEX vector class: %q", baseOp, ins.Raw) + } + if !amd64EVEXVectorRegister(ins.Args[2], byteWidth) { + return true, false, fmt.Errorf("amd64 %s second source must be a same-width EVEX vector register: %q", baseOp, ins.Raw) + } + if broadcast { + if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory first source: %q", baseOp, ins.Raw) + } + } else if ins.Args[1].Kind == OpReg { + if !amd64EVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("amd64 %s first source must match the destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s first source must be a vector register or memory: %q", baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[3]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(ins.Args[3].Reg) + if err != nil { + return true, false, err + } + } + + var firstBytes string + if broadcast { + lanes := byteWidth * 8 / laneBits + scalar, loadErr := c.evalIntSized(ins.Args[1], amd64IntegerTypeForBits(laneBits)) + if loadErr != nil { + return true, false, loadErr + } + firstLanes := amd64SplatInteger(c, lanes, laneBits, scalar) + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", cast, lanes, laneBits, firstLanes, byteWidth) + firstBytes = "%" + cast + } else { + firstBytes, err = c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[2], byteWidth) + if err != nil { + return true, false, err + } + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + + // Intel names the inputs A=old destination, B=EVEX.vvvv, C=EVEX.r/m. + // Go's Zevex_i_rm_v_r source order is therefore imm, C, B, A. + resultBytes := c.emitTernaryLogicBytes(byteWidth, uint8(ins.Args[0].Imm), oldBytes, secondBytes, firstBytes) + if masked { + lanes := byteWidth * 8 / laneBits + computed := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, resultBytes) + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result := amd64ApplyIntegerLaneMask(c, lanes, laneBits, computed, old, mask, zeroing) + cast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", cast, lanes, laneBits, result, byteWidth) + resultBytes = "%" + cast + } + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, resultBytes) +} + +// emitTernaryLogicBytes evaluates all 256 bitwise Boolean truth tables. The +// immediate bit selected for an input tuple is (A<<2)|(B<<1)|C, matching the +// Intel/Clang _MM_TERNLOG_A/B/C constants F0/CC/AA. +func (c *amd64Ctx) emitTernaryLogicBytes(byteWidth int, immediate uint8, a, b, third string) string { + switch immediate { + case 0x00: + return "zeroinitializer" + case 0xff: + return llvmAllOnesI8Vec(byteWidth) + case 0xf0: + return a + case 0xcc: + return b + case 0xaa: + return third + } + + inputs := []string{a, b, third} + inverted := make([]string, len(inputs)) + for index, input := range inputs { + name := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor <%d x i8> %s, %s\n", name, byteWidth, input, llvmAllOnesI8Vec(byteWidth)) + inverted[index] = "%" + name + } + + result := "" + for truthIndex := 0; truthIndex < 8; truthIndex++ { + truthA := truthIndex&4 != 0 + truthB := truthIndex&2 != 0 + truthC := truthIndex&1 != 0 + if !amd64TernaryLogicBit(immediate, truthA, truthB, truthC) { + continue + } + termInputs := make([]string, 3) + for inputIndex := range inputs { + truthBit := 2 - inputIndex + if truthIndex&(1< %s, %s\n", firstAnd, byteWidth, termInputs[0], termInputs[1]) + term := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and <%d x i8> %%%s, %s\n", term, byteWidth, firstAnd, termInputs[2]) + if result == "" { + result = "%" + term + continue + } + merged := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or <%d x i8> %s, %%%s\n", merged, byteWidth, result, term) + result = "%" + merged + } + return result +} + +func amd64TernaryLogicBit(immediate uint8, a, b, third bool) bool { + truthIndex := 0 + if a { + truthIndex |= 4 + } + if b { + truthIndex |= 2 + } + if third { + truthIndex |= 1 + } + return immediate&(1< 255 { + return form, fmt.Errorf("%s %s immediate must be an unsigned byte: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == wantArgs+1 + if c.goarch == "386" && (hasPassthrough || masked) { + return form, fmt.Errorf("386 %s form exceeds the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if properties.zeroing && !masked { + return form, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + maskIndex := len(ins.Args) - 2 + if masked && !amd64NonzeroKOperand(ins.Args[maskIndex]) { + return form, fmt.Errorf("%s %s masked form expects K1-K7: %q", c.goarch, baseOp, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return form, fmt.Errorf("%s %s destination must be a vector register: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(destination.Reg) + passthrough := Operand{} + if shape.scalar { + passthrough = ins.Args[2] + if byteWidth != 16 || !c.isGoEVEXVectorRegister(destination, 16) || !c.isGoEVEXVectorRegister(passthrough, 16) { + return form, fmt.Errorf("%s %s scalar pass-through and destination must be X registers: %q", c.goarch, baseOp, ins.Raw) + } + } else { + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 || !c.isGoEVEXVectorRegister(destination, byteWidth) { + return form, fmt.Errorf("%s %s packed destination must be an in-range X, Y, or Z register: %q", c.goarch, baseOp, ins.Raw) + } + if shape.twoSource { + passthrough = ins.Args[2] + if !c.isGoEVEXVectorRegister(passthrough, byteWidth) { + return form, fmt.Errorf("%s %s second packed source must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } + } + source := ins.Args[1] + if properties.broadcast { + if !isAMD64MemoryOperand(source) { + return form, fmt.Errorf("%s %s.BCST requires a scalar memory source: %q", c.goarch, baseOp, ins.Raw) + } + } else if source.Kind == OpReg { + if !c.isGoEVEXVectorRegister(source, byteWidth) { + return form, fmt.Errorf("%s %s source register must match the destination width: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return form, fmt.Errorf("%s %s source must be a matching vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if properties.sae && (source.Kind != OpReg || !shape.scalar && byteWidth != 64) { + return form, fmt.Errorf("%s %s.SAE requires a register source and scalar or Z form: %q", c.goarch, baseOp, ins.Raw) + } + mask := "" + if masked { + var err error + mask, err = c.loadK(ins.Args[maskIndex].Reg) + if err != nil { + return form, err + } + } + return amd64UnaryImmediateFloatingForm{ + properties: properties, source: source, passthrough: passthrough, + destination: destination, byteWidth: byteWidth, mask: mask, + immediate: uint8(ins.Args[0].Imm), + }, nil +} diff --git a/amd64_lower_unpack.go b/amd64_lower_unpack.go new file mode 100644 index 00000000..8fa9655d --- /dev/null +++ b/amd64_lower_unpack.go @@ -0,0 +1,280 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerPackedUnpack implements the complete Go 1.27 packed interleave family: +// integer and floating legacy forms plus their VEX/EVEX X/Y/Z counterparts. +// The unusual legacy LWL/HWL and LLQ/HLQ spellings are Go assembler names. +func (c *amd64Ctx) lowerPackedUnpack(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + laneBits, high, vector, legacyMMX, broadcast, recognized := amd64PackedUnpackProperties(baseOp) + if !recognized { + return false, false, nil + } + if !vector { + return c.lowerLegacyPackedUnpack(baseOp, suffix, laneBits, high, legacyMMX, ins) + } + return c.lowerVectorPackedUnpack(baseOp, suffix, laneBits, high, broadcast, ins) +} + +func amd64PackedUnpackProperties(op string) (laneBits int, high, vector, legacyMMX, broadcast, ok bool) { + switch op { + case "PUNPCKLBW": + return 8, false, false, true, false, true + case "PUNPCKHBW": + return 8, true, false, true, false, true + case "PUNPCKLWL": + return 16, false, false, true, false, true + case "PUNPCKHWL": + return 16, true, false, true, false, true + case "PUNPCKLLQ": + return 32, false, false, true, false, true + case "PUNPCKHLQ": + return 32, true, false, true, false, true + case "PUNPCKLQDQ": + return 64, false, false, false, false, true + case "PUNPCKHQDQ": + return 64, true, false, false, false, true + case "UNPCKLPS": + return 32, false, false, false, false, true + case "UNPCKHPS": + return 32, true, false, false, false, true + case "UNPCKLPD": + return 64, false, false, false, false, true + case "UNPCKHPD": + return 64, true, false, false, false, true + case "VPUNPCKLBW": + return 8, false, true, false, false, true + case "VPUNPCKHBW": + return 8, true, true, false, false, true + case "VPUNPCKLWD": + return 16, false, true, false, false, true + case "VPUNPCKHWD": + return 16, true, true, false, false, true + case "VPUNPCKLDQ": + return 32, false, true, false, true, true + case "VPUNPCKHDQ": + return 32, true, true, false, true, true + case "VPUNPCKLQDQ": + return 64, false, true, false, true, true + case "VPUNPCKHQDQ": + return 64, true, true, false, true, true + case "VUNPCKLPS": + return 32, false, true, false, true, true + case "VUNPCKHPS": + return 32, true, true, false, true, true + case "VUNPCKLPD": + return 64, false, true, false, true, true + case "VUNPCKHPD": + return 64, true, true, false, true, true + default: + return 0, false, false, false, false, false + } +} + +func (c *amd64Ctx) lowerLegacyPackedUnpack(baseOp, suffix string, laneBits int, high, legacyMMX bool, ins Instr) (bool, bool, error) { + if suffix != "" { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects packed source, packed destination: %q", c.goarch, baseOp, ins.Raw) + } + dst := ins.Args[1].Reg + if _, mmx := amd64ParseMReg(dst); mmx { + if !legacyMMX { + return true, false, fmt.Errorf("%s %s has no MMX row in Go 1.27's yxm table: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch != "amd64" { + return true, false, fmt.Errorf("386 %s MMX form is illegal in 32-bit mode: %q", baseOp, ins.Raw) + } + firstBits, err := c.loadLegacyMMXPackedSource(ins.Args[0]) + if err != nil { + return true, false, fmt.Errorf("amd64 %s MMX source: %w", baseOp, err) + } + secondBits, err := c.loadReg(dst) + if err != nil { + return true, false, err + } + lanes := 64 / laneBits + first := c.bitcastI64ToIntegerLanes(lanes, laneBits, firstBits) + second := c.bitcastI64ToIntegerLanes(lanes, laneBits, secondBits) + result := c.emitPackedUnpackLanes(8, laneBits, high, first, second) + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to i64\n", bits, lanes, laneBits, result) + return true, false, c.storeReg(dst, "%"+bits) + } + + if !c.isGoLegacyXReg(dst) { + return true, false, fmt.Errorf("%s %s destination is outside Go 1.27's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + if ins.Args[0].Kind == OpReg { + if !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s XMM source is outside Go 1.27's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s source must be X or memory: %q", c.goarch, baseOp, ins.Raw) + } + firstBytes, err := c.loadPackedCompareBytes(ins.Args[0], 16) + if err != nil { + return true, false, err + } + secondBytes, err := c.loadX(dst) + if err != nil { + return true, false, err + } + lanes := 128 / laneBits + first := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, firstBytes) + second := c.bitcastVectorBytesToIntegerLanes(16, lanes, laneBits, secondBytes) + result := c.emitPackedUnpackLanes(16, laneBits, high, first, second) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, lanes, laneBits, result) + return true, false, c.storeX(dst, "%"+out) +} + +func (c *amd64Ctx) lowerVectorPackedUnpack(baseOp, suffix string, laneBits int, high, supportsBroadcast bool, ins Instr) (bool, bool, error) { + broadcast, zeroing := false, false + switch suffix { + case "": + case "Z": + zeroing = true + case "BCST": + broadcast = true + case "BCST.Z": + broadcast, zeroing = true, true + default: + return true, false, fmt.Errorf("%s %s has a suffix absent from its Go 1.27 optab: %q", c.goarch, baseOp, ins.Raw) + } + if broadcast && !supportsBroadcast { + return true, false, fmt.Errorf("%s %s has no broadcast encoding in Go 1.27's optab: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("%s %s expects src1, src2, [K mask,] destination: %q", c.goarch, baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if c.goarch == "386" && masked { + return true, false, fmt.Errorf("386 %s mask forms exceed the Go assembler frontend's three-operand limit: %q", baseOp, ins.Raw) + } + if zeroing && !masked { + return true, false, fmt.Errorf("%s %s zeroing requires a K1-K7 mask: %q", c.goarch, baseOp, ins.Raw) + } + dstArg := ins.Args[len(ins.Args)-1] + if dstArg.Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects a vector-register destination: %q", c.goarch, baseOp, ins.Raw) + } + byteWidth := amd64VectorByteWidth(dstArg.Reg) + if byteWidth != 16 && byteWidth != 32 && byteWidth != 64 { + return true, false, fmt.Errorf("%s %s expects an X, Y, or Z destination: %q", c.goarch, baseOp, ins.Raw) + } + if !amd64EVEXVectorRegister(dstArg, byteWidth) || !amd64EVEXVectorRegister(ins.Args[1], byteWidth) { + return true, false, fmt.Errorf("%s %s second source and destination must be same-width vector registers: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && byteWidth == 64 { + for _, arg := range []Operand{ins.Args[1], dstArg} { + index, _ := amd64VectorRegisterIndex(arg.Reg, byteWidth) + if index >= 8 { + return true, false, fmt.Errorf("386 %s Z register is outside Go 1.27's 32-bit EVEX range: %q", baseOp, ins.Raw) + } + } + } + if broadcast { + if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s.BCST requires a memory first source: %q", c.goarch, baseOp, ins.Raw) + } + } else if ins.Args[0].Kind == OpReg { + if !amd64EVEXVectorRegister(ins.Args[0], byteWidth) { + return true, false, fmt.Errorf("%s %s first source must match its destination width: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && byteWidth == 64 { + index, _ := amd64VectorRegisterIndex(ins.Args[0].Reg, byteWidth) + if index >= 8 { + return true, false, fmt.Errorf("386 %s Z register is outside Go 1.27's 32-bit EVEX range: %q", baseOp, ins.Raw) + } + } + } else if !isAMD64MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("%s %s first source must be a vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + + var mask string + if masked { + if !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + var err error + mask, err = c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + } + lanes := byteWidth * 8 / laneBits + var first string + var err error + if broadcast { + var scalar string + scalar, err = c.evalIntSized(ins.Args[0], amd64IntegerTypeForBits(laneBits)) + if err == nil { + first = amd64SplatInteger(c, lanes, laneBits, scalar) + } + } else { + var firstBytes string + firstBytes, err = c.loadPackedCompareBytes(ins.Args[0], byteWidth) + if err == nil { + first = c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, firstBytes) + } + } + if err != nil { + return true, false, err + } + secondBytes, err := c.loadPackedCompareBytes(ins.Args[1], byteWidth) + if err != nil { + return true, false, err + } + second := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, secondBytes) + result := c.emitPackedUnpackLanes(byteWidth, laneBits, high, first, second) + if masked { + oldBytes, err := c.loadPackedCompareBytes(dstArg, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, laneBits, result, old, mask, zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(dstArg.Reg, byteWidth, "%"+out) +} + +// emitPackedUnpackLanes interleaves the second (vvvv/old destination) source +// with the first (r/m) source independently within each 128-bit vector lane. +func (c *amd64Ctx) emitPackedUnpackLanes(byteWidth, laneBits int, high bool, first, second string) string { + lanes := byteWidth * 8 / laneBits + groupBits := 128 + if byteWidth == 8 { + groupBits = 64 + } + groupLanes := groupBits / laneBits + half := groupLanes / 2 + start := 0 + if high { + start = half + } + mask := make([]string, 0, lanes) + for group := 0; group < lanes/groupLanes; group++ { + base := group * groupLanes + for lane := start; lane < start+half; lane++ { + index := base + lane + mask = append(mask, fmt.Sprintf("i32 %d", index), fmt.Sprintf("i32 %d", lanes+index)) + } + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %s, <%d x i%d> %s, <%d x i32> <%s>\n", + result, lanes, laneBits, second, lanes, laneBits, first, lanes, strings.Join(mask, ", ")) + return "%" + result +} diff --git a/amd64_lower_unpack_float_test.go b/amd64_lower_unpack_float_test.go new file mode 100644 index 00000000..19d91ba3 --- /dev/null +++ b/amd64_lower_unpack_float_test.go @@ -0,0 +1,120 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86FloatingUnpackCompleteGoAssemblerForms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast, zLast := 15, 22 + if target.goarch == "386" { + legacyLast, zLast = 7, 7 + } + var source strings.Builder + source.WriteString("TEXT floatingunpackforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"UNPCKLPS", "UNPCKHPS", "UNPCKLPD", "UNPCKHPD"} { + fmt.Fprintf(&source, "\t%s X0, X%d\n", op, legacyLast) + fmt.Fprintf(&source, "\t%s 8(AX), X%d\n", op, legacyLast) + vector := "V" + op + for _, width := range []string{"X", "Y"} { + fmt.Fprintf(&source, "\t%s %s0, %s1, %s2\n", vector, width, width, width) + fmt.Fprintf(&source, "\t%s 8(AX), %s20, %s21\n", vector, width, width) + fmt.Fprintf(&source, "\t%s.BCST 8(AX), %s20, %s21\n", vector, width, width) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s %s20, %s21, K1, %s22\n", vector, width, width, width) + fmt.Fprintf(&source, "\t%s.BCST.Z 8(AX), %s21, K7, %s22\n", vector, width, width) + } + } + fmt.Fprintf(&source, "\t%s Z0, Z6, Z%d\n", vector, zLast) + fmt.Fprintf(&source, "\t%s 8(AX), Z6, Z%d\n", vector, zLast) + fmt.Fprintf(&source, "\t%s.BCST 8(AX), Z6, Z%d\n", vector, zLast) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s Z20, Z21, K2, Z22\n", vector) + fmt.Fprintf(&source, "\t%s.Z 8(AX), Z21, K6, Z22\n", vector) + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "floatingunpackforms": {Name: "floatingunpackforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "floating-unpack-"+target.name+".ll", "floating-unpack-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86FloatingUnpackRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "UNPCKLPS.Z X0, X1", + "UNPCKHPD X0", + "UNPCKLPD M0, M1", + "UNPCKHPS Y0, X1", + "UNPCKLPS X0, (AX)", + "VUNPCKLPD X0, X1", + "VUNPCKHPS X0, Y1, Y2", + "VUNPCKLPD X0, X1, (AX)", + "VUNPCKHPD X0, X1, K0, X2", + "VUNPCKLPS.Z X0, X1, X2", + "VUNPCKHPS.BCST X0, X1, X2", + "VUNPCKLPD.BCST 8(AX), X1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86FloatingUnpackRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "UNPCKLPS X8, X0", + "UNPCKHPD X0, X8", + "VUNPCKLPD Z8, Z1, Z2", + "VUNPCKHPS Z0, Z1, Z8", + "VUNPCKLPS X0, X1, K1, X2", + "VUNPCKHPD.Z X0, X1, K1, X2", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86FloatingUnpackRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86FloatingUnpackRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's floating unpack forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_variable_shift.go b/amd64_lower_variable_shift.go new file mode 100644 index 00000000..e0fbb7a6 --- /dev/null +++ b/amd64_lower_variable_shift.go @@ -0,0 +1,138 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64PerLaneVariableShiftSpec struct { + laneBits int + operation string + arithmetic bool +} + +var amd64PerLaneVariableShiftSpecs = map[string]amd64PerLaneVariableShiftSpec{ + "VPSLLVW": {laneBits: 16, operation: "shl"}, + "VPSLLVD": {laneBits: 32, operation: "shl"}, + "VPSLLVQ": {laneBits: 64, operation: "shl"}, + "VPSRLVW": {laneBits: 16, operation: "lshr"}, + "VPSRLVD": {laneBits: 32, operation: "lshr"}, + "VPSRLVQ": {laneBits: 64, operation: "lshr"}, + "VPSRAVW": {laneBits: 16, operation: "ashr", arithmetic: true}, + "VPSRAVD": {laneBits: 32, operation: "ashr", arithmetic: true}, + "VPSRAVQ": {laneBits: 64, operation: "ashr", arithmetic: true}, +} + +// lowerPerLaneVariableShift implements the full Go 1.27 per-lane packed +// variable-shift family. The first Plan 9 source supplies one count per lane. +func (c *amd64Ctx) lowerPerLaneVariableShift(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, ok := amd64PerLaneVariableShiftSpecs[baseOp] + if !ok { + return false, false, nil + } + suffixes, err := amd64ParseTwoSourcePermuteSuffixes(rawOp, baseOp) + if err != nil { + return true, false, fmt.Errorf("%w: %q", err, ins.Raw) + } + if suffixes.broadcast && spec.laneBits == 16 { + return true, false, fmt.Errorf("amd64 %s does not enable broadcast in Go 1.27: %q", baseOp, ins.Raw) + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return true, false, fmt.Errorf("amd64 %s expects per-lane counts, source, [K mask,] destination: %q", baseOp, ins.Raw) + } + masked := len(ins.Args) == 4 + if masked && c.goarch == "386" { + return true, false, fmt.Errorf("386 %s masked form exceeds the Go assembler frontend's operand limit: %q", baseOp, ins.Raw) + } + if suffixes.zeroing && !masked { + return true, false, fmt.Errorf("amd64 %s .Z requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + byteWidth := 0 + if destination.Kind == OpReg { + byteWidth = amd64VectorByteWidth(destination.Reg) + } + if byteWidth == 0 || !c.isGoPackedVectorMoveRegister(destination, byteWidth) { + return true, false, fmt.Errorf("amd64 %s expects an in-range X, Y, or Z destination: %q", baseOp, ins.Raw) + } + data := ins.Args[1] + if !c.isGoPackedVectorMoveRegister(data, byteWidth) { + return true, false, fmt.Errorf("amd64 %s data source must match the destination width: %q", baseOp, ins.Raw) + } + counts := ins.Args[0] + if counts.Kind == OpReg { + if !c.isGoPackedVectorMoveRegister(counts, byteWidth) { + return true, false, fmt.Errorf("amd64 %s count register must match the destination width: %q", baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(counts) { + return true, false, fmt.Errorf("amd64 %s counts must be a matching vector register or memory: %q", baseOp, ins.Raw) + } + if suffixes.broadcast && !isAMD64MemoryOperand(counts) { + return true, false, fmt.Errorf("amd64 %s.BCST requires a memory count source: %q", baseOp, ins.Raw) + } + + mask := "" + if masked { + maskArg := ins.Args[2] + if maskArg.Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + maskIndex, validMask := amd64ParseKReg(maskArg.Reg) + if !validMask || maskIndex == 0 { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + + lanes := byteWidth * 8 / spec.laneBits + countValues, err := c.loadPackedCompareLanes(counts, byteWidth, spec.laneBits, suffixes.broadcast) + if err != nil { + return true, false, err + } + dataValues, err := c.loadPackedCompareLanes(data, byteWidth, spec.laneBits, false) + if err != nil { + return true, false, err + } + result := c.emitPerLaneVariableShift(spec, lanes, countValues, dataValues) + if masked { + oldBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + old := c.bitcastVectorBytesToIntegerLanes(byteWidth, lanes, spec.laneBits, oldBytes) + result = amd64ApplyIntegerLaneMask(c, lanes, spec.laneBits, result, old, mask, suffixes.zeroing) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <%d x i8>\n", out, lanes, spec.laneBits, result, byteWidth) + return true, false, c.storeVectorBytes(destination.Reg, byteWidth, "%"+out) +} + +func (c *amd64Ctx) emitPerLaneVariableShift(spec amd64PerLaneVariableShiftSpec, lanes int, counts, data string) string { + typeName := fmt.Sprintf("<%d x i%d>", lanes, spec.laneBits) + limit := amd64SplatInteger(c, lanes, spec.laneBits, fmt.Sprintf("%d", spec.laneBits)) + inRange := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult %s %s, %s\n", inRange, typeName, counts, limit) + fallbackCount := "zeroinitializer" + if spec.arithmetic { + fallbackCount = amd64SplatInteger(c, lanes, spec.laneBits, fmt.Sprintf("%d", spec.laneBits-1)) + } + safeCounts := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %s\n", safeCounts, lanes, inRange, typeName, counts, typeName, fallbackCount) + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %%%s\n", shifted, spec.operation, typeName, data, safeCounts) + if spec.arithmetic { + return "%" + shifted + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %%%s, %s zeroinitializer\n", result, lanes, inRange, typeName, shifted, typeName) + return "%" + result +} diff --git a/amd64_lower_variable_shift_test.go b/amd64_lower_variable_shift_test.go new file mode 100644 index 00000000..08c0f3f5 --- /dev/null +++ b/amd64_lower_variable_shift_test.go @@ -0,0 +1,113 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateX86PerLaneVariableShiftCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 exposes the W/D/Q per-lane left, logical-right, and + // arithmetic-right shifts. Every opcode has X/Y/Z rows and optional K + // masking/.Z; D/Q additionally enable scalar count broadcast. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + lastZ := 20 + if target.goarch == "386" { + lastZ = 7 + } + var source strings.Builder + source.WriteString("TEXT perlanevariableshiftforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{ + "VPSLLVW", "VPSLLVD", "VPSLLVQ", + "VPSRLVW", "VPSRLVD", "VPSRLVQ", + "VPSRAVW", "VPSRAVD", "VPSRAVQ", + } { + fmt.Fprintf(&source, "\t%s X1, X20, X21\n", op) + fmt.Fprintf(&source, "\t%s 8(AX), Y20, Y21\n", op) + fmt.Fprintf(&source, "\t%s Z1, Z2, Z%d\n", op, lastZ) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s X1, X20, K1, X21\n", op) + fmt.Fprintf(&source, "\t%s.Z Y1, Y20, K2, Y21\n", op) + fmt.Fprintf(&source, "\t%s.Z 40(AX), Z20, K3, Z21\n", op) + } + if strings.HasSuffix(op, "D") || strings.HasSuffix(op, "Q") { + fmt.Fprintf(&source, "\t%s.BCST 104(AX), X20, X21\n", op) + fmt.Fprintf(&source, "\t%s.BCST 112(AX), Y20, Y21\n", op) + fmt.Fprintf(&source, "\t%s.BCST 120(AX), Z2, Z%d\n", op, lastZ) + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s.BCST.Z 128(AX), Z20, K4, Z21\n", op) + } + } + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "perlanevariableshiftforms": {Name: "perlanevariableshiftforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "per-lane-variable-shift-"+target.name+".ll", "per-lane-variable-shift-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86PerLaneVariableShiftRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "VPSLLVQ X0, X1", + "VPSLLVQ $1, X1, X2", + "VPSLLVQ X0, Y1, Y2", + "VPSLLVQ X0, (AX), X2", + "VPSLLVQ X0, X1, K0, X2", + "VPSLLVQ X0, X1, AX", + "VPSLLVQ.Z X0, X1, X2", + "VPSLLVQ.BCST X0, X1, X2", + "VPSLLVW.BCST (AX), X1, X2", + "VPSLLVQ.Z.BCST (AX), X1, K1, X2", + "VPSLLVQ.RN_SAE X0, X1, X2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86PerLaneVariableShiftRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + assertX86PerLaneVariableShiftRejected(t, "386", "i386-unknown-linux-gnu", "VPSLLVQ X0, X1, K1, X2") + assertX86PerLaneVariableShiftRejected(t, "386", "i386-unknown-linux-gnu", "VPSLLVQ Z0, Z1, Z8") +} + +func assertX86PerLaneVariableShiftRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's per-lane variable shift forms", instruction) + } +} diff --git a/amd64_lower_vcomi.go b/amd64_lower_vcomi.go new file mode 100644 index 00000000..2d56bd52 --- /dev/null +++ b/amd64_lower_vcomi.go @@ -0,0 +1,84 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerVectorScalarFlagCompare implements the complete Go 1.27 _yvcomisd +// family shared by VCOMISD, VCOMISS, VUCOMISD, and VUCOMISS. The table has +// one VEX X/m,X row and one EVEX X/m,X row; only the EVEX register-source +// encoding accepts .SAE. +func (c *amd64Ctx) lowerVectorScalarFlagCompare(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + elemType := LLVMType("") + switch baseOp { + case "VCOMISD", "VUCOMISD": + elemType = LLVMType("double") + case "VCOMISS", "VUCOMISS": + elemType = LLVMType("float") + default: + return false, false, nil + } + if suffix != "" && suffix != "SAE" { + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's _yvcomisd table: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects X/m, X: %q", c.goarch, baseOp, ins.Raw) + } + src, dst := ins.Args[0], ins.Args[1] + if !amd64EVEXVectorRegister(dst, 16) { + return true, false, fmt.Errorf("%s %s destination must be an X0-X31 register: %q", c.goarch, baseOp, ins.Raw) + } + if src.Kind == OpReg { + if !amd64EVEXVectorRegister(src, 16) { + return true, false, fmt.Errorf("%s %s register source must be an X0-X31 register: %q", c.goarch, baseOp, ins.Raw) + } + } else { + if !isAMD64MemoryOperand(src) { + return true, false, fmt.Errorf("%s %s source must be X0-X31 or memory: %q", c.goarch, baseOp, ins.Raw) + } + if suffix == "SAE" { + return true, false, fmt.Errorf("%s %s.SAE requires a register source: %q", c.goarch, baseOp, ins.Raw) + } + } + + var source, destination string + if elemType == LLVMType("double") { + source, err = c.evalF64(src) + if err == nil { + destination, err = c.evalF64(dst) + } + } else { + source, err = c.evalF32(src) + if err == nil { + destination, err = c.evalF32(dst) + } + } + if err != nil { + return true, false, err + } + c.setScalarFloatCompareFlags(elemType, destination, source) + return true, false, nil +} + +// setScalarFloatCompareFlags models the EFLAGS values written by COMIS*/ +// UCOMIS*: ZF/PF/CF describe equal/unordered/below and OF/SF are cleared. +func (c *amd64Ctx) setScalarFloatCompareFlags(elemType LLVMType, destination, source string) { + z := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp ueq %s %s, %s\n", z, elemType, destination, source) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", z, c.flagsZSlot) + cf := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp ult %s %s, %s\n", cf, elemType, destination, source) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCFSlot) + pf := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp uno %s %s, %s\n", pf, elemType, destination, source) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", pf, c.flagsPFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsSltSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) +} diff --git a/amd64_lower_vcvtss2sd_test.go b/amd64_lower_vcvtss2sd_test.go new file mode 100644 index 00000000..b9086dbd --- /dev/null +++ b/amd64_lower_vcvtss2sd_test.go @@ -0,0 +1,199 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateAMD64VCVTSS2SDCompleteGo127Forms(t *testing.T) { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT vcvtss2sdforms(SB),$0-0\n") + for _, op := range []string{"VCVTSS2SD", "VCVTSD2SS"} { + fmt.Fprintf(&source, "\t%s X0, X1, X2\n", op) + fmt.Fprintf(&source, "\t%s (AX), X3, X4\n", op) + fmt.Fprintf(&source, "\t%s X31, X30, X29\n", op) + if op == "VCVTSS2SD" { + fmt.Fprintf(&source, "\t%s.SAE X31, X30, X29\n", op) + } else { + for _, rounding := range []string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"} { + fmt.Fprintf(&source, "\t%s.%s X31, X30, X29\n", op, rounding) + } + } + if target.goarch == "amd64" { + fmt.Fprintf(&source, "\t%s X31, X30, K1, X29\n", op) + fmt.Fprintf(&source, "\t%s.Z (AX), X30, K2, X29\n", op) + if op == "VCVTSS2SD" { + fmt.Fprintf(&source, "\t%s.SAE.Z X31, X30, K3, X29\n", op) + } else { + fmt.Fprintf(&source, "\t%s.RD_SAE.Z X31, X30, K3, X29\n", op) + } + } + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"vcvtss2sdforms": {Name: "vcvtss2sdforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "vcvtss2sd-"+target.name+".ll", "vcvtss2sd-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86ScalarPrecisionConvertRejectsFormsOutsideGo127(t *testing.T) { + tests := []struct { + goarch string + triple string + instruction string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VCVTSS2SD.RD_SAE X0, X1, X2"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VCVTSD2SS.SAE X0, X1, X2"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VCVTSS2SD.SAE (AX), X1, X2"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VCVTSD2SS.RN_SAE (AX), X1, X2"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VCVTSS2SD.Z X0, X1, X2"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VCVTSD2SS X0, X1, K0, X2"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu", instruction: "VCVTSS2SD Y0, X1, X2"}, + {goarch: "386", triple: "i386-unknown-linux-gnu", instruction: "VCVTSD2SS X0, X1, K1, X2"}, + } + for _, test := range tests { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),NOSPLIT,$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err == nil { + _, err = Translate(file, Options{ + TargetTriple: test.triple, + Goarch: test.goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + } + if err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scalar precision-conversion forms for %s", test.instruction, test.goarch) + } + }) + } +} + +func TestAMD64ScalarPrecisionConvertRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT scalarPrecisionConvertSemantics(SB),NOSPLIT,$0-48 + MOVQ out+0(FP), AX + MOVQ doubles+8(FP), BX + MOVQ floats+16(FP), CX + MOVQ upper+24(FP), DX + MOVQ old+32(FP), SI + KMOVQ mask+40(FP), K1 + MOVSD (BX), X0 + MOVUPS (DX), X1 + MOVUPS (SI), X2 + VCVTSD2SS.RN_SAE X0, X1, X2 + MOVUPS X2, 0(AX) + VCVTSD2SS.RD_SAE X0, X1, X2 + MOVUPS X2, 16(AX) + VCVTSD2SS.RU_SAE X0, X1, X2 + MOVUPS X2, 32(AX) + VCVTSD2SS.RZ_SAE X0, X1, X2 + MOVUPS X2, 48(AX) + MOVUPS (SI), X2 + VCVTSD2SS.RU_SAE X0, X1, K1, X2 + MOVUPS X2, 64(AX) + MOVUPS (SI), X2 + VCVTSD2SS.RU_SAE.Z X0, X1, K1, X2 + MOVUPS X2, 80(AX) + MOVSS (CX), X0 + VCVTSS2SD.SAE X0, X1, X2 + MOVUPS X2, 96(AX) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: I64, Index: 5, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "scalarPrecisionConvertSemantics": {Name: "scalarPrecisionConvertSemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, I64}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void scalarPrecisionConvertSemantics(uint32_t *, const double *, const float *, const uint32_t *, const uint32_t *, uint64_t); +int main(void) { + double input = 1.0 + 0x1p-24; + float input32 = 1.5f; + uint32_t upper[4] = {0xaaaaaaaaU, 0x11111111U, 0x22222222U, 0x33333333U}; + uint32_t old[4] = {0xdeadbeefU, 0xbbbbbbbbU, 0xccccccccU, 0xddddddddU}; + uint32_t out[28] = {0}; + scalarPrecisionConvertSemantics(out, &input, &input32, upper, old, 0); + uint32_t low[4] = {0x3f800000U, 0x3f800000U, 0x3f800001U, 0x3f800000U}; + for (int group = 0; group < 4; group++) { + if (out[group*4] != low[group]) return 1 + group; + for (int lane = 1; lane < 4; lane++) if (out[group*4+lane] != upper[lane]) return 10 + group*4 + lane; + } + if (out[16] != old[0]) return 40; + if (out[20] != 0) return 41; + for (int lane = 1; lane < 4; lane++) { + if (out[16+lane] != upper[lane]) return 42 + lane; + if (out[20+lane] != upper[lane]) return 46 + lane; + } + uint64_t converted = 0, want = 0x3ff8000000000000ULL; + memcpy(&converted, &out[24], sizeof(converted)); + if (converted != want) return 60; + if (out[26] != upper[2] || out[27] != upper[3]) return 61; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "scalar_precision_convert", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_vec.go b/amd64_lower_vec.go index a4c111a6..8056f515 100644 --- a/amd64_lower_vec.go +++ b/amd64_lower_vec.go @@ -6,26 +6,163 @@ import ( ) func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err error) { + if ok, term, err := c.lowerFourSource(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerPackedStringCompare(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerExplicitMaskMove(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerIndexedPermute(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerQwordBitLookup(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerMaskToVector(op, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerVectorToMask(op, ins); ok { + return ok, term, err + } + rawOp := op + if ok, term, err := c.lowerSingleSourceIntegerNarrow(rawOp, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerPackedIntegerInsert(rawOp, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerScalarFloatBroadcast(rawOp, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerAES(rawOp, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerPackedWordShuffle(rawOp, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerPackedBitCount(rawOp, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerPackedConflict(rawOp, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerPackedExpand(rawOp, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerGFNI(rawOp, ins); ok { + return ok, term, err + } + if ok, term, err := c.lowerPackedCompress(rawOp, ins); ok { + return ok, term, err + } + zeroMasking := false if raw := string(op); strings.Contains(raw, ".") { + for _, suffix := range strings.Split(raw, ".")[1:] { + if suffix == "Z" { + zeroMasking = true + } + } if i := strings.IndexByte(raw, '.'); i >= 0 { op = Op(raw[:i]) } } + if op == "MOVD" { + if rawOp != op { + return true, false, fmt.Errorf("%s MOVD does not accept instruction suffixes: %q", c.goarch, ins.Raw) + } + if err := c.validateMOVDAliasForm(ins); err != nil { + return true, false, err + } + // cmd/asm maps the Plan 9 spelling MOVD to AMOVQ. In particular, + // memory/XMM forms transfer 64 bits; MOVD is not Intel's 32-bit MOVD + // mnemonic here. + op = "MOVQ" + } + if _, ok := amd64MaskMoveSpecs[op]; ok { + if rawOp != op { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", op, ins.Raw) + } + return true, false, c.lowerMaskMove(op, ins) + } + if _, ok := amd64GatherSpecs[op]; ok { + if rawOp != op { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", op, ins.Raw) + } + return true, false, c.lowerGather(op, ins) + } + if _, ok := amd64VSIBPrefetchSpecs[op]; ok { + if rawOp != op { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", op, ins.Raw) + } + return true, false, c.lowerGather(op, ins) + } + if _, ok := amd64MaskLogicalSpecs[op]; ok { + if rawOp != op { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", op, ins.Raw) + } + return true, false, c.lowerMaskLogical(op, ins) + } + if _, ok := amd64MaskArithmeticSpecs[op]; ok { + if rawOp != op { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, op, ins.Raw) + } + return true, false, c.lowerMaskArithmetic(op, ins) + } + if _, ok := amd64MaskUnpackBits[op]; ok { + if rawOp != op { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, op, ins.Raw) + } + return true, false, c.lowerMaskUnpack(op, ins) + } + if _, ok := amd64TernaryLogicSpecs[op]; ok { + return c.lowerTernaryLogic(rawOp, ins) + } + if _, ok := amd64VectorAlignSpecs[op]; ok { + return c.lowerVectorAlign(rawOp, ins) + } + if _, ok := amd64IFMASpecs[op]; ok { + return c.lowerIFMA(rawOp, ins) + } + if _, ok := amd64FunnelShiftSpecs[op]; ok { + return c.lowerFunnelShift(rawOp, ins) + } + if _, ok := amd64PackedRotateSpecs[op]; ok { + return c.lowerPackedRotate(rawOp, ins) + } + if _, ok := amd64EVEXPackedLogicalSpecs[op]; ok { + return c.lowerEVEXPackedLogical(rawOp, ins) + } + if _, ok := amd64PackedFloatingLogicalSpecs[op]; ok { + return c.lowerPackedFloatingLogical(rawOp, ins) + } + if _, ok := amd64FMA3Specs[op]; ok { + return c.lowerFMA3(rawOp, ins) + } + if _, ok := amd64BinaryFloatingSpecs[op]; ok { + return c.lowerBinaryFloating(rawOp, ins) + } + if _, ok := amd64HorizontalFloatingSpecs[op]; ok { + return c.lowerHorizontalFloating(rawOp, ins) + } switch op { - case "MOVOU", "MOVOA", "MOVUPS", "MOVAPS", "MOVO", "MOVQ", "MOVL", "MOVD", + case "MOVOU", "MOVOA", "MOVUPS", "MOVAPS", "MOVO", "MOVQ", "VMOVQ", "MOVL", "MOVD", "VMOVDQU", "VMOVDQA", "VMOVNTDQ", "VMOVDQU64", "VMOVDQA64", "VMOVAPS", "VMOVAPD", - "VPCMPEQB", "VPCMPGTB", "VPMOVMSKB", "VZEROUPPER", "VZEROALL", "VPBROADCASTB", "VPBROADCASTQ", "VPAND", "VPXOR", "VPOR", "VPADDD", "VPADDQ", "VPTEST", - "VPANDQ", "VPXORQ", "VPORQ", "VPCLMULQDQ", "VPTERNLOGD", "VEXTRACTF32X4", - "VPERMB", "VGF2P8AFFINEQB", "VPERMI2B", "VPCOMPRESSQ", "VPOPCNTB", "VPCMPUQ", - "VBROADCASTI128", "VBROADCASTF32X2", "VBROADCASTSD", "VXORPD", - "VPSHUFB", "VPSHUFD", "VPSLLD", "VPSRLD", "VPSRLQ", "VPSLLQ", "VPSRLDQ", "VPSLLDQ", "VPUNPCKLBW", "VPUNPCKHBW", + "VPCMPEQB", "VPCMPGTB", "VPMOVMSKB", "VZEROUPPER", "VZEROALL", "VPBROADCASTB", "VPBROADCASTD", "VPBROADCASTQ", "VPAND", "VPXOR", "VPOR", "VPADDD", "VPADDQ", "VPSUBB", "VPTEST", "VTESTPD", "VTESTPS", + "VPCLMULQDQ", "VEXTRACTF32X4", + "VPCMPUQ", + "VBROADCASTF32X2", "VBROADCASTSD", + "VPSHUFB", "VPSHUFD", "VPSLLD", "VPSLLQ", "VPSLLW", "VPSRAD", "VPSRAW", "VPSRLD", "VPSRLQ", "VPSRLW", "VPSRLDQ", "VPSLLDQ", "VPUNPCKLBW", "VPUNPCKHBW", "VPUNPCKLDQ", "VPUNPCKHDQ", "VPUNPCKLQDQ", "VPUNPCKHQDQ", "VPALIGNR", "VPERM2I128", "VPERM2F128", "VINSERTI128", "VPBLENDD", - "PXOR", "POR", "PAND", "PANDN", "PADDD", "PADDL", "PSUBB", "PSUBL", "PMULULQ", "PCLMULQDQ", "PCMPEQB", "PCMPEQL", "PCMPGTB", "PMOVMSKB", - "PSHUFB", "PSRLDQ", "PSLLDQ", "PSRLQ", "PSLLW", "PSRLW", "PSRLL", "PSLLL", "PSRAL", "PEXTRD", "PEXTRB", "PEXTRQ", - "PINSRQ", "PINSRD", "PINSRB", "PINSRW", "PALIGNR", "PUNPCKLBW", "PUNPCKHBW", "PUNPCKLLQ", "PUNPCKHLQ", "PUNPCKLQDQ", "PSHUFL", "PSHUFD", "PSHUFHW", "SHUFPS", - "PBLENDW", "PADDQ", "KMOVB", "KMOVW", "KMOVQ", "KXORQ", + "PXOR", "POR", "PAND", "PADDB", "PADDD", "PADDL", "PSUBB", "PSUBL", "PSUBUSB", "PMULLW", "PMULULQ", "PCLMULQDQ", "PCMPEQB", "PCMPEQW", "PCMPEQL", "PCMPGTB", "PABSD", "PTEST", "PMOVMSKB", + "PMINUB", "PMINSB", "PMINUW", "PMINSW", "PMINUD", "PMINSD", "PMAXUB", "PMAXSB", "PMAXUW", "PMAXSW", "PMAXUD", "PMAXSD", + "PSHUFB", "PSRLDQ", "PSLLDQ", "PSRLO", "PSLLO", "PSRLQ", "PSLLQ", "PSLLW", "PSRLW", "PSRLL", "PSLLL", "PSRAL", "PEXTRD", "PEXTRB", "PEXTRQ", + "PALIGNR", "PUNPCKLBW", "PUNPCKHBW", "PUNPCKLLQ", "PUNPCKHLQ", "PUNPCKLQDQ", "PUNPCKHQDQ", "PSHUFL", "PSHUFD", "SHUFPS", + "PBLENDW", "PADDQ", "SHA1NEXTE", "SHA1MSG1", "SHA1MSG2", "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", - "AESENC", "AESENCLAST", "AESDEC", "AESDECLAST", "AESIMC", "AESKEYGENASSIST", "PCMPESTRI": + "AESENC", "AESENCLAST", "AESDEC", "AESDECLAST", "AESIMC", "AESKEYGENASSIST": // ok default: return false, false, nil @@ -57,7 +194,7 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err } } // MOVL Xn, dst stores the low 32 bits of the vector register. - if op == "MOVL" && len(ins.Args) == 2 && ins.Args[0].Kind == OpReg { + if (op == "MOVL" || op == "MOVD") && len(ins.Args) == 2 && ins.Args[0].Kind == OpReg { if _, ok := amd64ParseXReg(ins.Args[0].Reg); ok { vec, err := c.loadX(ins.Args[0].Reg) if err != nil { @@ -125,9 +262,20 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err if op == "VMOVDQA64" { op = "VMOVDQU64" } + if op == "PSLLO" { + op = "PSLLDQ" + } + if op == "PSRLO" { + op = "PSRLDQ" + } if op == "VPERM2F128" { op = "VPERM2I128" } + if op == "VMOVQ" { + // VMOVQ has the same scalar 64-bit X-register semantics as MOVQ; + // only the machine encoding differs. + op = "MOVQ" + } if op == "VMOVAPS" || op == "VMOVAPD" { if len(ins.Args) == 2 { if (ins.Args[0].Kind == OpReg && isAMD64ZReg(ins.Args[0].Reg)) || @@ -138,19 +286,6 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err } } } - if op == "VPXORQ" || op == "VPANDQ" || op == "VPORQ" { - if len(ins.Args) == 3 && ins.Args[2].Kind == OpReg && !isAMD64ZReg(ins.Args[2].Reg) { - switch op { - case "VPXORQ": - op = "VPXOR" - case "VPANDQ": - op = "VPAND" - case "VPORQ": - op = "VPOR" - } - } - } - // MOVUPS/MOVAPS/MOVO are aliases for unaligned/aligned 128-bit xmm moves. if op == "MOVUPS" || op == "MOVAPS" || op == "MOVO" { op = "MOVOU" @@ -218,6 +353,8 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err switch ins.Args[1].Kind { case OpReg: return true, false, c.storeReg(ins.Args[1].Reg, "%"+lo) + case OpFP: + return true, false, c.storeFPResult(ins.Args[1].FPOffset, I64, "%"+lo) case OpMem: addr, err := c.addrFromMem(ins.Args[1].Mem) if err != nil { @@ -226,6 +363,13 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err p := c.ptrFromAddrI64(addr) fmt.Fprintf(c.b, " store i64 %%%s, ptr %s, align 1\n", lo, p) return true, false, nil + case OpSym: + p, err := c.ptrFromSB(ins.Args[1].Sym) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store i64 %%%s, ptr %s, align 1\n", lo, p) + return true, false, nil default: return true, false, fmt.Errorf("amd64 MOVQ from X reg unsupported dst: %q", ins.Raw) } @@ -233,215 +377,6 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err } switch op { - case "KXORQ": - if len(ins.Args) != 3 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 KXORQ expects Ksrc1, Ksrc2, Kdst: %q", ins.Raw) - } - if _, ok := amd64ParseKReg(ins.Args[0].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseKReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseKReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - a, err := c.loadK(ins.Args[0].Reg) - if err != nil { - return true, false, err - } - b, err := c.loadK(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - x := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i64 %s, %s\n", x, a, b) - return true, false, c.storeK(ins.Args[2].Reg, "%"+x) - - case "KMOVB", "KMOVW", "KMOVQ": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("amd64 %s expects 2 operands: %q", op, ins.Raw) - } - bits := 64 - loadTy := "i64" - switch op { - case "KMOVB": - bits, loadTy = 8, "i8" - case "KMOVW": - bits, loadTy = 16, "i16" - } - maskValue := func(v string) string { - if bits == 64 { - return v - } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %s, %d\n", t, v, (uint64(1)< %s to <64 x i8>\n", out, outVec) return true, false, c.storeZ(ins.Args[2].Reg, "%"+out) - case "VPXORQ", "VPANDQ", "VPORQ": - if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects src1, src2, dstReg: %q", op, ins.Raw) - } - if _, ok := amd64ParseZReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - a, err := c.loadZVecOperand(ins.Args[0]) - if err != nil { - return true, false, err - } - b, err := c.loadZVecOperand(ins.Args[1]) - if err != nil { - return true, false, err + case "VPBROADCASTD": + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 VPBROADCASTD expects scalar src, vector dst: %q", ins.Raw) } - ab := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <64 x i8> %s to <8 x i64>\n", ab, a) - bb := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <64 x i8> %s to <8 x i64>\n", bb, b) - t := c.newTmp() - switch op { - case "VPXORQ": - fmt.Fprintf(c.b, " %%%s = xor <8 x i64> %%%s, %%%s\n", t, ab, bb) - case "VPANDQ": - fmt.Fprintf(c.b, " %%%s = and <8 x i64> %%%s, %%%s\n", t, ab, bb) - case "VPORQ": - fmt.Fprintf(c.b, " %%%s = or <8 x i64> %%%s, %%%s\n", t, ab, bb) + var low32 string + if ins.Args[0].Kind == OpReg { + if _, ok := amd64ParseXReg(ins.Args[0].Reg); ok { + value, err := c.loadX(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + words := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", words, value) + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x i32> %%%s, i32 0\n", extracted, words) + low32 = "%" + extracted + } } - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <8 x i64> %%%s to <64 x i8>\n", out, t) - return true, false, c.storeZ(ins.Args[2].Reg, "%"+out) - - case "VBROADCASTI128": - // VBROADCASTI128 Xsrc|mem, Ydst - if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VBROADCASTI128 expects Xsrc|mem, Ydst: %q", ins.Raw) + if low32 == "" { + var value64 string + var err error + switch ins.Args[0].Kind { + case OpMem: + addr, addrErr := c.addrFromMem(ins.Args[0].Mem) + if addrErr != nil { + return true, false, addrErr + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i32, ptr %s, align 1\n", loaded, c.ptrFromAddrI64(addr)) + low32 = "%" + loaded + case OpSym: + p, ptrErr := c.ptrFromSB(ins.Args[0].Sym) + if ptrErr != nil { + return true, false, ptrErr + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i32, ptr %s, align 1\n", loaded, p) + low32 = "%" + loaded + default: + value64, err = c.evalI64(ins.Args[0]) + if err != nil { + return true, false, err + } + } + if low32 == "" { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", truncated, value64) + low32 = "%" + truncated + } } - if _, ok := amd64ParseYReg(ins.Args[1].Reg); !ok { + lanes := 0 + store := func(string) error { return nil } + switch { + case isAMD64XReg(ins.Args[1].Reg): + lanes = 4 + store = func(value string) error { + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %s to <16 x i8>\n", bytesValue, value) + return c.storeX(ins.Args[1].Reg, "%"+bytesValue) + } + case isAMD64YReg(ins.Args[1].Reg): + lanes = 8 + store = func(value string) error { + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <8 x i32> %s to <32 x i8>\n", bytesValue, value) + return c.storeY(ins.Args[1].Reg, "%"+bytesValue) + } + case isAMD64ZReg(ins.Args[1].Reg): + lanes = 16 + store = func(value string) error { + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i32> %s to <64 x i8>\n", bytesValue, value) + return c.storeZ(ins.Args[1].Reg, "%"+bytesValue) + } + default: return false, false, nil } - src, err := c.loadXVecOperand(ins.Args[0]) - if err != nil { - return true, false, err + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i32> zeroinitializer, i32 %s, i32 0\n", seed, lanes, low32) + mask := make([]string, lanes) + for i := range mask { + mask[i] = "i32 0" } - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %s, <16 x i8> %s, <32 x i32> %s\n", out, src, src, llvmRepeatI8Mask(16, 32)) - return true, false, c.storeY(ins.Args[1].Reg, "%"+out) + broadcast := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i32> %%%s, <%d x i32> zeroinitializer, <%d x i32> <%s>\n", broadcast, lanes, seed, lanes, lanes, strings.Join(mask, ", ")) + return true, false, store("%" + broadcast) case "VBROADCASTF32X2", "VBROADCASTSD", "VPBROADCASTQ": // These instructions broadcast the low 64 source bits. Their lane @@ -646,54 +620,7 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err fmt.Fprintf(c.b, " %%%s = shufflevector <8 x i8> %%%s, <8 x i8> %%%s, <64 x i32> %s\n", out, chunk, chunk, llvmRepeatI8Mask(8, 64)) return true, false, c.storeZ(ins.Args[1].Reg, "%"+out) - case "VXORPD": - // VXORPD src1, src2, dst; this is a bitwise operation despite the - // floating-point mnemonic, so byte-vector xor preserves all bits. - if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VXORPD expects src1, src2, dst: %q", ins.Raw) - } - if _, ok := amd64ParseZReg(ins.Args[2].Reg); ok { - a, err := c.loadZVecOperand(ins.Args[0]) - if err != nil { - return true, false, err - } - b, err := c.loadZVecOperand(ins.Args[1]) - if err != nil { - return true, false, err - } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor <64 x i8> %s, %s\n", t, a, b) - return true, false, c.storeZ(ins.Args[2].Reg, "%"+t) - } - if _, ok := amd64ParseYReg(ins.Args[2].Reg); ok { - a, err := c.loadYVecOperand(ins.Args[0]) - if err != nil { - return true, false, err - } - b, err := c.loadYVecOperand(ins.Args[1]) - if err != nil { - return true, false, err - } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor <32 x i8> %s, %s\n", t, a, b) - return true, false, c.storeY(ins.Args[2].Reg, "%"+t) - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); ok { - a, err := c.loadXVecOperand(ins.Args[0]) - if err != nil { - return true, false, err - } - b, err := c.loadXVecOperand(ins.Args[1]) - if err != nil { - return true, false, err - } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor <16 x i8> %s, %s\n", t, a, b) - return true, false, c.storeX(ins.Args[2].Reg, "%"+t) - } - return false, false, nil - - case "VPXOR", "VPOR", "VPADDD", "VPADDQ": + case "VPXOR", "VPOR", "VPADDD", "VPADDQ", "VPSUBB": // V* three-operand op; support both X and Y destinations. if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { return true, false, fmt.Errorf("amd64 %s expects src1, src2, dstReg: %q", op, ins.Raw) @@ -729,6 +656,8 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err add := c.newTmp() fmt.Fprintf(c.b, " %%%s = add <4 x i64> %%%s, %%%s\n", add, ab, bb) fmt.Fprintf(c.b, " %%%s = bitcast <4 x i64> %%%s to <32 x i8>\n", t, add) + case "VPSUBB": + fmt.Fprintf(c.b, " %%%s = sub <32 x i8> %s, %s\n", t, b, a) } return true, false, c.storeY(ins.Args[2].Reg, "%"+t) } @@ -763,6 +692,8 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err add := c.newTmp() fmt.Fprintf(c.b, " %%%s = add <2 x i64> %%%s, %%%s\n", add, ab, bb) fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", t, add) + case "VPSUBB": + fmt.Fprintf(c.b, " %%%s = sub <16 x i8> %s, %s\n", t, b, a) } return true, false, c.storeX(ins.Args[2].Reg, "%"+t) } @@ -815,149 +746,233 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err return false, false, nil case "VPSHUFD": - // VPSHUFD $imm, Ysrc, Ydst - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VPSHUFD expects $imm, Ysrc, Ydst: %q", ins.Raw) - } - if _, ok := amd64ParseYReg(ins.Args[1].Reg); !ok { - return false, false, nil + // VPSHUFD $imm, X|Y|Zsrc/mem, X|Y|Zdst. The immediate + // selects dwords independently in each 128-bit lane. + if (len(ins.Args) != 3 && len(ins.Args) != 4) || ins.Args[0].Kind != OpImm { + return true, false, fmt.Errorf("amd64 VPSHUFD expects $imm, src, dst or $imm, src, Kmask, dst: %q", ins.Raw) } - if _, ok := amd64ParseYReg(ins.Args[2].Reg); !ok { - return false, false, nil + dstIdx := len(ins.Args) - 1 + if ins.Args[dstIdx].Kind != OpReg { + return true, false, fmt.Errorf("amd64 VPSHUFD expects vector destination: %q", ins.Raw) } imm := uint64(ins.Args[0].Imm) & 0xff - idx := func(k uint) uint64 { return (imm >> (2 * k)) & 3 } - src, err := c.loadY(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - bc := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <32 x i8> %s to <8 x i32>\n", bc, src) - mask := fmt.Sprintf("<8 x i32> ", - idx(0), idx(1), idx(2), idx(3), - 4+idx(0), 4+idx(1), 4+idx(2), 4+idx(3)) - sh := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <8 x i32> %%%s, <8 x i32> zeroinitializer, %s\n", sh, bc, mask) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <8 x i32> %%%s to <32 x i8>\n", out, sh) - return true, false, c.storeY(ins.Args[2].Reg, "%"+out) - - case "VPSLLD", "VPSRLD": - // VPS*D $imm, Ysrc, Ydst - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects $imm, Ysrc, Ydst: %q", op, ins.Raw) - } - if _, ok := amd64ParseYReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseYReg(ins.Args[2].Reg); !ok { + lanes := 0 + byteWidth := 0 + var src string + var err error + var loadDst func() (string, error) + store := func(string) error { return nil } + switch { + case isAMD64XReg(ins.Args[dstIdx].Reg): + lanes, byteWidth = 4, 16 + src, err = c.loadXVecOperand(ins.Args[1]) + loadDst = func() (string, error) { return c.loadX(ins.Args[dstIdx].Reg) } + store = func(v string) error { return c.storeX(ins.Args[dstIdx].Reg, v) } + case isAMD64YReg(ins.Args[dstIdx].Reg): + lanes, byteWidth = 8, 32 + src, err = c.loadYVecOperand(ins.Args[1]) + loadDst = func() (string, error) { return c.loadY(ins.Args[dstIdx].Reg) } + store = func(v string) error { return c.storeY(ins.Args[dstIdx].Reg, v) } + case isAMD64ZReg(ins.Args[dstIdx].Reg): + lanes, byteWidth = 16, 64 + src, err = c.loadZVecOperand(ins.Args[1]) + loadDst = func() (string, error) { return c.loadZ(ins.Args[dstIdx].Reg) } + store = func(v string) error { return c.storeZ(ins.Args[dstIdx].Reg, v) } + default: return false, false, nil } - n := ins.Args[0].Imm & 31 - src, err := c.loadY(ins.Args[1].Reg) if err != nil { return true, false, err } bc := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <32 x i8> %s to <8 x i32>\n", bc, src) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i32>\n", bc, byteWidth, src, lanes) + mask := llvmVPSHUFDMask(lanes, imm) sh := c.newTmp() - if op == "VPSLLD" { - fmt.Fprintf(c.b, " %%%s = shl <8 x i32> %%%s, \n", sh, bc, n, n, n, n, n, n, n, n) - } else { - fmt.Fprintf(c.b, " %%%s = lshr <8 x i32> %%%s, \n", sh, bc, n, n, n, n, n, n, n, n) + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i32> %%%s, <%d x i32> zeroinitializer, <%d x i32> %s\n", sh, lanes, bc, lanes, lanes, mask) + shuffled := "%" + sh + if len(ins.Args) == 4 { + if ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("amd64 VPSHUFD masked form expects K mask: %q", ins.Raw) + } + if _, ok := amd64ParseKReg(ins.Args[2].Reg); !ok { + return false, false, nil + } + maskValue, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := loadDst() + if err != nil { + return true, false, err + } + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to <%d x i32>\n", old, byteWidth, oldBytes, lanes) + shuffled = amd64ApplyI32LaneMask(c, lanes, shuffled, "%"+old, maskValue, zeroMasking) } out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <8 x i32> %%%s to <32 x i8>\n", out, sh) - return true, false, c.storeY(ins.Args[2].Reg, "%"+out) - - case "VPSRLQ", "VPSLLQ": - // VPSR/LQ $imm, Ysrc, Ydst - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects $imm, Ysrc, Ydst: %q", op, ins.Raw) - } - if _, ok := amd64ParseYReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseYReg(ins.Args[2].Reg); !ok { + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i32> %s to <%d x i8>\n", out, lanes, shuffled, byteWidth) + return true, false, store("%" + out) + + case "VPSLLD", "VPSLLQ", "VPSLLW", "VPSRAD", "VPSRAW", "VPSRLD", "VPSRLQ", "VPSRLW": + // Go's x86 assembler uses _yvpslld for this whole family: + // $imm8, X|Y|Z src/mem, [Kmask,] X|Y|Z dst + // X|m128 count, X|Y|Z src, [Kmask,] X|Y|Z dst + // The count is uniform: variable forms use the low 64 bits of X|m128. + if (len(ins.Args) != 3 && len(ins.Args) != 4) || ins.Args[len(ins.Args)-1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects count, vector src, [K mask,] vector dst: %q", op, ins.Raw) + } + dst := ins.Args[len(ins.Args)-1].Reg + byteWidth := 0 + var src string + var err error + loadDst := func() (string, error) { return "", nil } + store := func(string) error { return nil } + switch { + case isAMD64XReg(dst): + byteWidth = 16 + src, err = c.loadXVecOperand(ins.Args[1]) + loadDst = func() (string, error) { return c.loadX(dst) } + store = func(v string) error { return c.storeX(dst, v) } + case isAMD64YReg(dst): + byteWidth = 32 + src, err = c.loadYVecOperand(ins.Args[1]) + loadDst = func() (string, error) { return c.loadY(dst) } + store = func(v string) error { return c.storeY(dst, v) } + case isAMD64ZReg(dst): + byteWidth = 64 + src, err = c.loadZVecOperand(ins.Args[1]) + loadDst = func() (string, error) { return c.loadZ(dst) } + store = func(v string) error { return c.storeZ(dst, v) } + default: return false, false, nil } - n := ins.Args[0].Imm & 63 - src, err := c.loadY(ins.Args[1].Reg) if err != nil { return true, false, err } + + elemBits := 32 + switch op[len(op)-1] { + case 'Q': + elemBits = 64 + case 'W': + elemBits = 16 + } + lanes := byteWidth * 8 / elemBits + vecType := fmt.Sprintf("<%d x i%d>", lanes, elemBits) bc := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <32 x i8> %s to <4 x i64>\n", bc, src) - sh := c.newTmp() - if op == "VPSLLQ" { - fmt.Fprintf(c.b, " %%%s = shl <4 x i64> %%%s, \n", sh, bc, n, n, n, n) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", bc, byteWidth, src, vecType) + + llvmOp := "shl" + arithmetic := op == "VPSRAD" || op == "VPSRAW" + if arithmetic { + llvmOp = "ashr" + } else if strings.HasPrefix(string(op), "VPSRL") { + llvmOp = "lshr" + } + + shifted := "zeroinitializer" + if ins.Args[0].Kind == OpImm { + count := uint64(ins.Args[0].Imm) & 0xff + if arithmetic && count >= uint64(elemBits) { + count = uint64(elemBits - 1) + } + if arithmetic || count < uint64(elemBits) { + sh := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %%%s, %s\n", sh, llvmOp, vecType, bc, llvmSplatInteger(lanes, elemBits, count)) + shifted = "%" + sh + } } else { - fmt.Fprintf(c.b, " %%%s = lshr <4 x i64> %%%s, \n", sh, bc, n, n, n, n) + countVec, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, fmt.Errorf("amd64 %s count: %w", op, err) + } + countWords := c.newTmp() + count := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", countWords, countVec) + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 0\n", count, countWords) + inRange := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i64 %%%s, %d\n", inRange, count, elemBits) + safeCount := c.newTmp() + fallback := 0 + if arithmetic { + fallback = elemBits - 1 + } + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 %d\n", safeCount, inRange, count, fallback) + shiftCount := "%" + safeCount + if elemBits < 64 { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i%d\n", truncated, safeCount, elemBits) + shiftCount = "%" + truncated + } + countSplat := amd64SplatInteger(c, lanes, elemBits, shiftCount) + sh := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %%%s, %s\n", sh, llvmOp, vecType, bc, countSplat) + shifted = "%" + sh + if !arithmetic { + condition := amd64SplatI1(c, lanes, "%"+inRange) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %s, %s %s, %s zeroinitializer\n", selected, lanes, condition, vecType, shifted, vecType) + shifted = "%" + selected + } + } + + if len(ins.Args) == 4 { + if ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s masked form expects K mask: %q", op, ins.Raw) + } + if _, ok := amd64ParseKReg(ins.Args[2].Reg); !ok { + return false, false, nil + } + maskValue, err := c.loadK(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + oldBytes, err := loadDst() + if err != nil { + return true, false, err + } + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i8> %s to %s\n", old, byteWidth, oldBytes, vecType) + shifted = amd64ApplyIntegerLaneMask(c, lanes, elemBits, shifted, "%"+old, maskValue, zeroMasking) } out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <4 x i64> %%%s to <32 x i8>\n", out, sh) - return true, false, c.storeY(ins.Args[2].Reg, "%"+out) + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to <%d x i8>\n", out, vecType, shifted, byteWidth) + return true, false, store("%" + out) case "VPALIGNR": - // VPALIGNR $imm, Ysrc1, Ysrc2, Ydst ; dst = alignr(src2, src1, imm) - if len(ins.Args) != 4 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg || ins.Args[3].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VPALIGNR expects $imm, Ysrc1, Ysrc2, Ydst: %q", ins.Raw) - } - if _, ok := amd64ParseYReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseYReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseYReg(ins.Args[3].Reg); !ok { - return false, false, nil - } - n := ins.Args[0].Imm - if n < 0 { - n = 0 + return c.lowerPackedAlignRight(rawOp, ins) + + case "VPERM2I128": + // VPERM2I128 $imm, Ysrc1, Ysrc2, Ydst + if rawOp != "VPERM2I128" && rawOp != "VPERM2F128" { + return true, false, fmt.Errorf("amd64 %s does not accept instruction suffixes: %q", op, ins.Raw) } - if n > 255 { - n = 255 + if c.goarch != "amd64" { + return true, false, fmt.Errorf("%s %s exceeds the Go assembler frontend's operand limit: %q", c.goarch, rawOp, ins.Raw) } - src1, err := c.loadY(ins.Args[1].Reg) - if err != nil { - return true, false, err + if len(ins.Args) != 4 || !amd64UnsignedImmediate(ins.Args[0], 8) || ins.Args[2].Kind != OpReg || ins.Args[3].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects $imm8, Y/m256, Ysrc, Ydst: %q", rawOp, ins.Raw) } - src2, err := c.loadY(ins.Args[2].Reg) - if err != nil { - return true, false, err + if ins.Args[1].Kind == OpReg { + if _, ok := amd64ParseYReg(ins.Args[1].Reg); !ok { + return true, false, fmt.Errorf("amd64 %s expects a Y/m256 first source: %q", rawOp, ins.Raw) + } + } else if ins.Args[1].Kind != OpMem && ins.Args[1].Kind != OpSym { + return true, false, fmt.Errorf("amd64 %s expects a Y/m256 first source: %q", rawOp, ins.Raw) } - lo1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <32 x i8> %s, <32 x i8> zeroinitializer, <16 x i32> %s\n", lo1, src1, llvmI32RangeMask(0, 16)) - hi1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <32 x i8> %s, <32 x i8> zeroinitializer, <16 x i32> %s\n", hi1, src1, llvmI32RangeMask(16, 16)) - lo2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <32 x i8> %s, <32 x i8> zeroinitializer, <16 x i32> %s\n", lo2, src2, llvmI32RangeMask(0, 16)) - hi2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <32 x i8> %s, <32 x i8> zeroinitializer, <16 x i32> %s\n", hi2, src2, llvmI32RangeMask(16, 16)) - outLo := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %%%s, <16 x i8> %%%s, <16 x i32> %s\n", outLo, lo2, lo1, llvmAlignRightBytesMask(n)) - outHi := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %%%s, <16 x i8> %%%s, <16 x i32> %s\n", outHi, hi2, hi1, llvmAlignRightBytesMask(n)) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %%%s, <16 x i8> %%%s, <32 x i32> %s\n", out, outLo, outHi, llvmI32RangeMask(0, 32)) - return true, false, c.storeY(ins.Args[3].Reg, "%"+out) - - case "VPERM2I128": - // VPERM2I128 $imm, Ysrc1, Ysrc2, Ydst - if len(ins.Args) != 4 || ins.Args[0].Kind != OpImm || ins.Args[3].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VPERM2I128 expects $imm, Ysrc1, Ysrc2, Ydst: %q", ins.Raw) + if _, ok := amd64ParseYReg(ins.Args[2].Reg); !ok { + return true, false, fmt.Errorf("amd64 %s expects a Y-register second source: %q", rawOp, ins.Raw) } if _, ok := amd64ParseYReg(ins.Args[3].Reg); !ok { - return false, false, nil + return true, false, fmt.Errorf("amd64 %s expects a Y-register destination: %q", rawOp, ins.Raw) } - imm := uint64(ins.Args[0].Imm) & 0xff + imm := uint64(ins.Args[0].Imm) // AT&T order: imm, src1, src2, dst ; choose lanes from src2 (arg2) + src1 (arg1). src1, err := c.loadYVecOperand(ins.Args[1]) if err != nil { return true, false, err } - src2, err := c.loadYVecOperand(ins.Args[2]) + src2, err := c.loadY(ins.Args[2].Reg) if err != nil { return true, false, err } @@ -975,7 +990,7 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err } lowSel := sel(imm) hiSel := sel(imm >> 4) - mask := fmt.Sprintf("<4 x i32> ", lowSel, lowSel+4, hiSel, hiSel+4) + mask := fmt.Sprintf("<4 x i32> ", lowSel*2, lowSel*2+1, hiSel*2, hiSel*2+1) b2 := c.newTmp() fmt.Fprintf(c.b, " %%%s = bitcast <32 x i8> %s to <4 x i64>\n", b2, src2) b1 := c.newTmp() @@ -1055,36 +1070,10 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err return true, false, c.storeY(ins.Args[3].Reg, "%"+out) case "VMOVNTDQ": - // VMOVNTDQ Ysrc, mem - if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VMOVNTDQ expects Ysrc, dst: %q", ins.Raw) - } - if _, ok := amd64ParseYReg(ins.Args[0].Reg); !ok { - return false, false, nil - } - src, err := c.loadY(ins.Args[0].Reg) - if err != nil { - return true, false, err - } - switch ins.Args[1].Kind { - case OpMem: - addr, err := c.addrFromMem(ins.Args[1].Mem) - if err != nil { - return true, false, err - } - p := c.ptrFromAddrI64(addr) - fmt.Fprintf(c.b, " store <32 x i8> %s, ptr %s, align 1\n", src, p) - return true, false, nil - case OpSym: - p, err := c.ptrFromSB(ins.Args[1].Sym) - if err != nil { - return true, false, err - } - fmt.Fprintf(c.b, " store <32 x i8> %s, ptr %s, align 1\n", src, p) - return true, false, nil - default: - return true, false, fmt.Errorf("amd64 VMOVNTDQ unsupported dst: %q", ins.Raw) - } + // Compatibility entry point for direct lowerVec unit tests. Ordinary + // translation dispatches the whole family through the dedicated + // lowerer before reaching this legacy switch. + return c.lowerNonTemporalVectorMove(op, ins) case "AESENC", "AESENCLAST", "AESDEC", "AESDECLAST": // Two-operand form: OP Xsrc, Xdst @@ -1165,164 +1154,8 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", bc, call) return true, false, c.storeX(ins.Args[2].Reg, "%"+bc) - case "VPTEST": - // VPTEST Ysrc1, Ysrc2 (sets flags based on bitwise tests; used with JZ/JNZ). - // We implement the ZF behavior (ZF=1 iff (a&b)==0) since stdlib uses JNZ. - if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VPTEST expects Ysrc1, Ysrc2: %q", ins.Raw) - } - if _, ok := amd64ParseYReg(ins.Args[0].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseYReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - a, err := c.loadY(ins.Args[0].Reg) - if err != nil { - return true, false, err - } - b, err := c.loadY(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - and := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and <32 x i8> %s, %s\n", and, a, b) - bc := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <32 x i8> %%%s to <4 x i64>\n", bc, and) - e0, e1, e2, e3 := c.newTmp(), c.newTmp(), c.newTmp(), c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractelement <4 x i64> %%%s, i32 0\n", e0, bc) - fmt.Fprintf(c.b, " %%%s = extractelement <4 x i64> %%%s, i32 1\n", e1, bc) - fmt.Fprintf(c.b, " %%%s = extractelement <4 x i64> %%%s, i32 2\n", e2, bc) - fmt.Fprintf(c.b, " %%%s = extractelement <4 x i64> %%%s, i32 3\n", e3, bc) - o01 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", o01, e0, e1) - o23 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", o23, e2, e3) - o := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", o, o01, o23) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp eq i64 %%%s, 0\n", z, o) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", z, c.flagsZSlot) - // CF/other flags are not used by stdlib here; clear CF to avoid stale reads. - fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsCFSlot) - return true, false, nil - - case "PCMPESTRI": - // PCMPESTRI $imm, mem, Xsrc (implicit lengths; result index in ECX). - // - // LLVM 19 has backend issues selecting the native X86ISD::PCMPESTR node - // for the corresponding intrinsic in some environments. For now we - // emulate the subset used by the Go stdlib: - // imm=0x0c: unsigned byte compare, equal ordered, first match. - // - // We compute the first offset i in [0..15] where: - // - bytes(mem[i:]) has a prefix that matches Xsrc[0:lenA] - // - or a partial match at the end of the 16-byte block (to drive the - // stdlib's "partial match" control flow). - // If no match/partial match exists, return 16. - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PCMPESTRI expects $imm, mem, Xsrc: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - imm := int64(ins.Args[0].Imm) & 0xff - if imm != 0x0c { - return true, false, fmt.Errorf("amd64 PCMPESTRI: unsupported imm 0x%x (only 0x0c supported): %q", imm, ins.Raw) - } - - // A: needle bytes. - a, err := c.loadX(ins.Args[2].Reg) - if err != nil { - return true, false, err - } - // B: 16-byte haystack chunk. - var bvec string - switch ins.Args[1].Kind { - case OpMem: - addr, err := c.addrFromMem(ins.Args[1].Mem) - if err != nil { - return true, false, err - } - p := c.ptrFromAddrI64(addr) - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load <16 x i8>, ptr %s, align 1\n", ld, p) - bvec = "%" + ld - case OpSym: - p, err := c.ptrFromSB(ins.Args[1].Sym) - if err != nil { - return true, false, err - } - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load <16 x i8>, ptr %s, align 1\n", ld, p) - bvec = "%" + ld - default: - return true, false, fmt.Errorf("amd64 PCMPESTRI unsupported mem operand: %q", ins.Raw) - } - - ax, err := c.loadReg(AX) - if err != nil { - return true, false, err - } - la := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", la, ax) - - allOnes := llvmAllOnesI8Vec(16) - idx := c.newTmp() - fmt.Fprintf(c.b, " %%%s = add i32 0, 16\n", idx) - prev := "%" + idx - - // Build first-match index using a select chain. - for i := 0; i < 16; i++ { - // Shuffle B so that element 0 is B[i], padding beyond 16 with 0. - maskElts := make([]string, 0, 16) - for k := 0; k < 16; k++ { - j := i + k - if j < 16 { - maskElts = append(maskElts, fmt.Sprintf("i32 %d", j)) - } else { - // 16 selects element 0 of the second (zero) vector. - maskElts = append(maskElts, "i32 16") - } - } - mask := "<16 x i32> <" + strings.Join(maskElts, ", ") + ">" - - sh := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %s, <16 x i8> zeroinitializer, %s\n", sh, bvec, mask) - cmp := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp eq <16 x i8> %%%s, %s\n", cmp, sh, a) - sel := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select <16 x i1> %%%s, <16 x i8> %s, <16 x i8> zeroinitializer\n", sel, cmp, allOnes) - pm := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %%%s)\n", pm, sel) - - // minLen = min(lenA, 16-i) - cap := 16 - i - lt := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ult i32 %%%s, %d\n", lt, la, cap) - min := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %%%s, i32 %d\n", min, lt, la, cap) - sh1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shl i32 1, %%%s\n", sh1, min) - req := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sub i32 %%%s, 1\n", req, sh1) - have := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i32 %%%s, %%%s\n", have, pm, req) - okt := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp eq i32 %%%s, %%%s\n", okt, have, req) - - unset := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 16\n", unset, prev) - take := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", take, okt, unset) - next := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %d, i32 %s\n", next, take, i, prev) - prev = "%" + next - } - - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", z, prev) - return true, false, c.storeReg(CX, "%"+z) + case "PTEST", "VPTEST", "VTESTPD", "VTESTPS": + return c.lowerVectorTest(rawOp, ins) case "VPAND": // VPAND src1, src2, dst supports both XMM and YMM widths. @@ -1430,43 +1263,7 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err return true, false, c.storeY(ins.Args[1].Reg, "%"+spl) case "VPSRLDQ", "VPSLLDQ": - // VPSR/LLDQ $imm, Ysrc, Ydst - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects $imm, Ysrc, Ydst: %q", op, ins.Raw) - } - if _, ok := amd64ParseYReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseYReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - n := ins.Args[0].Imm - if n < 0 { - n = 0 - } - if n > 16 { - n = 16 - } - src, err := c.loadY(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - lo := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <32 x i8> %s, <32 x i8> zeroinitializer, <16 x i32> %s\n", lo, src, llvmI32RangeMask(0, 16)) - hi := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <32 x i8> %s, <32 x i8> zeroinitializer, <16 x i32> %s\n", hi, src, llvmI32RangeMask(16, 16)) - lo2 := c.newTmp() - hi2 := c.newTmp() - if op == "VPSLLDQ" { - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %%%s, <16 x i8> zeroinitializer, <16 x i32> %s\n", lo2, lo, llvmShiftLeftBytesMask(n)) - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %%%s, <16 x i8> zeroinitializer, <16 x i32> %s\n", hi2, hi, llvmShiftLeftBytesMask(n)) - } else { - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %%%s, <16 x i8> zeroinitializer, <16 x i32> %s\n", lo2, lo, llvmShiftRightBytesMask(n)) - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %%%s, <16 x i8> zeroinitializer, <16 x i32> %s\n", hi2, hi, llvmShiftRightBytesMask(n)) - } - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %%%s, <16 x i8> %%%s, <32 x i32> %s\n", out, lo2, hi2, llvmI32RangeMask(0, 32)) - return true, false, c.storeY(ins.Args[2].Reg, "%"+out) + return c.lowerPackedByteShift(rawOp, ins) case "VPUNPCKLBW", "VPUNPCKHBW": if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { @@ -1668,57 +1465,122 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", out, sh) return true, false, c.storeX(ins.Args[1].Reg, "%"+out) - case "PSHUFL", "PSHUFD": - // PSHUFL $imm, Xsrc, Xdst - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects $imm, Xsrc, Xdst: %q", op, ins.Raw) + case "PUNPCKHQDQ": + // PUNPCKHQDQ Xsrc/m128, Xdst interleaves the high quadwords: + // dst = {dst[127:64], src[127:64]}. + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 PUNPCKHQDQ expects Xsrc/m128, Xdst: %q", ins.Raw) } if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { return false, false, nil } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil + src, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err } - imm := uint64(ins.Args[0].Imm) & 0xff - idx := func(k uint) uint64 { return (imm >> (2 * k)) & 3 } - src, err := c.loadX(ins.Args[1].Reg) + dstv, err := c.loadX(ins.Args[1].Reg) if err != nil { return true, false, err } - bc1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", bc1, src) - mask := fmt.Sprintf("<4 x i32> ", idx(0), idx(1), idx(2), idx(3)) + dstQ := c.newTmp() + srcQ := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", dstQ, dstv) + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", srcQ, src) sh := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <4 x i32> %%%s, <4 x i32> zeroinitializer, %s\n", sh, bc1, mask) - bc2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %%%s to <16 x i8>\n", bc2, sh) - return true, false, c.storeX(ins.Args[2].Reg, "%"+bc2) + fmt.Fprintf(c.b, " %%%s = shufflevector <2 x i64> %%%s, <2 x i64> %%%s, <2 x i32> \n", sh, dstQ, srcQ) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", out, sh) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) - case "PSHUFHW": - // PSHUFHW $imm, Xsrc, Xdst (shuffle high 4 words; low 4 words unchanged). - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PSHUFHW expects $imm, Xsrc, Xdst: %q", ins.Raw) + case "VPUNPCKLDQ", "VPUNPCKHDQ", "VPUNPCKLQDQ", "VPUNPCKHQDQ": + if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects src1, src2, dst: %q", op, ins.Raw) } - if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { - return false, false, nil + if _, ok := amd64ParseXReg(ins.Args[2].Reg); ok { + a, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + b, err := c.loadXVecOperand(ins.Args[1]) + if err != nil { + return true, false, err + } + laneType := "i64" + lanes := 2 + mask := "" + if op == "VPUNPCKLQDQ" { + mask = "" + } else if op == "VPUNPCKLDQ" { + laneType, lanes = "i32", 4 + mask = "" + } else if op == "VPUNPCKHDQ" { + laneType, lanes = "i32", 4 + mask = "" + } + aq := c.newTmp() + bq := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x %s>\n", aq, a, lanes, laneType) + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x %s>\n", bq, b, lanes, laneType) + sh := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x %s> %%%s, <%d x %s> %%%s, <%d x i32> %s\n", sh, lanes, laneType, bq, lanes, laneType, aq, lanes, mask) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x %s> %%%s to <16 x i8>\n", out, lanes, laneType, sh) + return true, false, c.storeX(ins.Args[2].Reg, "%"+out) + } + if _, ok := amd64ParseYReg(ins.Args[2].Reg); ok { + a, err := c.loadYVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + b, err := c.loadYVecOperand(ins.Args[1]) + if err != nil { + return true, false, err + } + laneType := "i64" + lanes := 4 + mask := "" + if op == "VPUNPCKLQDQ" { + mask = "" + } else if op == "VPUNPCKLDQ" { + laneType, lanes = "i32", 8 + mask = "" + } else if op == "VPUNPCKHDQ" { + laneType, lanes = "i32", 8 + mask = "" + } + aq := c.newTmp() + bq := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <32 x i8> %s to <%d x %s>\n", aq, a, lanes, laneType) + fmt.Fprintf(c.b, " %%%s = bitcast <32 x i8> %s to <%d x %s>\n", bq, b, lanes, laneType) + sh := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x %s> %%%s, <%d x %s> %%%s, <%d x i32> %s\n", sh, lanes, laneType, bq, lanes, laneType, aq, lanes, mask) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x %s> %%%s to <32 x i8>\n", out, lanes, laneType, sh) + return true, false, c.storeY(ins.Args[2].Reg, "%"+out) + } + return false, false, nil + + case "PSHUFL", "PSHUFD": + // PSHUFL/PSHUFD $imm, Xsrc/mem, Xdst. + if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects $imm, Xsrc/mem, Xdst: %q", op, ins.Raw) } if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { return false, false, nil } imm := uint64(ins.Args[0].Imm) & 0xff idx := func(k uint) uint64 { return (imm >> (2 * k)) & 3 } - src, err := c.loadX(ins.Args[1].Reg) + src, err := c.loadXVecOperand(ins.Args[1]) if err != nil { return true, false, err } bc1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <8 x i16>\n", bc1, src) - mask := fmt.Sprintf("<8 x i32> ", - 4+idx(0), 4+idx(1), 4+idx(2), 4+idx(3)) + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", bc1, src) + mask := fmt.Sprintf("<4 x i32> ", idx(0), idx(1), idx(2), idx(3)) sh := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <8 x i16> %%%s, <8 x i16> zeroinitializer, %s\n", sh, bc1, mask) + fmt.Fprintf(c.b, " %%%s = shufflevector <4 x i32> %%%s, <4 x i32> zeroinitializer, %s\n", sh, bc1, mask) bc2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <8 x i16> %%%s to <16 x i8>\n", bc2, sh) + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %%%s to <16 x i8>\n", bc2, sh) return true, false, c.storeX(ins.Args[2].Reg, "%"+bc2) case "SHUFPS": @@ -2187,33 +2049,11 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err return false, false, nil } dst := ins.Args[1].Reg - switch ins.Args[0].Kind { - case OpReg: - v, err := c.loadX(ins.Args[0].Reg) - if err != nil { - return true, false, err - } - return true, false, c.storeX(dst, v) - case OpMem: - addr, err := c.addrFromMem(ins.Args[0].Mem) - if err != nil { - return true, false, err - } - p := c.ptrFromAddrI64(addr) - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load <16 x i8>, ptr %s, align 1\n", ld, p) - return true, false, c.storeX(dst, "%"+ld) - case OpSym: - p, err := c.ptrFromSB(ins.Args[0].Sym) - if err != nil { - return true, false, err - } - ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load <16 x i8>, ptr %s, align 1\n", ld, p) - return true, false, c.storeX(dst, "%"+ld) - default: - return true, false, fmt.Errorf("amd64 %s unsupported src: %q", op, ins.Raw) + value, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, fmt.Errorf("amd64 %s unsupported src %s: %w", op, ins.Args[0].String(), err) } + return true, false, c.storeX(dst, value) } if ins.Args[0].Kind != OpReg { @@ -2226,32 +2066,59 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err if err != nil { return true, false, err } - switch ins.Args[1].Kind { - case OpMem: - addr, err := c.addrFromMem(ins.Args[1].Mem) + if err := c.storeXVecOperand(ins.Args[1], srcv); err != nil { + return true, false, fmt.Errorf("amd64 %s unsupported dst %s: %w", op, ins.Args[1].String(), err) + } + return true, false, nil + + case "PXOR", "POR", "PAND": + if rawOp != op { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, op, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects MMX/m64, MMX or X/m128, X: %q", c.goarch, op, ins.Raw) + } + if _, ok := amd64ParseMReg(ins.Args[1].Reg); ok { + if c.goarch == "386" { + return true, false, fmt.Errorf("386 %s MMX forms are illegal in 32-bit mode: %q", op, ins.Raw) + } + var src string + var err error + if ins.Args[0].Kind == OpReg { + if _, ok := amd64ParseMReg(ins.Args[0].Reg); !ok { + return true, false, fmt.Errorf("amd64 %s MMX form requires an MMX source: %q", op, ins.Raw) + } + src, err = c.loadReg(ins.Args[0].Reg) + } else if isAMD64MemoryOperand(ins.Args[0]) { + src, err = c.evalIntSized(ins.Args[0], I64) + } else { + return true, false, fmt.Errorf("amd64 %s MMX form requires MMX or memory source: %q", op, ins.Raw) + } if err != nil { return true, false, err } - p := c.ptrFromAddrI64(addr) - fmt.Fprintf(c.b, " store <16 x i8> %s, ptr %s, align 1\n", srcv, p) - return true, false, nil - case OpSym: - p, err := c.ptrFromSB(ins.Args[1].Sym) + dst, err := c.loadReg(ins.Args[1].Reg) if err != nil { return true, false, err } - fmt.Fprintf(c.b, " store <16 x i8> %s, ptr %s, align 1\n", srcv, p) - return true, false, nil - default: - return true, false, fmt.Errorf("amd64 %s unsupported dst: %q", op, ins.Raw) + result := c.newTmp() + llvmOp := "and" + if op == "POR" { + llvmOp = "or" + } else if op == "PXOR" { + llvmOp = "xor" + } + fmt.Fprintf(c.b, " %%%s = %s i64 %s, %s\n", result, llvmOp, dst, src) + return true, false, c.storeReg(ins.Args[1].Reg, "%"+result) } - - case "PXOR", "POR", "PAND", "PANDN": - if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 %s expects Xsrc, Xdst: %q", op, ins.Raw) + if !c.isGoLegacyXReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("%s %s destination must be an in-range MMX or X register: %q", c.goarch, op, ins.Raw) } - if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { - return false, false, nil + if ins.Args[0].Kind == OpReg && !c.isGoLegacyXReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("%s %s XMM form requires an in-range X source: %q", c.goarch, op, ins.Raw) + } + if ins.Args[0].Kind == OpMem && !x86MemoryRegistersValidForArch(ins.Args[0].Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s source uses an out-of-range address register: %q", c.goarch, op, ins.Raw) } src, err := c.loadXVecOperand(ins.Args[0]) if err != nil { @@ -2266,16 +2133,12 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err fmt.Fprintf(c.b, " %%%s = xor <16 x i8> %s, %s\n", t, dstv, src) } else if op == "POR" { fmt.Fprintf(c.b, " %%%s = or <16 x i8> %s, %s\n", t, dstv, src) - } else if op == "PANDN" { - notv := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor <16 x i8> %s, %s\n", notv, dstv, llvmAllOnesI8Vec(16)) - fmt.Fprintf(c.b, " %%%s = and <16 x i8> %%%s, %s\n", t, notv, src) } else { fmt.Fprintf(c.b, " %%%s = and <16 x i8> %s, %s\n", t, dstv, src) } return true, false, c.storeX(ins.Args[1].Reg, "%"+t) - case "PADDL", "PADDD", "PADDQ", "PSUBB", "PSUBL": + case "PADDB", "PADDL", "PADDD", "PADDQ", "PSUBB", "PSUBL", "PMULLW": // Two-operand packed arithmetic: dst = dst (+|-) src. if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { return true, false, fmt.Errorf("amd64 %s expects Xsrc, Xdst: %q", op, ins.Raw) @@ -2292,8 +2155,10 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err return true, false, err } vecTy := "<4 x i32>" - if op == "PSUBB" { + if op == "PADDB" || op == "PSUBB" { vecTy = "<16 x i8>" + } else if op == "PMULLW" { + vecTy = "<8 x i16>" } else if op == "PADDQ" { vecTy = "<2 x i64>" } @@ -2308,17 +2173,116 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err bs = "%" + bt } x := c.newTmp() - if op == "PADDL" || op == "PADDD" || op == "PADDQ" { + if op == "PADDB" || op == "PADDL" || op == "PADDD" || op == "PADDQ" { fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", x, vecTy, bs, as) + } else if op == "PMULLW" { + fmt.Fprintf(c.b, " %%%s = mul %s %s, %s\n", x, vecTy, bs, as) } else { fmt.Fprintf(c.b, " %%%s = sub %s %s, %s\n", x, vecTy, bs, as) } - if vecTy == "<16 x i8>" { - return true, false, c.storeX(ins.Args[1].Reg, "%"+x) + if vecTy == "<16 x i8>" { + return true, false, c.storeX(ins.Args[1].Reg, "%"+x) + } + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", out, vecTy, x) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) + + case "PSUBUSB": + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 PSUBUSB expects Xsrc, Xdst: %q", ins.Raw) + } + if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { + return false, false, nil + } + src, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + dst, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return false, false, nil + } + underflow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult <16 x i8> %s, %s\n", underflow, dst, src) + difference := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub <16 x i8> %s, %s\n", difference, dst, src) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <16 x i1> %%%s, <16 x i8> zeroinitializer, <16 x i8> %%%s\n", result, underflow, difference) + return true, false, c.storeX(ins.Args[1].Reg, "%"+result) + + case "PABSD": + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 PABSD expects Xsrc, Xdst: %q", ins.Raw) + } + if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { + return false, false, nil + } + src, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + values := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", values, src) + negative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt <4 x i32> %%%s, zeroinitializer\n", negative, values) + negated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub <4 x i32> zeroinitializer, %%%s\n", negated, values) + absolute := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <4 x i1> %%%s, <4 x i32> %%%s, <4 x i32> %%%s\n", absolute, negative, negated, values) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %%%s to <16 x i8>\n", out, absolute) + return true, false, c.storeX(ins.Args[1].Reg, "%"+out) + + case "PMINUB", "PMINSB", "PMINUW", "PMINSW", "PMINUD", "PMINSD", + "PMAXUB", "PMAXSB", "PMAXUW", "PMAXSW", "PMAXUD", "PMAXSD": + // Two-operand packed integer min/max: dst = min|max(dst, src). + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("amd64 %s expects Xsrc/mem, Xdst: %q", op, ins.Raw) + } + dst, err := c.loadX(ins.Args[1].Reg) + if err != nil { + return false, false, nil + } + src, err := c.loadXVecOperand(ins.Args[0]) + if err != nil { + return true, false, err + } + vecTy := "<16 x i8>" + maskTy := "<16 x i1>" + if strings.HasSuffix(string(op), "W") { + vecTy = "<8 x i16>" + maskTy = "<8 x i1>" + } else if strings.HasSuffix(string(op), "D") { + vecTy = "<4 x i32>" + maskTy = "<4 x i1>" + } + srcv, dstv := src, dst + if vecTy != "<16 x i8>" { + srcBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to %s\n", srcBits, src, vecTy) + srcv = "%" + srcBits + dstBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to %s\n", dstBits, dst, vecTy) + dstv = "%" + dstBits + } + pred := "slt" + if strings.Contains(string(op), "U") { + pred = "ult" } - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", out, vecTy, x) - return true, false, c.storeX(ins.Args[1].Reg, "%"+out) + if strings.HasPrefix(string(op), "PMAX") { + pred = strings.Replace(pred, "lt", "gt", 1) + } + cmp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %s %s %s, %s\n", cmp, pred, vecTy, dstv, srcv) + sel := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %s, %s %s\n", sel, maskTy, cmp, vecTy, dstv, vecTy, srcv) + out := "%" + sel + if vecTy != "<16 x i8>" { + back := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", back, vecTy, sel) + out = "%" + back + } + return true, false, c.storeX(ins.Args[1].Reg, out) case "PSLLW", "PSRLW", "PSLLL", "PSRLL", "PSRAL": // Two-operand packed integer shift immediate. @@ -2369,9 +2333,9 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", out, vecTy, sh) return true, false, c.storeX(ins.Args[1].Reg, "%"+out) - case "PCMPEQL": + case "PCMPEQW", "PCMPEQL": if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PCMPEQL expects Xsrc, Xdst: %q", ins.Raw) + return true, false, fmt.Errorf("amd64 %s expects Xsrc, Xdst: %q", op, ins.Raw) } if _, ok := amd64ParseXReg(ins.Args[0].Reg); !ok { return false, false, nil @@ -2387,123 +2351,27 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err if err != nil { return true, false, err } + laneType := "i32" + lanes := 4 + if op == "PCMPEQW" { + laneType = "i16" + lanes = 8 + } + vecType := fmt.Sprintf("<%d x %s>", lanes, laneType) as := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", as, src) + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to %s\n", as, src, vecType) bs := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", bs, dstv) + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to %s\n", bs, dstv, vecType) cmp := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp eq <4 x i32> %%%s, %%%s\n", cmp, bs, as) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %%%s, %%%s\n", cmp, vecType, bs, as) sext := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sext <4 x i1> %%%s to <4 x i32>\n", sext, cmp) + fmt.Fprintf(c.b, " %%%s = sext <%d x i1> %%%s to %s\n", sext, lanes, cmp, vecType) out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %%%s to <16 x i8>\n", out, sext) + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", out, vecType, sext) return true, false, c.storeX(ins.Args[1].Reg, "%"+out) case "VPCLMULQDQ": - if len(ins.Args) != 4 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg || ins.Args[3].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VPCLMULQDQ expects $imm, Zsrc, Zdst, Zout: %q", ins.Raw) - } - if _, ok := amd64ParseZReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseZReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseZReg(ins.Args[3].Reg); !ok { - return false, false, nil - } - imm := ins.Args[0].Imm & 0xff - src, err := c.loadZ(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - dstv, err := c.loadZ(ins.Args[2].Reg) - if err != nil { - return true, false, err - } - bd := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <64 x i8> %s to <8 x i64>\n", bd, dstv) - bs := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <64 x i8> %s to <8 x i64>\n", bs, src) - lanes := make([]string, 0, 4) - for i := 0; i < 4; i++ { - dlane := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <8 x i64> %%%s, <8 x i64> zeroinitializer, <2 x i32> \n", dlane, bd, i*2, i*2+1) - slane := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <8 x i64> %%%s, <8 x i64> zeroinitializer, <2 x i32> \n", slane, bs, i*2, i*2+1) - call := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %%%s, <2 x i64> %%%s, i8 %d)\n", call, dlane, slane, imm) - lanes = append(lanes, "%"+call) - } - merged0 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <2 x i64> %s, <2 x i64> %s, <4 x i32> \n", merged0, lanes[0], lanes[1]) - merged1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <2 x i64> %s, <2 x i64> %s, <4 x i32> \n", merged1, lanes[2], lanes[3]) - merged := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <4 x i64> %%%s, <4 x i64> %%%s, <8 x i32> \n", merged, merged0, merged1) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <8 x i64> %%%s to <64 x i8>\n", out, merged) - return true, false, c.storeZ(ins.Args[3].Reg, "%"+out) - - case "VPTERNLOGD": - if len(ins.Args) != 4 || ins.Args[0].Kind != OpImm || ins.Args[3].Kind != OpReg { - return true, false, fmt.Errorf("amd64 VPTERNLOGD expects $imm, src1, src2, dst: %q", ins.Raw) - } - if _, ok := amd64ParseYReg(ins.Args[3].Reg); ok { - if ins.Args[1].Kind == OpReg { - if _, ok := amd64ParseYReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - } - if ins.Args[2].Kind == OpReg { - if _, ok := amd64ParseYReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - } - if ins.Args[0].Imm != 0x96 { - return true, false, fmt.Errorf("amd64 VPTERNLOGD only supports imm 0x96 for now: %q", ins.Raw) - } - a, err := c.loadYVecOperand(ins.Args[1]) - if err != nil { - return true, false, err - } - b, err := c.loadYVecOperand(ins.Args[2]) - if err != nil { - return true, false, err - } - dstv, err := c.loadY(ins.Args[3].Reg) - if err != nil { - return true, false, err - } - x1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor <32 x i8> %s, %s\n", x1, dstv, a) - x2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor <32 x i8> %%%s, %s\n", x2, x1, b) - return true, false, c.storeY(ins.Args[3].Reg, "%"+x2) - } - if _, ok := amd64ParseZReg(ins.Args[3].Reg); !ok { - return false, false, nil - } - if ins.Args[0].Imm != 0x96 { - return true, false, fmt.Errorf("amd64 VPTERNLOGD only supports imm 0x96 for now: %q", ins.Raw) - } - a, err := c.loadZVecOperand(ins.Args[1]) - if err != nil { - return true, false, err - } - b, err := c.loadZVecOperand(ins.Args[2]) - if err != nil { - return true, false, err - } - dstv, err := c.loadZ(ins.Args[3].Reg) - if err != nil { - return true, false, err - } - x1 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor <64 x i8> %s, %s\n", x1, dstv, a) - x2 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor <64 x i8> %%%s, %s\n", x2, x1, b) - return true, false, c.storeZ(ins.Args[3].Reg, "%"+x2) + return c.lowerPackedCarrylessMultiply(rawOp, ins) case "VEXTRACTF32X4": if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { @@ -2525,34 +2393,7 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err return true, false, c.storeX(ins.Args[2].Reg, "%"+out) case "PCLMULQDQ": - // PCLMULQDQ $imm, Xsrc, Xdst => Xdst = pclmul(Xdst, Xsrc, imm) - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PCLMULQDQ expects $imm, Xsrc, Xdst: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - imm := ins.Args[0].Imm & 0xff - src, err := c.loadX(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - dstv, err := c.loadX(ins.Args[2].Reg) - if err != nil { - return true, false, err - } - bd := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", bd, dstv) - bs := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", bs, src) - call := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %%%s, <2 x i64> %%%s, i8 %d)\n", call, bd, bs, imm) - bc := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", bc, call) - return true, false, c.storeX(ins.Args[2].Reg, "%"+bc) + return c.lowerPackedCarrylessMultiply(rawOp, ins) case "PCMPEQB", "PCMPGTB": if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { @@ -2627,108 +2468,6 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err fmt.Fprintf(c.b, " %%%s = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %s, <16 x i8> %s)\n", call, dst, mask) return true, false, c.storeX(ins.Args[1].Reg, "%"+call) - case "PINSRQ": - // PINSRQ $imm, src64, Xdst - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PINSRQ expects $imm, src, Xdst: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - idx := ins.Args[0].Imm & 1 - src, err := c.evalI64(ins.Args[1]) - if err != nil { - return true, false, err - } - dst, err := c.loadX(ins.Args[2].Reg) - if err != nil { - return true, false, err - } - bc := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", bc, dst) - insv := c.newTmp() - fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> %%%s, i64 %s, i32 %d\n", insv, bc, src, idx) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", out, insv) - return true, false, c.storeX(ins.Args[2].Reg, "%"+out) - - case "PINSRD": - // PINSRD $imm, src32, Xdst - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PINSRD expects $imm, src, Xdst: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - idx := ins.Args[0].Imm & 3 - src64, err := c.evalI64(ins.Args[1]) - if err != nil { - return true, false, err - } - src32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", src32, src64) - dst, err := c.loadX(ins.Args[2].Reg) - if err != nil { - return true, false, err - } - bc := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", bc, dst) - insv := c.newTmp() - fmt.Fprintf(c.b, " %%%s = insertelement <4 x i32> %%%s, i32 %%%s, i32 %d\n", insv, bc, src32, idx) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <4 x i32> %%%s to <16 x i8>\n", out, insv) - return true, false, c.storeX(ins.Args[2].Reg, "%"+out) - - case "PINSRW": - // PINSRW $imm, src16, Xdst - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PINSRW expects $imm, src, Xdst: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - idx := ins.Args[0].Imm & 7 - src64, err := c.evalI64(ins.Args[1]) - if err != nil { - return true, false, err - } - src16 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i16\n", src16, src64) - dst, err := c.loadX(ins.Args[2].Reg) - if err != nil { - return true, false, err - } - bc := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <8 x i16>\n", bc, dst) - insv := c.newTmp() - fmt.Fprintf(c.b, " %%%s = insertelement <8 x i16> %%%s, i16 %%%s, i32 %d\n", insv, bc, src16, idx) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = bitcast <8 x i16> %%%s to <16 x i8>\n", out, insv) - return true, false, c.storeX(ins.Args[2].Reg, "%"+out) - - case "PINSRB": - // PINSRB $imm, src8, Xdst - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PINSRB expects $imm, src, Xdst: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - idx := ins.Args[0].Imm & 15 - src64, err := c.evalI64(ins.Args[1]) - if err != nil { - return true, false, err - } - src8 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i8\n", src8, src64) - dst, err := c.loadX(ins.Args[2].Reg) - if err != nil { - return true, false, err - } - insv := c.newTmp() - fmt.Fprintf(c.b, " %%%s = insertelement <16 x i8> %s, i8 %%%s, i32 %d\n", insv, dst, src8, idx) - return true, false, c.storeX(ins.Args[2].Reg, "%"+insv) - case "PEXTRB": // PEXTRB $imm, Xsrc, dst if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg { @@ -2801,84 +2540,27 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err } case "PALIGNR": - // PALIGNR $imm, Xsrc, Xdst ; dst = alignr(dst, src, imm) - if len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PALIGNR expects $imm, Xsrc, Xdst: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - if _, ok := amd64ParseXReg(ins.Args[2].Reg); !ok { - return false, false, nil - } - n := ins.Args[0].Imm - if n < 0 { - n = 0 - } - if n > 255 { - n = 255 - } - src, err := c.loadX(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - dst, err := c.loadX(ins.Args[2].Reg) - if err != nil { - return true, false, err - } - sh := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %s, <16 x i8> %s, <16 x i32> %s\n", sh, dst, src, llvmAlignRightBytesMask(n)) - return true, false, c.storeX(ins.Args[2].Reg, "%"+sh) + return c.lowerPackedAlignRight(rawOp, ins) - case "PSRLDQ": - // PSRLDQ $imm, Xdst - if len(ins.Args) != 2 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PSRLDQ expects $imm, Xdst: %q", ins.Raw) - } - if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { - return false, false, nil - } - n := ins.Args[0].Imm - if n < 0 || n > 16 { - return true, false, fmt.Errorf("amd64 PSRLDQ invalid imm %d: %q", n, ins.Raw) - } - v, err := c.loadX(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - shuf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %s, <16 x i8> zeroinitializer, <16 x i32> %s\n", shuf, v, llvmShiftRightBytesMask(n)) - return true, false, c.storeX(ins.Args[1].Reg, "%"+shuf) + case "PSRLDQ", "PSLLDQ": + return c.lowerPackedByteShift(rawOp, ins) - case "PSLLDQ": - // PSLLDQ $imm, Xdst + case "PSRLQ", "PSLLQ": + // PSR/LLQ $imm, Xdst (shift each 64-bit lane). Counts at or above + // the lane width clear the destination rather than wrapping modulo 64. if len(ins.Args) != 2 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PSLLDQ expects $imm, Xdst: %q", ins.Raw) + return true, false, fmt.Errorf("amd64 %s expects $imm, Xdst: %q", op, ins.Raw) } if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { return false, false, nil } n := ins.Args[0].Imm - if n < 0 || n > 16 { - return true, false, fmt.Errorf("amd64 PSLLDQ invalid imm %d: %q", n, ins.Raw) - } - v, err := c.loadX(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - shuf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %s, <16 x i8> zeroinitializer, <16 x i32> %s\n", shuf, v, llvmShiftLeftBytesMask(n)) - return true, false, c.storeX(ins.Args[1].Reg, "%"+shuf) - - case "PSRLQ": - // PSRLQ $imm, Xdst (shift each 64-bit lane right) - if len(ins.Args) != 2 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("amd64 PSRLQ expects $imm, Xdst: %q", ins.Raw) + if n < 0 { + return true, false, fmt.Errorf("amd64 %s shift count must be non-negative: %q", op, ins.Raw) } - if _, ok := amd64ParseXReg(ins.Args[1].Reg); !ok { - return false, false, nil + if n >= 64 { + return true, false, c.storeX(ins.Args[1].Reg, "zeroinitializer") } - n := ins.Args[0].Imm & 63 v, err := c.loadX(ins.Args[1].Reg) if err != nil { return true, false, err @@ -2886,7 +2568,11 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err bc := c.newTmp() fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", bc, v) sh := c.newTmp() - fmt.Fprintf(c.b, " %%%s = lshr <2 x i64> %%%s, \n", sh, bc, n, n) + shiftOp := "lshr" + if op == "PSLLQ" { + shiftOp = "shl" + } + fmt.Fprintf(c.b, " %%%s = %s <2 x i64> %%%s, \n", sh, shiftOp, bc, n, n) back := c.newTmp() fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", back, sh) return true, false, c.storeX(ins.Args[1].Reg, "%"+back) @@ -2930,6 +2616,66 @@ func (c *amd64Ctx) lowerVec(op Op, ins Instr) (ok bool, terminated bool, err err return false, false, nil } +func (c *amd64Ctx) validateMOVDAliasForm(ins Instr) error { + if len(ins.Args) != 2 { + return fmt.Errorf("%s MOVD expects 2 operands: %q", c.goarch, ins.Raw) + } + src, dst := ins.Args[0], ins.Args[1] + srcMem, dstMem := isAMD64MemoryOperand(src), isAMD64MemoryOperand(dst) + srcX, dstX := isAMD64MOVDXRegister(src), isAMD64MOVDXRegister(dst) + srcM, dstM := isAMD64MOVDMRegister(src), isAMD64MOVDMRegister(dst) + srcGP, dstGP := c.isGoYrlRegister(src), c.isGoYrlRegister(dst) + + valid := false + if c.goarch == "386" { + // In 32-bit mode AMOVQ has only its memory/MMX/XMM rows. Go rejects + // every GP and immediate form as an illegal 64-bit instruction. + valid = (dstMem && (srcX || srcM)) || + (dstX && (srcMem || srcX)) || + (dstM && (srcMem || srcX)) + } else { + valid = (dstGP && (src.Kind == OpImm || srcGP || srcMem || srcX || srcM)) || + (dstMem && (src.Kind == OpImm || srcGP || srcX || srcM)) || + (dstX && (srcGP || srcMem || srcX)) || + (dstM && (srcGP || srcMem || srcX || srcM)) + } + if !valid { + return fmt.Errorf("%s MOVD operands are outside Go 1.27's MOVD/ymovq forms: %q", c.goarch, ins.Raw) + } + return nil +} + +func isAMD64MOVDXRegister(op Operand) bool { + if op.Kind != OpReg { + return false + } + _, ok := amd64ParseXReg(op.Reg) + return ok +} + +func isAMD64MOVDMRegister(op Operand) bool { + if op.Kind != OpReg { + return false + } + _, ok := amd64ParseMReg(op.Reg) + return ok +} + +func (c *amd64Ctx) isGoYrlRegister(op Operand) bool { + if op.Kind != OpReg || !isAMD64YrlRegister(op.Reg) { + return false + } + if c.goarch != "386" { + return true + } + switch op.Reg { + case AX, BX, CX, DX, SP, BP, SI, DI: + return true + default: + return false + } +} + func llvmShiftRightBytesMask(n int64) string { // shufflevector mask for right shift by n bytes. // Use second vector's element 0 (index 16) as the "zero" source. @@ -2970,29 +2716,6 @@ func llvmShiftLeftBytesMask(n int64) string { return sb.String() } -func llvmAlignRightBytesMask(n int64) string { - // shufflevector mask for alignr(dst, src, n): - // result bytes are selected from concatenation [dst, src], right shifted by n. - var sb strings.Builder - sb.WriteString("<") - for i := 0; i < 16; i++ { - if i != 0 { - sb.WriteString(", ") - } - idx := int64(i) + n - switch { - case idx < 16: - fmt.Fprintf(&sb, "i32 %d", idx) - case idx < 32: - fmt.Fprintf(&sb, "i32 %d", idx) - default: - sb.WriteString("i32 16") - } - } - sb.WriteString(">") - return sb.String() -} - func llvmRepeatI8Mask(chunk, width int) string { if chunk <= 0 { chunk = 1 @@ -3009,6 +2732,50 @@ func llvmRepeatI8Mask(chunk, width int) string { return sb.String() } +func llvmVPSHUFDMask(lanes int, imm uint64) string { + var b strings.Builder + b.WriteByte('<') + for lane := 0; lane < lanes; lane++ { + if lane != 0 { + b.WriteString(", ") + } + base := lane &^ 3 + selected := base + int((imm>>uint(2*(lane&3)))&3) + fmt.Fprintf(&b, "i32 %d", selected) + } + b.WriteByte('>') + return b.String() +} + +func llvmSplatInteger(lanes, bits int, value uint64) string { + var b strings.Builder + b.WriteByte('<') + for lane := 0; lane < lanes; lane++ { + if lane != 0 { + b.WriteString(", ") + } + fmt.Fprintf(&b, "i%d %d", bits, value) + } + b.WriteByte('>') + return b.String() +} + +func amd64SplatInteger(c *amd64Ctx, lanes, bits int, value string) string { + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> poison, i%d %s, i32 0\n", seed, lanes, bits, bits, value) + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %%%s, <%d x i%d> poison, <%d x i32> zeroinitializer\n", splat, lanes, bits, seed, lanes, bits, lanes) + return "%" + splat +} + +func amd64SplatI1(c *amd64Ctx, lanes int, value string) string { + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i1> poison, i1 %s, i32 0\n", seed, lanes, value) + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i1> %%%s, <%d x i1> poison, <%d x i32> zeroinitializer\n", splat, lanes, seed, lanes, lanes) + return "%" + splat +} + func llvmAllOnesI8Vec(n int) string { if n <= 0 { return "<>" @@ -3030,6 +2797,16 @@ func isAMD64ZReg(r Reg) bool { return ok } +func isAMD64XReg(r Reg) bool { + _, ok := amd64ParseXReg(r) + return ok +} + +func isAMD64YReg(r Reg) bool { + _, ok := amd64ParseYReg(r) + return ok +} + func llvmI32RangeMask(start int, n int) string { // Build . if n <= 0 { @@ -3069,6 +2846,34 @@ func amd64MaskBitI1(c *amd64Ctx, mask string, idx int) string { return "%" + bit } +func amd64ApplyI32LaneMask(c *amd64Ctx, lanes int, computed, old, mask string, zeroing bool) string { + return amd64ApplyIntegerLaneMask(c, lanes, 32, computed, old, mask, zeroing) +} + +func amd64ApplyIntegerLaneMask(c *amd64Ctx, lanes, bits int, computed, old, mask string, zeroing bool) string { + result := old + if zeroing { + result = "zeroinitializer" + } + for lane := 0; lane < lanes; lane++ { + bit := amd64MaskBitI1(c, mask, lane) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", value, lanes, bits, computed, lane) + fallback := "0" + if !zeroing { + oldValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", oldValue, lanes, bits, old, lane) + fallback = "%" + oldValue + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %%%s, i%d %s\n", selected, bit, bits, value, bits, fallback) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", inserted, lanes, bits, result, bits, selected, lane) + result = "%" + inserted + } + return result +} + func amd64PackI1x8ToI64(c *amd64Ctx, pred string) string { acc := "0" for i := 0; i < 8; i++ { diff --git a/amd64_lower_vecflags.go b/amd64_lower_vecflags.go new file mode 100644 index 00000000..dc4de0f9 --- /dev/null +++ b/amd64_lower_vecflags.go @@ -0,0 +1,144 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64VectorTestSpec struct { + maxBytes int + vector bool + signLaneBits int +} + +// amd64VectorTestSpecs models the complete Go 1.27 PTEST/VPTEST/VTEST grammar. +// PTEST uses the legacy yxm_q4 X/m128 row. The VEX instructions share +// _yvptest's X/m128,X and Y/m256,Y rows. VTESTPD and VTESTPS consider only the +// sign bit in each floating-point lane; PTEST and VPTEST consider every bit. +var amd64VectorTestSpecs = map[Op]amd64VectorTestSpec{ + "PTEST": {maxBytes: 16}, + "VPTEST": {maxBytes: 32, vector: true}, + "VTESTPD": {maxBytes: 32, vector: true, signLaneBits: 64}, + "VTESTPS": {maxBytes: 32, vector: true, signLaneBits: 32}, +} + +func (c *amd64Ctx) lowerVectorTest(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64VectorTestSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s has no suffixed form in Go 1.27: %q", c.goarch, baseOp, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("%s %s expects vector/memory source and vector destination: %q", c.goarch, baseOp, ins.Raw) + } + + source, destination := ins.Args[0], ins.Args[1] + byteWidth := amd64VectorByteWidth(destination.Reg) + if (byteWidth != 16 && byteWidth != 32) || byteWidth > spec.maxBytes { + return true, false, fmt.Errorf("%s %s destination width is outside its Go 1.27 table: %q", c.goarch, baseOp, ins.Raw) + } + if spec.vector { + // Go's VEX classes admit X/Y0-15 even in 386 mode. They also admit + // extended address registers there, so do not apply the legacy 386 + // register filter to VEX memory operands. + if !amd64VEXVectorRegister(destination, byteWidth) { + return true, false, fmt.Errorf("%s %s destination is outside Go's VEX X/Y class: %q", c.goarch, baseOp, ins.Raw) + } + } else if byteWidth != 16 || !c.isGoLegacyXReg(destination.Reg) { + return true, false, fmt.Errorf("%s %s destination is outside Go's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + + if source.Kind == OpReg { + if spec.vector { + if !amd64VEXVectorRegister(source, byteWidth) { + return true, false, fmt.Errorf("%s %s source must match the destination's VEX width: %q", c.goarch, baseOp, ins.Raw) + } + } else if byteWidth != 16 || !c.isGoLegacyXReg(source.Reg) { + return true, false, fmt.Errorf("%s %s source is outside Go's legacy X class: %q", c.goarch, baseOp, ins.Raw) + } + } else if !isAMD64MemoryOperand(source) { + return true, false, fmt.Errorf("%s %s source must be a same-width vector register or memory: %q", c.goarch, baseOp, ins.Raw) + } + if !spec.vector && source.Kind == OpMem && !x86MemoryRegistersValidForArch(source.Mem, c.goarch) { + return true, false, fmt.Errorf("%s %s source uses an out-of-range legacy address register: %q", c.goarch, baseOp, ins.Raw) + } + + sourceBytes, err := c.loadPackedCompareBytes(source, byteWidth) + if err != nil { + return true, false, err + } + destinationBytes, err := c.loadPackedCompareBytes(destination, byteWidth) + if err != nil { + return true, false, err + } + + intersection := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and <%d x i8> %s, %s\n", intersection, byteWidth, destinationBytes, sourceBytes) + invertedDestination := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor <%d x i8> %s, %s\n", invertedDestination, byteWidth, destinationBytes, llvmAllOnesI8Vec(byteWidth)) + outsideDestination := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and <%d x i8> %%%s, %s\n", outsideDestination, byteWidth, invertedDestination, sourceBytes) + + var zero, carry string + if spec.signLaneBits == 0 { + // Avoid an i256 scalar: LLVM 22 aborts while legalizing that type for + // i386. Reducing individual bytes compiles on every supported target. + zero = c.emitVectorBytesAreZero(byteWidth, "%"+intersection) + carry = c.emitVectorBytesAreZero(byteWidth, "%"+outsideDestination) + } else { + zero = c.emitNoSignBits(byteWidth, spec.signLaneBits, "%"+intersection) + carry = c.emitNoSignBits(byteWidth, spec.signLaneBits, "%"+outsideDestination) + } + + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", zero, c.flagsZSlot) + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", carry, c.flagsCFSlot) + // Intel defines OF, SF, and PF as cleared for all four instructions. + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsSltSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsPFSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) + return true, false, nil +} + +func (c *amd64Ctx) emitVectorBytesAreZero(byteWidth int, bytes string) string { + // Extract bytes directly. LLVM 22's i386 backend also aborts on some + // otherwise-valid bitcasts between illegal 256-bit vector types. + combined := "0" + for index := 0; index < byteWidth; index++ { + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i8> %s, i32 %d\n", element, byteWidth, bytes, index) + merged := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i8 %s, %%%s\n", merged, combined, element) + combined = "%" + merged + } + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i8 %s, 0\n", zero, combined) + return "%" + zero +} + +func (c *amd64Ctx) emitNoSignBits(byteWidth, laneBits int, bytes string) string { + lanes := byteWidth * 8 / laneBits + any := "false" + for lane := 0; lane < lanes; lane++ { + // X86 is little-endian, so each lane's sign bit is the high bit of + // its final byte. Testing that byte avoids illegal 256-bit vector + // bitcasts in LLVM 22's i386 legalizer. + index := (lane+1)*(laneBits/8) - 1 + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i8> %s, i32 %d\n", element, byteWidth, bytes, index) + negative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i8 %%%s, 0\n", negative, element) + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %s, %%%s\n", combined, any, negative) + any = "%" + combined + } + none := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", none, any) + return "%" + none +} diff --git a/amd64_lower_vecflags_test.go b/amd64_lower_vecflags_test.go new file mode 100644 index 00000000..fbe690ab --- /dev/null +++ b/amd64_lower_vecflags_test.go @@ -0,0 +1,237 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64VectorTestGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64VectorTestSpec{ + "PTEST": {maxBytes: 16}, + "VPTEST": {maxBytes: 32, vector: true}, + "VTESTPD": {maxBytes: 32, vector: true, signLaneBits: 64}, + "VTESTPS": {maxBytes: 32, vector: true, signLaneBits: 32}, + } + if len(amd64VectorTestSpecs) != len(expected) { + t.Fatalf("vector-test grammar has %d entries, want %d", len(amd64VectorTestSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64VectorTestSpecs[op]; !ok { + t.Errorf("vector-test grammar omitted %s", op) + } else if got != want { + t.Errorf("vector-test grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86VectorTestCompleteGoFormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + legacyLast := 15 + if target.goarch == "386" { + legacyLast = 7 + } + source := fmt.Sprintf(`TEXT vectortestforms(SB),$0-0 + PTEST X0, X%d + PTEST 0(AX), X%d + VPTEST X0, X15 + VPTEST 16(R9), X15 + VPTEST Y0, Y15 + VPTEST 32(R9), Y15 + VTESTPD X0, X15 + VTESTPD 48(R9), X15 + VTESTPD Y0, Y15 + VTESTPD 64(R9), Y15 + VTESTPS X0, X15 + VTESTPS 80(R9), X15 + VTESTPS Y0, Y15 + VTESTPS 96(R9), Y15 + RET +`, legacyLast, legacyLast) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "vectortestforms": {Name: "vectortestforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"<16 x i8>", "<32 x i8>", "store i1"} { + if !strings.Contains(ir, want) { + t.Fatalf("vector-test lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "vector-test-"+target.name+".ll", "vector-test-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86VectorTestRejectsFormsOutsideGoTables(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "PTEST Y0, Y1"}, + {goarch: "amd64", instruction: "PTEST X0, 0(AX)"}, + {goarch: "amd64", instruction: "PTEST X16, X0"}, + {goarch: "amd64", instruction: "PTEST.Z X0, X1"}, + {goarch: "386", instruction: "PTEST X8, X0"}, + {goarch: "386", instruction: "PTEST 0(R9), X0"}, + {goarch: "amd64", instruction: "VPTEST X0, Y1"}, + {goarch: "amd64", instruction: "VPTEST Z0, Z1"}, + {goarch: "amd64", instruction: "VPTEST X16, X0"}, + {goarch: "amd64", instruction: "VPTEST.Z X0, X1"}, + {goarch: "amd64", instruction: "VTESTPD X0, Y1"}, + {goarch: "amd64", instruction: "VTESTPD Z0, Z1"}, + {goarch: "amd64", instruction: "VTESTPS X16, X0"}, + {goarch: "amd64", instruction: "VTESTPS X0, X1, X2"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside the Go 1.27 vector-test tables", test.instruction) + } + }) + } +} + +func TestAMD64VectorTestRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT vectortestsemantics(SB),$0-24 + MOVQ out+0(FP), CX + MOVQ source+8(FP), AX + MOVQ destination+16(FP), BX + MOVUPS 0(AX), X0 + MOVUPS 0(BX), X1 + MOVB $0x7f, DL + ADDB $1, DL + PTEST X0, X1 + SETEQ 0(CX) + SETCS 1(CX) + SETMI 2(CX) + SETOS 3(CX) + SETPS 4(CX) + + MOVQ source+8(FP), AX + MOVQ destination+16(FP), BX + VMOVDQU 32(BX), Y1 + XORB DL, DL + VPTEST 32(AX), Y1 + SETEQ 5(CX) + SETCS 6(CX) + SETMI 7(CX) + SETOS 8(CX) + SETPS 9(CX) + + MOVQ source+8(FP), AX + MOVQ destination+16(FP), BX + MOVUPS 64(BX), X1 + VTESTPS 64(AX), X1 + SETEQ 10(CX) + SETCS 11(CX) + SETMI 12(CX) + SETOS 13(CX) + SETPS 14(CX) + + MOVQ source+8(FP), AX + MOVQ destination+16(FP), BX + VMOVDQU 96(BX), Y1 + VTESTPD 96(AX), Y1 + SETEQ 15(CX) + SETCS 16(CX) + SETMI 17(CX) + SETOS 18(CX) + SETPS 19(CX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{"vectortestsemantics": { + Name: "vectortestsemantics", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void vectortestsemantics(uint8_t *, const uint8_t *, const uint8_t *); +int main(void) { + uint8_t source[128] = {0}, destination[128] = {0}, out[20] = {0}; + source[0] = 1; + source[32] = 1; destination[32] = 1; + source[64] = 1; destination[64] = 1; + source[103] = 0x80; + vectortestsemantics(out, source, destination); + const uint8_t want[20] = { + 1, 0, 0, 0, 0, + 0, 1, 0, 0, 0, + 1, 1, 0, 0, 0, + 1, 0, 0, 0, 0, + }; + for (int i = 0; i < 20; i++) if (out[i] != want[i]) return 10 + i; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "vector_test_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_vextractps_test.go b/amd64_lower_vextractps_test.go new file mode 100644 index 00000000..6a79ec29 --- /dev/null +++ b/amd64_lower_vextractps_test.go @@ -0,0 +1,219 @@ +package plan9asm + +import ( + "reflect" + "runtime" + "sort" + "strings" + "testing" +) + +func TestAMD64PackedScalarExtractGrammarIsComplete(t *testing.T) { + got := make([]string, 0, len(amd64PackedScalarExtractSpecs)) + for op := range amd64PackedScalarExtractSpecs { + got = append(got, string(op)) + } + sort.Strings(got) + want := []string{ + "EXTRACTPS", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", + "VEXTRACTPS", "VPEXTRB", "VPEXTRD", "VPEXTRQ", "VPEXTRW", + } + if !reflect.DeepEqual(got, want) { + t.Fatalf("packed scalar-extract grammar opcodes = %v, want %v", got, want) + } +} + +func TestTranslateX86ExtractPSCompleteGo127Forms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + highX, highGP := "X15", "R15" + if target.goarch == "386" { + highX, highGP = "X7", "DI" + } + source := "TEXT extractpsforms(SB),$0-0\n" + + "\tEXTRACTPS $0, X0, AX\n" + + "\tEXTRACTPS $3, " + highX + ", (BX)\n" + + "\tEXTRACTPS $2, " + highX + ", " + highGP + "\n" + + "\tVEXTRACTPS $-128, X0, AX\n" + + "\tVPEXTRQ $0, X0, (BX)\n" + + "\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"extractpsforms": {Name: "extractpsforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "extractps-"+target.name+".ll", "extractps-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86ExtractPSRejectsFormsOutsideGo127Table(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "EXTRACTPS $-1, X0, AX"}, + {goarch: "amd64", instruction: "EXTRACTPS $4, X0, AX"}, + {goarch: "amd64", instruction: "EXTRACTPS $0, X16, AX"}, + {goarch: "amd64", instruction: "EXTRACTPS $0, X0, M0"}, + {goarch: "386", instruction: "EXTRACTPS $0, X8, AX"}, + {goarch: "386", instruction: "EXTRACTPS $0, X0, R8"}, + {goarch: "386", instruction: "PEXTRQ $0, X0, AX"}, + } { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "$", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scalar-extract tables", test.instruction) + } + }) + } +} + +func TestAMD64ExtractPSRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT extractpssemantics(SB),NOSPLIT,$0-16 + MOVQ in+0(FP), AX + MOVQ out+8(FP), BX + MOVUPS (AX), X0 + EXTRACTPS $0, X0, CX + MOVL CX, 0(BX) + EXTRACTPS $3, X0, 4(BX) + VEXTRACTPS $2, X0, DX + MOVL DX, 8(BX) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"extractpssemantics": { + Name: "extractpssemantics", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void extractpssemantics(void *, void *); +int main(void) { + uint32_t in[4] = {0x3f800001,0x40000002,0x40400003,0x40800004}, out[3] = {0}; + extractpssemantics(in, out); + return out[0] == in[0] && out[1] == in[3] && out[2] == in[2] ? 0 : 10; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "extractps_semantics", triple, ir, mainC, runPrefix) +} + +func TestTranslateAMD64VExtractPSCompleteGo127Forms(t *testing.T) { + const source = `TEXT vextractpsforms(SB),$0-0 + VEXTRACTPS $-128, X0, AX + VEXTRACTPS $255, X1, (AX) + VEXTRACTPS $255, X31, R15 + RET +` + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: target.triple, + Sigs: map[string]FuncSig{"vextractpsforms": {Name: "vextractpsforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "vextractps-"+target.name+".ll", "vextractps-"+target.name+".o", ir) + }) + } +} + +func TestTranslateAMD64VExtractPSRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "VEXTRACTPS $-129, X1, AX", + "VEXTRACTPS $-1, X31, AX", + "VEXTRACTPS $256, X1, AX", + "VEXTRACTPS $1, Y1, AX", + "VEXTRACTPS $1, X1, X2", + } { + t.Run(instruction, func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yvextractps table", instruction) + } + }) + } +} diff --git a/amd64_lower_vinserti128_test.go b/amd64_lower_vinserti128_test.go new file mode 100644 index 00000000..52a67c52 --- /dev/null +++ b/amd64_lower_vinserti128_test.go @@ -0,0 +1,163 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateX86VINSERTI128CompleteGo127Forms(t *testing.T) { + const source = `TEXT vinserti128_forms(SB),$0-0 + VINSERTI128 $0, X0, Y1, Y2 + VINSERTI128 $255, 8(BX), Y15, Y15 + VINSERTI128 $1, X15, Y0, Y1 + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "vinserti128_forms": {Name: "vinserti128_forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "vinserti128-"+target.name+".ll", "vinserti128-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86VINSERTI128RejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "VINSERTI128 X0, Y1, Y2", + "VINSERTI128 $0, X0, Y1", + "VINSERTI128 $-1, X0, Y1, Y2", + "VINSERTI128 $256, X0, Y1, Y2", + "VINSERTI128 AX, X0, Y1, Y2", + "VINSERTI128 $0, Y0, Y1, Y2", + "VINSERTI128 $0, X16, Y1, Y2", + "VINSERTI128 $0, X0, X1, Y2", + "VINSERTI128 $0, X0, Y16, Y2", + "VINSERTI128 $0, X0, Y1, X2", + "VINSERTI128 $0, X0, Y1, Y16", + "VINSERTI128 $0, X0, Y1, 8(BX)", + "VINSERTI128.Z $0, X0, Y1, Y2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VINSERTI128 table", instruction) + } + }) + } + const source386 = "TEXT bad(SB),$0-0\n\tVINSERTI128 $0, X0, Y1, Y2\n\tRET\n" + requireX86GoAssemblerResult(t, "386", source386, false) + file, err := Parse(ArchAMD64, source386) + if err == nil { + if _, err := Translate(file, Options{ + Goarch: "386", + TargetTriple: "i386-unknown-linux-gnu", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatal("Translate accepted 386 VINSERTI128 despite Go 1.27's frontend operand limit") + } + } +} + +func TestAMD64VINSERTI128RuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT vinserti128Semantics(SB),$0-24 + MOVQ out+0(FP), AX + MOVQ narrow+8(FP), BX + MOVQ wide+16(FP), CX + VMOVDQU64 (BX), X0 + VMOVDQU64 (CX), Y1 + VINSERTI128 $0, X0, Y1, Y2 + VMOVDQU64 Y2, 0(AX) + VINSERTI128 $255, X0, Y1, Y3 + VMOVDQU64 Y3, 32(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "vinserti128Semantics": { + Name: "vinserti128Semantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: frame, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void vinserti128Semantics(uint64_t *, const uint64_t *, const uint64_t *); +int main(void) { + const uint64_t narrow[2] = {10, 11}; + const uint64_t wide[4] = {20, 21, 22, 23}; + uint64_t out[8] = {0}; + const uint64_t want[8] = {10, 11, 22, 23, 20, 21, 10, 11}; + vinserti128Semantics(out, narrow, wide); + for (int i = 0; i < 8; i++) if (out[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "vinserti128", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_vmov_half_test.go b/amd64_lower_vmov_half_test.go new file mode 100644 index 00000000..52206aa0 --- /dev/null +++ b/amd64_lower_vmov_half_test.go @@ -0,0 +1,167 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestAMD64MoveHalfGrammarCoversCompleteGoFamily(t *testing.T) { + expected := map[Op]amd64MoveHalfSpec{ + "MOVLPS": {}, + "MOVHPS": {high: true}, + "MOVLPD": {}, + "MOVHPD": {high: true}, + "VMOVLPS": {vector: true}, + "VMOVHPS": {high: true, vector: true}, + "VMOVLPD": {vector: true}, + "VMOVHPD": {high: true, vector: true}, + } + if len(amd64MoveHalfSpecs) != len(expected) { + t.Fatalf("move-half grammar has %d entries, want %d", len(amd64MoveHalfSpecs), len(expected)) + } + for op, want := range expected { + if got, ok := amd64MoveHalfSpecs[op]; !ok { + t.Errorf("move-half grammar omitted %s", op) + } else if got != want { + t.Errorf("move-half grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86VEXMoveHalfCompleteFormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + base, last := 30, 31 + if target.goarch == "386" { + base, last = 6, 7 + } + var source strings.Builder + source.WriteString("TEXT vmovhalfforms(SB),$0-0\n") + for _, op := range []string{"VMOVLPS", "VMOVHPS", "VMOVLPD", "VMOVHPD"} { + fmt.Fprintf(&source, "\t%s X%d, 0(AX)\n", op, last) + fmt.Fprintf(&source, "\t%s 8(AX), X%d, X%d\n", op, base, last) + } + source.WriteString("\tRET\n") + requireX86GoAssemblerResult(t, target.goarch, source.String(), true) + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: target.goarch, TargetTriple: target.triple, Sigs: map[string]FuncSig{"vmovhalfforms": {Name: "vmovhalfforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "extractelement <2 x i64>") || !strings.Contains(ir, "insertelement <2 x i64>") { + t.Fatalf("VEX half-move lowering omitted lane operations:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "vmov-half-"+target.name+".ll", "vmov-half-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86VEXMoveHalfRejectsFormsOutsideGoTable(t *testing.T) { + for _, instruction := range []string{ + "VMOVHPS.Z 0(AX), X1, X2", + "VMOVLPS Y0, 0(AX)", + "VMOVHPD 0(AX), Y1, Y2", + "VMOVLPD X0, X1, X2", + "VMOVHPS 0(AX), X1", + "VMOVLPS X0, X1", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's _yvmovhpd table", instruction) + } + }) + } +} + +func TestAMD64VEXMoveHalfRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT vmovhalfsemantics(SB),$0-24 + MOVQ out+0(FP), AX + MOVQ base+8(FP), CX + MOVQ half+16(FP), DX + MOVUPS 0(CX), X1 + STC + VMOVHPS 0(DX), X1, X2 + MOVUPS X2, 0(AX) + VMOVLPS 0(DX), X1, X3 + MOVUPS X3, 16(AX) + SETCS 32(AX) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{"vmovhalfsemantics": { + Name: "vmovhalfsemantics", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void vmovhalfsemantics(uint8_t *, const uint64_t *, const uint64_t *); +int main(void) { + uint8_t out[33] = {0}; + const uint64_t base[2] = {UINT64_C(0x1111222233334444), UINT64_C(0x5555666677778888)}; + const uint64_t half[1] = {UINT64_C(0xaaaabbbbccccdddd)}; + uint64_t got[4]; + vmovhalfsemantics(out, base, half); + memcpy(got, out, 32); + if (got[0] != base[0] || got[1] != half[0]) return 10; + if (got[2] != half[0] || got[3] != base[1]) return 11; + if (out[32] != 1) return 12; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "vex_move_half_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_vmov_integer.go b/amd64_lower_vmov_integer.go new file mode 100644 index 00000000..3fbf31ca --- /dev/null +++ b/amd64_lower_vmov_integer.go @@ -0,0 +1,108 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerVectorScalarIntegerMove implements the complete Go 1.27 _yvmovd and +// _yvmovq tables. Both instructions transfer between X registers and scalar +// GP/memory operands; VMOVQ additionally permits X-to-X transfers. +func (c *amd64Ctx) lowerVectorScalarIntegerMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + bits := 0 + switch rawOp { + case "VMOVD": + bits = 32 + case "VMOVQ": + bits = 64 + default: + if strings.HasPrefix(rawOp, "VMOVD.") || strings.HasPrefix(rawOp, "VMOVQ.") { + return true, false, fmt.Errorf("%s %s suffix is absent from Go 1.27's scalar integer move tables: %q", c.goarch, strings.SplitN(rawOp, ".", 2)[0], ins.Raw) + } + return false, false, nil + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("%s %s expects exactly two operands: %q", c.goarch, rawOp, ins.Raw) + } + + src, dst := ins.Args[0], ins.Args[1] + srcX := isAMD64GoXRegister(src) + dstX := isAMD64GoXRegister(dst) + if srcX && dstX { + if rawOp != "VMOVQ" { + return true, false, fmt.Errorf("%s VMOVD has no X-to-X form in Go 1.27's _yvmovd table: %q", c.goarch, ins.Raw) + } + low, err := c.loadXLowInteger(src.Reg, 64) + if err != nil { + return true, false, err + } + return true, false, c.storeVMOVIntegerX(dst.Reg, 64, low) + } + if srcX { + transferBits := bits + if c.goarch == "386" && dst.Kind == OpReg { + transferBits = 32 + } + if !c.isGoVMOVScalarOperand(dst) { + return true, false, fmt.Errorf("%s %s destination must be a GP register, memory, or X register: %q", c.goarch, rawOp, ins.Raw) + } + low, err := c.loadXLowInteger(src.Reg, transferBits) + if err != nil { + return true, false, err + } + return true, false, c.storeVMOVIntegerScalar(dst, transferBits, low) + } + if dstX { + transferBits := bits + if c.goarch == "386" && src.Kind == OpReg { + transferBits = 32 + } + if !c.isGoVMOVScalarOperand(src) { + return true, false, fmt.Errorf("%s %s source must be a GP register, memory, or X register: %q", c.goarch, rawOp, ins.Raw) + } + low, err := c.evalIntSized(src, amd64IntegerTypeForBits(transferBits)) + if err != nil { + return true, false, err + } + return true, false, c.storeVMOVIntegerX(dst.Reg, transferBits, low) + } + return true, false, fmt.Errorf("%s %s requires one X-register operand: %q", c.goarch, rawOp, ins.Raw) +} + +func isAMD64GoXRegister(operand Operand) bool { + if operand.Kind != OpReg { + return false + } + _, ok := amd64ParseXReg(operand.Reg) + return ok +} + +func (c *amd64Ctx) isGoVMOVScalarOperand(operand Operand) bool { + if isAMD64MemoryOperand(operand) { + return true + } + return operand.Kind == OpReg && isX86YrlRegisterForArch(operand.Reg, c.goarch) +} + +func (c *amd64Ctx) storeVMOVIntegerX(dst Reg, bits int, low string) error { + lanes := 128 / bits + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> zeroinitializer, i%d %s, i32 0\n", inserted, lanes, bits, bits, low) + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", bytes, lanes, bits, inserted) + return c.storeX(dst, "%"+bytes) +} + +func (c *amd64Ctx) storeVMOVIntegerScalar(dst Operand, bits int, value string) error { + typ := amd64IntegerTypeForBits(bits) + if dst.Kind != OpReg { + return c.storeScalarIntegerOperand(dst, typ, value) + } + if bits == 64 { + return c.storeRegUnchecked(dst.Reg, value) + } + widened := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", widened, value) + return c.storeRegUnchecked(dst.Reg, "%"+widened) +} diff --git a/amd64_lower_vmov_integer_test.go b/amd64_lower_vmov_integer_test.go new file mode 100644 index 00000000..9c0d4167 --- /dev/null +++ b/amd64_lower_vmov_integer_test.go @@ -0,0 +1,114 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateX86VMOVDVMOVQCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27's _yvmovd and _yvmovq tables allow scalar GP/memory transfers + // in both directions. VMOVQ additionally allows X-to-X low-qword moves. + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := `TEXT vmovintegerscalarforms(SB),NOSPLIT,$0-0 + VMOVD AX, X0 + VMOVD X0, AX + VMOVD SP, X1 + VMOVD X1, SP + VMOVD 8(AX), X20 + VMOVD X20, 12(AX) + VMOVQ AX, X2 + VMOVQ X2, AX + VMOVQ SP, X3 + VMOVQ X3, SP + VMOVQ 16(AX), X30 + VMOVQ X30, 24(AX) + VMOVQ X0, X1 + VMOVQ X20, X31 +` + if target.goarch == "amd64" { + source += "\tVMOVD R8, X31\n\tVMOVD X31, R9\n\tVMOVQ R10, X30\n\tVMOVQ X30, R11\n" + } + source += "\tRET\n" + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "vmovintegerscalarforms": {Name: "vmovintegerscalarforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "vmov-integer-scalar-"+target.name+".ll", "vmov-integer-scalar-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86VMOVDVMOVQRejectsFormsOutsideGoAssemblerTables(t *testing.T) { + for _, instruction := range []string{ + "VMOVD X0, X1", + "VMOVD Y0, AX", + "VMOVD AX, Y0", + "VMOVD Z0, AX", + "VMOVD AX, Z0", + "VMOVD AX, BX", + "VMOVD (AX), 8(BX)", + "VMOVD.Z AX, X0", + "VMOVD AX, K1, X0", + "VMOVQ Y0, AX", + "VMOVQ AX, Y0", + "VMOVQ Z0, X0", + "VMOVQ AX, BX", + "VMOVQ (AX), 8(BX)", + "VMOVQ.Z X0, X1", + "VMOVQ X0, K1, X1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + assertX86VMOVIntegerRejected(t, "amd64", "x86_64-unknown-linux-gnu", instruction) + }) + } + for _, instruction := range []string{ + "VMOVD R8, X0", + "VMOVD X0, R8", + "VMOVQ R8, X0", + "VMOVQ X0, R8", + } { + t.Run("386_"+strings.NewReplacer(" ", "_").Replace(instruction), func(t *testing.T) { + assertX86VMOVIntegerRejected(t, "386", "i386-unknown-linux-gnu", instruction) + }) + } +} + +func assertX86VMOVIntegerRejected(t *testing.T, goarch, triple, instruction string) { + t.Helper() + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: goarch, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VMOVD/VMOVQ forms for %s", instruction, goarch) + } +} diff --git a/amd64_lower_vmov_scalar.go b/amd64_lower_vmov_scalar.go new file mode 100644 index 00000000..b60a3a42 --- /dev/null +++ b/amd64_lower_vmov_scalar.go @@ -0,0 +1,211 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerVectorScalarMove implements all Go 1.27 _yvmovsd forms shared by +// VMOVSD and VMOVSS: scalar loads/stores, three-register upper merges, and +// their EVEX masked variants. +func (c *amd64Ctx) lowerVectorScalarMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + suffix := "" + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp, suffix = rawOp[:dot], rawOp[dot+1:] + } + elemBits := 0 + switch baseOp { + case "VMOVSD": + elemBits = 64 + case "VMOVSS": + elemBits = 32 + default: + return false, false, nil + } + if c.goarch != "amd64" { + return true, false, fmt.Errorf("%s %s is absent from Go 1.27's 386 assembler forms: %q", c.goarch, baseOp, ins.Raw) + } + if suffix != "" && suffix != "Z" { + return true, false, fmt.Errorf("amd64 %s suffix is absent from Go 1.27's _yvmovsd table: %q", baseOp, ins.Raw) + } + zeroing := suffix == "Z" + switch len(ins.Args) { + case 2: + if zeroing { + return true, false, fmt.Errorf("amd64 %s zeroing requires a K1-K7 mask and register destination: %q", baseOp, ins.Raw) + } + return c.lowerVectorScalarMoveTwoOperand(baseOp, elemBits, ins) + case 3: + if amd64ScalarXOperand(ins.Args[0]) && amd64ScalarXOperand(ins.Args[1]) && amd64ScalarXOperand(ins.Args[2]) { + if zeroing { + return true, false, fmt.Errorf("amd64 %s zeroing requires a K1-K7 mask: %q", baseOp, ins.Raw) + } + return c.lowerVectorScalarMoveRegisterMerge(elemBits, ins.Args[0], ins.Args[1], Operand{}, ins.Args[2], false) + } + return c.lowerVectorScalarMoveMaskedMemory(baseOp, elemBits, zeroing, ins) + case 4: + if !amd64ScalarXOperand(ins.Args[0]) || !amd64ScalarXOperand(ins.Args[1]) || !amd64ScalarXOperand(ins.Args[3]) { + return true, false, fmt.Errorf("amd64 %s four-operand form expects X, X, K1-K7, X: %q", baseOp, ins.Raw) + } + if !amd64NonzeroKOperand(ins.Args[2]) { + return true, false, fmt.Errorf("amd64 %s masked form expects K1-K7: %q", baseOp, ins.Raw) + } + return c.lowerVectorScalarMoveRegisterMerge(elemBits, ins.Args[0], ins.Args[1], ins.Args[2], ins.Args[3], zeroing) + default: + return true, false, fmt.Errorf("amd64 %s operand list is absent from Go 1.27's _yvmovsd table: %q", baseOp, ins.Raw) + } +} + +func (c *amd64Ctx) lowerVectorScalarMoveTwoOperand(baseOp string, elemBits int, ins Instr) (bool, bool, error) { + src, dst := ins.Args[0], ins.Args[1] + if amd64ScalarXOperand(src) && isAMD64MemoryOperand(dst) { + value, err := c.loadXLowInteger(src.Reg, elemBits) + if err != nil { + return true, false, err + } + return true, false, c.storeVectorScalarMemory(dst, elemBits, value, "") + } + if isAMD64MemoryOperand(src) && amd64ScalarXOperand(dst) { + value, err := c.evalIntSized(src, amd64IntegerTypeForBits(elemBits)) + if err != nil { + return true, false, err + } + return true, false, c.storeVectorScalarRegister(dst.Reg, elemBits, value, "zeroinitializer", "", false) + } + return true, false, fmt.Errorf("amd64 %s two-operand form requires X-to-memory or memory-to-X: %q", baseOp, ins.Raw) +} + +func (c *amd64Ctx) lowerVectorScalarMoveMaskedMemory(baseOp string, elemBits int, zeroing bool, ins Instr) (bool, bool, error) { + if !amd64NonzeroKOperand(ins.Args[1]) { + return true, false, fmt.Errorf("amd64 %s three-operand masked memory form expects K1-K7 in the middle: %q", baseOp, ins.Raw) + } + mask, err := c.loadK(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + if amd64ScalarXOperand(ins.Args[0]) && isAMD64MemoryOperand(ins.Args[2]) { + if zeroing { + return true, false, fmt.Errorf("amd64 %s cannot use .Z with a memory destination: %q", baseOp, ins.Raw) + } + value, err := c.loadXLowInteger(ins.Args[0].Reg, elemBits) + if err != nil { + return true, false, err + } + return true, false, c.storeVectorScalarMemory(ins.Args[2], elemBits, value, mask) + } + if isAMD64MemoryOperand(ins.Args[0]) && amd64ScalarXOperand(ins.Args[2]) { + value, err := c.evalIntSized(ins.Args[0], amd64IntegerTypeForBits(elemBits)) + if err != nil { + return true, false, err + } + return true, false, c.storeVectorScalarRegister(ins.Args[2].Reg, elemBits, value, "zeroinitializer", mask, zeroing) + } + return true, false, fmt.Errorf("amd64 %s masked memory form requires X, K, memory or memory, K, X: %q", baseOp, ins.Raw) +} + +func (c *amd64Ctx) lowerVectorScalarMoveRegisterMerge(elemBits int, lowSource, upperSource, maskArg, dst Operand, zeroing bool) (bool, bool, error) { + low, err := c.loadXLowInteger(lowSource.Reg, elemBits) + if err != nil { + return true, false, err + } + upperBytes, err := c.loadX(upperSource.Reg) + if err != nil { + return true, false, err + } + lanes := 128 / elemBits + upper := c.bitcastVectorBytesToIntegerLanes(16, lanes, elemBits, upperBytes) + mask := "" + if maskArg.Kind == OpReg { + mask, err = c.loadK(maskArg.Reg) + if err != nil { + return true, false, err + } + } + return true, false, c.storeVectorScalarRegister(dst.Reg, elemBits, low, upper, mask, zeroing) +} + +func amd64ScalarXOperand(op Operand) bool { + if op.Kind != OpReg { + return false + } + index, ok := amd64ParseXReg(op.Reg) + return ok && index < 32 +} + +func amd64NonzeroKOperand(op Operand) bool { + if op.Kind != OpReg { + return false + } + index, ok := amd64ParseKReg(op.Reg) + return ok && index != 0 +} + +func (c *amd64Ctx) loadXLowInteger(reg Reg, elemBits int) (string, error) { + bytesValue, err := c.loadX(reg) + if err != nil { + return "", err + } + lanes := 128 / elemBits + values := c.bitcastVectorBytesToIntegerLanes(16, lanes, elemBits, bytesValue) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 0\n", low, lanes, elemBits, values) + return "%" + low, nil +} + +func (c *amd64Ctx) storeVectorScalarRegister(dst Reg, elemBits int, low, base, mask string, zeroing bool) error { + lanes := 128 / elemBits + if mask != "" { + fallback := "0" + if !zeroing { + old, err := c.loadXLowInteger(dst, elemBits) + if err != nil { + return err + } + fallback = old + } + maskBit := amd64MaskBitI1(c, mask, 0) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %s, i%d %s\n", selected, maskBit, elemBits, low, elemBits, fallback) + low = "%" + selected + } + updated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %s, i32 0\n", updated, lanes, elemBits, base, elemBits, low) + bytesValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", bytesValue, lanes, elemBits, updated) + return c.storeX(dst, "%"+bytesValue) +} + +func (c *amd64Ctx) storeVectorScalarMemory(dst Operand, elemBits int, value, mask string) error { + if mask != "" { + old, err := c.evalIntSized(dst, amd64IntegerTypeForBits(elemBits)) + if err != nil { + return err + } + maskBit := amd64MaskBitI1(c, mask, 0) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i%d %s, i%d %s\n", selected, maskBit, elemBits, value, elemBits, old) + value = "%" + selected + } + switch dst.Kind { + case OpMem: + ptr, ptrType, err := c.ptrFromMem(dst.Mem) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store i%d %s, %s %s, align 1\n", elemBits, value, ptrType, ptr) + return nil + case OpSym: + ptr, err := c.ptrFromSB(dst.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store i%d %s, ptr %s, align 1\n", elemBits, value, ptr) + return nil + case OpFP: + return c.storeFPResult(dst.FPOffset, amd64IntegerTypeForBits(elemBits), value) + default: + return fmt.Errorf("expected scalar memory destination, got %s", dst.String()) + } +} diff --git a/amd64_lower_vmov_scalar_aggregate_test.go b/amd64_lower_vmov_scalar_aggregate_test.go new file mode 100644 index 00000000..d2881634 --- /dev/null +++ b/amd64_lower_vmov_scalar_aggregate_test.go @@ -0,0 +1,160 @@ +//go:build !llgo + +package plan9asm + +import ( + "errors" + "fmt" + "runtime" + "testing" +) + +func TestTranslateX86WideStoresSpanComplex64Result(t *testing.T) { + for _, tc := range []struct { + name string + instruction string + amd64Only bool + needsZeroXMM bool + }{ + {name: "movsd", instruction: "MOVSD X0, ret+0(FP)", needsZeroXMM: true}, + {name: "movq-xmm", instruction: "MOVQ X0, ret+0(FP)", needsZeroXMM: true}, + {name: "vmovq-xmm", instruction: "VMOVQ X0, ret+0(FP)", needsZeroXMM: true}, + {name: "movq-gp", instruction: "MOVQ AX, ret+0(FP)", amd64Only: true}, + {name: "vmovsd", instruction: "VMOVSD X0, ret+0(FP)", amd64Only: true, needsZeroXMM: true}, + } { + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + if tc.amd64Only && target.goarch != "amd64" { + continue + } + t.Run(tc.name+"/"+target.name, func(t *testing.T) { + functionName := "widestorecomplex64result" + source := fmt.Sprintf("TEXT %s(SB),$0-8\n", functionName) + if tc.needsZeroXMM { + source += "\tPXOR X0, X0\n" + } + source += "\t" + tc.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + options := Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + functionName: { + Name: functionName, + Ret: LLVMType("{ float, float }"), + Frame: FrameLayout{Results: []FrameSlot{ + {Offset: 0, Type: LLVMType("float"), Index: 0, Field: -1, Name: "ret"}, + {Offset: 4, Type: LLVMType("float"), Index: 1, Field: -1, Name: "ret"}, + }}, + }, + }, + } + if tc.name == "movq-gp" { + mod, directErr := translateModuleDirect(file, options) + if directErr == nil { + mod.Dispose() + t.Fatal("direct linear prototype unexpectedly accepted a wide aggregate-result store") + } + if !errors.Is(directErr, errDirectModuleUnsupported) { + t.Fatalf("direct linear prototype error = %v, want fallback request", directErr) + } + } + ll, err := Translate(file, options) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "wide-store-complex64-result.ll", "wide-store-complex64-result.o", ll) + }) + } + } +} + +func TestAMD64VMOVSDStoresComplex64ResultRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT vmovsdcomplex64result(SB),$0-16 + MOVQ input+0(FP), AX + VMOVSD (AX), X0 + VMOVSD X0, ret+8(FP) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "vmovsdcomplex64result": { + Name: "vmovsdcomplex64result", + Args: []LLVMType{Ptr}, + Ret: LLVMType("{ float, float }"), + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1, Name: "input"}}, + Results: []FrameSlot{ + {Offset: 8, Type: LLVMType("float"), Index: 0, Field: -1, Name: "ret"}, + {Offset: 12, Type: LLVMType("float"), Index: 1, Field: -1, Name: "ret"}, + }, + }, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + ll += ` +define void @call_vmovsdcomplex64result(ptr %input, ptr %output) { +entry: + %result = call { float, float } @vmovsdcomplex64result(ptr %input) + %real = extractvalue { float, float } %result, 0 + %imag = extractvalue { float, float } %result, 1 + store float %real, ptr %output, align 4 + %imagptr = getelementptr float, ptr %output, i64 1 + store float %imag, ptr %imagptr, align 4 + ret void +} +` + mainC := ` +extern void call_vmovsdcomplex64result(const float *input, float *output); +int main(void) { + const float input[2] = { 1.25f, -2.5f }; + float got[2] = { 0.0f, 0.0f }; + call_vmovsdcomplex64result(input, got); + if (got[0] != input[0]) return 1; + if (got[1] != input[1]) return 2; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "vmovsd_complex64_result", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_x87.go b/amd64_lower_x87.go index 0ef86ec0..e6cc7ef1 100644 --- a/amd64_lower_x87.go +++ b/amd64_lower_x87.go @@ -1,12 +1,31 @@ package plan9asm -import "fmt" +import ( + "fmt" + "strings" +) func isX87Op(op Op) bool { switch op { - case "FMOVD", "FMOVDP", "FMOVV", "FMOVVP", "FXCHD", "FADDDP", - "FDIVD", "FMULD", "FMULDP", "FSTCW", "FLDCW", "FRNDINT", - "FABS", "FUCOMI", "FTST", "FSTSW", "FLD1", "FSQRT": + case "FMOVB", "FMOVBP", "FMOVD", "FMOVDP", "FMOVF", "FMOVFP", + "FMOVL", "FMOVLP", "FMOVV", "FMOVVP", "FMOVW", "FMOVWP", + "FMOVX", "FMOVXP", "FBLD", "FBSTP", "FXCHD", + "FADDW", "FADDL", "FADDF", "FADDD", "FADDDP", + "FMULW", "FMULL", "FMULF", "FMULD", "FMULDP", + "FSUBW", "FSUBL", "FSUBF", "FSUBD", "FSUBDP", + "FSUBRW", "FSUBRL", "FSUBRF", "FSUBRD", "FSUBRDP", + "FDIVW", "FDIVL", "FDIVF", "FDIVD", "FDIVDP", + "FDIVRW", "FDIVRL", "FDIVRF", "FDIVRD", "FDIVRDP", + "FCOMD", "FCOMDP", "FCOMDPP", "FCOMF", "FCOMFP", "FCOMI", "FCOMIP", + "FCOML", "FCOMLP", "FCOMW", "FCOMWP", + "FUCOM", "FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP", + "FCMOVCC", "FCMOVCS", "FCMOVEQ", "FCMOVHI", "FCMOVLS", + "FCMOVB", "FCMOVBE", "FCMOVNB", "FCMOVNBE", "FCMOVE", "FCMOVNE", "FCMOVNU", "FCMOVU", "FCMOVUN", + "FSTCW", "FLDCW", "FLDENV", "FRSTOR", "FSAVE", "FSTENV", "FRNDINT", + "F2XM1", "FABS", "FCHS", "FCLEX", "FCOS", "FDECSTP", "FINCSTP", "FINIT", + "FTST", "FSTSW", "FLD1", "FLDL2E", "FLDL2T", "FLDLG2", "FLDLN2", + "FLDPI", "FLDZ", "FNOP", "FPATAN", "FPREM", "FPREM1", "FPTAN", "FSCALE", + "FSIN", "FSINCOS", "FSQRT", "FXAM", "FXTRACT", "FYL2X", "FYL2XP1": return true default: return false @@ -17,15 +36,71 @@ func (c *amd64Ctx) lowerX87(op Op, ins Instr) (ok bool, terminated bool, err err if !isX87Op(op) { return false, false, nil } - if c.goarch != "386" { - return true, false, fmt.Errorf("amd64: x87 instruction %s requires GOARCH=386", op) - } - switch op { + case "FBLD": + if len(ins.Args) != 1 || !isX87MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("386 FBLD expects memory source: %q", ins.Raw) + } + value, err := c.loadX87PackedBCD(ins.Args[0]) + if err != nil { + return true, false, err + } + return true, false, c.pushX87(value) + + case "FBSTP": + if len(ins.Args) != 1 || !isX87MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("386 FBSTP expects memory destination: %q", ins.Raw) + } + if err := c.storeX87PackedBCD(ins.Args[0], c.loadX87(0)); err != nil { + return true, false, err + } + c.popX87() + return true, false, nil + + case "FMOVB", "FMOVX": + if len(ins.Args) != 2 || !isX87MemoryOperand(ins.Args[0]) || !isX87F0(ins.Args[1]) { + return true, false, fmt.Errorf("386 %s expects memory source and F0 destination: %q", op, ins.Raw) + } + var value string + var err error + if op == "FMOVB" { + value, err = c.loadX87PackedBCD(ins.Args[0]) + } else { + value, err = c.loadX87Extended(ins.Args[0]) + } + if err != nil { + return true, false, err + } + return true, false, c.pushX87(value) + + case "FMOVBP", "FMOVXP": + if len(ins.Args) != 2 || !isX87F0(ins.Args[0]) || !isX87MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("386 %s expects F0 source and memory destination: %q", op, ins.Raw) + } + var err error + if op == "FMOVBP" { + err = c.storeX87PackedBCD(ins.Args[1], c.loadX87(0)) + } else { + err = c.storeX87Extended(ins.Args[1], c.loadX87(0)) + } + if err != nil { + return true, false, err + } + c.popX87() + return true, false, nil + case "FMOVD": if len(ins.Args) != 2 { return true, false, fmt.Errorf("386 FMOVD expects src, dst: %q", ins.Raw) } + srcReg, srcIsReg := x87OperandReg(ins.Args[0]) + dstReg, dstIsReg := x87OperandReg(ins.Args[1]) + valid := (isX87MemoryOperand(ins.Args[0]) || ins.Args[0].Kind == OpImm) && dstIsReg && dstReg == 0 || + srcIsReg && srcReg == 0 && (isX87MemoryOperand(ins.Args[1]) || dstIsReg) || + srcIsReg && dstIsReg && dstReg == 0 + if !valid { + return true, false, fmt.Errorf("386 FMOVD expects memory,F0, Freg,F0, F0,memory, or F0,Freg: %q", ins.Raw) + } v, err := c.evalX87F64(ins.Args[0]) if err != nil { return true, false, err @@ -36,8 +111,8 @@ func (c *amd64Ctx) lowerX87(op Op, ins Instr) (ok bool, terminated bool, err err return true, false, c.storeX87F64(ins.Args[1], v) case "FMOVDP": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("386 FMOVDP expects src, dst: %q", ins.Raw) + if len(ins.Args) != 2 || !isX87F0(ins.Args[0]) || !(isX87MemoryOperand(ins.Args[1]) || isX87RegisterOperand(ins.Args[1])) { + return true, false, fmt.Errorf("386 FMOVDP expects F0 source and memory or x87-register destination: %q", ins.Raw) } v, err := c.evalX87F64(ins.Args[0]) if err != nil { @@ -49,12 +124,36 @@ func (c *amd64Ctx) lowerX87(op Op, ins Instr) (ok bool, terminated bool, err err c.popX87() return true, false, nil - case "FMOVV": + case "FMOVF", "FMOVL", "FMOVW": if len(ins.Args) != 2 { - return true, false, fmt.Errorf("386 FMOVV expects src, dst: %q", ins.Raw) + return true, false, fmt.Errorf("386 %s expects src, dst: %q", op, ins.Raw) + } + if isX87MemoryOperand(ins.Args[0]) && isX87F0(ins.Args[1]) { + value, err := c.loadX87MoveValue(op, ins.Args[0]) + if err != nil { + return true, false, err + } + return true, false, c.pushX87(value) + } + if isX87F0(ins.Args[0]) && isX87MemoryOperand(ins.Args[1]) { + return true, false, c.storeX87MoveValue(op, ins.Args[1], c.loadX87(0)) + } + return true, false, fmt.Errorf("386 %s expects memory source and F0 destination, or F0 source and memory destination: %q", op, ins.Raw) + + case "FMOVFP", "FMOVLP", "FMOVWP": + if len(ins.Args) != 2 || !isX87F0(ins.Args[0]) || !isX87MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("386 %s expects F0 source and memory destination: %q", op, ins.Raw) } - if idx, ok := x87OperandReg(ins.Args[1]); !ok || idx != 0 { - return true, false, fmt.Errorf("386 FMOVV expects F0 destination: %q", ins.Raw) + baseOp := Op(strings.TrimSuffix(string(op), "P")) + if err := c.storeX87MoveValue(baseOp, ins.Args[1], c.loadX87(0)); err != nil { + return true, false, err + } + c.popX87() + return true, false, nil + + case "FMOVV": + if len(ins.Args) != 2 || !isX87MemoryOperand(ins.Args[0]) || !isX87F0(ins.Args[1]) { + return true, false, fmt.Errorf("386 FMOVV expects memory source and F0 destination: %q", ins.Raw) } v, err := c.evalIntSized(ins.Args[0], I64) if err != nil { @@ -65,11 +164,8 @@ func (c *amd64Ctx) lowerX87(op Op, ins Instr) (ok bool, terminated bool, err err return true, false, c.pushX87("%" + f) case "FMOVVP": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("386 FMOVVP expects src, dst: %q", ins.Raw) - } - if index, ok := x87OperandReg(ins.Args[0]); !ok || index != 0 { - return true, false, fmt.Errorf("386 FMOVVP expects F0 source: %q", ins.Raw) + if len(ins.Args) != 2 || !isX87F0(ins.Args[0]) || !isX87MemoryOperand(ins.Args[1]) { + return true, false, fmt.Errorf("386 FMOVVP expects F0 source and memory destination: %q", ins.Raw) } var iv string if c.useHardwareX87() { @@ -101,53 +197,26 @@ func (c *amd64Ctx) lowerX87(op Op, ins Instr) (ok bool, terminated bool, err err c.storeX87(bv, av) return true, false, nil - case "FDIVD", "FMULD": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("386 %s expects src, dst: %q", op, ins.Raw) - } - src, err := c.evalX87F64(ins.Args[0]) - if err != nil { - return true, false, err - } - dst, err := c.evalX87F64(ins.Args[1]) - if err != nil { - return true, false, err - } - out := c.newTmp() - if op == "FDIVD" { - fmt.Fprintf(c.b, " %%%s = fdiv double %s, %s\n", out, dst, src) - } else { - fmt.Fprintf(c.b, " %%%s = fmul double %s, %s\n", out, dst, src) - } - return true, false, c.storeX87F64(ins.Args[1], "%"+out) + case "FADDW", "FADDL", "FADDF", "FADDD", "FADDDP", + "FMULW", "FMULL", "FMULF", "FMULD", "FMULDP", + "FSUBW", "FSUBL", "FSUBF", "FSUBD", "FSUBDP", + "FSUBRW", "FSUBRL", "FSUBRF", "FSUBRD", "FSUBRDP", + "FDIVW", "FDIVL", "FDIVF", "FDIVD", "FDIVDP", + "FDIVRW", "FDIVRL", "FDIVRF", "FDIVRD", "FDIVRDP": + return true, false, c.lowerX87Arithmetic(op, ins) - case "FADDDP", "FMULDP": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("386 %s expects src, dst: %q", op, ins.Raw) - } - src, err := c.evalX87F64(ins.Args[0]) - if err != nil { - return true, false, err - } - dst, err := c.evalX87F64(ins.Args[1]) - if err != nil { - return true, false, err - } - out := c.newTmp() - if op == "FADDDP" { - fmt.Fprintf(c.b, " %%%s = fadd double %s, %s\n", out, dst, src) - } else { - fmt.Fprintf(c.b, " %%%s = fmul double %s, %s\n", out, dst, src) - } - if err := c.storeX87F64(ins.Args[1], "%"+out); err != nil { - return true, false, err - } - c.popX87() - return true, false, nil + case "FCOMD", "FCOMDP", "FCOMDPP", "FCOMF", "FCOMFP", "FCOMI", "FCOMIP", + "FCOML", "FCOMLP", "FCOMW", "FCOMWP", + "FUCOM", "FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP": + return true, false, c.lowerX87Compare(op, ins) + + case "FCMOVCC", "FCMOVCS", "FCMOVEQ", "FCMOVHI", "FCMOVLS", + "FCMOVB", "FCMOVBE", "FCMOVNB", "FCMOVNBE", "FCMOVE", "FCMOVNE", "FCMOVNU", "FCMOVU", "FCMOVUN": + return true, false, c.lowerX87ConditionalMove(op, ins) case "FSTCW": - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("386 FSTCW expects dst: %q", ins.Raw) + if len(ins.Args) != 1 || !isX87MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("386 FSTCW expects memory destination: %q", ins.Raw) } if c.useHardwareX87() { c.storeHardwareX87ControlWord() @@ -157,8 +226,8 @@ func (c *amd64Ctx) lowerX87(op Op, ins Instr) (ok bool, terminated bool, err err return true, false, c.storeX87I16(ins.Args[0], "%"+cw) case "FLDCW": - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("386 FLDCW expects src: %q", ins.Raw) + if len(ins.Args) != 1 || !isX87MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("386 FLDCW expects memory source: %q", ins.Raw) } cw, err := c.evalIntSized(ins.Args[0], I16) if err != nil { @@ -170,6 +239,28 @@ func (c *amd64Ctx) lowerX87(op Op, ins Instr) (ok bool, terminated bool, err err } return true, false, nil + case "FLDENV", "FRSTOR": + if len(ins.Args) != 1 || !isX87MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("386 %s expects memory source: %q", op, ins.Raw) + } + return true, false, c.loadX87Environment(ins.Args[0]) + + case "FSAVE", "FSTENV": + if len(ins.Args) != 1 || !isX87MemoryOperand(ins.Args[0]) { + return true, false, fmt.Errorf("386 %s expects memory destination: %q", op, ins.Raw) + } + if err := c.storeX87Environment(ins.Args[0]); err != nil { + return true, false, err + } + if op == "FSAVE" { + for i := range c.x87Slot { + c.storeX87(i, "0.000000e+00") + } + fmt.Fprintf(c.b, " store i16 895, ptr %s\n", c.x87ControlSlot) + fmt.Fprintf(c.b, " store i16 0, ptr %s\n", c.x87StatusSlot) + } + return true, false, nil + case "FRNDINT": if len(ins.Args) != 0 { return true, false, fmt.Errorf("386 FRNDINT takes no operands: %q", ins.Raw) @@ -180,6 +271,18 @@ func (c *amd64Ctx) lowerX87(op Op, ins Instr) (ok bool, terminated bool, err err } return true, false, c.storeX87F64(Operand{Kind: OpReg, Reg: Reg("F0")}, c.roundX87Software(c.loadX87(0))) + case "F2XM1": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 F2XM1 takes no operands: %q", ins.Raw) + } + value := c.loadX87(0) + power := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call double @llvm.exp2.f64(double %s)\n", power, value) + fmt.Fprintf(c.b, " %%%s = fsub double %%%s, 1.000000e+00\n", result, power) + c.storeX87(0, "%"+result) + return true, false, nil + case "FABS", "FSQRT": if len(ins.Args) != 0 { return true, false, fmt.Errorf("386 %s takes no operands: %q", op, ins.Raw) @@ -194,27 +297,171 @@ func (c *amd64Ctx) lowerX87(op Op, ins Instr) (ok bool, terminated bool, err err c.storeX87(0, "%"+out) return true, false, nil - case "FUCOMI": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("386 FUCOMI expects lhs, rhs: %q", ins.Raw) + case "FCHS": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 FCHS takes no operands: %q", ins.Raw) } - lhs, err := c.evalX87F64(ins.Args[0]) - if err != nil { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg double %s\n", result, c.loadX87(0)) + c.storeX87(0, "%"+result) + return true, false, nil + + case "FCLEX": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 FCLEX takes no operands: %q", ins.Raw) + } + status := c.newTmp() + conditionCodes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i16, ptr %s\n", status, c.x87StatusSlot) + fmt.Fprintf(c.b, " %%%s = and i16 %%%s, 18176\n", conditionCodes, status) // C3,C2,C1,C0 + fmt.Fprintf(c.b, " store i16 %%%s, ptr %s\n", conditionCodes, c.x87StatusSlot) + return true, false, nil + + case "FCOS", "FSIN": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 %s takes no operands: %q", op, ins.Raw) + } + intrinsic := "llvm.cos.f64" + if op == "FSIN" { + intrinsic = "llvm.sin.f64" + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call double @%s(double %s)\n", result, intrinsic, c.loadX87(0)) + c.storeX87(0, "%"+result) + c.clearX87C2() + return true, false, nil + + case "FDECSTP", "FINCSTP": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 %s takes no operands: %q", op, ins.Raw) + } + c.rotateX87Stack(op == "FINCSTP") + return true, false, nil + + case "FINIT": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 FINIT takes no operands: %q", ins.Raw) + } + for i := range c.x87Slot { + c.storeX87(i, "0.000000e+00") + } + fmt.Fprintf(c.b, " store i16 895, ptr %s\n", c.x87ControlSlot) + fmt.Fprintf(c.b, " store i16 0, ptr %s\n", c.x87StatusSlot) + return true, false, nil + + case "FNOP": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 FNOP takes no operands: %q", ins.Raw) + } + return true, false, nil + + case "FPATAN": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 FPATAN takes no operands: %q", ins.Raw) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call double @atan2(double %s, double %s)\n", result, c.loadX87(1), c.loadX87(0)) + c.storeX87(1, "%"+result) + c.popX87() + return true, false, nil + + case "FPREM", "FPREM1": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 %s takes no operands: %q", op, ins.Raw) + } + function := "fmod" + if op == "FPREM1" { + function = "remainder" + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call double @%s(double %s, double %s)\n", result, function, c.loadX87(0), c.loadX87(1)) + c.storeX87(0, "%"+result) + c.clearX87C2() + return true, false, nil + + case "FPTAN": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 FPTAN takes no operands: %q", ins.Raw) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call double @tan(double %s)\n", result, c.loadX87(0)) + c.storeX87(0, "%"+result) + if err := c.pushX87("1.000000e+00"); err != nil { return true, false, err } - rhs, err := c.evalX87F64(ins.Args[1]) - if err != nil { + c.clearX87C2() + return true, false, nil + + case "FSCALE": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 FSCALE takes no operands: %q", ins.Raw) + } + exponent := c.newTmp() + scale := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call double @llvm.trunc.f64(double %s)\n", exponent, c.loadX87(1)) + fmt.Fprintf(c.b, " %%%s = call double @llvm.exp2.f64(double %%%s)\n", scale, exponent) + fmt.Fprintf(c.b, " %%%s = fmul double %s, %%%s\n", result, c.loadX87(0), scale) + c.storeX87(0, "%"+result) + return true, false, nil + + case "FSINCOS": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 FSINCOS takes no operands: %q", ins.Raw) + } + value := c.loadX87(0) + sine := c.newTmp() + cosine := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call double @llvm.sin.f64(double %s)\n", sine, value) + fmt.Fprintf(c.b, " %%%s = call double @llvm.cos.f64(double %s)\n", cosine, value) + c.storeX87(0, "%"+sine) + if err := c.pushX87("%" + cosine); err != nil { return true, false, err } - z := c.newTmp() - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fcmp ueq double %s, %s\n", z, lhs, rhs) - fmt.Fprintf(c.b, " %%%s = fcmp ult double %s, %s\n", cf, lhs, rhs) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", z, c.flagsZSlot) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCFSlot) - // FUCOMI clears both SF and OF. flagsSltSlot models SF xor OF for - // signed conditions, so those conditions must observe false here. - fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsSltSlot) + c.clearX87C2() + return true, false, nil + + case "FXAM": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 FXAM takes no operands: %q", ins.Raw) + } + c.classifyX87F0() + return true, false, nil + + case "FXTRACT": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 FXTRACT takes no operands: %q", ins.Raw) + } + value := c.loadX87(0) + abs := c.newTmp() + log := c.newTmp() + exponent := c.newTmp() + scale := c.newTmp() + significand := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call double @llvm.fabs.f64(double %s)\n", abs, value) + fmt.Fprintf(c.b, " %%%s = call double @llvm.log2.f64(double %%%s)\n", log, abs) + fmt.Fprintf(c.b, " %%%s = call double @llvm.floor.f64(double %%%s)\n", exponent, log) + fmt.Fprintf(c.b, " %%%s = call double @llvm.exp2.f64(double %%%s)\n", scale, exponent) + fmt.Fprintf(c.b, " %%%s = fdiv double %s, %%%s\n", significand, value, scale) + c.storeX87(0, "%"+significand) + return true, false, c.pushX87("%" + exponent) + + case "FYL2X", "FYL2XP1": + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("386 %s takes no operands: %q", op, ins.Raw) + } + x := c.loadX87(0) + if op == "FYL2XP1" { + incremented := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fadd double %s, 1.000000e+00\n", incremented, x) + x = "%" + incremented + } + log := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call double @llvm.log2.f64(double %s)\n", log, x) + fmt.Fprintf(c.b, " %%%s = fmul double %s, %%%s\n", result, c.loadX87(1), log) + c.storeX87(1, "%"+result) + c.popX87() return true, false, nil case "FTST": @@ -246,22 +493,251 @@ func (c *amd64Ctx) lowerX87(op Op, ins Instr) (ok bool, terminated bool, err err return true, false, nil case "FSTSW": - if len(ins.Args) != 1 { - return true, false, fmt.Errorf("386 FSTSW expects dst: %q", ins.Raw) + if len(ins.Args) != 1 || !(isX87MemoryOperand(ins.Args[0]) || ins.Args[0].Kind == OpReg && ins.Args[0].Reg == AX) { + return true, false, fmt.Errorf("386 FSTSW expects memory destination or AX: %q", ins.Raw) } status := c.newTmp() fmt.Fprintf(c.b, " %%%s = load i16, ptr %s\n", status, c.x87StatusSlot) return true, false, c.storeX87I16(ins.Args[0], "%"+status) - case "FLD1": + case "FLD1", "FLDL2E", "FLDL2T", "FLDLG2", "FLDLN2", "FLDPI", "FLDZ": if len(ins.Args) != 0 { - return true, false, fmt.Errorf("386 FLD1 takes no operands: %q", ins.Raw) + return true, false, fmt.Errorf("386 %s takes no operands: %q", op, ins.Raw) + } + constant := map[Op]string{ + "FLD1": "1.0000000000000000e+00", + "FLDL2E": "1.4426950408889634e+00", + "FLDL2T": "3.3219280948873623e+00", + "FLDLG2": "3.0102999566398120e-01", + "FLDLN2": "6.9314718055994531e-01", + "FLDPI": "3.1415926535897931e+00", + "FLDZ": "0.0000000000000000e+00", } - return true, false, c.pushX87("1.000000e+00") + return true, false, c.pushX87(constant[op]) } return false, false, nil } +func (c *amd64Ctx) lowerX87Arithmetic(op Op, ins Instr) error { + if len(ins.Args) != 2 { + return fmt.Errorf("386 %s expects src, dst: %q", op, ins.Raw) + } + name := string(op) + pop := strings.HasSuffix(name, "DP") + width := name[len(name)-1:] + base := strings.TrimSuffix(name, width) + if pop { + width = "D" + base = strings.TrimSuffix(name, "DP") + } + + if pop { + if !isX87F0(ins.Args[0]) || !isX87RegisterOperand(ins.Args[1]) { + return fmt.Errorf("386 %s expects F0 source and x87-register destination: %q", op, ins.Raw) + } + } else if width == "D" { + srcIndex, srcReg := x87OperandReg(ins.Args[0]) + dstIndex, dstReg := x87OperandReg(ins.Args[1]) + loadToF0 := (isX87MemoryOperand(ins.Args[0]) || ins.Args[0].Kind == OpImm) && dstReg && dstIndex == 0 + regToF0 := srcReg && dstReg && dstIndex == 0 + f0ToReg := srcReg && srcIndex == 0 && dstReg + if !loadToF0 && !regToF0 && !f0ToReg { + return fmt.Errorf("386 %s expects memory,F0, Freg,F0, or F0,Freg: %q", op, ins.Raw) + } + } else if !isX87MemoryOperand(ins.Args[0]) || !isX87F0(ins.Args[1]) { + return fmt.Errorf("386 %s expects memory source and F0 destination: %q", op, ins.Raw) + } + + var src string + var err error + switch width { + case "W", "L": + typ := I16 + if width == "L" { + typ = I32 + } + integer, evalErr := c.evalIntSized(ins.Args[0], typ) + if evalErr != nil { + return evalErr + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sitofp %s %s to double\n", converted, typ, integer) + src = "%" + converted + case "F": + value, evalErr := c.evalF32(ins.Args[0]) + if evalErr != nil { + return evalErr + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fpext float %s to double\n", converted, value) + src = "%" + converted + case "D": + src, err = c.evalX87F64(ins.Args[0]) + if err != nil { + return err + } + default: + return fmt.Errorf("386 %s has unknown x87 arithmetic width", op) + } + dst, err := c.evalX87F64(ins.Args[1]) + if err != nil { + return err + } + lhs, rhs := dst, src + if strings.HasPrefix(base, "FSUBR") || strings.HasPrefix(base, "FDIVR") { + lhs, rhs = src, dst + } + operation := "" + switch { + case strings.HasPrefix(base, "FADD"): + operation = "fadd" + case strings.HasPrefix(base, "FMUL"): + operation = "fmul" + case strings.HasPrefix(base, "FSUB"): + operation = "fsub" + case strings.HasPrefix(base, "FDIV"): + operation = "fdiv" + } + if operation == "" { + return fmt.Errorf("386 %s has unknown x87 arithmetic operation", op) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s double %s, %s\n", result, operation, lhs, rhs) + if err := c.storeX87F64(ins.Args[1], "%"+result); err != nil { + return err + } + if pop { + c.popX87() + } + return nil +} + +func (c *amd64Ctx) lowerX87Compare(op Op, ins Instr) error { + if len(ins.Args) != 2 { + return fmt.Errorf("386 %s expects lhs, rhs: %q", op, ins.Raw) + } + name := string(op) + directFlags := name == "FCOMI" || name == "FCOMIP" || name == "FUCOMI" || name == "FUCOMIP" + popCount := 0 + switch name { + case "FCOMDP", "FCOMFP", "FCOMIP", "FCOMLP", "FCOMWP", "FUCOMIP", "FUCOMP": + popCount = 1 + case "FCOMDPP", "FUCOMPP": + popCount = 2 + } + + var lhsOperand, rhsOperand Operand + width := "D" + switch { + case name == "FCOMI" || name == "FCOMIP": + if !isX87RegisterOperand(ins.Args[0]) || !isX87F0(ins.Args[1]) { + return fmt.Errorf("386 %s expects x87-register source and F0 destination: %q", op, ins.Raw) + } + lhsOperand, rhsOperand = ins.Args[1], ins.Args[0] + case strings.HasPrefix(name, "FUCOM") || name == "FCOMDPP": + if !isX87F0(ins.Args[0]) || !isX87RegisterOperand(ins.Args[1]) { + return fmt.Errorf("386 %s expects F0 source and x87-register destination: %q", op, ins.Raw) + } + lhsOperand, rhsOperand = ins.Args[0], ins.Args[1] + case name == "FCOMD" || name == "FCOMDP": + srcIndex, srcReg := x87OperandReg(ins.Args[0]) + dstIndex, dstReg := x87OperandReg(ins.Args[1]) + loadToF0 := (isX87MemoryOperand(ins.Args[0]) || ins.Args[0].Kind == OpImm) && dstReg && dstIndex == 0 + regToF0 := srcReg && dstReg && dstIndex == 0 + f0ToReg := srcReg && srcIndex == 0 && dstReg + if !loadToF0 && !regToF0 && !f0ToReg { + return fmt.Errorf("386 %s expects memory,F0, Freg,F0, or F0,Freg: %q", op, ins.Raw) + } + lhsOperand, rhsOperand = ins.Args[1], ins.Args[0] + default: + widthIndex := len("FCOM") + if len(name) <= widthIndex { + return fmt.Errorf("386 %s has unknown x87 compare form", op) + } + width = name[widthIndex : widthIndex+1] + if !isX87MemoryOperand(ins.Args[0]) || !isX87F0(ins.Args[1]) { + return fmt.Errorf("386 %s expects memory source and F0 destination: %q", op, ins.Raw) + } + lhsOperand, rhsOperand = ins.Args[1], ins.Args[0] + } + + lhs, err := c.evalX87F64(lhsOperand) + if err != nil { + return err + } + var rhs string + switch width { + case "D": + rhs, err = c.evalX87F64(rhsOperand) + case "F": + var narrow string + narrow, err = c.evalF32(rhsOperand) + if err == nil { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fpext float %s to double\n", wide, narrow) + rhs = "%" + wide + } + case "L", "W": + typ := I16 + if width == "L" { + typ = I32 + } + var integer string + integer, err = c.evalIntSized(rhsOperand, typ) + if err == nil { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sitofp %s %s to double\n", wide, typ, integer) + rhs = "%" + wide + } + default: + return fmt.Errorf("386 %s has unknown x87 compare width", op) + } + if err != nil { + return err + } + if directFlags { + c.setX87CompareFlags(lhs, rhs) + } else { + c.setX87CompareStatus(lhs, rhs) + } + for i := 0; i < popCount; i++ { + c.popX87() + } + return nil +} + +func (c *amd64Ctx) x87CompareBits(lhs, rhs string) (equal, less, unordered string) { + equalTmp := c.newTmp() + lessTmp := c.newTmp() + unorderedTmp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp ueq double %s, %s\n", equalTmp, lhs, rhs) + fmt.Fprintf(c.b, " %%%s = fcmp ult double %s, %s\n", lessTmp, lhs, rhs) + fmt.Fprintf(c.b, " %%%s = fcmp uno double %s, %s\n", unorderedTmp, lhs, rhs) + return equalTmp, lessTmp, unorderedTmp +} + +func (c *amd64Ctx) setX87CompareFlags(lhs, rhs string) { + equal, less, unordered := c.x87CompareBits(lhs, rhs) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", equal, c.flagsZSlot) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", less, c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", unordered, c.flagsPFSlot) + // FCOMI/FUCOMI clear OF, SF, and AF. flagsSltSlot models SF xor OF. + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsSltSlot) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsOFSlot) +} + +func (c *amd64Ctx) setX87CompareStatus(lhs, rhs string) { + equal, less, unordered := c.x87CompareBits(lhs, rhs) + c3Word := c.x87StatusBit(equal, 16384) + c2Word := c.x87StatusBit(unordered, 1024) + c0Word := c.x87StatusBit(less, 256) + partial := c.newTmp() + status := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i16 %s, %s\n", partial, c3Word, c2Word) + fmt.Fprintf(c.b, " %%%s = or i16 %%%s, %s\n", status, partial, c0Word) + fmt.Fprintf(c.b, " store i16 %%%s, ptr %s\n", status, c.x87StatusSlot) +} + func x87OperandReg(op Operand) (int, bool) { if op.Kind != OpReg { return 0, false @@ -269,6 +745,244 @@ func x87OperandReg(op Operand) (int, bool) { return amd64ParseX87Reg(op.Reg) } +func isX87RegisterOperand(op Operand) bool { + _, ok := x87OperandReg(op) + return ok +} + +func isX87F0(op Operand) bool { + index, ok := x87OperandReg(op) + return ok && index == 0 +} + +func isX87MemoryOperand(op Operand) bool { + return op.Kind == OpMem || op.Kind == OpSym || op.Kind == OpFP +} + +func (c *amd64Ctx) loadX87MoveValue(op Op, src Operand) (string, error) { + switch op { + case "FMOVF": + value, err := c.evalF32(src) + if err != nil { + return "", err + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fpext float %s to double\n", wide, value) + return "%" + wide, nil + case "FMOVL", "FMOVW": + typ := I32 + if op == "FMOVW" { + typ = I16 + } + value, err := c.evalIntSized(src, typ) + if err != nil { + return "", err + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sitofp %s %s to double\n", wide, typ, value) + return "%" + wide, nil + default: + return "", fmt.Errorf("386: unsupported x87 move load %s", op) + } +} + +func (c *amd64Ctx) storeX87MoveValue(op Op, dst Operand, value string) error { + switch op { + case "FMOVF": + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fptrunc double %s to float\n", narrow, value) + return c.storeX87TypedMemory(dst, LLVMType("float"), "%"+narrow) + case "FMOVL", "FMOVW": + typ := I32 + if op == "FMOVW" { + typ = I16 + } + rounded := c.roundX87Software(value) + integer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fptosi double %s to %s\n", integer, rounded, typ) + return c.storeX87TypedMemory(dst, typ, "%"+integer) + default: + return fmt.Errorf("386: unsupported x87 move store %s", op) + } +} + +func (c *amd64Ctx) storeX87TypedMemory(dst Operand, typ LLVMType, value string) error { + if dst.Kind == OpFP { + return c.storeFPResult(dst.FPOffset, typ, value) + } + ptr, ptrType, err := c.x87MemoryPointer(dst) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, %s %s, align 1\n", typ, value, ptrType, ptr) + return nil +} + +func (c *amd64Ctx) x87MemoryPointer(op Operand) (string, string, error) { + if !isX87MemoryOperand(op) { + return "", "", fmt.Errorf("386 x87 instruction expected memory, got %s", op.String()) + } + ptr, ptrType, err := c.x86DescriptorMemoryPointer(op) + if err != nil { + return "", "", fmt.Errorf("386 x87 memory operand %s: %w", op.String(), err) + } + return ptr, ptrType, nil +} + +func (c *amd64Ctx) loadX87Environment(src Operand) error { + ptr, _, err := c.x87MemoryPointer(src) + if err != nil { + return err + } + control := c.newTmp() + statusPtr := c.newTmp() + status := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i16, ptr %s, align 1\n", control, ptr) + fmt.Fprintf(c.b, " %%%s = getelementptr i8, ptr %s, i64 4\n", statusPtr, ptr) + fmt.Fprintf(c.b, " %%%s = load i16, ptr %%%s, align 1\n", status, statusPtr) + fmt.Fprintf(c.b, " store i16 %%%s, ptr %s\n", control, c.x87ControlSlot) + fmt.Fprintf(c.b, " store i16 %%%s, ptr %s\n", status, c.x87StatusSlot) + if c.useHardwareX87() { + c.loadHardwareX87ControlWord() + } + return nil +} + +func (c *amd64Ctx) storeX87Environment(dst Operand) error { + ptr, _, err := c.x87MemoryPointer(dst) + if err != nil { + return err + } + if c.useHardwareX87() { + c.storeHardwareX87ControlWord() + } + control := c.newTmp() + status := c.newTmp() + statusPtr := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i16, ptr %s\n", control, c.x87ControlSlot) + fmt.Fprintf(c.b, " %%%s = load i16, ptr %s\n", status, c.x87StatusSlot) + fmt.Fprintf(c.b, " store i16 %%%s, ptr %s, align 1\n", control, ptr) + fmt.Fprintf(c.b, " %%%s = getelementptr i8, ptr %s, i64 4\n", statusPtr, ptr) + fmt.Fprintf(c.b, " store i16 %%%s, ptr %%%s, align 1\n", status, statusPtr) + return nil +} + +func (c *amd64Ctx) loadX87Extended(src Operand) (string, error) { + ptr, ptrType, err := c.x87MemoryPointer(src) + if err != nil { + return "", err + } + extended := c.newTmp() + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load x86_fp80, %s %s, align 1\n", extended, ptrType, ptr) + fmt.Fprintf(c.b, " %%%s = fptrunc x86_fp80 %%%s to double\n", value, extended) + return "%" + value, nil +} + +func (c *amd64Ctx) storeX87Extended(dst Operand, value string) error { + ptr, ptrType, err := c.x87MemoryPointer(dst) + if err != nil { + return err + } + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fpext double %s to x86_fp80\n", extended, value) + fmt.Fprintf(c.b, " store x86_fp80 %%%s, %s %s, align 1\n", extended, ptrType, ptr) + return nil +} + +func (c *amd64Ctx) loadX87PackedBCD(src Operand) (string, error) { + ptr, _, err := c.x87MemoryPointer(src) + if err != nil { + return "", err + } + accumulator := "0" + for i := 8; i >= 0; i-- { + bytePtr := c.newTmp() + packed := c.newTmp() + low := c.newTmp() + highShifted := c.newTmp() + high := c.newTmp() + low64 := c.newTmp() + high64 := c.newTmp() + digit10 := c.newTmp() + digits := c.newTmp() + scaled := c.newTmp() + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = getelementptr i8, ptr %s, i64 %d\n", bytePtr, ptr, i) + fmt.Fprintf(c.b, " %%%s = load i8, ptr %%%s, align 1\n", packed, bytePtr) + fmt.Fprintf(c.b, " %%%s = and i8 %%%s, 15\n", low, packed) + fmt.Fprintf(c.b, " %%%s = lshr i8 %%%s, 4\n", highShifted, packed) + fmt.Fprintf(c.b, " %%%s = and i8 %%%s, 15\n", high, highShifted) + fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i64\n", low64, low) + fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i64\n", high64, high) + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, 10\n", digit10, high64) + fmt.Fprintf(c.b, " %%%s = add i64 %%%s, %%%s\n", digits, digit10, low64) + fmt.Fprintf(c.b, " %%%s = mul i64 %s, 100\n", scaled, accumulator) + fmt.Fprintf(c.b, " %%%s = add i64 %%%s, %%%s\n", next, scaled, digits) + accumulator = "%" + next + } + signPtr := c.newTmp() + signByte := c.newTmp() + signBits := c.newTmp() + isNegative := c.newTmp() + negative := c.newTmp() + signed := c.newTmp() + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = getelementptr i8, ptr %s, i64 9\n", signPtr, ptr) + fmt.Fprintf(c.b, " %%%s = load i8, ptr %%%s, align 1\n", signByte, signPtr) + fmt.Fprintf(c.b, " %%%s = and i8 %%%s, -128\n", signBits, signByte) + fmt.Fprintf(c.b, " %%%s = icmp ne i8 %%%s, 0\n", isNegative, signBits) + fmt.Fprintf(c.b, " %%%s = sub i64 0, %s\n", negative, accumulator) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 %s\n", signed, isNegative, negative, accumulator) + fmt.Fprintf(c.b, " %%%s = sitofp i64 %%%s to double\n", value, signed) + return "%" + value, nil +} + +func (c *amd64Ctx) storeX87PackedBCD(dst Operand, value string) error { + ptr, _, err := c.x87MemoryPointer(dst) + if err != nil { + return err + } + rounded := c.roundX87Software(value) + integer := c.newTmp() + isNegative := c.newTmp() + negated := c.newTmp() + absolute := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fptosi double %s to i64\n", integer, rounded) + fmt.Fprintf(c.b, " %%%s = icmp slt i64 %%%s, 0\n", isNegative, integer) + fmt.Fprintf(c.b, " %%%s = sub i64 0, %%%s\n", negated, integer) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 %%%s\n", absolute, isNegative, negated, integer) + remaining := "%" + absolute + for i := 0; i < 9; i++ { + digits := c.newTmp() + tens := c.newTmp() + ones := c.newTmp() + tensByte := c.newTmp() + onesByte := c.newTmp() + shifted := c.newTmp() + packed := c.newTmp() + bytePtr := c.newTmp() + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = urem i64 %s, 100\n", digits, remaining) + fmt.Fprintf(c.b, " %%%s = udiv i64 %%%s, 10\n", tens, digits) + fmt.Fprintf(c.b, " %%%s = urem i64 %%%s, 10\n", ones, digits) + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i8\n", tensByte, tens) + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i8\n", onesByte, ones) + fmt.Fprintf(c.b, " %%%s = shl i8 %%%s, 4\n", shifted, tensByte) + fmt.Fprintf(c.b, " %%%s = or i8 %%%s, %%%s\n", packed, shifted, onesByte) + fmt.Fprintf(c.b, " %%%s = getelementptr i8, ptr %s, i64 %d\n", bytePtr, ptr, i) + fmt.Fprintf(c.b, " store i8 %%%s, ptr %%%s, align 1\n", packed, bytePtr) + fmt.Fprintf(c.b, " %%%s = udiv i64 %s, 100\n", next, remaining) + remaining = "%" + next + } + sign := c.newTmp() + signPtr := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i8 -128, i8 0\n", sign, isNegative) + fmt.Fprintf(c.b, " %%%s = getelementptr i8, ptr %s, i64 9\n", signPtr, ptr) + fmt.Fprintf(c.b, " store i8 %%%s, ptr %%%s, align 1\n", sign, signPtr) + return nil +} + func (c *amd64Ctx) loadX87(index int) string { t := c.newTmp() fmt.Fprintf(c.b, " %%%s = load double, ptr %s\n", t, c.x87Slot[index]) @@ -294,6 +1008,73 @@ func (c *amd64Ctx) popX87() { c.storeX87(len(c.x87Slot)-1, "0.000000e+00") } +func (c *amd64Ctx) rotateX87Stack(increment bool) { + values := make([]string, len(c.x87Slot)) + for i := range values { + values[i] = c.loadX87(i) + } + if increment { + for i := range values { + c.storeX87(i, values[(i+1)%len(values)]) + } + return + } + for i := range values { + c.storeX87(i, values[(i+len(values)-1)%len(values)]) + } +} + +func (c *amd64Ctx) clearX87C2() { + status := c.newTmp() + cleared := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i16, ptr %s\n", status, c.x87StatusSlot) + fmt.Fprintf(c.b, " %%%s = and i16 %%%s, -1025\n", cleared, status) + fmt.Fprintf(c.b, " store i16 %%%s, ptr %s\n", cleared, c.x87StatusSlot) +} + +func (c *amd64Ctx) classifyX87F0() { + value := c.loadX87(0) + isNaN := c.newTmp() + isZero := c.newTmp() + abs := c.newTmp() + isInfinity := c.newTmp() + notNaN := c.newTmp() + notZero := c.newTmp() + c2 := c.newTmp() + c0 := c.newTmp() + bits := c.newTmp() + signBits := c.newTmp() + isNegative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp uno double %s, %s\n", isNaN, value, value) + fmt.Fprintf(c.b, " %%%s = fcmp oeq double %s, 0.000000e+00\n", isZero, value) + fmt.Fprintf(c.b, " %%%s = call double @llvm.fabs.f64(double %s)\n", abs, value) + fmt.Fprintf(c.b, " %%%s = fcmp oeq double %%%s, 0x7FF0000000000000\n", isInfinity, abs) + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", notNaN, isNaN) + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", notZero, isZero) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", c2, notNaN, notZero) + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", c0, isNaN, isInfinity) + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", bits, value) + fmt.Fprintf(c.b, " %%%s = and i64 %%%s, -9223372036854775808\n", signBits, bits) + fmt.Fprintf(c.b, " %%%s = icmp ne i64 %%%s, 0\n", isNegative, signBits) + c3Word := c.x87StatusBit(isZero, 16384) + c2Word := c.x87StatusBit(c2, 1024) + c1Word := c.x87StatusBit(isNegative, 512) + c0Word := c.x87StatusBit(c0, 256) + first := c.newTmp() + second := c.newTmp() + status := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i16 %s, %s\n", first, c3Word, c2Word) + fmt.Fprintf(c.b, " %%%s = or i16 %%%s, %s\n", second, first, c1Word) + fmt.Fprintf(c.b, " %%%s = or i16 %%%s, %s\n", status, second, c0Word) + fmt.Fprintf(c.b, " store i16 %%%s, ptr %s\n", status, c.x87StatusSlot) +} + +func (c *amd64Ctx) x87StatusBit(condition string, mask int) string { + word := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i16 %d, i16 0\n", word, condition, mask) + return "%" + word +} + func (c *amd64Ctx) evalX87F64(op Operand) (string, error) { if index, ok := x87OperandReg(op); ok { return c.loadX87(index), nil diff --git a/amd64_lower_x87_conditional_move.go b/amd64_lower_x87_conditional_move.go new file mode 100644 index 00000000..f0d4d9c6 --- /dev/null +++ b/amd64_lower_x87_conditional_move.go @@ -0,0 +1,56 @@ +package plan9asm + +import "fmt" + +func (c *amd64Ctx) lowerX87ConditionalMove(op Op, ins Instr) error { + if len(ins.Args) != 2 { + return fmt.Errorf("%s %s expects one x87 source and F0 destination: %q", c.goarch, op, ins.Raw) + } + source, sourceOK := x87OperandReg(ins.Args[0]) + destination, destinationOK := x87OperandReg(ins.Args[1]) + if !sourceOK || !destinationOK || destination != 0 { + return fmt.Errorf("%s %s operands are outside Go 1.27's Yrf,F0 row: %q", c.goarch, op, ins.Raw) + } + + cf := func() string { return c.loadFlag(c.flagsCFSlot) } + zf := func() string { return c.loadFlag(c.flagsZSlot) } + pf := func() string { return c.loadFlag(c.flagsPFSlot) } + not := func(value string) string { + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", inverted, value) + return "%" + inverted + } + combine := func(instruction, left, right string) string { + condition := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s i1 %s, %s\n", condition, instruction, left, right) + return "%" + condition + } + + condition := "" + switch op { + case "FCMOVB", "FCMOVCS": + condition = cf() + case "FCMOVBE", "FCMOVLS": + condition = combine("or", cf(), zf()) + case "FCMOVE", "FCMOVEQ": + condition = zf() + case "FCMOVNB", "FCMOVCC": + condition = not(cf()) + case "FCMOVNBE", "FCMOVHI": + condition = combine("and", not(cf()), not(zf())) + case "FCMOVNE": + condition = not(zf()) + case "FCMOVNU": + condition = not(pf()) + case "FCMOVU", "FCMOVUN": + condition = pf() + default: + return fmt.Errorf("unsupported x87 conditional move %s", op) + } + sourceValue := c.loadX87(source) + destinationValue := c.loadX87(0) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, double %s, double %s\n", selected, condition, sourceValue, destinationValue) + c.storeX87(0, "%"+selected) + return nil +} diff --git a/amd64_lower_x87_conditional_move_test.go b/amd64_lower_x87_conditional_move_test.go new file mode 100644 index 00000000..7d05c6a9 --- /dev/null +++ b/amd64_lower_x87_conditional_move_test.go @@ -0,0 +1,203 @@ +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +var x87ConditionalMoveGo127Ops = []string{ + "FCMOVCC", "FCMOVCS", "FCMOVEQ", "FCMOVHI", "FCMOVLS", + "FCMOVB", "FCMOVBE", "FCMOVNB", "FCMOVNBE", "FCMOVE", + "FCMOVNE", "FCMOVNU", "FCMOVU", "FCMOVUN", +} + +func x86X87ConditionalMoveCompleteFormsSource() string { + var source strings.Builder + source.WriteString("TEXT x87conditionalmoveforms(SB),$0-0\n") + for _, op := range x87ConditionalMoveGo127Ops { + source.WriteString("\t" + op + " F0, F0\n") + source.WriteString("\t" + op + " F7, F0\n") + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86X87ConditionalMoveCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86X87ConditionalMoveCompleteFormsSource() + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"x87conditionalmoveforms": {Name: "x87conditionalmoveforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"select i1", "or i1", "and i1", "xor i1"} { + if !strings.Contains(ir, want) { + t.Fatalf("x87 conditional-move lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, target.triple, "x87-conditional-move-"+target.name+".ll", "x87-conditional-move-"+target.name+".o", ir) + }) + } +} + +func TestTranslateX86X87ConditionalMoveRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, instruction := range []string{ + "FCMOVB 0(AX), F0", + "FCMOVBE F8, F0", + "FCMOVE F1, F2", + "FCMOVNB F1", + "FCMOVNBE F1, F0, F2", + "FCMOVU.Z F1, F0", + } { + for _, goarch := range []string{"amd64", "386"} { + t.Run(goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's yfcmv table", instruction) + } + }) + } + } +} + +func TestAMD64X87ConditionalMoveRuntimeConditions(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT x87conditionalmovesemantics(SB),NOSPLIT,$0-8 + MOVQ data+0(FP), DI + + FINIT + FMOVD 64(DI), F0 + FMOVD 72(DI), F0 + STC + FCMOVB F1, F0 + FMOVDP F0, 0(DI) + FINIT + FMOVD 64(DI), F0 + FMOVD 72(DI), F0 + STC + FCMOVNB F1, F0 + FMOVDP F0, 8(DI) + + FINIT + FMOVD 64(DI), F0 + FMOVD 72(DI), F0 + XORL AX, AX + FCMOVE F1, F0 + FMOVDP F0, 16(DI) + FINIT + FMOVD 64(DI), F0 + FMOVD 72(DI), F0 + XORL AX, AX + FCMOVNE F1, F0 + FMOVDP F0, 24(DI) + + FINIT + FMOVD 64(DI), F0 + FMOVD 72(DI), F0 + XORL AX, AX + FCMOVBE F1, F0 + FMOVDP F0, 32(DI) + FINIT + FMOVD 64(DI), F0 + FMOVD 72(DI), F0 + XORL AX, AX + FCMOVNBE F1, F0 + FMOVDP F0, 40(DI) + + FINIT + FMOVD 64(DI), F0 + FMOVD 72(DI), F0 + XORL AX, AX + FCMOVU F1, F0 + FMOVDP F0, 48(DI) + FINIT + FMOVD 64(DI), F0 + FMOVD 72(DI), F0 + XORL AX, AX + FCMOVNU F1, F0 + FMOVDP F0, 56(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "x87conditionalmovesemantics": { + Name: "x87conditionalmovesemantics", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void x87conditionalmovesemantics(uint8_t *); +int main(void) { + double data[10] = {0}; + data[8] = 1.25; + data[9] = 9.5; + x87conditionalmovesemantics((uint8_t *)data); + const double expected[8] = {1.25, 9.5, 1.25, 9.5, 1.25, 9.5, 1.25, 9.5}; + for (int i = 0; i < 8; ++i) if (data[i] != expected[i]) return 10+i; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "x87_conditional_move_semantics", triple, ir, mainC, runPrefix) +} diff --git a/amd64_lower_xadd_test.go b/amd64_lower_xadd_test.go new file mode 100644 index 00000000..78f88c77 --- /dev/null +++ b/amd64_lower_xadd_test.go @@ -0,0 +1,294 @@ +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateX86XADDCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + source string + }{ + { + name: "darwin-amd64", + goarch: "amd64", + triple: "x86_64-apple-darwin", + source: ` +DATA xadddata+0(SB)/8, $0 +GLOBL xadddata(SB), $8 +TEXT xaddforms(SB),$0-0 + XADDB AH, BL + XADDB R11, R12 + XADDB DL, 8(BX) + XADDB R11, xadddata(SB) + XADDW DX, BX + XADDW R11, R12 + XADDW DX, 8(BX) + XADDW R11, xadddata(SB) + XADDL DX, BX + XADDL R11, R12 + XADDL DX, 8(BX) + XADDL R11, xadddata(SB) + XADDQ DX, BX + XADDQ R11, R12 + XADDQ DX, 8(BX) + XADDQ R11, xadddata(SB) + RET +`, + }, + { + name: "linux-amd64", + goarch: "amd64", + triple: "x86_64-unknown-linux-gnu", + source: ` +DATA xadddata+0(SB)/8, $0 +GLOBL xadddata(SB), $8 +TEXT xaddforms(SB),$0-0 + XADDB AH, BL + XADDB R11, R12 + XADDB DL, 8(BX) + XADDB R11, xadddata(SB) + XADDW DX, BX + XADDW R11, R12 + XADDW DX, 8(BX) + XADDW R11, xadddata(SB) + XADDL DX, BX + XADDL R11, R12 + XADDL DX, 8(BX) + XADDL R11, xadddata(SB) + XADDQ DX, BX + XADDQ R11, R12 + XADDQ DX, 8(BX) + XADDQ R11, xadddata(SB) + RET +`, + }, + { + name: "windows-amd64", + goarch: "amd64", + triple: "x86_64-pc-windows-msvc", + source: ` +DATA xadddata+0(SB)/8, $0 +GLOBL xadddata(SB), $8 +TEXT xaddforms(SB),$0-0 + XADDB AH, BL + XADDB R11, R12 + XADDB DL, 8(BX) + XADDB R11, xadddata(SB) + XADDW DX, BX + XADDW R11, R12 + XADDW DX, 8(BX) + XADDW R11, xadddata(SB) + XADDL DX, BX + XADDL R11, R12 + XADDL DX, 8(BX) + XADDL R11, xadddata(SB) + XADDQ DX, BX + XADDQ R11, R12 + XADDQ DX, 8(BX) + XADDQ R11, xadddata(SB) + RET +`, + }, + { + name: "linux-386", + goarch: "386", + triple: "i386-unknown-linux-gnu", + source: ` +DATA xadddata386+0(SB)/4, $0 +GLOBL xadddata386(SB), $4 +TEXT xaddforms(SB),$0-0 + XADDB AH, BL + XADDB BP, DI + XADDB DL, 8(BX) + XADDB SI, xadddata386(SB) + XADDW DX, BX + XADDW SI, DI + XADDW DX, 8(BX) + XADDW SI, xadddata386(SB) + XADDL DX, BX + XADDL SI, DI + XADDL DX, 8(BX) + XADDL SI, xadddata386(SB) + RET +`, + }, + { + name: "windows-386", + goarch: "386", + triple: "i686-pc-windows-msvc", + source: ` +DATA xadddata386+0(SB)/4, $0 +GLOBL xadddata386(SB), $4 +TEXT xaddforms(SB),$0-0 + XADDB AH, BL + XADDB BP, DI + XADDB DL, 8(BX) + XADDB SI, xadddata386(SB) + XADDW DX, BX + XADDW SI, DI + XADDW DX, 8(BX) + XADDW SI, xadddata386(SB) + XADDL DX, BX + XADDL SI, DI + XADDL DX, 8(BX) + XADDL SI, xadddata386(SB) + RET +`, + }, + } { + t.Run(target.name, func(t *testing.T) { + requireX86GoAssemblerResult(t, target.goarch, target.source, true) + file, err := Parse(ArchAMD64, target.source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"xaddforms": {Name: "xaddforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"add i8", "add i16", "add i32", "store i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("XADD lowering omitted %q:\n%s", want, ll) + } + } + if target.goarch == "amd64" && !strings.Contains(ll, "add i64") { + t.Fatalf("XADDQ lowering omitted add i64:\n%s", ll) + } + compileLLVMToObject(t, llc, target.triple, "xadd-"+target.name+".ll", "xadd-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86XADDRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "XADDB (BX), DL"}, + {goarch: "amd64", instruction: "XADDW $1, DX"}, + {goarch: "amd64", instruction: "XADDL X0, DX"}, + {goarch: "amd64", instruction: "XADDQ DX, $1"}, + {goarch: "amd64", instruction: "XADDQ DX"}, + {goarch: "amd64", instruction: "XADDL DX, BX, AX"}, + {goarch: "386", instruction: "XADDB SP, (BX)"}, + {goarch: "386", instruction: "XADDL R8, (BX)"}, + {goarch: "386", instruction: "XADDQ DX, BX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's XADD optab", test.instruction) + } + }) + } +} + +func TestAMD64XADDRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT xaddsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVQ $5, AX + MOVQ $7, BX + XADDQ AX, BX + MOVQ AX, 0(DI) + MOVQ BX, 8(DI) + MOVB $0xff, 16(DI) + MOVB $1, CL + XADDB CL, 16(DI) + MOVB CL, 17(DI) + SETCS 18(DI) + SETEQ 19(DI) + SETPS 20(DI) + SETMI 21(DI) + SETOS 22(DI) + MOVQ $0x1122, AX + XADDB AH, AL + MOVQ AX, 24(DI) + MOVQ $0x1122334455660001, AX + MOVQ $0x887766554433ffff, BX + XADDW AX, BX + MOVQ AX, 32(DI) + MOVQ BX, 40(DI) + MOVQ $3, AX + XADDQ AX, AX + MOVQ AX, 48(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "xaddsemantics": { + Name: "xaddsemantics", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void xaddsemantics(uint8_t *); +int main(void) { + uint8_t out[56] = {0}; + xaddsemantics(out); + if (*(uint64_t *)(out+0) != 7 || *(uint64_t *)(out+8) != 12) return 10; + if (out[16] != 0 || out[17] != 0xff) return 11; + if (out[18] != 1 || out[19] != 1 || out[20] != 1) return 12; + if (out[21] != 0 || out[22] != 0) return 13; + if (*(uint64_t *)(out+24) != 0x2233) return 14; + if (*(uint64_t *)(out+32) != UINT64_C(0x112233445566ffff)) return 15; + if (*(uint64_t *)(out+40) != UINT64_C(0x8877665544330000)) return 16; + if (*(uint64_t *)(out+48) != 6) return 17; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "xadd_semantics", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_xchg_test.go b/amd64_lower_xchg_test.go new file mode 100644 index 00000000..03b170d6 --- /dev/null +++ b/amd64_lower_xchg_test.go @@ -0,0 +1,220 @@ +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func x86XCHGCompleteFormsSource(goarch string) string { + var source strings.Builder + symbol := "xchgdata" + size := 8 + if goarch == "386" { + symbol = "xchgdata386" + size = 4 + } + fmt.Fprintf(&source, "DATA %s+0(SB)/%d, $0\n", symbol, size) + fmt.Fprintf(&source, "GLOBL %s(SB), $%d\n", symbol, size) + source.WriteString("TEXT xchgforms(SB),$0-0\n") + if goarch == "amd64" { + source.WriteString("\tXCHGB AH, BL\n\tXCHGB R11, R12\n") + } else { + source.WriteString("\tXCHGB AH, BL\n\tXCHGB BP, DI\n") + } + source.WriteString("\tXCHGB DL, 8(BX)\n\tXCHGB 8(BX), DL\n") + if goarch == "amd64" { + source.WriteString("\tXCHGB R11, " + symbol + "(SB)\n\tXCHGB " + symbol + "(SB), R11\n") + } else { + source.WriteString("\tXCHGB SI, " + symbol + "(SB)\n\tXCHGB " + symbol + "(SB), SI\n") + } + widths := []string{"W", "L"} + if goarch == "amd64" { + widths = append(widths, "Q") + } + for _, width := range widths { + if goarch == "amd64" { + fmt.Fprintf(&source, "\tXCHG%s DX, BX\n\tXCHG%s R11, R12\n", width, width) + } else { + fmt.Fprintf(&source, "\tXCHG%s DX, BX\n\tXCHG%s SI, DI\n", width, width) + } + fmt.Fprintf(&source, "\tXCHG%s DX, 8(BX)\n\tXCHG%s 8(BX), DX\n", width, width) + if goarch == "amd64" { + fmt.Fprintf(&source, "\tXCHG%s R11, %s(SB)\n\tXCHG%s %s(SB), R11\n", width, symbol, width, symbol) + } else { + fmt.Fprintf(&source, "\tXCHG%s SI, %s(SB)\n\tXCHG%s %s(SB), SI\n", width, symbol, width, symbol) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateX86XCHGCompleteGo127FormsAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := x86XCHGCompleteFormsSource(target.goarch) + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"xchgforms": {Name: "xchgforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"atomicrmw xchg", "i8", "i16", "i32"} { + if !strings.Contains(ll, want) { + t.Fatalf("XCHG lowering omitted %q:\n%s", want, ll) + } + } + if target.goarch == "amd64" && !strings.Contains(ll, "i64") { + t.Fatalf("XCHGQ lowering omitted i64 operations:\n%s", ll) + } + compileLLVMToObject(t, llc, target.triple, "xchg-"+target.name+".ll", "xchg-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86XCHGRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, test := range []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "XCHGB X0, DL"}, + {goarch: "amd64", instruction: "XCHGW $1, DX"}, + {goarch: "amd64", instruction: "XCHGL 0(BX), 8(CX)"}, + {goarch: "amd64", instruction: "XCHGQ DX, X0"}, + {goarch: "amd64", instruction: "XCHGW DX"}, + {goarch: "amd64", instruction: "XCHGL DX, BX, AX"}, + {goarch: "386", instruction: "XCHGB SP, (BX)"}, + {goarch: "386", instruction: "XCHGL R8, (BX)"}, + {goarch: "386", instruction: "XCHGQ DX, BX"}, + } { + t.Run(test.goarch+"/"+strings.NewReplacer(" ", "_", ",", "").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's XCHG optab", test.instruction) + } + }) + } +} + +func TestAMD64XCHGRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT xchgsemantics(SB),NOSPLIT,$0-8 + MOVQ out+0(FP), DI + MOVQ $0x1122, AX + MOVQ $0x3344, BX + XCHGB AH, BL + MOVQ AX, 0(DI) + MOVQ BX, 8(DI) + MOVQ $0x1122334455667788, AX + MOVQ $0x887766554433aabb, BX + XCHGW AX, BX + MOVQ AX, 16(DI) + MOVQ BX, 24(DI) + MOVQ $0x1122334455667788, AX + MOVQ $0x88776655aabbccdd, BX + XCHGL AX, BX + MOVQ AX, 32(DI) + MOVQ BX, 40(DI) + MOVQ $5, AX + MOVQ $7, BX + XCHGQ AX, BX + MOVQ AX, 48(DI) + MOVQ BX, 56(DI) + MOVB $0x5a, 64(DI) + MOVQ $0x11223344556677c3, AX + CMPQ AX, AX + STC + XCHGB 64(DI), AL + MOVQ AX, 72(DI) + SETCS 80(DI) + SETEQ 81(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "xchgsemantics": { + Name: "xchgsemantics", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void xchgsemantics(uint8_t *); +int main(void) { + uint8_t out[88] = {0}; + xchgsemantics(out); + if (*(uint64_t *)(out+0) != UINT64_C(0x4422)) return 10; + if (*(uint64_t *)(out+8) != UINT64_C(0x3311)) return 11; + if (*(uint64_t *)(out+16) != UINT64_C(0x112233445566aabb)) return 12; + if (*(uint64_t *)(out+24) != UINT64_C(0x8877665544337788)) return 13; + if (*(uint64_t *)(out+32) != UINT64_C(0xaabbccdd)) return 14; + if (*(uint64_t *)(out+40) != UINT64_C(0x55667788)) return 15; + if (*(uint64_t *)(out+48) != 7 || *(uint64_t *)(out+56) != 5) return 16; + if (out[64] != 0xc3 || *(uint64_t *)(out+72) != UINT64_C(0x112233445566775a)) return 17; + if (out[80] != 1 || out[81] != 1) return 18; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "xchg_semantics", triple, ll, mainC, runPrefix) +} diff --git a/amd64_lower_xlat.go b/amd64_lower_xlat.go new file mode 100644 index 00000000..0633719e --- /dev/null +++ b/amd64_lower_xlat.go @@ -0,0 +1,40 @@ +package plan9asm + +import "fmt" + +func (c *amd64Ctx) lowerXLAT(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "XLAT" { + return false, false, nil + } + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("%s XLAT takes no operands: %q", c.goarch, ins.Raw) + } + base := "" + if c.goarch == "386" { + value, err := c.evalIntSized(Operand{Kind: OpReg, Reg: BX}, I32) + if err != nil { + return true, false, err + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, value) + base = "%" + wide + } else { + value, err := c.loadReg(BX) + if err != nil { + return true, false, err + } + base = value + } + index, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AL}, I8) + if err != nil { + return true, false, err + } + wideIndex := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i8 %s to i64\n", wideIndex, index) + basePointer := c.ptrFromAddrI64(base) + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = getelementptr i8, ptr %s, i64 %%%s\n", pointer, basePointer, wideIndex) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i8, ptr %%%s, align 1\n", value, pointer) + return true, false, c.storeRegSized(AL, I8, "%"+value) +} diff --git a/amd64_lower_xstate.go b/amd64_lower_xstate.go new file mode 100644 index 00000000..da007ebb --- /dev/null +++ b/amd64_lower_xstate.go @@ -0,0 +1,155 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type amd64XStateFamily uint8 + +const ( + amd64XStateFX amd64XStateFamily = iota + amd64XStateXSAVE + amd64XStateXSAVEOPT + amd64XStateXSAVEC + amd64XStateXSAVES + amd64XStateXRSTOR + amd64XStateXRSTORS +) + +type amd64XStateDirection uint8 + +const ( + amd64XStateSave amd64XStateDirection = iota + amd64XStateRestore +) + +type amd64XStateSpec struct { + family amd64XStateFamily + direction amd64XStateDirection + mode64 bool + implicitMask bool + memoryBytes int +} + +// amd64XStateSpecs is the complete Go 1.27 extended-state memory grammar. +// Opcode spelling selects only the state family, transfer direction, and +// encoding mode; one parser owns the shared Ym memory operand rule. +var amd64XStateSpecs = map[Op]amd64XStateSpec{ + "FXSAVE": {family: amd64XStateFX, direction: amd64XStateSave, memoryBytes: 512}, + "FXSAVE64": {family: amd64XStateFX, direction: amd64XStateSave, mode64: true, memoryBytes: 512}, + "FXRSTOR": {family: amd64XStateFX, direction: amd64XStateRestore, memoryBytes: 512}, + "FXRSTOR64": {family: amd64XStateFX, direction: amd64XStateRestore, mode64: true, memoryBytes: 512}, + "XSAVE": {family: amd64XStateXSAVE, direction: amd64XStateSave, implicitMask: true, memoryBytes: 1}, + "XSAVE64": {family: amd64XStateXSAVE, direction: amd64XStateSave, mode64: true, implicitMask: true, memoryBytes: 1}, + "XSAVEOPT": {family: amd64XStateXSAVEOPT, direction: amd64XStateSave, implicitMask: true, memoryBytes: 1}, + "XSAVEOPT64": {family: amd64XStateXSAVEOPT, direction: amd64XStateSave, mode64: true, implicitMask: true, memoryBytes: 1}, + "XSAVEC": {family: amd64XStateXSAVEC, direction: amd64XStateSave, implicitMask: true, memoryBytes: 1}, + "XSAVEC64": {family: amd64XStateXSAVEC, direction: amd64XStateSave, mode64: true, implicitMask: true, memoryBytes: 1}, + "XSAVES": {family: amd64XStateXSAVES, direction: amd64XStateSave, implicitMask: true, memoryBytes: 1}, + "XSAVES64": {family: amd64XStateXSAVES, direction: amd64XStateSave, mode64: true, implicitMask: true, memoryBytes: 1}, + "XRSTOR": {family: amd64XStateXRSTOR, direction: amd64XStateRestore, implicitMask: true, memoryBytes: 1}, + "XRSTOR64": {family: amd64XStateXRSTOR, direction: amd64XStateRestore, mode64: true, implicitMask: true, memoryBytes: 1}, + "XRSTORS": {family: amd64XStateXRSTORS, direction: amd64XStateRestore, implicitMask: true, memoryBytes: 1}, + "XRSTORS64": {family: amd64XStateXRSTORS, direction: amd64XStateRestore, mode64: true, implicitMask: true, memoryBytes: 1}, +} + +type amd64XStateForm struct { + memory Operand +} + +func (c *amd64Ctx) lowerXState(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(rawOp, '.'); dot >= 0 { + baseOp = rawOp[:dot] + } + spec, recognized := amd64XStateSpecs[Op(baseOp)] + if !recognized { + return false, false, nil + } + if rawOp != baseOp { + return true, false, fmt.Errorf("%s %s does not accept instruction suffixes: %q", c.goarch, baseOp, ins.Raw) + } + if c.goarch == "386" && spec.mode64 { + return true, false, fmt.Errorf("386 %s is absent from Go 1.27's 32-bit encoding table: %q", baseOp, ins.Raw) + } + form, err := c.parseXStateForm(baseOp, ins) + if err != nil { + return true, false, err + } + return c.emitXState(spec, form) +} + +func (c *amd64Ctx) parseXStateForm(op string, ins Instr) (amd64XStateForm, error) { + var form amd64XStateForm + if len(ins.Args) != 1 { + return form, fmt.Errorf("%s %s expects one Go 1.27 Ym memory operand: %q", c.goarch, op, ins.Raw) + } + memory := ins.Args[0] + if !isAMD64MemoryOperand(memory) { + return form, fmt.Errorf("%s %s expects Go 1.27 Ym memory: %q", c.goarch, op, ins.Raw) + } + if memory.Kind == OpMem && !x86MemoryRegistersValidForArch(memory.Mem, c.goarch) { + return form, fmt.Errorf("%s %s address uses an out-of-range register: %q", c.goarch, op, ins.Raw) + } + return amd64XStateForm{memory: memory}, nil +} + +func (spec amd64XStateSpec) mnemonic() string { + var mnemonic string + switch spec.family { + case amd64XStateFX: + mnemonic = "fxsave" + if spec.direction == amd64XStateRestore { + mnemonic = "fxrstor" + } + case amd64XStateXSAVE: + mnemonic = "xsave" + case amd64XStateXSAVEOPT: + mnemonic = "xsaveopt" + case amd64XStateXSAVEC: + mnemonic = "xsavec" + case amd64XStateXSAVES: + mnemonic = "xsaves" + case amd64XStateXRSTOR: + mnemonic = "xrstor" + case amd64XStateXRSTORS: + mnemonic = "xrstors" + default: + panic("unknown amd64 xstate family") + } + if spec.mode64 { + mnemonic += "64" + } + return mnemonic +} + +func (c *amd64Ctx) emitXState(spec amd64XStateSpec, form amd64XStateForm) (bool, bool, error) { + pointer, pointerType, err := c.x86DescriptorMemoryPointer(form.memory) + if err != nil { + return true, false, err + } + memoryConstraint := "=*m" + if spec.direction == amd64XStateRestore { + memoryConstraint = "*m" + } + constraints := memoryConstraint + arguments := fmt.Sprintf("%s elementtype([%d x i8]) %s", pointerType, spec.memoryBytes, pointer) + if spec.implicitMask { + ax, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AX}, I32) + if err != nil { + return true, false, err + } + dx, err := c.evalIntSized(Operand{Kind: OpReg, Reg: DX}, I32) + if err != nil { + return true, false, err + } + constraints += ",{ax},{dx}" + arguments += fmt.Sprintf(", i32 %s, i32 %s", ax, dx) + } + constraints += ",~{memory},~{dirflag},~{fpsr},~{flags}" + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(%s)\n", + spec.mnemonic()+" $0", constraints, arguments) + return true, false, nil +} diff --git a/amd64_lower_xstate_test.go b/amd64_lower_xstate_test.go new file mode 100644 index 00000000..d8d37f09 --- /dev/null +++ b/amd64_lower_xstate_test.go @@ -0,0 +1,211 @@ +package plan9asm + +import ( + "reflect" + "runtime" + "sort" + "strings" + "testing" +) + +func TestAMD64XStateGrammarIsComplete(t *testing.T) { + got := make([]string, 0, len(amd64XStateSpecs)) + for op := range amd64XStateSpecs { + got = append(got, string(op)) + } + sort.Strings(got) + want := []string{ + "FXRSTOR", "FXRSTOR64", "FXSAVE", "FXSAVE64", + "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", + "XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", "XSAVES", "XSAVES64", + } + if !reflect.DeepEqual(got, want) { + t.Fatalf("xstate grammar opcodes = %v, want %v", got, want) + } + for op, want := range map[Op]amd64XStateSpec{ + "FXSAVE": {family: amd64XStateFX, direction: amd64XStateSave, memoryBytes: 512}, + "FXSAVE64": {family: amd64XStateFX, direction: amd64XStateSave, mode64: true, memoryBytes: 512}, + "FXRSTOR": {family: amd64XStateFX, direction: amd64XStateRestore, memoryBytes: 512}, + "FXRSTOR64": {family: amd64XStateFX, direction: amd64XStateRestore, mode64: true, memoryBytes: 512}, + "XSAVE": {family: amd64XStateXSAVE, direction: amd64XStateSave, implicitMask: true, memoryBytes: 1}, + "XSAVE64": {family: amd64XStateXSAVE, direction: amd64XStateSave, mode64: true, implicitMask: true, memoryBytes: 1}, + "XSAVEOPT": {family: amd64XStateXSAVEOPT, direction: amd64XStateSave, implicitMask: true, memoryBytes: 1}, + "XSAVEOPT64": {family: amd64XStateXSAVEOPT, direction: amd64XStateSave, mode64: true, implicitMask: true, memoryBytes: 1}, + "XSAVEC": {family: amd64XStateXSAVEC, direction: amd64XStateSave, implicitMask: true, memoryBytes: 1}, + "XSAVEC64": {family: amd64XStateXSAVEC, direction: amd64XStateSave, mode64: true, implicitMask: true, memoryBytes: 1}, + "XSAVES": {family: amd64XStateXSAVES, direction: amd64XStateSave, implicitMask: true, memoryBytes: 1}, + "XSAVES64": {family: amd64XStateXSAVES, direction: amd64XStateSave, mode64: true, implicitMask: true, memoryBytes: 1}, + "XRSTOR": {family: amd64XStateXRSTOR, direction: amd64XStateRestore, implicitMask: true, memoryBytes: 1}, + "XRSTOR64": {family: amd64XStateXRSTOR, direction: amd64XStateRestore, mode64: true, implicitMask: true, memoryBytes: 1}, + "XRSTORS": {family: amd64XStateXRSTORS, direction: amd64XStateRestore, implicitMask: true, memoryBytes: 1}, + "XRSTORS64": {family: amd64XStateXRSTORS, direction: amd64XStateRestore, mode64: true, implicitMask: true, memoryBytes: 1}, + } { + if got := amd64XStateSpecs[op]; got != want { + t.Errorf("xstate grammar %s = %+v, want %+v", op, got, want) + } + } +} + +func TestTranslateX86XStateCompleteGoAssemblerForms(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + source := `TEXT xstateforms(SB),$0-0 + FXSAVE (BX) + FXRSTOR 8(BP) + XSAVE 16(SI) + XRSTOR 24(DI) + XSAVEOPT 32(BX) + XSAVEC 40(BP) + XSAVES 48(SI) + XRSTORS 56(DI) +` + if target.goarch == "amd64" { + source += ` FXSAVE64 64(R11) + FXRSTOR64 72(R12) + XSAVE64 80(R13) + XRSTOR64 88(R14) + XSAVEOPT64 96(R15) + XSAVEC64 104(R11) + XSAVES64 112(R12) + XRSTORS64 120(R13) +` + } + source += "\tRET\n" + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"xstateforms": {Name: "xstateforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"fxsave", "fxrstor", "xsave", "xrstor", "xsaveopt", "xsavec", "xsaves", "xrstors"} { + if !strings.Contains(ir, want+" $0") { + t.Errorf("IR is missing %s:\n%s", want, ir) + } + } + if want := `"target-features"="+fxsr,+xsave,+xsavec,+xsaveopt,+xsaves"`; !strings.Contains(ir, want) { + t.Errorf("IR is missing complete xstate feature set %s:\n%s", want, ir) + } + compileLLVMToObject(t, llc, target.triple, "xstate-"+target.name+".ll", "xstate-"+target.name+".o", ir) + }) + } +} + +func TestAMD64FXStateRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT fxstatesemantics(SB),NOSPLIT,$0-8 + MOVQ area+0(FP), DI + FXSAVE (DI) + FXRSTOR (DI) + FXSAVE64 512(DI) + FXRSTOR64 512(DI) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: triple, + Sigs: map[string]FuncSig{"fxstatesemantics": { + Name: "fxstatesemantics", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void fxstatesemantics(uint8_t *); +int main(void) { + __attribute__((aligned(16))) uint8_t area[1024]; + memset(area, 0xa5, sizeof(area)); + fxstatesemantics(area); + uint16_t control0 = 0, control1 = 0; + memcpy(&control0, area, sizeof(control0)); + memcpy(&control1, area + 512, sizeof(control1)); + if (control0 == UINT16_C(0xa5a5)) return 10; + if (control1 == UINT16_C(0xa5a5)) return 11; + if (control0 != control1) return 12; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "fxstate_semantics", triple, ir, mainC, runPrefix) +} + +func TestTranslateX86XStateRejectsFormsOutsideGoTables(t *testing.T) { + tests := []struct { + goarch string + instruction string + }{ + {goarch: "amd64", instruction: "FXSAVE AX"}, + {goarch: "amd64", instruction: "FXRSTOR $1"}, + {goarch: "amd64", instruction: "XSAVE"}, + {goarch: "amd64", instruction: "XRSTOR (BX), (CX)"}, + {goarch: "amd64", instruction: "XSAVEOPT.Z (BX)"}, + {goarch: "amd64", instruction: "XSAVEC X0"}, + {goarch: "amd64", instruction: "XSAVES AX"}, + {goarch: "amd64", instruction: "XRSTORS $1"}, + {goarch: "386", instruction: "XSAVE (R11)"}, + } + for _, op := range []string{"FXSAVE64", "FXRSTOR64", "XSAVE64", "XRSTOR64", "XSAVEOPT64", "XSAVEC64", "XSAVES64", "XRSTORS64"} { + tests = append(tests, struct { + goarch string + instruction string + }{goarch: "386", instruction: op + " (BX)"}) + } + for _, test := range tests { + t.Run(test.goarch+"_"+strings.NewReplacer(" ", "_", "$", "", "(", "_", ")", "_").Replace(test.instruction), func(t *testing.T) { + source := "TEXT bad(SB),$0-0\n\t" + test.instruction + "\n\tRET\n" + requireX86GoAssemblerResult(t, test.goarch, source, false) + file, err := Parse(ArchAMD64, source) + if err != nil { + return + } + triple := "x86_64-unknown-linux-gnu" + if test.goarch == "386" { + triple = "i386-unknown-linux-gnu" + } + if _, err := Translate(file, Options{ + Goarch: test.goarch, TargetTriple: triple, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's xstate tables", test.instruction) + } + }) + } +} diff --git a/amd64_needed.go b/amd64_needed.go index 9a52b4df..f821374c 100644 --- a/amd64_needed.go +++ b/amd64_needed.go @@ -2,18 +2,27 @@ package plan9asm import "strings" -// funcNeedsAMD64CFG decides whether we need the CFG-based amd64 translator. -// The linear prototype cannot handle labels/branches and most vector ops. +// funcNeedsAMD64CFG decides whether the direct LLVM-module prototype can +// represent an amd64 function. Textual translation always uses the complete +// architecture-aware x86 CFG lowerer. func funcNeedsAMD64CFG(fn Func) bool { for _, ins := range fn.Instrs { if ins.Op == OpLABEL { return true } op := strings.ToUpper(string(ins.Op)) + for _, operand := range ins.Args { + if _, _, ok := x86MachineRegisterOperand(operand); ok { + return true + } + if x86SegmentRegisterOperand(operand) { + return true + } + } switch Op(op) { - case "JMP", "JL", "JLT", "JLE", "JG", "JGT", "JGE", + case "JMP", "JCXZW", "JCXZL", "JCXZQ", "JL", "JLT", "JLE", "JG", "JGT", "JGE", "JB", "JLO", "JBE", "JA", "JHI", "JAE", "JHS", - "JZ", "JE", "JEQ", "JNZ", "JNE", "JNC", "JC", "JCC", "JLS", "JNA", "JS", "JNS": + "JZ", "JE", "JEQ", "JNZ", "JNE", "JNC", "JC", "JCS", "JCC", "JLS", "JNA", "JS", "JNS": return true } // A handful of amd64 stdlib asm functions are straight-line, but if we @@ -21,10 +30,10 @@ func funcNeedsAMD64CFG(fn Func) bool { if strings.HasPrefix(op, "MOVO") || strings.HasPrefix(op, "PCLMUL") || strings.HasPrefix(op, "CRC32") || strings.HasPrefix(op, "PXOR") { return true } - // Keep the linear path only for the tiny subset it currently lowers. + // Keep the direct-module path only for the tiny subset it currently lowers. switch Op(op) { case OpTEXT, OpBYTE, OpMOVQ, OpMOVL, OpADDQ, OpSUBQ, OpXORQ, OpCPUID, OpXGETBV: - // For MOVQ/MOVL, linear lowering supports immediate/reg/FP value flow. + // For MOVQ/MOVL, direct lowering supports immediate/reg/FP value flow. // Addressing forms (mem/sym) require CFG lowering. if (op == "MOVQ" || op == "MOVL") && len(ins.Args) == 2 { for _, a := range ins.Args { diff --git a/amd64_operand_forms_test.go b/amd64_operand_forms_test.go index dde7de5c..bac6e8ca 100644 --- a/amd64_operand_forms_test.go +++ b/amd64_operand_forms_test.go @@ -99,22 +99,19 @@ func TestAMD64VectorLoweringBranchCoverage(t *testing.T) { } } - check("gf2-z-source-class", "VGF2P8AFFINEQB", Instr{Args: []Operand{imm(0), reg("Z0"), reg("X1"), reg("Z2")}}, false, false) + check("gf2-z-source-class", "VGF2P8AFFINEQB", Instr{Args: []Operand{imm(0), reg("Z0"), reg("X1"), reg("Z2")}}, true, true) check("gf2-z-source-error", "VGF2P8AFFINEQB", Instr{Args: []Operand{imm(0), reg("Z0"), ident("bad"), reg("Z2")}}, true, true) - check("gf2-y-source-class", "VGF2P8AFFINEQB", Instr{Args: []Operand{imm(0), reg("Y0"), reg("X1"), reg("Y2")}}, false, false) + check("gf2-y-source-class", "VGF2P8AFFINEQB", Instr{Args: []Operand{imm(0), reg("Y0"), reg("X1"), reg("Y2")}}, true, true) check("gf2-y-source-error", "VGF2P8AFFINEQB", Instr{Args: []Operand{imm(0), reg("Y0"), ident("bad"), reg("Y2")}}, true, true) - check("gf2-unsupported-dst", "VGF2P8AFFINEQB", Instr{Args: []Operand{imm(0), reg("Y0"), reg("Y1"), reg("X2")}}, false, false) + check("gf2-unsupported-dst", "VGF2P8AFFINEQB", Instr{Args: []Operand{imm(0), reg("Y0"), reg("Y1"), reg("X2")}}, true, true) - check("broadcast-i128-args", "VBROADCASTI128", Instr{Args: []Operand{reg("X0")}}, true, true) - check("broadcast-i128-dst", "VBROADCASTI128", Instr{Args: []Operand{reg("X0"), reg("X1")}}, false, false) - check("broadcast-i128-source", "VBROADCASTI128", Instr{Args: []Operand{ident("bad"), reg("Y1")}}, true, true) check("broadcast-scalar-args", "VBROADCASTSD", Instr{Args: []Operand{imm(1)}}, true, true) check("broadcast-scalar-source", "VBROADCASTSD", Instr{Args: []Operand{ident("bad"), reg("Y1")}}, true, true) - check("broadcast-scalar-immediate", "VBROADCASTSD", Instr{Args: []Operand{imm(1), reg("Y1")}}, false, false) - check("broadcast-scalar-gpr", "VBROADCASTSD", Instr{Args: []Operand{reg("AX"), reg("Y1")}}, false, false) + check("broadcast-scalar-immediate", "VBROADCASTSD", Instr{Args: []Operand{imm(1), reg("Y1")}}, true, true) + check("broadcast-scalar-gpr", "VBROADCASTSD", Instr{Args: []Operand{reg("AX"), reg("Y1")}}, true, true) check("broadcast-scalar-x-source", "VBROADCASTSD", Instr{Args: []Operand{reg("X0"), reg("Y1")}}, false, true) - check("broadcast-scalar-x-dst", "VBROADCASTSD", Instr{Args: []Operand{reg("X0"), reg("X1")}}, false, false) - check("broadcast-scalar-dst", "VBROADCASTSD", Instr{Args: []Operand{mem("AX"), reg("AX")}}, false, false) + check("broadcast-scalar-x-dst", "VBROADCASTSD", Instr{Args: []Operand{reg("X0"), reg("X1")}}, true, true) + check("broadcast-scalar-dst", "VBROADCASTSD", Instr{Args: []Operand{mem("AX"), reg("AX")}}, true, true) check("broadcast-q-x", "VPBROADCASTQ", Instr{Args: []Operand{reg("X0"), reg("X1")}}, false, true) check("broadcast-q-gpr", "VPBROADCASTQ", Instr{Args: []Operand{reg("AX"), reg("X1")}}, false, true) check("broadcast-q-immediate", "VPBROADCASTQ", Instr{Args: []Operand{imm(1), reg("X1")}}, false, false) @@ -129,6 +126,18 @@ func TestAMD64VectorLoweringBranchCoverage(t *testing.T) { check("punpckllq-src", "PUNPCKLLQ", Instr{Args: []Operand{reg("Y0"), reg("X1")}}, false, false) check("punpckhlq-source-error", "PUNPCKHLQ", Instr{Args: []Operand{ident("bad"), reg("X1")}}, true, true) check("punpckllq-memory", "PUNPCKLLQ", Instr{Args: []Operand{mem("AX"), reg("X1")}}, false, true) + for _, op := range []Op{"PMINUB", "PMINSB", "PMINUW", "PMINSW", "PMINUD", "PMINSD", "PMAXUB", "PMAXSB", "PMAXUW", "PMAXSW", "PMAXUD", "PMAXSD"} { + check(string(op)+"-args", op, Instr{Args: []Operand{reg("X0")}}, true, true) + check(string(op)+"-dst", op, Instr{Args: []Operand{reg("X0"), reg("Y1")}}, false, false) + check(string(op)+"-source", op, Instr{Args: []Operand{ident("bad"), reg("X1")}}, true, true) + check(string(op)+"-memory", op, Instr{Args: []Operand{mem("AX"), reg("X1")}}, false, true) + } + for _, op := range []Op{"PSLLQ", "PSRLQ"} { + check(string(op)+"-args", op, Instr{Args: []Operand{imm(1)}}, true, true) + check(string(op)+"-dst", op, Instr{Args: []Operand{imm(1), reg("Y1")}}, false, false) + check(string(op)+"-count", op, Instr{Args: []Operand{reg("AX"), reg("X1")}}, true, true) + check(string(op)+"-negative", op, Instr{Args: []Operand{imm(-1), reg("X1")}}, true, true) + } check("xorpd-args", "VXORPD", Instr{Args: []Operand{reg("X0")}}, true, true) check("xorpd-z", "VXORPD", Instr{Args: []Operand{reg("Z0"), reg("Z1"), reg("Z2")}}, false, true) @@ -140,11 +149,11 @@ func TestAMD64VectorLoweringBranchCoverage(t *testing.T) { check("xorpd-x", "VXORPD", Instr{Args: []Operand{reg("X0"), reg("X1"), reg("X2")}}, false, true) check("xorpd-x-source1", "VXORPD", Instr{Args: []Operand{ident("bad"), reg("X1"), reg("X2")}}, true, true) check("xorpd-x-source2", "VXORPD", Instr{Args: []Operand{reg("X0"), ident("bad"), reg("X2")}}, true, true) - check("xorpd-unsupported-dst", "VXORPD", Instr{Args: []Operand{reg("X0"), reg("X1"), reg("AX")}}, false, false) + check("xorpd-unsupported-dst", "VXORPD", Instr{Args: []Operand{reg("X0"), reg("X1"), reg("AX")}}, true, true) - check("ternlog-y-source1-class", "VPTERNLOGD", Instr{Args: []Operand{imm(0x96), reg("X0"), reg("Y1"), reg("Y2")}}, false, false) - check("ternlog-y-source2-class", "VPTERNLOGD", Instr{Args: []Operand{imm(0x96), reg("Y0"), reg("X1"), reg("Y2")}}, false, false) - check("ternlog-y-imm", "VPTERNLOGD", Instr{Args: []Operand{imm(0x95), reg("Y0"), reg("Y1"), reg("Y2")}}, true, true) + check("ternlog-y-source1-class", "VPTERNLOGD", Instr{Args: []Operand{imm(0x96), reg("X0"), reg("Y1"), reg("Y2")}}, true, true) + check("ternlog-y-source2-class", "VPTERNLOGD", Instr{Args: []Operand{imm(0x96), reg("Y0"), reg("X1"), reg("Y2")}}, true, true) + check("ternlog-y-imm", "VPTERNLOGD", Instr{Args: []Operand{imm(0x95), reg("Y0"), reg("Y1"), reg("Y2")}}, false, true) check("ternlog-y-source1", "VPTERNLOGD", Instr{Args: []Operand{imm(0x96), ident("bad"), reg("Y1"), reg("Y2")}}, true, true) check("ternlog-y-source2", "VPTERNLOGD", Instr{Args: []Operand{imm(0x96), reg("Y0"), ident("bad"), reg("Y2")}}, true, true) diff --git a/amd64_raw.go b/amd64_raw.go new file mode 100644 index 00000000..ee3efbe1 --- /dev/null +++ b/amd64_raw.go @@ -0,0 +1,8569 @@ +package plan9asm + +import ( + "encoding/binary" + "fmt" + "sort" + "strings" + + "golang.org/x/arch/x86/x86asm" +) + +func normalizeX86RawFile(file *File, goarch string) (*File, error) { + if file == nil || file.Arch != ArchAMD64 { + return file, nil + } + normalized := *file + normalized.Funcs = append([]Func(nil), file.Funcs...) + if err := preserveAddressSensitiveX86RawText(&normalized); err != nil { + return nil, err + } + for i := range normalized.Funcs { + if normalized.Funcs[i].X86RawText != nil { + continue + } + fn, err := decodeX86RawDirectives(normalized.Funcs[i], goarch) + if err != nil { + return nil, fmt.Errorf("%s: %w", normalized.Funcs[i].Sym, err) + } + normalized.Funcs[i] = fn + } + return &normalized, nil +} + +// preserveAddressSensitiveX86RawText identifies raw-only TEXT bodies whose +// exact byte layout is observed elsewhere in the same source file. Typical +// examples are boot trampolines patched through symbol+offset references and +// TEXT-backed descriptor/data tables. Decoding such a body into LLVM +// operations would make the referenced byte offsets false even when the +// instruction semantics happened to match. +// +// Raw-only bodies that are merely called or jumped to are deliberately not +// selected: those remain on the normal semantic decoder path. +func preserveAddressSensitiveX86RawText(file *File) error { + if file == nil || file.Arch != ArchAMD64 { + return nil + } + candidates := make(map[string]int) + encoded := make(map[int][]byte) + for index := range file.Funcs { + fn := &file.Funcs[index] + candidateName := strings.TrimSuffix(fn.Sym, "<>") + if fn.X86RawText != nil { + candidates[candidateName] = index + encoded[index] = append([]byte(nil), fn.X86RawText...) + continue + } + var code []byte + hasRaw := false + rawOnly := true + for _, ins := range fn.Instrs { + if ins.Op == OpTEXT { + continue + } + if !isX86RawDirective(ins) { + rawOnly = false + break + } + part, err := x86RawDirectiveBytes(ins) + if err != nil { + return fmt.Errorf("%s: %w", fn.Sym, err) + } + code = append(code, part...) + hasRaw = true + } + if !rawOnly || !hasRaw { + continue + } + candidates[candidateName] = index + encoded[index] = code + } + if len(candidates) == 0 { + return nil + } + + addressed := make(map[int]bool) + markSymbol := func(symbol string) { + base, _, ok := parseSBRef(strings.TrimSpace(strings.TrimPrefix(symbol, "*"))) + if !ok { + return + } + base = strings.TrimSuffix(base, "<>") + if index, exists := candidates[base]; exists { + addressed[index] = true + } + } + for _, fn := range file.Funcs { + for _, ins := range fn.Instrs { + op := Op(strings.ToUpper(string(ins.Op))) + if op == OpCALL || op == OpJMP || op == OpRET || isAMD64ConditionalBranch(op) { + continue + } + for _, operand := range ins.Args { + switch operand.Kind { + case OpSym: + markSymbol(operand.Sym) + case OpMem: + if operand.Mem.Sym != "" { + markSymbol(operand.Mem.Sym) + } + } + } + } + } + for index := range addressed { + file.Funcs[index].X86RawText = append([]byte(nil), encoded[index]...) + } + return nil +} + +// decodeX86RawDirectives replaces consecutive BYTE/WORD/LONG/QUAD directives +// with the Plan 9 instructions represented by those bytes. The decoder and +// syntax printer come from Go's architecture tables; the resulting instruction +// still has to pass the ordinary plan9asm operand-form and semantic lowerers. +// This is deliberately not an opaque inline-assembly escape hatch. +func decodeX86RawDirectives(fn Func, goarch string) (Func, error) { + mode := 64 + if goarch == "386" { + mode = 32 + } else if goarch != "" && goarch != "amd64" { + return fn, fmt.Errorf("raw x86 directives require GOARCH 386 or amd64, got %q", goarch) + } + + knownLabels := make(map[string]bool) + for _, ins := range fn.Instrs { + if ins.Op == OpLABEL && len(ins.Args) == 1 && ins.Args[0].Kind == OpLabel { + knownLabels[ins.Args[0].Sym] = true + } + } + + var normalized []Instr + for i := 0; i < len(fn.Instrs); { + if !isX86RawDirective(fn.Instrs[i]) { + normalized = append(normalized, fn.Instrs[i]) + i++ + continue + } + + start := i + var code []byte + var rawLines []string + for i < len(fn.Instrs) && isX86RawDirective(fn.Instrs[i]) { + encoded, err := x86RawDirectiveBytes(fn.Instrs[i]) + if err != nil { + return fn, err + } + code = append(code, encoded...) + rawLines = append(rawLines, fn.Instrs[i].Raw) + i++ + } + rawGroup := strings.Join(rawLines, "; ") + if mode == 64 { + if target, ok := x86RawRetpolineTarget(code); ok { + normalized = append(normalized, Instr{ + Op: OpJMP, + Args: []Operand{{Kind: OpReg, Reg: target}}, + Raw: fmt.Sprintf("JMP %s /* decoded retpoline from %s */", target, rawGroup), + }) + continue + } + } + decoded, err := decodeX86RawDirectiveGroup(code, mode, start, rawGroup, knownLabels) + if err != nil { + return fn, err + } + normalized = append(normalized, decoded...) + } + fn.Instrs = normalized + return fn, nil +} + +type x86RawDecodedInstruction struct { + length int + instrs []Instr +} + +// decodeX86RawDirectiveGroup follows every reachable path through one raw +// directive group. Internal relative JMP/Jcc targets become synthetic source +// labels, so backward edges and both short and near conditional branches keep +// their control-flow semantics. Bytes skipped by all reachable paths remain +// uninterpreted, which permits the embedded signatures and constant data used +// by generated assembly. Any edge outside the group or into an instruction is +// still rejected rather than being guessed from final linked layout. +func decodeX86RawDirectiveGroup(code []byte, mode, start int, rawGroup string, knownLabels map[string]bool) ([]Instr, error) { + decodedByOffset := make(map[int]x86RawDecodedInstruction) + labels := make(map[int]string) + owners := make([]int, len(code)) + for i := range owners { + owners[i] = -1 + } + queue := []int{0} + queued := map[int]bool{0: true} + + labelFor := func(target int) string { + if label := labels[target]; label != "" { + return label + } + base := fmt.Sprintf("raw_jcc_%d_%d", start, target) + label := base + for suffix := 2; knownLabels[label]; suffix++ { + label = fmt.Sprintf("%s_%d", base, suffix) + } + knownLabels[label] = true + labels[target] = label + return label + } + enqueue := func(target int) error { + if target < 0 || target > len(code) { + return fmt.Errorf("raw x86 PC-relative target byte %d at instruction %d is outside directive group: %q", target, start, rawGroup) + } + if target < len(code) && owners[target] >= 0 && owners[target] != target { + return fmt.Errorf("raw x86 PC-relative target byte %d at instruction %d is not an instruction boundary: %q", target, start, rawGroup) + } + labelFor(target) + if !queued[target] { + queued[target] = true + queue = append(queue, target) + } + return nil + } + markInstruction := func(offset, length int) error { + if length <= 0 || offset+length > len(code) { + return fmt.Errorf("raw x86 instruction at instruction %d byte %d has invalid length %d: %q", start, offset, length, rawGroup) + } + for current := offset; current < offset+length; current++ { + if owners[current] >= 0 && owners[current] != offset { + return fmt.Errorf("raw x86 instruction at instruction %d byte %d overlaps instruction at byte %d: %q", start, offset, owners[current], rawGroup) + } + } + for current := offset; current < offset+length; current++ { + owners[current] = offset + } + return nil + } + annotate := func(instrs []Instr) []Instr { + for i := range instrs { + instrs[i].Raw = fmt.Sprintf("%s /* decoded from %s */", instrs[i].Raw, rawGroup) + } + return instrs + } + + for len(queue) != 0 { + blockStart := queue[0] + queue = queue[1:] + if blockStart == len(code) { + continue + } + if owners[blockStart] >= 0 && owners[blockStart] != blockStart { + return nil, fmt.Errorf("raw x86 PC-relative target byte %d at instruction %d is not an instruction boundary: %q", blockStart, start, rawGroup) + } + for offset := blockStart; offset < len(code); { + if _, exists := decodedByOffset[offset]; exists { + break + } + if owners[offset] >= 0 && owners[offset] != offset { + return nil, fmt.Errorf("raw x86 reachable byte %d at instruction %d is inside instruction at byte %d: %q", offset, start, owners[offset], rawGroup) + } + if instruction, length, ok := decodedX86AMDSystemManagementInstruction(code[offset:]); ok { + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + + if instruction, length, ok, err := decodedX86SegmentMoveInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 segment-register move at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if syntax, length, ok := decodedX86RandomInstruction(code[offset:], mode); ok { + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instrs, err := parseDecodedX86Instruction(syntax) + if err != nil { + return nil, fmt.Errorf("parse decoded raw x86 instruction %q at instruction %d byte %d: %w", syntax, start, offset, err) + } + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: annotate(instrs)} + offset += length + continue + } + if instruction, length, ok, err := decodedX86CacheLineWritebackInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 cache-line writeback at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VBROADCASTI128Instruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VBROADCASTI128 at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VMOVQInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VMOVQ at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86MaskMoveInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 KMOV at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86MaskVectorMoveInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 mask/vector move at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86EVEXPackedIntegerMoveInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 EVEX packed integer move at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86EVEXPackedFloatMoveInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 EVEX packed float move at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86DuplicateMoveInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 duplicate move at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VEXPackedFloatLogicalInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VEX packed floating logical instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86FloatingUnpackInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 floating unpack at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86InLaneFloatingPermuteInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 in-lane floating permute at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86ImmediatePackedBlendInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 immediate packed blend at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VEXBinaryFloatInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VEX binary floating instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86ScalarIntegerFloatInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 scalar integer-to-float instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86ScalarPrecisionConvertInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 scalar precision conversion at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86SameWidthConversionInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 same-width packed conversion at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VectorFloatCompareInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 vector floating compare instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VEXHorizontalFloatInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VEX horizontal floating instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VEXPackedIntegerLogicalInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VEX packed integer logical instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86EVEXPackedLogicalInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 EVEX packed logical instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VEXPackedMADDInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VEX packed multiply-add instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VEXFMA3Instruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VEX FMA3 instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VEXTRACT128Instruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VEXTRACT128 instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VEXNonTemporalMoveInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VEX non-temporal move at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86InsertPSInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 INSERTPS/VINSERTPS at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86PackedScalarExtractInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 packed scalar extract at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VPERMQInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VPERMQ at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VINSERT128Instruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VINSERT128 at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86EVEXPackedInsertInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 EVEX packed insert at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VEXPackedBroadcastInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 packed broadcast at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86PackedAlignRightInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 packed align-right at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86Permute128Instruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 128-bit lane permute at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VSHUFPSInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VSHUFPS at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86PackedShuffleInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 packed shuffle at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86Shuffle128BitBlocksInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VSHUFF/VSHUFI block shuffle at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VPSHUFBInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VPSHUFB at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86PackedExtendInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 packed extending move at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86PackedIntegerArithmeticInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 packed integer arithmetic at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86PackedImmediateRotateInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 packed immediate rotate at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VectorAlignInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VALIGN at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86TernaryLogicInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 ternary logic at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86FunnelShiftInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 funnel shift at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86PackedLogicalShiftInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 packed logical shift at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VPERMI2Instruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VPERMI2 at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86IFMAInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 IFMA at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VPINSRInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VPINSR at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VPUNPCKInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VPUNPCK at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VNNIInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VNNI at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86VariableDwordPermuteInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 VPERMD/VPERMPS at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86SHAInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 SHA at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86BLSInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 BLS at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86ANDNInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 ANDN at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86MULXInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 MULX at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86RORXInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 RORX at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86DwordToQwordMultiplyInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 dword-to-qword multiply at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + if instruction, length, ok, err := decodedX86PackedMultiplyLowInstruction(code[offset:], mode); ok { + if err != nil { + return nil, fmt.Errorf("decode raw x86 packed multiply-low at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, length); err != nil { + return nil, err + } + instruction.Raw = fmt.Sprintf("%s /* decoded from %s */", instruction.Raw, rawGroup) + decodedByOffset[offset] = x86RawDecodedInstruction{length: length, instrs: []Instr{instruction}} + offset += length + continue + } + + inst, err := x86asm.Decode(code[offset:], mode) + if err != nil || inst.Len <= 0 || inst.Op == 0 { + if err == nil { + if inst.Len <= 0 { + err = fmt.Errorf("decoder consumed zero bytes") + } else { + err = fmt.Errorf("incomplete or unknown instruction") + } + } + return nil, fmt.Errorf("decode raw x86 directive group at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + if err := markInstruction(offset, inst.Len); err != nil { + return nil, err + } + syntax, err := decodedX86GoSyntax(inst, code[offset:offset+inst.Len]) + if err != nil { + return nil, fmt.Errorf("convert decoded raw x86 instruction at instruction %d byte %d: %w: %q", start, offset, err, rawGroup) + } + opName := strings.Fields(syntax)[0] + op := Op(strings.ToUpper(opName)) + if inst.PCRel != 0 { + target, ok := x86RawRelativeTarget(inst, offset) + isJump := op == OpJMP + isConditional := isAMD64ConditionalBranch(op) + if !ok || (!isJump && !isConditional) { + return nil, fmt.Errorf("raw x86 PC-relative instruction at instruction %d byte %d cannot be mapped safely to source labels: %q", start, offset, rawGroup) + } + if err := enqueue(target); err != nil { + return nil, fmt.Errorf("raw x86 branch at byte %d: %w", offset, err) + } + label := labelFor(target) + branch := Instr{Op: op, Args: []Operand{{Kind: OpIdent, Ident: label}}, Raw: fmt.Sprintf("%s %s /* decoded from %s */", op, label, rawGroup)} + decodedByOffset[offset] = x86RawDecodedInstruction{length: inst.Len, instrs: []Instr{branch}} + if isConditional { + if err := enqueue(offset + inst.Len); err != nil { + return nil, fmt.Errorf("raw x86 conditional fallthrough at byte %d: %w", offset, err) + } + } + break + } + if inst.Op == x86asm.JMP { + return nil, fmt.Errorf("raw x86 indirect jump at instruction %d byte %d cannot be mapped safely: %q", start, offset, rawGroup) + } + instrs, err := parseDecodedX86Instruction(syntax) + if err != nil { + return nil, fmt.Errorf("parse decoded raw x86 instruction %q at instruction %d byte %d: %w", syntax, start, offset, err) + } + decodedByOffset[offset] = x86RawDecodedInstruction{length: inst.Len, instrs: annotate(instrs)} + offset += inst.Len + if inst.Op == x86asm.RET { + break + } + } + } + + offsets := make([]int, 0, len(decodedByOffset)) + for offset := range decodedByOffset { + offsets = append(offsets, offset) + } + sort.Ints(offsets) + result := make([]Instr, 0, len(offsets)+len(labels)) + for _, offset := range offsets { + if label := labels[offset]; label != "" { + result = append(result, Instr{Op: OpLABEL, Args: []Operand{{Kind: OpLabel, Sym: label}}, Raw: label + ":"}) + } + result = append(result, decodedByOffset[offset].instrs...) + } + if label := labels[len(code)]; label != "" { + result = append(result, Instr{Op: OpLABEL, Args: []Operand{{Kind: OpLabel, Sym: label}}, Raw: label + ":"}) + } + return result, nil +} + +// decodedX86SegmentMoveInstruction recognizes the complete 8C/8E segment +// register move family represented by Go 1.27's ymovtab. Go spells these +// operations MOVW even though x86 disassemblers often print register forms as +// MOVL or MOVQ according to the encoded general-register destination width. +func decodedX86SegmentMoveInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segmentOverride := Reg("") + addressOverride := false + rex := byte(0) + for i < len(code) { + switch code[i] { + case 0x64: + rex = 0 + segmentOverride = FS + i++ + case 0x65: + rex = 0 + segmentOverride = GS + i++ + case 0x66: + rex = 0 + i++ + case 0x67: + rex = 0 + addressOverride = true + i++ + default: + if mode == 64 && code[i] >= 0x40 && code[i] <= 0x4f { + rex = code[i] + i++ + continue + } + goto opcode + } + } + +opcode: + if i >= len(code) || (code[i] != 0x8c && code[i] != 0x8e) || len(code) < i+2 { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + modRM := code[i+1] + segmentNumber := int(modRM>>3&7) + int(rex>>2&1)*8 + segmentNames := [...]Reg{ES, CS, SS, DS, FS, GS} + if segmentNumber >= len(segmentNames) { + return Instr{}, 0, true, fmt.Errorf("reserved segment-register encoding %d", segmentNumber) + } + bExt := int(rex & 1) + xExt := int(rex>>1) & 1 + other, consumed, decodeErr := decodedX86RMSource(code[i+1:], mode, bExt, xExt, segmentOverride, 1) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + segment := Operand{Kind: OpReg, Reg: segmentNames[segmentNumber]} + args := []Operand{segment, other} + if code[i] == 0x8e { + args[0], args[1] = args[1], args[0] + } + return Instr{ + Op: "MOVW", + Args: args, + Raw: fmt.Sprintf("MOVW %s, %s", args[0].String(), args[1].String()), + }, i + 1 + consumed, true, nil +} + +// decodedX86MaskMoveInstruction recognizes Go 1.27's complete VEX-encoded +// KMOVB/W/D/Q family. x/arch v0.14 does not decode opmask registers and can +// split these bytes into unrelated legacy instructions, so recover all four +// _ykmovb operand rows before consulting the generic decoder. +func decodedX86MaskMoveInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + var vexLength, rExt, xExt, bExt int + var vexBits byte + switch { + case len(code) >= i+3 && code[i] == 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + default: + return Instr{}, 0, false, nil + } + opcodeIndex := i + vexLength + if len(code) <= opcodeIndex || code[opcodeIndex] < 0x90 || code[opcodeIndex] > 0x93 { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if vexBits&0x04 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.L must be zero") + } + if vexBits&0x78 != 0x78 { + return Instr{}, 0, true, fmt.Errorf("VEX.vvvv must be 1111") + } + + opcode := code[opcodeIndex] + pp := vexBits & 3 + width64 := vexLength == 3 && vexBits&0x80 != 0 + width := "" + if opcode == 0x90 || opcode == 0x91 { + switch { + case !width64 && pp == 1: + width = "B" + case !width64 && pp == 0: + width = "W" + case width64 && pp == 1: + width = "D" + case width64 && pp == 0: + width = "Q" + } + } else { + switch { + case !width64 && pp == 1: + width = "B" + case !width64 && pp == 0: + width = "W" + case !width64 && pp == 3: + width = "D" + case width64 && pp == 3: + width = "Q" + } + } + if width == "" { + return Instr{}, 0, true, fmt.Errorf("invalid VEX.W/pp combination") + } + + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + mod := modRM >> 6 + regNumber := int(modRM>>3&7) + rExt*8 + rmNumber := int(modRM&7) + bExt*8 + kReg := func(number int) (Operand, error) { + if number < 0 || number > 7 { + return Operand{}, fmt.Errorf("invalid opmask register K%d", number) + } + return Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", number))}, nil + } + gpReg := func(number int) (Operand, error) { + reg, valid := decodedX86GeneralRegister(number) + if !valid || mode == 32 && number >= 8 { + return Operand{}, fmt.Errorf("invalid general register %d", number) + } + return Operand{Kind: OpReg, Reg: reg}, nil + } + + var src, dst Operand + consumed := 1 + switch opcode { + case 0x90: // K-or-memory -> K + dst, err = kReg(regNumber) + if err != nil { + return Instr{}, 0, true, err + } + if mod == 3 { + src, err = kReg(rmNumber) + } else { + src, consumed, err = decodedX86VEXRMSource(code[modRMIndex:], mode, bExt, xExt, segment) + } + case 0x91: // K -> memory + if mod == 3 { + return Instr{}, 0, true, fmt.Errorf("opcode 91 requires a memory destination") + } + src, err = kReg(regNumber) + if err == nil { + dst, consumed, err = decodedX86VEXRMSource(code[modRMIndex:], mode, bExt, xExt, segment) + } + case 0x92: // GP -> K + if mod != 3 { + return Instr{}, 0, true, fmt.Errorf("opcode 92 requires a general-register source") + } + dst, err = kReg(regNumber) + if err == nil { + src, err = gpReg(rmNumber) + } + case 0x93: // K -> GP + if mod != 3 { + return Instr{}, 0, true, fmt.Errorf("opcode 93 requires a general-register destination") + } + src, err = kReg(rmNumber) + if err == nil { + dst, err = gpReg(regNumber) + } + } + if err != nil { + return Instr{}, 0, true, err + } + op := Op("KMOV" + width) + instruction = Instr{ + Op: op, + Args: []Operand{src, dst}, + Raw: fmt.Sprintf("%s %s, %s", op, src.String(), dst.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +// decodedX86EVEXPackedIntegerMoveInstruction recognizes the complete EVEX +// family behind Go 1.27's shared _yvmovdqa32 table. x/arch v0.14 cannot +// decode these encodings, including the raw VMOVDQU32 loads emitted by +// github.com/minio/sha256-simd. Decode all six opcodes and all twelve table +// rows before consulting the generic decoder. +func decodedX86EVEXPackedIntegerMoveInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + return decodedX86EVEXPackedMoveInstruction(code, mode, "packed integer move", func(pp byte, width64 bool, opcode byte) (Op, bool, bool) { + store := opcode == 0x7f + if opcode != 0x6f && !store { + return "", false, false + } + switch { + case pp == 1 && !width64: + return "VMOVDQA32", store, true + case pp == 1 && width64: + return "VMOVDQA64", store, true + case pp == 3 && !width64: + return "VMOVDQU8", store, true + case pp == 3 && width64: + return "VMOVDQU16", store, true + case pp == 2 && !width64: + return "VMOVDQU32", store, true + case pp == 2 && width64: + return "VMOVDQU64", store, true + default: + return "", false, false + } + }) +} + +// decodedX86EVEXPackedFloatMoveInstruction recognizes the EVEX rows of Go +// 1.27's shared _yvmovapd table. Its VEX rows are handled correctly by the +// generic decoder, while x/arch v0.14 rejects the EVEX VMOVAPS/APD/UPS/UPD +// encodings used by generated ecosystem assembly. +func decodedX86EVEXPackedFloatMoveInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + return decodedX86EVEXPackedMoveInstruction(code, mode, "packed float move", func(pp byte, width64 bool, opcode byte) (Op, bool, bool) { + store := opcode == 0x29 || opcode == 0x11 + switch { + case pp == 0 && !width64 && (opcode == 0x28 || opcode == 0x29): + return "VMOVAPS", store, true + case pp == 1 && width64 && (opcode == 0x28 || opcode == 0x29): + return "VMOVAPD", store, true + case pp == 0 && !width64 && (opcode == 0x10 || opcode == 0x11): + return "VMOVUPS", store, true + case pp == 1 && width64 && (opcode == 0x10 || opcode == 0x11): + return "VMOVUPD", store, true + default: + return "", false, false + } + }) +} + +type decodedX86EVEXMoveMatcher func(pp byte, width64 bool, opcode byte) (op Op, store bool, ok bool) + +func decodedX86EVEXPackedMoveInstruction(code []byte, mode int, family string, match decodedX86EVEXMoveMatcher) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto evex + } + } + +evex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+6 || code[i] != 0x62 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + if p0&0x0f != 1 || p1&0x04 == 0 || p1&0x78 != 0x78 || p2&0x08 == 0 { + return Instr{}, 0, false, nil + } + pp := p1 & 3 + width64 := p1&0x80 != 0 + op, store, matched := match(pp, width64, opcode) + if !matched { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if p2&0x10 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.b is not valid for %s", family) + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorPrefix := [...]string{"X", "Y", "Z"}[vectorBits] + disp8Scale := [...]int{16, 32, 64}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if zeroing && store { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing is invalid for a memory store") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + modRM := code[modRMIndex] + regNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + reg := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, regNumber))} + rm, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + + args := []Operand{rm, reg} + if store { + args[0], args[1] = reg, rm + } + if maskNumber != 0 { + mask := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))} + args = []Operand{args[0], mask, args[1]} + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + instruction = Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))} + return instruction, modRMIndex + consumed, true, nil +} + +func decodedX86EVEXRMOperand(code []byte, mode, bExt, xExt int, segment Reg, vectorPrefix string, disp8Scale int) (Operand, int, error) { + if len(code) == 0 { + return Operand{}, 0, fmt.Errorf("missing ModRM byte") + } + if code[0]>>6 == 3 { + number := int(code[0]&7) + bExt*8 + xExt*16 + return Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, number))}, 1, nil + } + return decodedX86RMSource(code, mode, bExt, xExt, segment, disp8Scale) +} + +func x86RawRelativeTarget(inst x86asm.Inst, offset int) (int, bool) { + for _, arg := range inst.Args { + if relative, ok := arg.(x86asm.Rel); ok { + return offset + inst.Len + int(relative), true + } + } + return 0, false +} + +// decodedX86VMOVQInstruction recognizes the complete Go 1.27 _yvmovd and +// _yvmovq families. VMOVD has the X-to-GP/memory and reverse forms; VMOVQ +// additionally has two X-to-X encodings. Recover every VEX and EVEX form +// before consulting the generic decoder, which can split the raw VMOVD bytes +// emitted by Weaviate into a relative branch. +func decodedX86VMOVQInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXVMOVDQInstruction(code, i, mode, segment, addressOverride) + } + if len(code) < i+3 { + return Instr{}, 0, false, nil + } + + var rExt, xExt, bExt, vexLength int + var vexBits byte + switch code[i] { + case 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + case 0xc4: + if len(code) < i+4 || code[i+1]&0x1f != 1 { + return Instr{}, 0, false, nil + } + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + default: + return Instr{}, 0, false, nil + } + opcodeIndex := i + vexLength + if len(code) <= opcodeIndex { + return Instr{}, 0, false, nil + } + + opcode := code[opcodeIndex] + pp := vexBits & 3 + width64 := vexLength == 3 && vexBits&0x80 != 0 + type vmovqDirection int + const ( + xToGeneral vmovqDirection = iota + xToVector + generalToX + vectorToX + ) + op := Op("") + direction := xToGeneral + switch { + case opcode == 0x7e && pp == 1 && !width64: + op = "VMOVD" + direction = xToGeneral + case opcode == 0x6e && pp == 1 && !width64: + op = "VMOVD" + direction = generalToX + case opcode == 0x7e && pp == 1 && width64: + op = "VMOVQ" + direction = xToGeneral + case opcode == 0xd6 && pp == 1 && !width64: + op = "VMOVQ" + direction = xToVector + case opcode == 0x6e && pp == 1 && width64: + op = "VMOVQ" + direction = generalToX + case opcode == 0x7e && pp == 2 && !width64: + op = "VMOVQ" + direction = vectorToX + default: + return Instr{}, 0, false, nil + } + ok = true + if vexBits&0x7c != 0x78 { + return Instr{}, 0, true, fmt.Errorf("VEX.vvvv must be 1111 and VEX.L must be zero") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + vectorNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || vectorNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + vector := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", vectorNumber))} + rmVector := direction == xToVector || direction == vectorToX + rm, consumed, decodeErr := decodedX86VEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, rmVector) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + if mode == 32 && width64 && rm.Kind == OpReg { + return Instr{}, 0, true, fmt.Errorf("64-bit general register is unavailable in 32-bit mode") + } + + args := []Operand{vector, rm} + if direction == generalToX || direction == vectorToX { + args[0], args[1] = rm, vector + } + instruction = Instr{ + Op: op, + Args: args, + Raw: fmt.Sprintf("%s %s, %s", op, args[0].String(), args[1].String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +func decodedX86EVEXVMOVDQInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+5 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + if p0&0x0f != 1 || p1&0x04 == 0 || p1&0x78 != 0x78 || p2 != 0x08 { + return Instr{}, 0, false, nil + } + pp := p1 & 3 + width64 := p1&0x80 != 0 + type vmovdqDirection int + const ( + xToGeneral vmovdqDirection = iota + xToVector + generalToX + vectorToX + ) + op := Op("") + direction := xToGeneral + switch { + case opcode == 0x7e && pp == 1 && !width64: + op = "VMOVD" + direction = xToGeneral + case opcode == 0x6e && pp == 1 && !width64: + op = "VMOVD" + direction = generalToX + case opcode == 0x7e && pp == 1 && width64: + op = "VMOVQ" + direction = xToGeneral + case opcode == 0xd6 && pp == 1 && width64: + op = "VMOVQ" + direction = xToVector + case opcode == 0x6e && pp == 1 && width64: + op = "VMOVQ" + direction = generalToX + case opcode == 0x7e && pp == 2 && width64: + op = "VMOVQ" + direction = vectorToX + default: + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + modRMIndex := i + 5 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + vectorNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + rmVector := direction == xToVector || direction == vectorToX + if mode == 32 && (vectorNumber >= 8 || rmVector && modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + if modRM>>6 == 3 && !rmVector && xExt != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.X cannot extend a general register") + } + vector := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", vectorNumber))} + transferBytes := 4 + if op == "VMOVQ" { + transferBytes = 8 + } + var rm Operand + var consumed int + var decodeErr error + if rmVector { + rm, consumed, decodeErr = decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X", transferBytes) + } else { + rm, consumed, decodeErr = decodedX86RMSource(code[modRMIndex:], mode, bExt, xExt, segment, transferBytes) + } + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + if mode == 32 && op == "VMOVQ" && rm.Kind == OpReg && !rmVector { + return Instr{}, 0, true, fmt.Errorf("64-bit general register is unavailable in 32-bit mode") + } + args := []Operand{vector, rm} + if direction == generalToX || direction == vectorToX { + args[0], args[1] = rm, vector + } + instruction = Instr{ + Op: op, + Args: args, + Raw: fmt.Sprintf("%s %s, %s", op, args[0].String(), args[1].String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +func decodedX86VEXRMOperand(code []byte, mode, bExt, xExt int, segment Reg, vectorRegister bool) (Operand, int, error) { + if len(code) == 0 { + return Operand{}, 0, fmt.Errorf("missing ModRM byte") + } + if code[0]>>6 != 3 || !vectorRegister { + return decodedX86VEXRMSource(code, mode, bExt, xExt, segment) + } + number := int(code[0]&7) + bExt*8 + if mode == 32 && number >= 8 { + return Operand{}, 0, fmt.Errorf("extended vector register in 32-bit mode") + } + return Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", number))}, 1, nil +} + +// decodedX86VEXNonTemporalMoveInstruction recognizes the complete VEX.128 and +// VEX.256 non-temporal vector-move family before x/arch's generic decoder. +// x/arch v0.14 loses the VEX.L register width for VMOVNTDQ/VMOVNTDQA and can +// decode VMOVNTPD/VMOVNTPS as legacy integer subtraction. EVEX forms are not +// handled here because the generic decoder preserves their X/Y/Z widths. +func decodedX86VEXNonTemporalMoveInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+3 { + return Instr{}, 0, false, nil + } + + var rExt, xExt, bExt, vexLength, opcodeMap int + var vexBits byte + switch code[i] { + case 0xc5: + vexLength = 2 + opcodeMap = 1 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + case 0xc4: + if len(code) < i+4 { + return Instr{}, 0, false, nil + } + vexLength = 3 + opcodeMap = int(code[i+1] & 0x1f) + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + default: + return Instr{}, 0, false, nil + } + opcodeIndex := i + vexLength + if len(code) <= opcodeIndex { + return Instr{}, 0, false, nil + } + + opcode := code[opcodeIndex] + prefix := vexBits & 3 + load := false + op := Op("") + switch { + case opcodeMap == 1 && opcode == 0xe7 && prefix == 1: + op = "VMOVNTDQ" + case opcodeMap == 1 && opcode == 0x2b && prefix == 1: + op = "VMOVNTPD" + case opcodeMap == 1 && opcode == 0x2b && prefix == 0: + op = "VMOVNTPS" + case opcodeMap == 2 && opcode == 0x2a && prefix == 1: + op = "VMOVNTDQA" + load = true + default: + return Instr{}, 0, false, nil + } + ok = true + if vexLength == 3 && vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if vexBits&0x78 != 0x78 { + return Instr{}, 0, true, fmt.Errorf("VEX.vvvv must be 1111") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + if modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("register r/m operand is absent from Go 1.27's %s table", op) + } + vectorNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || vectorNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + vector := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, vectorNumber))} + memory, consumed, decodeErr := decodedX86VEXRMSource(code[modRMIndex:], mode, bExt, xExt, segment) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + args := []Operand{vector, memory} + if load { + args[0], args[1] = memory, vector + } + instruction = Instr{ + Op: op, + Args: args, + Raw: fmt.Sprintf("%s %s, %s", op, args[0].String(), args[1].String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +// decodedX86VINSERT128Instruction recognizes the complete VEX +// VINSERTF128/VINSERTI128 family. x/arch v0.14 can misclassify the bytes that +// follow these instructions as PC-relative control flow. +func decodedX86VINSERT128Instruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if len(code) < i+5 || code[i] != 0xc4 || code[i+1]&0x1f != 3 { + return Instr{}, 0, false, nil + } + op, recognized := map[byte]Op{0x18: "VINSERTF128", 0x38: "VINSERTI128"}[code[i+3]] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if mode != 32 && mode != 64 { + return Instr{}, 0, true, fmt.Errorf("unsupported x86 mode %d", mode) + } + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("386 %s exceeds the Go assembler frontend's operand limit", op) + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vex0, vexBits := code[i+1], code[i+2] + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if vexBits&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("%s requires VEX.256", op) + } + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + modRMIndex := i + 4 + modRM := code[modRMIndex] + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + firstSource, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("Y%d", secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("Y%d", destinationNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{immediate, firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s, %s", op, immediate.String(), firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, immediateIndex + 1, true, nil +} + +// decodedX86EVEXPackedInsertInstruction recognizes every EVEX row in Go +// 1.27's _yvinsertf32x4 and _yvinsertf32x8 tables. The floating and integer +// spellings share their encodings apart from the opcode, while EVEX.W selects +// 32- or 64-bit lane names. This includes Y/Z output widths, register and +// memory insert sources, and optional merge/zero masks. +func decodedX86EVEXPackedInsertInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto evex + } + } + +evex: + if len(code) < i+5 || code[i] != 0x62 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + if p0&0x0f != 3 || p1&3 != 1 { + return Instr{}, 0, false, nil + } + integer := opcode == 0x38 || opcode == 0x3a + wideInsert := opcode == 0x1a || opcode == 0x3a + if opcode != 0x18 && opcode != 0x1a && !integer { + return Instr{}, 0, false, nil + } + ok = true + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("EVEX packed vector inserts are unavailable in 32-bit mode") + } + if p1&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX fixed bit must be one") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if p2&0x10 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.b is unavailable for packed vector inserts") + } + vectorBits := p2 >> 5 & 3 + if wideInsert { + if vectorBits != 2 { + return Instr{}, 0, true, fmt.Errorf("wide packed vector insert requires a Z output") + } + } else if vectorBits != 1 && vectorBits != 2 { + return Instr{}, 0, true, fmt.Errorf("packed vector insert requires a Y or Z output") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + insertBytes := 16 + sourceName := "X" + laneBits := 32 + if p1&0x80 != 0 { + laneBits = 64 + } + if wideInsert { + insertBytes = 32 + sourceName = "Y" + } + stem := "VINSERTF" + if integer { + stem = "VINSERTI" + } + op := Op(fmt.Sprintf("%s%dX%d", stem, laneBits, insertBytes*8/laneBits)) + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + modRMIndex := i + 5 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + secondNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + first, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, sourceName, insertBytes) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + second := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{immediate, first, second} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil +} + +// decodedX86VEXPackedBroadcastInstruction recognizes the complete VEX and EVEX +// VPBROADCASTB/W/D/Q family represented by Go 1.27's _yvpbroadcastb table. +// x/arch v0.14 can misclassify the VEX bytes as PC-relative branches, as +// observed in github.com/vivint/infectious, and cannot decode the EVEX +// general-register form used by github.com/JohanLindvall/haste. +func decodedX86VEXPackedBroadcastInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXPackedBroadcastInstruction(code, i, mode, segment, addressOverride) + } + if len(code) < i+5 || code[i] != 0xc4 || code[i+1]&0x1f != 2 { + return Instr{}, 0, false, nil + } + op, recognized := map[byte]Op{ + 0x78: "VPBROADCASTB", + 0x79: "VPBROADCASTW", + 0x58: "VPBROADCASTD", + 0x59: "VPBROADCASTQ", + }[code[i+3]] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if mode != 32 && mode != 64 { + return Instr{}, 0, true, fmt.Errorf("unsupported x86 mode %d", mode) + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vex0, vexBits := code[i+1], code[i+2] + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if int(^vexBits>>3)&15 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.vvvv must be 1111") + } + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + modRMIndex := i + 4 + modRM := code[modRMIndex] + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + vectorName := "X" + if vexBits&0x04 != 0 { + vectorName = "Y" + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{source, destination}, + Raw: fmt.Sprintf("%s %s, %s", op, source.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +func decodedX86EVEXPackedBroadcastInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+5 || code[i] != 0x62 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + if p0&0x0f != 2 || p1&3 != 1 { + return Instr{}, 0, false, nil + } + width64 := p1&0x80 != 0 + vectorSource := false + laneBytes := 0 + op := Op("") + switch opcode { + case 0x7a: + op, laneBytes = "VPBROADCASTB", 1 + case 0x7b: + op, laneBytes = "VPBROADCASTW", 2 + case 0x7c: + if width64 { + op, laneBytes = "VPBROADCASTQ", 8 + } else { + op, laneBytes = "VPBROADCASTD", 4 + } + case 0x78: + op, laneBytes, vectorSource = "VPBROADCASTB", 1, true + case 0x79: + op, laneBytes, vectorSource = "VPBROADCASTW", 2, true + case 0x58: + op, laneBytes, vectorSource = "VPBROADCASTD", 4, true + case 0x59: + op, laneBytes, vectorSource = "VPBROADCASTQ", 8, true + default: + return Instr{}, 0, false, nil + } + ok = true + if (!vectorSource || opcode != 0x59) && opcode != 0x7c && width64 { + return Instr{}, 0, true, fmt.Errorf("EVEX.W must be zero for %s", op) + } + if vectorSource && opcode == 0x59 && !width64 { + return Instr{}, 0, true, fmt.Errorf("EVEX.W must be one for %s", op) + } + if p1&0x7c != 0x7c || p2&0x08 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.vvvv must be reserved") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if p2&0x10 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.b is unavailable for packed scalar broadcasts") + } + vectorBits := p2 >> 5 & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + modRMIndex := i + 5 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + + var source Operand + consumed := 0 + if vectorSource { + if mode == 32 && modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + source, consumed, err = decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X", laneBytes) + } else { + if modRM>>6 != 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX opcode %#x requires a general-register source", opcode) + } + if xExt != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.X cannot extend a general register") + } + if mode == 32 && laneBytes == 8 { + return Instr{}, 0, true, fmt.Errorf("64-bit general register is unavailable in 32-bit mode") + } + source, consumed, err = decodedX86RMSource(code[modRMIndex:], mode, bExt, 0, segment, laneBytes) + } + if err != nil { + return Instr{}, 0, true, err + } + args := []Operand{source} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86PackedAlignRightInstruction recognizes every raw PALIGNR and +// VPALIGNR encoding represented by Go 1.27's ypalignr and +// _yvgf2p8affineinvqb tables: legacy X, VEX X/Y, and EVEX X/Y/Z with optional +// merge/zero masks. x/arch v0.14 rejects the VEX bytes used by the historical +// sha256-simd copy in github.com/ipfs/fs-repo-migrations. +func decodedX86PackedAlignRightInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + hasDataSizePrefix := false + rex := byte(0) + hasREX := false + for i < len(code) { + switch code[i] { + case 0x64: + rex = 0 + hasREX = false + segment = FS + i++ + case 0x65: + rex = 0 + hasREX = false + segment = GS + i++ + case 0x66: + rex = 0 + hasREX = false + hasDataSizePrefix = true + i++ + case 0x67: + rex = 0 + hasREX = false + addressOverride = true + i++ + default: + if mode == 64 && code[i] >= 0x40 && code[i] <= 0x4f { + rex = code[i] + hasREX = true + i++ + continue + } + goto opcode + } + } + +opcode: + if i >= len(code) { + return Instr{}, 0, false, nil + } + if code[i] == 0xc4 { + if hasDataSizePrefix || hasREX || len(code) < i+5 || code[i+1]&0x1f != 3 || code[i+3] != 0x0f { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("386 VPALIGNR exceeds the Go assembler frontend's operand limit") + } + vex0, vexBits := code[i+1], code[i+2] + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + vectorName := "X" + if vexBits&0x04 != 0 { + vectorName = "Y" + } + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + modRMIndex := i + 4 + modRM := code[modRMIndex] + firstSource, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + args := []Operand{ + {Kind: OpImm, Imm: int64(code[immediateIndex])}, + firstSource, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondSourceNumber))}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))}, + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: "VPALIGNR", Args: args, Raw: "VPALIGNR " + strings.Join(rawArgs, ", ")}, immediateIndex + 1, true, nil + } + if code[i] == 0x62 { + if hasDataSizePrefix || hasREX || len(code) < i+6 || code[i+1]&0x0f != 3 || code[i+2]&0x07 != 5 || code[i+4] != 0x0f { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("386 VPALIGNR exceeds the Go assembler frontend's operand limit") + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p1&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.W must be zero") + } + vectorBits := p2 >> 5 & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + if p2&0x10 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast is absent from Go 1.27's VPALIGNR table") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + modRM := code[modRMIndex] + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, vectorWidth) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + op := Op("VPALIGNR") + args := []Operand{ + {Kind: OpImm, Imm: int64(code[immediateIndex])}, + firstSource, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondSourceNumber))}, + } + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))}) + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil + } + + if !hasDataSizePrefix || len(code) < i+5 || code[i] != 0x0f || code[i+1] != 0x3a || code[i+2] != 0x0f { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if hasREX && rex&0x08 != 0 { + return Instr{}, 0, true, fmt.Errorf("REX.W is absent from Go 1.27's PALIGNR encoding") + } + rExt := int(rex>>2) & 1 + xExt := int(rex>>1) & 1 + bExt := int(rex & 1) + modRMIndex := i + 3 + modRM := code[modRMIndex] + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (destinationNumber >= 8 || bExt != 0 || xExt != 0) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + instruction = Instr{ + Op: "PALIGNR", + Args: []Operand{immediate, source, destination}, + Raw: fmt.Sprintf("PALIGNR %s, %s, %s", immediate.String(), source.String(), destination.String()), + } + return instruction, immediateIndex + 1, true, nil +} + +// decodedX86Permute128Instruction recognizes every raw VPERM2F128 and +// VPERM2I128 encoding represented by Go 1.27's _yvperm2f128 table: an +// immediate, Y/m256 first source, Y second source, and Y destination. +func decodedX86Permute128Instruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + hasLegacyPrefix := false + hasREX := false + for i < len(code) { + switch code[i] { + case 0x64: + hasREX = false + segment = FS + i++ + case 0x65: + hasREX = false + segment = GS + i++ + case 0x66: + hasREX = false + hasLegacyPrefix = true + i++ + case 0x67: + hasREX = false + addressOverride = true + i++ + default: + if mode == 64 && code[i] >= 0x40 && code[i] <= 0x4f { + hasREX = true + i++ + continue + } + goto opcode + } + } + +opcode: + if i >= len(code) || code[i] != 0xc4 || hasLegacyPrefix || hasREX || len(code) < i+5 { + return Instr{}, 0, false, nil + } + vex0, vexBits, opcode := code[i+1], code[i+2], code[i+3] + if vex0&0x1f != 3 || (opcode != 0x06 && opcode != 0x46) { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("386 VPERM2F128/VPERM2I128 exceeds the Go assembler frontend's operand limit") + } + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if vexBits&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.L must select 256-bit vectors") + } + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + modRMIndex := i + 4 + modRM := code[modRMIndex] + firstSource, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "Y") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + op := Op("VPERM2F128") + if opcode == 0x46 { + op = "VPERM2I128" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + args := []Operand{ + {Kind: OpImm, Imm: int64(code[immediateIndex])}, + firstSource, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("Y%d", secondSourceNumber))}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("Y%d", destinationNumber))}, + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil +} + +// decodedX86InsertPSInstruction recognizes all encodings represented by Go +// 1.27's yxshuf and _yvinsertps tables: legacy INSERTPS plus VEX and EVEX +// VINSERTPS, each with an X-register or ModRM/SIB memory source. x/arch v0.14 +// can consume one byte past VINSERTPS and desynchronize the rest of a raw +// directive group, as observed in github.com/racerxdl/segdsp. +func decodedX86InsertPSInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto encoding + } + } + +encoding: + if len(code) <= i { + return Instr{}, 0, false, nil + } + + if code[i] == 0x66 { + j := i + 1 + rex := byte(0) + if j < len(code) && code[j]&0xf0 == 0x40 { + rex = code[j] + j++ + } + if len(code) < j+4 || code[j] != 0x0f || code[j+1] != 0x3a || code[j+2] != 0x21 { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 && rex != 0 { + return Instr{}, 0, true, fmt.Errorf("REX prefix in 32-bit mode") + } + modRMIndex := j + 3 + modRM := code[modRMIndex] + rExt := int(rex>>2) & 1 + xExt := int(rex>>1) & 1 + bExt := int(rex) & 1 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended destination register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + return Instr{ + Op: "INSERTPS", + Args: []Operand{immediate, source, destination}, + Raw: fmt.Sprintf("INSERTPS %s, %s, %s", immediate.String(), source.String(), destination.String()), + }, immediateIndex + 1, true, nil + } + + if code[i] == 0xc4 { + if len(code) < i+5 || code[i+1]&0x1f != 3 || code[i+3] != 0x21 { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + p0, p1 := code[i+1], code[i+2] + if p1&0x87 != 0x01 { + return Instr{}, 0, true, fmt.Errorf("VINSERTPS requires VEX.W0.L0.66") + } + modRMIndex := i + 4 + modRM := code[modRMIndex] + rExt := int(^p0>>7) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + baseNumber := int(^p1>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (baseNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended VINSERTPS register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + base := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", baseNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + return Instr{ + Op: "VINSERTPS", + Args: []Operand{immediate, source, base, destination}, + Raw: fmt.Sprintf("VINSERTPS %s, %s, %s, %s", immediate.String(), source.String(), base.String(), destination.String()), + }, immediateIndex + 1, true, nil + } + + if code[i] != 0x62 || len(code) < i+6 || code[i+1]&0x0f != 3 || code[i+4] != 0x21 { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("EVEX VINSERTPS is unavailable in 32-bit mode") + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p1&0x87 != 0x05 || p2&0xf7 != 0 { + return Instr{}, 0, true, fmt.Errorf("VINSERTPS requires EVEX.W0.L0.66 without mask, zeroing, or broadcast") + } + modRMIndex := i + 5 + modRM := code[modRMIndex] + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + baseNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + source, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X", 4) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + base := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", baseNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + return Instr{ + Op: "VINSERTPS", + Args: []Operand{immediate, source, base, destination}, + Raw: fmt.Sprintf("VINSERTPS %s, %s, %s, %s", immediate.String(), source.String(), base.String(), destination.String()), + }, immediateIndex + 1, true, nil +} + +// decodedX86PackedScalarExtractInstruction recognizes every VEX and EVEX +// encoding row shared by Go 1.27's _yvextractps and _yvpextrw tables: +// VEXTRACTPS and VPEXTRB/W/D/Q with GP-register or ModRM/SIB memory +// destinations. x/arch v0.14 does not decode VEXTRACTPS and can interpret +// bytes after other scalar extracts as instructions or PC-relative operands, +// so recover the complete family before consulting the generic decoder. +func decodedX86PackedScalarExtractInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto prefix + } + } + +prefix: + if len(code) <= i { + return Instr{}, 0, false, nil + } + var ( + mapNumber byte + opcode byte + width64 bool + rExt int + rHighExt int + xExt int + bExt int + modRMIndex int + disp8Scale = 1 + evex bool + twoByteVEX bool + prefixValidated bool + ) + switch code[i] { + case 0xc4: + if len(code) < i+4 { + return Instr{}, 0, false, nil + } + mapNumber = code[i+1] & 0x1f + opcode = code[i+3] + width64 = code[i+2]&0x80 != 0 + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + modRMIndex = i + 4 + prefixValidated = code[i+2]&0x7f == 0x79 + case 0xc5: + if len(code) < i+3 { + return Instr{}, 0, false, nil + } + mapNumber = 1 + opcode = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + modRMIndex = i + 3 + twoByteVEX = true + prefixValidated = code[i+1]&0x7f == 0x79 + case 0x62: + if len(code) < i+5 { + return Instr{}, 0, false, nil + } + evex = true + mapNumber = code[i+1] & 0x0f + opcode = code[i+4] + width64 = code[i+2]&0x80 != 0 + rExt = int(^code[i+1]>>7) & 1 + rHighExt = int(^code[i+1]>>4) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + modRMIndex = i + 5 + prefixValidated = code[i+2]&0x7f == 0x7d && code[i+3] == 0x08 + default: + return Instr{}, 0, false, nil + } + + var op Op + laneBytes := 0 + expectedWidth64 := false + switch { + case mapNumber == 3 && opcode == 0x14: + op, laneBytes = "VPEXTRB", 1 + case mapNumber == 3 && opcode == 0x15: + op, laneBytes = "VPEXTRW", 2 + case mapNumber == 3 && opcode == 0x16 && !width64: + op, laneBytes = "VPEXTRD", 4 + case mapNumber == 3 && opcode == 0x16 && width64: + op, laneBytes, expectedWidth64 = "VPEXTRQ", 8, true + case mapNumber == 3 && opcode == 0x17: + op, laneBytes = "VEXTRACTPS", 4 + case mapNumber == 1 && opcode == 0xc5: + op, laneBytes = "VPEXTRW", 2 + default: + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if !prefixValidated { + return Instr{}, 0, true, fmt.Errorf("reserved vvvv, vector length, prefix, or EVEX mask bits are invalid") + } + if width64 != expectedWidth64 { + return Instr{}, 0, true, fmt.Errorf("invalid W bit for %s", op) + } + if evex { + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("EVEX packed scalar extracts are unavailable in 32-bit mode") + } + disp8Scale = laneBytes + } + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + sourceNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && sourceNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended source register in 32-bit mode") + } + destination, consumed, decodeErr := decodedX86RMSource(code[modRMIndex:], mode, bExt, xExt, segment, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + if mapNumber == 1 && destination.Kind != OpReg { + return Instr{}, 0, true, fmt.Errorf("VEX map-1 VPEXTRW requires a GP-register destination") + } + if evex && destination.Kind == OpReg && xExt != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX packed scalar extract destination is outside the GP-register class") + } + if twoByteVEX && destination.Kind == OpReg && bExt != 0 { + return Instr{}, 0, true, fmt.Errorf("two-byte VEX cannot encode an extended destination register") + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + source := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", sourceNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{immediate, source, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, immediate.String(), source.String(), destination.String()), + } + return instruction, immediateIndex + 1, true, nil +} + +// decodedX86VPERMQInstruction recognizes the complete VEX.256 immediate +// VPERMQ Y/m256, Y family. x/arch v0.14 can misclassify its trailing immediate +// as a PC-relative operand, so recover register and ModRM/SIB memory forms +// before consulting the generic decoder. EVEX forms are decoded correctly by +// x/arch and continue through the ordinary path. +func decodedX86VPERMQInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if len(code) < i+4 || code[i] != 0xc4 || code[i+1]&0x1f != 3 || code[i+3] != 0x00 { + return Instr{}, 0, false, nil + } + ok = true + if mode != 32 && mode != 64 { + return Instr{}, 0, true, fmt.Errorf("unsupported x86 mode %d", mode) + } + if code[i+2] != 0xfd { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be one, VEX.vvvv must be 1111, VEX.L must be one, and VEX.pp must be 66") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + vex1 := code[i+1] + rExt := int(^vex1>>7) & 1 + xExt := int(^vex1>>6) & 1 + bExt := int(^vex1>>5) & 1 + modRMIndex := i + 4 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + source, consumed, err := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "Y") + if err != nil { + return Instr{}, 0, true, err + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("Y%d", destinationNumber))} + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + instruction = Instr{ + Op: "VPERMQ", + Args: []Operand{immediate, source, destination}, + Raw: fmt.Sprintf("VPERMQ %s, %s, %s", immediate.String(), source.String(), destination.String()), + } + return instruction, immediateIndex + 1, true, nil +} + +// decodedX86ScalarPrecisionConvertInstruction recognizes the complete +// CVTSS2SD/CVTSD2SS and VCVTSS2SD/VCVTSD2SS family represented by Go 1.27's +// legacy yxm and EVEX-aware _yvaddsd tables. Besides VEX and legacy forms it +// handles EVEX high X registers, memory, masks, zeroing, SAE, and all four +// embedded rounding modes. x/arch v0.14 can split VCVTSD2SS into POP/ROLL. +func decodedX86ScalarPrecisionConvertInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto encoding + } + } + +encoding: + if len(code) <= i { + return Instr{}, 0, false, nil + } + + // Legacy F2/F3 0F 5A /r forms overwrite their X destination. + j := i + if code[j] == 0xf2 || code[j] == 0xf3 { + prefix := code[j] + j++ + rex := byte(0) + if j < len(code) && code[j]&0xf0 == 0x40 { + rex = code[j] + j++ + } + if len(code) >= j+3 && code[j] == 0x0f && code[j+1] == 0x5a { + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 && rex != 0 { + return Instr{}, 0, true, fmt.Errorf("REX prefix in 32-bit mode") + } + op := Op("CVTSD2SS") + if prefix == 0xf3 { + op = "CVTSS2SD" + } + modRMIndex := j + 2 + modRM := code[modRMIndex] + rExt := int(rex>>2) & 1 + xExt := int(rex>>1) & 1 + bExt := int(rex) & 1 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended destination register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + return Instr{Op: op, Args: []Operand{source, destination}, Raw: fmt.Sprintf("%s %s, %s", op, source.String(), destination.String())}, modRMIndex + consumed, true, nil + } + } + + if code[i] == 0xc4 || code[i] == 0xc5 { + var vexLength, rExt, xExt, bExt int + var vexBits, opcode byte + switch code[i] { + case 0xc5: + if len(code) < i+4 { + return Instr{}, 0, false, nil + } + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + opcode = code[i+2] + case 0xc4: + if len(code) < i+5 || code[i+1]&0x1f != 1 { + return Instr{}, 0, false, nil + } + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + opcode = code[i+3] + } + if opcode != 0x5a || (vexBits&3 != 2 && vexBits&3 != 3) { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if vexLength == 3 && vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if vexBits&0x04 != 0 { + return Instr{}, 0, true, fmt.Errorf("scalar precision conversion requires VEX.128") + } + op := Op("VCVTSD2SS") + if vexBits&3 == 2 { + op = "VCVTSS2SD" + } + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + modRM := code[modRMIndex] + first, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondNumber := int(^vexBits>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended VEX register in 32-bit mode") + } + second := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", secondNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + return Instr{Op: op, Args: []Operand{first, second, destination}, Raw: fmt.Sprintf("%s %s, %s, %s", op, first.String(), second.String(), destination.String())}, modRMIndex + consumed, true, nil + } + + if len(code) < i+6 || code[i] != 0x62 || code[i+1]&0x0f != 1 || code[i+4] != 0x5a { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + prefix := p1 & 3 + wBit := p1&0x80 != 0 + op := Op("") + inputBytes := 0 + supportsRounding := false + switch prefix { + case 3: + op = "VCVTSD2SS" + inputBytes = 8 + supportsRounding = true + if !wBit { + return Instr{}, 0, true, fmt.Errorf("VCVTSD2SS requires EVEX.W1") + } + case 2: + op = "VCVTSS2SD" + inputBytes = 4 + if wBit { + return Instr{}, 0, true, fmt.Errorf("VCVTSS2SD requires EVEX.W0") + } + default: + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if p1&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX fixed bit must be one") + } + modRMIndex := i + 5 + modRM := code[modRMIndex] + embeddedControl := p2&0x10 != 0 + vectorBits := p2 >> 5 & 3 + if !embeddedControl && vectorBits != 0 { + return Instr{}, 0, true, fmt.Errorf("scalar precision conversion requires EVEX.128") + } + if embeddedControl && modRM>>6 != 3 { + return Instr{}, 0, true, fmt.Errorf("embedded rounding/SAE requires a register source") + } + if embeddedControl { + if supportsRounding { + op += Op("." + [...]string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"}[vectorBits]) + } else if vectorBits == 0 { + op += ".SAE" + } else { + return Instr{}, 0, true, fmt.Errorf("VCVTSS2SD supports SAE but not explicit rounding") + } + } + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("386 scalar precision conversion mask forms exceed the Go assembler frontend's operand limit") + } + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + first, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X", inputBytes) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + second := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", secondNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + args := []Operand{first, second} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86DuplicateMoveInstruction recognizes every Go 1.27 yxm and +// _yvmovddup encoding for MOVDDUP/MOVSHDUP/MOVSLDUP and their V-prefixed +// forms. This includes legacy X, VEX X/Y, and EVEX X/Y/Z register or memory +// sources with optional merge/zero masks and compressed displacements. +// x/arch v0.14 rejects the VMOVSHDUP bytes generated by segdsp. +func decodedX86DuplicateMoveInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto encoding + } + } + +encoding: + if len(code) <= i { + return Instr{}, 0, false, nil + } + + // Legacy duplicate moves use F2/F3 0F opcode /r and the ModRM.reg X + // register as the destination. + j := i + if code[j] == 0xf2 || code[j] == 0xf3 { + prefix := code[j] + j++ + rex := byte(0) + if j < len(code) && code[j]&0xf0 == 0x40 { + rex = code[j] + j++ + } + if len(code) >= j+3 && code[j] == 0x0f { + op := Op("") + switch { + case prefix == 0xf2 && code[j+1] == 0x12: + op = "MOVDDUP" + case prefix == 0xf3 && code[j+1] == 0x12: + op = "MOVSLDUP" + case prefix == 0xf3 && code[j+1] == 0x16: + op = "MOVSHDUP" + } + if op != "" { + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 && rex != 0 { + return Instr{}, 0, true, fmt.Errorf("REX prefix in 32-bit mode") + } + modRMIndex := j + 2 + modRM := code[modRMIndex] + rExt := int(rex>>2) & 1 + xExt := int(rex>>1) & 1 + bExt := int(rex) & 1 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended destination register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + return Instr{Op: op, Args: []Operand{source, destination}, Raw: fmt.Sprintf("%s %s, %s", op, source.String(), destination.String())}, modRMIndex + consumed, true, nil + } + } + } + + if code[i] == 0xc4 || code[i] == 0xc5 { + var vexLength, rExt, xExt, bExt int + var vexBits, opcode byte + switch code[i] { + case 0xc5: + if len(code) < i+4 { + return Instr{}, 0, false, nil + } + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + opcode = code[i+2] + case 0xc4: + if len(code) < i+5 || code[i+1]&0x1f != 1 { + return Instr{}, 0, false, nil + } + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + opcode = code[i+3] + } + prefix := vexBits & 3 + op := Op("") + switch { + case prefix == 3 && opcode == 0x12: + op = "VMOVDDUP" + case prefix == 2 && opcode == 0x12: + op = "VMOVSLDUP" + case prefix == 2 && opcode == 0x16: + op = "VMOVSHDUP" + } + if op == "" { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if vexLength == 3 && vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if vexBits&0x78 != 0x78 { + return Instr{}, 0, true, fmt.Errorf("VEX.vvvv must be reserved") + } + vectorName := "X" + if vexBits&0x04 != 0 { + vectorName = "Y" + } + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + modRM := code[modRMIndex] + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended VEX register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + return Instr{Op: op, Args: []Operand{source, destination}, Raw: fmt.Sprintf("%s %s, %s", op, source.String(), destination.String())}, modRMIndex + consumed, true, nil + } + + if len(code) < i+6 || code[i] != 0x62 || code[i+1]&0x0f != 1 { + return Instr{}, 0, false, nil + } + p0, p1, p2, opcode := code[i+1], code[i+2], code[i+3], code[i+4] + prefix := p1 & 3 + op := Op("") + elementBytes := 4 + switch { + case prefix == 3 && opcode == 0x12: + op = "VMOVDDUP" + elementBytes = 8 + case prefix == 2 && opcode == 0x12: + op = "VMOVSLDUP" + case prefix == 2 && opcode == 0x16: + op = "VMOVSHDUP" + default: + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if p1&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX fixed bit must be one") + } + double := op == "VMOVDDUP" + if double != (p1&0x80 != 0) { + return Instr{}, 0, true, fmt.Errorf("EVEX.W does not match duplicate-move element width") + } + if p1&0x78 != 0x78 || p2&0x08 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.vvvvv must be reserved") + } + if p2&0x10 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast is absent from Go 1.27's duplicate-move table") + } + vectorBits := p2 >> 5 & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + disp8Scale := vectorWidth + if double && vectorBits == 0 { + disp8Scale = elementBytes + } + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + modRMIndex := i + 5 + modRM := code[modRMIndex] + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + sourceNumber := int(modRM&7) + bExt*8 + xExt*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && vectorName == "Z" { + if modRM>>6 == 3 && sourceNumber >= 8 || destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("high Z register is unavailable in 32-bit mode") + } + } + source, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{source} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86InLaneFloatingPermuteInstruction recognizes every encoding in Go +// 1.27's shared _yvpermilpd table: VPERMILPS/VPERMILPD immediate and +// variable-control VEX X/Y forms plus EVEX X/Y/Z, memory, scalar broadcast, +// merge-mask, and zero-mask forms. x/arch v0.14 can split a VEX immediate form +// into a fake PC-relative branch inside generated segdsp byte streams. +func decodedX86InLaneFloatingPermuteInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto encoding + } + } + +encoding: + if len(code) <= i { + return Instr{}, 0, false, nil + } + if code[i] == 0xc4 { + if len(code) < i+5 { + return Instr{}, 0, false, nil + } + vex0, vexBits, opcode := code[i+1], code[i+2], code[i+3] + mapNumber := vex0 & 0x1f + immediate := mapNumber == 3 && (opcode == 0x04 || opcode == 0x05) + variable := mapNumber == 2 && (opcode == 0x0c || opcode == 0x0d) + if !immediate && !variable { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if immediate && vexBits&0x78 != 0x78 { + return Instr{}, 0, true, fmt.Errorf("immediate VPERMIL requires reserved VEX.vvvv") + } + vectorName := "X" + if vexBits&0x04 != 0 { + vectorName = "Y" + } + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + modRMIndex := i + 4 + modRM := code[modRMIndex] + destinationNumber := int(modRM>>3&7) + rExt*8 + secondNumber := int(^vexBits>>3) & 15 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || destinationNumber >= 8 || variable && secondNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended VEX register in 32-bit mode") + } + first, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + double := opcode&1 != 0 + op := Op("VPERMILPS") + if double { + op = "VPERMILPD" + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := make([]Operand, 0, 3) + end := modRMIndex + consumed + if immediate { + if len(code) <= end { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + args = append(args, Operand{Kind: OpImm, Imm: int64(code[end])}, first, destination) + end++ + } else { + second := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondNumber))} + args = append(args, first, second, destination) + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, end, true, nil + } + + if len(code) < i+6 || code[i] != 0x62 { + return Instr{}, 0, false, nil + } + p0, p1, p2, opcode := code[i+1], code[i+2], code[i+3], code[i+4] + mapNumber := p0 & 0x0f + immediate := mapNumber == 3 && (opcode == 0x04 || opcode == 0x05) + variable := mapNumber == 2 && (opcode == 0x0c || opcode == 0x0d) + if !immediate && !variable { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if p1&0x07 != 5 { + return Instr{}, 0, true, fmt.Errorf("EVEX fixed bit and pp must select 66") + } + double := opcode&1 != 0 + if double != (p1&0x80 != 0) { + return Instr{}, 0, true, fmt.Errorf("EVEX.W does not match VPERMILPS/PD") + } + if immediate && (p1&0x78 != 0x78 || p2&0x08 == 0) { + return Instr{}, 0, true, fmt.Errorf("immediate VPERMIL requires reserved EVEX.vvvvv") + } + vectorBits := p2 >> 5 & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + laneBytes := 4 + op := Op("VPERMILPS") + if double { + laneBytes = 8 + op = "VPERMILPD" + } + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("386 VPERMIL mask forms exceed the Go assembler frontend's operand limit") + } + modRMIndex := i + 5 + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = laneBytes + op += ".BCST" + } + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + firstNumber := int(modRM&7) + bExt*8 + xExt*16 + secondNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && vectorName == "Z" { + if modRM>>6 == 3 && firstNumber >= 8 || variable && secondNumber >= 8 || destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("high Z register is unavailable in 32-bit mode") + } + } + first, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := make([]Operand, 0, 4) + end := modRMIndex + consumed + if immediate { + if len(code) <= end { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + args = append(args, Operand{Kind: OpImm, Imm: int64(code[end])}, first) + end++ + } else { + second := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondNumber))} + args = append(args, first, second) + } + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, end, true, nil +} + +// decodedX86ImmediatePackedBlendInstruction recognizes the complete Go 1.27 +// immediate packed-blend family: legacy PBLENDW/BLENDPS/BLENDPD X forms and +// VEX VPBLENDW/VPBLENDD/VBLENDPS/VBLENDPD X/Y forms. Every register and +// ModRM/SIB memory source is handled before x/arch's generic decoder, which +// can split VBLENDPD into unrelated scalar instructions in generated code. +func decodedX86ImmediatePackedBlendInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto encoding + } + } + +encoding: + if len(code) <= i { + return Instr{}, 0, false, nil + } + + // Legacy 66 0F 3A /r ib encodings use the ModRM.reg X register as both + // their second source and destination. + j := i + if code[j] == 0x66 { + j++ + rex := byte(0) + if j < len(code) && code[j]&0xf0 == 0x40 { + rex = code[j] + j++ + } + if len(code) >= j+4 && code[j] == 0x0f && code[j+1] == 0x3a { + op, recognized := map[byte]Op{0x0c: "BLENDPS", 0x0d: "BLENDPD", 0x0e: "PBLENDW"}[code[j+2]] + if recognized { + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 && rex != 0 { + return Instr{}, 0, true, fmt.Errorf("REX prefix in 32-bit mode") + } + modRMIndex := j + 3 + modRM := code[modRMIndex] + rExt := int(rex>>2) & 1 + xExt := int(rex>>1) & 1 + bExt := int(rex) & 1 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended destination register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + return Instr{ + Op: op, + Args: []Operand{immediate, source, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, immediate.String(), source.String(), destination.String()), + }, immediateIndex + 1, true, nil + } + } + } + + // All vector forms are VEX.128/256.66.0F3A.W0. Go's 386 frontend + // cannot represent their four Plan 9 operands and rejects them. + if len(code) < i+5 || code[i] != 0xc4 || code[i+1]&0x1f != 3 { + return Instr{}, 0, false, nil + } + op, recognized := map[byte]Op{ + 0x02: "VPBLENDD", + 0x0c: "VBLENDPS", + 0x0d: "VBLENDPD", + 0x0e: "VPBLENDW", + }[code[i+3]] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("386 %s exceeds the Go assembler frontend's operand limit", op) + } + vex0, vexBits := code[i+1], code[i+2] + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + vectorName := "X" + if vexBits&0x04 != 0 { + vectorName = "Y" + } + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + modRMIndex := i + 4 + modRM := code[modRMIndex] + first, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + secondNumber := int(^vexBits>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + second := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + return Instr{ + Op: op, + Args: []Operand{immediate, first, second, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s, %s", op, immediate.String(), first.String(), second.String(), destination.String()), + }, immediateIndex + 1, true, nil +} + +// decodedX86FloatingUnpackInstruction recognizes every legacy yxm and +// VEX/EVEX _yvandnpd row used by UNPCKLPS/UNPCKHPS/UNPCKLPD/UNPCKHPD and +// their V-prefixed forms. This includes X/Y/Z widths, register and ModRM/SIB +// memory sources, EVEX broadcast, merge masks, zero masks, and compressed +// displacements. x/arch v0.14 can overrun VUNPCK by one byte and desynchronize +// a raw directive stream, as observed in github.com/racerxdl/segdsp. +func decodedX86FloatingUnpackInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto encoding + } + } + +encoding: + if len(code) <= i { + return Instr{}, 0, false, nil + } + + legacyPrefix := byte(0) + j := i + if code[j] == 0x66 { + legacyPrefix = 1 + j++ + } + rex := byte(0) + if j < len(code) && code[j]&0xf0 == 0x40 { + rex = code[j] + j++ + } + if len(code) >= j+3 && code[j] == 0x0f && (code[j+1] == 0x14 || code[j+1] == 0x15) { + opcode := code[j+1] + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 && rex != 0 { + return Instr{}, 0, true, fmt.Errorf("REX prefix in 32-bit mode") + } + stem := "UNPCKL" + if opcode == 0x15 { + stem = "UNPCKH" + } + op := Op(stem + map[byte]string{0: "PS", 1: "PD"}[legacyPrefix]) + modRMIndex := j + 2 + modRM := code[modRMIndex] + rExt := int(rex>>2) & 1 + xExt := int(rex>>1) & 1 + bExt := int(rex) & 1 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended destination register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + return Instr{ + Op: op, + Args: []Operand{source, destination}, + Raw: fmt.Sprintf("%s %s, %s", op, source.String(), destination.String()), + }, modRMIndex + consumed, true, nil + } + + var vexLength, rExt, xExt, bExt int + var vexBits, opcode byte + switch { + case len(code) >= i+3 && code[i] == 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + opcode = code[i+2] + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + opcode = code[i+3] + } + if vexLength != 0 && (opcode == 0x14 || opcode == 0x15) { + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if vexBits&3 > 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp does not select PS or PD floating unpack") + } + if vexLength == 3 && vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("floating unpack requires VEX.W0") + } + stem := "VUNPCKL" + if opcode == 0x15 { + stem = "VUNPCKH" + } + op := Op(stem + map[byte]string{0: "PS", 1: "PD"}[vexBits&3]) + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorName := "X" + if vexBits&0x04 != 0 { + vectorName = "Y" + } + secondNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended VEX register in 32-bit mode") + } + first, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + second := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + return Instr{ + Op: op, + Args: []Operand{first, second, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, first.String(), second.String(), destination.String()), + }, modRMIndex + consumed, true, nil + } + + if code[i] != 0x62 || len(code) < i+6 || code[i+1]&0x0f != 1 || (code[i+4] != 0x14 && code[i+4] != 0x15) { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p1&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX fixed bit must be one") + } + if p1&3 > 1 { + return Instr{}, 0, true, fmt.Errorf("EVEX.pp does not select PS or PD floating unpack") + } + double := p1&3 == 1 + if double != (p1&0x80 != 0) { + return Instr{}, 0, true, fmt.Errorf("EVEX.W and pp disagree for floating unpack") + } + vectorBits := p2 >> 5 & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorBytes := [...]int{16, 32, 64}[vectorBits] + laneBytes := 4 + suffix := "PS" + if double { + laneBytes = 8 + suffix = "PD" + } + stem := "VUNPCKL" + if code[i+4] == 0x15 { + stem = "VUNPCKH" + } + op := Op(stem + suffix) + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX masking is unavailable for 386 floating unpack forms") + } + + modRMIndex := i + 5 + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + disp8Scale := vectorBytes + if broadcast { + disp8Scale = laneBytes + op += ".BCST" + } + evexRExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + evexXExt := int(^p0>>6) & 1 + evexBExt := int(^p0>>5) & 1 + firstNumber := int(modRM&7) + evexBExt*8 + evexXExt*16 + secondNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + evexRExt*8 + rHighExt*16 + if mode == 32 && vectorName == "Z" { + if modRM>>6 == 3 && firstNumber >= 8 || secondNumber >= 8 || destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("high Z register is unavailable in 32-bit mode") + } + } + first, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, evexBExt, evexXExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + second := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{first, second} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86VEXPackedFloatLogicalInstruction recognizes the complete +// VEX.128/VEX.256 VANDPS/PD, VANDNPS/PD, VORPS/PD, and VXORPS/PD family. +// x/arch v0.14 can split or reject valid VEX encodings, including the raw +// VXORPS emitted by Weaviate, so recover every register and ModRM/SIB memory +// form before the generic decoder. VEX.W is ignored by these opcode rows. +func decodedX86VEXPackedFloatLogicalInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + var vexLength, rExt, xExt, bExt int + var vexBits, opcode byte + switch { + case len(code) >= i+3 && code[i] == 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + opcode = code[i+2] + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + opcode = code[i+3] + default: + return Instr{}, 0, false, nil + } + stem, recognized := map[byte]string{ + 0x54: "VAND", + 0x55: "VANDN", + 0x56: "VOR", + 0x57: "VXOR", + }[opcode] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + suffix := "" + switch vexBits & 3 { + case 0: + suffix = "PS" + case 1: + suffix = "PD" + default: + return Instr{}, 0, true, fmt.Errorf("VEX.pp does not select a packed floating logical instruction") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + firstSource, consumed, err := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if err != nil { + return Instr{}, 0, true, err + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + op := Op(stem + suffix) + instruction = Instr{ + Op: op, + Args: []Operand{firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +// decodedX86VEXPackedIntegerLogicalInstruction recognizes the complete +// VEX.128/VEX.256 VPAND, VPANDN, VPOR, and VPXOR family described by Go +// 1.27's shared _yvaddsubpd operand table. Recover both VEX.WIG values and +// every register and ModRM/SIB memory form before the generic decoder, which +// can split or reject raw encodings emitted by ecosystem assembly. +func decodedX86VEXPackedIntegerLogicalInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + var vexLength, rExt, xExt, bExt int + var vexBits, opcode byte + switch { + case len(code) >= i+3 && code[i] == 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + opcode = code[i+2] + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + opcode = code[i+3] + default: + return Instr{}, 0, false, nil + } + op, recognized := map[byte]Op{ + 0xdb: "VPAND", + 0xdf: "VPANDN", + 0xeb: "VPOR", + 0xef: "VPXOR", + }[opcode] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + firstSource, consumed, err := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if err != nil { + return Instr{}, 0, true, err + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +// decodedX86EVEXPackedLogicalInstruction recognizes every EVEX register, +// memory, broadcast, merge-mask, and zero-mask row shared by Go 1.27's +// VPANDD/Q, VPANDND/Q, VPORD/Q, and VPXORD/Q _yvblendmpd table. +func decodedX86EVEXPackedLogicalInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto evex + } + } + +evex: + if len(code) < i+5 || code[i] != 0x62 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p0&0x0f != 1 || p1&3 != 1 { + return Instr{}, 0, false, nil + } + stem, recognized := map[byte]string{0xdb: "VPAND", 0xdf: "VPANDN", 0xeb: "VPOR", 0xef: "VPXOR"}[code[i+4]] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if p1&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX fixed bit must be one") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vectorBits := p2 >> 5 & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorBytes := [...]int{16, 32, 64}[vectorBits] + width := "D" + laneBytes := 4 + if p1&0x80 != 0 { + width = "Q" + laneBytes = 8 + } + op := Op(stem + width) + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX masking is unavailable for 386 packed logical forms") + } + + modRMIndex := i + 5 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + disp8Scale := vectorBytes + if broadcast { + disp8Scale = laneBytes + op += ".BCST" + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + firstNumber := int(modRM&7) + bExt*8 + xExt*16 + secondNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && vectorName == "Z" { + if modRM>>6 == 3 && firstNumber >= 8 || secondNumber >= 8 || destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("high Z register is unavailable in 32-bit mode") + } + } + first, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + second := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{first, second} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86VEXPackedMADDInstruction recognizes the complete VEX.128 and +// VEX.256 VPMADDWD and VPMADDUBSW family in Go 1.27's opcode tables. +// VPMADDWD is available through both two- and three-byte VEX map-1 forms; +// VPMADDUBSW uses the three-byte VEX map-2 form. VEX.W is ignored. Recover +// every register and ModRM/SIB memory form before the generic decoder, which +// can split raw VPMADDWD bytes emitted by ecosystem assembly. +func decodedX86VEXPackedMADDInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + var vexLength, opcodeMap, rExt, xExt, bExt int + var vexBits, opcode byte + switch { + case len(code) >= i+3 && code[i] == 0xc5: + vexLength = 2 + opcodeMap = 1 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + opcode = code[i+2] + case len(code) >= i+4 && code[i] == 0xc4: + vexLength = 3 + opcodeMap = int(code[i+1] & 0x1f) + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + opcode = code[i+3] + default: + return Instr{}, 0, false, nil + } + op, recognized := map[[2]int]Op{ + {1, 0xf5}: "VPMADDWD", + {2, 0x04}: "VPMADDUBSW", + }[[2]int{opcodeMap, int(opcode)}] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + firstSource, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +// decodedX86VEXBinaryFloatInstruction recognizes the complete VEX and EVEX +// VADD, VMUL, VSUB, VMIN, VDIV, and VMAX family for PS/PD/SS/SD. Scalar VEX +// forms require VEX.128; packed VEX forms accept both vector widths. EVEX adds +// X/Y/Z widths, masking, zeroing, packed broadcasts, rounding, and SAE. +// Recover every register and ModRM/SIB memory form before the generic decoder. +func decodedX86VEXBinaryFloatInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXBinaryFloatInstruction(code, i, mode, segment, addressOverride) + } + var vexLength, rExt, xExt, bExt int + var vexBits, opcode byte + switch { + case len(code) >= i+3 && code[i] == 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + opcode = code[i+2] + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + opcode = code[i+3] + default: + return Instr{}, 0, false, nil + } + stem, recognized := map[byte]string{ + 0x58: "VADD", + 0x59: "VMUL", + 0x5c: "VSUB", + 0x5d: "VMIN", + 0x5e: "VDIV", + 0x5f: "VMAX", + }[opcode] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + pp := vexBits & 3 + suffix := [...]string{"PS", "PD", "SS", "SD"}[pp] + scalar := pp >= 2 + if scalar && vexBits&0x04 != 0 { + return Instr{}, 0, true, fmt.Errorf("scalar binary floating instruction requires VEX.128") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + firstSource, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + op := Op(stem + suffix) + instruction = Instr{ + Op: op, + Args: []Operand{firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +func decodedX86EVEXBinaryFloatInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+6 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + stem, recognized := map[byte]string{ + 0x58: "VADD", + 0x59: "VMUL", + 0x5c: "VSUB", + 0x5d: "VMIN", + 0x5e: "VDIV", + 0x5f: "VMAX", + }[opcode] + if p0&0x0f != 1 || !recognized { + return Instr{}, 0, false, nil + } + ok = true + if p1&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("invalid EVEX prefix") + } + pp := p1 & 3 + width64 := p1&0x80 != 0 + wantWidth64 := pp == 1 || pp == 3 + if width64 != wantWidth64 { + return Instr{}, 0, true, fmt.Errorf("EVEX.W does not match floating element type") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + modRMIndex := i + 5 + modRM := code[modRMIndex] + vectorBits := (p2 >> 5) & 3 + scalar := pp >= 2 + evexB := p2&0x10 != 0 + registerSource := modRM>>6 == 3 + embeddedControl := evexB && registerSource + broadcast := evexB && !registerSource + if broadcast && scalar { + return Instr{}, 0, true, fmt.Errorf("scalar binary floating instruction does not support broadcast") + } + if !embeddedControl && vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + + vectorPrefix := "X" + vectorWidth := 16 + switch { + case embeddedControl && !scalar: + vectorPrefix = "Z" + vectorWidth = 64 + case !scalar: + vectorPrefix = [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth = [...]int{16, 32, 64}[vectorBits] + } + laneBytes := 4 + if pp == 1 || pp == 3 { + laneBytes = 8 + } + disp8Scale := vectorWidth + if scalar || broadcast { + disp8Scale = laneBytes + } + + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && (maskNumber != 0 || rExt != 0 || rHighExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register or mask in 32-bit mode") + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + + suffix := [...]string{"PS", "PD", "SS", "SD"}[pp] + op := Op(stem + suffix) + if broadcast { + op += ".BCST" + } + if embeddedControl { + if stem == "VMIN" || stem == "VMAX" { + op += ".SAE" + } else { + op += [...]Op{".RN_SAE", ".RD_SAE", ".RU_SAE", ".RZ_SAE"}[vectorBits] + } + } + if zeroing { + op += ".Z" + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + args := []Operand{firstSource, secondSource} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86ScalarIntegerFloatInstruction recognizes Go 1.27's complete +// signed and unsigned scalar integer-to-floating-point family. VEX supports +// the four signed forms; EVEX additionally supports unsigned forms, ignored +// scalar L'L encodings, and register-only embedded rounding where enabled. +func decodedX86ScalarIntegerFloatInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto prefix + } + } + +prefix: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXScalarIntegerFloatInstruction(code, i, mode, segment, addressOverride) + } + if len(code) < i+4 { + return Instr{}, 0, false, nil + } + + var vexLength, rExt, xExt, bExt int + var vexBits byte + switch { + case code[i] == 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + case code[i] == 0xc4 && len(code) >= i+5 && code[i+1]&0x1f == 1: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + default: + return Instr{}, 0, false, nil + } + opcodeIndex := i + vexLength + if len(code) <= opcodeIndex || code[opcodeIndex] != 0x2a { + return Instr{}, 0, false, nil + } + ok = true + pp := vexBits & 3 + if pp != 2 && pp != 3 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be F3 or F2") + } + if vexBits&0x04 != 0 { + return Instr{}, 0, true, fmt.Errorf("scalar integer-to-float instruction requires VEX.128") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + passthroughNumber := int(^vexBits>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || passthroughNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86RMSource(code[modRMIndex:], mode, bExt, xExt, segment, 1) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + width64 := vexLength == 3 && vexBits&0x80 != 0 + op := scalarIntegerFloatRawOperation(false, pp, width64) + passthrough := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", passthroughNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + args := []Operand{source, passthrough, destination} + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s, %s, %s", op, source.String(), passthrough.String(), destination.String())}, modRMIndex + consumed, true, nil +} + +func decodedX86EVEXScalarIntegerFloatInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+6 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + if p0&0x0f != 1 || opcode != 0x2a && opcode != 0x7b { + return Instr{}, 0, false, nil + } + ok = true + if p1&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("invalid EVEX prefix") + } + pp := p1 & 3 + if pp != 2 && pp != 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX.pp must be F3 or F2") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if p2&0x87 != 0 { + return Instr{}, 0, true, fmt.Errorf("masking and zeroing are absent from the scalar integer-to-float table") + } + + modRMIndex := i + 5 + modRM := code[modRMIndex] + vectorBits := (p2 >> 5) & 3 + embeddedRounding := p2&0x10 != 0 + if !embeddedRounding && vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + if embeddedRounding && modRM>>6 != 3 { + return Instr{}, 0, true, fmt.Errorf("embedded rounding requires a register source") + } + width64 := p1&0x80 != 0 + roundingEnabled := pp == 2 || width64 + if embeddedRounding && !roundingEnabled { + return Instr{}, 0, true, fmt.Errorf("explicit rounding is absent from VCVTSI2SDL/VCVTUSI2SDL") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + passthroughNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if modRM>>6 == 3 && xExt != 0 { + return Instr{}, 0, true, fmt.Errorf("general register source cannot use the EVEX high vector extension") + } + if mode == 32 && (rExt != 0 || rHighExt != 0 || xExt != 0 || bExt != 0 || passthroughNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + sourceBytes := 4 + if width64 { + sourceBytes = 8 + } + source, consumed, decodeErr := decodedX86RMSource(code[modRMIndex:], mode, bExt, xExt, segment, sourceBytes) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + op := scalarIntegerFloatRawOperation(opcode == 0x7b, pp, width64) + if embeddedRounding { + op += [...]Op{".RN_SAE", ".RD_SAE", ".RU_SAE", ".RZ_SAE"}[vectorBits] + } + passthrough := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", passthroughNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + args := []Operand{source, passthrough, destination} + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s, %s, %s", op, source.String(), passthrough.String(), destination.String())}, modRMIndex + consumed, true, nil +} + +func scalarIntegerFloatRawOperation(unsigned bool, pp byte, width64 bool) Op { + prefix := "VCVTSI2" + if unsigned { + prefix = "VCVTUSI2" + } + result := "SS" + if pp == 3 { + result = "SD" + } + source := "L" + if width64 { + source = "Q" + } + return Op(prefix + result + source) +} + +// decodedX86VectorFloatCompareInstruction recognizes the complete VEX and +// EVEX VCMPPD/PS/SD/SS family. VEX writes X/Y vector results. EVEX writes K +// results and adds an optional K write mask, packed broadcast, and SAE. +func decodedX86VectorFloatCompareInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto prefix + } + } + +prefix: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXVectorFloatCompareInstruction(code, i, mode, segment, addressOverride) + } + if len(code) < i+5 { + return Instr{}, 0, false, nil + } + + var vexLength, rExt, xExt, bExt int + var vexBits byte + switch { + case code[i] == 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + case code[i] == 0xc4 && len(code) >= i+6 && code[i+1]&0x1f == 1: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + default: + return Instr{}, 0, false, nil + } + opcodeIndex := i + vexLength + if len(code) <= opcodeIndex || code[opcodeIndex] != 0xc2 { + return Instr{}, 0, false, nil + } + ok = true + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("vector floating compare is absent from Go's 386 table") + } + if vexLength == 3 && vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + pp := vexBits & 3 + scalar := pp >= 2 + if scalar && vexBits&0x04 != 0 { + return Instr{}, 0, true, fmt.Errorf("scalar vector floating compare requires VEX.128") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + firstSource, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + op := vectorFloatCompareRawOperation(pp) + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + args := []Operand{immediate, firstSource, secondSource, destination} + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s, %s, %s, %s", op, immediate.String(), firstSource.String(), secondSource.String(), destination.String())}, immediateIndex + 1, true, nil +} + +func decodedX86EVEXVectorFloatCompareInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+7 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p0&0x0f != 1 || code[i+4] != 0xc2 { + return Instr{}, 0, false, nil + } + ok = true + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("vector floating compare is absent from Go's 386 table") + } + if p1&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("invalid EVEX prefix") + } + pp := p1 & 3 + width64 := p1&0x80 != 0 + wantWidth64 := pp == 1 || pp == 3 + if width64 != wantWidth64 { + return Instr{}, 0, true, fmt.Errorf("EVEX.W does not match floating element type") + } + if p2&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing is absent from vector floating compare") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + if rExt != 0 || rHighExt != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX destination is an unextended K register") + } + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + modRM := code[modRMIndex] + vectorBits := (p2 >> 5) & 3 + scalar := pp >= 2 + evexB := p2&0x10 != 0 + registerSource := modRM>>6 == 3 + sae := evexB && registerSource + broadcast := evexB && !registerSource + if broadcast && scalar { + return Instr{}, 0, true, fmt.Errorf("scalar vector floating compare does not support broadcast") + } + if !sae && vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + + vectorPrefix := "X" + vectorWidth := 16 + switch { + case sae && !scalar: + vectorPrefix = "Z" + vectorWidth = 64 + case !scalar: + vectorPrefix = [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth = [...]int{16, 32, 64}[vectorBits] + } + laneBytes := 4 + if width64 { + laneBytes = 8 + } + disp8Scale := vectorWidth + if scalar || broadcast { + disp8Scale = laneBytes + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + + op := vectorFloatCompareRawOperation(pp) + if broadcast { + op += ".BCST" + } + if sae { + op += ".SAE" + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", modRM>>3&7))} + args := []Operand{immediate, firstSource, secondSource} + if writeMask := int(p2 & 7); writeMask != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", writeMask))}) + } + args = append(args, destination) + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil +} + +func vectorFloatCompareRawOperation(pp byte) Op { + return [...]Op{"VCMPPS", "VCMPPD", "VCMPSS", "VCMPSD"}[pp] +} + +// decodedX86VEXHorizontalFloatInstruction recognizes the complete VEX.128 and +// VEX.256 VHADDPS/PD and VHSUBPS/PD family in Go 1.27's _yvaddsubpd table. +// VEX.W is ignored. Recover every register and ModRM/SIB memory form before +// the generic decoder, which can misdecode these bytes as relative branches. +func decodedX86VEXHorizontalFloatInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + var vexLength, rExt, xExt, bExt int + var vexBits, opcode byte + switch { + case len(code) >= i+3 && code[i] == 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + opcode = code[i+2] + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + opcode = code[i+3] + default: + return Instr{}, 0, false, nil + } + stem, recognized := map[byte]string{0x7c: "VHADD", 0x7d: "VHSUB"}[opcode] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + suffix := "" + switch vexBits & 3 { + case 1: + suffix = "PD" + case 3: + suffix = "PS" + default: + return Instr{}, 0, true, fmt.Errorf("VEX.pp does not select a horizontal floating instruction") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + firstSource, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + op := Op(stem + suffix) + instruction = Instr{ + Op: op, + Args: []Operand{firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +type decodedX86VEXFMA3Spec struct { + stem string + scalar bool +} + +func (spec decodedX86VEXFMA3Spec) op(width64 bool) Op { + suffix := "PS" + if spec.scalar { + suffix = "SS" + } + if width64 { + if spec.scalar { + suffix = "SD" + } else { + suffix = "PD" + } + } + return Op(spec.stem + suffix) +} + +// decodedX86VEXFMA3Ops covers all 36 packed and 24 scalar FMA3 names in Go +// 1.27's _yvaddpd and _yvaddsd operand tables. VEX.W selects PS/PD or SS/SD. +var decodedX86VEXFMA3Ops = map[byte]decodedX86VEXFMA3Spec{ + 0x96: {stem: "VFMADDSUB132"}, + 0x97: {stem: "VFMSUBADD132"}, + 0x98: {stem: "VFMADD132"}, + 0x99: {stem: "VFMADD132", scalar: true}, + 0x9a: {stem: "VFMSUB132"}, + 0x9b: {stem: "VFMSUB132", scalar: true}, + 0x9c: {stem: "VFNMADD132"}, + 0x9d: {stem: "VFNMADD132", scalar: true}, + 0x9e: {stem: "VFNMSUB132"}, + 0x9f: {stem: "VFNMSUB132", scalar: true}, + 0xa6: {stem: "VFMADDSUB213"}, + 0xa7: {stem: "VFMSUBADD213"}, + 0xa8: {stem: "VFMADD213"}, + 0xa9: {stem: "VFMADD213", scalar: true}, + 0xaa: {stem: "VFMSUB213"}, + 0xab: {stem: "VFMSUB213", scalar: true}, + 0xac: {stem: "VFNMADD213"}, + 0xad: {stem: "VFNMADD213", scalar: true}, + 0xae: {stem: "VFNMSUB213"}, + 0xaf: {stem: "VFNMSUB213", scalar: true}, + 0xb6: {stem: "VFMADDSUB231"}, + 0xb7: {stem: "VFMSUBADD231"}, + 0xb8: {stem: "VFMADD231"}, + 0xb9: {stem: "VFMADD231", scalar: true}, + 0xba: {stem: "VFMSUB231"}, + 0xbb: {stem: "VFMSUB231", scalar: true}, + 0xbc: {stem: "VFNMADD231"}, + 0xbd: {stem: "VFNMADD231", scalar: true}, + 0xbe: {stem: "VFNMSUB231"}, + 0xbf: {stem: "VFNMSUB231", scalar: true}, +} + +// decodedX86VEXFMA3Instruction recognizes every VEX and EVEX FMA3 form behind +// Go 1.27's complete FMA3 table. EVEX adds X/Y/Z widths, masking, zeroing, +// packed broadcasts, and embedded rounding. x/arch v0.14 can split or reject +// raw FMA encodings emitted by generated ecosystem assembly, so recover the +// family before the generic decoder. +func decodedX86VEXFMA3Instruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXFMA3Instruction(code, i, mode, segment, addressOverride) + } + if len(code) < i+5 || code[i] != 0xc4 || code[i+1]&0x1f != 2 { + return Instr{}, 0, false, nil + } + vex0, vexBits, opcode := code[i+1], code[i+2], code[i+3] + spec, recognized := decodedX86VEXFMA3Ops[opcode] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if spec.scalar && vexBits&0x04 != 0 { + return Instr{}, 0, true, fmt.Errorf("scalar FMA3 requires VEX.128") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + modRMIndex := i + 4 + modRM := code[modRMIndex] + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + firstSource, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + op := spec.op(vexBits&0x80 != 0) + instruction = Instr{ + Op: op, + Args: []Operand{firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +func decodedX86EVEXFMA3Instruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+6 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + spec, recognized := decodedX86VEXFMA3Ops[opcode] + if p0&0x0f != 2 || !recognized { + return Instr{}, 0, false, nil + } + ok = true + if p1&0x04 == 0 || p1&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("EVEX.pp must be 66") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + modRMIndex := i + 5 + modRM := code[modRMIndex] + vectorBits := (p2 >> 5) & 3 + evexB := p2&0x10 != 0 + registerSource := modRM>>6 == 3 + embeddedRounding := evexB && registerSource + broadcast := evexB && !registerSource + if broadcast && spec.scalar { + return Instr{}, 0, true, fmt.Errorf("scalar FMA3 does not support broadcast") + } + if !embeddedRounding && vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + + vectorPrefix := "X" + vectorWidth := 16 + switch { + case embeddedRounding && !spec.scalar: + vectorPrefix = "Z" + vectorWidth = 64 + case !spec.scalar: + vectorPrefix = [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth = [...]int{16, 32, 64}[vectorBits] + } + laneBytes := 4 + width64 := p1&0x80 != 0 + if width64 { + laneBytes = 8 + } + disp8Scale := vectorWidth + if spec.scalar || broadcast { + disp8Scale = laneBytes + } + + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && (maskNumber != 0 || rExt != 0 || rHighExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register or mask in 32-bit mode") + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + + op := spec.op(width64) + if broadcast { + op += ".BCST" + } + if embeddedRounding { + op += [...]Op{".RN_SAE", ".RD_SAE", ".RU_SAE", ".RZ_SAE"}[vectorBits] + } + if zeroing { + op += ".Z" + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + args := []Operand{firstSource, secondSource} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86VEXTRACT128Instruction recognizes the complete Go 1.27 vector +// lane-extract family: the VEX F128/I128 forms and all EVEX F/I 32/64-bit +// 128/256-bit block forms. x/arch v0.14 can misdecode these raw bytes as +// PC-relative control flow or reject the EVEX encodings outright. +func decodedX86VEXTRACT128Instruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXTRACTInstruction(code, i, mode, segment, addressOverride) + } + if len(code) < i+6 || code[i] != 0xc4 || code[i+1]&0x1f != 3 { + return Instr{}, 0, false, nil + } + vex0, vexBits, opcode := code[i+1], code[i+2], code[i+3] + op, recognized := map[byte]Op{0x19: "VEXTRACTF128", 0x39: "VEXTRACTI128"}[opcode] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if vexBits&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("VEXTRACT128 requires VEX.256") + } + if int(^vexBits>>3)&15 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.vvvv must be 1111") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + modRMIndex := i + 4 + modRM := code[modRMIndex] + sourceNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || sourceNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + destination, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + source := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("Y%d", sourceNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{immediate, source, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, immediate.String(), source.String(), destination.String()), + } + return instruction, immediateIndex + 1, true, nil +} + +func decodedX86EVEXTRACTInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+5 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p0&0x0f != 3 || p1&0x07 != 5 { + return Instr{}, 0, false, nil + } + opcode := code[i+4] + width64 := p1&0x80 != 0 + outputBytes := 0 + op := Op("") + switch opcode { + case 0x19: + outputBytes = 16 + op = "VEXTRACTF32X4" + if width64 { + op = "VEXTRACTF64X2" + } + case 0x1b: + outputBytes = 32 + op = "VEXTRACTF32X8" + if width64 { + op = "VEXTRACTF64X4" + } + case 0x39: + outputBytes = 16 + op = "VEXTRACTI32X4" + if width64 { + op = "VEXTRACTI64X2" + } + case 0x3b: + outputBytes = 32 + op = "VEXTRACTI32X8" + if width64 { + op = "VEXTRACTI64X4" + } + default: + return Instr{}, 0, false, nil + } + ok = true + if p1&0x78 != 0x78 || p2&0x08 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.vvvv must be reserved") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if p2&0x10 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.b is unavailable for vector extract") + } + vectorBits := (p2 >> 5) & 3 + if outputBytes == 16 && vectorBits != 1 && vectorBits != 2 { + return Instr{}, 0, true, fmt.Errorf("128-bit extract requires a 256- or 512-bit source") + } + if outputBytes == 32 && vectorBits != 2 { + return Instr{}, 0, true, fmt.Errorf("256-bit extract requires a 512-bit source") + } + sourceName := [...]string{"", "Y", "Z"}[vectorBits] + destinationName := "X" + if outputBytes == 32 { + destinationName = "Y" + } + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + if zeroing && modRM>>6 != 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing is invalid for a memory destination") + } + sourceNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + destinationNumber := int(modRM&7) + bExt*8 + xExt*16 + if mode == 32 && (sourceNumber >= 8 || modRM>>6 == 3 && destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + destination, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, destinationName, outputBytes) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + source := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", sourceName, sourceNumber))} + args := []Operand{immediate, source} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil +} + +// decodedX86VSHUFPSInstruction recognizes Go 1.27's complete shared +// VSHUFPS/VSHUFPD operand table. x/arch v0.14 rejects some extended VEX +// encodings and all EVEX forms used by generated ecosystem assembly. +func decodedX86VSHUFPSInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXPackedFloatShuffleInstruction(code, i, mode, segment, addressOverride) + } + var vexLength, rExt, xExt, bExt int + var vexBits byte + switch { + case len(code) >= i+3 && code[i] == 0xc5 && code[i+2] == 0xc6: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1 && code[i+3] == 0xc6: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + default: + return Instr{}, 0, false, nil + } + ok = true + if vexLength == 3 && vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + op := Op("") + switch vexBits & 3 { + case 0: + op = "VSHUFPS" + case 1: + op = "VSHUFPD" + default: + return Instr{}, 0, true, fmt.Errorf("VEX.pp does not select VSHUFPS or VSHUFPD") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + firstSource, consumed, err := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if err != nil { + return Instr{}, 0, true, err + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{immediate, firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s, %s", op, immediate.String(), firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, immediateIndex + 1, true, nil +} + +func decodedX86EVEXPackedFloatShuffleInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+7 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p0&0x0f != 1 || p1&0x04 == 0 || code[i+4] != 0xc6 { + return Instr{}, 0, false, nil + } + op := Op("") + switch { + case p1&3 == 0 && p1&0x80 == 0: + op = "VSHUFPS" + case p1&3 == 1 && p1&0x80 != 0: + op = "VSHUFPD" + default: + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorPrefix := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = 4 + if op == "VSHUFPD" { + disp8Scale = 8 + } + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + args := []Operand{immediate, firstSource, secondSource} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil +} + +// decodedX86PackedShuffleInstruction recognizes the complete Go 1.27 +// _yvpshufd family: VPSHUFD, VPSHUFHW, and VPSHUFLW across VEX.128, +// VEX.256, and EVEX.128/256/512, including memory, mask, zeroing, and the +// VPSHUFD broadcast forms. x/arch v0.14 can split the VEX bytes emitted by +// Weaviate into a relative branch, so recover the family before consulting +// the generic decoder. +func decodedX86PackedShuffleInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vectorPrefix + } + } + +vectorPrefix: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXPackedShuffleInstruction(code, i, mode, segment, addressOverride) + } + + var vexLength, rExt, xExt, bExt int + var vexBits byte + switch { + case len(code) >= i+3 && code[i] == 0xc5 && code[i+2] == 0x70: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1 && code[i+3] == 0x70: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + default: + return Instr{}, 0, false, nil + } + op := map[byte]Op{1: "VPSHUFD", 2: "VPSHUFHW", 3: "VPSHUFLW"}[vexBits&3] + if op == "" { + return Instr{}, 0, false, nil + } + ok = true + if vexBits&0x78 != 0x78 { + return Instr{}, 0, true, fmt.Errorf("VEX.vvvv must be reserved") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorName := "X" + if vexBits&0x04 != 0 { + vectorName = "Y" + } + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{immediate, source, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, immediate.String(), source.String(), destination.String()), + } + return instruction, immediateIndex + 1, true, nil +} + +func decodedX86EVEXPackedShuffleInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+5 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p0&0x0f != 1 || p1&0x04 == 0 || code[i+4] != 0x70 { + return Instr{}, 0, false, nil + } + op := map[byte]Op{1: "VPSHUFD", 2: "VPSHUFHW", 3: "VPSHUFLW"}[p1&3] + if op == "" || op == "VPSHUFD" && p1&0x80 != 0 { + return Instr{}, 0, false, nil + } + ok = true + if p1&0x78 != 0x78 || p2&0x08 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.vvvv must be reserved") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("386 packed shuffle mask form exceeds the Go assembler frontend's operand limit") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && op != "VPSHUFD" { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast is only available for VPSHUFD") + } + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = 4 + } + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && (destinationNumber >= 8 || modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{immediate, source} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil +} + +// decodedX86Shuffle128BitBlocksInstruction recognizes the complete EVEX-only +// Go 1.27 _yvshuff32x4 family: VSHUFF32X4, VSHUFF64X2, VSHUFI32X4, and +// VSHUFI64X2. x/arch v0.14 rejects these raw encodings, including the +// VSHUFF64X2 sequence in github.com/minio/sha256-simd. +func decodedX86Shuffle128BitBlocksInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto evex + } + } + +evex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+7 || code[i] != 0x62 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + if p0&0x0f != 3 || p1&0x07 != 5 || opcode != 0x23 && opcode != 0x43 { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vectorBits := (p2 >> 5) & 3 + if vectorBits != 1 && vectorBits != 2 { + return Instr{}, 0, true, fmt.Errorf("VSHUFF/VSHUFI block shuffle requires a 256- or 512-bit vector") + } + vectorPrefix := [...]string{"", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{0, 32, 64}[vectorBits] + width64 := p1&0x80 != 0 + op := Op("VSHUFF32X4") + laneBytes := 4 + if opcode == 0x43 { + op = "VSHUFI32X4" + } + if width64 { + laneBytes = 8 + if opcode == 0x23 { + op = "VSHUFF64X2" + } else { + op = "VSHUFI64X2" + } + } + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = laneBytes + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + args := []Operand{immediate, firstSource, secondSource} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil +} + +// decodedX86VPSHUFBInstruction recognizes every VEX and EVEX encoding behind +// Go 1.27's _yvandnpd table. x/arch v0.14 rejects the EVEX forms used by +// github.com/minio/sha256-simd. +func decodedX86VPSHUFBInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vectorPrefix + } + } + +vectorPrefix: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+4 { + return Instr{}, 0, false, nil + } + if code[i] == 0xc4 && code[i+1]&0x1f == 2 && code[i+3] == 0x00 { + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vex0, vex1 := code[i+1], code[i+2] + if vex1&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vex1&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if len(code) <= i+4 { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + vectorName := "X" + if vex1&0x04 != 0 { + vectorName = "Y" + } + modRMIndex := i + 4 + modRM := code[modRMIndex] + dataNumber := int(^vex1>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (dataNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + control, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + data := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, dataNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + return Instr{ + Op: "VPSHUFB", + Args: []Operand{control, data, destination}, + Raw: fmt.Sprintf("VPSHUFB %s, %s, %s", control.String(), data.String(), destination.String()), + }, modRMIndex + consumed, true, nil + } + + if len(code) < i+5 || code[i] != 0x62 || code[i+1]&0x0f != 2 || code[i+2]&0x07 != 5 || code[i+4] != 0x00 { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p1&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.W must be zero") + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + if p2&0x10 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.b is unavailable for VPSHUFB") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("386 VPSHUFB mask form exceeds the Go assembler frontend's operand limit") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + dataNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && (dataNumber >= 8 || destinationNumber >= 8 || modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + control, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, vectorWidth) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + data := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, dataNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{control, data} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + op := Op("VPSHUFB") + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +type decodedX86PackedExtendProperties struct { + op Op + inputBits int + outputBits int +} + +func decodedX86PackedExtendOpcode(opcode byte) (decodedX86PackedExtendProperties, bool) { + properties := map[byte]decodedX86PackedExtendProperties{ + 0x20: {op: "VPMOVSXBW", inputBits: 8, outputBits: 16}, + 0x21: {op: "VPMOVSXBD", inputBits: 8, outputBits: 32}, + 0x22: {op: "VPMOVSXBQ", inputBits: 8, outputBits: 64}, + 0x23: {op: "VPMOVSXWD", inputBits: 16, outputBits: 32}, + 0x24: {op: "VPMOVSXWQ", inputBits: 16, outputBits: 64}, + 0x25: {op: "VPMOVSXDQ", inputBits: 32, outputBits: 64}, + 0x30: {op: "VPMOVZXBW", inputBits: 8, outputBits: 16}, + 0x31: {op: "VPMOVZXBD", inputBits: 8, outputBits: 32}, + 0x32: {op: "VPMOVZXBQ", inputBits: 8, outputBits: 64}, + 0x33: {op: "VPMOVZXWD", inputBits: 16, outputBits: 32}, + 0x34: {op: "VPMOVZXWQ", inputBits: 16, outputBits: 64}, + 0x35: {op: "VPMOVZXDQ", inputBits: 32, outputBits: 64}, + }[opcode] + return properties, properties.op != "" +} + +// decodedX86PackedExtendInstruction recognizes all six signed and all six +// unsigned packed extending moves in Go 1.27. It covers their VEX.128/256 and +// EVEX.128/256/512 register and memory forms, including high registers, +// writemasks, zeroing, and compressed displacements. EVEX.b is deliberately +// rejected because no broadcast form exists in the Go operand tables. +func decodedX86PackedExtendInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vectorPrefix + } + } + +vectorPrefix: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXPackedExtendInstruction(code, i, mode, segment, addressOverride) + } + if len(code) < i+4 || code[i] != 0xc4 || code[i+1]&0x1f != 2 { + return Instr{}, 0, false, nil + } + vex0, vex1 := code[i+1], code[i+2] + properties, recognized := decodedX86PackedExtendOpcode(code[i+3]) + if !recognized || vex1&3 != 1 || vex1&0x80 != 0 { + return Instr{}, 0, false, nil + } + ok = true + if vex1&0x78 != 0x78 { + return Instr{}, 0, true, fmt.Errorf("VEX.vvvv must be reserved") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + modRMIndex := i + 4 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (destinationNumber >= 8 || code[modRMIndex]>>6 == 3 && int(code[modRMIndex]&7)+bExt*8 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + destinationName := "X" + if vex1&0x04 != 0 { + destinationName = "Y" + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", destinationName, destinationNumber))} + instruction = Instr{ + Op: properties.op, + Args: []Operand{source, destination}, + Raw: fmt.Sprintf("%s %s, %s", properties.op, source.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +func decodedX86EVEXPackedExtendInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+5 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p0&0x0f != 2 || p1&0x07 != 5 { + return Instr{}, 0, false, nil + } + properties, recognized := decodedX86PackedExtendOpcode(code[i+4]) + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if p1&0x78 != 0x78 || p2&0x08 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.vvvv must be reserved") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if p2&0x10 != 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.b is unavailable for packed extending moves") + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + destinationName := [...]string{"X", "Y", "Z"}[vectorBits] + destinationBytes := [...]int{16, 32, 64}[vectorBits] + sourceBytes := destinationBytes * properties.inputBits / properties.outputBits + sourceName := "X" + if sourceBytes > 16 { + sourceName = "Y" + } + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + sourceNumber := int(modRM&7) + bExt*8 + xExt*16 + if mode == 32 && (destinationNumber >= 8 || modRM>>6 == 3 && sourceNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, sourceName, sourceBytes) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", destinationName, destinationNumber))} + args := []Operand{source} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + op := properties.op + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +type decodedX86PackedLogicalShiftProperties struct { + op Op + laneBytes int + immediate bool +} + +func decodedX86PackedLogicalShiftOpcode(opcode, modRM byte) (decodedX86PackedLogicalShiftProperties, bool) { + laneBytes := map[byte]int{0x71: 2, 0x72: 4, 0x73: 8}[opcode] + if laneBytes != 0 { + direction := modRM >> 3 & 7 + if direction != 2 && direction != 6 { + return decodedX86PackedLogicalShiftProperties{}, false + } + stem := "VPSRL" + if direction == 6 { + stem = "VPSLL" + } + suffix := map[int]string{2: "W", 4: "D", 8: "Q"}[laneBytes] + return decodedX86PackedLogicalShiftProperties{op: Op(stem + suffix), laneBytes: laneBytes, immediate: true}, true + } + variable := map[byte]struct { + op Op + laneBytes int + }{ + 0xf1: {op: "VPSLLW", laneBytes: 2}, + 0xf2: {op: "VPSLLD", laneBytes: 4}, + 0xf3: {op: "VPSLLQ", laneBytes: 8}, + 0xd1: {op: "VPSRLW", laneBytes: 2}, + 0xd2: {op: "VPSRLD", laneBytes: 4}, + 0xd3: {op: "VPSRLQ", laneBytes: 8}, + } + properties, ok := variable[opcode] + if !ok { + return decodedX86PackedLogicalShiftProperties{}, false + } + return decodedX86PackedLogicalShiftProperties{op: properties.op, laneBytes: properties.laneBytes}, true +} + +// decodedX86PackedLogicalShiftInstruction recognizes every immediate and +// XMM/m128 uniform-count encoding in Go 1.27's _yvpslld table for the six +// logical left/right W/D/Q shifts. x/arch v0.14 rejects the EVEX forms used by +// github.com/minio/sha256-simd. +func decodedX86PackedLogicalShiftInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vectorPrefix + } + } + +vectorPrefix: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+4 { + return Instr{}, 0, false, nil + } + + var vexBits byte + var opcodeIndex, modRMIndex, rExt, xExt, bExt int + isVEX := false + vexHasW := false + switch { + case code[i] == 0xc5: + vexBits = code[i+1] + opcodeIndex = i + 2 + modRMIndex = i + 3 + rExt = int(^vexBits>>7) & 1 + isVEX = true + case len(code) >= i+5 && code[i] == 0xc4 && code[i+1]&0x1f == 1: + vex0 := code[i+1] + vexBits = code[i+2] + opcodeIndex = i + 3 + modRMIndex = i + 4 + rExt = int(^vex0>>7) & 1 + xExt = int(^vex0>>6) & 1 + bExt = int(^vex0>>5) & 1 + isVEX = true + vexHasW = true + } + if isVEX { + properties, recognized := decodedX86PackedLogicalShiftOpcode(code[opcodeIndex], code[modRMIndex]) + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexHasW && vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + vectorName := "X" + if vexBits&0x04 != 0 { + vectorName = "Y" + } + modRM := code[modRMIndex] + vvvvNumber := int(^vexBits>>3) & 15 + if properties.immediate { + if mode == 32 && vvvvNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, vvvvNumber))} + return Instr{ + Op: properties.op, + Args: []Operand{immediate, source, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", properties.op, immediate.String(), source.String(), destination.String()), + }, immediateIndex + 1, true, nil + } + + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (vvvvNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + count, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X") + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + data := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, vvvvNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + return Instr{ + Op: properties.op, + Args: []Operand{count, data, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", properties.op, count.String(), data.String(), destination.String()), + }, modRMIndex + consumed, true, nil + } + + if len(code) < i+6 || code[i] != 0x62 || code[i+1]&0x0f != 1 || code[i+2]&0x07 != 5 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + modRMIndex = i + 5 + modRM := code[modRMIndex] + properties, recognized := decodedX86PackedLogicalShiftOpcode(code[i+4], modRM) + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if (p1&0x80 != 0) != (properties.laneBytes == 8) { + return Instr{}, 0, true, fmt.Errorf("EVEX.W does not match %s", properties.op) + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("386 %s mask form exceeds the Go assembler frontend's operand limit", properties.op) + } + + rExt = int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt = int(^p0>>6) & 1 + bExt = int(^p0>>5) & 1 + vvvvNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + broadcast := p2&0x10 != 0 + if properties.immediate { + if p0&0x90 != 0x90 { + return Instr{}, 0, true, fmt.Errorf("EVEX.R and EVEX.R' must not extend the shift opcode selector") + } + if broadcast && properties.laneBytes == 2 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast is unavailable for %s", properties.op) + } + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + if mode == 32 && (vvvvNumber >= 8 || modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = properties.laneBytes + } + source, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, vvvvNumber))} + args := []Operand{immediate, source} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + op := properties.op + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil + } + + if broadcast { + return Instr{}, 0, true, fmt.Errorf("EVEX.b is unavailable for the uniform-count form of %s", properties.op) + } + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && (vvvvNumber >= 8 || destinationNumber >= 8 || modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + count, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "X", 16) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + data := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, vvvvNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{count, data} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + op := properties.op + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86TernaryLogicInstruction recognizes VPTERNLOGD/Q across the +// complete Go 1.27 _yvalignd table. x/arch v0.14 rejects the EVEX encodings +// used by github.com/minio/sha256-simd. +func decodedX86TernaryLogicInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + return decodedX86EVEXImmediateThreeVectorInstruction(code, mode, 0x25, "VPTERNLOGD", "VPTERNLOGQ", "VPTERNLOG") +} + +// decodedX86VectorAlignInstruction recognizes VALIGND/Q across the complete +// Go 1.27 _yvalignd table. +func decodedX86VectorAlignInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + return decodedX86EVEXImmediateThreeVectorInstruction(code, mode, 0x03, "VALIGND", "VALIGNQ", "VALIGN") +} + +// decodedX86FunnelShiftInstruction recognizes the complete Go 1.27 VBMI2 +// funnel-shift family: immediate/variable, left/right, and W/D/Q lanes. +// x/arch v0.14 rejects all of these EVEX encodings. +func decodedX86FunnelShiftInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto evex + } + } + +evex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+6 || code[i] != 0x62 || code[i+2]&0x07 != 5 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + mapNumber := p0 & 0x0f + variable := false + switch mapNumber { + case 2: + variable = true + case 3: + default: + return Instr{}, 0, false, nil + } + opcode := code[i+4] + wBit := p1&0x80 != 0 + laneBits := 0 + left := false + switch opcode { + case 0x70: + left, laneBits = true, 16 + case 0x71: + left = true + if wBit { + laneBits = 64 + } else { + laneBits = 32 + } + case 0x72: + laneBits = 16 + case 0x73: + if wBit { + laneBits = 64 + } else { + laneBits = 32 + } + default: + return Instr{}, 0, false, nil + } + ok = true + if laneBits == 16 && !wBit { + return Instr{}, 0, true, fmt.Errorf("EVEX.W must be one for word funnel shifts") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if !variable && mode == 32 { + return Instr{}, 0, true, fmt.Errorf("386 immediate funnel shifts exceed the Go assembler frontend's operand limit") + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if variable && mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("386 variable funnel-shift mask form exceeds the Go assembler frontend's operand limit") + } + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && laneBits == 16 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast is unavailable for word funnel shifts") + } + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && (secondSourceNumber >= 8 || destinationNumber >= 8 || modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = laneBits / 8 + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + opDirection := "R" + if left { + opDirection = "L" + } + laneSuffix := map[int]string{16: "W", 32: "D", 64: "Q"}[laneBits] + op := Op("VPSH" + opDirection + "D") + if variable { + op += "V" + } + op += Op(laneSuffix) + args := make([]Operand, 0, 5) + end := modRMIndex + consumed + if !variable { + if len(code) <= end { + return Instr{}, 0, false, nil + } + args = append(args, Operand{Kind: OpImm, Imm: int64(code[end])}) + end++ + } + args = append(args, firstSource, secondSource) + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, end, true, nil +} + +// decodedX86EVEXImmediateThreeVectorInstruction implements the EVEX immediate, +// r/m, vvvv, destination shape shared by Go 1.27's _yvalignd families. +func decodedX86EVEXImmediateThreeVectorInstruction(code []byte, mode int, opcode byte, dwordOp, qwordOp Op, family string) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto evex + } + } + +evex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+7 || code[i] != 0x62 || code[i+1]&0x0f != 3 || code[i+2]&0x07 != 5 || code[i+4] != opcode { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if mode == 32 { + return Instr{}, 0, true, fmt.Errorf("386 %s is rejected by the Go assembler frontend's operand limit", family) + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + laneBytes := 4 + op := dwordOp + if p1&0x80 != 0 { + laneBytes = 8 + op = qwordOp + } + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = laneBytes + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{immediate, firstSource, secondSource} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil +} + +// decodedX86PackedImmediateRotateInstruction recognizes all four EVEX +// immediate rotates in Go 1.27's _yvprold table. x/arch v0.14 rejects these +// raw encodings, including VPRORD in github.com/minio/sha256-simd. +func decodedX86PackedImmediateRotateInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto evex + } + } + +evex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+7 || code[i] != 0x62 || code[i+1]&0x0f != 1 || code[i+2]&0x07 != 5 || code[i+4] != 0x72 { + return Instr{}, 0, false, nil + } + modRMIndex := i + 5 + modRM := code[modRMIndex] + selector := modRM >> 3 & 7 + if selector != 0 && selector != 1 { + // Opcode 72 is a grouped encoding. Selectors /2 and /6 are the + // VPSRL/VPSLL logical-shift family, and other selectors may belong to + // decoders added later. This decoder only owns the rotate selectors. + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p0&0x90 != 0x90 { + return Instr{}, 0, true, fmt.Errorf("EVEX.R and EVEX.R' must not extend the rotate opcode selector") + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + laneBytes := 4 + left := false + switch selector { + case 0: + case 1: + left = true + } + op := Op("VPRORD") + if left { + op = "VPROLD" + } + if p1&0x80 != 0 { + laneBytes = 8 + if left { + op = "VPROLQ" + } else { + op = "VPRORQ" + } + } + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("386 %s mask form exceeds the Go assembler frontend's operand limit", op) + } + + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + broadcast := p2&0x10 != 0 + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + destinationNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + if mode == 32 && (destinationNumber >= 8 || modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = laneBytes + } + source, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{immediate, source} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, immediateIndex + 1, true, nil +} + +var decodedX86PackedIntegerArithmeticOps = map[byte]struct { + op Op + laneBytes int +}{ + 0xfc: {op: "VPADDB", laneBytes: 1}, + 0xfd: {op: "VPADDW", laneBytes: 2}, + 0xfe: {op: "VPADDD", laneBytes: 4}, + 0xd4: {op: "VPADDQ", laneBytes: 8}, + 0xec: {op: "VPADDSB", laneBytes: 1}, + 0xed: {op: "VPADDSW", laneBytes: 2}, + 0xdc: {op: "VPADDUSB", laneBytes: 1}, + 0xdd: {op: "VPADDUSW", laneBytes: 2}, + 0xf8: {op: "VPSUBB", laneBytes: 1}, + 0xf9: {op: "VPSUBW", laneBytes: 2}, + 0xfa: {op: "VPSUBD", laneBytes: 4}, + 0xfb: {op: "VPSUBQ", laneBytes: 8}, + 0xe8: {op: "VPSUBSB", laneBytes: 1}, + 0xe9: {op: "VPSUBSW", laneBytes: 2}, + 0xd8: {op: "VPSUBUSB", laneBytes: 1}, + 0xd9: {op: "VPSUBUSW", laneBytes: 2}, +} + +// decodedX86PackedIntegerArithmeticInstruction recognizes the complete +// VEX/EVEX VPADD and VPSUB families behind Go 1.27's shared _yvandnpd table. +// x/arch v0.14 rejects EVEX forms and can split VEX forms used by ecosystem +// assembly. +func decodedX86PackedIntegerArithmeticInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vectorPrefix + } + } + +vectorPrefix: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+3 { + return Instr{}, 0, false, nil + } + + var vexBits byte + var opcodeIndex, modRMIndex, rExt, xExt, bExt int + isVEX := false + switch { + case code[i] == 0xc5: + vexBits = code[i+1] + opcodeIndex = i + 2 + modRMIndex = i + 3 + rExt = int(^vexBits>>7) & 1 + isVEX = true + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1: + vex0 := code[i+1] + vexBits = code[i+2] + opcodeIndex = i + 3 + modRMIndex = i + 4 + rExt = int(^vex0>>7) & 1 + xExt = int(^vex0>>6) & 1 + bExt = int(^vex0>>5) & 1 + isVEX = true + } + if isVEX { + properties, recognized := decodedX86PackedIntegerArithmeticOps[code[opcodeIndex]] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorName := "X" + if vexBits&0x04 != 0 { + vectorName = "Y" + } + modRM := code[modRMIndex] + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + firstSource, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + return Instr{ + Op: properties.op, + Args: []Operand{firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", properties.op, firstSource.String(), secondSource.String(), destination.String()), + }, modRMIndex + consumed, true, nil + } + + if len(code) < i+5 || code[i] != 0x62 || code[i+1]&0x0f != 1 || code[i+2]&0x07 != 5 { + return Instr{}, 0, false, nil + } + properties, recognized := decodedX86PackedIntegerArithmeticOps[code[i+4]] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + wBit := p1&0x80 != 0 + if wBit != (properties.laneBytes == 8) { + return Instr{}, 0, true, fmt.Errorf("EVEX.W does not match %s", properties.op) + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("386 %s mask form exceeds the Go assembler frontend's operand limit", properties.op) + } + + rExt = int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt = int(^p0>>6) & 1 + bExt = int(^p0>>5) & 1 + modRMIndex = i + 5 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && properties.laneBytes != 4 && properties.laneBytes != 8 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast is unavailable for %s", properties.op) + } + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && (secondSourceNumber >= 8 || destinationNumber >= 8 || modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = properties.laneBytes + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{firstSource, secondSource} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + op := properties.op + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86VPERMI2Instruction recognizes the complete EVEX-only family +// behind Go 1.27's shared _yvblendmpd table. x/arch v0.14 rejects these raw +// encodings, including VPERMI2Q in github.com/minio/sha256-simd. +func decodedX86VPERMI2Instruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto evex + } + } + +evex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+6 || code[i] != 0x62 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + if p0&0x0f != 2 || p1&0x07 != 5 || opcode < 0x75 || opcode > 0x77 { + return Instr{}, 0, false, nil + } + width64 := p1&0x80 != 0 + op := Op("") + laneBytes := 0 + switch opcode { + case 0x75: + if width64 { + op, laneBytes = "VPERMI2W", 2 + } else { + op, laneBytes = "VPERMI2B", 1 + } + case 0x76: + if width64 { + op, laneBytes = "VPERMI2Q", 8 + } else { + op, laneBytes = "VPERMI2D", 4 + } + case 0x77: + if width64 { + op, laneBytes = "VPERMI2PD", 8 + } else { + op, laneBytes = "VPERMI2PS", 4 + } + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorPrefix := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && laneBytes < 4 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast is unavailable for byte and word VPERMI2") + } + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = laneBytes + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + args := []Operand{firstSource, secondSource} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86IFMAInstruction recognizes the complete EVEX-only +// VPMADD52HUQ/LUQ family behind Go 1.27's _yvblendmpd table. x/arch v0.14 +// rejects these encodings. +func decodedX86IFMAInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto evex + } + } + +evex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+6 || code[i] != 0x62 || code[i+1]&0x0f != 2 || code[i+2]&0x07 != 5 { + return Instr{}, 0, false, nil + } + op := Op("") + switch code[i+4] { + case 0xb4: + op = "VPMADD52LUQ" + case 0xb5: + op = "VPMADD52HUQ" + default: + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p1&0x80 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.W must be one for %s", op) + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + if mode == 32 && maskNumber != 0 { + return Instr{}, 0, true, fmt.Errorf("386 %s mask form exceeds the Go assembler frontend's operand limit", op) + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && (secondSourceNumber >= 8 || destinationNumber >= 8 || modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = 8 + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{firstSource, secondSource} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} + +// decodedX86VPINSRInstruction recognizes the complete VEX.128 VPINSR +// byte/word/dword/qword family, including two- and three-byte VEX encodings and +// every ModRM/SIB source. x/arch v0.14 rejects some extended-register VPINSRQ +// forms used by generated crypto assembly. EVEX forms continue through x/arch. +func decodedX86VPINSRInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + var vexLength, rExt, xExt, bExt int + var vexBits byte + op := Op("") + switch { + case len(code) >= i+3 && code[i] == 0xc5 && code[i+2] == 0xc4: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + op = "VPINSRW" + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1 && code[i+3] == 0xc4: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + op = "VPINSRW" + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 3 && code[i+3] == 0x20: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + op = "VPINSRB" + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 3 && code[i+3] == 0x22: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + op = "VPINSRD" + if vexBits&0x80 != 0 { + op = "VPINSRQ" + } + default: + return Instr{}, 0, false, nil + } + ok = true + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexBits&0x04 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.L must be zero") + } + if (op == "VPINSRB" || op == "VPINSRW") && vexLength == 3 && vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero for %s", op) + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + firstVectorNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (op == "VPINSRQ" || rExt != 0 || xExt != 0 || bExt != 0 || firstVectorNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("64-bit width or extended register in 32-bit mode") + } + scalar, consumed, err := decodedX86VEXRMSource(code[modRMIndex:], mode, bExt, xExt, segment) + if err != nil { + return Instr{}, 0, true, err + } + immediateIndex := modRMIndex + consumed + if len(code) <= immediateIndex { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + immediate := Operand{Kind: OpImm, Imm: int64(code[immediateIndex])} + firstVector := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", firstVectorNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{immediate, scalar, firstVector, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s, %s", op, immediate.String(), scalar.String(), firstVector.String(), destination.String()), + } + return instruction, immediateIndex + 1, true, nil +} + +// decodedX86VPUNPCKInstruction recognizes the complete VEX.128/VEX.256 +// low/high byte, word, dword, and qword unpack family. x/arch v0.14 can split +// or reject VEX encodings with extended registers, so recover every VEX +// register and ModRM/SIB memory form before the generic decoder. EVEX forms +// continue through x/arch. +func decodedX86VPUNPCKInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + var vexLength, rExt, xExt, bExt int + var vexBits, opcode byte + switch { + case len(code) >= i+3 && code[i] == 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + opcode = code[i+2] + case len(code) >= i+4 && code[i] == 0xc4 && code[i+1]&0x1f == 1: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + opcode = code[i+3] + default: + return Instr{}, 0, false, nil + } + op, recognized := map[byte]Op{ + 0x60: "VPUNPCKLBW", + 0x61: "VPUNPCKLWD", + 0x62: "VPUNPCKLDQ", + 0x6c: "VPUNPCKLQDQ", + 0x68: "VPUNPCKHBW", + 0x69: "VPUNPCKHWD", + 0x6a: "VPUNPCKHDQ", + 0x6d: "VPUNPCKHQDQ", + }[opcode] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexLength == 3 && vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + firstSource, consumed, err := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if err != nil { + return Instr{}, 0, true, err + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +func decodedX86VEXVectorRMOperand(code []byte, mode, bExt, xExt int, segment Reg, vectorPrefix string) (Operand, int, error) { + if len(code) == 0 { + return Operand{}, 0, fmt.Errorf("missing ModRM byte") + } + if code[0]>>6 != 3 { + return decodedX86VEXRMSource(code, mode, bExt, xExt, segment) + } + number := int(code[0]&7) + bExt*8 + if mode == 32 && number >= 8 { + return Operand{}, 0, fmt.Errorf("extended vector register in 32-bit mode") + } + return Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, number))}, 1, nil +} + +// decodedX86VNNIInstruction recognizes the complete VEX.128/VEX.256 +// AVX-VNNI dot-product family. Go's assembler exposes the equivalent named +// EVEX forms, while generated third-party assembly uses raw VEX encodings that +// x/arch v0.14 cannot decode. Recover all four opcodes and every register or +// ModRM/SIB memory source before consulting the generic decoder. +func decodedX86VNNIInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+4 || code[i] != 0xc4 || code[i+1]&0x1f != 2 { + return Instr{}, 0, false, nil + } + vexBits := code[i+2] + opcode := code[i+3] + op, recognized := map[byte]Op{ + 0x50: "VPDPBUSD", + 0x51: "VPDPBUSDS", + 0x52: "VPDPWSSD", + 0x53: "VPDPWSSDS", + }[opcode] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + vex1 := code[i+1] + rExt := int(^vex1>>7) & 1 + xExt := int(^vex1>>6) & 1 + bExt := int(^vex1>>5) & 1 + modRMIndex := i + 4 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + secondSourceNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || secondSourceNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + firstSource, consumed, err := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if err != nil { + return Instr{}, 0, true, err + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{firstSource, secondSource, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +// decodedX86VariableDwordPermuteInstruction recognizes the complete VEX.256 +// VPERMD/VPERMPS family shared by Go 1.27's _yvpermd table. x/arch v0.14 can +// reject or split these encodings, so recover every register and ModRM/SIB +// memory source before consulting the generic decoder. EVEX forms continue +// through x/arch. +func decodedX86VariableDwordPermuteInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) < i+4 || code[i] != 0xc4 || code[i+1]&0x1f != 2 { + return Instr{}, 0, false, nil + } + vexBits := code[i+2] + opcode := code[i+3] + op, recognized := map[byte]Op{ + 0x36: "VPERMD", + 0x16: "VPERMPS", + }[opcode] + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if vexBits&3 != 1 { + return Instr{}, 0, true, fmt.Errorf("VEX.pp must be 66") + } + if vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if vexBits&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.L must be one") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + vex1 := code[i+1] + rExt := int(^vex1>>7) & 1 + xExt := int(^vex1>>6) & 1 + bExt := int(^vex1>>5) & 1 + modRMIndex := i + 4 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + indicesNumber := int(^vexBits>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || indicesNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + data, consumed, err := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, "Y") + if err != nil { + return Instr{}, 0, true, err + } + indices := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("Y%d", indicesNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("Y%d", destinationNumber))} + instruction = Instr{ + Op: op, + Args: []Operand{data, indices, destination}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, data.String(), indices.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +// decodedX86RandomInstruction recognizes the complete register-only +// RDRAND/RDSEED encoding family. x/arch v0.14 drops the operand from the +// 64-bit RDRAND spelling and cannot decode RDSEED, so these encodings must be +// recovered before the generic decoder is consulted. +func decodedX86RandomInstruction(code []byte, mode int) (syntax string, length int, ok bool) { + i := 0 + bits := 32 + if len(code) > i && code[i] == 0x66 { + bits = 16 + i++ + } + rex := byte(0) + if mode == 64 && len(code) > i && code[i] >= 0x40 && code[i] <= 0x4f { + rex = code[i] + i++ + if rex&0x08 != 0 { + bits = 64 + } + } + if len(code) < i+3 || code[i] != 0x0f || code[i+1] != 0xc7 { + return "", 0, false + } + modRM := code[i+2] + if modRM>>6 != 3 { + return "", 0, false + } + family := "" + switch modRM >> 3 & 7 { + case 6: + family = "RDRAND" + case 7: + family = "RDSEED" + default: + return "", 0, false + } + register := int(modRM & 7) + if mode == 64 && rex&0x01 != 0 { + register += 8 + } + registerNames := [...]string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"} + width := map[int]string{16: "W", 32: "L", 64: "Q"}[bits] + return fmt.Sprintf("%s%s %s", family, width, registerNames[register]), i + 3, true +} + +// decodedX86VBROADCASTI128Instruction recognizes the complete AVX2 +// VBROADCASTI128 m128, Y family. x/arch v0.14 misdecodes this VEX opcode as +// legacy scalar instructions, so recover every ModRM/SIB memory form before +// consulting the generic decoder. +func decodedX86VBROADCASTI128Instruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + // VEX.256.66.0F38.W0 5A /r. The unused encoded vvvv field must be + // 1111, so the complete third VEX byte is 0x7d. + if len(code) < i+5 || code[i] != 0xc4 || code[i+1]&0x1f != 2 || code[i+2] != 0x7d || code[i+3] != 0x5a { + return Instr{}, 0, false, nil + } + ok = true + if mode != 32 && mode != 64 { + return Instr{}, 0, true, fmt.Errorf("unsupported x86 mode %d", mode) + } + vex1 := code[i+1] + rExt := int(^vex1>>7) & 1 + xExt := int(^vex1>>6) & 1 + bExt := int(^vex1>>5) & 1 + destinationNumber := int(code[i+4]>>3&7) + rExt*8 + if mode == 32 && (rExt != 0 || xExt != 0 || bExt != 0 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + source, consumed, err := decodedX86VEXRMSource(code[i+4:], mode, bExt, xExt, segment) + if err != nil { + return Instr{}, 0, true, err + } + if source.Kind != OpMem { + return Instr{}, 0, true, fmt.Errorf("source must be m128 memory") + } + destination := Reg(fmt.Sprintf("Y%d", destinationNumber)) + instruction = Instr{ + Op: "VBROADCASTI128", + Args: []Operand{source, {Kind: OpReg, Reg: destination}}, + Raw: fmt.Sprintf("VBROADCASTI128 %s, %s", source.String(), destination), + } + return instruction, i + 4 + consumed, true, nil +} + +// decodedX86SHAInstruction recognizes the complete Go 1.27 Intel SHA table: +// SHA1NEXTE, SHA1MSG1/2, SHA1RNDS4, SHA256MSG1/2, and SHA256RNDS2. Older +// x/arch decoders reject some raw 0F38 encodings used by minio/sha256-simd. +func decodedX86SHAInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto rex + } + } + +rex: + rexPrefix := byte(0) + if mode == 64 && i < len(code) && code[i]&0xf0 == 0x40 { + rexPrefix = code[i] + i++ + } + if len(code) < i+4 || code[i] != 0x0f { + return Instr{}, 0, false, nil + } + + op := Op("") + immediate := false + switch { + case code[i+1] == 0x38: + switch code[i+2] { + case 0xc8: + op = "SHA1NEXTE" + case 0xc9: + op = "SHA1MSG1" + case 0xca: + op = "SHA1MSG2" + case 0xcb: + op = "SHA256RNDS2" + case 0xcc: + op = "SHA256MSG1" + case 0xcd: + op = "SHA256MSG2" + default: + return Instr{}, 0, false, nil + } + case code[i+1] == 0x3a && code[i+2] == 0xcc: + op = "SHA1RNDS4" + immediate = true + default: + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + modRMIndex := i + 3 + modRM := code[modRMIndex] + rExt := int(rexPrefix>>2) & 1 + xExt := int(rexPrefix>>1) & 1 + bExt := int(rexPrefix) & 1 + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", destinationNumber))} + + var source Operand + consumed := 0 + if modRM>>6 == 3 { + sourceNumber := int(modRM&7) + bExt*8 + if mode == 32 && sourceNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + source = Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("X%d", sourceNumber))} + consumed = 1 + } else { + var decodeErr error + source, consumed, decodeErr = decodedX86RMSource(code[modRMIndex:], mode, bExt, xExt, segment, 1) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + } + + args := []Operand{source, destination} + end := modRMIndex + consumed + if immediate { + if len(code) <= end { + return Instr{}, 0, true, fmt.Errorf("missing immediate byte") + } + // SHA1RNDS4 consumes only the low two bits. Normalize the raw byte to + // Go's Yu2 operand class so the recovered instruction remains valid. + args = []Operand{{Kind: OpImm, Imm: int64(code[end] & 3)}, source, destination} + end++ + } else if op == "SHA256RNDS2" { + args = []Operand{{Kind: OpReg, Reg: Reg("X0")}, source, destination} + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, end, true, nil +} + +// decodedX86BLSInstruction recognizes the complete BMI1 BLSI/BLSMSK/BLSR +// register and ModRM/SIB memory families. x/arch v0.14 reports these VEX.NDD +// encodings as unknown AVX opcodes, so recover them before generic decoding. +func decodedX86BLSInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if len(code) < i+5 || code[i] != 0xc4 || code[i+1]&0x1f != 2 || code[i+2]&0x07 != 0 || code[i+3] != 0xf3 { + return Instr{}, 0, false, nil + } + ok = true + vex1, vex2 := code[i+1], code[i+2] + xExt := int(^vex1>>6) & 1 + bExt := int(^vex1>>5) & 1 + width64 := vex2&0x80 != 0 + destinationNumber := int(^vex2>>3) & 15 + modRM := code[i+4] + family := "" + switch modRM >> 3 & 7 { + case 1: + family = "BLSR" + case 2: + family = "BLSMSK" + case 3: + family = "BLSI" + default: + return Instr{}, 0, true, fmt.Errorf("invalid opcode extension /%d", modRM>>3&7) + } + if mode != 32 && mode != 64 { + return Instr{}, 0, true, fmt.Errorf("unsupported x86 mode %d", mode) + } + if mode == 32 && (xExt != 0 || bExt != 0 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended register in 32-bit mode") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + source, consumed, err := decodedX86VEXRMSource(code[i+4:], mode, bExt, xExt, segment) + if err != nil { + return Instr{}, 0, true, err + } + destination, valid := decodedX86GeneralRegister(destinationNumber) + if !valid { + return Instr{}, 0, true, fmt.Errorf("invalid destination register %d", destinationNumber) + } + op := Op(family + "L") + if width64 && mode == 64 { + op = Op(family + "Q") + } + instruction = Instr{ + Op: op, + Args: []Operand{source, {Kind: OpReg, Reg: destination}}, + Raw: fmt.Sprintf("%s %s, %s", op, source.String(), destination), + } + return instruction, i + 4 + consumed, true, nil +} + +// decodedX86MULXInstruction recognizes the complete BMI2 MULX register and +// ModRM/SIB memory family. x/arch rejects this VEX.NDD encoding even though +// Go's assembler and the semantic lowerer support MULXL/MULXQ. +func decodedX86MULXInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if len(code) < i+5 || code[i] != 0xc4 || code[i+1]&0x1f != 2 || code[i+2]&0x07 != 3 || code[i+3] != 0xf6 { + return Instr{}, 0, false, nil + } + ok = true + vex1, vex2 := code[i+1], code[i+2] + if vex2&0x04 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.L must be zero") + } + rExt := int(^vex1>>7) & 1 + xExt := int(^vex1>>6) & 1 + bExt := int(^vex1>>5) & 1 + width64 := vex2&0x80 != 0 + lowRegister := int(^vex2>>3) & 15 + modRM := code[i+4] + highRegister := int(modRM>>3&7) + rExt*8 + if mode == 32 && (width64 || rExt != 0 || xExt != 0 || bExt != 0 || lowRegister >= 8 || highRegister >= 8) { + return Instr{}, 0, true, fmt.Errorf("64-bit width or extended register in 32-bit mode") + } + if mode != 32 && mode != 64 { + return Instr{}, 0, true, fmt.Errorf("unsupported x86 mode %d", mode) + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + source, consumed, err := decodedX86VEXRMSource(code[i+4:], mode, bExt, xExt, segment) + if err != nil { + return Instr{}, 0, true, err + } + low, valid := decodedX86GeneralRegister(lowRegister) + if !valid { + return Instr{}, 0, true, fmt.Errorf("invalid low destination register %d", lowRegister) + } + high, valid := decodedX86GeneralRegister(highRegister) + if !valid { + return Instr{}, 0, true, fmt.Errorf("invalid high destination register %d", highRegister) + } + op := Op("MULXL") + if width64 { + op = "MULXQ" + } + instruction = Instr{ + Op: op, + Args: []Operand{source, {Kind: OpReg, Reg: low}, {Kind: OpReg, Reg: high}}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, source.String(), low, high), + } + return instruction, i + 4 + consumed, true, nil +} + +func decodedX86VEXRMSource(code []byte, mode, bExt, xExt int, segment Reg) (Operand, int, error) { + return decodedX86RMSource(code, mode, bExt, xExt, segment, 1) +} + +func decodedX86RMSource(code []byte, mode, bExt, xExt int, segment Reg, disp8Scale int) (Operand, int, error) { + if len(code) == 0 { + return Operand{}, 0, fmt.Errorf("missing ModRM byte") + } + if disp8Scale <= 0 { + return Operand{}, 0, fmt.Errorf("invalid disp8 scale %d", disp8Scale) + } + modRM := code[0] + mod := int(modRM >> 6) + rm := int(modRM & 7) + if mod == 3 { + register, ok := decodedX86GeneralRegister(rm + bExt*8) + if !ok || mode == 32 && rm+bExt*8 >= 8 { + return Operand{}, 0, fmt.Errorf("invalid source register") + } + return Operand{Kind: OpReg, Reg: register}, 1, nil + } + + mem := MemRef{Segment: segment} + consumed := 1 + readDisp8 := func() error { + if len(code) < consumed+1 { + return fmt.Errorf("truncated disp8") + } + mem.Off = int64(int8(code[consumed])) * int64(disp8Scale) + consumed++ + return nil + } + readDisp32 := func() error { + if len(code) < consumed+4 { + return fmt.Errorf("truncated disp32") + } + mem.Off = int64(int32(binary.LittleEndian.Uint32(code[consumed : consumed+4]))) + consumed += 4 + return nil + } + + if rm == 4 { + if len(code) < consumed+1 { + return Operand{}, 0, fmt.Errorf("truncated SIB byte") + } + sib := code[consumed] + consumed++ + indexNumber := int(sib>>3&7) + xExt*8 + if int(sib>>3&7) != 4 || xExt != 0 { + index, ok := decodedX86GeneralRegister(indexNumber) + if !ok || mode == 32 && indexNumber >= 8 { + return Operand{}, 0, fmt.Errorf("invalid SIB index register") + } + mem.Index = index + mem.Scale = int64(1 << (sib >> 6)) + } + baseBits := int(sib & 7) + if mod == 0 && baseBits == 5 { + if err := readDisp32(); err != nil { + return Operand{}, 0, err + } + } else { + baseNumber := baseBits + bExt*8 + base, ok := decodedX86GeneralRegister(baseNumber) + if !ok || mode == 32 && baseNumber >= 8 { + return Operand{}, 0, fmt.Errorf("invalid SIB base register") + } + mem.Base = base + } + } else if mod == 0 && rm == 5 { + if mode == 64 { + return Operand{}, 0, fmt.Errorf("RIP-relative source is not source-layout safe") + } + if err := readDisp32(); err != nil { + return Operand{}, 0, err + } + } else { + baseNumber := rm + bExt*8 + base, ok := decodedX86GeneralRegister(baseNumber) + if !ok || mode == 32 && baseNumber >= 8 { + return Operand{}, 0, fmt.Errorf("invalid base register") + } + mem.Base = base + } + + switch mod { + case 1: + if err := readDisp8(); err != nil { + return Operand{}, 0, err + } + case 2: + if err := readDisp32(); err != nil { + return Operand{}, 0, err + } + } + return Operand{Kind: OpMem, Mem: mem}, consumed, nil +} + +func decodedX86GeneralRegister(number int) (Reg, bool) { + names := [...]Reg{AX, CX, DX, BX, SP, BP, SI, DI, "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"} + if number < 0 || number >= len(names) { + return "", false + } + return names[number], true +} + +// x86RawRetpolineTarget recognizes the complete amd64 RETPOLINE(reg) byte +// family emitted by the Go runtime. Its local CALL and backward PAUSE loop are +// a speculative-execution barrier; architecturally the sequence replaces the +// temporary return address with reg and returns to it, which is an indirect +// tail jump. Requiring every fixed byte prevents arbitrary PC-relative raw +// control flow from being accepted through this path. +func x86RawRetpolineTarget(code []byte) (Reg, bool) { + if len(code) != 14 || + code[0] != 0xe8 || code[1] != 0x04 || code[2] != 0 || code[3] != 0 || code[4] != 0 || + code[5] != 0xf3 || code[6] != 0x90 || code[7] != 0xeb || code[8] != 0xfc || + (code[9] != 0x48 && code[9] != 0x4c) || code[10] != 0x89 || code[11]&0xc7 != 0x04 || + code[12] != 0x24 || code[13] != 0xc3 { + return "", false + } + register := int(code[11]>>3&7) + int(code[9]>>2&1)*8 + if register == 4 { + return "", false + } + names := [...]Reg{AX, CX, DX, BX, SP, BP, SI, DI, "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"} + return names[register], true +} + +func decodedX86GoSyntax(inst x86asm.Inst, encoding []byte) (string, error) { + syntax := x86asm.GoSyntax(inst, 0, nil) + replaceOp := func(op string) { + if space := strings.IndexByte(syntax, ' '); space >= 0 { + syntax = op + syntax[space:] + } else { + syntax = op + } + } + if op, ok := decodedX86CacheLineWriteback(encoding); ok { + replaceOp(op) + return syntax, nil + } + + switch inst.Op { + case x86asm.NOP: + // The decoder prints NOPL/NOPW according to the encoded data size. + // The address operand of a multi-byte x86 NOP is not read, so the + // semantic instruction is the operand-free Plan 9 NOP. + return "NOP", nil + case x86asm.MOVSXD: + replaceOp("MOVLQSX") + case x86asm.MOVDQA: + replaceOp("MOVO") + case x86asm.MOVDQU: + replaceOp("MOVOU") + case x86asm.MOVNTDQ: + // Go's assembler calls the legacy 128-bit non-temporal store MOVNTO. + // MOVNTDQ is reserved for the VEX/EVEX VMOVNTDQ spelling. + replaceOp("MOVNTO") + case x86asm.MOVSD_XMM: + replaceOp("MOVSD") + case x86asm.IMUL: + argumentCount := 0 + for _, argument := range inst.Args { + if argument != nil { + argumentCount++ + } + } + if argumentCount == 3 { + destination, ok := inst.Args[0].(x86asm.Reg) + if !ok { + return "", fmt.Errorf("three-operand IMUL destination is not a register") + } + width := map[int]string{16: "W", 32: "L", 64: "Q"}[decodedX86RegisterBits(destination)] + if width == "" { + return "", fmt.Errorf("three-operand IMUL has unsupported destination width %d", decodedX86RegisterBits(destination)) + } + replaceOp("IMUL3" + width) + } + case x86asm.BSWAP: + destination, ok := inst.Args[0].(x86asm.Reg) + if !ok { + return "", fmt.Errorf("BSWAP destination is not a register") + } + width := map[int]string{32: "L", 64: "Q"}[decodedX86RegisterBits(destination)] + if width == "" { + return "", fmt.Errorf("BSWAP has unsupported destination width %d", decodedX86RegisterBits(destination)) + } + replaceOp("BSWAP" + width) + case x86asm.CVTSI2SS, x86asm.CVTSI2SD: + sourceBits := inst.MemBytes * 8 + if source, ok := inst.Args[1].(x86asm.Reg); ok { + sourceBits = decodedX86RegisterBits(source) + } + sourceWidth := map[int]string{32: "L", 64: "Q"}[sourceBits] + if sourceWidth == "" { + return "", fmt.Errorf("%s has unsupported decoded source width %d", inst.Op, sourceBits) + } + resultWidth := "SS" + if inst.Op == x86asm.CVTSI2SD { + resultWidth = "SD" + } + replaceOp("CVTS" + sourceWidth + "2" + resultWidth) + case x86asm.CVTSS2SI, x86asm.CVTSD2SI, x86asm.CVTTSS2SI, x86asm.CVTTSD2SI: + // x/arch prints Intel's SI destination stem (and, in some memory + // cases, derives the wrong Plan 9 width). Go's assembler names this + // legacy family CVT{T}{SS,SD}2S{L,Q}. Recover the destination width + // from REX.W, which is the architectural selector for all four ops. + outputWidth := "L" + if inst.Mode == 64 { + for _, prefix := range inst.Prefix { + if prefix.IsREX() && prefix&x86asm.PrefixREXW != 0 { + outputWidth = "Q" + break + } + } + } + name := map[x86asm.Op]string{ + x86asm.CVTSS2SI: "CVTSS2S", + x86asm.CVTSD2SI: "CVTSD2S", + x86asm.CVTTSS2SI: "CVTTSS2S", + x86asm.CVTTSD2SI: "CVTTSD2S", + }[inst.Op] + replaceOp(name + outputWidth) + case x86asm.PACKSSDW: + replaceOp("PACKSSLW") + case x86asm.PCMPEQD: + replaceOp("PCMPEQL") + case x86asm.PCMPGTD: + replaceOp("PCMPGTL") + case x86asm.PMADDWD: + replaceOp("PMADDWL") + case x86asm.PMULUDQ: + replaceOp("PMULULQ") + case x86asm.PSLLD: + replaceOp("PSLLL") + case x86asm.PSRAD: + replaceOp("PSRAL") + case x86asm.PSRLD: + replaceOp("PSRLL") + case x86asm.PSUBD: + replaceOp("PSUBL") + case x86asm.PUNPCKHDQ: + replaceOp("PUNPCKHLQ") + case x86asm.PUNPCKHWD: + replaceOp("PUNPCKHWL") + case x86asm.PUNPCKLDQ: + replaceOp("PUNPCKLLQ") + case x86asm.PUNPCKLWD: + replaceOp("PUNPCKLWL") + case x86asm.CRC32: + bits := inst.MemBytes * 8 + if source, ok := inst.Args[1].(x86asm.Reg); ok { + bits = decodedX86RegisterBits(source) + } + width := map[int]string{8: "B", 16: "W", 32: "L", 64: "Q"}[bits] + if width == "" { + return "", fmt.Errorf("CRC32 has unsupported decoded source width %d", bits) + } + replaceOp("CRC32" + width) + case x86asm.MOVSX, x86asm.MOVZX: + dst, ok := inst.Args[0].(x86asm.Reg) + if !ok { + return "", fmt.Errorf("%s destination is not a register", inst.Op) + } + destinationBits := decodedX86RegisterBits(dst) + sourceBits := inst.MemBytes * 8 + if source, ok := inst.Args[1].(x86asm.Reg); ok { + sourceBits = decodedX86RegisterBits(source) + } + widthLetter := func(bits int) string { + switch bits { + case 8: + return "B" + case 16: + return "W" + case 32: + return "L" + case 64: + return "Q" + default: + return "" + } + } + sourceLetter := widthLetter(sourceBits) + destinationLetter := widthLetter(destinationBits) + if sourceLetter == "" || destinationLetter == "" { + return "", fmt.Errorf("%s has unsupported decoded widths %d -> %d", inst.Op, sourceBits, destinationBits) + } + extension := "SX" + if inst.Op == x86asm.MOVZX { + extension = "ZX" + } + replaceOp("MOV" + sourceLetter + destinationLetter + extension) + } + normalizeDecodedX86GoOpcode(inst, &syntax, replaceOp) + return syntax, nil +} + +// normalizeDecodedX86GoOpcode bridges the architectural names emitted by +// x/arch's decoder and the semantic names/classes used by Go 1.27's +// cmd/internal/obj/x86 tables. Go's assembler intentionally uses aliases such +// as SETOS and CMOVQLE, while x/arch prints Intel names such as SETO and +// CMOVLE. x/arch also prints the byte-immediate ADD opcode as ADDL even when +// its destination is an 8-bit register; that spelling is rejected by Go's +// Yml/Ymb operand classes and must be corrected from the decoded operands. +func normalizeDecodedX86GoOpcode(inst x86asm.Inst, syntax *string, replaceOp func(string)) { + op := strings.ToUpper(inst.Op.String()) + setAliases := map[string]string{ + "SETA": "SETHI", "SETAE": "SETCC", "SETB": "SETCS", "SETBE": "SETLS", + "SETE": "SETEQ", "SETG": "SETGT", "SETGE": "SETGE", "SETL": "SETLT", + "SETLE": "SETLE", "SETNE": "SETNE", "SETNO": "SETOC", "SETNP": "SETPC", + "SETNS": "SETPL", "SETO": "SETOS", "SETP": "SETPS", "SETS": "SETMI", + } + if alias, ok := setAliases[op]; ok { + replaceOp(alias) + // GoSyntax deliberately omits the B suffix for extended byte registers + // (for example it prints SETO R9). Reconstruct the decoded register's + // actual byte spelling before reparsing the instruction. + if len(inst.Args) > 0 { + if reg, ok := inst.Args[0].(x86asm.Reg); ok { + *syntax = alias + " " + reg.String() + } + } + return + } + + cmovConditions := map[string]string{ + "CMOVA": "HI", "CMOVAE": "CC", "CMOVB": "CS", "CMOVBE": "LS", + "CMOVE": "EQ", "CMOVG": "GT", "CMOVGE": "GE", "CMOVL": "LT", + "CMOVLE": "LE", "CMOVNE": "NE", "CMOVNO": "OC", "CMOVNP": "PC", + "CMOVNS": "PL", "CMOVO": "OS", "CMOVP": "PS", "CMOVS": "MI", + } + if condition, ok := cmovConditions[op]; ok { + bits := 0 + for i := 0; i < 2 && i < len(inst.Args); i++ { + if reg, ok := inst.Args[i].(x86asm.Reg); ok { + if n := decodedX86RegisterBits(reg); n > bits { + bits = n + } + } + } + if bits == 0 { + bits = inst.MemBytes * 8 + } + width := map[int]string{16: "W", 32: "L", 64: "Q"}[bits] + if width != "" { + replaceOp("CMOV" + width + condition) + } + return + } + + if decodedX86WidthOpcode(op) == "" || len(inst.Args) == 0 { + return + } + dstBits := 0 + if reg, ok := inst.Args[0].(x86asm.Reg); ok { + dstBits = decodedX86RegisterBits(reg) + } else if _, ok := inst.Args[0].(x86asm.Mem); ok { + dstBits = inst.MemBytes * 8 + } + width := map[int]string{8: "B", 16: "W", 32: "L", 64: "Q"}[dstBits] + if width != "" { + replaceOp(op + width) + } +} + +func decodedX86WidthOpcode(op string) string { + switch op { + case "ADD", "ADC", "SBB", "SUB", "AND", "OR", "XOR", "CMP", "TEST": + return op + default: + return "" + } +} + +// decodedX86CacheLineWritebackInstruction recognizes the complete raw +// CLFLUSH/CLFLUSHOPT/CLWB memory family before x/arch's generic decoder. In +// particular, generated assembly in github.com/wencode/hack places a REX +// prefix before the mandatory 0x66 prefix, which x/arch v0.14 rejects even +// though x86 hardware accepts the prefix sequence. +func decodedX86CacheLineWritebackInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + hasDataSizePrefix := false + addressOverride := false + segment := Reg("") + rex := byte(0) + hasREX := false + for i < len(code) { + switch code[i] { + case 0x64: + // A legacy prefix after REX makes that REX byte ineffective. Only + // the REX prefix immediately preceding the opcode escape applies. + rex = 0 + hasREX = false + segment = FS + i++ + case 0x65: + rex = 0 + hasREX = false + segment = GS + i++ + case 0x66: + rex = 0 + hasREX = false + hasDataSizePrefix = true + i++ + case 0x67: + rex = 0 + hasREX = false + addressOverride = true + i++ + default: + if mode == 64 && code[i] >= 0x40 && code[i] <= 0x4f { + rex = code[i] + hasREX = true + i++ + continue + } + goto opcode + } + } + +opcode: + if len(code) < i+3 || code[i] != 0x0f || code[i+1] != 0xae { + return Instr{}, 0, false, nil + } + modRM := code[i+2] + extension := modRM >> 3 & 7 + op := Op("") + switch { + case extension == 7 && !hasDataSizePrefix: + op = "CLFLUSH" + case extension == 7 && hasDataSizePrefix: + op = "CLFLUSHOPT" + case extension == 6 && hasDataSizePrefix: + op = "CLWB" + default: + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if hasREX && rex&0x0c != 0 { + return Instr{}, 0, true, fmt.Errorf("REX.W and REX.R are absent from Go 1.27's %s encoding", op) + } + if modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("%s requires a memory operand", op) + } + bExt := int(rex & 1) + xExt := int(rex>>1) & 1 + memory, consumed, decodeErr := decodedX86VEXRMSource(code[i+2:], mode, bExt, xExt, segment) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + instruction = Instr{ + Op: op, + Args: []Operand{memory}, + Raw: fmt.Sprintf("%s %s", op, memory.String()), + } + return instruction, i + 2 + consumed, true, nil +} + +// decodedX86CacheLineWriteback recovers instructions which x/arch v0.14 +// cannot distinguish from their older 0F AE encodings. The explicit 0x66 +// mandatory prefix plus the ModRM extension is the architectural distinction: +// /7 is CLFLUSHOPT and /6 is CLWB. Parse only the actual prefix/opcode region +// so an identical byte sequence inside a displacement cannot be mistaken for +// an opcode. +func decodedX86CacheLineWriteback(encoding []byte) (string, bool) { + hasDataSizePrefix := false + i := 0 + for i < len(encoding) { + switch encoding[i] { + case 0x26, 0x2e, 0x36, 0x3e, 0x64, 0x65, 0x67, 0xf0, 0xf2, 0xf3: + i++ + case 0x66: + hasDataSizePrefix = true + i++ + default: + if encoding[i] >= 0x40 && encoding[i] <= 0x4f { + i++ + continue + } + goto opcode + } + } + +opcode: + if !hasDataSizePrefix || i+2 >= len(encoding) || encoding[i] != 0x0f || encoding[i+1] != 0xae { + return "", false + } + modRM := encoding[i+2] + if modRM>>6 == 3 { + return "", false + } + switch modRM >> 3 & 7 { + case 7: + return "CLFLUSHOPT", true + case 6: + return "CLWB", true + default: + return "", false + } +} + +func decodedX86RegisterBits(reg x86asm.Reg) int { + switch { + case x86asm.AL <= reg && reg <= x86asm.R15B: + return 8 + case x86asm.AX <= reg && reg <= x86asm.R15W: + return 16 + case x86asm.EAX <= reg && reg <= x86asm.R15L: + return 32 + case x86asm.RAX <= reg && reg <= x86asm.R15: + return 64 + default: + return 0 + } +} + +func isX86RawDirective(ins Instr) bool { + switch Op(strings.ToUpper(string(ins.Op))) { + case OpBYTE, OpWORD, "LONG", "QUAD": + return true + default: + return false + } +} + +func x86RawDirectiveBytes(ins Instr) ([]byte, error) { + if len(ins.Args) != 1 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return nil, fmt.Errorf("%s expects exactly one resolved integer constant: %q", ins.Op, ins.Raw) + } + value := uint64(ins.Args[0].Imm) + switch Op(strings.ToUpper(string(ins.Op))) { + case OpBYTE: + return []byte{byte(value)}, nil + case OpWORD: + var buf [2]byte + binary.LittleEndian.PutUint16(buf[:], uint16(value)) + return buf[:], nil + case "LONG": + var buf [4]byte + binary.LittleEndian.PutUint32(buf[:], uint32(value)) + return buf[:], nil + case "QUAD": + var buf [8]byte + binary.LittleEndian.PutUint64(buf[:], value) + return buf[:], nil + default: + return nil, fmt.Errorf("not an x86 raw directive: %q", ins.Raw) + } +} + +func parseDecodedX86Instruction(syntax string) ([]Instr, error) { + file, err := Parse(ArchAMD64, "TEXT decoded(SB), NOSPLIT, $0-0\n"+syntax+"\n") + if err != nil { + return nil, err + } + if len(file.Funcs) != 1 || len(file.Funcs[0].Instrs) < 2 { + return nil, fmt.Errorf("decoder syntax produced no instruction") + } + return append([]Instr(nil), file.Funcs[0].Instrs[1:]...), nil +} diff --git a/amd64_raw_alias_test.go b/amd64_raw_alias_test.go new file mode 100644 index 00000000..c53f47e0 --- /dev/null +++ b/amd64_raw_alias_test.go @@ -0,0 +1,582 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestX86RawDecoderPreservesGoOpcodeAliasesAndMandatoryPrefixes(t *testing.T) { + tests := []struct { + name string + code []byte + want Op + }{ + {name: "PACKSSDW is Go PACKSSLW", code: []byte{0x66, 0x0f, 0x6b, 0xca}, want: "PACKSSLW"}, + {name: "PCMPEQD is Go PCMPEQL", code: []byte{0x66, 0x0f, 0x76, 0xca}, want: "PCMPEQL"}, + {name: "PCMPGTD is Go PCMPGTL", code: []byte{0x66, 0x0f, 0x66, 0xca}, want: "PCMPGTL"}, + {name: "PMADDWD is Go PMADDWL", code: []byte{0x66, 0x0f, 0xf5, 0xca}, want: "PMADDWL"}, + {name: "PMULUDQ is Go PMULULQ", code: []byte{0x66, 0x0f, 0xf4, 0xca}, want: "PMULULQ"}, + {name: "PSLLD is Go PSLLL", code: []byte{0x66, 0x0f, 0xf2, 0xca}, want: "PSLLL"}, + {name: "PSRAD is Go PSRAL", code: []byte{0x66, 0x0f, 0xe2, 0xca}, want: "PSRAL"}, + {name: "PSRLD is Go PSRLL", code: []byte{0x66, 0x0f, 0xd2, 0xca}, want: "PSRLL"}, + {name: "PSUBD is Go PSUBL", code: []byte{0x66, 0x0f, 0xfa, 0xca}, want: "PSUBL"}, + {name: "PUNPCKHDQ is Go PUNPCKHLQ", code: []byte{0x66, 0x0f, 0x6a, 0xca}, want: "PUNPCKHLQ"}, + {name: "PUNPCKHWD is Go PUNPCKHWL", code: []byte{0x66, 0x0f, 0x69, 0xca}, want: "PUNPCKHWL"}, + {name: "PUNPCKLDQ is Go PUNPCKLLQ", code: []byte{0x66, 0x0f, 0x62, 0xca}, want: "PUNPCKLLQ"}, + {name: "PUNPCKLWD is Go PUNPCKLWL", code: []byte{0x66, 0x0f, 0x61, 0xca}, want: "PUNPCKLWL"}, + {name: "MOVDQA is Go MOVO", code: []byte{0x66, 0x0f, 0x6f, 0xc1}, want: "MOVO"}, + {name: "MOVDQU is Go MOVOU", code: []byte{0xf3, 0x0f, 0x6f, 0xc1}, want: "MOVOU"}, + {name: "MOVSD XMM is Go MOVSD", code: []byte{0xf2, 0x0f, 0x10, 0xc1}, want: "MOVSD"}, + {name: "CLFLUSHOPT mandatory prefix", code: []byte{0x66, 0x0f, 0xae, 0x38}, want: "CLFLUSHOPT"}, + {name: "CLWB mandatory prefix", code: []byte{0x66, 0x0f, 0xae, 0x30}, want: "CLWB"}, + } + for _, goarch := range []string{"386", "amd64"} { + for _, test := range tests { + t.Run(goarch+"/"+test.name, func(t *testing.T) { + fn := Func{} + for _, value := range test.code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, goarch) + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || got.Instrs[0].Op != test.want { + t.Fatalf("decoded %#x as %#v, want one %s instruction", test.code, got.Instrs, test.want) + } + }) + } + } +} + +func TestX86RawDecoderVBROADCASTI128CompleteFamily(t *testing.T) { + tests := []struct { + name string + goarch string + code []byte + source MemRef + dest Reg + }{ + {name: "low registers", goarch: "amd64", code: []byte{0xc4, 0xe2, 0x7d, 0x5a, 0x13}, source: MemRef{Base: BX}, dest: "Y2"}, + {name: "extended base", goarch: "amd64", code: []byte{0xc4, 0xc2, 0x7d, 0x5a, 0x13}, source: MemRef{Base: "R11"}, dest: "Y2"}, + {name: "extended destination", goarch: "amd64", code: []byte{0xc4, 0x62, 0x7d, 0x5a, 0x1b}, source: MemRef{Base: BX}, dest: "Y11"}, + {name: "extended base and destination with displacement", goarch: "amd64", code: []byte{0xc4, 0x42, 0x7d, 0x5a, 0x70, 0x10}, source: MemRef{Base: "R8", Off: 16}, dest: "Y14"}, + {name: "extended SIB", goarch: "amd64", code: []byte{0xc4, 0x02, 0x7d, 0x5a, 0x64, 0x88, 0x20}, source: MemRef{Base: "R8", Index: "R9", Scale: 4, Off: 32}, dest: "Y12"}, + {name: "FS segment", goarch: "amd64", code: []byte{0x64, 0xc4, 0xe2, 0x7d, 0x5a, 0x13}, source: MemRef{Segment: FS, Base: BX}, dest: "Y2"}, + {name: "32-bit base", goarch: "386", code: []byte{0xc4, 0xe2, 0x7d, 0x5a, 0x53, 0x7f}, source: MemRef{Base: BX, Off: 127}, dest: "Y2"}, + {name: "32-bit absolute", goarch: "386", code: []byte{0xc4, 0xe2, 0x7d, 0x5a, 0x15, 0x78, 0x56, 0x34, 0x12}, source: MemRef{Off: 0x12345678}, dest: "Y2"}, + } + for _, test := range tests { + t.Run(test.goarch+"/"+test.name, func(t *testing.T) { + fn := Func{} + for _, value := range test.code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, test.goarch) + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 { + t.Fatalf("decoded %#x as %#v, want one instruction", test.code, got.Instrs) + } + ins := got.Instrs[0] + if ins.Op != "VBROADCASTI128" || len(ins.Args) != 2 || ins.Args[0].Kind != OpMem || ins.Args[0].Mem != test.source || ins.Args[1].Kind != OpReg || ins.Args[1].Reg != test.dest { + t.Fatalf("decoded %#x as %#v, want VBROADCASTI128 %#v, %s", test.code, ins, test.source, test.dest) + } + }) + } +} + +func TestX86RawDecoderNormalizesArchitecturalAliasesToGo127Forms(t *testing.T) { + code := []byte{ + 0x41, 0x0f, 0x90, 0xc1, // SETO R9B -> SETOS R9B + 0x41, 0x0f, 0x92, 0xc1, // SETB R9B -> SETCS R9B + 0x48, 0x0f, 0x4e, 0xc1, // CMOVLE RAX, RCX -> CMOVQLE AX, CX + 0x04, 0x01, // ADD $1, AL -> ADDB $1, AL + } + fn := Func{} + for _, value := range code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, "amd64") + if err != nil { + t.Fatal(err) + } + want := []Op{"SETOS", "SETCS", "CMOVQLE", "ADDB"} + if len(got.Instrs) != len(want) { + t.Fatalf("decoded %#x as %#v, want %d instructions", code, got.Instrs, len(want)) + } + for i, op := range want { + if got.Instrs[i].Op != op { + t.Errorf("decoded instruction %d as %s, want %s (%q)", i, got.Instrs[i].Op, op, got.Instrs[i].Raw) + } + } + if got.Instrs[0].Args[0].Reg != R9B || got.Instrs[1].Args[0].Reg != R9B { + t.Errorf("SETcc byte aliases = %s and %s, want R9B", got.Instrs[0].Args[0].Reg, got.Instrs[1].Args[0].Reg) + } +} + +func TestX86RawDecoderNormalizesEveryThreeOperandIMULWidth(t *testing.T) { + tests := []struct { + name string + code []byte + want Op + }{ + {name: "word imm8 register", code: []byte{0x66, 0x6b, 0xf9, 0x07}, want: "IMUL3W"}, + {name: "long imm8 register", code: []byte{0x6b, 0xf9, 0x07}, want: "IMUL3L"}, + {name: "quad imm8 register", code: []byte{0x48, 0x6b, 0xf9, 0x07}, want: "IMUL3Q"}, + {name: "word imm16 memory", code: []byte{0x66, 0x69, 0x78, 0x08, 0x34, 0x12}, want: "IMUL3W"}, + {name: "long imm32 memory", code: []byte{0x69, 0x78, 0x08, 0x78, 0x56, 0x34, 0x12}, want: "IMUL3L"}, + {name: "quad imm32 memory", code: []byte{0x48, 0x69, 0x78, 0x08, 0x78, 0x56, 0x34, 0x12}, want: "IMUL3Q"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + fn := Func{} + for _, value := range test.code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || got.Instrs[0].Op != test.want || len(got.Instrs[0].Args) != 3 { + t.Fatalf("decoded %#x as %#v, want one three-operand %s", test.code, got.Instrs, test.want) + } + }) + } +} + +func TestX86RawDecoderNormalizesCompleteBSWAPFamily(t *testing.T) { + tests := []struct { + name string + code []byte + want Op + reg Reg + }{ + {name: "long low register", code: []byte{0x0f, 0xc8}, want: "BSWAPL", reg: AX}, + {name: "long extended register", code: []byte{0x41, 0x0f, 0xcf}, want: "BSWAPL", reg: Reg("R15")}, + {name: "quad low register", code: []byte{0x48, 0x0f, 0xc8}, want: "BSWAPQ", reg: AX}, + {name: "quad extended register", code: []byte{0x49, 0x0f, 0xcf}, want: "BSWAPQ", reg: Reg("R15")}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + fn := Func{} + for _, value := range test.code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || got.Instrs[0].Op != test.want || len(got.Instrs[0].Args) != 1 || got.Instrs[0].Args[0].Reg != test.reg { + t.Fatalf("decoded %#x as %#v, want %s %s", test.code, got.Instrs, test.want, test.reg) + } + }) + } +} + +func TestX86RawDecoderNormalizesCompleteScalarIntegerFloatFamily(t *testing.T) { + tests := []struct { + name string + code []byte + want Op + }{ + {name: "long to float register", code: []byte{0xf3, 0x0f, 0x2a, 0xc8}, want: "CVTSL2SS"}, + {name: "long to float memory", code: []byte{0xf3, 0x0f, 0x2a, 0x48, 0x08}, want: "CVTSL2SS"}, + {name: "quad to float register", code: []byte{0xf3, 0x48, 0x0f, 0x2a, 0xc8}, want: "CVTSQ2SS"}, + {name: "quad to float memory", code: []byte{0xf3, 0x48, 0x0f, 0x2a, 0x48, 0x08}, want: "CVTSQ2SS"}, + {name: "long to double register", code: []byte{0xf2, 0x0f, 0x2a, 0xc8}, want: "CVTSL2SD"}, + {name: "long to double memory", code: []byte{0xf2, 0x0f, 0x2a, 0x48, 0x08}, want: "CVTSL2SD"}, + {name: "quad to double register", code: []byte{0xf2, 0x48, 0x0f, 0x2a, 0xc8}, want: "CVTSQ2SD"}, + {name: "quad to double memory", code: []byte{0xf2, 0x48, 0x0f, 0x2a, 0x48, 0x08}, want: "CVTSQ2SD"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + fn := Func{} + for _, value := range test.code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || got.Instrs[0].Op != test.want || len(got.Instrs[0].Args) != 2 { + t.Fatalf("decoded %#x as %#v, want one %s", test.code, got.Instrs, test.want) + } + }) + } +} + +func TestX86RawDecoderNormalizesCompleteScalarFloatIntegerFamily(t *testing.T) { + for _, goarch := range []string{"386", "amd64"} { + for _, precision := range []struct { + name string + prefix byte + }{ + {name: "SS", prefix: 0xf3}, + {name: "SD", prefix: 0xf2}, + } { + for _, conversion := range []struct { + name string + opcode byte + }{ + {name: "CVT", opcode: 0x2d}, + {name: "CVTT", opcode: 0x2c}, + } { + for _, width := range []struct { + name string + rex []byte + }{ + {name: "L"}, + {name: "Q", rex: []byte{0x48}}, + } { + if goarch == "386" && width.name == "Q" { + continue + } + for _, source := range []struct { + name string + modRM byte + disp []byte + }{ + {name: "register", modRM: 0xc1}, + {name: "memory", modRM: 0x43, disp: []byte{0x08}}, + } { + name := goarch + "/" + conversion.name + precision.name + "2S" + width.name + "/" + source.name + t.Run(name, func(t *testing.T) { + code := []byte{precision.prefix} + code = append(code, width.rex...) + code = append(code, 0x0f, conversion.opcode, source.modRM) + code = append(code, source.disp...) + fn := Func{} + for _, value := range code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, goarch) + if err != nil { + t.Fatal(err) + } + want := Op(conversion.name + precision.name + "2S" + width.name) + if len(got.Instrs) != 1 || got.Instrs[0].Op != want || len(got.Instrs[0].Args) != 2 { + t.Fatalf("decoded %#x as %#v, want one %s", code, got.Instrs, want) + } + }) + } + } + } + } + } +} + +func TestTranslateX86RawScalarFloatIntegerReportedEncoding(t *testing.T) { + const source = `TEXT rawScalarFloatInteger(SB),$0-0 + LONG $0x2c0f48f2 + BYTE $0xc0 // CVTTSD2SQ X0, AX + RET +` + for _, triple := range []string{ + "x86_64-apple-darwin", + "x86_64-unknown-linux-gnu", + "x86_64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "rawScalarFloatInteger": {Name: "rawScalarFloatInteger", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "fptosi double") || !strings.Contains(ir, " to i64") { + t.Fatalf("raw CVTTSD2SQ semantics missing:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "raw-scalar-float-integer.ll", "raw-scalar-float-integer.o", ir) + }) + } +} + +func TestX86RawDecoderNormalizesCompleteMOVNTDQFamily(t *testing.T) { + tests := []struct { + name string + code []byte + reg Reg + base Reg + }{ + {name: "low vector and base registers", code: []byte{0x66, 0x0f, 0xe7, 0x13}, reg: Reg("X2"), base: BX}, + {name: "extended vector register", code: []byte{0x66, 0x44, 0x0f, 0xe7, 0x1b}, reg: Reg("X11"), base: BX}, + {name: "extended base register", code: []byte{0x66, 0x41, 0x0f, 0xe7, 0x13}, reg: Reg("X2"), base: Reg("R11")}, + {name: "extended vector and base registers", code: []byte{0x66, 0x45, 0x0f, 0xe7, 0x1b}, reg: Reg("X11"), base: Reg("R11")}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + fn := Func{} + for _, value := range test.code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || got.Instrs[0].Op != "MOVNTO" || len(got.Instrs[0].Args) != 2 || got.Instrs[0].Args[0].Reg != test.reg || got.Instrs[0].Args[1].Mem.Base != test.base { + t.Fatalf("decoded %#x as %#v, want MOVNTO %s, (%s)", test.code, got.Instrs, test.reg, test.base) + } + }) + } +} + +func TestTranslateAMD64MOVNTOCompleteOperandForm(t *testing.T) { + const source = `TEXT movnto(SB),$0-0 + MOVNTO X2, 32(BX)(R8*1) + MOVNTO X11, sink<>(SB) + RET + +GLOBL sink<>(SB),$16 +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"movnto": {Name: "movnto", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if count := strings.Count(ir, "store <16 x i8> %"); count != 2 { + t.Fatalf("MOVNTO emitted %d vector stores, want 2:\n%s", count, ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-movnto.ll", "amd64-movnto.o", ir) +} + +func TestDecodedX86CacheLineWritebackCoversMemoryEncodingsWithoutFalsePositives(t *testing.T) { + for _, test := range []struct { + name string + code []byte + want string + ok bool + }{ + {name: "CLFLUSHOPT displacement", code: []byte{0x67, 0x66, 0x0f, 0xae, 0x78, 0x08}, want: "CLFLUSHOPT", ok: true}, + {name: "CLWB SIB displacement", code: []byte{0x66, 0x0f, 0xae, 0xb4, 0x24, 0x78, 0x56, 0x34, 0x12}, want: "CLWB", ok: true}, + {name: "CLWB REX base", code: []byte{0x66, 0x41, 0x0f, 0xae, 0x30}, want: "CLWB", ok: true}, + {name: "plain CLFLUSH", code: []byte{0x0f, 0xae, 0x38}}, + {name: "plain XSAVEOPT", code: []byte{0x0f, 0xae, 0x30}}, + {name: "register ModRM", code: []byte{0x66, 0x0f, 0xae, 0xf8}}, + {name: "opcode bytes in displacement", code: []byte{0x66, 0x8b, 0x80, 0x0f, 0xae, 0x38, 0x00}}, + } { + t.Run(test.name, func(t *testing.T) { + got, ok := decodedX86CacheLineWriteback(test.code) + if got != test.want || ok != test.ok { + t.Fatalf("decodedX86CacheLineWriteback(%#x) = %q, %v; want %q, %v", test.code, got, ok, test.want, test.ok) + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupReportedWencodeCLFLUSHOPT(t *testing.T) { + code := []byte{0x41, 0x66, 0x0f, 0xae, 0x3c, 0x09} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "wencode CLFLUSHOPT sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "CLFLUSHOPT" || len(decoded[0].Args) != 1 || decoded[0].Args[0].String() != "0(CX)(CX*1)" { + t.Fatalf("decoded %x as %#v, want CLFLUSHOPT 0(CX)(CX*1)", code, decoded) + } +} + +func encodeX86RawCacheLineWriteback(op Op, mode, base, index int) []byte { + extension := byte(7) + mandatory := op != "CLFLUSH" + if op == "CLWB" { + extension = 6 + } + var prefixes []byte + if mode == 64 { + rex := byte(0x40 | base/8 | index/8<<1) + if mandatory { + prefixes = append(prefixes, 0x66) + } + prefixes = append(prefixes, rex) + } else if mandatory { + prefixes = append(prefixes, 0x66) + } + mod := byte(0) + if base&7 == 5 { + mod = 1 + } + modRM := mod<<6 | extension<<3 | 4 + sib := byte(2<<6 | (index&7)<<3 | base&7) + code := append(prefixes, 0x0f, 0xae, modRM, sib) + if mod == 1 { + code = append(code, 0) + } + return code +} + +func TestDecodedX86RawCacheLineWritebackCompleteRegisterAddressFamily(t *testing.T) { + operations := []Op{"CLFLUSH", "CLFLUSHOPT", "CLWB"} + count := 0 + for _, mode := range []int{32, 64} { + registers := 8 + if mode == 64 { + registers = 16 + } + for _, op := range operations { + for base := 0; base < registers; base++ { + for index := 0; index < registers; index++ { + if index == 4 { + continue // SIB index 4 without X is the no-index encoding. + } + code := encodeX86RawCacheLineWriteback(op, mode, base, index) + got, length, ok, err := decodedX86CacheLineWritebackInstruction(code, mode) + baseReg, _ := decodedX86GeneralRegister(base) + indexReg, _ := decodedX86GeneralRegister(index) + wantMemory := MemRef{Base: baseReg, Index: indexReg, Scale: 4} + if err != nil || !ok || length != len(code) || got.Op != op || len(got.Args) != 1 || got.Args[0].Kind != OpMem || got.Args[0].Mem != wantMemory { + t.Fatalf("decode mode=%d %x = %+v, length=%d, ok=%v, err=%v; want %s %+v", mode, code, got, length, ok, err, op, wantMemory) + } + count++ + } + } + } + } + if count != 888 { + t.Fatalf("covered %d cache-line register-address encodings, want 888", count) + } +} + +func TestDecodedX86RawCacheLineWritebackMemoryAndInvalidForms(t *testing.T) { + for _, test := range []struct { + name string + code []byte + mode int + op Op + mem MemRef + }{ + {name: "CLFLUSH base", code: []byte{0x0f, 0xae, 0x3b}, mode: 64, op: "CLFLUSH", mem: MemRef{Base: BX}}, + {name: "CLFLUSHOPT disp8", code: []byte{0x66, 0x0f, 0xae, 0x7e, 0x7f}, mode: 64, op: "CLFLUSHOPT", mem: MemRef{Base: SI, Off: 127}}, + {name: "CLWB disp32", code: []byte{0x66, 0x0f, 0xae, 0xb7, 0x78, 0x56, 0x34, 0x12}, mode: 64, op: "CLWB", mem: MemRef{Base: DI, Off: 0x12345678}}, + {name: "CLFLUSHOPT ineffective REX before 66", code: []byte{0x41, 0x66, 0x0f, 0xae, 0x3c, 0x09}, mode: 64, op: "CLFLUSHOPT", mem: MemRef{Base: CX, Index: CX, Scale: 1}}, + {name: "CLFLUSHOPT effective REX after 66", code: []byte{0x66, 0x41, 0x0f, 0xae, 0x3c, 0x09}, mode: 64, op: "CLFLUSHOPT", mem: MemRef{Base: "R9", Index: CX, Scale: 1}}, + {name: "CLWB FS extended SIB", code: []byte{0x64, 0x66, 0x43, 0x0f, 0xae, 0x74, 0x8b, 0x20}, mode: 64, op: "CLWB", mem: MemRef{Segment: FS, Base: "R11", Index: "R9", Scale: 4, Off: 32}}, + {name: "CLFLUSHOPT 386 absolute", code: []byte{0x66, 0x0f, 0xae, 0x3d, 0x78, 0x56, 0x34, 0x12}, mode: 32, op: "CLFLUSHOPT", mem: MemRef{Off: 0x12345678}}, + } { + t.Run(test.name, func(t *testing.T) { + got, length, ok, err := decodedX86CacheLineWritebackInstruction(test.code, test.mode) + if err != nil || !ok || length != len(test.code) || got.Op != test.op || len(got.Args) != 1 || got.Args[0].Kind != OpMem || got.Args[0].Mem != test.mem { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %s %+v", test.code, got, length, ok, err, test.op, test.mem) + } + }) + } + + for _, test := range []struct { + name string + code []byte + mode int + }{ + {name: "address override", code: []byte{0x67, 0x66, 0x0f, 0xae, 0x38}, mode: 64}, + {name: "REX.W", code: []byte{0x66, 0x48, 0x0f, 0xae, 0x38}, mode: 64}, + {name: "REX.R", code: []byte{0x66, 0x44, 0x0f, 0xae, 0x38}, mode: 64}, + {name: "register operand", code: []byte{0x66, 0x0f, 0xae, 0xf8}, mode: 64}, + {name: "RIP relative", code: []byte{0x66, 0x0f, 0xae, 0x3d, 0, 0, 0, 0}, mode: 64}, + {name: "truncated SIB", code: []byte{0x66, 0x0f, 0xae, 0x3c}, mode: 64}, + {name: "truncated disp8", code: []byte{0x66, 0x0f, 0xae, 0x78}, mode: 64}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86CacheLineWritebackInstruction(test.code, test.mode) + if !ok || err == nil { + t.Fatalf("invalid encoding %x returned ok=%v err=%v", test.code, ok, err) + } + }) + } + for _, code := range [][]byte{ + {0x0f, 0xae, 0x30}, // XSAVEOPT, not CLWB. + {0x66, 0x0f, 0xae, 0x28}, // unrelated ModRM extension. + {0x66, 0x0f, 0xaf, 0x38}, // unrelated opcode. + {0x66, 0x0f}, // truncated before the opcode can be identified. + {0xf2, 0x66, 0x0f, 0xae, 0x38}, // unsupported mandatory prefix combination. + {0x66, 0x0f, 0xae, 0x38, 0x0f, 0xae, 0x38}, // only the first instruction is consumed. + } { + _, length, ok, err := decodedX86CacheLineWritebackInstruction(code, 64) + if len(code) == 7 { + if err != nil || !ok || length != 4 { + t.Fatalf("concatenated encoding %x returned length=%d ok=%v err=%v", code, length, ok, err) + } + continue + } + if ok || err != nil { + t.Fatalf("unrelated encoding %x returned ok=%v err=%v", code, ok, err) + } + } +} + +func TestTranslateX86RawAliasesThroughLLVM22(t *testing.T) { + const source = `TEXT rawaliases(SB),$0-0 + BYTE $0x66; BYTE $0x0f; BYTE $0x6b; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0x76; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0x66; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0xf5; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0xf4; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0xf2; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0xe2; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0xd2; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0xfa; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0x6a; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0x69; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0x62; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0x61; BYTE $0xca + BYTE $0x66; BYTE $0x0f; BYTE $0x6f; BYTE $0xc1 + BYTE $0xf3; BYTE $0x0f; BYTE $0x6f; BYTE $0xc1 + BYTE $0xf2; BYTE $0x0f; BYTE $0x10; BYTE $0xc1 + BYTE $0x66; BYTE $0x0f; BYTE $0xae; BYTE $0x38 + BYTE $0x66; BYTE $0x0f; BYTE $0xae; BYTE $0x30 + RET +` + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + } { + t.Run(target.goarch, func(t *testing.T) { + requireX86GoAssemblerResult(t, target.goarch, source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"rawaliases": {Name: "rawaliases", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"clflushopt $0", "clwb $0", "+clflushopt,+clwb"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw alias lowering omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "x86-raw-aliases.ll", "x86-raw-aliases.o", ir) + }) + } +} diff --git a/amd64_raw_align_right_test.go b/amd64_raw_align_right_test.go new file mode 100644 index 00000000..5ea0f075 --- /dev/null +++ b/amd64_raw_align_right_test.go @@ -0,0 +1,216 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86RawPALIGNR(immediate byte, mode, source, destination int) []byte { + code := []byte{0x66} + if mode == 64 { + code = append(code, byte(0x40|destination/8<<2|source/8)) + } + modRM := byte(0xc0 | destination&7<<3 | source&7) + return append(code, 0x0f, 0x3a, 0x0f, modRM, immediate) +} + +func encodeX86RawVEXVPALIGNR(immediate byte, wide bool, first, second, destination int) []byte { + p0 := byte((1-destination/8)<<7 | 1<<6 | (1-first/8)<<5 | 3) + p1 := byte((^second&15)<<3 | 1) + if wide { + p1 |= 4 + } + modRM := byte(0xc0 | destination&7<<3 | first&7) + return []byte{0xc4, p0, p1, 0x0f, modRM, immediate} +} + +func encodeX86RawEVEXVPALIGNR(immediate, vectorBits byte, mask int, zeroing bool, first, second, destination int) []byte { + p0 := byte((^destination>>3)&1)<<7 | + byte((^first>>4)&1)<<6 | + byte((^first>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | 3 + p1 := byte(^second&15)<<3 | 5 + p2 := vectorBits<<5 | byte((^second>>4)&1)<<3 | byte(mask) + if zeroing { + p2 |= 0x80 + } + modRM := byte(0xc0 | destination&7<<3 | first&7) + return []byte{0x62, p0, p1, p2, 0x0f, modRM, immediate} +} + +func TestDecodeX86RawDirectiveGroupReportedIPFSVPALIGNR(t *testing.T) { + code := []byte{0xc4, 0xe3, 0x41, 0x0f, 0xc6, 0x04} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "IPFS VPALIGNR sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + const want = "VPALIGNR $4, X6, X7, X0" + if len(decoded) != 1 || !strings.HasPrefix(decoded[0].Raw, want+" ") { + t.Fatalf("decoded %x as %#v, want %q", code, decoded, want) + } +} + +func TestDecodedX86RawPALIGNRCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, mode := range []int{32, 64} { + registers := 8 + if mode == 64 { + registers = 16 + } + for source := 0; source < registers; source++ { + for destination := 0; destination < registers; destination++ { + immediate := byte(source*16 + destination) + code := encodeX86RawPALIGNR(immediate, mode, source, destination) + got, length, ok, err := decodedX86PackedAlignRightInstruction(code, mode) + want := fmt.Sprintf("PALIGNR $%d, X%d, X%d", immediate, source, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode mode=%d %x = %+v, length=%d, ok=%v, err=%v; want %q", mode, code, got, length, ok, err, want) + } + count++ + } + } + } + if count != 320 { + t.Fatalf("covered %d PALIGNR register encodings, want 320", count) + } +} + +func TestDecodedX86RawVPALIGNRCompleteVEXRegisterFamily(t *testing.T) { + count := 0 + for _, wide := range []bool{false, true} { + vectorName := "X" + if wide { + vectorName = "Y" + } + for first := 0; first < 16; first++ { + for second := 0; second < 16; second++ { + for destination := 0; destination < 16; destination++ { + immediate := byte(first*16 + destination) + code := encodeX86RawVEXVPALIGNR(immediate, wide, first, second, destination) + got, length, ok, err := decodedX86PackedAlignRightInstruction(code, 64) + want := fmt.Sprintf("VPALIGNR $%d, %s%d, %s%d, %s%d", immediate, vectorName, first, vectorName, second, vectorName, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + if count != 8192 { + t.Fatalf("covered %d VEX VPALIGNR register encodings, want 8192", count) + } +} + +func TestDecodedX86RawVPALIGNRCompleteEVEXRegisterFamily(t *testing.T) { + count := 0 + for vectorBits, vectorName := range []string{"X", "Y", "Z"} { + for _, masking := range []struct { + mask int + zeroing bool + suffix string + }{ + {}, + {mask: 3}, + {mask: 7, zeroing: true, suffix: ".Z"}, + } { + for first := 0; first < 32; first++ { + for second := 0; second < 32; second++ { + for destination := 0; destination < 32; destination++ { + immediate := byte(first*8 + destination) + code := encodeX86RawEVEXVPALIGNR(immediate, byte(vectorBits), masking.mask, masking.zeroing, first, second, destination) + got, length, ok, err := decodedX86PackedAlignRightInstruction(code, 64) + args := []string{ + fmt.Sprintf("$%d", immediate), + fmt.Sprintf("%s%d", vectorName, first), + fmt.Sprintf("%s%d", vectorName, second), + } + if masking.mask != 0 { + args = append(args, fmt.Sprintf("K%d", masking.mask)) + } + args = append(args, fmt.Sprintf("%s%d", vectorName, destination)) + want := "VPALIGNR" + masking.suffix + " " + strings.Join(args, ", ") + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + } + if count != 294912 { + t.Fatalf("covered %d EVEX VPALIGNR register encodings, want 294912", count) + } +} + +func TestDecodedX86RawPackedAlignRightMemoryAndInvalidForms(t *testing.T) { + for _, test := range []struct { + name string + code []byte + want string + }{ + { + name: "legacy extended SIB", + code: []byte{0x64, 0x66, 0x47, 0x0f, 0x3a, 0x0f, 0x64, 0x8b, 0x20, 0xff}, + want: "PALIGNR $255, 32(R11)(R9*4)(FS), X12", + }, + { + name: "VEX extended SIB", + code: []byte{0x65, 0xc4, 0x03, 0x15, 0x0f, 0x64, 0x8b, 0x20, 0xfe}, + want: "VPALIGNR $254, 32(R11)(R9*4)(GS), Y13, Y12", + }, + { + name: "EVEX compressed disp8 zero mask", + code: []byte{0x64, 0x62, 0x03, 0x15, 0xc2, 0x0f, 0x64, 0x8b, 0x7f, 0xfd}, + want: "VPALIGNR.Z $253, 8128(R11)(R9*4)(FS), Z29, K2, Z28", + }, + } { + t.Run(test.name, func(t *testing.T) { + got, length, ok, err := decodedX86PackedAlignRightInstruction(test.code, 64) + if err != nil || !ok || length != len(test.code) || got.Raw != test.want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", test.code, got, length, ok, err, test.want) + } + }) + } + + for _, test := range []struct { + name string + mode int + encoding []byte + wantOK bool + }{ + {name: "VEX 386 operand limit", mode: 32, encoding: encodeX86RawVEXVPALIGNR(1, false, 0, 1, 2), wantOK: true}, + {name: "EVEX 386 operand limit", mode: 32, encoding: encodeX86RawEVEXVPALIGNR(1, 0, 0, false, 0, 1, 2), wantOK: true}, + {name: "VEX wrong pp", mode: 64, encoding: []byte{0xc4, 0xe3, 0x40, 0x0f, 0xc6, 4}, wantOK: true}, + {name: "VEX W", mode: 64, encoding: []byte{0xc4, 0xe3, 0xc1, 0x0f, 0xc6, 4}, wantOK: true}, + {name: "VEX truncated immediate", mode: 64, encoding: []byte{0xc4, 0xe3, 0x41, 0x0f, 0xc6}, wantOK: true}, + {name: "EVEX W", mode: 64, encoding: []byte{0x62, 0xf3, 0x85, 0x08, 0x0f, 0xc2, 4}, wantOK: true}, + {name: "EVEX broadcast", mode: 64, encoding: []byte{0x62, 0xf3, 0x05, 0x18, 0x0f, 0x02, 4}, wantOK: true}, + {name: "EVEX reserved vector length", mode: 64, encoding: []byte{0x62, 0xf3, 0x05, 0x68, 0x0f, 0xc2, 4}, wantOK: true}, + {name: "EVEX zero without mask", mode: 64, encoding: []byte{0x62, 0xf3, 0x05, 0x88, 0x0f, 0xc2, 4}, wantOK: true}, + {name: "EVEX truncated immediate", mode: 64, encoding: []byte{0x62, 0xf3, 0x05, 0x08, 0x0f, 0xc2}, wantOK: true}, + {name: "legacy REX.W", mode: 64, encoding: []byte{0x66, 0x48, 0x0f, 0x3a, 0x0f, 0xc2, 4}, wantOK: true}, + {name: "legacy RIP relative", mode: 64, encoding: []byte{0x66, 0x0f, 0x3a, 0x0f, 0x05, 0, 0, 0, 0, 4}, wantOK: true}, + {name: "address override", mode: 64, encoding: []byte{0x67, 0xc4, 0xe3, 0x41, 0x0f, 0xc6, 4}, wantOK: true}, + {name: "wrong opcode", mode: 64, encoding: []byte{0xc4, 0xe3, 0x41, 0x0e, 0xc6, 4}}, + {name: "wrong map", mode: 64, encoding: []byte{0xc4, 0xe2, 0x41, 0x0f, 0xc6, 4}}, + {name: "legacy missing 66", mode: 64, encoding: []byte{0x0f, 0x3a, 0x0f, 0xc2, 4}}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86PackedAlignRightInstruction(test.encoding, test.mode) + if ok != test.wantOK { + t.Fatalf("encoding %x returned ok=%v err=%v, want ok=%v", test.encoding, ok, err, test.wantOK) + } + if test.wantOK && err == nil { + t.Fatalf("invalid encoding %x was accepted", test.encoding) + } + if !test.wantOK && err != nil { + t.Fatalf("unrelated encoding %x returned err=%v", test.encoding, err) + } + }) + } +} diff --git a/amd64_raw_andn.go b/amd64_raw_andn.go new file mode 100644 index 00000000..3ded5133 --- /dev/null +++ b/amd64_raw_andn.go @@ -0,0 +1,79 @@ +package plan9asm + +import "fmt" + +// decodedX86ANDNInstruction recognizes the complete BMI1 ANDNL/ANDNQ +// Yml,Yrl,Yrl family. x/arch v0.14 reports this VEX.NDS encoding as an +// unknown AVX opcode, so recover every register and safe ModRM/SIB memory form +// before generic decoding. +func decodedX86ANDNInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if len(code) < i+4 || code[i] != 0xc4 || code[i+1]&0x1f != 2 || code[i+3] != 0xf2 { + return Instr{}, 0, false, nil + } + ok = true + if mode != 32 && mode != 64 { + return Instr{}, 0, true, fmt.Errorf("unsupported x86 mode %d", mode) + } + vexExt, vexByte := code[i+1], code[i+2] + if vexByte&7 != 0 { + return Instr{}, 0, true, fmt.Errorf("reserved ANDN VEX prefix") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if len(code) <= i+4 { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + rExt := int(^vexExt>>7) & 1 + xExt := int(^vexExt>>6) & 1 + bExt := int(^vexExt>>5) & 1 + width64 := vexByte&0x80 != 0 + secondNumber := int(^vexByte>>3) & 15 + modRM := code[i+4] + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (secondNumber >= 8 || destinationNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended source or destination register in 32-bit mode") + } + second, valid := decodedX86GeneralRegister(secondNumber) + if !valid { + return Instr{}, 0, true, fmt.Errorf("invalid second-source register %d", secondNumber) + } + destination, valid := decodedX86GeneralRegister(destinationNumber) + if !valid { + return Instr{}, 0, true, fmt.Errorf("invalid destination register %d", destinationNumber) + } + first, consumed, err := decodedX86VEXRMSource(code[i+4:], mode, bExt, xExt, segment) + if err != nil { + return Instr{}, 0, true, err + } + op := Op("ANDNL") + if width64 && mode == 64 { + op = "ANDNQ" + } + instruction = Instr{ + Op: op, + Args: []Operand{first, {Kind: OpReg, Reg: second}, {Kind: OpReg, Reg: destination}}, + Raw: fmt.Sprintf("%s %s, %s, %s", op, first.String(), second, destination), + } + return instruction, i + 4 + consumed, true, nil +} diff --git a/amd64_raw_blend_imm_test.go b/amd64_raw_blend_imm_test.go new file mode 100644 index 00000000..7f7a13d4 --- /dev/null +++ b/amd64_raw_blend_imm_test.go @@ -0,0 +1,193 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +type rawImmediatePackedBlendSpec struct { + opcode byte + legacy Op + vector Op +} + +var rawImmediatePackedBlendSpecs = []rawImmediatePackedBlendSpec{ + {opcode: 0x0e, legacy: "PBLENDW", vector: "VPBLENDW"}, + {opcode: 0x0c, legacy: "BLENDPS", vector: "VBLENDPS"}, + {opcode: 0x0d, legacy: "BLENDPD", vector: "VBLENDPD"}, + {opcode: 0x02, vector: "VPBLENDD"}, +} + +func encodeX86RawLegacyImmediatePackedBlend(spec rawImmediatePackedBlendSpec, source, destination int, immediate byte) []byte { + rex := byte(0x40 | source>>3&1 | destination>>3&1<<2) + code := []byte{0x66} + if rex != 0x40 { + code = append(code, rex) + } + return append(code, 0x0f, 0x3a, spec.opcode, byte(0xc0|destination&7<<3|source&7), immediate) +} + +func encodeX86RawVEXImmediatePackedBlend(spec rawImmediatePackedBlendSpec, vectorBits byte, first, second, destination int, immediate byte) []byte { + p0 := byte((^destination>>3)&1)<<7 | 0x40 | byte((^first>>3)&1)<<5 | 3 + p1 := byte(^second&15)<<3 | vectorBits<<2 | 1 + return []byte{0xc4, p0, p1, spec.opcode, byte(0xc0 | destination&7<<3 | first&7), immediate} +} + +func TestDecodeX86RawDirectiveGroupReportedSegDSPVBLENDPD(t *testing.T) { + // vblendpd $12, %ymm1, %ymm0, %ymm0; + // vunpcklps %xmm3, %xmm5, %xmm0 + code := []byte{0xc4, 0xe3, 0x7d, 0x0d, 0xc1, 0x0c, 0xc5, 0xd0, 0x14, 0xc3} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "segdsp VBLENDPD sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 2 || !strings.HasPrefix(decoded[0].Raw, "VBLENDPD $12, Y1, Y0, Y0 ") { + t.Fatalf("decoded %x as %#v", code, decoded) + } +} + +func TestDecodedX86RawImmediatePackedBlendCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, spec := range rawImmediatePackedBlendSpecs { + if spec.legacy != "" { + for source := 0; source < 16; source++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86RawLegacyImmediatePackedBlend(spec, source, destination, 0xa5) + got, length, ok, err := decodedX86ImmediatePackedBlendInstruction(code, 64) + want := fmt.Sprintf("%s $165, X%d, X%d", spec.legacy, source, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + for vectorBits := byte(0); vectorBits < 2; vectorBits++ { + vectorName := [...]string{"X", "Y"}[vectorBits] + for first := 0; first < 16; first++ { + for second := 0; second < 16; second++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86RawVEXImmediatePackedBlend(spec, vectorBits, first, second, destination, 0x5a) + got, length, ok, err := decodedX86ImmediatePackedBlendInstruction(code, 64) + want := fmt.Sprintf("%s $90, %s%d, %s%d, %s%d", spec.vector, vectorName, first, vectorName, second, vectorName, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + } + if count != 33536 { + t.Fatalf("covered %d immediate packed-blend register encodings, want 33536", count) + } +} + +func TestDecodedX86RawImmediatePackedBlendMemoryAndInvalidForms(t *testing.T) { + legacyMemory := []byte{0x66, 0x47, 0x0f, 0x3a, 0x0e, 0x7c, 0x8b, 0x01, 0x7f} + got, length, ok, err := decodedX86ImmediatePackedBlendInstruction(legacyMemory, 64) + wantMemory := MemRef{Base: "R11", Index: "R9", Scale: 4, Off: 1} + if err != nil || !ok || length != len(legacyMemory) || got.Op != "PBLENDW" || got.Args[0].Imm != 127 || got.Args[2].String() != "X15" || got.Args[1].Kind != OpMem || !reflect.DeepEqual(got.Args[1].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", legacyMemory, got, length, ok, err) + } + vexMemory := []byte{0xc4, 0x03, 0x75, 0x0d, 0x7c, 0x8b, 0x02, 0xfe} + got, length, ok, err = decodedX86ImmediatePackedBlendInstruction(vexMemory, 64) + wantMemory.Off = 2 + if err != nil || !ok || length != len(vexMemory) || got.Op != "VBLENDPD" || got.Args[0].Imm != 254 || got.Args[2].String() != "Y1" || got.Args[3].String() != "Y15" || got.Args[1].Kind != OpMem || !reflect.DeepEqual(got.Args[1].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", vexMemory, got, length, ok, err) + } + + validLegacy := encodeX86RawLegacyImmediatePackedBlend(rawImmediatePackedBlendSpecs[0], 7, 7, 1) + validVEX := encodeX86RawVEXImmediatePackedBlend(rawImmediatePackedBlendSpecs[0], 0, 7, 7, 7, 1) + for name, invalid := range map[string][]byte{ + "legacy missing immediate": validLegacy[:len(validLegacy)-1], + "vex missing immediate": validVEX[:len(validVEX)-1], + "vex W": {validVEX[0], validVEX[1], validVEX[2] | 0x80, validVEX[3], validVEX[4], validVEX[5]}, + "vex prefix": {validVEX[0], validVEX[1], validVEX[2] &^ 0x01, validVEX[3], validVEX[4], validVEX[5]}, + "address override": append([]byte{0x67}, validVEX...), + } { + if instruction, _, matched, decodeErr := decodedX86ImmediatePackedBlendInstruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, invalid, instruction, matched, decodeErr) + } + } + if instruction, _, matched, decodeErr := decodedX86ImmediatePackedBlendInstruction(validVEX, 32); !matched || decodeErr == nil { + t.Fatalf("386 VEX encoding %x decoded as %+v, ok=%v, err=%v", validVEX, instruction, matched, decodeErr) + } +} + +func TestX86ImmediatePackedBlendGo127ArchitectureOracle(t *testing.T) { + const accepted386 = `TEXT ok(SB),$0-0 + PBLENDW $7, X6, X7 + BLENDPS $7, X6, X7 + BLENDPD $7, X6, X7 + RET +` + requireX86GoAssemblerResult(t, "386", accepted386, true) + for _, instruction := range []string{ + "VPBLENDW $7, X0, X1, X2", + "VPBLENDD $7, Y0, Y1, Y2", + "VBLENDPS $7, X0, X1, X2", + "VBLENDPD $7, Y0, Y1, Y2", + } { + requireX86GoAssemblerResult(t, "386", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + } +} + +func TestTranslateX86RawImmediatePackedBlendTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + registerMax int + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin", registerMax: 15}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", registerMax: 15}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc", registerMax: 15}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu", registerMax: 7}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc", registerMax: 7}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT raw_immediate_packed_blend(SB),NOSPLIT,$0-0\n") + for _, spec := range rawImmediatePackedBlendSpecs { + var encodings [][]byte + if spec.legacy != "" { + encodings = append(encodings, encodeX86RawLegacyImmediatePackedBlend(spec, target.registerMax, target.registerMax, 0xa5)) + } + if target.goarch == "amd64" { + encodings = append(encodings, encodeX86RawVEXImmediatePackedBlend(spec, 1, target.registerMax, target.registerMax, target.registerMax, 0x5a)) + } + for _, encoding := range encodings { + for _, value := range encoding { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "raw_immediate_packed_blend": {Name: "raw_immediate_packed_blend", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-immediate-packed-blend-"+target.name+".ll", "raw-immediate-packed-blend-"+target.name+".o", ll) + }) + } +} diff --git a/amd64_raw_decode_test.go b/amd64_raw_decode_test.go new file mode 100644 index 00000000..202cd113 --- /dev/null +++ b/amd64_raw_decode_test.go @@ -0,0 +1,356 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestAMD64RawDirectiveSequenceUsesSemanticLowering(t *testing.T) { + source := `TEXT rawLoad(SB), NOSPLIT, $256-0 + MOVQ $0, R11 + BYTE $0x4e + BYTE $0x0f + BYTE $0xb7 + BYTE $0x7c + BYTE $0x5c + BYTE $0x78 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{ + "rawLoad": {Name: "rawLoad", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("Translate() error = %v", err) + } + if strings.Contains(ir, "module asm") { + t.Fatalf("raw instructions bypassed semantic lowering:\n%s", ir) + } + if !strings.Contains(ir, "load i16") || !strings.Contains(ir, "zext i16") { + t.Fatalf("decoded MOVWQZX semantics missing:\n%s", ir) + } +} + +func TestX86RawOnlyFunctionUsesSemanticLowering(t *testing.T) { + for _, test := range []struct { + name string + goarch string + triple string + source string + }{ + { + name: "amd64", + goarch: "amd64", + triple: "x86_64-unknown-linux-gnu", + source: "TEXT raw(SB), NOSPLIT, $0-0\nBYTE $0x90\nBYTE $0xc3\n", + }, + { + name: "386", + goarch: "386", + triple: "i386-unknown-linux-gnu", + source: "TEXT raw(SB), NOSPLIT, $0-0\nBYTE $0x90\nBYTE $0xc3\n", + }, + } { + t.Run(test.name, func(t *testing.T) { + file, err := Parse(ArchAMD64, test.source) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + ir, err := Translate(file, Options{ + Goarch: test.goarch, + TargetTriple: test.triple, + Sigs: map[string]FuncSig{ + "raw": {Name: "raw", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("Translate() error = %v", err) + } + if strings.Contains(ir, "module asm") { + t.Fatalf("raw-only function bypassed instruction validation:\n%s", ir) + } + if !strings.Contains(ir, "define void @raw()") || !strings.Contains(ir, "ret void") { + t.Fatalf("semantic function body missing:\n%s", ir) + } + }) + } +} + +func TestX86RawPCRelativeInstructionOutsideDirectiveGroupFailsClosed(t *testing.T) { + source := `TEXT rawBranch(SB), NOSPLIT, $0-0 + MOVQ $0, AX + BYTE $0xeb + BYTE $0x7f + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + _, err = Translate(file, Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{ + "rawBranch": {Name: "rawBranch", Ret: Void}, + }, + }) + if err == nil || !strings.Contains(err.Error(), "PC-relative") { + t.Fatalf("Translate() error = %v, want explicit PC-relative raw-instruction rejection", err) + } +} + +func TestX86RawInternalConditionalBranchCompleteFamily(t *testing.T) { + targets := []struct { + goarch string + triple string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + } + forms := []struct { + name string + bytes func(condition byte) []byte + }{ + {name: "short_forward", bytes: func(condition byte) []byte { + return []byte{0x70 + condition, 0x01, 0x90, 0xc3} + }}, + {name: "short_backward", bytes: func(condition byte) []byte { + return []byte{0x90, 0x70 + condition, 0xfd, 0xc3} + }}, + {name: "near_forward", bytes: func(condition byte) []byte { + return []byte{0x0f, 0x80 + condition, 0x01, 0, 0, 0, 0x90, 0xc3} + }}, + {name: "near_backward", bytes: func(condition byte) []byte { + return []byte{0x90, 0x0f, 0x80 + condition, 0xf9, 0xff, 0xff, 0xff, 0xc3} + }}, + } + + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range targets { + t.Run(target.goarch, func(t *testing.T) { + var source strings.Builder + sigs := make(map[string]FuncSig) + for condition := byte(0); condition < 16; condition++ { + for _, form := range forms { + name := fmt.Sprintf("rawJcc_%02x_%s", condition, form.name) + fmt.Fprintf(&source, "TEXT %s(SB), NOSPLIT, $0-0\n", name) + for _, value := range form.bytes(condition) { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + sigs[name] = FuncSig{Name: name, Ret: Void} + } + } + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: target.goarch, TargetTriple: target.triple, Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "raw_jcc") { + t.Fatalf("synthetic raw branch labels missing:\n%s", ir) + } + compileLLVMToObject(t, llc, target.triple, "raw-jcc-"+target.goarch+".ll", "raw-jcc-"+target.goarch+".o", ir) + }) + } +} + +func TestX86RawMULXReportedEncoding(t *testing.T) { + const source = `TEXT rawMULX(SB), NOSPLIT, $0-0 + BYTE $0xc4 + BYTE $0x42 + BYTE $0xe3 + BYTE $0xf6 + BYTE $0xf6 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"rawMULX": {Name: "rawMULX", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "raw-mulx.ll", "raw-mulx.o", ir) +} + +func TestX86RawMULXCompleteGoAssemblerForms(t *testing.T) { + // Go's x86 table defines both register and Yml memory sources for MULXL + // and (on amd64) MULXQ. Exercise both widths plus direct, SIB, disp8 and + // base-less disp32 ModRM forms, including extended registers. + targets := []struct { + goarch string + triple string + forms [][]byte + }{ + { + goarch: "amd64", + triple: "x86_64-unknown-linux-gnu", + forms: [][]byte{ + {0xc4, 0x42, 0xe3, 0xf6, 0xf6}, // MULXQ R14, BX, R14 + {0xc4, 0x42, 0x3b, 0xf6, 0xfe}, // MULXL R14, R8, R15 + {0xc4, 0x22, 0xab, 0xf6, 0x5c, 0x88, 0x10}, // MULXQ 16(AX)(R9*4), R10, R11 + {0xc4, 0xe2, 0x6b, 0xf6, 0x5c, 0x48, 0x08}, // MULXL 8(AX)(CX*2), DX, BX + {0xc4, 0xe2, 0xfb, 0xf6, 0x0c, 0x25, 0x78, 0x56, 0x34, 0x12}, // MULXQ 0x12345678, AX, CX + }, + }, + { + goarch: "386", + triple: "i386-unknown-linux-gnu", + forms: [][]byte{ + {0xc4, 0xe2, 0x73, 0xf6, 0xd0}, // MULXL AX, CX, DX + {0xc4, 0xe2, 0x6b, 0xf6, 0x5c, 0x48, 0x08}, // MULXL 8(AX)(CX*2), DX, BX + {0xc4, 0xe2, 0x7b, 0xf6, 0x0d, 0x78, 0x56, 0x34, 0x12}, // MULXL 0x12345678, AX, CX + }, + }, + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range targets { + t.Run(target.goarch, func(t *testing.T) { + var source strings.Builder + sigs := make(map[string]FuncSig) + for i, encoding := range target.forms { + name := fmt.Sprintf("rawMULX_%d", i) + fmt.Fprintf(&source, "TEXT %s(SB), NOSPLIT, $0-0\n", name) + for _, value := range encoding { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + source.WriteString("\tRET\n") + sigs[name] = FuncSig{Name: name, Ret: Void} + } + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: target.goarch, TargetTriple: target.triple, Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-mulx-forms.ll", "raw-mulx-forms.o", ir) + }) + } +} + +func TestX86RawMULXRejectsLayoutDependentAddressForms(t *testing.T) { + tests := []struct { + name string + encoding []byte + }{ + {name: "address_size_override", encoding: []byte{0x67, 0xc4, 0xe2, 0x6b, 0xf6, 0x5c, 0x48, 0x08}}, + {name: "rip_relative", encoding: []byte{0xc4, 0xe2, 0xfb, 0xf6, 0x0d, 0, 0, 0, 0}}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawMULX(SB), NOSPLIT, $0-0\n") + for _, value := range test.encoding { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + _, err = Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawMULX": {Name: "rawMULX", Ret: Void}}}) + if err == nil || !strings.Contains(err.Error(), "source-layout safe") { + t.Fatalf("Translate() error = %v, want source-layout safety rejection", err) + } + }) + } +} + +func TestX86RawForwardJumpSkipsEmbeddedDataButStillLowersReachableCode(t *testing.T) { + const source = `TEXT rawSignature(SB), NOSPLIT, $0-0 + BYTE $0xeb + BYTE $0x04 + LONG $0xe77da1c4 + BYTE $0xc3 +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawSignature": {Name: "rawSignature", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if strings.Contains(ir, "module asm") || !strings.Contains(ir, "ret void") { + t.Fatalf("reachable raw control flow was not lowered semantically:\n%s", ir) + } +} + +func encodeX86RawRetpoline(register int) []byte { + return []byte{0xe8, 0x04, 0, 0, 0, 0xf3, 0x90, 0xeb, 0xfc, byte(0x48 | (register&8)>>1), 0x89, byte(0x04 | (register&7)<<3), 0x24, 0xc3} +} + +func TestX86RawRetpolineFamilyLowersToIndirectTailCalls(t *testing.T) { + names := []string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"} + var source strings.Builder + sigs := map[string]FuncSig{} + for register, name := range names { + if register == 4 { + continue + } + function := "retpoline" + name + fmt.Fprintf(&source, "TEXT %s(SB),NOSPLIT,$0-0\n", function) + for _, value := range encodeX86RawRetpoline(register) { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + sigs[function] = FuncSig{Name: function, Ret: Void} + if got, ok := x86RawRetpolineTarget(encodeX86RawRetpoline(register)); !ok || got != Reg(name) { + t.Fatalf("decoded retpoline register %d as %s, ok=%v", register, got, ok) + } + } + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + if strings.Contains(ir, "module asm") || !strings.Contains(ir, "call i64 %") || !strings.Contains(ir, "ret void") { + t.Fatalf("raw retpolines were not lowered as semantic indirect tail calls:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-retpoline.ll", "amd64-raw-retpoline.o", ir) +} + +func TestX86RawRetpolineDecoderRejectsNearMisses(t *testing.T) { + for _, offset := range []int{0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 13} { + nearMiss := append([]byte(nil), encodeX86RawRetpoline(0)...) + nearMiss[offset] ^= 1 + if _, ok := x86RawRetpolineTarget(nearMiss); ok { + t.Fatalf("retpoline decoder accepted byte %d near miss %#v", offset, nearMiss) + } + } + if _, ok := x86RawRetpolineTarget(encodeX86RawRetpoline(4)); ok { + t.Fatal("retpoline decoder accepted impossible SP target") + } +} diff --git a/amd64_raw_duplicate_test.go b/amd64_raw_duplicate_test.go new file mode 100644 index 00000000..9af336ff --- /dev/null +++ b/amd64_raw_duplicate_test.go @@ -0,0 +1,345 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "reflect" + "runtime" + "strings" + "testing" +) + +type rawDuplicateMoveSpec struct { + legacyPrefix byte + opcode byte + legacy Op + vector Op + double bool +} + +var rawDuplicateMoveSpecs = []rawDuplicateMoveSpec{ + {legacyPrefix: 0xf2, opcode: 0x12, legacy: "MOVDDUP", vector: "VMOVDDUP", double: true}, + {legacyPrefix: 0xf3, opcode: 0x16, legacy: "MOVSHDUP", vector: "VMOVSHDUP"}, + {legacyPrefix: 0xf3, opcode: 0x12, legacy: "MOVSLDUP", vector: "VMOVSLDUP"}, +} + +func encodeX86RawLegacyDuplicateMove(spec rawDuplicateMoveSpec, source, destination int) []byte { + rex := byte(0x40 | source>>3&1 | destination>>3&1<<2) + code := []byte{spec.legacyPrefix} + if rex != 0x40 { + code = append(code, rex) + } + return append(code, 0x0f, spec.opcode, byte(0xc0|destination&7<<3|source&7)) +} + +func encodeX86RawVEXDuplicateMove(spec rawDuplicateMoveSpec, vectorBits byte, source, destination int) []byte { + p0 := byte((^destination>>3)&1)<<7 | 0x40 | byte((^source>>3)&1)<<5 | 1 + pp := byte(2) + if spec.double { + pp = 3 + } + p1 := byte(0x78 | vectorBits<<2 | pp) + return []byte{0xc4, p0, p1, spec.opcode, byte(0xc0 | destination&7<<3 | source&7)} +} + +func encodeX86RawEVEXDuplicateMove(spec rawDuplicateMoveSpec, vectorBits byte, mask int, zeroing bool, source, destination int) []byte { + p0 := byte((^destination>>3)&1)<<7 | + byte((^source>>4)&1)<<6 | + byte((^source>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | 1 + pp := byte(2) + if spec.double { + pp = 3 + } + p1 := byte(0x7c | pp) + if spec.double { + p1 |= 0x80 + } + p2 := vectorBits<<5 | 0x08 | byte(mask) + if zeroing { + p2 |= 0x80 + } + return []byte{0x62, p0, p1, p2, spec.opcode, byte(0xc0 | destination&7<<3 | source&7)} +} + +func TestDecodeX86RawDirectiveGroupReportedSegDSPVMOVSHDUP(t *testing.T) { + // vmovshdup %xmm0, %xmm1; + // vpermilps $208, %xmm7, %xmm0 + code := []byte{0xc5, 0xfa, 0x16, 0xc8, 0xc4, 0xe3, 0x79, 0x04, 0xc7, 0xd0} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "segdsp VMOVSHDUP sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 2 || !strings.HasPrefix(decoded[0].Raw, "VMOVSHDUP X0, X1 ") { + t.Fatalf("decoded %x as %#v", code, decoded) + } +} + +func TestDecodedX86RawDuplicateMoveCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, spec := range rawDuplicateMoveSpecs { + for source := 0; source < 16; source++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86RawLegacyDuplicateMove(spec, source, destination) + got, length, ok, err := decodedX86DuplicateMoveInstruction(code, 64) + want := fmt.Sprintf("%s X%d, X%d", spec.legacy, source, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + for vectorBits := byte(0); vectorBits < 2; vectorBits++ { + vectorName := [...]string{"X", "Y"}[vectorBits] + for source := 0; source < 16; source++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86RawVEXDuplicateMove(spec, vectorBits, source, destination) + got, length, ok, err := decodedX86DuplicateMoveInstruction(code, 64) + want := fmt.Sprintf("%s %s%d, %s%d", spec.vector, vectorName, source, vectorName, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + for vectorBits := byte(0); vectorBits < 3; vectorBits++ { + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + for _, masking := range []struct { + mask int + zeroing bool + suffix string + }{{}, {mask: 3}, {mask: 7, zeroing: true, suffix: ".Z"}} { + for source := 0; source < 32; source++ { + for destination := 0; destination < 32; destination++ { + code := encodeX86RawEVEXDuplicateMove(spec, vectorBits, masking.mask, masking.zeroing, source, destination) + got, length, ok, err := decodedX86DuplicateMoveInstruction(code, 64) + args := []string{fmt.Sprintf("%s%d", vectorName, source)} + if masking.mask != 0 { + args = append(args, fmt.Sprintf("K%d", masking.mask)) + } + args = append(args, fmt.Sprintf("%s%d", vectorName, destination)) + want := string(spec.vector) + masking.suffix + " " + strings.Join(args, ", ") + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + } + if count != 29952 { + t.Fatalf("covered %d duplicate-move register encodings, want 29952", count) + } +} + +func TestDecodedX86RawDuplicateMoveMemoryAndInvalidForms(t *testing.T) { + legacyMemory := []byte{0xf3, 0x47, 0x0f, 0x16, 0x7c, 0x8b, 0x01} + got, length, ok, err := decodedX86DuplicateMoveInstruction(legacyMemory, 64) + wantMemory := MemRef{Base: "R11", Index: "R9", Scale: 4, Off: 1} + if err != nil || !ok || length != len(legacyMemory) || got.Op != "MOVSHDUP" || got.Args[1].String() != "X15" || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", legacyMemory, got, length, ok, err) + } + vexMemory := []byte{0xc4, 0x01, 0x7e, 0x16, 0x7c, 0x8b, 0x02} + got, length, ok, err = decodedX86DuplicateMoveInstruction(vexMemory, 64) + wantMemory.Off = 2 + if err != nil || !ok || length != len(vexMemory) || got.Op != "VMOVSHDUP" || got.Args[1].String() != "Y15" || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", vexMemory, got, length, ok, err) + } + evexMemory := []byte{0x62, 0xf1, 0xff, 0x8b, 0x12, 0x50, 0x02} + got, length, ok, err = decodedX86DuplicateMoveInstruction(evexMemory, 64) + wantMemory = MemRef{Base: "AX", Off: 16} + if err != nil || !ok || length != len(evexMemory) || got.Op != "VMOVDDUP.Z" || got.Args[1].String() != "K3" || got.Args[2].String() != "X2" || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", evexMemory, got, length, ok, err) + } + + validVEX := encodeX86RawVEXDuplicateMove(rawDuplicateMoveSpecs[1], 0, 7, 7) + validEVEX := encodeX86RawEVEXDuplicateMove(rawDuplicateMoveSpecs[1], 2, 0, false, 7, 5) + for name, invalid := range map[string][]byte{ + "vex W": {validVEX[0], validVEX[1], validVEX[2] | 0x80, validVEX[3], validVEX[4]}, + "vex vvvv": {validVEX[0], validVEX[1], validVEX[2] &^ 0x08, validVEX[3], validVEX[4]}, + "evex fixed bit": {validEVEX[0], validEVEX[1], validEVEX[2] &^ 0x04, validEVEX[3], validEVEX[4], validEVEX[5]}, + "evex wrong W": {validEVEX[0], validEVEX[1], validEVEX[2] | 0x80, validEVEX[3], validEVEX[4], validEVEX[5]}, + "evex vvvvv": {validEVEX[0], validEVEX[1], validEVEX[2] &^ 0x08, validEVEX[3] &^ 0x08, validEVEX[4], validEVEX[5]}, + "evex broadcast": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 0x10, validEVEX[4], validEVEX[5]}, + "evex reserved length": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 0x60, validEVEX[4], validEVEX[5]}, + "zero without mask": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 0x80, validEVEX[4], validEVEX[5]}, + "address override": append([]byte{0x67}, validVEX...), + } { + if instruction, _, matched, decodeErr := decodedX86DuplicateMoveInstruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, invalid, instruction, matched, decodeErr) + } + } + highZ386 := encodeX86RawEVEXDuplicateMove(rawDuplicateMoveSpecs[1], 2, 0, false, 8, 2) + if instruction, _, matched, decodeErr := decodedX86DuplicateMoveInstruction(highZ386, 32); !matched || decodeErr == nil { + t.Fatalf("386 high-Z encoding %x decoded as %+v, ok=%v, err=%v", highZ386, instruction, matched, decodeErr) + } +} + +func TestX86DuplicateMoveRawGo127ArchitectureOracle(t *testing.T) { + const accepted386 = `TEXT ok(SB),$0-0 + MOVDDUP X6, X7 + MOVSHDUP X6, X7 + MOVSLDUP X6, X7 + VMOVDDUP Y6, Y7 + VMOVSHDUP X20, K1, X21 + VMOVSLDUP.Z Y20, K2, Y21 + VMOVDDUP Z6, K3, Z7 + RET +` + requireX86GoAssemblerResult(t, "386", accepted386, true) + for _, instruction := range []string{ + "MOVSHDUP X8, X0", + "VMOVDDUP Z8, Z0", + } { + requireX86GoAssemblerResult(t, "386", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + } +} + +func TestTranslateX86RawDuplicateMoveTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT raw_duplicate_move(SB),NOSPLIT,$0-0\n") + for _, spec := range rawDuplicateMoveSpecs { + var encodings [][]byte + if target.goarch == "amd64" { + encodings = append(encodings, + encodeX86RawLegacyDuplicateMove(spec, 15, 14), + encodeX86RawVEXDuplicateMove(spec, 1, 15, 14), + encodeX86RawEVEXDuplicateMove(spec, 2, 7, true, 31, 30), + ) + } else { + encodings = append(encodings, + encodeX86RawLegacyDuplicateMove(spec, 7, 6), + encodeX86RawVEXDuplicateMove(spec, 1, 7, 6), + encodeX86RawEVEXDuplicateMove(spec, 0, 1, false, 20, 21), + encodeX86RawEVEXDuplicateMove(spec, 2, 2, true, 6, 7), + ) + } + for _, encoding := range encodings { + for _, value := range encoding { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "raw_duplicate_move": {Name: "raw_duplicate_move", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-duplicate-move-"+target.name+".ll", "raw-duplicate-move-"+target.name+".o", ll) + }) + } +} + +func TestAMD64DuplicateMoveRuntimeSemantics(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test only runs on amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT duplicateMoveSemantics(SB),NOSPLIT,$0-32 + MOVQ out+0(FP), AX + MOVQ source+8(FP), BX + MOVQ old+16(FP), CX + KMOVQ mask+24(FP), K1 + VMOVUPS (BX), Y0 + VMOVSHDUP Y0, Y1 + VMOVUPS Y1, 0(AX) + VMOVSLDUP Y0, Y2 + VMOVUPS Y2, 32(AX) + VMOVDDUP (BX), X3 + VMOVUPS X3, 64(AX) + VMOVUPS (CX), Y4 + VMOVSHDUP Y0, K1, Y4 + VMOVUPS Y4, 80(AX) + VMOVUPS (CX), Y4 + VMOVSLDUP.Z Y0, K1, Y4 + VMOVUPS Y4, 112(AX) + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: I64, Index: 3, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple = "x86_64-apple-macosx" + runPrefix = []string{"/usr/bin/arch", "-x86_64"} + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "amd64", + Sigs: map[string]FuncSig{ + "duplicateMoveSemantics": {Name: "duplicateMoveSemantics", Args: []LLVMType{Ptr, Ptr, Ptr, I64}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void duplicateMoveSemantics(uint32_t *, const uint32_t *, const uint32_t *, uint64_t); +int main(void) { + uint32_t source[8] = {10, 11, 20, 21, 30, 31, 40, 41}; + uint32_t old[8] = {100, 101, 102, 103, 104, 105, 106, 107}; + uint32_t out[36] = {0}; + uint64_t mask = 0x55; + duplicateMoveSemantics(out, source, old, mask); + uint32_t sh[8] = {11, 11, 21, 21, 31, 31, 41, 41}; + uint32_t sl[8] = {10, 10, 20, 20, 30, 30, 40, 40}; + uint32_t dd[4] = {10, 11, 10, 11}; + for (int i = 0; i < 8; i++) if (out[i] != sh[i]) return 1 + i; + for (int i = 0; i < 8; i++) if (out[8+i] != sl[i]) return 20 + i; + for (int i = 0; i < 4; i++) if (out[16+i] != dd[i]) return 40 + i; + for (int i = 0; i < 8; i++) { + uint32_t want = (mask >> i) & 1 ? sh[i] : old[i]; + if (out[20+i] != want) return 50 + i; + } + for (int i = 0; i < 8; i++) { + uint32_t want = (mask >> i) & 1 ? sl[i] : 0; + if (out[28+i] != want) return 70 + i; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "duplicate_move", triple, ll, mainC, runPrefix) +} diff --git a/amd64_raw_evex_insert_test.go b/amd64_raw_evex_insert_test.go new file mode 100644 index 00000000..31747f28 --- /dev/null +++ b/amd64_raw_evex_insert_test.go @@ -0,0 +1,218 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +func encodeX86RawEVEXPackedInsert(op Op, vectorBits byte, mask int, zeroing bool, first, second, destination int, immediate byte) []byte { + opcode := map[Op]byte{ + "VINSERTF32X4": 0x18, + "VINSERTF64X2": 0x18, + "VINSERTF32X8": 0x1a, + "VINSERTF64X4": 0x1a, + "VINSERTI32X4": 0x38, + "VINSERTI64X2": 0x38, + "VINSERTI32X8": 0x3a, + "VINSERTI64X4": 0x3a, + }[op] + p0 := byte((^destination>>3)&1)<<7 | + byte((^first>>4)&1)<<6 | + byte((^first>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | 3 + p1 := byte(^second&15)<<3 | 5 + if strings.Contains(string(op), "64") { + p1 |= 0x80 + } + p2 := vectorBits<<5 | byte((^second>>4)&1)<<3 | byte(mask) + if zeroing { + p2 |= 0x80 + } + modRM := byte(0xc0 | destination&7<<3 | first&7) + return []byte{0x62, p0, p1, p2, opcode, modRM, immediate} +} + +func TestDecodeX86RawDirectiveGroupReportedHasteEVEXPackedInsert(t *testing.T) { + code := []byte{0x62, 0xf3, 0xfd, 0x48, 0x38, 0x47, 0x01, 0x01} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "haste VINSERTI64X2 sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + const want = "VINSERTI64X2 $1, 16(DI), Z0, Z0" + if len(decoded) != 1 || !strings.HasPrefix(decoded[0].Raw, want+" ") { + t.Fatalf("decoded %x as %#v, want %q", code, decoded, want) + } +} + +func TestDecodedX86RawEVEXPackedInsertCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, family := range []struct { + ops []Op + vectorBits []byte + }{ + { + ops: []Op{"VINSERTF32X4", "VINSERTF64X2", "VINSERTI32X4", "VINSERTI64X2"}, + vectorBits: []byte{1, 2}, + }, + { + ops: []Op{"VINSERTF32X8", "VINSERTF64X4", "VINSERTI32X8", "VINSERTI64X4"}, + vectorBits: []byte{2}, + }, + } { + for _, op := range family.ops { + for _, vectorBits := range family.vectorBits { + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + firstName := "X" + if strings.HasSuffix(string(op), "X8") || strings.HasSuffix(string(op), "X4") && strings.Contains(string(op), "64X4") { + firstName = "Y" + } + for _, masking := range []struct { + mask int + zeroing bool + suffix string + }{ + {}, + {mask: 3}, + {mask: 7, zeroing: true, suffix: ".Z"}, + } { + for first := 0; first < 32; first++ { + for second := 0; second < 32; second++ { + for destination := 0; destination < 32; destination++ { + immediate := byte(first*8 + destination) + code := encodeX86RawEVEXPackedInsert(op, vectorBits, masking.mask, masking.zeroing, first, second, destination, immediate) + got, length, ok, err := decodedX86EVEXPackedInsertInstruction(code, 64) + args := []string{ + fmt.Sprintf("$%d", immediate), + fmt.Sprintf("%s%d", firstName, first), + fmt.Sprintf("%s%d", vectorName, second), + } + if masking.mask != 0 { + args = append(args, fmt.Sprintf("K%d", masking.mask)) + } + args = append(args, fmt.Sprintf("%s%d", vectorName, destination)) + want := string(op) + masking.suffix + " " + strings.Join(args, ", ") + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + } + } + } + if count != 1179648 { + t.Fatalf("covered %d EVEX packed-insert register encodings, want 1179648", count) + } +} + +func TestDecodedX86RawEVEXPackedInsertMemoryAndInvalidForms(t *testing.T) { + code := []byte{0x62, 0x03, 0x15, 0xc3, 0x3a, 0x64, 0x8b, 0x02, 0xff} + got, length, ok, err := decodedX86EVEXPackedInsertInstruction(code, 64) + wantMemory := MemRef{Base: "R11", Index: "R9", Scale: 4, Off: 64} + if err != nil || !ok || length != len(code) || got.Op != "VINSERTI32X8.Z" || len(got.Args) != 5 || got.Args[0].Imm != 255 || got.Args[1].Kind != OpMem || !reflect.DeepEqual(got.Args[1].Mem, wantMemory) || got.Args[2].String() != "Z29" || got.Args[3].String() != "K3" || got.Args[4].String() != "Z28" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + + valid := encodeX86RawEVEXPackedInsert("VINSERTI64X2", 2, 0, false, 0, 1, 2, 3) + for name, mutate := range map[string]func([]byte){ + "missing EVEX fixed bit": func(code []byte) { code[2] &^= 0x04 }, + "EVEX.b": func(code []byte) { code[3] |= 0x10 }, + "reserved length": func(code []byte) { code[3] |= 0x60 }, + "zero without mask": func(code []byte) { code[3] |= 0x80 }, + "x4 with X output": func(code []byte) { code[3] &^= 0x60 }, + "x8 with Y output": func(code []byte) { + code[3] = code[3]&^0x60 | 0x20 + code[4] = 0x3a + }, + } { + invalid := append([]byte(nil), valid...) + mutate(invalid) + if instruction, _, matched, decodeErr := decodedX86EVEXPackedInsertInstruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, invalid, instruction, matched, decodeErr) + } + } + for _, invalid := range [][]byte{ + {0x62}, + {valid[0], valid[1] ^ 1, valid[2], valid[3], valid[4], valid[5], valid[6]}, + {valid[0], valid[1], valid[2] &^ 1, valid[3], valid[4], valid[5], valid[6]}, + {valid[0], valid[1], valid[2], valid[3], 0x19, valid[5], valid[6]}, + } { + if instruction, _, matched, decodeErr := decodedX86EVEXPackedInsertInstruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("unrelated encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + truncatedImmediate := valid[:len(valid)-1] + if _, _, matched, decodeErr := decodedX86EVEXPackedInsertInstruction(truncatedImmediate, 64); !matched || decodeErr == nil { + t.Fatalf("truncated immediate returned ok=%v err=%v", matched, decodeErr) + } + ripRelative := []byte{0x62, 0xf3, 0xfd, 0x48, 0x38, 0x05, 0, 0, 0, 0, 1} + if _, _, matched, decodeErr := decodedX86EVEXPackedInsertInstruction(ripRelative, 64); !matched || decodeErr == nil { + t.Fatalf("RIP-relative encoding returned ok=%v err=%v", matched, decodeErr) + } + addressOverride := append([]byte{0x67}, valid...) + if _, _, matched, decodeErr := decodedX86EVEXPackedInsertInstruction(addressOverride, 64); !matched || decodeErr == nil { + t.Fatalf("address-override encoding returned ok=%v err=%v", matched, decodeErr) + } + for _, op := range []Op{"VINSERTF32X4", "VINSERTF64X2", "VINSERTF32X8", "VINSERTF64X4", "VINSERTI32X4", "VINSERTI64X2", "VINSERTI32X8", "VINSERTI64X4"} { + vectorBits := byte(1) + if strings.HasSuffix(string(op), "X8") || strings.Contains(string(op), "64X4") { + vectorBits = 2 + } + invalid := encodeX86RawEVEXPackedInsert(op, vectorBits, 0, false, 0, 0, 1, 0) + if _, _, matched, decodeErr := decodedX86EVEXPackedInsertInstruction(invalid, 32); !matched || decodeErr == nil { + t.Fatalf("386 %s encoding %x returned ok=%v err=%v", op, invalid, matched, decodeErr) + } + } +} + +func TestTranslateX86RawEVEXPackedInsertTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + code := [][]byte{ + encodeX86RawEVEXPackedInsert("VINSERTI64X2", 1, 3, true, 20, 20, 21, 1), + } + code = append(code, + []byte{0x62, 0xf3, 0xfd, 0x48, 0x38, 0x47, 0x01, 0x01}, + []byte{0x62, 0x03, 0x15, 0xc3, 0x3a, 0x64, 0x8b, 0x02, 0xff}, + ) + var source strings.Builder + source.WriteString("TEXT raw_evex_packed_insert(SB),NOSPLIT,$0-0\n") + for _, instruction := range code { + for _, value := range instruction { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"raw_evex_packed_insert": {Name: "raw_evex_packed_insert", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-evex-packed-insert-"+target.name+".ll", "raw-evex-packed-insert-"+target.name+".o", ir) + }) + } +} diff --git a/amd64_raw_evex_packed_broadcast_test.go b/amd64_raw_evex_packed_broadcast_test.go new file mode 100644 index 00000000..6f10cd01 --- /dev/null +++ b/amd64_raw_evex_packed_broadcast_test.go @@ -0,0 +1,223 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +func encodeX86RawEVEXPackedBroadcast(op Op, vectorBits byte, mask int, zeroing, vectorSource bool, source, destination int) []byte { + opcode := byte(0) + width64 := false + if vectorSource { + switch op { + case "VPBROADCASTB": + opcode = 0x78 + case "VPBROADCASTW": + opcode = 0x79 + case "VPBROADCASTD": + opcode = 0x58 + case "VPBROADCASTQ": + opcode = 0x59 + width64 = true + } + } else { + switch op { + case "VPBROADCASTB": + opcode = 0x7a + case "VPBROADCASTW": + opcode = 0x7b + case "VPBROADCASTD": + opcode = 0x7c + case "VPBROADCASTQ": + opcode = 0x7c + width64 = true + } + } + p0 := byte((^destination>>3)&1)<<7 | + byte((^source>>4)&1)<<6 | + byte((^source>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | 2 + p1 := byte(0x7d) + if width64 { + p1 |= 0x80 + } + p2 := vectorBits<<5 | 0x08 | byte(mask) + if zeroing { + p2 |= 0x80 + } + modRM := byte(0xc0 | destination&7<<3 | source&7) + return []byte{0x62, p0, p1, p2, opcode, modRM} +} + +func TestDecodeX86RawDirectiveGroupReportedHasteEVEXBroadcast(t *testing.T) { + code := []byte{0x62, 0x52, 0xfd, 0x48, 0x7c, 0xf2} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "haste VPBROADCASTQ sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + const want = "VPBROADCASTQ R10, Z14" + if len(decoded) != 1 || !strings.HasPrefix(decoded[0].Raw, want+" ") { + t.Fatalf("decoded %x as %#v, want %q", code, decoded, want) + } +} + +func TestDecodedX86RawEVEXPackedBroadcastCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, op := range []Op{"VPBROADCASTB", "VPBROADCASTW", "VPBROADCASTD", "VPBROADCASTQ"} { + for vectorBits, vectorName := range []string{"X", "Y", "Z"} { + for _, masking := range []struct { + mask int + zeroing bool + suffix string + }{ + {}, + {mask: 3}, + {mask: 7, zeroing: true, suffix: ".Z"}, + } { + for _, sourceKind := range []struct { + vector bool + count int + prefix string + }{ + {count: 16, prefix: "R"}, + {vector: true, count: 32, prefix: "X"}, + } { + for source := 0; source < sourceKind.count; source++ { + for destination := 0; destination < 32; destination++ { + code := encodeX86RawEVEXPackedBroadcast(op, byte(vectorBits), masking.mask, masking.zeroing, sourceKind.vector, source, destination) + got, length, ok, err := decodedX86VEXPackedBroadcastInstruction(code, 64) + args := []string{fmt.Sprintf("%s%d", sourceKind.prefix, source)} + if !sourceKind.vector { + args[0] = decodedX86RegisterNameForTest(source) + } + if masking.mask != 0 { + args = append(args, fmt.Sprintf("K%d", masking.mask)) + } + args = append(args, fmt.Sprintf("%s%d", vectorName, destination)) + want := string(op) + masking.suffix + " " + strings.Join(args, ", ") + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + } + } + if count != 55296 { + t.Fatalf("covered %d EVEX packed-broadcast register encodings, want 55296", count) + } +} + +func TestDecodedX86RawEVEXPackedBroadcastMemoryAndInvalidForms(t *testing.T) { + code := []byte{0x65, 0x62, 0x12, 0x7d, 0x2b, 0x58, 0x64, 0x8b, 0x20} + got, length, ok, err := decodedX86VEXPackedBroadcastInstruction(code, 64) + wantMemory := MemRef{Segment: GS, Base: "R11", Index: "R9", Scale: 4, Off: 128} + if err != nil || !ok || length != len(code) || got.Op != "VPBROADCASTD" || len(got.Args) != 3 || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) || got.Args[1].String() != "K3" || got.Args[2].String() != "Y12" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + + valid := encodeX86RawEVEXPackedBroadcast("VPBROADCASTD", 0, 0, false, false, 0, 0) + for name, mutate := range map[string]func([]byte){ + "W on byte": func(code []byte) { code[2] |= 0x80; code[4] = 0x7a }, + "used vvvv": func(code []byte) { code[2] &^= 0x08 }, + "used high vvvv": func(code []byte) { code[3] &^= 0x08 }, + "EVEX.b": func(code []byte) { code[3] |= 0x10 }, + "reserved length": func(code []byte) { code[3] |= 0x60 }, + "zero without mask": func(code []byte) { code[3] |= 0x80 }, + "GP high extension": func(code []byte) { code[1] &^= 0x40 }, + "GP opcode on memory": func(code []byte) { code[5] &^= 0xc0 }, + } { + invalid := append([]byte(nil), valid...) + mutate(invalid) + if instruction, _, matched, decodeErr := decodedX86VEXPackedBroadcastInstruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, invalid, instruction, matched, decodeErr) + } + } + for _, invalid := range [][]byte{ + {0x62}, + {valid[0], valid[1] ^ 1, valid[2], valid[3], valid[4], valid[5]}, + {valid[0], valid[1], valid[2] &^ 1, valid[3], valid[4], valid[5]}, + {valid[0], valid[1], valid[2], valid[3], 0x77, valid[5]}, + } { + if instruction, _, matched, decodeErr := decodedX86VEXPackedBroadcastInstruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("unrelated encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + + ripRelative := []byte{0x62, 0xf2, 0x7d, 0x08, 0x58, 0x05, 0, 0, 0, 0} + if _, _, matched, decodeErr := decodedX86VEXPackedBroadcastInstruction(ripRelative, 64); !matched || decodeErr == nil { + t.Fatalf("RIP-relative encoding returned ok=%v err=%v", matched, decodeErr) + } + addressOverride := append([]byte{0x67}, valid...) + if _, _, matched, decodeErr := decodedX86VEXPackedBroadcastInstruction(addressOverride, 64); !matched || decodeErr == nil { + t.Fatalf("address-override encoding returned ok=%v err=%v", matched, decodeErr) + } + for name, invalid := range map[string][]byte{ + "extended destination on 386": encodeX86RawEVEXPackedBroadcast("VPBROADCASTD", 0, 0, false, false, 0, 8), + "extended source on 386": encodeX86RawEVEXPackedBroadcast("VPBROADCASTD", 0, 0, false, true, 8, 0), + "qword GP source on 386": encodeX86RawEVEXPackedBroadcast("VPBROADCASTQ", 0, 0, false, false, 0, 0), + } { + if _, _, matched, decodeErr := decodedX86VEXPackedBroadcastInstruction(invalid, 32); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x returned ok=%v err=%v", name, invalid, matched, decodeErr) + } + } + valid386 := encodeX86RawEVEXPackedBroadcast("VPBROADCASTD", 0, 0, false, false, 7, 7) + got, length, ok, err = decodedX86VEXPackedBroadcastInstruction(valid386, 32) + if err != nil || !ok || length != len(valid386) || got.Raw != "VPBROADCASTD DI, X7" { + t.Fatalf("386 base-register form decoded as %+v, length=%d ok=%v err=%v", got, length, ok, err) + } +} + +func TestTranslateX86RawEVEXPackedBroadcastTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + code := [][]byte{ + encodeX86RawEVEXPackedBroadcast("VPBROADCASTD", 0, 0, false, false, 0, 1), + encodeX86RawEVEXPackedBroadcast("VPBROADCASTB", 1, 1, true, true, 1, 2), + } + if target.goarch == "amd64" { + code = append(code, []byte{0x62, 0x52, 0xfd, 0x48, 0x7c, 0xf2}) + } + var source strings.Builder + source.WriteString("TEXT raw_evex_packed_broadcast(SB),NOSPLIT,$0-0\n") + for _, instruction := range code { + for _, value := range instruction { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"raw_evex_packed_broadcast": {Name: "raw_evex_packed_broadcast", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-evex-packed-broadcast-"+target.name+".ll", "raw-evex-packed-broadcast-"+target.name+".o", ir) + }) + } +} diff --git a/amd64_raw_evex_packed_float_move_test.go b/amd64_raw_evex_packed_float_move_test.go new file mode 100644 index 00000000..4cfa2ebc --- /dev/null +++ b/amd64_raw_evex_packed_float_move_test.go @@ -0,0 +1,80 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestX86RawEVEXPackedFloatMoveCompleteGo127Family(t *testing.T) { + // Go 1.27's _yvmovapd table gives VMOVAPS/APD/UPS/UPD the same + // bidirectional X/Y/Z and K-masked EVEX forms in addition to the four + // legacy VEX rows. These LLVM-verified encodings cover every EVEX opcode, + // direction, vector width, mask mode, high-register field, and compressed + // disp8 addressing shape used by that table. + tests := []struct { + name string + code []byte + want string + }{ + {name: "aps x load masked", code: []byte{0x62, 0xf1, 0x7c, 0x09, 0x28, 0xc1}, want: "VMOVAPS X1, K1, X0"}, + {name: "aps x store compressed disp8", code: []byte{0x62, 0xf1, 0x7c, 0x0a, 0x29, 0x50, 0x01}, want: "VMOVAPS X2, K2, 16(AX)"}, + {name: "apd y high load masked", code: []byte{0x62, 0xa1, 0xfd, 0x29, 0x28, 0xe5}, want: "VMOVAPD Y21, K1, Y20"}, + {name: "apd y store masked sib", code: []byte{0x62, 0x91, 0xfd, 0x2a, 0x29, 0x64, 0x88, 0x03}, want: "VMOVAPD Y4, K2, 96(R8)(R9*4)"}, + {name: "apd z high load zeroing", code: []byte{0x62, 0xa1, 0xfd, 0xcb, 0x28, 0xe5}, want: "VMOVAPD.Z Z21, K3, Z20"}, + {name: "ups z high load zeroing", code: []byte{0x62, 0x01, 0x7c, 0xcf, 0x10, 0xfe}, want: "VMOVUPS.Z Z30, K7, Z31"}, + {name: "ups z store compressed disp8", code: []byte{0x62, 0xf1, 0x7c, 0x4e, 0x11, 0x7f, 0x07}, want: "VMOVUPS Z7, K6, 448(DI)"}, + {name: "upd x load masked", code: []byte{0x62, 0xf1, 0xfd, 0x09, 0x10, 0xd3}, want: "VMOVUPD X3, K1, X2"}, + {name: "upd x store compressed disp8", code: []byte{0x62, 0xf1, 0xfd, 0x0a, 0x11, 0x60, 0x02}, want: "VMOVUPD X4, K2, 32(AX)"}, + {name: "ups y memory load zeroing sib", code: []byte{0x62, 0x91, 0x7c, 0xaa, 0x10, 0x64, 0x88, 0x03}, want: "VMOVUPS.Z 96(R8)(R9*4), K2, Y4"}, + {name: "ups y high store masked", code: []byte{0x62, 0x41, 0x7c, 0x2b, 0x11, 0x4c, 0x24, 0x02}, want: "VMOVUPS Y25, K3, 64(R12)"}, + {name: "upd z high store masked sib", code: []byte{0x62, 0x01, 0xfd, 0x4b, 0x11, 0x4c, 0x6c, 0x02}, want: "VMOVUPD Z25, K3, 128(R12)(R13*2)"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + got, err := decodeX86RawDirectives(rawX86Function(test.code), "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || !strings.HasPrefix(got.Instrs[0].Raw, test.want+" ") { + t.Fatalf("decoded %#x as %#v, want %q", test.code, got.Instrs, test.want) + } + }) + } + + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + var source strings.Builder + source.WriteString("TEXT raw_evex_packed_float_move(SB),NOSPLIT,$0-0\n") + for _, test := range tests { + for _, value := range test.code { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"raw_evex_packed_float_move": {Name: "raw_evex_packed_float_move", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "raw-evex-packed-float-move.ll", "raw-evex-packed-float-move.o", ir) +} + +func TestX86RawEVEXPackedFloatMoveReportedMinioInstruction(t *testing.T) { + code := []byte{0x62, 0xc1, 0x7c, 0x48, 0x10, 0x04, 0x09} + got, err := decodeX86RawDirectives(rawX86Function(code), "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || !strings.HasPrefix(got.Instrs[0].Raw, "VMOVUPS 0(R9)(CX*1), Z16 ") { + t.Fatalf("decoded reported minio bytes as %#v", got.Instrs) + } +} diff --git a/amd64_raw_evex_packed_integer_move_test.go b/amd64_raw_evex_packed_integer_move_test.go new file mode 100644 index 00000000..5c116d12 --- /dev/null +++ b/amd64_raw_evex_packed_integer_move_test.go @@ -0,0 +1,121 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestX86RawEVEXPackedIntegerMoveCompleteGo127Family(t *testing.T) { + // Go 1.27 gives VMOVDQA32/64 and VMOVDQU8/16/32/64 the same + // 12-row _yvmovdqa32 table: X/Y/Z, load/store, with and without a + // nonzero K mask. These LLVM-verified encodings exercise every opcode, + // both directions, every vector width, high registers, SIB addressing, + // zeroing, and EVEX compressed disp8 scaling. + tests := []struct { + name string + code []byte + want string + }{ + {name: "dqa32 x load", code: []byte{0x62, 0xf1, 0x7d, 0x08, 0x6f, 0xc1}, want: "VMOVDQA32 X1, X0"}, + {name: "dqa32 x store compressed disp8", code: []byte{0x62, 0xf1, 0x7d, 0x08, 0x7f, 0x50, 0x01}, want: "VMOVDQA32 X2, 16(AX)"}, + {name: "dqa64 y high load masked", code: []byte{0x62, 0xa1, 0xfd, 0x29, 0x6f, 0xe5}, want: "VMOVDQA64 Y21, K1, Y20"}, + {name: "dqa64 y store masked sib", code: []byte{0x62, 0x91, 0xfd, 0x2a, 0x7f, 0x64, 0x88, 0x03}, want: "VMOVDQA64 Y4, K2, 96(R8)(R9*4)"}, + {name: "dqu8 z high load zeroing", code: []byte{0x62, 0x01, 0x7f, 0xcf, 0x6f, 0xfe}, want: "VMOVDQU8.Z Z30, K7, Z31"}, + {name: "dqu8 z store compressed disp8", code: []byte{0x62, 0xf1, 0x7f, 0x4e, 0x7f, 0x7f, 0x07}, want: "VMOVDQU8 Z7, K6, 448(DI)"}, + {name: "dqu16 x load masked", code: []byte{0x62, 0xf1, 0xff, 0x09, 0x6f, 0xd3}, want: "VMOVDQU16 X3, K1, X2"}, + {name: "dqu16 x store compressed disp8", code: []byte{0x62, 0xf1, 0xff, 0x0a, 0x7f, 0x60, 0x02}, want: "VMOVDQU16 X4, K2, 32(AX)"}, + {name: "dqu32 y memory load zeroing sib", code: []byte{0x62, 0x91, 0x7e, 0xaa, 0x6f, 0x64, 0x88, 0x03}, want: "VMOVDQU32.Z 96(R8)(R9*4), K2, Y4"}, + {name: "dqu32 y high store masked", code: []byte{0x62, 0x41, 0x7e, 0x2b, 0x7f, 0x4c, 0x24, 0x02}, want: "VMOVDQU32 Y25, K3, 64(R12)"}, + {name: "dqu64 z high load masked", code: []byte{0x62, 0x01, 0xfe, 0x4f, 0x6f, 0xf7}, want: "VMOVDQU64 Z31, K7, Z30"}, + {name: "dqu64 z high store masked sib", code: []byte{0x62, 0x01, 0xfe, 0x4b, 0x7f, 0x4c, 0x6c, 0x02}, want: "VMOVDQU64 Z25, K3, 128(R12)(R13*2)"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + got, err := decodeX86RawDirectives(rawX86Function(test.code), "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || !strings.HasPrefix(got.Instrs[0].Raw, test.want+" ") { + t.Fatalf("decoded %#x as %#v, want %q", test.code, got.Instrs, test.want) + } + }) + } + + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + var source strings.Builder + source.WriteString("TEXT raw_evex_packed_integer_move(SB),NOSPLIT,$0-0\n") + for _, test := range tests { + for _, value := range test.code { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]FuncSig{"raw_evex_packed_integer_move": {Name: "raw_evex_packed_integer_move", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "raw-evex-packed-integer-move.ll", "raw-evex-packed-integer-move.o", ir) +} + +func TestX86RawEVEXPackedIntegerMoveReportedMinioSequence(t *testing.T) { + var code []byte + for register := byte(0); register < 8; register++ { + modRM := byte(0x07 | register<<3) + code = append(code, 0x62, 0xf1, 0x7e, 0x48, 0x6f, modRM) + if register != 0 { + code[len(code)-1] |= 0x40 + code = append(code, register) + } + } + got, err := decodeX86RawDirectives(rawX86Function(code), "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 8 { + t.Fatalf("decoded minio sequence as %d instructions: %#v", len(got.Instrs), got.Instrs) + } + for index, instruction := range got.Instrs { + want := fmt.Sprintf("VMOVDQU32 %d(DI), Z%d", index*64, index) + if !strings.HasPrefix(instruction.Raw, want+" ") { + t.Fatalf("instruction %d = %q, want %q", index, instruction.Raw, want) + } + } +} + +func TestX86RawEVEXPackedIntegerMoveRejectsInvalidEVEXForms(t *testing.T) { + for _, test := range []struct { + name string + code []byte + }{ + {name: "broadcast bit", code: []byte{0x62, 0xf1, 0x7e, 0x58, 0x6f, 0xc1}}, + {name: "zeroing without mask", code: []byte{0x62, 0xf1, 0x7e, 0xc8, 0x6f, 0xc1}}, + {name: "zeroing store", code: []byte{0x62, 0xf1, 0x7e, 0x89, 0x7f, 0x08}}, + {name: "reserved vector length", code: []byte{0x62, 0xf1, 0x7e, 0x68, 0x6f, 0xc1}}, + {name: "address override", code: []byte{0x67, 0x62, 0xf1, 0x7e, 0x48, 0x6f, 0x07}}, + } { + t.Run(test.name, func(t *testing.T) { + if _, _, ok, err := decodedX86EVEXPackedIntegerMoveInstruction(test.code, 64); !ok || err == nil { + t.Fatalf("decoded invalid encoding %#x with ok=%v err=%v", test.code, ok, err) + } + }) + } +} + +func rawX86Function(code []byte) Func { + fn := Func{} + for _, value := range code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + return fn +} diff --git a/amd64_raw_evex_packed_logical_test.go b/amd64_raw_evex_packed_logical_test.go new file mode 100644 index 00000000..d155f4c7 --- /dev/null +++ b/amd64_raw_evex_packed_logical_test.go @@ -0,0 +1,200 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +func encodeX86RawEVEXPackedLogical(op Op, vectorBits byte, mask int, zeroing, broadcast bool, first, second, destination int) []byte { + opcode := map[Op]byte{ + "VPANDD": 0xdb, + "VPANDQ": 0xdb, + "VPANDND": 0xdf, + "VPANDNQ": 0xdf, + "VPORD": 0xeb, + "VPORQ": 0xeb, + "VPXORD": 0xef, + "VPXORQ": 0xef, + }[op] + p0 := byte((^destination>>3)&1)<<7 | + byte((^first>>4)&1)<<6 | + byte((^first>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | 1 + p1 := byte(^second&15)<<3 | 5 + if strings.HasSuffix(string(op), "Q") { + p1 |= 0x80 + } + p2 := vectorBits<<5 | byte((^second>>4)&1)<<3 | byte(mask) + if zeroing { + p2 |= 0x80 + } + if broadcast { + p2 |= 0x10 + } + modRM := byte(0xc0 | destination&7<<3 | first&7) + return []byte{0x62, p0, p1, p2, opcode, modRM} +} + +func TestDecodeX86RawDirectiveGroupReportedHasteEVEXPackedLogical(t *testing.T) { + code := []byte{0x62, 0xf1, 0xf5, 0x48, 0xef, 0xc9} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "haste VPXORQ sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + const want = "VPXORQ Z1, Z1, Z1" + if len(decoded) != 1 || !strings.HasPrefix(decoded[0].Raw, want+" ") { + t.Fatalf("decoded %x as %#v, want %q", code, decoded, want) + } +} + +func TestDecodedX86RawEVEXPackedLogicalCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, op := range []Op{"VPANDD", "VPANDQ", "VPANDND", "VPANDNQ", "VPORD", "VPORQ", "VPXORD", "VPXORQ"} { + for vectorBits, vectorName := range []string{"X", "Y", "Z"} { + for _, masking := range []struct { + mask int + zeroing bool + suffix string + }{ + {}, + {mask: 3}, + {mask: 7, zeroing: true, suffix: ".Z"}, + } { + for first := 0; first < 32; first++ { + for second := 0; second < 32; second++ { + for destination := 0; destination < 32; destination++ { + code := encodeX86RawEVEXPackedLogical(op, byte(vectorBits), masking.mask, masking.zeroing, false, first, second, destination) + got, length, ok, err := decodedX86EVEXPackedLogicalInstruction(code, 64) + args := []string{ + fmt.Sprintf("%s%d", vectorName, first), + fmt.Sprintf("%s%d", vectorName, second), + } + if masking.mask != 0 { + args = append(args, fmt.Sprintf("K%d", masking.mask)) + } + args = append(args, fmt.Sprintf("%s%d", vectorName, destination)) + want := string(op) + masking.suffix + " " + strings.Join(args, ", ") + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + } + } + if count != 2359296 { + t.Fatalf("covered %d EVEX packed-logical register encodings, want 2359296", count) + } +} + +func TestDecodedX86RawEVEXPackedLogicalMemoryAndInvalidForms(t *testing.T) { + code := []byte{0x62, 0x01, 0x95, 0xd3, 0xdb, 0x64, 0x8b, 0x20} + got, length, ok, err := decodedX86EVEXPackedLogicalInstruction(code, 64) + wantMemory := MemRef{Base: "R11", Index: "R9", Scale: 4, Off: 256} + if err != nil || !ok || length != len(code) || got.Op != "VPANDQ.BCST.Z" || len(got.Args) != 4 || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) || got.Args[1].String() != "Z29" || got.Args[2].String() != "K3" || got.Args[3].String() != "Z28" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + + valid := encodeX86RawEVEXPackedLogical("VPXORD", 0, 0, false, false, 0, 1, 2) + for name, mutate := range map[string]func([]byte){ + "missing EVEX fixed bit": func(code []byte) { code[2] &^= 0x04 }, + "reserved length": func(code []byte) { code[3] |= 0x60 }, + "zero without mask": func(code []byte) { code[3] |= 0x80 }, + "broadcast register": func(code []byte) { code[3] |= 0x10 }, + } { + invalid := append([]byte(nil), valid...) + mutate(invalid) + if instruction, _, matched, decodeErr := decodedX86EVEXPackedLogicalInstruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, invalid, instruction, matched, decodeErr) + } + } + for _, invalid := range [][]byte{ + {0x62}, + {valid[0], valid[1] ^ 1, valid[2], valid[3], valid[4], valid[5]}, + {valid[0], valid[1], valid[2] &^ 1, valid[3], valid[4], valid[5]}, + {valid[0], valid[1], valid[2], valid[3], 0xee, valid[5]}, + } { + if instruction, _, matched, decodeErr := decodedX86EVEXPackedLogicalInstruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("unrelated encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + ripRelative := []byte{0x62, 0xf1, 0x75, 0x08, 0xef, 0x15, 0, 0, 0, 0} + if _, _, matched, decodeErr := decodedX86EVEXPackedLogicalInstruction(ripRelative, 64); !matched || decodeErr == nil { + t.Fatalf("RIP-relative encoding returned ok=%v err=%v", matched, decodeErr) + } + addressOverride := append([]byte{0x67}, valid...) + if _, _, matched, decodeErr := decodedX86EVEXPackedLogicalInstruction(addressOverride, 64); !matched || decodeErr == nil { + t.Fatalf("address-override encoding returned ok=%v err=%v", matched, decodeErr) + } + for name, invalid := range map[string][]byte{ + "masked on 386": encodeX86RawEVEXPackedLogical("VPXORD", 0, 1, false, false, 0, 1, 2), + "high Z first on 386": encodeX86RawEVEXPackedLogical("VPXORD", 2, 0, false, false, 8, 1, 2), + "high Z second on 386": encodeX86RawEVEXPackedLogical("VPXORD", 2, 0, false, false, 0, 8, 2), + "high Z destination 386": encodeX86RawEVEXPackedLogical("VPXORD", 2, 0, false, false, 0, 1, 8), + } { + if _, _, matched, decodeErr := decodedX86EVEXPackedLogicalInstruction(invalid, 32); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x returned ok=%v err=%v", name, invalid, matched, decodeErr) + } + } + valid386 := encodeX86RawEVEXPackedLogical("VPXORD", 1, 0, false, false, 29, 30, 31) + got, length, ok, err = decodedX86EVEXPackedLogicalInstruction(valid386, 32) + if err != nil || !ok || length != len(valid386) || got.Raw != "VPXORD Y29, Y30, Y31" { + t.Fatalf("386 high X/Y register form decoded as %+v, length=%d ok=%v err=%v", got, length, ok, err) + } +} + +func TestTranslateX86RawEVEXPackedLogicalTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + code := [][]byte{ + encodeX86RawEVEXPackedLogical("VPXORD", 1, 0, false, false, 29, 30, 31), + } + if target.goarch == "amd64" { + code = append(code, + []byte{0x62, 0xf1, 0xf5, 0x48, 0xef, 0xc9}, + []byte{0x62, 0x01, 0x95, 0xd3, 0xdb, 0x64, 0x8b, 0x20}, + ) + } + var source strings.Builder + source.WriteString("TEXT raw_evex_packed_logical(SB),NOSPLIT,$0-0\n") + for _, instruction := range code { + for _, value := range instruction { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"raw_evex_packed_logical": {Name: "raw_evex_packed_logical", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-evex-packed-logical-"+target.name+".ll", "raw-evex-packed-logical-"+target.name+".o", ir) + }) + } +} diff --git a/amd64_raw_funnel_shift_test.go b/amd64_raw_funnel_shift_test.go new file mode 100644 index 00000000..b938de21 --- /dev/null +++ b/amd64_raw_funnel_shift_test.go @@ -0,0 +1,128 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestDecodeX86RawDirectiveGroupFunnelShiftCompleteFamily(t *testing.T) { + // Bytes are Go 1.27 assembler oracle cases spanning immediate/variable, + // left/right, W/D/Q, and high EVEX registers. + for _, test := range []struct { + name string + code []byte + want string + }{ + {name: "left immediate w", code: []byte{0x62, 0x13, 0xc5, 0x0b, 0x70, 0xd8, 0x41}, want: "VPSHLDW $65, X24, X7, K3, X11"}, + {name: "left immediate d", code: []byte{0x62, 0x43, 0x05, 0x04, 0x71, 0xd0, 0x2f}, want: "VPSHLDD $47, X8, X31, K4, X26"}, + {name: "left immediate q", code: []byte{0x62, 0x33, 0xd5, 0x04, 0x71, 0xfe, 0x5e}, want: "VPSHLDQ $94, X22, X21, K4, X15"}, + {name: "right immediate w", code: []byte{0x62, 0xc3, 0xfd, 0x09, 0x72, 0xf7, 0x1b}, want: "VPSHRDW $27, X15, X0, K1, X22"}, + {name: "right immediate q", code: []byte{0x62, 0x53, 0xfd, 0x03, 0x73, 0xee, 0x2a}, want: "VPSHRDQ $42, X14, X16, K3, X13"}, + {name: "left variable w", code: []byte{0x62, 0x32, 0xb5, 0x0f, 0x70, 0xea}, want: "VPSHLDVW X18, X9, K7, X13"}, + {name: "left variable d", code: []byte{0x62, 0xd2, 0x75, 0x0f, 0x71, 0xff}, want: "VPSHLDVD X15, X1, K7, X7"}, + {name: "left variable q", code: []byte{0x62, 0x72, 0xf5, 0x07, 0x71, 0xe3}, want: "VPSHLDVQ X3, X17, K7, X12"}, + {name: "right variable w", code: []byte{0x62, 0xf2, 0xed, 0x0f, 0x72, 0xc2}, want: "VPSHRDVW X2, X2, K7, X0"}, + {name: "right variable d", code: []byte{0x62, 0x32, 0x1d, 0x0a, 0x73, 0xc7}, want: "VPSHRDVD X23, X12, K2, X8"}, + {name: "right variable q", code: []byte{0x62, 0x22, 0xa5, 0x09, 0x73, 0xc4}, want: "VPSHRDVQ X20, X11, K1, X24"}, + {name: "left variable d broadcast zero", code: []byte{0x62, 0xf2, 0x75, 0xdb, 0x71, 0x50, 0x7f}, want: "VPSHLDVD.BCST.Z 508(AX), Z1, K3, Z2"}, + {name: "right immediate q broadcast zero", code: []byte{0x62, 0xf3, 0xf5, 0xdb, 0x73, 0x50, 0x7f, 0x09}, want: "VPSHRDQ.BCST.Z $9, 1016(AX), Z1, K3, Z2"}, + } { + t.Run(test.name, func(t *testing.T) { + decoded, err := decodeX86RawDirectiveGroup(test.code, 64, 0, test.name, map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || !strings.HasPrefix(decoded[0].Raw, test.want+" ") { + t.Fatalf("decoded %x as %#v, want %q", test.code, decoded, test.want) + } + }) + } +} + +func TestDecodedX86RawFunnelShiftAllRegisterFields(t *testing.T) { + for _, operation := range []struct { + op Op + opcode byte + mapValue byte + w byte + variable bool + }{ + {op: "VPSHLDW", opcode: 0x70, mapValue: 3, w: 1}, + {op: "VPSHLDD", opcode: 0x71, mapValue: 3}, + {op: "VPSHLDQ", opcode: 0x71, mapValue: 3, w: 1}, + {op: "VPSHRDW", opcode: 0x72, mapValue: 3, w: 1}, + {op: "VPSHRDD", opcode: 0x73, mapValue: 3}, + {op: "VPSHRDQ", opcode: 0x73, mapValue: 3, w: 1}, + {op: "VPSHLDVW", opcode: 0x70, mapValue: 2, w: 1, variable: true}, + {op: "VPSHLDVD", opcode: 0x71, mapValue: 2, variable: true}, + {op: "VPSHLDVQ", opcode: 0x71, mapValue: 2, w: 1, variable: true}, + {op: "VPSHRDVW", opcode: 0x72, mapValue: 2, w: 1, variable: true}, + {op: "VPSHRDVD", opcode: 0x73, mapValue: 2, variable: true}, + {op: "VPSHRDVQ", opcode: 0x73, mapValue: 2, w: 1, variable: true}, + } { + for vectorBits, vectorName := range []string{"X", "Y", "Z"} { + for first := 0; first < 32; first++ { + for second := 0; second < 32; second++ { + for destination := 0; destination < 32; destination++ { + p0 := byte((^destination>>3)&1)<<7 | + byte((^first>>4)&1)<<6 | + byte((^first>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | operation.mapValue + p1 := operation.w<<7 | byte(^second&15)<<3 | 5 + p2 := byte(vectorBits)<<5 | byte((^second>>4)&1)<<3 + modRM := byte(0xc0 | destination&7<<3 | first&7) + encoding := []byte{0x62, p0, p1, p2, operation.opcode, modRM} + if !operation.variable { + encoding = append(encoding, 0xa5) + } + instruction, length, ok, err := decodedX86FunnelShiftInstruction(encoding, 64) + if !ok || err != nil || length != len(encoding) { + t.Fatalf("op=%s width=%s first=%d second=%d destination=%d: ok=%v length=%d err=%v", operation.op, vectorName, first, second, destination, ok, length, err) + } + immediate := "" + if !operation.variable { + immediate = "$165, " + } + want := fmt.Sprintf("%s %s%s%d, %s%d, %s%d", operation.op, immediate, vectorName, first, vectorName, second, vectorName, destination) + if instruction.Raw != want { + t.Fatalf("encoding %x decoded as %q, want %q", encoding, instruction.Raw, want) + } + } + } + } + } + } +} + +func TestDecodedX86RawFunnelShiftRejectsReservedAndUnsafeForms(t *testing.T) { + for _, test := range []struct { + name string + mode int + encoding []byte + wantOK bool + }{ + {name: "386 immediate operand limit", mode: 32, encoding: []byte{0x62, 0xf3, 0xf5, 0x08, 0x73, 0xc2, 1}, wantOK: true}, + {name: "386 variable masked operand limit", mode: 32, encoding: []byte{0x62, 0xf2, 0xf5, 0x09, 0x73, 0xc2}, wantOK: true}, + {name: "386 variable extended register", mode: 32, encoding: []byte{0x62, 0x72, 0xf5, 0x08, 0x73, 0xc2}, wantOK: true}, + {name: "reserved vector length", mode: 64, encoding: []byte{0x62, 0xf2, 0xf5, 0x68, 0x73, 0xc2}, wantOK: true}, + {name: "word broadcast", mode: 64, encoding: []byte{0x62, 0xf2, 0xf5, 0x18, 0x72, 0x10}, wantOK: true}, + {name: "broadcast register", mode: 64, encoding: []byte{0x62, 0xf2, 0xf5, 0x18, 0x73, 0xc2}, wantOK: true}, + {name: "zero without mask", mode: 64, encoding: []byte{0x62, 0xf2, 0xf5, 0x88, 0x73, 0xc2}, wantOK: true}, + {name: "address override", mode: 64, encoding: []byte{0x67, 0x62, 0xf2, 0xf5, 0x08, 0x73, 0xc2}, wantOK: true}, + {name: "wrong map", mode: 64, encoding: []byte{0x62, 0xf1, 0xf5, 0x08, 0x73, 0xc2}, wantOK: false}, + {name: "wrong prefix", mode: 64, encoding: []byte{0x62, 0xf2, 0xf4, 0x08, 0x73, 0xc2}, wantOK: false}, + {name: "word wrong w", mode: 64, encoding: []byte{0x62, 0xf2, 0x75, 0x08, 0x72, 0xc2}, wantOK: true}, + {name: "truncated immediate", mode: 64, encoding: []byte{0x62, 0xf3, 0xf5, 0x08, 0x73, 0xc2}, wantOK: false}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86FunnelShiftInstruction(test.encoding, test.mode) + if ok != test.wantOK { + t.Fatalf("encoding %x: ok=%v, want %v (err=%v)", test.encoding, ok, test.wantOK, err) + } + if test.wantOK && err == nil { + t.Fatalf("encoding %x was recognized without rejection", test.encoding) + } + }) + } +} diff --git a/amd64_raw_ifma_test.go b/amd64_raw_ifma_test.go new file mode 100644 index 00000000..9fbe4a35 --- /dev/null +++ b/amd64_raw_ifma_test.go @@ -0,0 +1,98 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestDecodeX86RawDirectiveGroupIFMACompleteFamily(t *testing.T) { + // Bytes come from Go 1.27's avx512_ifma assembler test table and cover + // both opcodes, all widths, high registers, memory, and masking. + for _, test := range []struct { + name string + code []byte + want string + }{ + {name: "high x high registers", code: []byte{0x62, 0xe2, 0xa5, 0x09, 0xb5, 0xd7}, want: "VPMADD52HUQ X7, X11, K1, X18"}, + {name: "high y high registers", code: []byte{0x62, 0x82, 0x85, 0x27, 0xb5, 0xcc}, want: "VPMADD52HUQ Y28, Y31, K7, Y17"}, + {name: "low y memory", code: []byte{0x62, 0xf2, 0xb5, 0x29, 0xb4, 0x94, 0x2c, 0x11, 0, 0, 0}, want: "VPMADD52LUQ 17(SP)(BP*1), Y9, K1, Y2"}, + {name: "low z high registers", code: []byte{0x62, 0x22, 0xd5, 0x47, 0xb4, 0xe0}, want: "VPMADD52LUQ Z16, Z21, K7, Z28"}, + {name: "low z broadcast zeroing", code: []byte{0x62, 0xf2, 0xf5, 0xdb, 0xb4, 0x50, 0x7f}, want: "VPMADD52LUQ.BCST.Z 1016(AX), Z1, K3, Z2"}, + } { + t.Run(test.name, func(t *testing.T) { + decoded, err := decodeX86RawDirectiveGroup(test.code, 64, 0, test.name, map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || !strings.HasPrefix(decoded[0].Raw, test.want+" ") { + t.Fatalf("decoded %x as %#v, want %q", test.code, decoded, test.want) + } + }) + } +} + +func TestDecodedX86RawIFMAAllRegisterFields(t *testing.T) { + for _, operation := range []struct { + opcode byte + op Op + }{ + {opcode: 0xb4, op: "VPMADD52LUQ"}, + {opcode: 0xb5, op: "VPMADD52HUQ"}, + } { + for vectorBits, vectorName := range []string{"X", "Y", "Z"} { + for first := 0; first < 32; first++ { + for second := 0; second < 32; second++ { + for destination := 0; destination < 32; destination++ { + p0 := byte((^destination>>3)&1)<<7 | + byte((^first>>4)&1)<<6 | + byte((^first>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | 2 + p1 := byte(1)<<7 | byte(^second&15)<<3 | 5 + p2 := byte(vectorBits)<<5 | byte((^second>>4)&1)<<3 + modRM := byte(0xc0 | destination&7<<3 | first&7) + encoding := []byte{0x62, p0, p1, p2, operation.opcode, modRM} + instruction, length, ok, err := decodedX86IFMAInstruction(encoding, 64) + if !ok || err != nil || length != len(encoding) { + t.Fatalf("op=%s width=%s first=%d second=%d destination=%d: ok=%v length=%d err=%v", operation.op, vectorName, first, second, destination, ok, length, err) + } + want := fmt.Sprintf("%s %s%d, %s%d, %s%d", operation.op, vectorName, first, vectorName, second, vectorName, destination) + if instruction.Raw != want { + t.Fatalf("encoding %x decoded as %q, want %q", encoding, instruction.Raw, want) + } + } + } + } + } + } +} + +func TestDecodedX86RawIFMARejectsReservedAndUnsafeForms(t *testing.T) { + for _, test := range []struct { + name string + mode int + encoding []byte + wantOK bool + }{ + {name: "386 masked operand limit", mode: 32, encoding: []byte{0x62, 0xf2, 0xf5, 0x09, 0xb4, 0xc2}, wantOK: true}, + {name: "386 extended register", mode: 32, encoding: []byte{0x62, 0x72, 0xf5, 0x08, 0xb4, 0xc2}, wantOK: true}, + {name: "reserved vector length", mode: 64, encoding: []byte{0x62, 0xf2, 0xf5, 0x68, 0xb4, 0xc2}, wantOK: true}, + {name: "broadcast register", mode: 64, encoding: []byte{0x62, 0xf2, 0xf5, 0x18, 0xb4, 0xc2}, wantOK: true}, + {name: "zero without mask", mode: 64, encoding: []byte{0x62, 0xf2, 0xf5, 0x88, 0xb5, 0xc2}, wantOK: true}, + {name: "address override", mode: 64, encoding: []byte{0x67, 0x62, 0xf2, 0xf5, 0x08, 0xb4, 0xc2}, wantOK: true}, + {name: "wrong map", mode: 64, encoding: []byte{0x62, 0xf3, 0xf5, 0x08, 0xb4, 0xc2}, wantOK: false}, + {name: "wrong prefix", mode: 64, encoding: []byte{0x62, 0xf2, 0xf4, 0x08, 0xb4, 0xc2}, wantOK: false}, + {name: "wrong w", mode: 64, encoding: []byte{0x62, 0xf2, 0x75, 0x08, 0xb4, 0xc2}, wantOK: true}, + {name: "truncated", mode: 64, encoding: []byte{0x62, 0xf2, 0xf5, 0x08, 0xb4}, wantOK: false}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86IFMAInstruction(test.encoding, test.mode) + if ok != test.wantOK { + t.Fatalf("encoding %x: ok=%v, want %v (err=%v)", test.encoding, ok, test.wantOK, err) + } + if test.wantOK && err == nil { + t.Fatalf("encoding %x was recognized without rejection", test.encoding) + } + }) + } +} diff --git a/amd64_raw_insertps_test.go b/amd64_raw_insertps_test.go new file mode 100644 index 00000000..a3b2d5a4 --- /dev/null +++ b/amd64_raw_insertps_test.go @@ -0,0 +1,190 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +func encodeX86RawLegacyINSERTPS(source, destination int, immediate byte) []byte { + rex := byte(0x40 | source>>3&1 | destination>>3&1<<2) + code := []byte{0x66} + if rex != 0x40 { + code = append(code, rex) + } + return append(code, 0x0f, 0x3a, 0x21, byte(0xc0|destination&7<<3|source&7), immediate) +} + +func encodeX86RawVEXINSERTPS(source, base, destination int, immediate byte) []byte { + p0 := byte((^destination>>3)&1)<<7 | 0x40 | byte((^source>>3)&1)<<5 | 3 + p1 := byte(^base&15)<<3 | 1 + return []byte{0xc4, p0, p1, 0x21, byte(0xc0 | destination&7<<3 | source&7), immediate} +} + +func encodeX86RawEVEXINSERTPS(source, base, destination int, immediate byte) []byte { + p0 := byte((^destination>>3)&1)<<7 | + byte((^source>>4)&1)<<6 | + byte((^source>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | 3 + p1 := byte(^base&15)<<3 | 5 + p2 := byte((^base>>4)&1) << 3 + return []byte{0x62, p0, p1, p2, 0x21, byte(0xc0 | destination&7<<3 | source&7), immediate} +} + +func TestDecodeX86RawDirectiveGroupReportedSegDSPVINSERTPS(t *testing.T) { + // vinsertps $0x1c, %xmm10, %xmm8, %xmm1; + // vshufps $0x24, %xmm0, %xmm1, %xmm0 + code := []byte{0xc4, 0xc3, 0x39, 0x21, 0xca, 0x1c, 0xc5, 0xf0, 0xc6, 0xc0, 0x24} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "segdsp VINSERTPS sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 2 || !strings.HasPrefix(decoded[0].Raw, "VINSERTPS $28, X10, X8, X1 ") { + t.Fatalf("decoded %x as %#v", code, decoded) + } +} + +func TestDecodedX86RawINSERTPSCompleteRegisterFamily(t *testing.T) { + count := 0 + for source := 0; source < 16; source++ { + for destination := 0; destination < 16; destination++ { + immediate := byte(source*16 + destination) + code := encodeX86RawLegacyINSERTPS(source, destination, immediate) + got, length, ok, err := decodedX86InsertPSInstruction(code, 64) + want := fmt.Sprintf("INSERTPS $%d, X%d, X%d", immediate, source, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + for source := 0; source < 16; source++ { + for base := 0; base < 16; base++ { + for destination := 0; destination < 16; destination++ { + immediate := byte(source*16 + destination) + code := encodeX86RawVEXINSERTPS(source, base, destination, immediate) + got, length, ok, err := decodedX86InsertPSInstruction(code, 64) + want := fmt.Sprintf("VINSERTPS $%d, X%d, X%d, X%d", immediate, source, base, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + for source := 0; source < 32; source++ { + for base := 0; base < 32; base++ { + for destination := 0; destination < 32; destination++ { + immediate := byte(source*8 + destination) + code := encodeX86RawEVEXINSERTPS(source, base, destination, immediate) + got, length, ok, err := decodedX86InsertPSInstruction(code, 64) + want := fmt.Sprintf("VINSERTPS $%d, X%d, X%d, X%d", immediate, source, base, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + if count != 37120 { + t.Fatalf("covered %d INSERTPS/VINSERTPS register encodings, want 37120", count) + } +} + +func TestDecodedX86RawINSERTPSMemoryAndInvalidForms(t *testing.T) { + legacyMemory := []byte{0x66, 0x47, 0x0f, 0x3a, 0x21, 0x7c, 0x8b, 0x01, 0xff} + got, length, ok, err := decodedX86InsertPSInstruction(legacyMemory, 64) + wantMemory := MemRef{Base: "R11", Index: "R9", Scale: 4, Off: 1} + if err != nil || !ok || length != len(legacyMemory) || got.Op != "INSERTPS" || got.Args[2].String() != "X15" || got.Args[1].Kind != OpMem || !reflect.DeepEqual(got.Args[1].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", legacyMemory, got, length, ok, err) + } + vexMemory := []byte{0xc4, 0x03, 0x01, 0x21, 0x7c, 0x8b, 0x02, 0x80} + got, length, ok, err = decodedX86InsertPSInstruction(vexMemory, 64) + wantMemory.Off = 2 + if err != nil || !ok || length != len(vexMemory) || got.Op != "VINSERTPS" || got.Args[2].String() != "X15" || got.Args[3].String() != "X15" || got.Args[1].Kind != OpMem || !reflect.DeepEqual(got.Args[1].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", vexMemory, got, length, ok, err) + } + evexMemory := []byte{0x62, 0x03, 0x05, 0x00, 0x21, 0x7c, 0x8b, 0x02, 0x40} + got, length, ok, err = decodedX86InsertPSInstruction(evexMemory, 64) + wantMemory.Off = 8 + if err != nil || !ok || length != len(evexMemory) || got.Op != "VINSERTPS" || got.Args[2].String() != "X31" || got.Args[3].String() != "X31" || got.Args[1].Kind != OpMem || !reflect.DeepEqual(got.Args[1].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", evexMemory, got, length, ok, err) + } + + validVEX := encodeX86RawVEXINSERTPS(7, 7, 7, 1) + validEVEX := encodeX86RawEVEXINSERTPS(31, 31, 31, 1) + for name, invalid := range map[string][]byte{ + "vex W": {validVEX[0], validVEX[1], validVEX[2] | 0x80, validVEX[3], validVEX[4], validVEX[5]}, + "vex vector length": {validVEX[0], validVEX[1], validVEX[2] | 0x04, validVEX[3], validVEX[4], validVEX[5]}, + "evex W": {validEVEX[0], validEVEX[1], validEVEX[2] | 0x80, validEVEX[3], validEVEX[4], validEVEX[5], validEVEX[6]}, + "evex mask": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 1, validEVEX[4], validEVEX[5], validEVEX[6]}, + "evex zero": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 0x80, validEVEX[4], validEVEX[5], validEVEX[6]}, + "evex broadcast": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 0x10, validEVEX[4], validEVEX[5], validEVEX[6]}, + "truncated vex immediate": validVEX[:len(validVEX)-1], + "truncated evex immediate": validEVEX[:len(validEVEX)-1], + "address override": append([]byte{0x67}, validVEX...), + } { + if instruction, _, matched, decodeErr := decodedX86InsertPSInstruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, invalid, instruction, matched, decodeErr) + } + } + if instruction, _, matched, decodeErr := decodedX86InsertPSInstruction(validEVEX, 32); !matched || decodeErr == nil { + t.Fatalf("386 EVEX encoding %x decoded as %+v, ok=%v, err=%v", validEVEX, instruction, matched, decodeErr) + } + extended386 := encodeX86RawVEXINSERTPS(8, 0, 0, 1) + if instruction, _, matched, decodeErr := decodedX86InsertPSInstruction(extended386, 32); !matched || decodeErr == nil { + t.Fatalf("386 extended encoding %x decoded as %+v, ok=%v, err=%v", extended386, instruction, matched, decodeErr) + } +} + +func TestTranslateX86RawINSERTPSTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + registerMax int + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin", registerMax: 15}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", registerMax: 15}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc", registerMax: 15}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu", registerMax: 7}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc", registerMax: 7}, + } { + t.Run(target.name, func(t *testing.T) { + code := [][]byte{ + encodeX86RawLegacyINSERTPS(target.registerMax, target.registerMax, 0xff), + encodeX86RawVEXINSERTPS(target.registerMax, target.registerMax, target.registerMax, 0x1c), + } + if target.goarch == "amd64" { + code = append(code, encodeX86RawEVEXINSERTPS(31, 30, 29, 0x80)) + } + var source strings.Builder + source.WriteString("TEXT raw_insertps(SB),NOSPLIT,$0-0\n") + for _, instruction := range code { + for _, value := range instruction { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"raw_insertps": {Name: "raw_insertps", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-insertps-"+target.name+".ll", "raw-insertps-"+target.name+".o", ir) + }) + } +} diff --git a/amd64_raw_mask_move_test.go b/amd64_raw_mask_move_test.go new file mode 100644 index 00000000..95104f47 --- /dev/null +++ b/amd64_raw_mask_move_test.go @@ -0,0 +1,93 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestX86RawMaskMoveCompleteGo127Family(t *testing.T) { + // Go 1.27's shared _ykmovb table gives KMOVB/W/D/Q the same four + // encoding rows: K->memory, K->GP, K-or-memory->K, and GP->K. Cover + // every row at every width, plus the extended GP form reported by + // github.com/minio/sha256-simd. + tests := []struct { + name string + code []byte + want string + }{ + {name: "b k to k", code: []byte{0xc5, 0xf9, 0x90, 0xcd}, want: "KMOVB K5, K1"}, + {name: "b memory to k", code: []byte{0xc5, 0xf9, 0x90, 0x08}, want: "KMOVB 0(AX), K1"}, + {name: "b k to memory", code: []byte{0xc5, 0xf9, 0x91, 0x00}, want: "KMOVB K0, 0(AX)"}, + {name: "b k to gp", code: []byte{0xc5, 0xf9, 0x93, 0xc5}, want: "KMOVB K5, AX"}, + {name: "b gp to k", code: []byte{0xc5, 0xf9, 0x92, 0xe8}, want: "KMOVB AX, K5"}, + {name: "w k to k", code: []byte{0xc5, 0xf8, 0x90, 0xcd}, want: "KMOVW K5, K1"}, + {name: "w memory to k", code: []byte{0xc5, 0xf8, 0x90, 0x08}, want: "KMOVW 0(AX), K1"}, + {name: "w k to memory", code: []byte{0xc5, 0xf8, 0x91, 0x00}, want: "KMOVW K0, 0(AX)"}, + {name: "w k to gp", code: []byte{0xc5, 0xf8, 0x93, 0xc5}, want: "KMOVW K5, AX"}, + {name: "w gp to k", code: []byte{0xc5, 0xf8, 0x92, 0xe8}, want: "KMOVW AX, K5"}, + {name: "d k to k", code: []byte{0xc4, 0xe1, 0xf9, 0x90, 0xcd}, want: "KMOVD K5, K1"}, + {name: "d memory to k", code: []byte{0xc4, 0xe1, 0xf9, 0x90, 0x08}, want: "KMOVD 0(AX), K1"}, + {name: "d k to memory", code: []byte{0xc4, 0xe1, 0xf9, 0x91, 0x00}, want: "KMOVD K0, 0(AX)"}, + {name: "d k to gp", code: []byte{0xc5, 0xfb, 0x93, 0xc5}, want: "KMOVD K5, AX"}, + {name: "d gp to k", code: []byte{0xc5, 0xfb, 0x92, 0xe8}, want: "KMOVD AX, K5"}, + {name: "q k to k", code: []byte{0xc4, 0xe1, 0xf8, 0x90, 0xcd}, want: "KMOVQ K5, K1"}, + {name: "q memory to k", code: []byte{0xc4, 0xe1, 0xf8, 0x90, 0x08}, want: "KMOVQ 0(AX), K1"}, + {name: "q k to memory", code: []byte{0xc4, 0xe1, 0xf8, 0x91, 0x00}, want: "KMOVQ K0, 0(AX)"}, + {name: "q k to gp", code: []byte{0xc4, 0xe1, 0xfb, 0x93, 0xc5}, want: "KMOVQ K5, AX"}, + {name: "q gp to k", code: []byte{0xc4, 0xe1, 0xfb, 0x92, 0xe8}, want: "KMOVQ AX, K5"}, + {name: "q reported extended gp to k", code: []byte{0xc4, 0xc1, 0xfb, 0x92, 0xce}, want: "KMOVQ R14, K1"}, + {name: "q extended k to gp", code: []byte{0xc4, 0x61, 0xfb, 0x93, 0xd7}, want: "KMOVQ K7, R10"}, + {name: "q extended sib memory to k", code: []byte{0xc4, 0x81, 0xf8, 0x90, 0x4c, 0x88, 0x20}, want: "KMOVQ 32(R8)(R9*4), K1"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + fn := Func{} + for _, value := range test.code { + fn.Instrs = append(fn.Instrs, Instr{Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(value)}}}) + } + got, err := decodeX86RawDirectives(fn, "amd64") + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || !strings.HasPrefix(got.Instrs[0].Raw, test.want+" ") { + t.Fatalf("decoded %#x as %#v, want %q", test.code, got.Instrs, test.want) + } + }) + } + + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "386", triple: "i386-unknown-linux-gnu"}, + } { + t.Run(target.goarch+"/lower", func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT raw_mask_move(SB),NOSPLIT,$0-0\n") + for _, test := range tests[:20] { + for _, value := range test.code { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"raw_mask_move": {Name: "raw_mask_move", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-mask-move-"+target.goarch+".ll", "raw-mask-move-"+target.goarch+".o", ir) + }) + } +} diff --git a/amd64_raw_mask_vector_move.go b/amd64_raw_mask_vector_move.go new file mode 100644 index 00000000..b9d7fdbc --- /dev/null +++ b/amd64_raw_mask_vector_move.go @@ -0,0 +1,113 @@ +package plan9asm + +import "fmt" + +type decodedX86MaskVectorMoveProperties struct { + op Op + maskToVector bool +} + +func decodedX86MaskVectorMoveOpcode(opcode byte, width64 bool) (decodedX86MaskVectorMoveProperties, bool) { + width := byte(0) + if width64 { + width = 1 + } + properties := map[[2]byte]decodedX86MaskVectorMoveProperties{ + {0x28, 0}: {op: "VPMOVM2B", maskToVector: true}, + {0x28, 1}: {op: "VPMOVM2W", maskToVector: true}, + {0x38, 0}: {op: "VPMOVM2D", maskToVector: true}, + {0x38, 1}: {op: "VPMOVM2Q", maskToVector: true}, + {0x29, 0}: {op: "VPMOVB2M"}, + {0x29, 1}: {op: "VPMOVW2M"}, + {0x39, 0}: {op: "VPMOVD2M"}, + {0x39, 1}: {op: "VPMOVQ2M"}, + }[[2]byte{opcode, width}] + return properties, properties.op != "" +} + +// decodedX86MaskVectorMoveInstruction recognizes Go 1.27's complete +// VPMOVM2{B,W,D,Q} and VPMOV{B,W,D,Q}2M family. These EVEX-only instructions +// have register-only K/X/Y/Z forms and do not permit writemasking, zeroing, or +// EVEX.b. Recover all vector registers and widths before the generic decoder. +func decodedX86MaskVectorMoveInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64, 0x65: + i++ + case 0x67: + addressOverride = true + i++ + default: + goto evex + } + } + +evex: + if mode != 32 && mode != 64 || len(code) < i+6 || code[i] != 0x62 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + if p0&0x0f != 2 || p1&3 != 2 { + return Instr{}, 0, false, nil + } + properties, recognized := decodedX86MaskVectorMoveOpcode(opcode, p1&0x80 != 0) + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if p1&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("invalid EVEX prefix") + } + if p1&0x78 != 0x78 || p2&0x08 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.vvvv must be reserved") + } + if p2&0x97 != 0 { + return Instr{}, 0, true, fmt.Errorf("mask/vector moves do not support masking, zeroing, or EVEX.b") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + + modRMIndex := i + 5 + modRM := code[modRMIndex] + if modRM>>6 != 3 { + return Instr{}, 0, true, fmt.Errorf("mask/vector moves require register operands") + } + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + vectorNumber := 0 + maskNumber := 0 + if properties.maskToVector { + if xExt != 0 || bExt != 0 { + return Instr{}, 0, true, fmt.Errorf("K source register cannot be extended") + } + vectorNumber = int(modRM>>3&7) + rExt*8 + rHighExt*16 + maskNumber = int(modRM & 7) + } else { + if rExt != 0 || rHighExt != 0 { + return Instr{}, 0, true, fmt.Errorf("K destination register cannot be extended") + } + vectorNumber = int(modRM&7) + bExt*8 + xExt*16 + maskNumber = int(modRM >> 3 & 7) + } + if mode == 32 && vectorNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + vectorPrefix := [...]string{"X", "Y", "Z"}[vectorBits] + vector := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, vectorNumber))} + mask := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))} + args := []Operand{vector, mask} + if properties.maskToVector { + args[0], args[1] = args[1], args[0] + } + return Instr{Op: properties.op, Args: args, Raw: fmt.Sprintf("%s %s, %s", properties.op, args[0].String(), args[1].String())}, modRMIndex + 1, true, nil +} diff --git a/amd64_raw_mask_vector_move_test.go b/amd64_raw_mask_vector_move_test.go new file mode 100644 index 00000000..9cec94bd --- /dev/null +++ b/amd64_raw_mask_vector_move_test.go @@ -0,0 +1,166 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +type rawMaskVectorMoveSpec struct { + opcode byte + width64 bool + op Op + laneBits int + maskToVector bool +} + +var rawMaskVectorMoveSpecs = []rawMaskVectorMoveSpec{ + {opcode: 0x28, op: "VPMOVM2B", laneBits: 8, maskToVector: true}, + {opcode: 0x28, width64: true, op: "VPMOVM2W", laneBits: 16, maskToVector: true}, + {opcode: 0x38, op: "VPMOVM2D", laneBits: 32, maskToVector: true}, + {opcode: 0x38, width64: true, op: "VPMOVM2Q", laneBits: 64, maskToVector: true}, + {opcode: 0x29, op: "VPMOVB2M", laneBits: 8}, + {opcode: 0x29, width64: true, op: "VPMOVW2M", laneBits: 16}, + {opcode: 0x39, op: "VPMOVD2M", laneBits: 32}, + {opcode: 0x39, width64: true, op: "VPMOVQ2M", laneBits: 64}, +} + +func encodeX86EVEXMaskVectorMove(spec rawMaskVectorMoveSpec, vectorBits byte, vector, mask int) []byte { + p0 := byte(2) + regField, rmField := vector, mask + if spec.maskToVector { + p0 |= byte((1-(vector>>3)&1)<<7 | 1<<6 | 1<<5 | (1-(vector>>4)&1)<<4) + } else { + regField, rmField = mask, vector + p0 |= byte(1<<7 | (1-(vector>>4)&1)<<6 | (1-(vector>>3)&1)<<5 | 1<<4) + } + p1 := byte(15<<3 | 1<<2 | 2) + if spec.width64 { + p1 |= 0x80 + } + p2 := byte(vectorBits<<5 | 1<<3) + modRM := byte(0xc0 | (regField&7)<<3 | rmField&7) + return []byte{0x62, p0, p1, p2, spec.opcode, modRM} +} + +func TestDecodedX86EVEXMaskVectorMoveCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, spec := range rawMaskVectorMoveSpecs { + for vectorBits := byte(0); vectorBits < 3; vectorBits++ { + prefix := [...]string{"X", "Y", "Z"}[vectorBits] + for vector := 0; vector < 32; vector++ { + for mask := 0; mask < 8; mask++ { + code := encodeX86EVEXMaskVectorMove(spec, vectorBits, vector, mask) + got, length, ok, err := decodedX86MaskVectorMoveInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", prefix, vector), fmt.Sprintf("K%d", mask)} + if spec.maskToVector { + wantArgs[0], wantArgs[1] = wantArgs[1], wantArgs[0] + } + if got.Op != spec.op || len(got.Args) != 2 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, spec.op, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + if count != 6144 { + t.Fatalf("covered %d EVEX mask/vector move encodings, want 6144", count) + } +} + +func TestDecodedX86EVEXMaskVectorMoveGoAndWeaviateEncodings(t *testing.T) { + tests := []struct { + code []byte + op Op + args []string + }{ + {code: []byte{0x62, 0x72, 0x7e, 0x48, 0x38, 0xc0}, op: "VPMOVM2D", args: []string{"K0", "Z8"}}, + {code: []byte{0x62, 0x62, 0x7e, 0x08, 0x28, 0xd4}, op: "VPMOVM2B", args: []string{"K4", "X26"}}, + {code: []byte{0x62, 0xd2, 0x7e, 0x48, 0x29, 0xc9}, op: "VPMOVB2M", args: []string{"Z9", "K1"}}, + {code: []byte{0x62, 0x92, 0xfe, 0x28, 0x29, 0xe3}, op: "VPMOVW2M", args: []string{"Y27", "K4"}}, + } + for _, test := range tests { + got, length, ok, err := decodedX86MaskVectorMoveInstruction(test.code, 64) + if err != nil || !ok || length != len(test.code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", test.code, got, length, ok, err) + } + if got.Op != test.op || len(got.Args) != 2 || got.Args[0].String() != test.args[0] || got.Args[1].String() != test.args[1] { + t.Fatalf("decode %x = %+v, want %s %s", test.code, got, test.op, strings.Join(test.args, ", ")) + } + } +} + +func TestDecodedX86EVEXMaskVectorMoveInvalidForms(t *testing.T) { + spec := rawMaskVectorMoveSpecs[0] + base := encodeX86EVEXMaskVectorMove(spec, 0, 0, 0) + invalid := make([][]byte, 0, 9) + reservedVVVV := append([]byte(nil), base...) + reservedVVVV[2] &^= 0x08 + reservedHighV := append([]byte(nil), base...) + reservedHighV[3] &^= 0x08 + reservedLength := append([]byte(nil), base...) + reservedLength[3] |= 0x60 + masking := append([]byte(nil), base...) + masking[3] |= 0x01 + zeroing := append([]byte(nil), base...) + zeroing[3] |= 0x80 + broadcast := append([]byte(nil), base...) + broadcast[3] |= 0x10 + memory := append([]byte(nil), base...) + memory[5] &^= 0xc0 + extendedKSource := append([]byte(nil), base...) + extendedKSource[1] &^= 0x20 + vectorToMask := encodeX86EVEXMaskVectorMove(rawMaskVectorMoveSpecs[4], 0, 0, 0) + extendedKDestination := append([]byte(nil), vectorToMask...) + extendedKDestination[1] &^= 0x80 + invalid = append(invalid, reservedVVVV, reservedHighV, reservedLength, masking, zeroing, broadcast, memory, extendedKSource, extendedKDestination) + for _, code := range invalid { + if _, _, ok, err := decodedX86MaskVectorMoveInstruction(code, 64); !ok || err == nil { + t.Fatalf("invalid encoding %x returned ok=%v err=%v", code, ok, err) + } + } +} + +func TestTranslateRawEVEXMaskToVectorWeaviateBlockRegression(t *testing.T) { + const source = `TEXT rawMaskToVectorBlock(SB), $0-0 + LONG $0x487e7262; WORD $0xc038 + LONG $0x4875d162; WORD $0xc8fa + LONG $0x487e7262; WORD $0xc738 + LONG $0x4875d162; WORD $0xc8fa + LONG $0x487e7262; WORD $0xc138 + LONG $0x486dd162; WORD $0xd0fa + LONG $0x487e7262; WORD $0xc238 + LONG $0x4865d162; WORD $0xd8fa + LONG $0x487e7262; WORD $0xc338 + LONG $0x485dd162; WORD $0xe0fa + LONG $0x487e7262; WORD $0xc438 + LONG $0x4855d162; WORD $0xe8fa + LONG $0x487e7262; WORD $0xc538 + LONG $0x484dd162; WORD $0xf0fa + LONG $0x487e7262; WORD $0xc638 + LONG $0x4845d162; WORD $0xf8fa + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawMaskToVectorBlock": {Name: "rawMaskToVectorBlock", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if strings.Count(ir, "select i1") < 8*16 { + t.Fatalf("raw VPMOVM2D block omitted mask expansion:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-mask-to-vector.ll", "amd64-raw-mask-to-vector.o", ir) +} diff --git a/amd64_raw_mul_dword_qword.go b/amd64_raw_mul_dword_qword.go new file mode 100644 index 00000000..0e02affa --- /dev/null +++ b/amd64_raw_mul_dword_qword.go @@ -0,0 +1,236 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// decodedX86DwordToQwordMultiplyInstruction recognizes every VEX and EVEX +// encoding of VPMULDQ and VPMULUDQ in Go 1.27's _yvandnpd table. x/arch +// v0.14 does not decode these encodings, so raw BYTE/LONG directive users +// need the complete X/Y/Z, memory, mask, zeroing, and broadcast family here. +func decodedX86DwordToQwordMultiplyInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if i >= len(code) { + return Instr{}, 0, false, nil + } + + var ( + opcodeIndex int + modRMIndex int + mapSelect int + width int + rExt int + rHigh int + xExt int + bExt int + vRegister int + vHigh int + rmHigh int + masked bool + zeroing bool + broadcast bool + mask int + evex bool + ) + + switch code[i] { + case 0xc5: + if len(code) < i+3 { + return Instr{}, 0, false, nil + } + vexByte := code[i+1] + opcodeIndex, modRMIndex = i+2, i+3 + mapSelect = 1 + if vexByte&3 != 1 || code[opcodeIndex] != 0xf4 { + return Instr{}, 0, false, nil + } + rExt = int(^vexByte>>7) & 1 + vRegister = int(^vexByte>>3) & 15 + width = 16 + if vexByte&4 != 0 { + width = 32 + } + case 0xc4: + if len(code) < i+4 { + return Instr{}, 0, false, nil + } + vexExt, vexByte := code[i+1], code[i+2] + opcodeIndex, modRMIndex = i+3, i+4 + mapSelect = int(vexExt & 0x1f) + if vexByte&3 != 1 || !x86DwordToQwordMultiplyOpcode(mapSelect, code[opcodeIndex]) { + return Instr{}, 0, false, nil + } + ok = true + if vexByte&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + rExt = int(^vexExt>>7) & 1 + xExt = int(^vexExt>>6) & 1 + bExt = int(^vexExt>>5) & 1 + vRegister = int(^vexByte>>3) & 15 + width = 16 + if vexByte&4 != 0 { + width = 32 + } + case 0x62: + if len(code) < i+5 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcodeIndex, modRMIndex = i+4, i+5 + mapSelect = int(p0 & 3) + if p0&0x0c != 0 || p1&3 != 1 || !x86DwordToQwordMultiplyOpcode(mapSelect, code[opcodeIndex]) { + return Instr{}, 0, false, nil + } + ok, evex = true, true + if p1&0x84 != 0x84 { + return Instr{}, 0, true, fmt.Errorf("EVEX.W must be one and reserved bit must be set") + } + rExt = int(^p0>>7) & 1 + rHigh = int(^p0>>4) & 1 + xExt = int(^p0>>6) & 1 + bExt = int(^p0>>5) & 1 + vRegister = int(^p1>>3) & 15 + vHigh = int(^p2>>3) & 1 + rmHigh = xExt + zeroing = p2&0x80 != 0 + broadcast = p2&0x10 != 0 + mask = int(p2 & 7) + masked = mask != 0 + switch p2 >> 5 & 3 { + case 0: + width = 16 + case 1: + width = 32 + case 2: + width = 64 + default: + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + default: + return Instr{}, 0, false, nil + } + + if !ok { + ok = true + } + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + modRM := code[modRMIndex] + if evex && broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + if zeroing && !masked { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + destinationNumber := int(modRM>>3&7) + rExt*8 + rHigh*16 + secondNumber := vRegister + vHigh*16 + if mode == 32 && (destinationNumber >= 8 || secondNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector or address register in 32-bit mode") + } + destination, valid := decodedX86VectorRegister(destinationNumber, width) + if !valid { + return Instr{}, 0, true, fmt.Errorf("invalid destination vector register %d", destinationNumber) + } + second, valid := decodedX86VectorRegister(secondNumber, width) + if !valid { + return Instr{}, 0, true, fmt.Errorf("invalid second-source vector register %d", secondNumber) + } + first, consumed, err := decodedX86VectorRMSource(code[modRMIndex:], mode, bExt, xExt, rmHigh, width, segment) + if err != nil { + return Instr{}, 0, true, err + } + + op := "VPMULUDQ" + if mapSelect == 2 { + op = "VPMULDQ" + } + var suffixes []string + if broadcast { + suffixes = append(suffixes, "BCST") + } + if zeroing { + suffixes = append(suffixes, "Z") + } + if len(suffixes) != 0 { + op += "." + strings.Join(suffixes, ".") + } + args := []Operand{first, {Kind: OpReg, Reg: second}} + if masked { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", mask))}) + } + args = append(args, Operand{Kind: OpReg, Reg: destination}) + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: Op(op), Args: args, Raw: op + " " + strings.Join(rawArgs, ", ")}, modRMIndex + consumed, true, nil +} + +func x86DwordToQwordMultiplyOpcode(mapSelect int, opcode byte) bool { + return mapSelect == 1 && opcode == 0xf4 || mapSelect == 2 && opcode == 0x28 +} + +func decodedX86VectorRMSource(code []byte, mode, bExt, xExt, highExt, width int, segment Reg) (Operand, int, error) { + if len(code) == 0 { + return Operand{}, 0, fmt.Errorf("missing ModRM byte") + } + if code[0]>>6 != 3 { + return decodedX86VEXRMSource(code, mode, bExt, xExt, segment) + } + number := int(code[0]&7) + bExt*8 + highExt*16 + if mode == 32 && number >= 8 { + return Operand{}, 0, fmt.Errorf("extended vector register in 32-bit mode") + } + register, ok := decodedX86VectorRegister(number, width) + if !ok { + return Operand{}, 0, fmt.Errorf("invalid first-source vector register %d", number) + } + return Operand{Kind: OpReg, Reg: register}, 1, nil +} + +func decodedX86VectorRegister(number, width int) (Reg, bool) { + prefix := "" + switch width { + case 16: + prefix = "X" + case 32: + prefix = "Y" + case 64: + prefix = "Z" + default: + return "", false + } + if number < 0 || number >= 32 { + return "", false + } + return Reg(fmt.Sprintf("%s%d", prefix, number)), true +} diff --git a/amd64_raw_mul_dword_qword_test.go b/amd64_raw_mul_dword_qword_test.go new file mode 100644 index 00000000..991ea459 --- /dev/null +++ b/amd64_raw_mul_dword_qword_test.go @@ -0,0 +1,197 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "testing" +) + +func TestX86RawDwordToQwordMultiplyReportedEncoding(t *testing.T) { + const source = ` +TEXT rawVPMULUDQ(SB),$0-0 + BYTE $0xc5 + BYTE $0xfd + BYTE $0xf4 + BYTE $0xc2 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goarch string + triple string + }{ + {goarch: "386", triple: "i686-unknown-linux-gnu"}, + {goarch: "386", triple: "i686-pc-windows-msvc"}, + {goarch: "amd64", triple: "x86_64-apple-darwin"}, + {goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + } { + t.Run(target.triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{"rawVPMULUDQ": {Name: "rawVPMULUDQ", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-vpmuludq.ll", "raw-vpmuludq.o", ir) + }) + } +} + +func TestX86RawDwordToQwordMultiplyCompleteVEXRegisterFields(t *testing.T) { + for _, family := range []struct { + name string + mapID byte + opcode byte + }{ + {name: "VPMULUDQ", mapID: 1, opcode: 0xf4}, + {name: "VPMULDQ", mapID: 2, opcode: 0x28}, + } { + for _, width := range []struct { + prefix string + l byte + }{ + {prefix: "X", l: 0}, + {prefix: "Y", l: 1}, + } { + for first := 0; first < 16; first++ { + for second := 0; second < 16; second++ { + for destination := 0; destination < 16; destination++ { + p0 := byte((^destination>>3)&1)<<7 | 1<<6 | byte((^first>>3)&1)<<5 | family.mapID + p1 := byte((^second)&15)<<3 | width.l<<2 | 1 + modRM := byte(0xc0 | destination&7<<3 | first&7) + encoding := []byte{0xc4, p0, p1, family.opcode, modRM} + instruction, length, ok, err := decodedX86DwordToQwordMultiplyInstruction(encoding, 64) + if !ok || err != nil || length != len(encoding) { + t.Fatalf("%s %s registers %d,%d,%d: ok=%v length=%d err=%v", family.name, width.prefix, first, second, destination, ok, length, err) + } + want := []Reg{ + Reg(fmt.Sprintf("%s%d", width.prefix, first)), + Reg(fmt.Sprintf("%s%d", width.prefix, second)), + Reg(fmt.Sprintf("%s%d", width.prefix, destination)), + } + if instruction.Op != Op(family.name) || len(instruction.Args) != len(want) { + t.Fatalf("encoding %x decoded as %#v", encoding, instruction) + } + for index := range want { + if instruction.Args[index].Kind != OpReg || instruction.Args[index].Reg != want[index] { + t.Fatalf("encoding %x arg %d = %#v, want %s", encoding, index, instruction.Args[index], want[index]) + } + } + } + } + } + } + } +} + +func TestX86RawDwordToQwordMultiplyCompleteEVEXRegisterFields(t *testing.T) { + for _, family := range []struct { + name string + mapID byte + opcode byte + }{ + {name: "VPMULUDQ", mapID: 1, opcode: 0xf4}, + {name: "VPMULDQ", mapID: 2, opcode: 0x28}, + } { + for _, width := range []struct { + prefix string + ll byte + }{ + {prefix: "X", ll: 0}, + {prefix: "Y", ll: 1}, + {prefix: "Z", ll: 2}, + } { + for first := 0; first < 32; first++ { + for second := 0; second < 32; second++ { + for destination := 0; destination < 32; destination++ { + p0 := byte((^destination>>3)&1)<<7 | byte((^first>>4)&1)<<6 | byte((^first>>3)&1)<<5 | byte((^destination>>4)&1)<<4 | family.mapID + p1 := byte(0x85 | ((^second)&15)<<3) + p2 := width.ll<<5 | byte((^second>>4)&1)<<3 | 1 + modRM := byte(0xc0 | destination&7<<3 | first&7) + encoding := []byte{0x62, p0, p1, p2, family.opcode, modRM} + instruction, length, ok, err := decodedX86DwordToQwordMultiplyInstruction(encoding, 64) + if !ok || err != nil || length != len(encoding) { + t.Fatalf("%s %s registers %d,%d,%d: ok=%v length=%d err=%v", family.name, width.prefix, first, second, destination, ok, length, err) + } + want := []Reg{ + Reg(fmt.Sprintf("%s%d", width.prefix, first)), + Reg(fmt.Sprintf("%s%d", width.prefix, second)), + "K1", + Reg(fmt.Sprintf("%s%d", width.prefix, destination)), + } + if instruction.Op != Op(family.name) || len(instruction.Args) != len(want) { + t.Fatalf("encoding %x decoded as %#v", encoding, instruction) + } + for index := range want { + if instruction.Args[index].Kind != OpReg || instruction.Args[index].Reg != want[index] { + t.Fatalf("encoding %x arg %d = %#v, want %s", encoding, index, instruction.Args[index], want[index]) + } + } + } + } + } + } + } +} + +func TestX86RawDwordToQwordMultiplyMemoryMaskAndBroadcastForms(t *testing.T) { + for _, test := range []struct { + name string + encoding []byte + wantOp Op + wantArgs int + wantMem bool + }{ + {name: "vex signed base", encoding: []byte{0xc4, 0xe2, 0x31, 0x28, 0x13}, wantOp: "VPMULDQ", wantArgs: 3, wantMem: true}, + {name: "vex unsigned extended base", encoding: []byte{0xc4, 0xc1, 0x31, 0xf4, 0x13}, wantOp: "VPMULUDQ", wantArgs: 3, wantMem: true}, + {name: "evex masked memory", encoding: []byte{0x62, 0x71, 0xfd, 0x0e, 0xf4, 0xbc, 0x75, 0xef, 0xff, 0xff, 0xff}, wantOp: "VPMULUDQ", wantArgs: 4, wantMem: true}, + {name: "evex broadcast", encoding: []byte{0x62, 0x71, 0xfd, 0x1e, 0xf4, 0xbc, 0x75, 0xef, 0xff, 0xff, 0xff}, wantOp: "VPMULUDQ.BCST", wantArgs: 4, wantMem: true}, + {name: "evex broadcast zero", encoding: []byte{0x62, 0x71, 0xfd, 0x9e, 0xf4, 0xbc, 0x75, 0xef, 0xff, 0xff, 0xff}, wantOp: "VPMULUDQ.BCST.Z", wantArgs: 4, wantMem: true}, + {name: "evex unmasked", encoding: []byte{0x62, 0x31, 0xfd, 0x08, 0xf4, 0xf8}, wantOp: "VPMULUDQ", wantArgs: 3}, + } { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86DwordToQwordMultiplyInstruction(test.encoding, 64) + if !ok || err != nil || length != len(test.encoding) { + t.Fatalf("encoding %x: ok=%v length=%d err=%v", test.encoding, ok, length, err) + } + if instruction.Op != test.wantOp || len(instruction.Args) != test.wantArgs || (instruction.Args[0].Kind == OpMem) != test.wantMem { + t.Fatalf("encoding %x decoded as %#v", test.encoding, instruction) + } + }) + } +} + +func TestX86RawDwordToQwordMultiplyRejectsReservedAndUnsafeForms(t *testing.T) { + for _, test := range []struct { + name string + mode int + encoding []byte + }{ + {name: "vex w", mode: 64, encoding: []byte{0xc4, 0xe1, 0xfd, 0xf4, 0xc2}}, + {name: "evex w", mode: 64, encoding: []byte{0x62, 0x31, 0x7d, 0x0e, 0xf4, 0xf8}}, + {name: "evex reserved length", mode: 64, encoding: []byte{0x62, 0x31, 0xfd, 0x6e, 0xf4, 0xf8}}, + {name: "zero without mask", mode: 64, encoding: []byte{0x62, 0x31, 0xfd, 0x88, 0xf4, 0xf8}}, + {name: "broadcast register", mode: 64, encoding: []byte{0x62, 0x31, 0xfd, 0x1e, 0xf4, 0xf8}}, + {name: "address override", mode: 64, encoding: []byte{0x67, 0xc5, 0xfd, 0xf4, 0xc2}}, + {name: "rip relative", mode: 64, encoding: []byte{0xc5, 0xfd, 0xf4, 0x05, 0, 0, 0, 0}}, + {name: "extended 386", mode: 32, encoding: []byte{0xc4, 0x61, 0x79, 0xf4, 0xc0}}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86DwordToQwordMultiplyInstruction(test.encoding, test.mode) + if !ok || err == nil { + t.Fatalf("encoding %x: ok=%v err=%v, want recognized rejection", test.encoding, ok, err) + } + }) + } +} diff --git a/amd64_raw_mul_low.go b/amd64_raw_mul_low.go new file mode 100644 index 00000000..5c5352a4 --- /dev/null +++ b/amd64_raw_mul_low.go @@ -0,0 +1,153 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// decodedX86PackedMultiplyLowInstruction recognizes the complete shared +// VPMULLD/VPMULLQ opcode family in Go 1.27. VPMULLD has VEX.128/256 and +// EVEX.128/256/512 forms; VPMULLQ is EVEX-only. EVEX forms include high +// registers, masks, zeroing, compressed memory, and D/Q broadcast widths. +func decodedX86PackedMultiplyLowInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vectorPrefix + } + } + +vectorPrefix: + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXPackedMultiplyLowInstruction(code, i, mode, segment, addressOverride) + } + if len(code) < i+4 || code[i] != 0xc4 || code[i+1]&0x1f != 2 || code[i+2]&0x83 != 1 || code[i+3] != 0x40 { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vex0, vex1 := code[i+1], code[i+2] + modRMIndex := i + 4 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorName := "X" + if vex1&0x04 != 0 { + vectorName = "Y" + } + rExt := int(^vex0>>7) & 1 + xExt := int(^vex0>>6) & 1 + bExt := int(^vex0>>5) & 1 + secondSourceNumber := int(^vex1>>3) & 15 + destinationNumber := int(code[modRMIndex]>>3&7) + rExt*8 + if mode == 32 && (secondSourceNumber >= 8 || destinationNumber >= 8 || code[modRMIndex]>>6 == 3 && int(code[modRMIndex]&7)+bExt*8 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + firstSource, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + instruction = Instr{ + Op: "VPMULLD", + Args: []Operand{firstSource, secondSource, destination}, + Raw: fmt.Sprintf("VPMULLD %s, %s, %s", firstSource.String(), secondSource.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +func decodedX86EVEXPackedMultiplyLowInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+5 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + if p0&0x0f != 2 || p1&0x07 != 5 || code[i+4] != 0x40 { + return Instr{}, 0, false, nil + } + ok = true + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + vectorBits := (p2 >> 5) & 3 + if vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth := [...]int{16, 32, 64}[vectorBits] + width64 := p1&0x80 != 0 + op := Op("VPMULLD") + laneBytes := 4 + if width64 { + op = "VPMULLQ" + laneBytes = 8 + } + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + modRMIndex := i + 5 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + modRM := code[modRMIndex] + broadcast := p2&0x10 != 0 + if broadcast && modRM>>6 == 3 { + return Instr{}, 0, true, fmt.Errorf("EVEX broadcast requires a memory source") + } + secondSourceNumber := (int(^p1>>3) & 15) + (int(^p2>>3)&1)*16 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + firstSourceNumber := int(modRM&7) + bExt*8 + xExt*16 + if mode == 32 && (secondSourceNumber >= 8 || destinationNumber >= 8 || modRM>>6 == 3 && firstSourceNumber >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = laneBytes + } + firstSource, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorName, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + secondSource := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, secondSourceNumber))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorName, destinationNumber))} + args := []Operand{firstSource, secondSource} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + if broadcast { + op += ".BCST" + } + if zeroing { + op += ".Z" + } + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} diff --git a/amd64_raw_mul_low_test.go b/amd64_raw_mul_low_test.go new file mode 100644 index 00000000..3df16cec --- /dev/null +++ b/amd64_raw_mul_low_test.go @@ -0,0 +1,171 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86VEXPackedMultiplyLow(width256 bool, destination, source1, source2 int) []byte { + l := byte(0) + if width256 { + l = 1 + } + p0 := byte((1-destination/8)<<7 | 1<<6 | (1-source2/8)<<5 | 2) + p1 := byte(((^source1)&15)<<3 | int(l)<<2 | 1) + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + return []byte{0xc4, p0, p1, 0x40, modRM} +} + +func encodeX86EVEXPackedMultiplyLow(width64 bool, vectorBits byte, mask int, zeroing bool, destination, source1, source2 int) []byte { + p0 := byte((1-destination/8&1)<<7 | (1-source2/16)<<6 | (1-source2/8&1)<<5 | (1-destination/16)<<4 | 2) + p1 := byte(((^source1)&15)<<3 | 5) + if width64 { + p1 |= 0x80 + } + p2 := byte(vectorBits<<5 | byte((^source1>>4)&1)<<3 | byte(mask)) + if zeroing { + p2 |= 0x80 + } + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + return []byte{0x62, p0, p1, p2, 0x40, modRM} +} + +func TestTranslateRawEVEXVPMULLDWeaviateRegression(t *testing.T) { + const source = `TEXT rawVPMULLD(SB), $0-0 + LONG $0x483df262 + WORD $0xe440 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawVPMULLD": {Name: "rawVPMULLD", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "mul <16 x i32>") { + t.Fatalf("raw VPMULLD lowering omitted packed multiply:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-evex-vpmulld.ll", "amd64-raw-evex-vpmulld.o", ir) +} + +func TestDecodedX86PackedMultiplyLowCompleteVEXRegisterFamily(t *testing.T) { + count := 0 + for _, width256 := range []bool{false, true} { + prefix := "X" + if width256 { + prefix = "Y" + } + for destination := 0; destination < 16; destination++ { + for source1 := 0; source1 < 16; source1++ { + for source2 := 0; source2 < 16; source2++ { + code := encodeX86VEXPackedMultiplyLow(width256, destination, source1, source2) + got, length, ok, err := decodedX86PackedMultiplyLowInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != "VPMULLD" || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want VPMULLD %s", code, got, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + if count != 8192 { + t.Fatalf("covered %d VEX packed multiply-low register encodings, want 8192", count) + } +} + +func TestDecodedX86PackedMultiplyLowCompleteEVEXRegisterFamily(t *testing.T) { + count := 0 + for _, width := range []struct { + width64 bool + op Op + }{ + {op: "VPMULLD"}, + {width64: true, op: "VPMULLQ"}, + } { + for vectorBits, prefix := range []string{"X", "Y", "Z"} { + for destination := 0; destination < 32; destination++ { + for source1 := 0; source1 < 32; source1++ { + for source2 := 0; source2 < 32; source2++ { + code := encodeX86EVEXPackedMultiplyLow(width.width64, byte(vectorBits), 1, false, destination, source1, source2) + got, length, ok, err := decodedX86PackedMultiplyLowInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), "K1", fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != width.op || len(got.Args) != 4 { + t.Fatalf("decode %x = %+v, want %s %s", code, got, width.op, strings.Join(wantArgs, ", ")) + } + for index := range wantArgs { + if got.Args[index].String() != wantArgs[index] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, width.op, strings.Join(wantArgs, ", ")) + } + } + count++ + } + } + } + } + } + if count != 196608 { + t.Fatalf("covered %d EVEX packed multiply-low register encodings, want 196608", count) + } +} + +func TestDecodedX86PackedMultiplyLowMemoryAndInvalidForms(t *testing.T) { + for _, test := range []struct { + name string + width64 bool + vectorBits byte + op Op + laneBytes int + }{ + {name: "dword", vectorBits: 2, op: "VPMULLD.BCST.Z", laneBytes: 4}, + {name: "qword", width64: true, vectorBits: 2, op: "VPMULLQ.BCST.Z", laneBytes: 8}, + } { + t.Run(test.name, func(t *testing.T) { + code := encodeX86EVEXPackedMultiplyLow(test.width64, test.vectorBits, 3, true, 21, 20, 0) + code[3] |= 0x10 + code[5] = 0x68 + code = append(code, 0x7f) + got, length, ok, err := decodedX86PackedMultiplyLowInstruction(code, 64) + wantSource := fmt.Sprintf("%d(AX)", test.laneBytes*127) + if err != nil || !ok || length != len(code) || got.Op != test.op || len(got.Args) != 4 || got.Args[0].String() != wantSource || got.Args[1].String() != "Z20" || got.Args[2].String() != "K3" || got.Args[3].String() != "Z21" { + t.Fatalf("decode %x = %+v, length=%d ok=%v err=%v; want %s %s, Z20, K3, Z21", code, got, length, ok, err, test.op, wantSource) + } + }) + } + + for name, code := range map[string][]byte{ + "truncated": {0xc4, 0xe2}, + "wrong map": {0xc4, 0xe1, 0x79, 0x40, 0xc0}, + "wrong pp": {0xc4, 0xe2, 0x78, 0x40, 0xc0}, + "VEX qword": {0xc4, 0xe2, 0xf9, 0x40, 0xc0}, + "wrong opcode": {0xc4, 0xe2, 0x79, 0x41, 0xc0}, + } { + if instruction, _, matched, decodeErr := decodedX86PackedMultiplyLowInstruction(code, 64); matched || decodeErr != nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, code, instruction, matched, decodeErr) + } + } + invalidBroadcast := encodeX86EVEXPackedMultiplyLow(false, 2, 1, false, 0, 0, 0) + invalidBroadcast[3] |= 0x10 + if _, _, matched, decodeErr := decodedX86PackedMultiplyLowInstruction(invalidBroadcast, 64); !matched || decodeErr == nil { + t.Fatalf("register broadcast returned ok=%v err=%v", matched, decodeErr) + } + zeroWithoutMask := encodeX86EVEXPackedMultiplyLow(false, 2, 0, true, 0, 0, 0) + if _, _, matched, decodeErr := decodedX86PackedMultiplyLowInstruction(zeroWithoutMask, 64); !matched || decodeErr == nil { + t.Fatalf("zero without mask returned ok=%v err=%v", matched, decodeErr) + } +} diff --git a/amd64_raw_packed_extend_test.go b/amd64_raw_packed_extend_test.go new file mode 100644 index 00000000..54f68e58 --- /dev/null +++ b/amd64_raw_packed_extend_test.go @@ -0,0 +1,238 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +type rawPackedExtendTestSpec struct { + opcode byte + op Op + inputBits int + outputBits int +} + +var rawPackedExtendTestSpecs = []rawPackedExtendTestSpec{ + {opcode: 0x20, op: "VPMOVSXBW", inputBits: 8, outputBits: 16}, + {opcode: 0x21, op: "VPMOVSXBD", inputBits: 8, outputBits: 32}, + {opcode: 0x22, op: "VPMOVSXBQ", inputBits: 8, outputBits: 64}, + {opcode: 0x23, op: "VPMOVSXWD", inputBits: 16, outputBits: 32}, + {opcode: 0x24, op: "VPMOVSXWQ", inputBits: 16, outputBits: 64}, + {opcode: 0x25, op: "VPMOVSXDQ", inputBits: 32, outputBits: 64}, + {opcode: 0x30, op: "VPMOVZXBW", inputBits: 8, outputBits: 16}, + {opcode: 0x31, op: "VPMOVZXBD", inputBits: 8, outputBits: 32}, + {opcode: 0x32, op: "VPMOVZXBQ", inputBits: 8, outputBits: 64}, + {opcode: 0x33, op: "VPMOVZXWD", inputBits: 16, outputBits: 32}, + {opcode: 0x34, op: "VPMOVZXWQ", inputBits: 16, outputBits: 64}, + {opcode: 0x35, op: "VPMOVZXDQ", inputBits: 32, outputBits: 64}, +} + +func encodeX86VEXPackedExtend(opcode byte, width256 bool, destination, source int) []byte { + l := byte(0) + if width256 { + l = 1 + } + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-source/8)<<5 | 2) + vex1 := byte(15<<3 | int(l)<<2 | 1) + modRM := byte(0xc0 | (destination&7)<<3 | source&7) + return []byte{0xc4, vex0, vex1, opcode, modRM} +} + +func encodeX86EVEXPackedExtend(opcode byte, vectorBits byte, mask int, zeroing bool, destination, source int) []byte { + p0 := byte((1-destination/8&1)<<7 | (1-source/16)<<6 | (1-source/8&1)<<5 | (1-destination/16)<<4 | 2) + p1 := byte(0x7d) + p2 := byte(vectorBits<<5 | 1<<3 | byte(mask)) + if zeroing { + p2 |= 0x80 + } + modRM := byte(0xc0 | (destination&7)<<3 | source&7) + return []byte{0x62, p0, p1, p2, opcode, modRM} +} + +func TestTranslateRawEVEXPackedExtendWeaviateRegression(t *testing.T) { + const source = `TEXT rawPackedExtend(SB), $0-0 + LONG $0x487df262 + WORD $0x2432 + BYTE $0x07 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawPackedExtend": {Name: "rawPackedExtend", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "zext i8") || !strings.Contains(ir, "to i64") { + t.Fatalf("raw VPMOVZXBQ lowering omitted byte-to-qword zero extension:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-evex-packed-extend.ll", "amd64-raw-evex-packed-extend.o", ir) +} + +func TestTranslateRawVEXPackedExtendWeaviateBlockRegression(t *testing.T) { + lastExtend := []byte{0xc4, 0xe2, 0x7d, 0x31, 0x7e, 0x18} + if got, length, ok, err := decodedX86PackedExtendInstruction(lastExtend, 64); err != nil || !ok || length != len(lastExtend) || got.Op != "VPMOVZXBD" { + t.Fatalf("direct decode %x = %+v, length=%d, ok=%v, err=%v", lastExtend, got, length, ok, err) + } + const source = `TEXT rawPackedExtendBlock(SB), $0-0 + LONG $0x317de2c4; BYTE $0x26 + LONG $0x317de2c4; WORD $0x086e + LONG $0xe45bfcc5 + LONG $0xed5bfcc5 + LONG $0x317de2c4; WORD $0x1076 + LONG $0xf65bfcc5 + LONG $0x317de2c4; WORD $0x187e + LONG $0xff5bfcc5 + LONG $0xb85de2c4; BYTE $0x1f + LONG $0xb855e2c4; WORD $0x2057 + LONG $0xb84de2c4; WORD $0x404f + LONG $0xb845e2c4; WORD $0x6047 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawPackedExtendBlock": {Name: "rawPackedExtendBlock", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if strings.Count(ir, "zext i8") < 4 || strings.Count(ir, "sitofp <8 x i32>") < 4 { + t.Fatalf("raw VPMOVZXBD/VCVTDQ2PS block omitted conversions:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-packed-extend-block.ll", "amd64-raw-packed-extend-block.o", ir) +} + +func TestDecodedX86PackedExtendCompleteVEXRegisterFamily(t *testing.T) { + count := 0 + for _, spec := range rawPackedExtendTestSpecs { + for _, width256 := range []bool{false, true} { + destinationPrefix := "X" + if width256 { + destinationPrefix = "Y" + } + for destination := 0; destination < 16; destination++ { + for source := 0; source < 16; source++ { + code := encodeX86VEXPackedExtend(spec.opcode, width256, destination, source) + got, length, ok, err := decodedX86PackedExtendInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantSource := fmt.Sprintf("X%d", source) + wantDestination := fmt.Sprintf("%s%d", destinationPrefix, destination) + if got.Op != spec.op || len(got.Args) != 2 || got.Args[0].String() != wantSource || got.Args[1].String() != wantDestination { + t.Fatalf("decode %x = %+v, want %s %s, %s", code, got, spec.op, wantSource, wantDestination) + } + count++ + } + } + } + } + if count != 6144 { + t.Fatalf("covered %d VEX packed-extend register encodings, want 6144", count) + } +} + +func TestDecodedX86PackedExtendCompleteEVEXRegisterFamily(t *testing.T) { + count := 0 + for _, spec := range rawPackedExtendTestSpecs { + for vectorBits, destinationPrefix := range []string{"X", "Y", "Z"} { + destinationBytes := 16 << vectorBits + sourcePrefix := "X" + if destinationBytes*spec.inputBits/spec.outputBits > 16 { + sourcePrefix = "Y" + } + for _, masking := range []struct { + mask int + zeroing bool + suffix string + }{ + {}, + {mask: 3}, + {mask: 7, zeroing: true, suffix: ".Z"}, + } { + for destination := 0; destination < 32; destination++ { + for source := 0; source < 32; source++ { + code := encodeX86EVEXPackedExtend(spec.opcode, byte(vectorBits), masking.mask, masking.zeroing, destination, source) + got, length, ok, err := decodedX86PackedExtendInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", sourcePrefix, source)} + if masking.mask != 0 { + wantArgs = append(wantArgs, fmt.Sprintf("K%d", masking.mask)) + } + wantArgs = append(wantArgs, fmt.Sprintf("%s%d", destinationPrefix, destination)) + if got.Op != spec.op+Op(masking.suffix) || len(got.Args) != len(wantArgs) { + t.Fatalf("decode %x = %+v, want %s %s", code, got, spec.op+Op(masking.suffix), strings.Join(wantArgs, ", ")) + } + for index := range wantArgs { + if got.Args[index].String() != wantArgs[index] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, spec.op+Op(masking.suffix), strings.Join(wantArgs, ", ")) + } + } + count++ + } + } + } + } + } + if count != 110592 { + t.Fatalf("covered %d EVEX packed-extend register encodings, want 110592", count) + } +} + +func TestDecodedX86PackedExtendCompressedMemoryAndInvalidForms(t *testing.T) { + for _, spec := range rawPackedExtendTestSpecs { + for vectorBits, destinationPrefix := range []string{"X", "Y", "Z"} { + destinationBytes := 16 << vectorBits + sourceBytes := destinationBytes * spec.inputBits / spec.outputBits + code := encodeX86EVEXPackedExtend(spec.opcode, byte(vectorBits), 2, true, 21, 0) + code[5] = 0x68 + code = append(code, 0x7f) + got, length, ok, err := decodedX86PackedExtendInstruction(code, 64) + wantSource := fmt.Sprintf("%d(AX)", sourceBytes*127) + wantDestination := fmt.Sprintf("%s21", destinationPrefix) + if err != nil || !ok || length != len(code) || got.Op != spec.op+".Z" || len(got.Args) != 3 || got.Args[0].String() != wantSource || got.Args[1].String() != "K2" || got.Args[2].String() != wantDestination { + t.Fatalf("decode %x = %+v, length=%d ok=%v err=%v; want %s.Z %s, K2, %s", code, got, length, ok, err, spec.op, wantSource, wantDestination) + } + } + } + + valid := encodeX86VEXPackedExtend(0x32, false, 0, 0) + invalidVVVV := append([]byte(nil), valid...) + invalidVVVV[2] &^= 0x08 + for name, code := range map[string][]byte{ + "truncated": {0xc4, 0xe2}, + "wrong map": {0xc4, 0xe1, 0x79, 0x32, 0xc0}, + "wrong pp": {0xc4, 0xe2, 0x78, 0x32, 0xc0}, + "wrong W": {0xc4, 0xe2, 0xf9, 0x32, 0xc0}, + "unrelated opcode": {0xc4, 0xe2, 0x79, 0x2f, 0xc0}, + } { + if instruction, _, matched, decodeErr := decodedX86PackedExtendInstruction(code, 64); matched || decodeErr != nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, code, instruction, matched, decodeErr) + } + } + if _, _, matched, decodeErr := decodedX86PackedExtendInstruction(invalidVVVV, 64); !matched || decodeErr == nil { + t.Fatalf("non-reserved VEX.vvvv encoding %x returned ok=%v err=%v", invalidVVVV, matched, decodeErr) + } + invalidBroadcast := encodeX86EVEXPackedExtend(0x32, 2, 1, false, 0, 0) + invalidBroadcast[3] |= 0x10 + invalidBroadcast[5] = 0x40 + invalidBroadcast = append(invalidBroadcast, 1) + if _, _, matched, decodeErr := decodedX86PackedExtendInstruction(invalidBroadcast, 64); !matched || decodeErr == nil { + t.Fatalf("EVEX broadcast returned ok=%v err=%v", matched, decodeErr) + } +} diff --git a/amd64_raw_permute128_test.go b/amd64_raw_permute128_test.go new file mode 100644 index 00000000..9920ca19 --- /dev/null +++ b/amd64_raw_permute128_test.go @@ -0,0 +1,113 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86RawVPERM2X128(opcode, immediate byte, first, second, destination int) []byte { + p0 := byte((1-destination/8)<<7 | 1<<6 | (1-first/8)<<5 | 3) + p1 := byte((^second&15)<<3 | 5) + modRM := byte(0xc0 | destination&7<<3 | first&7) + return []byte{0xc4, p0, p1, opcode, modRM, immediate} +} + +func TestDecodeX86RawDirectiveGroupReportedPsiphonVPERM2I128(t *testing.T) { + code := []byte{0xc4, 0xe3, 0x6d, 0x46, 0xc3, 0x20} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "Psiphon VPERM2I128 sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + const want = "VPERM2I128 $32, Y3, Y2, Y0" + if len(decoded) != 1 || !strings.HasPrefix(decoded[0].Raw, want+" ") { + t.Fatalf("decoded %x as %#v, want %q", code, decoded, want) + } +} + +func TestDecodedX86RawVPERM2X128CompleteRegisterFamily(t *testing.T) { + count := 0 + for _, operation := range []struct { + opcode byte + name string + }{ + {opcode: 0x06, name: "VPERM2F128"}, + {opcode: 0x46, name: "VPERM2I128"}, + } { + for first := 0; first < 16; first++ { + for second := 0; second < 16; second++ { + for destination := 0; destination < 16; destination++ { + immediate := byte(first*16 + destination) + code := encodeX86RawVPERM2X128(operation.opcode, immediate, first, second, destination) + got, length, ok, err := decodedX86Permute128Instruction(code, 64) + want := fmt.Sprintf("%s $%d, Y%d, Y%d, Y%d", operation.name, immediate, first, second, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + if count != 8192 { + t.Fatalf("covered %d VPERM2F128/VPERM2I128 register encodings, want 8192", count) + } +} + +func TestDecodedX86RawVPERM2X128MemoryAndInvalidForms(t *testing.T) { + for _, test := range []struct { + name string + code []byte + want string + }{ + { + name: "VPERM2F128 extended SIB", + code: []byte{0x65, 0xc4, 0x03, 0x15, 0x06, 0x64, 0x8b, 0x20, 0xff}, + want: "VPERM2F128 $255, 32(R11)(R9*4)(GS), Y13, Y12", + }, + { + name: "VPERM2I128 extended SIB", + code: []byte{0x64, 0xc4, 0x03, 0x15, 0x46, 0x64, 0x8b, 0x20, 0xfe}, + want: "VPERM2I128 $254, 32(R11)(R9*4)(FS), Y13, Y12", + }, + } { + t.Run(test.name, func(t *testing.T) { + got, length, ok, err := decodedX86Permute128Instruction(test.code, 64) + if err != nil || !ok || length != len(test.code) || got.Raw != test.want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", test.code, got, length, ok, err, test.want) + } + }) + } + + for _, test := range []struct { + name string + mode int + encoding []byte + wantOK bool + }{ + {name: "386 operand limit", mode: 32, encoding: encodeX86RawVPERM2X128(0x46, 1, 0, 1, 2), wantOK: true}, + {name: "wrong pp", mode: 64, encoding: []byte{0xc4, 0xe3, 0x6c, 0x46, 0xc3, 4}, wantOK: true}, + {name: "W", mode: 64, encoding: []byte{0xc4, 0xe3, 0xed, 0x46, 0xc3, 4}, wantOK: true}, + {name: "128-bit vector length", mode: 64, encoding: []byte{0xc4, 0xe3, 0x69, 0x46, 0xc3, 4}, wantOK: true}, + {name: "truncated immediate", mode: 64, encoding: []byte{0xc4, 0xe3, 0x6d, 0x46, 0xc3}, wantOK: true}, + {name: "address override", mode: 64, encoding: []byte{0x67, 0xc4, 0xe3, 0x6d, 0x46, 0xc3, 4}, wantOK: true}, + {name: "legacy prefix", mode: 64, encoding: []byte{0x66, 0xc4, 0xe3, 0x6d, 0x46, 0xc3, 4}}, + {name: "wrong opcode", mode: 64, encoding: []byte{0xc4, 0xe3, 0x6d, 0x47, 0xc3, 4}}, + {name: "wrong map", mode: 64, encoding: []byte{0xc4, 0xe2, 0x6d, 0x46, 0xc3, 4}}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86Permute128Instruction(test.encoding, test.mode) + if ok != test.wantOK { + t.Fatalf("encoding %x returned ok=%v err=%v, want ok=%v", test.encoding, ok, err, test.wantOK) + } + if test.wantOK && err == nil { + t.Fatalf("invalid encoding %x was accepted", test.encoding) + } + if !test.wantOK && err != nil { + t.Fatalf("unrelated encoding %x returned err=%v", test.encoding, err) + } + }) + } +} diff --git a/amd64_raw_permute_inlane_test.go b/amd64_raw_permute_inlane_test.go new file mode 100644 index 00000000..40409254 --- /dev/null +++ b/amd64_raw_permute_inlane_test.go @@ -0,0 +1,294 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +func encodeX86RawVEXInLaneFloatingPermute(double, immediate bool, vectorBits byte, first, second, destination int, imm byte) []byte { + mapNumber := byte(2) + opcode := byte(0x0c) + if immediate { + mapNumber = 3 + opcode = 0x04 + } + if double { + opcode++ + } + p0 := byte((^destination>>3)&1)<<7 | 0x40 | byte((^first>>3)&1)<<5 | mapNumber + p1 := byte(^second&15)<<3 | vectorBits<<2 | 1 + if immediate { + p1 = 0x78 | vectorBits<<2 | 1 + } + code := []byte{0xc4, p0, p1, opcode, byte(0xc0 | destination&7<<3 | first&7)} + if immediate { + code = append(code, imm) + } + return code +} + +func encodeX86RawEVEXInLaneFloatingPermute(double, immediate bool, vectorBits byte, mask int, zeroing, broadcast bool, first, second, destination int, imm byte) []byte { + mapNumber := byte(2) + opcode := byte(0x0c) + if immediate { + mapNumber = 3 + opcode = 0x04 + } + if double { + opcode++ + } + p0 := byte((^destination>>3)&1)<<7 | + byte((^first>>4)&1)<<6 | + byte((^first>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | mapNumber + p1 := byte(^second&15)<<3 | 5 + p2 := vectorBits<<5 | byte((^second>>4)&1)<<3 | byte(mask) + if immediate { + p1 = 0x7d + p2 |= 0x08 + } + if double { + p1 |= 0x80 + } + if zeroing { + p2 |= 0x80 + } + if broadcast { + p2 |= 0x10 + } + code := []byte{0x62, p0, p1, p2, opcode, byte(0xc0 | destination&7<<3 | first&7)} + if immediate { + code = append(code, imm) + } + return code +} + +func TestDecodeX86RawDirectiveGroupReportedSegDSPVPERMILPS(t *testing.T) { + // vpermilps $180, %ymm2, %ymm3; + // vblendps $72, %ymm3, %ymm1, %ymm3 + code := []byte{0xc4, 0xe3, 0x7d, 0x04, 0xda, 0xb4, 0xc4, 0xe3, 0x75, 0x0c, 0xdb, 0x48} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "segdsp VPERMILPS sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 2 || !strings.HasPrefix(decoded[0].Raw, "VPERMILPS $180, Y2, Y3 ") { + t.Fatalf("decoded %x as %#v", code, decoded) + } +} + +func TestDecodedX86RawInLaneFloatingPermuteCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, double := range []bool{false, true} { + op := "VPERMILPS" + if double { + op = "VPERMILPD" + } + for vectorBits := byte(0); vectorBits < 2; vectorBits++ { + vectorName := [...]string{"X", "Y"}[vectorBits] + for first := 0; first < 16; first++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86RawVEXInLaneFloatingPermute(double, true, vectorBits, first, 0, destination, 0xa5) + got, length, ok, err := decodedX86InLaneFloatingPermuteInstruction(code, 64) + want := fmt.Sprintf("%s $165, %s%d, %s%d", op, vectorName, first, vectorName, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + for first := 0; first < 16; first++ { + for second := 0; second < 16; second++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86RawVEXInLaneFloatingPermute(double, false, vectorBits, first, second, destination, 0) + got, length, ok, err := decodedX86InLaneFloatingPermuteInstruction(code, 64) + want := fmt.Sprintf("%s %s%d, %s%d, %s%d", op, vectorName, first, vectorName, second, vectorName, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + for vectorBits := byte(0); vectorBits < 3; vectorBits++ { + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + for _, masking := range []struct { + mask int + zeroing bool + suffix string + }{{}, {mask: 3}, {mask: 7, zeroing: true, suffix: ".Z"}} { + for first := 0; first < 32; first++ { + for destination := 0; destination < 32; destination++ { + code := encodeX86RawEVEXInLaneFloatingPermute(double, true, vectorBits, masking.mask, masking.zeroing, false, first, 0, destination, 0x5a) + got, length, ok, err := decodedX86InLaneFloatingPermuteInstruction(code, 64) + args := []string{"$90", fmt.Sprintf("%s%d", vectorName, first)} + if masking.mask != 0 { + args = append(args, fmt.Sprintf("K%d", masking.mask)) + } + args = append(args, fmt.Sprintf("%s%d", vectorName, destination)) + want := op + masking.suffix + " " + strings.Join(args, ", ") + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + for first := 0; first < 32; first++ { + for second := 0; second < 32; second++ { + for destination := 0; destination < 32; destination++ { + code := encodeX86RawEVEXInLaneFloatingPermute(double, false, vectorBits, masking.mask, masking.zeroing, false, first, second, destination, 0) + got, length, ok, err := decodedX86InLaneFloatingPermuteInstruction(code, 64) + args := []string{fmt.Sprintf("%s%d", vectorName, first), fmt.Sprintf("%s%d", vectorName, second)} + if masking.mask != 0 { + args = append(args, fmt.Sprintf("K%d", masking.mask)) + } + args = append(args, fmt.Sprintf("%s%d", vectorName, destination)) + want := op + masking.suffix + " " + strings.Join(args, ", ") + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + } + } + if count != 625664 { + t.Fatalf("covered %d in-lane floating-permute register encodings, want 625664", count) + } +} + +func TestDecodedX86RawInLaneFloatingPermuteMemoryAndInvalidForms(t *testing.T) { + vexMemory := []byte{0xc4, 0x03, 0x7d, 0x05, 0x7c, 0x8b, 0x02, 0xfe} + got, length, ok, err := decodedX86InLaneFloatingPermuteInstruction(vexMemory, 64) + wantMemory := MemRef{Base: "R11", Index: "R9", Scale: 4, Off: 2} + if err != nil || !ok || length != len(vexMemory) || got.Op != "VPERMILPD" || got.Args[0].Imm != 254 || got.Args[2].String() != "Y15" || got.Args[1].Kind != OpMem || !reflect.DeepEqual(got.Args[1].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", vexMemory, got, length, ok, err) + } + evexImmediateMemory := []byte{0x62, 0xf3, 0xfd, 0xdb, 0x05, 0x50, 0x02, 0x07} + got, length, ok, err = decodedX86InLaneFloatingPermuteInstruction(evexImmediateMemory, 64) + wantMemory = MemRef{Base: "AX", Off: 16} + if err != nil || !ok || length != len(evexImmediateMemory) || got.Op != "VPERMILPD.BCST.Z" || got.Args[0].Imm != 7 || got.Args[2].String() != "K3" || got.Args[3].String() != "Z2" || got.Args[1].Kind != OpMem || !reflect.DeepEqual(got.Args[1].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", evexImmediateMemory, got, length, ok, err) + } + evexVariableMemory := []byte{0x62, 0xf2, 0x75, 0x38, 0x0c, 0x50, 0x02} + got, length, ok, err = decodedX86InLaneFloatingPermuteInstruction(evexVariableMemory, 64) + wantMemory = MemRef{Base: "AX", Off: 8} + if err != nil || !ok || length != len(evexVariableMemory) || got.Op != "VPERMILPS.BCST" || got.Args[1].String() != "Y1" || got.Args[2].String() != "Y2" || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", evexVariableMemory, got, length, ok, err) + } + + validVEXImmediate := encodeX86RawVEXInLaneFloatingPermute(false, true, 0, 7, 0, 7, 1) + validEVEXVariable := encodeX86RawEVEXInLaneFloatingPermute(false, false, 2, 0, false, false, 7, 6, 5, 0) + validEVEXImmediate := encodeX86RawEVEXInLaneFloatingPermute(false, true, 2, 0, false, false, 7, 0, 5, 1) + for name, invalid := range map[string][]byte{ + "vex missing immediate": validVEXImmediate[:len(validVEXImmediate)-1], + "vex W": {validVEXImmediate[0], validVEXImmediate[1], validVEXImmediate[2] | 0x80, validVEXImmediate[3], validVEXImmediate[4], validVEXImmediate[5]}, + "vex prefix": {validVEXImmediate[0], validVEXImmediate[1], validVEXImmediate[2] &^ 0x01, validVEXImmediate[3], validVEXImmediate[4], validVEXImmediate[5]}, + "vex immediate vvvv": {validVEXImmediate[0], validVEXImmediate[1], validVEXImmediate[2] &^ 0x08, validVEXImmediate[3], validVEXImmediate[4], validVEXImmediate[5]}, + "evex fixed bit": {validEVEXVariable[0], validEVEXVariable[1], validEVEXVariable[2] &^ 0x04, validEVEXVariable[3], validEVEXVariable[4], validEVEXVariable[5]}, + "evex wrong W": {validEVEXVariable[0], validEVEXVariable[1], validEVEXVariable[2] | 0x80, validEVEXVariable[3], validEVEXVariable[4], validEVEXVariable[5]}, + "evex immediate vvvvv": {validEVEXImmediate[0], validEVEXImmediate[1], validEVEXImmediate[2] &^ 0x08, validEVEXImmediate[3] &^ 0x08, validEVEXImmediate[4], validEVEXImmediate[5], validEVEXImmediate[6]}, + "evex reserved length": {validEVEXVariable[0], validEVEXVariable[1], validEVEXVariable[2], validEVEXVariable[3] | 0x60, validEVEXVariable[4], validEVEXVariable[5]}, + "zero without mask": {validEVEXVariable[0], validEVEXVariable[1], validEVEXVariable[2], validEVEXVariable[3] | 0x80, validEVEXVariable[4], validEVEXVariable[5]}, + "register broadcast": {validEVEXVariable[0], validEVEXVariable[1], validEVEXVariable[2], validEVEXVariable[3] | 0x10, validEVEXVariable[4], validEVEXVariable[5]}, + "address override": append([]byte{0x67}, validVEXImmediate...), + } { + if instruction, _, matched, decodeErr := decodedX86InLaneFloatingPermuteInstruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, invalid, instruction, matched, decodeErr) + } + } + masked386 := encodeX86RawEVEXInLaneFloatingPermute(false, false, 0, 1, false, false, 0, 1, 2, 0) + if instruction, _, matched, decodeErr := decodedX86InLaneFloatingPermuteInstruction(masked386, 32); !matched || decodeErr == nil { + t.Fatalf("386 masked encoding %x decoded as %+v, ok=%v, err=%v", masked386, instruction, matched, decodeErr) + } + highZ386 := encodeX86RawEVEXInLaneFloatingPermute(false, false, 2, 0, false, false, 8, 1, 2, 0) + if instruction, _, matched, decodeErr := decodedX86InLaneFloatingPermuteInstruction(highZ386, 32); !matched || decodeErr == nil { + t.Fatalf("386 high-Z encoding %x decoded as %+v, ok=%v, err=%v", highZ386, instruction, matched, decodeErr) + } +} + +func TestX86InLaneFloatingPermuteRawGo127ArchitectureOracle(t *testing.T) { + const accepted386 = `TEXT ok(SB),$0-0 + VPERMILPS $7, X0, X1 + VPERMILPD X0, X1, X2 + VPERMILPS $7, X20, X21 + VPERMILPD Z0, Z6, Z7 + RET +` + requireX86GoAssemblerResult(t, "386", accepted386, true) + for _, instruction := range []string{ + "VPERMILPS $7, Z8, Z0", + "VPERMILPD Z0, Z1, Z8", + "VPERMILPS X0, X1, K1, X2", + } { + requireX86GoAssemblerResult(t, "386", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + } +} + +func TestTranslateX86RawInLaneFloatingPermuteTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT raw_in_lane_floating_permute(SB),NOSPLIT,$0-0\n") + for _, double := range []bool{false, true} { + var encodings [][]byte + if target.goarch == "amd64" { + encodings = append(encodings, + encodeX86RawVEXInLaneFloatingPermute(double, true, 1, 15, 0, 14, 0xa5), + encodeX86RawVEXInLaneFloatingPermute(double, false, 1, 15, 14, 13, 0), + encodeX86RawEVEXInLaneFloatingPermute(double, true, 2, 7, true, false, 31, 0, 30, 0x5a), + encodeX86RawEVEXInLaneFloatingPermute(double, false, 2, 3, false, false, 31, 30, 29, 0), + ) + } else { + encodings = append(encodings, + encodeX86RawVEXInLaneFloatingPermute(double, true, 1, 7, 0, 6, 0xa5), + encodeX86RawVEXInLaneFloatingPermute(double, false, 1, 7, 6, 5, 0), + encodeX86RawEVEXInLaneFloatingPermute(double, true, 0, 0, false, false, 20, 0, 21, 0x5a), + encodeX86RawEVEXInLaneFloatingPermute(double, false, 2, 0, false, false, 5, 6, 7, 0), + ) + } + for _, encoding := range encodings { + for _, value := range encoding { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "raw_in_lane_floating_permute": {Name: "raw_in_lane_floating_permute", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-in-lane-floating-permute-"+target.name+".ll", "raw-in-lane-floating-permute-"+target.name+".o", ll) + }) + } +} diff --git a/amd64_raw_rorx.go b/amd64_raw_rorx.go new file mode 100644 index 00000000..e0c6494b --- /dev/null +++ b/amd64_raw_rorx.go @@ -0,0 +1,82 @@ +package plan9asm + +import "fmt" + +// decodedX86RORXInstruction recognizes the complete BMI2 RORXL/RORXQ Yml, +// Yrl, imm8 family, including register and every source-layout-safe ModRM/SIB +// memory form. x/arch v0.14 reports the VEX.0F3A encoding as an unknown AVX +// opcode, so it must be recovered before generic decoding. +func decodedX86RORXInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vex + } + } + +vex: + if len(code) < i+4 || code[i] != 0xc4 || code[i+1]&0x1f != 3 || code[i+3] != 0xf0 { + return Instr{}, 0, false, nil + } + ok = true + if mode != 32 && mode != 64 { + return Instr{}, 0, true, fmt.Errorf("unsupported x86 mode %d", mode) + } + vexExt, vexByte := code[i+1], code[i+2] + if vexByte&3 != 3 || vexByte&4 != 0 || vexByte&0x78 != 0x78 { + return Instr{}, 0, true, fmt.Errorf("reserved RORX VEX prefix") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + if len(code) <= i+4 { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + rExt := int(^vexExt>>7) & 1 + xExt := int(^vexExt>>6) & 1 + bExt := int(^vexExt>>5) & 1 + width64 := vexByte&0x80 != 0 + modRM := code[i+4] + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && destinationNumber >= 8 { + return Instr{}, 0, true, fmt.Errorf("extended destination register in 32-bit mode") + } + destination, valid := decodedX86GeneralRegister(destinationNumber) + if !valid { + return Instr{}, 0, true, fmt.Errorf("invalid destination register %d", destinationNumber) + } + source, consumed, err := decodedX86VEXRMSource(code[i+4:], mode, bExt, xExt, segment) + if err != nil { + return Instr{}, 0, true, err + } + if len(code) <= i+4+consumed { + return Instr{}, 0, true, fmt.Errorf("missing imm8") + } + immediate := int64(code[i+4+consumed]) + op := Op("RORXL") + if width64 && mode == 64 { + op = "RORXQ" + } + instruction = Instr{ + Op: op, + Args: []Operand{ + {Kind: OpImm, Imm: immediate}, + source, + {Kind: OpReg, Reg: destination}, + }, + Raw: fmt.Sprintf("%s $%d, %s, %s", op, immediate, source.String(), destination), + } + return instruction, i + 5 + consumed, true, nil +} diff --git a/amd64_raw_same_width_conversion.go b/amd64_raw_same_width_conversion.go new file mode 100644 index 00000000..46ce9103 --- /dev/null +++ b/amd64_raw_same_width_conversion.go @@ -0,0 +1,212 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type decodedX86SameWidthConversionProperties struct { + op Op + laneBytes int + sae bool +} + +func decodedX86SameWidthConversionOpcode(opcode, pp byte) (decodedX86SameWidthConversionProperties, bool) { + properties := map[[2]byte]decodedX86SameWidthConversionProperties{ + {0x5b, 0}: {op: "VCVTDQ2PS", laneBytes: 4}, + {0x5b, 1}: {op: "VCVTPS2DQ", laneBytes: 4}, + {0x5b, 2}: {op: "VCVTTPS2DQ", laneBytes: 4, sae: true}, + {0x51, 0}: {op: "VSQRTPS", laneBytes: 4}, + {0x51, 1}: {op: "VSQRTPD", laneBytes: 8}, + }[[2]byte{opcode, pp}] + return properties, properties.op != "" +} + +// decodedX86SameWidthConversionInstruction recognizes every VEX and EVEX +// encoding behind Go 1.27's _yvcvtdq2ps table: VCVTDQ2PS, VCVTPS2DQ, +// VCVTTPS2DQ, VSQRTPD, and VSQRTPS. It covers X/Y/Z registers, ModRM/SIB +// memory, masking, zeroing, broadcasts, embedded rounding, SAE, and compressed +// displacements before the generic decoder can consume an incorrect length. +func decodedX86SameWidthConversionInstruction(code []byte, mode int) (instruction Instr, length int, ok bool, err error) { + i := 0 + segment := Reg("") + addressOverride := false + for i < len(code) { + switch code[i] { + case 0x64: + segment = FS + i++ + case 0x65: + segment = GS + i++ + case 0x67: + addressOverride = true + i++ + default: + goto vectorPrefix + } + } + +vectorPrefix: + if mode != 32 && mode != 64 { + return Instr{}, 0, false, nil + } + if len(code) > i && code[i] == 0x62 { + return decodedX86EVEXSameWidthConversionInstruction(code, i, mode, segment, addressOverride) + } + + var vexLength, rExt, xExt, bExt int + var vexBits, opcode byte + switch { + case len(code) >= i+4 && code[i] == 0xc5: + vexLength = 2 + vexBits = code[i+1] + rExt = int(^vexBits>>7) & 1 + opcode = code[i+2] + case len(code) >= i+5 && code[i] == 0xc4 && code[i+1]&0x1f == 1: + vexLength = 3 + vexBits = code[i+2] + rExt = int(^code[i+1]>>7) & 1 + xExt = int(^code[i+1]>>6) & 1 + bExt = int(^code[i+1]>>5) & 1 + opcode = code[i+3] + default: + return Instr{}, 0, false, nil + } + properties, recognized := decodedX86SameWidthConversionOpcode(opcode, vexBits&3) + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if vexLength == 3 && vexBits&0x80 != 0 { + return Instr{}, 0, true, fmt.Errorf("VEX.W must be zero") + } + if vexBits&0x78 != 0x78 { + return Instr{}, 0, true, fmt.Errorf("VEX.vvvv must be reserved") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + opcodeIndex := i + vexLength + modRMIndex := opcodeIndex + 1 + if len(code) <= modRMIndex { + return Instr{}, 0, true, fmt.Errorf("missing ModRM byte") + } + vectorPrefix := "X" + if vexBits&0x04 != 0 { + vectorPrefix = "Y" + } + modRM := code[modRMIndex] + destinationNumber := int(modRM>>3&7) + rExt*8 + if mode == 32 && (destinationNumber >= 8 || modRM>>6 == 3 && int(modRM&7)+bExt*8 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register in 32-bit mode") + } + source, consumed, decodeErr := decodedX86VEXVectorRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + instruction = Instr{ + Op: properties.op, + Args: []Operand{source, destination}, + Raw: fmt.Sprintf("%s %s, %s", properties.op, source.String(), destination.String()), + } + return instruction, modRMIndex + consumed, true, nil +} + +func decodedX86EVEXSameWidthConversionInstruction(code []byte, i, mode int, segment Reg, addressOverride bool) (instruction Instr, length int, ok bool, err error) { + if len(code) < i+6 { + return Instr{}, 0, false, nil + } + p0, p1, p2 := code[i+1], code[i+2], code[i+3] + opcode := code[i+4] + if p0&0x0f != 1 { + return Instr{}, 0, false, nil + } + properties, recognized := decodedX86SameWidthConversionOpcode(opcode, p1&3) + if !recognized { + return Instr{}, 0, false, nil + } + ok = true + if p1&0x04 == 0 { + return Instr{}, 0, true, fmt.Errorf("invalid EVEX prefix") + } + width64 := p1&0x80 != 0 + wantWidth64 := properties.laneBytes == 8 + if width64 != wantWidth64 { + return Instr{}, 0, true, fmt.Errorf("EVEX.W does not match conversion element type") + } + if p1&0x78 != 0x78 || p2&0x08 == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX.vvvv must be reserved") + } + if addressOverride { + return Instr{}, 0, true, fmt.Errorf("address-size override is not source-layout safe") + } + + modRMIndex := i + 5 + modRM := code[modRMIndex] + vectorBits := (p2 >> 5) & 3 + evexB := p2&0x10 != 0 + registerSource := modRM>>6 == 3 + embeddedControl := evexB && registerSource + broadcast := evexB && !registerSource + if !embeddedControl && vectorBits == 3 { + return Instr{}, 0, true, fmt.Errorf("reserved EVEX vector length") + } + + vectorPrefix := "Z" + vectorWidth := 64 + if !embeddedControl { + vectorPrefix = [...]string{"X", "Y", "Z"}[vectorBits] + vectorWidth = [...]int{16, 32, 64}[vectorBits] + } + disp8Scale := vectorWidth + if broadcast { + disp8Scale = properties.laneBytes + } + maskNumber := int(p2 & 7) + zeroing := p2&0x80 != 0 + if zeroing && maskNumber == 0 { + return Instr{}, 0, true, fmt.Errorf("EVEX zeroing requires a nonzero mask") + } + + rExt := int(^p0>>7) & 1 + rHighExt := int(^p0>>4) & 1 + xExt := int(^p0>>6) & 1 + bExt := int(^p0>>5) & 1 + destinationNumber := int(modRM>>3&7) + rExt*8 + rHighExt*16 + if mode == 32 && (maskNumber != 0 || destinationNumber >= 8 || modRM>>6 == 3 && int(modRM&7)+bExt*8+xExt*16 >= 8) { + return Instr{}, 0, true, fmt.Errorf("extended vector register or mask in 32-bit mode") + } + source, consumed, decodeErr := decodedX86EVEXRMOperand(code[modRMIndex:], mode, bExt, xExt, segment, vectorPrefix, disp8Scale) + if decodeErr != nil { + return Instr{}, 0, true, decodeErr + } + + op := properties.op + if broadcast { + op += ".BCST" + } + if embeddedControl { + if properties.sae { + op += ".SAE" + } else { + op += [...]Op{".RN_SAE", ".RD_SAE", ".RU_SAE", ".RZ_SAE"}[vectorBits] + } + } + if zeroing { + op += ".Z" + } + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("%s%d", vectorPrefix, destinationNumber))} + args := []Operand{source} + if maskNumber != 0 { + args = append(args, Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("K%d", maskNumber))}) + } + args = append(args, destination) + rawArgs := make([]string, len(args)) + for index := range args { + rawArgs[index] = args[index].String() + } + return Instr{Op: op, Args: args, Raw: fmt.Sprintf("%s %s", op, strings.Join(rawArgs, ", "))}, modRMIndex + consumed, true, nil +} diff --git a/amd64_raw_same_width_conversion_test.go b/amd64_raw_same_width_conversion_test.go new file mode 100644 index 00000000..69f73137 --- /dev/null +++ b/amd64_raw_same_width_conversion_test.go @@ -0,0 +1,173 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +type rawSameWidthConversionSpec struct { + opcode byte + pp byte + evexW bool + op Op + laneBytes int + sae bool +} + +var rawSameWidthConversionSpecs = []rawSameWidthConversionSpec{ + {opcode: 0x5b, pp: 0, op: "VCVTDQ2PS", laneBytes: 4}, + {opcode: 0x5b, pp: 1, op: "VCVTPS2DQ", laneBytes: 4}, + {opcode: 0x5b, pp: 2, op: "VCVTTPS2DQ", laneBytes: 4, sae: true}, + {opcode: 0x51, pp: 1, evexW: true, op: "VSQRTPD", laneBytes: 8}, + {opcode: 0x51, pp: 0, op: "VSQRTPS", laneBytes: 4}, +} + +func encodeX86VEXSameWidthConversion(spec rawSameWidthConversionSpec, vex3, width256 bool, destination, source int) []byte { + l := byte(0) + if width256 { + l = 1 + } + modRM := byte(0xc0 | (destination&7)<<3 | source&7) + if !vex3 { + vex1 := byte((1-(destination>>3)&1)<<7 | 15<<3 | int(l)<<2 | int(spec.pp)) + return []byte{0xc5, vex1, spec.opcode, modRM} + } + vex0 := byte((1-(destination>>3)&1)<<7 | 1<<6 | (1-(source>>3)&1)<<5 | 1) + vex1 := byte(15<<3 | int(l)<<2 | int(spec.pp)) + return []byte{0xc4, vex0, vex1, spec.opcode, modRM} +} + +func encodeX86EVEXSameWidthConversion(spec rawSameWidthConversionSpec, vectorBits byte, broadcastOrControl, zeroing bool, mask, destination, source int) []byte { + p0 := byte((1-(destination>>3)&1)<<7 | (1-(source>>4)&1)<<6 | (1-(source>>3)&1)<<5 | (1-(destination>>4)&1)<<4 | 1) + p1 := byte(15<<3 | 1<<2 | int(spec.pp)) + if spec.evexW { + p1 |= 0x80 + } + p2 := byte(int(vectorBits)<<5 | 1<<3 | mask) + if broadcastOrControl { + p2 |= 0x10 + } + if zeroing { + p2 |= 0x80 + } + modRM := byte(0xc0 | (destination&7)<<3 | source&7) + return []byte{0x62, p0, p1, p2, spec.opcode, modRM} +} + +func TestDecodedX86VEXSameWidthConversionCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, spec := range rawSameWidthConversionSpecs { + for _, vex3 := range []bool{false, true} { + for _, width256 := range []bool{false, true} { + prefix := "X" + if width256 { + prefix = "Y" + } + sourceLimit := 16 + if !vex3 { + sourceLimit = 8 + } + for destination := 0; destination < 16; destination++ { + for source := 0; source < sourceLimit; source++ { + code := encodeX86VEXSameWidthConversion(spec, vex3, width256, destination, source) + got, length, ok, err := decodedX86SameWidthConversionInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != spec.op || len(got.Args) != 2 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, spec.op, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + if count != 3840 { + t.Fatalf("covered %d VEX same-width conversion encodings, want 3840", count) + } +} + +func TestDecodedX86EVEXSameWidthConversionCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, spec := range rawSameWidthConversionSpecs { + for vectorBits := byte(0); vectorBits < 3; vectorBits++ { + prefix := [...]string{"X", "Y", "Z"}[vectorBits] + for destination := 0; destination < 32; destination++ { + for source := 0; source < 32; source++ { + code := encodeX86EVEXSameWidthConversion(spec, vectorBits, false, false, 1, destination, source) + got, length, ok, err := decodedX86SameWidthConversionInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source), "K1", fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != spec.op || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, spec.op, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + if count != 15360 { + t.Fatalf("covered %d EVEX same-width conversion encodings, want 15360", count) + } +} + +func TestDecodedX86EVEXSameWidthConversionModifiersMemoryAndInvalid(t *testing.T) { + find := func(op Op) rawSameWidthConversionSpec { + t.Helper() + for _, spec := range rawSameWidthConversionSpecs { + if spec.op == op { + return spec + } + } + t.Fatalf("missing raw same-width spec %s", op) + return rawSameWidthConversionSpec{} + } + convert := find("VCVTDQ2PS") + truncate := find("VCVTTPS2DQ") + sqrt := find("VSQRTPD") + tests := []struct { + name string + code []byte + op Op + args []string + }{ + {name: "vex weaviate", code: []byte{0xc5, 0xfc, 0x5b, 0xe4}, op: "VCVTDQ2PS", args: []string{"Y4", "Y4"}}, + {name: "broadcast zeroing", code: []byte{0x62, 0xf1, 0x7c, 0xdb, 0x5b, 0x50, 0x7f}, op: "VCVTDQ2PS.BCST.Z", args: []string{"508(AX)", "K3", "Z2"}}, + {name: "round up", code: encodeX86EVEXSameWidthConversion(convert, 2, true, false, 2, 4, 5), op: "VCVTDQ2PS.RU_SAE", args: []string{"Z5", "K2", "Z4"}}, + {name: "truncate sae zeroing", code: encodeX86EVEXSameWidthConversion(truncate, 0, true, true, 3, 6, 7), op: "VCVTTPS2DQ.SAE.Z", args: []string{"Z7", "K3", "Z6"}}, + {name: "sqrt round zero", code: encodeX86EVEXSameWidthConversion(sqrt, 3, true, false, 0, 8, 9), op: "VSQRTPD.RZ_SAE", args: []string{"Z9", "Z8"}}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + got, length, ok, err := decodedX86SameWidthConversionInstruction(test.code, 64) + if err != nil || !ok || length != len(test.code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", test.code, got, length, ok, err) + } + if got.Op != test.op || len(got.Args) != len(test.args) { + t.Fatalf("decode %x = %+v, want %s %s", test.code, got, test.op, strings.Join(test.args, ", ")) + } + for index := range test.args { + if got.Args[index].String() != test.args[index] { + t.Fatalf("decode %x = %+v, want %s %s", test.code, got, test.op, strings.Join(test.args, ", ")) + } + } + }) + } + + zeroWithoutMask := encodeX86EVEXSameWidthConversion(convert, 0, false, true, 0, 0, 0) + reservedLength := encodeX86EVEXSameWidthConversion(convert, 3, false, false, 0, 0, 0) + wrongW := encodeX86EVEXSameWidthConversion(convert, 0, false, false, 0, 0, 0) + wrongW[2] |= 0x80 + for _, code := range [][]byte{zeroWithoutMask, reservedLength, wrongW} { + if _, _, ok, err := decodedX86SameWidthConversionInstruction(code, 64); !ok || err == nil { + t.Fatalf("invalid encoding %x returned ok=%v err=%v", code, ok, err) + } + } +} diff --git a/amd64_raw_scalar_extract_test.go b/amd64_raw_scalar_extract_test.go new file mode 100644 index 00000000..c8e41cf3 --- /dev/null +++ b/amd64_raw_scalar_extract_test.go @@ -0,0 +1,199 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +type rawPackedScalarExtractSpec struct { + op Op + mapNumber byte + opcode byte + width64 bool +} + +var rawPackedScalarExtractSpecs = []rawPackedScalarExtractSpec{ + {op: "VPEXTRB", mapNumber: 3, opcode: 0x14}, + {op: "VPEXTRW", mapNumber: 3, opcode: 0x15}, + {op: "VPEXTRW", mapNumber: 1, opcode: 0xc5}, + {op: "VPEXTRD", mapNumber: 3, opcode: 0x16}, + {op: "VPEXTRQ", mapNumber: 3, opcode: 0x16, width64: true}, + {op: "VEXTRACTPS", mapNumber: 3, opcode: 0x17}, +} + +func encodeX86RawVEXPackedScalarExtract(spec rawPackedScalarExtractSpec, source, destination int, immediate byte) []byte { + p0 := byte((^source>>3)&1)<<7 | 0x40 | byte((^destination>>3)&1)<<5 | spec.mapNumber + p1 := byte(0x79) + if spec.width64 { + p1 |= 0x80 + } + modRM := byte(0xc0 | source&7<<3 | destination&7) + return []byte{0xc4, p0, p1, spec.opcode, modRM, immediate} +} + +func encodeX86RawEVEXPackedScalarExtract(spec rawPackedScalarExtractSpec, source, destination int, immediate byte) []byte { + p0 := byte((^source>>3)&1)<<7 | + 0x40 | + byte((^destination>>3)&1)<<5 | + byte((^source>>4)&1)<<4 | + spec.mapNumber + p1 := byte(0x7d) + if spec.width64 { + p1 |= 0x80 + } + modRM := byte(0xc0 | source&7<<3 | destination&7) + return []byte{0x62, p0, p1, 0x08, spec.opcode, modRM, immediate} +} + +func TestDecodeX86RawDirectiveGroupReportedSegDSPVEXTRACTPS(t *testing.T) { + // vmovss %xmm0, (%rdi); vextractps $1, %xmm0, 4(%rdi) + code := []byte{0xc5, 0xfa, 0x11, 0x07, 0xc4, 0xe3, 0x79, 0x17, 0x47, 0x04, 0x01} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "segdsp VEXTRACTPS sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 2 || !strings.HasPrefix(decoded[1].Raw, "VEXTRACTPS $1, X0, 4(DI) ") { + t.Fatalf("decoded %x as %#v", code, decoded) + } +} + +func TestDecodedX86RawPackedScalarExtractCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, spec := range rawPackedScalarExtractSpecs { + for source := 0; source < 16; source++ { + for destination := 0; destination < 16; destination++ { + immediate := byte(source*16 + destination) + code := encodeX86RawVEXPackedScalarExtract(spec, source, destination, immediate) + got, length, ok, err := decodedX86PackedScalarExtractInstruction(code, 64) + want := fmt.Sprintf("%s $%d, X%d, %s", spec.op, immediate, source, mustDecodedX86GeneralRegister(t, destination)) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + for source := 0; source < 32; source++ { + for destination := 0; destination < 16; destination++ { + immediate := byte(source*16 + destination) + code := encodeX86RawEVEXPackedScalarExtract(spec, source, destination, immediate) + got, length, ok, err := decodedX86PackedScalarExtractInstruction(code, 64) + want := fmt.Sprintf("%s $%d, X%d, %s", spec.op, immediate, source, mustDecodedX86GeneralRegister(t, destination)) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + if count != 4608 { + t.Fatalf("covered %d packed scalar-extract register encodings, want 4608", count) + } +} + +func TestDecodedX86RawPackedScalarExtractMemoryAndInvalidForms(t *testing.T) { + vexMemory := []byte{0xc4, 0x03, 0x79, 0x17, 0x7c, 0x8b, 0x01, 0xff} + got, length, ok, err := decodedX86PackedScalarExtractInstruction(vexMemory, 64) + wantMemory := MemRef{Base: "R11", Index: "R9", Scale: 4, Off: 1} + if err != nil || !ok || length != len(vexMemory) || got.Op != "VEXTRACTPS" || len(got.Args) != 3 || got.Args[1].String() != "X15" || got.Args[2].Kind != OpMem || !reflect.DeepEqual(got.Args[2].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", vexMemory, got, length, ok, err) + } + + evexMemory := []byte{0x62, 0x03, 0xfd, 0x08, 0x16, 0x7c, 0x8b, 0x02, 0x01} + got, length, ok, err = decodedX86PackedScalarExtractInstruction(evexMemory, 64) + wantMemory.Off = 16 + if err != nil || !ok || length != len(evexMemory) || got.Op != "VPEXTRQ" || len(got.Args) != 3 || got.Args[1].String() != "X31" || got.Args[2].Kind != OpMem || !reflect.DeepEqual(got.Args[2].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", evexMemory, got, length, ok, err) + } + + twoByteVEX := []byte{0xc5, 0xf9, 0xc5, 0xc1, 0x01} + got, length, ok, err = decodedX86PackedScalarExtractInstruction(twoByteVEX, 64) + if err != nil || !ok || length != len(twoByteVEX) || got.Raw != "VPEXTRW $1, X0, CX" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", twoByteVEX, got, length, ok, err) + } + + validVEX := encodeX86RawVEXPackedScalarExtract(rawPackedScalarExtractSpecs[0], 7, 7, 1) + validEVEX := encodeX86RawEVEXPackedScalarExtract(rawPackedScalarExtractSpecs[0], 31, 15, 1) + for name, invalid := range map[string][]byte{ + "vex reserved vvvv": {validVEX[0], validVEX[1], validVEX[2] &^ 0x08, validVEX[3], validVEX[4], validVEX[5]}, + "vex vector length": {validVEX[0], validVEX[1], validVEX[2] | 0x04, validVEX[3], validVEX[4], validVEX[5]}, + "evex mask": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 1, validEVEX[4], validEVEX[5], validEVEX[6]}, + "evex vector length": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 0x20, validEVEX[4], validEVEX[5], validEVEX[6]}, + "evex missing fixed bit": {validEVEX[0], validEVEX[1], validEVEX[2] &^ 0x04, validEVEX[3], validEVEX[4], validEVEX[5], validEVEX[6]}, + "truncated vex immediate": validVEX[:len(validVEX)-1], + "truncated evex immediate": validEVEX[:len(validEVEX)-1], + "address override": append([]byte{0x67}, validVEX...), + } { + if instruction, _, matched, decodeErr := decodedX86PackedScalarExtractInstruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, invalid, instruction, matched, decodeErr) + } + } + if instruction, _, matched, decodeErr := decodedX86PackedScalarExtractInstruction(validEVEX, 32); !matched || decodeErr == nil { + t.Fatalf("386 EVEX encoding %x decoded as %+v, ok=%v, err=%v", validEVEX, instruction, matched, decodeErr) + } + extended386 := encodeX86RawVEXPackedScalarExtract(rawPackedScalarExtractSpecs[0], 8, 0, 1) + if instruction, _, matched, decodeErr := decodedX86PackedScalarExtractInstruction(extended386, 32); !matched || decodeErr == nil { + t.Fatalf("386 extended encoding %x decoded as %+v, ok=%v, err=%v", extended386, instruction, matched, decodeErr) + } +} + +func TestTranslateX86RawPackedScalarExtractTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + registerMax int + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin", registerMax: 15}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", registerMax: 15}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc", registerMax: 15}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu", registerMax: 7}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc", registerMax: 7}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT raw_packed_scalar_extract(SB),NOSPLIT,$0-0\n") + for _, spec := range rawPackedScalarExtractSpecs { + code := encodeX86RawVEXPackedScalarExtract(spec, target.registerMax, target.registerMax, 1) + for _, value := range code { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + if target.goarch == "amd64" { + code = encodeX86RawEVEXPackedScalarExtract(spec, 31, 15, 1) + for _, value := range code { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"raw_packed_scalar_extract": {Name: "raw_packed_scalar_extract", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-packed-scalar-extract-"+target.name+".ll", "raw-packed-scalar-extract-"+target.name+".o", ir) + }) + } +} + +func mustDecodedX86GeneralRegister(t *testing.T, number int) Reg { + t.Helper() + reg, ok := decodedX86GeneralRegister(number) + if !ok { + t.Fatalf("missing general register %d", number) + } + return reg +} diff --git a/amd64_raw_scalar_integer_float_test.go b/amd64_raw_scalar_integer_float_test.go new file mode 100644 index 00000000..63b42ab8 --- /dev/null +++ b/amd64_raw_scalar_integer_float_test.go @@ -0,0 +1,184 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86VEXScalarIntegerFloat(pp byte, width64, vex3 bool, destination, passthrough, source int) []byte { + modRM := byte(0xc0 | (destination&7)<<3 | source&7) + if !vex3 { + vex1 := byte((1-(destination>>3)&1)<<7 | (^passthrough&15)<<3 | int(pp)) + return []byte{0xc5, vex1, 0x2a, modRM} + } + vex0 := byte((1-(destination>>3)&1)<<7 | 1<<6 | (1-(source>>3)&1)<<5 | 1) + vex1 := byte((^passthrough&15)<<3 | int(pp)) + if width64 { + vex1 |= 0x80 + } + return []byte{0xc4, vex0, vex1, 0x2a, modRM} +} + +func encodeX86EVEXScalarIntegerFloat(unsigned bool, pp byte, width64 bool, vectorBits byte, rounding bool, destination, passthrough, source int) []byte { + opcode := byte(0x2a) + if unsigned { + opcode = 0x7b + } + p0 := byte((1-(destination>>3)&1)<<7 | 1<<6 | (1-(source>>3)&1)<<5 | (1-(destination>>4)&1)<<4 | 1) + p1 := byte((^passthrough&15)<<3 | 1<<2 | int(pp)) + if width64 { + p1 |= 0x80 + } + p2 := byte(int(vectorBits)<<5 | (^passthrough>>4&1)<<3) + if rounding { + p2 |= 0x10 + } + modRM := byte(0xc0 | (destination&7)<<3 | source&7) + return []byte{0x62, p0, p1, p2, opcode, modRM} +} + +func scalarIntegerFloatRawOp(unsigned bool, pp byte, width64 bool) Op { + prefix := "VCVTSI2" + if unsigned { + prefix = "VCVTUSI2" + } + result := "SS" + if pp == 3 { + result = "SD" + } + source := "L" + if width64 { + source = "Q" + } + return Op(prefix + result + source) +} + +func TestTranslateRawVEXScalarIntegerFloatWeaviateRegression(t *testing.T) { + const source = `TEXT rawScalarIntegerFloat(SB), $0-0 + LONG $0xc82aeac5 + LONG $0xc02a9ac5 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawScalarIntegerFloat": {Name: "rawScalarIntegerFloat", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if strings.Count(ir, "sitofp i32") != 2 { + t.Fatalf("raw VCVTSI2SSL lowering omitted signed conversions:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-scalar-integer-float.ll", "amd64-raw-scalar-integer-float.o", ir) +} + +func TestDecodedX86VEXScalarIntegerFloatCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, pp := range []byte{2, 3} { + for destination := 0; destination < 16; destination++ { + for passthrough := 0; passthrough < 16; passthrough++ { + for source := 0; source < 8; source++ { + code := encodeX86VEXScalarIntegerFloat(pp, false, false, destination, passthrough, source) + assertDecodedX86ScalarIntegerFloat(t, code, scalarIntegerFloatRawOp(false, pp, false), destination, passthrough, source, "") + count++ + } + } + } + for _, width64 := range []bool{false, true} { + for destination := 0; destination < 16; destination++ { + for passthrough := 0; passthrough < 16; passthrough++ { + for source := 0; source < 16; source++ { + code := encodeX86VEXScalarIntegerFloat(pp, width64, true, destination, passthrough, source) + assertDecodedX86ScalarIntegerFloat(t, code, scalarIntegerFloatRawOp(false, pp, width64), destination, passthrough, source, "") + count++ + } + } + } + } + } + if count != 20480 { + t.Fatalf("covered %d VEX scalar integer-to-float encodings, want 20480", count) + } +} + +func TestDecodedX86EVEXScalarIntegerFloatCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, unsigned := range []bool{false, true} { + for _, pp := range []byte{2, 3} { + for _, width64 := range []bool{false, true} { + for vectorBits := byte(0); vectorBits < 3; vectorBits++ { + for destination := 0; destination < 32; destination++ { + for passthrough := 0; passthrough < 32; passthrough++ { + for source := 0; source < 16; source++ { + code := encodeX86EVEXScalarIntegerFloat(unsigned, pp, width64, vectorBits, false, destination, passthrough, source) + assertDecodedX86ScalarIntegerFloat(t, code, scalarIntegerFloatRawOp(unsigned, pp, width64), destination, passthrough, source, "") + count++ + } + } + } + } + } + } + } + if count != 393216 { + t.Fatalf("covered %d EVEX scalar integer-to-float encodings, want 393216", count) + } +} + +func TestDecodedX86EVEXScalarIntegerFloatRoundingMemoryAndInvalid(t *testing.T) { + for vectorBits, suffix := range []string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"} { + code := encodeX86EVEXScalarIntegerFloat(false, 2, true, byte(vectorBits), true, 17, 18, 9) + assertDecodedX86ScalarIntegerFloat(t, code, "VCVTSI2SSQ."+Op(suffix), 17, 18, 9, "") + } + memory := []byte{0x62, 0xe1, 0xff, 0x00, 0x2a, 0x60, 0x02} + got, length, ok, err := decodedX86ScalarIntegerFloatInstruction(memory, 64) + if err != nil || !ok || length != len(memory) || got.Op != "VCVTSI2SDQ" || len(got.Args) != 3 || got.Args[0].String() != "16(AX)" || got.Args[1].String() != "X16" || got.Args[2].String() != "X20" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", memory, got, length, ok, err) + } + + roundingMemory := encodeX86EVEXScalarIntegerFloat(false, 2, true, 0, true, 0, 0, 0) + roundingMemory[len(roundingMemory)-1] = 0 + nonRounding := encodeX86EVEXScalarIntegerFloat(false, 3, false, 0, true, 0, 0, 0) + invalid := [][]byte{ + encodeX86VEXScalarIntegerFloat(1, false, false, 0, 0, 0), + encodeX86EVEXScalarIntegerFloat(false, 2, false, 3, false, 0, 0, 0), + roundingMemory, + nonRounding, + } + for _, code := range invalid { + if _, _, ok, err := decodedX86ScalarIntegerFloatInstruction(code, 64); !ok || err == nil { + t.Fatalf("invalid encoding %x returned ok=%v err=%v", code, ok, err) + } + } +} + +func assertDecodedX86ScalarIntegerFloat(t *testing.T, code []byte, op Op, destination, passthrough, source int, sourceText string) { + t.Helper() + got, length, ok, err := decodedX86ScalarIntegerFloatInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + if sourceText == "" { + sourceText = decodedX86ScalarIntegerFloatTestRegister(source) + } + wantArgs := []string{sourceText, fmt.Sprintf("X%d", passthrough), fmt.Sprintf("X%d", destination)} + if got.Op != op || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, op, strings.Join(wantArgs, ", ")) + } +} + +func decodedX86ScalarIntegerFloatTestRegister(number int) string { + register, ok := decodedX86GeneralRegister(number) + if !ok { + return fmt.Sprintf("invalid%d", number) + } + return string(register) +} diff --git a/amd64_raw_scalar_precision_convert_test.go b/amd64_raw_scalar_precision_convert_test.go new file mode 100644 index 00000000..797e1fb1 --- /dev/null +++ b/amd64_raw_scalar_precision_convert_test.go @@ -0,0 +1,268 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +type rawScalarPrecisionConvertSpec struct { + legacyPrefix byte + legacy Op + vector Op + inputBytes int +} + +var rawScalarPrecisionConvertSpecs = []rawScalarPrecisionConvertSpec{ + {legacyPrefix: 0xf3, legacy: "CVTSS2SD", vector: "VCVTSS2SD", inputBytes: 4}, + {legacyPrefix: 0xf2, legacy: "CVTSD2SS", vector: "VCVTSD2SS", inputBytes: 8}, +} + +func encodeX86RawLegacyScalarPrecisionConvert(spec rawScalarPrecisionConvertSpec, source, destination int) []byte { + rex := byte(0x40 | source>>3&1 | destination>>3&1<<2) + code := []byte{spec.legacyPrefix} + if rex != 0x40 { + code = append(code, rex) + } + return append(code, 0x0f, 0x5a, byte(0xc0|destination&7<<3|source&7)) +} + +func encodeX86RawVEXScalarPrecisionConvert(spec rawScalarPrecisionConvertSpec, first, second, destination int) []byte { + p0 := byte((^destination>>3)&1)<<7 | 0x40 | byte((^first>>3)&1)<<5 | 1 + pp := byte(3) + if spec.inputBytes == 4 { + pp = 2 + } + p1 := byte(^second&15)<<3 | pp + return []byte{0xc4, p0, p1, 0x5a, byte(0xc0 | destination&7<<3 | first&7)} +} + +func encodeX86RawEVEXScalarPrecisionConvert(spec rawScalarPrecisionConvertSpec, control int, mask int, zeroing bool, first, second, destination int) []byte { + p0 := byte((^destination>>3)&1)<<7 | + byte((^first>>4)&1)<<6 | + byte((^first>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | 1 + pp := byte(3) + if spec.inputBytes == 4 { + pp = 2 + } + p1 := byte(^second&15)<<3 | 4 | pp + if spec.inputBytes == 8 { + p1 |= 0x80 + } + p2 := byte((^second>>4)&1)<<3 | byte(mask) + if control >= 0 { + p2 |= 0x10 | byte(control)<<5 + } + if zeroing { + p2 |= 0x80 + } + return []byte{0x62, p0, p1, p2, 0x5a, byte(0xc0 | destination&7<<3 | first&7)} +} + +func TestDecodeX86RawDirectiveGroupReportedSegDSPVCVTSD2SS(t *testing.T) { + // vcvtsd2ss %xmm0, %xmm0, %xmm0; + // vmovsd (%rcx), %xmm1 + code := []byte{0xc5, 0xfb, 0x5a, 0xc0, 0xc5, 0xfb, 0x10, 0x09} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "segdsp VCVTSD2SS sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 2 || !strings.HasPrefix(decoded[0].Raw, "VCVTSD2SS X0, X0, X0 ") { + t.Fatalf("decoded %x as %#v", code, decoded) + } +} + +func TestDecodedX86RawScalarPrecisionConvertCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, spec := range rawScalarPrecisionConvertSpecs { + for source := 0; source < 16; source++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86RawLegacyScalarPrecisionConvert(spec, source, destination) + got, length, ok, err := decodedX86ScalarPrecisionConvertInstruction(code, 64) + want := fmt.Sprintf("%s X%d, X%d", spec.legacy, source, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + for first := 0; first < 16; first++ { + for second := 0; second < 16; second++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86RawVEXScalarPrecisionConvert(spec, first, second, destination) + got, length, ok, err := decodedX86ScalarPrecisionConvertInstruction(code, 64) + want := fmt.Sprintf("%s X%d, X%d, X%d", spec.vector, first, second, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + controls := []int{-1, 0} + if spec.inputBytes == 8 { + controls = []int{-1, 0, 1, 2, 3} + } + for _, control := range controls { + for _, masking := range []struct { + mask int + zeroing bool + }{{}, {mask: 3}, {mask: 7, zeroing: true}} { + for first := 0; first < 32; first++ { + for second := 0; second < 32; second++ { + for destination := 0; destination < 32; destination++ { + code := encodeX86RawEVEXScalarPrecisionConvert(spec, control, masking.mask, masking.zeroing, first, second, destination) + got, length, ok, err := decodedX86ScalarPrecisionConvertInstruction(code, 64) + suffix := "" + if control >= 0 { + if spec.inputBytes == 4 { + suffix = ".SAE" + } else { + suffix = "." + [...]string{"RN_SAE", "RD_SAE", "RU_SAE", "RZ_SAE"}[control] + } + } + if masking.zeroing { + suffix += ".Z" + } + args := []string{fmt.Sprintf("X%d", first), fmt.Sprintf("X%d", second)} + if masking.mask != 0 { + args = append(args, fmt.Sprintf("K%d", masking.mask)) + } + args = append(args, fmt.Sprintf("X%d", destination)) + want := string(spec.vector) + suffix + " " + strings.Join(args, ", ") + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + } + } + if count != 696832 { + t.Fatalf("covered %d scalar precision-conversion register encodings, want 696832", count) + } +} + +func TestDecodedX86RawScalarPrecisionConvertMemoryAndInvalidForms(t *testing.T) { + legacyMemory := []byte{0xf3, 0x47, 0x0f, 0x5a, 0x7c, 0x8b, 0x01} + got, length, ok, err := decodedX86ScalarPrecisionConvertInstruction(legacyMemory, 64) + wantMemory := MemRef{Base: "R11", Index: "R9", Scale: 4, Off: 1} + if err != nil || !ok || length != len(legacyMemory) || got.Op != "CVTSS2SD" || got.Args[1].String() != "X15" || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", legacyMemory, got, length, ok, err) + } + vexMemory := []byte{0xc4, 0x01, 0x73, 0x5a, 0x7c, 0x8b, 0x02} + got, length, ok, err = decodedX86ScalarPrecisionConvertInstruction(vexMemory, 64) + wantMemory.Off = 2 + if err != nil || !ok || length != len(vexMemory) || got.Op != "VCVTSD2SS" || got.Args[1].String() != "X1" || got.Args[2].String() != "X15" || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", vexMemory, got, length, ok, err) + } + evexMemory := []byte{0x62, 0xf1, 0x56, 0x83, 0x5a, 0x50, 0x02} + got, length, ok, err = decodedX86ScalarPrecisionConvertInstruction(evexMemory, 64) + wantMemory = MemRef{Base: "AX", Off: 8} + if err != nil || !ok || length != len(evexMemory) || got.Op != "VCVTSS2SD.Z" || got.Args[1].String() != "X21" || got.Args[2].String() != "K3" || got.Args[3].String() != "X2" || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", evexMemory, got, length, ok, err) + } + + validVEX := encodeX86RawVEXScalarPrecisionConvert(rawScalarPrecisionConvertSpecs[0], 7, 6, 5) + validEVEXSS := encodeX86RawEVEXScalarPrecisionConvert(rawScalarPrecisionConvertSpecs[0], -1, 0, false, 7, 6, 5) + validEVEXSD := encodeX86RawEVEXScalarPrecisionConvert(rawScalarPrecisionConvertSpecs[1], -1, 0, false, 7, 6, 5) + for name, invalid := range map[string][]byte{ + "vex W": {validVEX[0], validVEX[1], validVEX[2] | 0x80, validVEX[3], validVEX[4]}, + "vex L": {validVEX[0], validVEX[1], validVEX[2] | 0x04, validVEX[3], validVEX[4]}, + "evex fixed bit": {validEVEXSS[0], validEVEXSS[1], validEVEXSS[2] &^ 0x04, validEVEXSS[3], validEVEXSS[4], validEVEXSS[5]}, + "evex SS wrong W": {validEVEXSS[0], validEVEXSS[1], validEVEXSS[2] | 0x80, validEVEXSS[3], validEVEXSS[4], validEVEXSS[5]}, + "evex SD wrong W": {validEVEXSD[0], validEVEXSD[1], validEVEXSD[2] &^ 0x80, validEVEXSD[3], validEVEXSD[4], validEVEXSD[5]}, + "evex length without SAE": {validEVEXSS[0], validEVEXSS[1], validEVEXSS[2], validEVEXSS[3] | 0x20, validEVEXSS[4], validEVEXSS[5]}, + "zero without mask": {validEVEXSS[0], validEVEXSS[1], validEVEXSS[2], validEVEXSS[3] | 0x80, validEVEXSS[4], validEVEXSS[5]}, + "SS explicit rounding": {validEVEXSS[0], validEVEXSS[1], validEVEXSS[2], validEVEXSS[3] | 0x30, validEVEXSS[4], validEVEXSS[5]}, + "address override": append([]byte{0x67}, validVEX...), + } { + if instruction, _, matched, decodeErr := decodedX86ScalarPrecisionConvertInstruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, invalid, instruction, matched, decodeErr) + } + } + roundingMemory := []byte{0x62, 0xf1, 0xff, 0x10, 0x5a, 0x00} + if instruction, _, matched, decodeErr := decodedX86ScalarPrecisionConvertInstruction(roundingMemory, 64); !matched || decodeErr == nil { + t.Fatalf("rounding memory encoding %x decoded as %+v, ok=%v, err=%v", roundingMemory, instruction, matched, decodeErr) + } + masked386 := encodeX86RawEVEXScalarPrecisionConvert(rawScalarPrecisionConvertSpecs[0], -1, 1, false, 0, 1, 2) + if instruction, _, matched, decodeErr := decodedX86ScalarPrecisionConvertInstruction(masked386, 32); !matched || decodeErr == nil { + t.Fatalf("386 masked encoding %x decoded as %+v, ok=%v, err=%v", masked386, instruction, matched, decodeErr) + } +} + +func TestTranslateX86RawScalarPrecisionConvertTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT raw_scalar_precision_convert(SB),NOSPLIT,$0-0\n") + for _, spec := range rawScalarPrecisionConvertSpecs { + var encodings [][]byte + if target.goarch == "amd64" { + control := 0 + if spec.inputBytes == 8 { + control = 3 + } + encodings = append(encodings, + encodeX86RawLegacyScalarPrecisionConvert(spec, 15, 14), + encodeX86RawVEXScalarPrecisionConvert(spec, 15, 14, 13), + encodeX86RawEVEXScalarPrecisionConvert(spec, -1, 3, true, 31, 30, 29), + encodeX86RawEVEXScalarPrecisionConvert(spec, control, 7, true, 31, 30, 29), + ) + } else { + control := 0 + if spec.inputBytes == 8 { + control = 2 + } + encodings = append(encodings, + encodeX86RawLegacyScalarPrecisionConvert(spec, 7, 6), + encodeX86RawVEXScalarPrecisionConvert(spec, 7, 6, 5), + encodeX86RawEVEXScalarPrecisionConvert(spec, -1, 0, false, 20, 21, 22), + encodeX86RawEVEXScalarPrecisionConvert(spec, control, 0, false, 20, 21, 22), + ) + } + for _, encoding := range encodings { + for _, value := range encoding { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "raw_scalar_precision_convert": {Name: "raw_scalar_precision_convert", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-scalar-precision-convert-"+target.name+".ll", "raw-scalar-precision-convert-"+target.name+".o", ll) + }) + } +} diff --git a/amd64_raw_segment_move_test.go b/amd64_raw_segment_move_test.go new file mode 100644 index 00000000..8e60fd2b --- /dev/null +++ b/amd64_raw_segment_move_test.go @@ -0,0 +1,118 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "testing" +) + +func TestDecodedX86RawSegmentMoveCompleteRegisterFamily(t *testing.T) { + segments := []string{"ES", "CS", "SS", "DS", "FS", "GS"} + count := 0 + for _, mode := range []int{32, 64} { + registers := 8 + if mode == 64 { + registers = 16 + } + for segmentNumber, segment := range segments { + for general := 0; general < registers; general++ { + rex := byte(0) + if mode == 64 && general >= 8 { + rex = 0x41 + } + for _, direction := range []struct { + opcode byte + want string + }{ + {opcode: 0x8e, want: fmt.Sprintf("MOVW %s, %s", decodedX86RegisterNameForTest(general), segment)}, + {opcode: 0x8c, want: fmt.Sprintf("MOVW %s, %s", segment, decodedX86RegisterNameForTest(general))}, + } { + code := make([]byte, 0, 3) + if rex != 0 { + code = append(code, rex) + } + code = append(code, direction.opcode, byte(0xc0|segmentNumber<<3|general&7)) + got, length, ok, err := decodedX86SegmentMoveInstruction(code, mode) + if err != nil || !ok || length != len(code) || got.Raw != direction.want { + t.Fatalf("decode mode=%d %x = %+v, length=%d, ok=%v, err=%v; want %q", mode, code, got, length, ok, err, direction.want) + } + count++ + } + } + } + } + if count != 288 { + t.Fatalf("covered %d raw segment-register moves, want 288", count) + } +} + +func decodedX86RegisterNameForTest(number int) string { + reg, ok := decodedX86GeneralRegister(number) + if !ok { + panic(number) + } + return string(reg) +} + +func TestDecodedX86RawSegmentMoveMemoryAndInvalidForms(t *testing.T) { + for _, test := range []struct { + name string + mode int + code []byte + want string + }{ + { + name: "load FS from extended SIB with FS override", + mode: 64, + code: []byte{0x64, 0x43, 0x8e, 0x64, 0x8b, 0x20}, + want: "MOVW 32(R11)(R9*4)(FS), FS", + }, + { + name: "store GS to extended SIB with GS override", + mode: 64, + code: []byte{0x65, 0x43, 0x8c, 0x6c, 0x8b, 0x20}, + want: "MOVW GS, 32(R11)(R9*4)(GS)", + }, + { + name: "386 absolute memory", + mode: 32, + code: []byte{0x66, 0x8e, 0x1d, 0x78, 0x56, 0x34, 0x12}, + want: "MOVW 305419896(), DS", + }, + } { + t.Run(test.name, func(t *testing.T) { + got, length, ok, err := decodedX86SegmentMoveInstruction(test.code, test.mode) + if err != nil || !ok || length != len(test.code) || got.Raw != test.want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", test.code, got, length, ok, err, test.want) + } + }) + } + + for _, test := range []struct { + name string + encoding []byte + wantOK bool + }{ + {name: "reserved segment six", encoding: []byte{0x8e, 0xf0}, wantOK: true}, + {name: "reserved segment seven", encoding: []byte{0x8c, 0xf8}, wantOK: true}, + {name: "REX.R reserved segment", encoding: []byte{0x44, 0x8e, 0xc0}, wantOK: true}, + {name: "RIP relative", encoding: []byte{0x8e, 0x1d, 0, 0, 0, 0}, wantOK: true}, + {name: "address override", encoding: []byte{0x67, 0x8e, 0xd8}, wantOK: true}, + {name: "truncated", encoding: []byte{0x8e}, wantOK: false}, + {name: "unrelated opcode", encoding: []byte{0x8f, 0xd8}, wantOK: false}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86SegmentMoveInstruction(test.encoding, 64) + if ok != test.wantOK { + t.Fatalf("encoding %x returned ok=%v err=%v, want ok=%v", test.encoding, ok, err, test.wantOK) + } + if test.wantOK && err == nil { + t.Fatalf("invalid encoding %x was accepted", test.encoding) + } + if !test.wantOK && err != nil { + t.Fatalf("unrelated encoding %x returned err=%v", test.encoding, err) + } + }) + } +} diff --git a/amd64_raw_sha_test.go b/amd64_raw_sha_test.go new file mode 100644 index 00000000..7875b2b3 --- /dev/null +++ b/amd64_raw_sha_test.go @@ -0,0 +1,50 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestDecodedX86SHACompleteGo127Family(t *testing.T) { + // Go 1.27 exposes every Intel SHA extension opcode. Cover register and + // memory sources, REX-extended X registers, the SHA1 immediate, and the + // implicit X0 operand used by SHA256RNDS2. + tests := []struct { + name string + code []byte + want string + }{ + {name: "sha1 next e", code: []byte{0x0f, 0x38, 0xc8, 0xca}, want: "SHA1NEXTE X2, X1"}, + {name: "sha1 message 1 high destination", code: []byte{0x44, 0x0f, 0x38, 0xc9, 0xf4}, want: "SHA1MSG1 X4, X14"}, + {name: "sha1 message 2 memory", code: []byte{0x41, 0x0f, 0x38, 0xca, 0x54, 0x8c, 0x20}, want: "SHA1MSG2 32(R12)(CX*4), X2"}, + {name: "sha256 message 1", code: []byte{0x0f, 0x38, 0xcc, 0xe5}, want: "SHA256MSG1 X5, X4"}, + {name: "sha256 message 2", code: []byte{0x0f, 0x38, 0xcd, 0xf5}, want: "SHA256MSG2 X5, X6"}, + {name: "sha1 rounds 4", code: []byte{0x0f, 0x3a, 0xcc, 0xd1, 0x03}, want: "SHA1RNDS4 $3, X1, X2"}, + {name: "sha256 rounds 2 implicit x0", code: []byte{0x0f, 0x38, 0xcb, 0xda}, want: "SHA256RNDS2 X0, X2, X3"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86SHAInstruction(test.code, 64) + if !ok { + t.Fatal("SHA encoding was not recognized") + } + if err != nil { + t.Fatal(err) + } + if length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as length=%d raw=%q, want length=%d raw=%q", test.code, length, instruction.Raw, len(test.code), test.want) + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupReportedMinioSHA256RNDS2(t *testing.T) { + code := []byte{0x0f, 0x38, 0xcb, 0xda} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "minio SHA256RNDS2", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "SHA256RNDS2" || !strings.HasPrefix(decoded[0].Raw, "SHA256RNDS2 X0, X2, X3 ") { + t.Fatalf("decoded reported minio bytes as %#v", decoded) + } +} diff --git a/amd64_raw_svm.go b/amd64_raw_svm.go new file mode 100644 index 00000000..23e8ad75 --- /dev/null +++ b/amd64_raw_svm.go @@ -0,0 +1,23 @@ +package plan9asm + +// decodedX86AMDSystemManagementInstruction covers AMD's fixed 0F 01 D8-DF +// system-management opcode family. golang.org/x/arch/x86asm does not decode +// these privileged instructions, so packages conventionally spell them as +// Plan 9 BYTE directives even though LLVM 22 can assemble their mnemonics. +func decodedX86AMDSystemManagementInstruction(code []byte) (Instr, int, bool) { + if len(code) < 3 || code[0] != 0x0f || code[1] != 0x01 || code[2] < 0xd8 || code[2] > 0xdf { + return Instr{}, 0, false + } + ops := [...]Op{ + "VMRUN", + "VMMCALL", + "VMLOAD", + "VMSAVE", + "STGI", + "CLGI", + "SKINIT", + "INVLPGA", + } + op := ops[code[2]-0xd8] + return Instr{Op: op, Raw: string(op)}, 3, true +} diff --git a/amd64_raw_svm_test.go b/amd64_raw_svm_test.go new file mode 100644 index 00000000..4561e903 --- /dev/null +++ b/amd64_raw_svm_test.go @@ -0,0 +1,109 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestX86RawDecoderCompleteAMDSystemManagementFamily(t *testing.T) { + family := []struct { + opcode byte + op Op + }{ + {opcode: 0xd8, op: "VMRUN"}, + {opcode: 0xd9, op: "VMMCALL"}, + {opcode: 0xda, op: "VMLOAD"}, + {opcode: 0xdb, op: "VMSAVE"}, + {opcode: 0xdc, op: "STGI"}, + {opcode: 0xdd, op: "CLGI"}, + {opcode: 0xde, op: "SKINIT"}, + {opcode: 0xdf, op: "INVLPGA"}, + } + for _, goarch := range []string{"386", "amd64"} { + for _, test := range family { + t.Run(goarch+"/"+string(test.op), func(t *testing.T) { + fn := Func{Instrs: []Instr{ + {Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: 0x0f}}}, + {Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: 0x01}}}, + {Op: OpBYTE, Args: []Operand{{Kind: OpImm, Imm: int64(test.opcode)}}}, + }} + got, err := decodeX86RawDirectives(fn, goarch) + if err != nil { + t.Fatal(err) + } + if len(got.Instrs) != 1 || got.Instrs[0].Op != test.op || len(got.Instrs[0].Args) != 0 { + t.Fatalf("decoded 0f 01 %02x as %#v, want one operand-free %s", test.opcode, got.Instrs, test.op) + } + }) + } + } +} + +func TestTranslateX86RawAMDSystemManagementFamilyAllTargets(t *testing.T) { + const source = `TEXT svmfamily(SB),$0-0 + BYTE $0x0f; BYTE $0x01; BYTE $0xd8 // VMRUN + BYTE $0x0f; BYTE $0x01; BYTE $0xd9 // VMMCALL + BYTE $0x0f; BYTE $0x01; BYTE $0xda // VMLOAD + BYTE $0x0f; BYTE $0x01; BYTE $0xdb // VMSAVE + BYTE $0x0f; BYTE $0x01; BYTE $0xdc // STGI + BYTE $0x0f; BYTE $0x01; BYTE $0xdd // CLGI + BYTE $0x0f; BYTE $0x01; BYTE $0xde // SKINIT + BYTE $0x0f; BYTE $0x01; BYTE $0xdf // INVLPGA + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + requireX86GoAssemblerResult(t, target.goarch, source, true) + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{"svmfamily": {Name: "svmfamily", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, op := range []string{"vmrun", "vmmcall", "vmload", "vmsave", "stgi", "clgi", "skinit", "invlpga"} { + if !strings.Contains(ll, `asm sideeffect "`+op+`"`) { + t.Fatalf("translated IR does not retain %s:\n%s", op, ll) + } + } + compileLLVMToObject(t, llc, target.triple, "raw-svm-family-"+target.name+".ll", "raw-svm-family-"+target.name+".o", ll) + }) + } +} + +func TestTranslateX86AMDSystemManagementFamilyRejectsOperands(t *testing.T) { + for _, op := range []string{"VMRUN", "VMMCALL", "VMLOAD", "VMSAVE", "STGI", "CLGI", "SKINIT", "INVLPGA"} { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+op+" AX\n") + if err != nil { + t.Fatalf("Parse(%s AX) error = %v", op, err) + } + if _, err := Translate(file, Options{ + TargetTriple: "x86_64-unknown-linux-gnu", + Goarch: "amd64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted operand form for fixed no-operand %s", op) + } + } +} diff --git a/amd64_raw_text_blob_test.go b/amd64_raw_text_blob_test.go new file mode 100644 index 00000000..06967f50 --- /dev/null +++ b/amd64_raw_text_blob_test.go @@ -0,0 +1,131 @@ +//go:build !llgo + +package plan9asm + +import ( + "os" + "os/exec" + "path/filepath" + "strconv" + "strings" + "testing" +) + +func TestX86AddressSensitiveRawTextBlobReportedURootFarJump(t *testing.T) { + const source = `TEXT setup(SB),NOSPLIT,$0-0 + MOVL AX, farjump64+6(SB) + JMP farjump64(SB) +TEXT farjump64(SB),NOSPLIT,$0-0 + BYTE $0xff; BYTE $0x2d; LONG $0 + LONG $0 + LONG $8 +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + ir, err := Translate(file, Options{ + Goarch: target.goarch, + TargetTriple: target.triple, + Sigs: map[string]FuncSig{ + "setup": {Name: "setup", Ret: Void}, + "farjump64": {Name: "farjump64", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "define void @farjump64()") || + !strings.Contains(ir, "naked noinline") || + !strings.Contains(ir, `.byte 255, 45, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0`) { + t.Fatalf("byte-exact naked raw TEXT body missing:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "raw-text-"+target.name+".ll", "raw-text-"+target.name+".o", ir) + assertX86RawTextAssemblyBytes(t, llc, target.triple, ir, []byte{0xff, 0x2d, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0}) + }) + } +} + +func assertX86RawTextAssemblyBytes(t *testing.T, llc, triple, ir string, want []byte) { + t.Helper() + dir := t.TempDir() + path := filepath.Join(dir, "raw-text.ll") + if err := os.WriteFile(path, []byte(ir), 0o600); err != nil { + t.Fatal(err) + } + cmd := exec.Command(llc, "-mtriple="+triple, "-filetype=asm", "-o", "-", path) + out, err := cmd.CombinedOutput() + if err != nil { + t.Fatalf("LLVM 22 assembly emission failed: %v\n%s", err, out) + } + var got []byte + for _, line := range strings.Split(string(out), "\n") { + fields := strings.Fields(line) + if len(fields) != 2 || fields[0] != ".byte" { + continue + } + value, err := strconv.ParseUint(fields[1], 0, 8) + if err != nil { + t.Fatalf("parse emitted byte line %q: %v", line, err) + } + got = append(got, byte(value)) + } + if string(got) != string(want) { + t.Fatalf("LLVM 22 emitted raw TEXT bytes %v, want %v\n%s", got, want, out) + } +} + +func TestX86AddressSensitiveRawTextBlobSelection(t *testing.T) { + const source = `TEXT refs(SB),NOSPLIT,$0-0 + MOVL AX, farjump32+1(SB) + LEAQ gdt(SB), CX + MOVL info(SB), BX + RET +TEXT farjump32(SB),NOSPLIT,$0-0 + BYTE $0xea; LONG $0; WORD $0x18 +TEXT gdt(SB),NOSPLIT,$0-0 + QUAD $0; QUAD $0x00cf9a000000ffff +TEXT info(SB),NOSPLIT,$0-0 + LONG $0 +TEXT semantic(SB),NOSPLIT,$0-0 + BYTE $0x90; BYTE $0xc3 +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + normalized, err := normalizeX86RawFile(file, "amd64") + if err != nil { + t.Fatal(err) + } + wants := map[string][]byte{ + "farjump32": {0xea, 0, 0, 0, 0, 0x18, 0}, + "gdt": {0, 0, 0, 0, 0, 0, 0, 0, 0xff, 0xff, 0, 0, 0, 0x9a, 0xcf, 0}, + "info": {0, 0, 0, 0}, + } + for _, fn := range normalized.Funcs { + want, selected := wants[fn.Sym] + if selected && string(fn.X86RawText) != string(want) { + t.Fatalf("%s raw TEXT bytes %v, want %v", fn.Sym, fn.X86RawText, want) + } + if fn.Sym == "semantic" && fn.X86RawText != nil { + t.Fatal("unaddressed raw instruction body bypassed semantic decoding") + } + } +} diff --git a/amd64_raw_unpack_float_test.go b/amd64_raw_unpack_float_test.go new file mode 100644 index 00000000..7c97961e --- /dev/null +++ b/amd64_raw_unpack_float_test.go @@ -0,0 +1,271 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +type rawFloatingUnpackSpec struct { + opcode byte + double bool + high bool +} + +var rawFloatingUnpackSpecs = []rawFloatingUnpackSpec{ + {opcode: 0x14}, + {opcode: 0x15, high: true}, + {opcode: 0x14, double: true}, + {opcode: 0x15, double: true, high: true}, +} + +func (spec rawFloatingUnpackSpec) op(vector bool) Op { + name := "UNPCKL" + if spec.high { + name = "UNPCKH" + } + if vector { + name = "V" + name + } + if spec.double { + name += "PD" + } else { + name += "PS" + } + return Op(name) +} + +func encodeX86RawLegacyFloatingUnpack(spec rawFloatingUnpackSpec, source, destination int) []byte { + code := []byte{} + if spec.double { + code = append(code, 0x66) + } + rex := byte(0x40 | source>>3&1 | destination>>3&1<<2) + if rex != 0x40 { + code = append(code, rex) + } + return append(code, 0x0f, spec.opcode, byte(0xc0|destination&7<<3|source&7)) +} + +func encodeX86RawVEXFloatingUnpack(spec rawFloatingUnpackSpec, vectorBits byte, first, second, destination int) []byte { + p0 := byte((^destination>>3)&1)<<7 | 0x40 | byte((^first>>3)&1)<<5 | 1 + p1 := byte(^second&15)<<3 | vectorBits<<2 + if spec.double { + p1 |= 1 + } + return []byte{0xc4, p0, p1, spec.opcode, byte(0xc0 | destination&7<<3 | first&7)} +} + +func encodeX86RawEVEXFloatingUnpack(spec rawFloatingUnpackSpec, vectorBits byte, mask int, zeroing, broadcast bool, first, second, destination int) []byte { + p0 := byte((^destination>>3)&1)<<7 | + byte((^first>>4)&1)<<6 | + byte((^first>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | 1 + p1 := byte(^second&15)<<3 | 4 + if spec.double { + p1 |= 0x81 + } + p2 := vectorBits<<5 | byte((^second>>4)&1)<<3 | byte(mask) + if zeroing { + p2 |= 0x80 + } + if broadcast { + p2 |= 0x10 + } + return []byte{0x62, p0, p1, p2, spec.opcode, byte(0xc0 | destination&7<<3 | first&7)} +} + +func TestDecodeX86RawDirectiveGroupReportedSegDSPVUNPCKLPS(t *testing.T) { + // vunpcklps %xmm3, %xmm5, %xmm0; + // vinsertf128 $1, %xmm0, %ymm0, %ymm0 + code := []byte{0xc5, 0xd0, 0x14, 0xc3, 0xc4, 0xe3, 0x7d, 0x18, 0xc0, 0x01} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "segdsp VUNPCKLPS sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 2 || !strings.HasPrefix(decoded[0].Raw, "VUNPCKLPS X3, X5, X0 ") { + t.Fatalf("decoded %x as %#v", code, decoded) + } +} + +func TestDecodedX86RawFloatingUnpackCompleteRegisterFamily(t *testing.T) { + count := 0 + for _, spec := range rawFloatingUnpackSpecs { + for first := 0; first < 16; first++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86RawLegacyFloatingUnpack(spec, first, destination) + got, length, ok, err := decodedX86FloatingUnpackInstruction(code, 64) + want := fmt.Sprintf("%s X%d, X%d", spec.op(false), first, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + for vectorBits := byte(0); vectorBits < 2; vectorBits++ { + vectorName := [...]string{"X", "Y"}[vectorBits] + for first := 0; first < 16; first++ { + for second := 0; second < 16; second++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86RawVEXFloatingUnpack(spec, vectorBits, first, second, destination) + got, length, ok, err := decodedX86FloatingUnpackInstruction(code, 64) + want := fmt.Sprintf("%s %s%d, %s%d, %s%d", spec.op(true), vectorName, first, vectorName, second, vectorName, destination) + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + for vectorBits := byte(0); vectorBits < 3; vectorBits++ { + vectorName := [...]string{"X", "Y", "Z"}[vectorBits] + for _, masking := range []struct { + mask int + zeroing bool + suffix string + }{{}, {mask: 3}, {mask: 7, zeroing: true, suffix: ".Z"}} { + for first := 0; first < 32; first++ { + for second := 0; second < 32; second++ { + for destination := 0; destination < 32; destination++ { + code := encodeX86RawEVEXFloatingUnpack(spec, vectorBits, masking.mask, masking.zeroing, false, first, second, destination) + got, length, ok, err := decodedX86FloatingUnpackInstruction(code, 64) + args := []string{fmt.Sprintf("%s%d", vectorName, first), fmt.Sprintf("%s%d", vectorName, second)} + if masking.mask != 0 { + args = append(args, fmt.Sprintf("K%d", masking.mask)) + } + args = append(args, fmt.Sprintf("%s%d", vectorName, destination)) + want := string(spec.op(true)) + masking.suffix + " " + strings.Join(args, ", ") + if err != nil || !ok || length != len(code) || got.Raw != want { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v; want %q", code, got, length, ok, err, want) + } + count++ + } + } + } + } + } + } + if count != 1213440 { + t.Fatalf("covered %d floating-unpack register encodings, want 1213440", count) + } +} + +func TestDecodedX86RawFloatingUnpackMemoryAndInvalidForms(t *testing.T) { + legacyMemory := []byte{0x66, 0x47, 0x0f, 0x15, 0x7c, 0x8b, 0x01} + got, length, ok, err := decodedX86FloatingUnpackInstruction(legacyMemory, 64) + wantMemory := MemRef{Base: "R11", Index: "R9", Scale: 4, Off: 1} + if err != nil || !ok || length != len(legacyMemory) || got.Op != "UNPCKHPD" || got.Args[1].String() != "X15" || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", legacyMemory, got, length, ok, err) + } + vexMemory := []byte{0xc4, 0x01, 0x75, 0x14, 0x7c, 0x8b, 0x02} + got, length, ok, err = decodedX86FloatingUnpackInstruction(vexMemory, 64) + wantMemory.Off = 2 + if err != nil || !ok || length != len(vexMemory) || got.Op != "VUNPCKLPD" || got.Args[1].String() != "Y1" || got.Args[2].String() != "Y15" || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", vexMemory, got, length, ok, err) + } + evexMemory := []byte{0x62, 0x01, 0x85, 0xdf, 0x15, 0x7c, 0x8b, 0x02} + got, length, ok, err = decodedX86FloatingUnpackInstruction(evexMemory, 64) + wantMemory.Off = 16 + if err != nil || !ok || length != len(evexMemory) || got.Op != "VUNPCKHPD.BCST.Z" || got.Args[1].String() != "Z15" || got.Args[2].String() != "K7" || got.Args[3].String() != "Z31" || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", evexMemory, got, length, ok, err) + } + + validVEX := encodeX86RawVEXFloatingUnpack(rawFloatingUnpackSpecs[0], 0, 7, 7, 7) + validEVEX := encodeX86RawEVEXFloatingUnpack(rawFloatingUnpackSpecs[0], 2, 0, false, false, 7, 7, 7) + for name, invalid := range map[string][]byte{ + "vex W": {validVEX[0], validVEX[1], validVEX[2] | 0x80, validVEX[3], validVEX[4]}, + "vex prefix": {validVEX[0], validVEX[1], validVEX[2] | 0x02, validVEX[3], validVEX[4]}, + "evex missing fixed bit": {validEVEX[0], validEVEX[1], validEVEX[2] &^ 0x04, validEVEX[3], validEVEX[4], validEVEX[5]}, + "evex prefix": {validEVEX[0], validEVEX[1], validEVEX[2] | 0x02, validEVEX[3], validEVEX[4], validEVEX[5]}, + "evex reserved length": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 0x60, validEVEX[4], validEVEX[5]}, + "zero without mask": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 0x80, validEVEX[4], validEVEX[5]}, + "register broadcast": {validEVEX[0], validEVEX[1], validEVEX[2], validEVEX[3] | 0x10, validEVEX[4], validEVEX[5]}, + "address override": append([]byte{0x67}, validVEX...), + } { + if instruction, _, matched, decodeErr := decodedX86FloatingUnpackInstruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, invalid, instruction, matched, decodeErr) + } + } + masked386 := encodeX86RawEVEXFloatingUnpack(rawFloatingUnpackSpecs[0], 2, 1, false, false, 0, 1, 2) + if instruction, _, matched, decodeErr := decodedX86FloatingUnpackInstruction(masked386, 32); !matched || decodeErr == nil { + t.Fatalf("386 masked encoding %x decoded as %+v, ok=%v, err=%v", masked386, instruction, matched, decodeErr) + } + highZ386 := encodeX86RawEVEXFloatingUnpack(rawFloatingUnpackSpecs[0], 2, 0, false, false, 8, 1, 2) + if instruction, _, matched, decodeErr := decodedX86FloatingUnpackInstruction(highZ386, 32); !matched || decodeErr == nil { + t.Fatalf("386 high-Z encoding %x decoded as %+v, ok=%v, err=%v", highZ386, instruction, matched, decodeErr) + } +} + +func TestX86FloatingUnpackGo127ArchitectureOracle(t *testing.T) { + const accepted386 = `TEXT ok(SB),$0-0 + VUNPCKLPS X20, X21, X22 + VUNPCKLPD Y20, Y21, Y22 + VUNPCKHPS Z5, Z6, Z7 + VUNPCKHPD.BCST 8(AX), X20, X21 + RET +` + requireX86GoAssemblerResult(t, "386", accepted386, true) + for _, instruction := range []string{ + "VUNPCKLPS Z8, Z1, Z2", + "VUNPCKHPS Z0, Z1, K1, Z2", + } { + requireX86GoAssemblerResult(t, "386", "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n", false) + } +} + +func TestTranslateX86RawFloatingUnpackTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + registerMax int + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin", registerMax: 15}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu", registerMax: 15}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc", registerMax: 15}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu", registerMax: 7}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc", registerMax: 7}, + } { + t.Run(target.name, func(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT raw_floating_unpack(SB),NOSPLIT,$0-0\n") + for _, spec := range rawFloatingUnpackSpecs { + code := [][]byte{ + encodeX86RawLegacyFloatingUnpack(spec, target.registerMax, target.registerMax), + encodeX86RawVEXFloatingUnpack(spec, 1, target.registerMax, target.registerMax, target.registerMax), + } + if target.goarch == "amd64" { + code = append(code, encodeX86RawEVEXFloatingUnpack(spec, 2, 7, true, false, 31, 30, 29)) + } else { + code = append(code, encodeX86RawEVEXFloatingUnpack(spec, 2, 0, false, false, 7, 6, 5)) + } + for _, instruction := range code { + for _, value := range instruction { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: target.goarch, TargetTriple: target.triple, + Sigs: map[string]FuncSig{"raw_floating_unpack": {Name: "raw_floating_unpack", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-floating-unpack-"+target.name+".ll", "raw-floating-unpack-"+target.name+".o", ir) + }) + } +} diff --git a/amd64_raw_valign_test.go b/amd64_raw_valign_test.go new file mode 100644 index 00000000..c8666163 --- /dev/null +++ b/amd64_raw_valign_test.go @@ -0,0 +1,95 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestDecodeX86RawVectorAlignCompleteGo127Family(t *testing.T) { + tests := []struct { + name string + code []byte + want string + }{ + {name: "dword x high masked", code: []byte{0x62, 0xa3, 0x55, 0x01, 0x03, 0xf4, 0xca}, want: "VALIGND $202, X20, X21, K1, X22"}, + {name: "qword y memory zeroing", code: []byte{0x62, 0xd3, 0xf5, 0xaa, 0x03, 0x50, 0x03, 0x96}, want: "VALIGNQ.Z $150, 96(R8), Y1, K2, Y2"}, + {name: "dword z register", code: []byte{0x62, 0x73, 0x55, 0x48, 0x03, 0xce, 0xca}, want: "VALIGND $202, Z6, Z5, Z9"}, + {name: "dword z broadcast high masked", code: []byte{0x62, 0x53, 0x7d, 0x54, 0x03, 0x4c, 0x24, 0x7f, 0x44}, want: "VALIGND.BCST $68, 508(R12), Z16, K4, Z9"}, + {name: "qword z broadcast zeroing", code: []byte{0x62, 0xf3, 0xf5, 0xdb, 0x03, 0x50, 0x7f, 0x09}, want: "VALIGNQ.BCST.Z $9, 1016(AX), Z1, K3, Z2"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + decoded, err := decodeX86RawDirectiveGroup(test.code, 64, 0, "VALIGN", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || !strings.HasPrefix(decoded[0].Raw, test.want+" ") { + t.Fatalf("decoded %x as %#v, want %q", test.code, decoded, test.want) + } + }) + } +} + +func TestDecodedX86RawVectorAlignAllRegisterFields(t *testing.T) { + for _, lane := range []struct { + w byte + op Op + }{ + {w: 0, op: "VALIGND"}, + {w: 1, op: "VALIGNQ"}, + } { + for vectorBits, vectorName := range []string{"X", "Y", "Z"} { + for first := 0; first < 32; first++ { + for second := 0; second < 32; second++ { + for destination := 0; destination < 32; destination++ { + p0 := byte((^destination>>3)&1)<<7 | + byte((^first>>4)&1)<<6 | + byte((^first>>3)&1)<<5 | + byte((^destination>>4)&1)<<4 | 3 + p1 := lane.w<<7 | byte(^second&15)<<3 | 5 + p2 := byte(vectorBits)<<5 | byte((^second>>4)&1)<<3 + modRM := byte(0xc0 | destination&7<<3 | first&7) + encoding := []byte{0x62, p0, p1, p2, 0x03, modRM, 0xa5} + instruction, length, ok, err := decodedX86VectorAlignInstruction(encoding, 64) + if !ok || err != nil || length != len(encoding) { + t.Fatalf("op=%s width=%s first=%d second=%d destination=%d: ok=%v length=%d err=%v", lane.op, vectorName, first, second, destination, ok, length, err) + } + want := fmt.Sprintf("%s $165, %s%d, %s%d, %s%d", lane.op, vectorName, first, vectorName, second, vectorName, destination) + if instruction.Raw != want { + t.Fatalf("encoding %x decoded as %q, want %q", encoding, instruction.Raw, want) + } + } + } + } + } + } +} + +func TestDecodedX86RawVectorAlignRejectsReservedAndUnsafeForms(t *testing.T) { + for _, test := range []struct { + name string + mode int + encoding []byte + wantOK bool + }{ + {name: "386 operand limit", mode: 32, encoding: []byte{0x62, 0xf3, 0x75, 0x08, 0x03, 0xc2, 0x01}, wantOK: true}, + {name: "reserved vector length", mode: 64, encoding: []byte{0x62, 0xf3, 0x75, 0x68, 0x03, 0xc2, 0x01}, wantOK: true}, + {name: "broadcast register", mode: 64, encoding: []byte{0x62, 0xf3, 0x75, 0x18, 0x03, 0xc2, 0x01}, wantOK: true}, + {name: "zero without mask", mode: 64, encoding: []byte{0x62, 0xf3, 0x75, 0x88, 0x03, 0xc2, 0x01}, wantOK: true}, + {name: "address override", mode: 64, encoding: []byte{0x67, 0x62, 0xf3, 0x75, 0x08, 0x03, 0xc2, 0x01}, wantOK: true}, + {name: "missing immediate", mode: 64, encoding: []byte{0x62, 0xf3, 0x75, 0x08, 0x03, 0xc2}, wantOK: false}, + {name: "wrong map", mode: 64, encoding: []byte{0x62, 0xf2, 0x75, 0x08, 0x03, 0xc2, 0x01}, wantOK: false}, + {name: "wrong prefix", mode: 64, encoding: []byte{0x62, 0xf3, 0x74, 0x08, 0x03, 0xc2, 0x01}, wantOK: false}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86VectorAlignInstruction(test.encoding, test.mode) + if ok != test.wantOK { + t.Fatalf("encoding %x: ok=%v, want %v (err=%v)", test.encoding, ok, test.wantOK, err) + } + if test.wantOK && err == nil { + t.Fatalf("encoding %x was recognized without rejection", test.encoding) + } + }) + } +} diff --git a/amd64_raw_vector_float_compare_test.go b/amd64_raw_vector_float_compare_test.go new file mode 100644 index 00000000..589a2cee --- /dev/null +++ b/amd64_raw_vector_float_compare_test.go @@ -0,0 +1,193 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86VEXVectorFloatCompare(pp byte, width256 bool, destination, secondSource, firstSource int, immediate byte) []byte { + l := byte(0) + if width256 { + l = 1 + } + vex0 := byte((1-(destination>>3)&1)<<7 | 1<<6 | (1-(firstSource>>3)&1)<<5 | 1) + vex1 := byte((^secondSource&15)<<3 | int(l)<<2 | int(pp)) + modRM := byte(0xc0 | (destination&7)<<3 | firstSource&7) + return []byte{0xc4, vex0, vex1, 0xc2, modRM, immediate} +} + +func encodeX86VEX2VectorFloatCompare(pp byte, width256 bool, destination, secondSource, firstSource int, immediate byte) []byte { + l := byte(0) + if width256 { + l = 1 + } + vex1 := byte((1-(destination>>3)&1)<<7 | (^secondSource&15)<<3 | int(l)<<2 | int(pp)) + modRM := byte(0xc0 | (destination&7)<<3 | firstSource&7) + return []byte{0xc5, vex1, 0xc2, modRM, immediate} +} + +func encodeX86EVEXVectorFloatCompare(pp, vectorBits byte, broadcastOrSAE bool, writeMask, destinationMask, secondSource, firstSource int, immediate byte) []byte { + p0 := byte(1<<7 | (1-(firstSource>>4)&1)<<6 | (1-(firstSource>>3)&1)<<5 | 1<<4 | 1) + p1 := byte((^secondSource&15)<<3 | 1<<2 | int(pp)) + if pp == 1 || pp == 3 { + p1 |= 0x80 + } + p2 := byte(int(vectorBits)<<5 | (^secondSource>>4&1)<<3 | writeMask) + if broadcastOrSAE { + p2 |= 0x10 + } + modRM := byte(0xc0 | (destinationMask&7)<<3 | firstSource&7) + return []byte{0x62, p0, p1, p2, 0xc2, modRM, immediate} +} + +func vectorFloatCompareRawOp(pp byte) Op { + return [...]Op{"VCMPPS", "VCMPPD", "VCMPSS", "VCMPSD"}[pp] +} + +func TestTranslateRawEVEXVectorFloatCompareWeaviateRegression(t *testing.T) { + const source = `TEXT rawVectorFloatCompare(SB), $0-0 + LONG $0x483cf162; WORD $0x06c2; BYTE $0x0c + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawVectorFloatCompare": {Name: "rawVectorFloatCompare", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "fcmp") { + t.Fatalf("raw EVEX VCMPPS lowering omitted floating compare:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-vector-float-compare.ll", "amd64-raw-vector-float-compare.o", ir) +} + +func TestDecodedX86VEXVectorFloatCompareCompleteRegisterFamily(t *testing.T) { + count := 0 + for pp := byte(0); pp < 4; pp++ { + widths := []bool{false, true} + if pp >= 2 { + widths = []bool{false} + } + for _, width256 := range widths { + prefix := "X" + if width256 { + prefix = "Y" + } + for destination := 0; destination < 16; destination++ { + for secondSource := 0; secondSource < 16; secondSource++ { + for firstSource := 0; firstSource < 16; firstSource++ { + code := encodeX86VEXVectorFloatCompare(pp, width256, destination, secondSource, firstSource, 0xa5) + got, length, ok, err := decodedX86VectorFloatCompareInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{"$165", fmt.Sprintf("%s%d", prefix, firstSource), fmt.Sprintf("%s%d", prefix, secondSource), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != vectorFloatCompareRawOp(pp) || len(got.Args) != 4 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] || got.Args[3].String() != wantArgs[3] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, vectorFloatCompareRawOp(pp), strings.Join(wantArgs, ", ")) + } + count++ + } + for firstSource := 0; firstSource < 8; firstSource++ { + code := encodeX86VEX2VectorFloatCompare(pp, width256, destination, secondSource, firstSource, 0xa5) + got, length, ok, err := decodedX86VectorFloatCompareInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{"$165", fmt.Sprintf("%s%d", prefix, firstSource), fmt.Sprintf("%s%d", prefix, secondSource), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != vectorFloatCompareRawOp(pp) || len(got.Args) != 4 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] || got.Args[3].String() != wantArgs[3] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, vectorFloatCompareRawOp(pp), strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + if count != 36864 { + t.Fatalf("covered %d VEX vector floating compare encodings, want 36864", count) + } +} + +func TestDecodedX86EVEXVectorFloatCompareCompleteRegisterFamily(t *testing.T) { + count := 0 + for pp := byte(0); pp < 4; pp++ { + for vectorBits := byte(0); vectorBits < 3; vectorBits++ { + prefix := [...]string{"X", "Y", "Z"}[vectorBits] + if pp >= 2 { + prefix = "X" + } + for destinationMask := 0; destinationMask < 8; destinationMask++ { + for secondSource := 0; secondSource < 32; secondSource++ { + for firstSource := 0; firstSource < 32; firstSource++ { + code := encodeX86EVEXVectorFloatCompare(pp, vectorBits, false, 1, destinationMask, secondSource, firstSource, 0x5a) + got, length, ok, err := decodedX86VectorFloatCompareInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{"$90", fmt.Sprintf("%s%d", prefix, firstSource), fmt.Sprintf("%s%d", prefix, secondSource), "K1", fmt.Sprintf("K%d", destinationMask)} + if got.Op != vectorFloatCompareRawOp(pp) || len(got.Args) != 5 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] || got.Args[3].String() != wantArgs[3] || got.Args[4].String() != wantArgs[4] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, vectorFloatCompareRawOp(pp), strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + if count != 98304 { + t.Fatalf("covered %d EVEX vector floating compare encodings, want 98304", count) + } +} + +func TestDecodedX86EVEXVectorFloatCompareModifiersMemoryAndInvalid(t *testing.T) { + tests := []struct { + name string + code []byte + op Op + args []string + }{ + {name: "weaviate memory", code: []byte{0x62, 0xf1, 0x3c, 0x48, 0xc2, 0x06, 0x0c}, op: "VCMPPS", args: []string{"$12", "0(SI)", "Z8", "K0"}}, + {name: "packed broadcast", code: []byte{0x62, 0xf1, 0xfd, 0x59, 0xc2, 0x48, 0x02, 0x7f}, op: "VCMPPD.BCST", args: []string{"$127", "16(AX)", "Z0", "K1", "K1"}}, + {name: "packed sae", code: encodeX86EVEXVectorFloatCompare(0, 2, true, 2, 7, 20, 21, 31), op: "VCMPPS.SAE", args: []string{"$31", "Z21", "Z20", "K2", "K7"}}, + {name: "scalar lig", code: encodeX86EVEXVectorFloatCompare(3, 1, false, 0, 4, 3, 21, 27), op: "VCMPSD", args: []string{"$27", "X21", "X3", "K4"}}, + {name: "scalar sae", code: encodeX86EVEXVectorFloatCompare(2, 3, true, 3, 5, 1, 11, 47), op: "VCMPSS.SAE", args: []string{"$47", "X11", "X1", "K3", "K5"}}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + got, length, ok, err := decodedX86VectorFloatCompareInstruction(test.code, 64) + if err != nil || !ok || length != len(test.code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", test.code, got, length, ok, err) + } + if got.Op != test.op || len(got.Args) != len(test.args) { + t.Fatalf("decode %x = %+v, want %s %s", test.code, got, test.op, strings.Join(test.args, ", ")) + } + for index := range test.args { + if got.Args[index].String() != test.args[index] { + t.Fatalf("decode %x = %+v, want %s %s", test.code, got, test.op, strings.Join(test.args, ", ")) + } + } + }) + } + + scalarBroadcast := encodeX86EVEXVectorFloatCompare(2, 0, true, 0, 0, 0, 0, 0) + scalarBroadcast[len(scalarBroadcast)-2] = 0 + invalid := [][]byte{ + encodeX86VEXVectorFloatCompare(2, true, 0, 0, 0, 0), + encodeX86EVEXVectorFloatCompare(0, 3, false, 0, 0, 0, 0, 0), + scalarBroadcast, + } + for _, code := range invalid { + if _, _, ok, err := decodedX86VectorFloatCompareInstruction(code, 64); !ok || err == nil { + t.Fatalf("invalid encoding %x returned ok=%v err=%v", code, ok, err) + } + } +} diff --git a/amd64_raw_vex_binary_float_test.go b/amd64_raw_vex_binary_float_test.go new file mode 100644 index 00000000..3bb0e777 --- /dev/null +++ b/amd64_raw_vex_binary_float_test.go @@ -0,0 +1,272 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +var x86VEXBinaryFloatTestOpcodes = map[byte]string{ + 0x58: "VADD", + 0x59: "VMUL", + 0x5c: "VSUB", + 0x5d: "VMIN", + 0x5e: "VDIV", + 0x5f: "VMAX", +} + +func encodeX86VEXBinaryFloat(opcode, pp byte, vex3, width256, widthIgnored bool, destination, source1, source2 int) []byte { + l := byte(0) + if width256 { + l = 1 + } + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + if !vex3 { + vex1 := byte((1-destination/8)<<7 | ((^source1)&15)<<3 | int(l)<<2 | int(pp)) + return []byte{0xc5, vex1, opcode, modRM} + } + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-source2/8)<<5 | 1) + vex1 := byte(((^source1)&15)<<3 | int(l)<<2 | int(pp)) + if widthIgnored { + vex1 |= 0x80 + } + return []byte{0xc4, vex0, vex1, opcode, modRM} +} + +func encodeX86EVEXBinaryFloat(opcode, pp, vectorBits byte, broadcastOrRounding, zeroing bool, mask, destination, source1, source2 int) []byte { + p0 := byte((1-(destination>>3)&1)<<7 | (1-(source2>>4)&1)<<6 | (1-(source2>>3)&1)<<5 | (1-(destination>>4)&1)<<4 | 1) + p1 := byte((^source1&15)<<3 | 1<<2 | int(pp)) + if pp == 1 || pp == 3 { + p1 |= 0x80 + } + p2 := byte(int(vectorBits)<<5 | (^source1>>4&1)<<3 | mask) + if broadcastOrRounding { + p2 |= 0x10 + } + if zeroing { + p2 |= 0x80 + } + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + return []byte{0x62, p0, p1, p2, opcode, modRM} +} + +func TestTranslateRawVEXBinaryFloatWeaviateRegression(t *testing.T) { + const source = `TEXT rawBinary(SB), $0-0 + LONG $0x0e5cf2c5 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawBinary": {Name: "rawBinary", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "fsub float") { + t.Fatalf("raw VSUBSS lowering omitted scalar subtraction:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-vex-binary-float.ll", "amd64-raw-vex-binary-float.o", ir) +} + +func TestTranslateRawEVEXBinaryFloatWeaviateRegression(t *testing.T) { + const source = `TEXT rawBinaryEVEX(SB), $0-0 + LONG $0x48347162 + WORD $0x0e5c + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawBinaryEVEX": {Name: "rawBinaryEVEX", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "fsub <16 x float>") { + t.Fatalf("raw EVEX VSUBPS lowering omitted packed subtraction:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-evex-binary-float.ll", "amd64-raw-evex-binary-float.o", ir) +} + +func TestDecodedX86VEXBinaryFloatCompleteRegisterFamily(t *testing.T) { + count := 0 + suffixes := map[byte]string{0: "PS", 1: "PD", 2: "SS", 3: "SD"} + for opcode, stem := range x86VEXBinaryFloatTestOpcodes { + for pp, suffix := range suffixes { + scalar := pp >= 2 + for _, vex3 := range []bool{false, true} { + widths := []bool{false, true} + if scalar { + widths = []bool{false} + } + for _, width256 := range widths { + prefix := "X" + if width256 { + prefix = "Y" + } + for _, widthIgnored := range []bool{false, true} { + if !vex3 && widthIgnored { + continue + } + source2Limit := 16 + if !vex3 { + source2Limit = 8 + } + for destination := 0; destination < 16; destination++ { + for source1 := 0; source1 < 16; source1++ { + for source2 := 0; source2 < source2Limit; source2++ { + code := encodeX86VEXBinaryFloat(opcode, pp, vex3, width256, widthIgnored, destination, source1, source2) + got, length, ok, err := decodedX86VEXBinaryFloatInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantOp := Op(stem + suffix) + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != wantOp || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + } + } + if count != 368640 { + t.Fatalf("covered %d VEX binary floating register encodings, want 368640", count) + } +} + +func TestDecodedX86EVEXBinaryFloatCompleteRegisterFamily(t *testing.T) { + count := 0 + suffixes := map[byte]string{0: "PS", 1: "PD", 2: "SS", 3: "SD"} + for opcode, stem := range x86VEXBinaryFloatTestOpcodes { + for pp, suffix := range suffixes { + vectorLengths := []byte{0, 1, 2} + for _, vectorBits := range vectorLengths { + prefix := [...]string{"X", "Y", "Z"}[vectorBits] + if pp >= 2 { + prefix = "X" + } + for destination := 0; destination < 32; destination++ { + for source1 := 0; source1 < 32; source1++ { + for source2 := 0; source2 < 32; source2++ { + code := encodeX86EVEXBinaryFloat(opcode, pp, vectorBits, false, false, 1, destination, source1, source2) + got, length, ok, err := decodedX86VEXBinaryFloatInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantOp := Op(stem + suffix) + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), "K1", fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != wantOp || len(got.Args) != 4 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] || got.Args[3].String() != wantArgs[3] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + if count != 2359296 { + t.Fatalf("covered %d EVEX binary floating register encodings, want 2359296", count) + } +} + +func TestDecodedX86EVEXBinaryFloatModifiersAndMemory(t *testing.T) { + tests := []struct { + name string + code []byte + op Op + args []string + }{ + {name: "packed zeroing", code: encodeX86EVEXBinaryFloat(0x58, 0, 1, false, true, 3, 29, 28, 21), op: "VADDPS.Z", args: []string{"Y21", "Y28", "K3", "Y29"}}, + {name: "packed broadcast zeroing", code: []byte{0x62, 0xf1, 0xed, 0xd9, 0x58, 0x08}, op: "VADDPD.BCST.Z", args: []string{"0(AX)", "Z2", "K1", "Z1"}}, + {name: "packed round nearest", code: []byte{0x62, 0xf1, 0xed, 0x19, 0x58, 0xcb}, op: "VADDPD.RN_SAE", args: []string{"Z3", "Z2", "K1", "Z1"}}, + {name: "packed round down", code: []byte{0x62, 0xf1, 0xed, 0x39, 0x58, 0xcb}, op: "VADDPD.RD_SAE", args: []string{"Z3", "Z2", "K1", "Z1"}}, + {name: "packed round up", code: []byte{0x62, 0xf1, 0xed, 0x59, 0x58, 0xcb}, op: "VADDPD.RU_SAE", args: []string{"Z3", "Z2", "K1", "Z1"}}, + {name: "packed round zero zeroing", code: []byte{0x62, 0xf1, 0xed, 0xf9, 0x58, 0xcb}, op: "VADDPD.RZ_SAE.Z", args: []string{"Z3", "Z2", "K1", "Z1"}}, + {name: "packed sae", code: []byte{0x62, 0xf1, 0xed, 0x59, 0x5f, 0xcb}, op: "VMAXPD.SAE", args: []string{"Z3", "Z2", "K1", "Z1"}}, + {name: "scalar round up", code: encodeX86EVEXBinaryFloat(0x5c, 2, 2, true, false, 2, 5, 6, 7), op: "VSUBSS.RU_SAE", args: []string{"X7", "X6", "K2", "X5"}}, + {name: "scalar sae zeroing", code: encodeX86EVEXBinaryFloat(0x5d, 3, 0, true, true, 4, 8, 9, 10), op: "VMINSD.SAE.Z", args: []string{"X10", "X9", "K4", "X8"}}, + {name: "compressed memory", code: []byte{0x62, 0x71, 0x34, 0x48, 0x5c, 0x4e, 0x02}, op: "VSUBPS", args: []string{"128(SI)", "Z9", "Z9"}}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + got, length, ok, err := decodedX86VEXBinaryFloatInstruction(test.code, 64) + if err != nil || !ok || length != len(test.code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", test.code, got, length, ok, err) + } + if got.Op != test.op || len(got.Args) != len(test.args) { + t.Fatalf("decode %x = %+v, want %s %s", test.code, got, test.op, strings.Join(test.args, ", ")) + } + for index := range test.args { + if got.Args[index].String() != test.args[index] { + t.Fatalf("decode %x = %+v, want %s %s", test.code, got, test.op, strings.Join(test.args, ", ")) + } + } + }) + } + + scalarBroadcast := encodeX86EVEXBinaryFloat(0x58, 2, 0, true, false, 0, 0, 0, 0) + scalarBroadcast[len(scalarBroadcast)-1] = 0 + wrongW := encodeX86EVEXBinaryFloat(0x58, 0, 0, false, false, 0, 0, 0, 0) + wrongW[2] ^= 0x80 + invalid := [][]byte{ + encodeX86EVEXBinaryFloat(0x58, 0, 0, false, true, 0, 0, 0, 0), + encodeX86EVEXBinaryFloat(0x58, 0, 3, false, false, 0, 0, 0, 0), + scalarBroadcast, + wrongW, + } + for _, code := range invalid { + if _, _, ok, err := decodedX86VEXBinaryFloatInstruction(code, 64); !ok || err == nil { + t.Fatalf("invalid EVEX encoding %x returned ok=%v err=%v", code, ok, err) + } + } + + mode32 := encodeX86EVEXBinaryFloat(0x58, 0, 0, false, false, 1, 0, 0, 0) + if _, _, ok, err := decodedX86VEXBinaryFloatInstruction(mode32, 32); !ok || err == nil { + t.Fatalf("masked EVEX form in 32-bit mode returned ok=%v err=%v", ok, err) + } +} + +func TestDecodedX86VEXBinaryFloatMemoryAndInvalidForms(t *testing.T) { + code := []byte{0x64, 0xc4, 0x01, 0xe5, 0x58, 0x64, 0x88, 0x20} + got, length, ok, err := decodedX86VEXBinaryFloatInstruction(code, 64) + wantSource := MemRef{Segment: FS, Base: "R8", Index: "R9", Scale: 4, Off: 32} + if err != nil || !ok || length != len(code) || got.Op != "VADDPD" || len(got.Args) != 3 || got.Args[0].Kind != OpMem || got.Args[0].Mem != wantSource || got.Args[1].String() != "Y3" || got.Args[2].String() != "Y12" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + + valid := encodeX86VEXBinaryFloat(0x58, 0, true, false, false, 0, 0, 0) + for _, invalid := range [][]byte{ + {0xc5}, + {0xc4, valid[1] ^ 1, valid[2], valid[3], valid[4]}, + encodeX86VEXBinaryFloat(0x5a, 0, true, false, false, 0, 0, 0), + } { + if instruction, _, matched, decodeErr := decodedX86VEXBinaryFloatInstruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("invalid encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + scalarY := encodeX86VEXBinaryFloat(0x58, 2, true, true, false, 0, 0, 0) + if _, _, matched, decodeErr := decodedX86VEXBinaryFloatInstruction(scalarY, 64); !matched || decodeErr == nil { + t.Fatalf("scalar VEX.256 encoding %x returned ok=%v err=%v", scalarY, matched, decodeErr) + } + extended := encodeX86VEXBinaryFloat(0x58, 0, true, false, false, 8, 8, 8) + if _, _, matched, decodeErr := decodedX86VEXBinaryFloatInstruction(extended, 32); !matched || decodeErr == nil { + t.Fatalf("32-bit extended-register form returned ok=%v err=%v", matched, decodeErr) + } +} diff --git a/amd64_raw_vex_fma3_test.go b/amd64_raw_vex_fma3_test.go new file mode 100644 index 00000000..2ba354dc --- /dev/null +++ b/amd64_raw_vex_fma3_test.go @@ -0,0 +1,245 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86VEXFMA3(opcode byte, width64, width256 bool, destination, source1, source2 int) []byte { + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-source2/8)<<5 | 2) + vex1 := byte(((^source1)&15)<<3 | 1) + if width64 { + vex1 |= 0x80 + } + if width256 { + vex1 |= 0x04 + } + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + return []byte{0xc4, vex0, vex1, opcode, modRM} +} + +func encodeX86EVEXFMA3(opcode byte, width64 bool, vectorBits byte, broadcastOrRounding, zeroing bool, mask, destination, source1, source2 int) []byte { + p0 := byte((1-(destination>>3)&1)<<7 | (1-(source2>>4)&1)<<6 | (1-(source2>>3)&1)<<5 | (1-(destination>>4)&1)<<4 | 2) + p1 := byte((^source1&15)<<3 | 1<<2 | 1) + if width64 { + p1 |= 0x80 + } + p2 := byte(int(vectorBits)<<5 | (^source1>>4&1)<<3 | mask) + if broadcastOrRounding { + p2 |= 0x10 + } + if zeroing { + p2 |= 0x80 + } + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + return []byte{0x62, p0, p1, p2, opcode, modRM} +} + +func TestTranslateRawVEXFMA3WeaviateRegression(t *testing.T) { + const source = `TEXT rawFMA(SB), $0-0 + LONG $0x985de2c4; BYTE $0x1e + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawFMA": {Name: "rawFMA", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "@llvm.fma.v8f32") { + t.Fatalf("raw VFMADD132PS lowering omitted vector FMA:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-vex-fma3.ll", "amd64-raw-vex-fma3.o", ir) +} + +func TestTranslateRawEVEXFMA3WeaviateRegression(t *testing.T) { + const source = `TEXT rawFMAEVEX(SB), $0-0 + LONG $0x4835d262; WORD $0xc9b8 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawFMAEVEX": {Name: "rawFMAEVEX", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "@llvm.fma.v16f32") { + t.Fatalf("raw EVEX VFMADD231PS lowering omitted vector FMA:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-evex-fma3.ll", "amd64-raw-evex-fma3.o", ir) +} + +func TestDecodedX86VEXFMA3CompleteRegisterFamily(t *testing.T) { + count := 0 + for opcode, spec := range decodedX86VEXFMA3Ops { + for _, width64 := range []bool{false, true} { + widths := []bool{false, true} + if spec.scalar { + widths = []bool{false} + } + for _, width256 := range widths { + prefix := "X" + if width256 { + prefix = "Y" + } + for destination := 0; destination < 16; destination++ { + for source1 := 0; source1 < 16; source1++ { + for source2 := 0; source2 < 16; source2++ { + code := encodeX86VEXFMA3(opcode, width64, width256, destination, source1, source2) + got, length, ok, err := decodedX86VEXFMA3Instruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantOp := spec.op(width64) + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != wantOp || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + if count != 393216 { + t.Fatalf("covered %d VEX FMA3 register encodings, want 393216", count) + } +} + +func TestDecodedX86EVEXFMA3CompleteRegisterFamily(t *testing.T) { + count := 0 + for opcode, spec := range decodedX86VEXFMA3Ops { + for _, width64 := range []bool{false, true} { + vectorLengths := []byte{0, 1, 2} + for _, vectorBits := range vectorLengths { + prefix := [...]string{"X", "Y", "Z"}[vectorBits] + if spec.scalar { + prefix = "X" + } + for destination := 0; destination < 32; destination++ { + for source1 := 0; source1 < 32; source1++ { + for source2 := 0; source2 < 32; source2++ { + code := encodeX86EVEXFMA3(opcode, width64, vectorBits, false, false, 1, destination, source1, source2) + got, length, ok, err := decodedX86VEXFMA3Instruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantOp := spec.op(width64) + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), "K1", fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != wantOp || len(got.Args) != 4 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] || got.Args[3].String() != wantArgs[3] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + if count != 5898240 { + t.Fatalf("covered %d EVEX FMA3 register encodings, want 5898240", count) + } +} + +func TestDecodedX86EVEXFMA3ModifiersAndMemory(t *testing.T) { + tests := []struct { + name string + code []byte + op Op + args []string + }{ + {name: "packed zeroing", code: encodeX86EVEXFMA3(0xb8, false, 1, false, true, 3, 29, 28, 21), op: "VFMADD231PS.Z", args: []string{"Y21", "Y28", "K3", "Y29"}}, + {name: "packed broadcast zeroing", code: []byte{0x62, 0xf2, 0xed, 0xd9, 0x98, 0x08}, op: "VFMADD132PD.BCST.Z", args: []string{"0(AX)", "Z2", "K1", "Z1"}}, + {name: "packed round nearest", code: encodeX86EVEXFMA3(0xa8, true, 0, true, false, 1, 1, 2, 3), op: "VFMADD213PD.RN_SAE", args: []string{"Z3", "Z2", "K1", "Z1"}}, + {name: "packed round down", code: encodeX86EVEXFMA3(0xba, false, 1, true, false, 2, 4, 5, 6), op: "VFMSUB231PS.RD_SAE", args: []string{"Z6", "Z5", "K2", "Z4"}}, + {name: "packed round up", code: encodeX86EVEXFMA3(0x9c, true, 2, true, false, 3, 7, 8, 9), op: "VFNMADD132PD.RU_SAE", args: []string{"Z9", "Z8", "K3", "Z7"}}, + {name: "packed round zero zeroing", code: encodeX86EVEXFMA3(0xae, false, 3, true, true, 4, 10, 11, 12), op: "VFNMSUB213PS.RZ_SAE.Z", args: []string{"Z12", "Z11", "K4", "Z10"}}, + {name: "scalar round up", code: encodeX86EVEXFMA3(0xb9, false, 2, true, false, 5, 13, 14, 15), op: "VFMADD231SS.RU_SAE", args: []string{"X15", "X14", "K5", "X13"}}, + {name: "compressed memory", code: []byte{0x62, 0xd2, 0x35, 0x48, 0xb8, 0x49, 0x02}, op: "VFMADD231PS", args: []string{"128(R9)", "Z9", "Z1"}}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + got, length, ok, err := decodedX86VEXFMA3Instruction(test.code, 64) + if err != nil || !ok || length != len(test.code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", test.code, got, length, ok, err) + } + if got.Op != test.op || len(got.Args) != len(test.args) { + t.Fatalf("decode %x = %+v, want %s %s", test.code, got, test.op, strings.Join(test.args, ", ")) + } + for index := range test.args { + if got.Args[index].String() != test.args[index] { + t.Fatalf("decode %x = %+v, want %s %s", test.code, got, test.op, strings.Join(test.args, ", ")) + } + } + }) + } + + scalarBroadcast := encodeX86EVEXFMA3(0x99, false, 0, true, false, 0, 0, 0, 0) + scalarBroadcast[len(scalarBroadcast)-1] = 0 + wrongPP := encodeX86EVEXFMA3(0x98, false, 0, false, false, 0, 0, 0, 0) + wrongPP[2] &^= 1 + invalid := [][]byte{ + encodeX86EVEXFMA3(0x98, false, 0, false, true, 0, 0, 0, 0), + encodeX86EVEXFMA3(0x98, false, 3, false, false, 0, 0, 0, 0), + scalarBroadcast, + wrongPP, + } + for _, code := range invalid { + if _, _, ok, err := decodedX86VEXFMA3Instruction(code, 64); !ok || err == nil { + t.Fatalf("invalid EVEX encoding %x returned ok=%v err=%v", code, ok, err) + } + } + + mode32 := encodeX86EVEXFMA3(0x98, false, 0, false, false, 1, 0, 0, 0) + if _, _, ok, err := decodedX86VEXFMA3Instruction(mode32, 32); !ok || err == nil { + t.Fatalf("masked EVEX form in 32-bit mode returned ok=%v err=%v", ok, err) + } +} + +func TestDecodedX86VEXFMA3MemoryAndInvalidForms(t *testing.T) { + code := []byte{0x64, 0xc4, 0x02, 0xe5, 0x98, 0x64, 0x88, 0x20} + got, length, ok, err := decodedX86VEXFMA3Instruction(code, 64) + wantSource := MemRef{Segment: FS, Base: "R8", Index: "R9", Scale: 4, Off: 32} + if err != nil || !ok || length != len(code) || got.Op != "VFMADD132PD" || len(got.Args) != 3 || got.Args[0].Kind != OpMem || got.Args[0].Mem != wantSource || got.Args[1].String() != "Y3" || got.Args[2].String() != "Y12" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + + valid := encodeX86VEXFMA3(0x98, false, false, 0, 0, 0) + for _, invalid := range [][]byte{ + {0xc4}, + {valid[0], valid[1] ^ 3, valid[2], valid[3], valid[4]}, + encodeX86VEXFMA3(0x95, false, false, 0, 0, 0), + } { + if instruction, _, matched, decodeErr := decodedX86VEXFMA3Instruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("invalid encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + invalidPP := []byte{valid[0], valid[1], valid[2] &^ 1, valid[3], valid[4]} + if _, _, matched, decodeErr := decodedX86VEXFMA3Instruction(invalidPP, 64); !matched || decodeErr == nil { + t.Fatalf("invalid pp encoding %x returned ok=%v err=%v", invalidPP, matched, decodeErr) + } + scalarY := encodeX86VEXFMA3(0x99, false, true, 0, 0, 0) + if _, _, matched, decodeErr := decodedX86VEXFMA3Instruction(scalarY, 64); !matched || decodeErr == nil { + t.Fatalf("scalar VEX.256 encoding %x returned ok=%v err=%v", scalarY, matched, decodeErr) + } + extended := encodeX86VEXFMA3(0x98, false, false, 8, 8, 8) + if _, _, matched, decodeErr := decodedX86VEXFMA3Instruction(extended, 32); !matched || decodeErr == nil { + t.Fatalf("32-bit extended-register form returned ok=%v err=%v", matched, decodeErr) + } +} diff --git a/amd64_raw_vex_horizontal_float_test.go b/amd64_raw_vex_horizontal_float_test.go new file mode 100644 index 00000000..666679ca --- /dev/null +++ b/amd64_raw_vex_horizontal_float_test.go @@ -0,0 +1,123 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86VEXHorizontalFloat(opcode, pp byte, vex3, width256, widthIgnored bool, destination, source1, source2 int) []byte { + l := byte(0) + if width256 { + l = 1 + } + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + if !vex3 { + vex1 := byte((1-destination/8)<<7 | ((^source1)&15)<<3 | int(l)<<2 | int(pp)) + return []byte{0xc5, vex1, opcode, modRM} + } + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-source2/8)<<5 | 1) + vex1 := byte(((^source1)&15)<<3 | int(l)<<2 | int(pp)) + if widthIgnored { + vex1 |= 0x80 + } + return []byte{0xc4, vex0, vex1, opcode, modRM} +} + +func TestTranslateRawVEXHorizontalFloatWeaviateRegression(t *testing.T) { + const source = `TEXT rawHorizontal(SB), $0-0 + LONG $0xc07cffc5 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawHorizontal": {Name: "rawHorizontal", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "fadd float") { + t.Fatalf("raw VHADDPS lowering omitted horizontal addition:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-vex-horizontal-float.ll", "amd64-raw-vex-horizontal-float.o", ir) +} + +func TestDecodedX86VEXHorizontalFloatCompleteRegisterFamily(t *testing.T) { + count := 0 + for opcode, stem := range map[byte]string{0x7c: "VHADD", 0x7d: "VHSUB"} { + for pp, suffix := range map[byte]string{1: "PD", 3: "PS"} { + for _, vex3 := range []bool{false, true} { + for _, width256 := range []bool{false, true} { + prefix := "X" + if width256 { + prefix = "Y" + } + for _, widthIgnored := range []bool{false, true} { + if !vex3 && widthIgnored { + continue + } + source2Limit := 16 + if !vex3 { + source2Limit = 8 + } + for destination := 0; destination < 16; destination++ { + for source1 := 0; source1 < 16; source1++ { + for source2 := 0; source2 < source2Limit; source2++ { + code := encodeX86VEXHorizontalFloat(opcode, pp, vex3, width256, widthIgnored, destination, source1, source2) + got, length, ok, err := decodedX86VEXHorizontalFloatInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantOp := Op(stem + suffix) + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != wantOp || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + } + } + if count != 81920 { + t.Fatalf("covered %d VEX horizontal floating register encodings, want 81920", count) + } +} + +func TestDecodedX86VEXHorizontalFloatMemoryAndInvalidForms(t *testing.T) { + code := []byte{0x64, 0xc4, 0x01, 0xe5, 0x7d, 0x64, 0x88, 0x20} + got, length, ok, err := decodedX86VEXHorizontalFloatInstruction(code, 64) + wantSource := MemRef{Segment: FS, Base: "R8", Index: "R9", Scale: 4, Off: 32} + if err != nil || !ok || length != len(code) || got.Op != "VHSUBPD" || len(got.Args) != 3 || got.Args[0].Kind != OpMem || got.Args[0].Mem != wantSource || got.Args[1].String() != "Y3" || got.Args[2].String() != "Y12" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + + valid := encodeX86VEXHorizontalFloat(0x7c, 1, true, false, false, 0, 0, 0) + for _, invalid := range [][]byte{ + {0xc5}, + {0xc4, valid[1] ^ 1, valid[2], valid[3], valid[4]}, + encodeX86VEXHorizontalFloat(0x7e, 1, true, false, false, 0, 0, 0), + } { + if instruction, _, matched, decodeErr := decodedX86VEXHorizontalFloatInstruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("invalid encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + invalidPP := encodeX86VEXHorizontalFloat(0x7c, 0, true, false, false, 0, 0, 0) + if _, _, matched, decodeErr := decodedX86VEXHorizontalFloatInstruction(invalidPP, 64); !matched || decodeErr == nil { + t.Fatalf("invalid pp encoding %x returned ok=%v err=%v", invalidPP, matched, decodeErr) + } + extended := encodeX86VEXHorizontalFloat(0x7c, 1, true, false, false, 8, 8, 8) + if _, _, matched, decodeErr := decodedX86VEXHorizontalFloatInstruction(extended, 32); !matched || decodeErr == nil { + t.Fatalf("32-bit extended-register form returned ok=%v err=%v", matched, decodeErr) + } +} diff --git a/amd64_raw_vex_integration_test.go b/amd64_raw_vex_integration_test.go new file mode 100644 index 00000000..d85d68f5 --- /dev/null +++ b/amd64_raw_vex_integration_test.go @@ -0,0 +1,49 @@ +//go:build !llgo + +package plan9asm + +import "testing" + +func TestTranslateX86RawVEXVNNIAndVariableDwordPermuteAllTargets(t *testing.T) { + const source = `TEXT rawvexfamilies(SB),$0-0 + // {vex} VPDPBUSD X2, X1, X0. + BYTE $0xc4; BYTE $0xe2; BYTE $0x71; BYTE $0x50; BYTE $0xc2 + // {vex} VPERMD Y5, Y3, Y4. + BYTE $0xc4; BYTE $0xe2; BYTE $0x65; BYTE $0x36; BYTE $0xe5 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + goarch string + triple string + }{ + {name: "darwin-amd64", goarch: "amd64", triple: "x86_64-apple-darwin"}, + {name: "linux-amd64", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, + {name: "windows-amd64", goarch: "amd64", triple: "x86_64-pc-windows-msvc"}, + {name: "linux-386", goarch: "386", triple: "i386-unknown-linux-gnu"}, + {name: "windows-386", goarch: "386", triple: "i686-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + requireX86GoAssemblerResult(t, target.goarch, source, true) + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: target.goarch, + Sigs: map[string]FuncSig{ + "rawvexfamilies": {Name: "rawvexfamilies", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "raw-vex-families-"+target.name+".ll", "raw-vex-families-"+target.name+".o", ll) + }) + } +} diff --git a/amd64_raw_vex_packed_float_logical_test.go b/amd64_raw_vex_packed_float_logical_test.go new file mode 100644 index 00000000..96bac889 --- /dev/null +++ b/amd64_raw_vex_packed_float_logical_test.go @@ -0,0 +1,156 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +var x86VEXPackedFloatLogicalTestOpcodes = map[byte]string{ + 0x54: "VAND", + 0x55: "VANDN", + 0x56: "VOR", + 0x57: "VXOR", +} + +func encodeX86VEXPackedFloatLogical(opcode, pp byte, vex3, width256, widthIgnored bool, destination, source1, source2 int) []byte { + l := byte(0) + if width256 { + l = 1 + } + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + if !vex3 { + vex1 := byte((1-destination/8)<<7 | ((^source1)&15)<<3 | int(l)<<2 | int(pp)) + return []byte{0xc5, vex1, opcode, modRM} + } + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-source2/8)<<5 | 1) + vex1 := byte(((^source1)&15)<<3 | int(l)<<2 | int(pp)) + if widthIgnored { + vex1 |= 0x80 + } + return []byte{0xc4, vex0, vex1, opcode, modRM} +} + +func TestTranslateRawVEXPackedFloatLogicalWeaviateRegression(t *testing.T) { + const source = `TEXT rawLogical(SB), $0-0 + WORD $0x8944; BYTE $0xc8 + WORD $0xe083; BYTE $0x03 + LONG $0xc057f8c5 + WORD $0xc931 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawLogical": {Name: "rawLogical", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "xor <4 x i32>") { + t.Fatalf("raw VXORPS lowering omitted vector xor:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-vex-logical.ll", "amd64-raw-vex-logical.o", ir) +} + +func TestDecodedX86VEXPackedFloatLogicalCompleteRegisterFamily(t *testing.T) { + count := 0 + for opcode, stem := range x86VEXPackedFloatLogicalTestOpcodes { + for pp, suffix := range map[byte]string{0: "PS", 1: "PD"} { + for _, vex3 := range []bool{false, true} { + for _, width256 := range []bool{false, true} { + prefix := "X" + if width256 { + prefix = "Y" + } + for _, widthIgnored := range []bool{false, true} { + if !vex3 && widthIgnored { + continue + } + source2Limit := 16 + if !vex3 { + source2Limit = 8 + } + for destination := 0; destination < 16; destination++ { + for source1 := 0; source1 < 16; source1++ { + for source2 := 0; source2 < source2Limit; source2++ { + code := encodeX86VEXPackedFloatLogical(opcode, pp, vex3, width256, widthIgnored, destination, source1, source2) + got, length, ok, err := decodedX86VEXPackedFloatLogicalInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantOp := Op(stem + suffix) + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != wantOp || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + } + } + if count != 163840 { + t.Fatalf("covered %d VEX packed floating logical register encodings, want 163840", count) + } +} + +func TestDecodedX86VEXPackedFloatLogicalMemoryForms(t *testing.T) { + tests := []struct { + name string + code []byte + op Op + source MemRef + second Reg + dest Reg + }{ + {name: "base", code: []byte{0xc4, 0xe1, 0x78, 0x57, 0x00}, op: "VXORPS", source: MemRef{Base: AX}, second: "X0", dest: "X0"}, + {name: "extended SIB displacement and FS", code: []byte{0x64, 0xc4, 0x01, 0x65, 0x54, 0x64, 0x88, 0x20}, op: "VANDPD", source: MemRef{Segment: FS, Base: "R8", Index: "R9", Scale: 4, Off: 32}, second: "Y3", dest: "Y12"}, + {name: "base displacement and GS", code: []byte{0x65, 0xc5, 0xec, 0x56, 0x4d, 0x7f}, op: "VORPS", source: MemRef{Segment: GS, Base: BP, Off: 0x7f}, second: "Y2", dest: "Y1"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + got, length, ok, err := decodedX86VEXPackedFloatLogicalInstruction(test.code, 64) + if err != nil || !ok || length != len(test.code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", test.code, got, length, ok, err) + } + if got.Op != test.op || len(got.Args) != 3 || got.Args[0].Kind != OpMem || got.Args[0].Mem != test.source || got.Args[1].Kind != OpReg || got.Args[1].Reg != test.second || got.Args[2].Kind != OpReg || got.Args[2].Reg != test.dest { + t.Fatalf("decode %x = %+v, want %s %+v, %s, %s", test.code, got, test.op, test.source, test.second, test.dest) + } + }) + } +} + +func TestDecodedX86VEXPackedFloatLogicalRejectsReservedForms(t *testing.T) { + valid := encodeX86VEXPackedFloatLogical(0x57, 0, true, false, false, 0, 0, 0) + for _, code := range [][]byte{ + {0xc5}, + {0xc4, valid[1] ^ 1, valid[2], valid[3], valid[4]}, + encodeX86VEXPackedFloatLogical(0x58, 0, true, false, false, 0, 0, 0), + } { + if got, _, ok, err := decodedX86VEXPackedFloatLogicalInstruction(code, 64); ok || err != nil { + t.Fatalf("reserved encoding %x decoded as %+v, ok=%v, err=%v", code, got, ok, err) + } + } + reservedPP := encodeX86VEXPackedFloatLogical(0x57, 2, true, false, false, 0, 0, 0) + if _, _, ok, err := decodedX86VEXPackedFloatLogicalInstruction(reservedPP, 64); !ok || err == nil { + t.Fatalf("reserved pp encoding %x returned ok=%v err=%v", reservedPP, ok, err) + } + ripRelative := []byte{0xc5, 0xec, 0x56, 0x0d, 0x78, 0x56, 0x34, 0x12} + if _, _, ok, err := decodedX86VEXPackedFloatLogicalInstruction(ripRelative, 64); !ok || err == nil { + t.Fatalf("source-layout-unsafe RIP-relative encoding %x returned ok=%v err=%v", ripRelative, ok, err) + } + extended := encodeX86VEXPackedFloatLogical(0x57, 0, true, false, false, 8, 8, 8) + if _, _, ok, err := decodedX86VEXPackedFloatLogicalInstruction(extended, 32); !ok || err == nil { + t.Fatalf("32-bit extended-register form returned ok=%v err=%v", ok, err) + } +} diff --git a/amd64_raw_vex_packed_integer_logical_test.go b/amd64_raw_vex_packed_integer_logical_test.go new file mode 100644 index 00000000..fc844faa --- /dev/null +++ b/amd64_raw_vex_packed_integer_logical_test.go @@ -0,0 +1,127 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +var x86VEXPackedIntegerLogicalTestOpcodes = map[byte]Op{ + 0xdb: "VPAND", + 0xdf: "VPANDN", + 0xeb: "VPOR", + 0xef: "VPXOR", +} + +func encodeX86VEXPackedIntegerLogical(opcode byte, vex3, width256, widthIgnored bool, destination, source1, source2 int) []byte { + l := byte(0) + if width256 { + l = 1 + } + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + if !vex3 { + vex1 := byte((1-destination/8)<<7 | ((^source1)&15)<<3 | int(l)<<2 | 1) + return []byte{0xc5, vex1, opcode, modRM} + } + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-source2/8)<<5 | 1) + vex1 := byte(((^source1)&15)<<3 | int(l)<<2 | 1) + if widthIgnored { + vex1 |= 0x80 + } + return []byte{0xc4, vex0, vex1, opcode, modRM} +} + +func TestTranslateRawVEXPackedIntegerLogicalWeaviateRegression(t *testing.T) { + const source = `TEXT rawLogical(SB), $0-0 + LONG $0xc0eff9c5 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawLogical": {Name: "rawLogical", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "xor <16 x i8>") { + t.Fatalf("raw VPXOR lowering omitted vector xor:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-vex-integer-logical.ll", "amd64-raw-vex-integer-logical.o", ir) +} + +func TestDecodedX86VEXPackedIntegerLogicalCompleteRegisterFamily(t *testing.T) { + count := 0 + for opcode, wantOp := range x86VEXPackedIntegerLogicalTestOpcodes { + for _, vex3 := range []bool{false, true} { + for _, width256 := range []bool{false, true} { + prefix := "X" + if width256 { + prefix = "Y" + } + for _, widthIgnored := range []bool{false, true} { + if !vex3 && widthIgnored { + continue + } + source2Limit := 16 + if !vex3 { + source2Limit = 8 + } + for destination := 0; destination < 16; destination++ { + for source1 := 0; source1 < 16; source1++ { + for source2 := 0; source2 < source2Limit; source2++ { + code := encodeX86VEXPackedIntegerLogical(opcode, vex3, width256, widthIgnored, destination, source1, source2) + got, length, ok, err := decodedX86VEXPackedIntegerLogicalInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != wantOp || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + } + if count != 81920 { + t.Fatalf("covered %d VEX packed integer logical register encodings, want 81920", count) + } +} + +func TestDecodedX86VEXPackedIntegerLogicalMemoryAndInvalidForms(t *testing.T) { + code := []byte{0x64, 0xc4, 0x01, 0xe5, 0xdb, 0x64, 0x88, 0x20} + got, length, ok, err := decodedX86VEXPackedIntegerLogicalInstruction(code, 64) + wantSource := MemRef{Segment: FS, Base: "R8", Index: "R9", Scale: 4, Off: 32} + if err != nil || !ok || length != len(code) || got.Op != "VPAND" || len(got.Args) != 3 || got.Args[0].Kind != OpMem || got.Args[0].Mem != wantSource || got.Args[1].String() != "Y3" || got.Args[2].String() != "Y12" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + + valid := encodeX86VEXPackedIntegerLogical(0xef, true, false, false, 0, 0, 0) + for _, invalid := range [][]byte{ + {0xc5}, + {0xc4, valid[1] ^ 1, valid[2], valid[3], valid[4]}, + encodeX86VEXPackedIntegerLogical(0xee, true, false, false, 0, 0, 0), + } { + if instruction, _, matched, decodeErr := decodedX86VEXPackedIntegerLogicalInstruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("invalid encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + invalidPP := []byte{valid[0], valid[1], valid[2] &^ 1, valid[3], valid[4]} + if _, _, matched, decodeErr := decodedX86VEXPackedIntegerLogicalInstruction(invalidPP, 64); !matched || decodeErr == nil { + t.Fatalf("invalid pp encoding %x returned ok=%v err=%v", invalidPP, matched, decodeErr) + } + extended := encodeX86VEXPackedIntegerLogical(0xef, true, false, false, 8, 8, 8) + if _, _, matched, decodeErr := decodedX86VEXPackedIntegerLogicalInstruction(extended, 32); !matched || decodeErr == nil { + t.Fatalf("32-bit extended-register form returned ok=%v err=%v", matched, decodeErr) + } +} diff --git a/amd64_raw_vex_packed_madd_test.go b/amd64_raw_vex_packed_madd_test.go new file mode 100644 index 00000000..0ee1f9c4 --- /dev/null +++ b/amd64_raw_vex_packed_madd_test.go @@ -0,0 +1,132 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86VEXPackedMADD(opcode byte, opcodeMap int, vex3, width256, widthIgnored bool, destination, source1, source2 int) []byte { + l := byte(0) + if width256 { + l = 1 + } + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + if !vex3 { + vex1 := byte((1-destination/8)<<7 | ((^source1)&15)<<3 | int(l)<<2 | 1) + return []byte{0xc5, vex1, opcode, modRM} + } + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-source2/8)<<5 | opcodeMap) + vex1 := byte(((^source1)&15)<<3 | int(l)<<2 | 1) + if widthIgnored { + vex1 |= 0x80 + } + return []byte{0xc4, vex0, vex1, opcode, modRM} +} + +func TestTranslateRawVEXPackedMADDWeaviateRegression(t *testing.T) { + const source = `TEXT rawMADD(SB), $0-0 + LONG $0xd4f5edc5 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawMADD": {Name: "rawMADD", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "mul <16 x i32>") { + t.Fatalf("raw VPMADDWD lowering omitted packed multiplication:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-vex-packed-madd.ll", "amd64-raw-vex-packed-madd.o", ir) +} + +func TestDecodedX86VEXPackedMADDCompleteRegisterFamily(t *testing.T) { + tests := []struct { + opcode byte + opcodeMap int + op Op + vex2 bool + }{ + {opcode: 0xf5, opcodeMap: 1, op: "VPMADDWD", vex2: true}, + {opcode: 0x04, opcodeMap: 2, op: "VPMADDUBSW"}, + } + count := 0 + for _, test := range tests { + for _, vex3 := range []bool{false, true} { + if !vex3 && !test.vex2 { + continue + } + for _, width256 := range []bool{false, true} { + prefix := "X" + if width256 { + prefix = "Y" + } + for _, widthIgnored := range []bool{false, true} { + if !vex3 && widthIgnored { + continue + } + source2Limit := 16 + if !vex3 { + source2Limit = 8 + } + for destination := 0; destination < 16; destination++ { + for source1 := 0; source1 < 16; source1++ { + for source2 := 0; source2 < source2Limit; source2++ { + code := encodeX86VEXPackedMADD(test.opcode, test.opcodeMap, vex3, width256, widthIgnored, destination, source1, source2) + got, length, ok, err := decodedX86VEXPackedMADDInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != test.op || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, test.op, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + } + if count != 36864 { + t.Fatalf("covered %d VEX packed multiply-add register encodings, want 36864", count) + } +} + +func TestDecodedX86VEXPackedMADDMemoryAndInvalidForms(t *testing.T) { + code := []byte{0x64, 0xc4, 0x02, 0xe5, 0x04, 0x64, 0x88, 0x20} + got, length, ok, err := decodedX86VEXPackedMADDInstruction(code, 64) + wantSource := MemRef{Segment: FS, Base: "R8", Index: "R9", Scale: 4, Off: 32} + if err != nil || !ok || length != len(code) || got.Op != "VPMADDUBSW" || len(got.Args) != 3 || got.Args[0].Kind != OpMem || got.Args[0].Mem != wantSource || got.Args[1].String() != "Y3" || got.Args[2].String() != "Y12" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + + valid := encodeX86VEXPackedMADD(0xf5, 1, true, false, false, 0, 0, 0) + for _, invalid := range [][]byte{ + {0xc5}, + encodeX86VEXPackedMADD(0xf4, 1, true, false, false, 0, 0, 0), + encodeX86VEXPackedMADD(0x04, 1, true, false, false, 0, 0, 0), + } { + if instruction, _, matched, decodeErr := decodedX86VEXPackedMADDInstruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("invalid encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + invalidPP := []byte{valid[0], valid[1], valid[2] &^ 1, valid[3], valid[4]} + if _, _, matched, decodeErr := decodedX86VEXPackedMADDInstruction(invalidPP, 64); !matched || decodeErr == nil { + t.Fatalf("invalid pp encoding %x returned ok=%v err=%v", invalidPP, matched, decodeErr) + } + extended := encodeX86VEXPackedMADD(0xf5, 1, true, false, false, 8, 8, 8) + if _, _, matched, decodeErr := decodedX86VEXPackedMADDInstruction(extended, 32); !matched || decodeErr == nil { + t.Fatalf("32-bit extended-register form returned ok=%v err=%v", matched, decodeErr) + } +} diff --git a/amd64_raw_vex_packed_shuffle_test.go b/amd64_raw_vex_packed_shuffle_test.go new file mode 100644 index 00000000..4506200f --- /dev/null +++ b/amd64_raw_vex_packed_shuffle_test.go @@ -0,0 +1,160 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86VEXPackedShuffle(pp byte, vex3, width256, widthIgnored bool, destination, source int, immediate byte) []byte { + l := byte(0) + if width256 { + l = 1 + } + modRM := byte(0xc0 | (destination&7)<<3 | source&7) + if !vex3 { + vex1 := byte((1-destination/8)<<7 | 15<<3 | int(l)<<2 | int(pp)) + return []byte{0xc5, vex1, 0x70, modRM, immediate} + } + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-source/8)<<5 | 1) + vex1 := byte(15<<3 | int(l)<<2 | int(pp)) + if widthIgnored { + vex1 |= 0x80 + } + return []byte{0xc4, vex0, vex1, 0x70, modRM, immediate} +} + +func TestTranslateRawVEXPackedShuffleWeaviateRegression(t *testing.T) { + const source = `TEXT rawShuffle(SB), $0-0 + LONG $0xc870f9c5 + BYTE $0x1b + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawShuffle": {Name: "rawShuffle", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "shufflevector <4 x i32>") { + t.Fatalf("raw VPSHUFD lowering omitted packed shuffle:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-vex-packed-shuffle.ll", "amd64-raw-vex-packed-shuffle.o", ir) +} + +func TestDecodedX86PackedShuffleCompleteVEXRegisterFamily(t *testing.T) { + tests := []struct { + pp byte + op Op + }{ + {pp: 1, op: "VPSHUFD"}, + {pp: 2, op: "VPSHUFHW"}, + {pp: 3, op: "VPSHUFLW"}, + } + count := 0 + for _, test := range tests { + for _, vex3 := range []bool{false, true} { + for _, width256 := range []bool{false, true} { + prefix := "X" + if width256 { + prefix = "Y" + } + for _, widthIgnored := range []bool{false, true} { + if !vex3 && widthIgnored { + continue + } + sourceLimit := 16 + if !vex3 { + sourceLimit = 8 + } + for destination := 0; destination < 16; destination++ { + for source := 0; source < sourceLimit; source++ { + immediate := byte(destination<<4 | source) + code := encodeX86VEXPackedShuffle(test.pp, vex3, width256, widthIgnored, destination, source, immediate) + got, length, ok, err := decodedX86PackedShuffleInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("$%d", immediate), fmt.Sprintf("%s%d", prefix, source), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != test.op || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, test.op, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + if count != 3840 { + t.Fatalf("covered %d VEX packed shuffle register encodings, want 3840", count) + } +} + +func TestDecodedX86PackedShuffleCompleteGo127Family(t *testing.T) { + // Go 1.27 assigns these three instructions the shared _yvpshufd table. + // The cases cover VEX/EVEX X/Y/Z, WIG, high registers, memory, masks, + // zeroing, the VPSHUFD-only broadcast, and compressed disp8. + tests := []struct { + name string + code []byte + want string + }{ + {name: "vex d reported weaviate", code: []byte{0xc5, 0xf9, 0x70, 0xc8, 0x1b}, want: "VPSHUFD $27, X0, X1"}, + {name: "vex hw y WIG memory", code: []byte{0x64, 0xc4, 0x01, 0xfe, 0x70, 0x64, 0x88, 0x20, 0x5a}, want: "VPSHUFHW $90, 32(R8)(R9*4)(FS), Y12"}, + {name: "evex d x high masked", code: []byte{0x62, 0x71, 0x7d, 0x0c, 0x70, 0xca, 0x7e}, want: "VPSHUFD $126, X2, K4, X9"}, + {name: "evex hw x high masked WIG", code: []byte{0x62, 0x41, 0xfe, 0x0a, 0x70, 0xfb, 0x0d}, want: "VPSHUFHW $13, X11, K2, X31"}, + {name: "evex lw y high masked", code: []byte{0x62, 0xe1, 0x7f, 0x2a, 0x70, 0xdf, 0x00}, want: "VPSHUFLW $0, Y7, K2, Y19"}, + {name: "evex d z broadcast zeroing", code: []byte{0x62, 0xf1, 0x7d, 0xdb, 0x70, 0x50, 0x7f, 0x09}, want: "VPSHUFD.BCST.Z $9, 508(AX), K3, Z2"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86PackedShuffleInstruction(test.code, 64) + if !ok { + t.Fatal("packed shuffle encoding was not recognized") + } + if err != nil { + t.Fatal(err) + } + if length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as length=%d raw=%q, want length=%d raw=%q", test.code, length, instruction.Raw, len(test.code), test.want) + } + }) + } +} + +func TestDecodedX86PackedShuffleRejectsInvalidForms(t *testing.T) { + valid := encodeX86VEXPackedShuffle(1, true, false, false, 0, 0, 1) + invalidVVVV := append([]byte(nil), valid...) + invalidVVVV[2] &^= 0x08 + for name, code := range map[string][]byte{ + "truncated": {0xc5}, + "wrong opcode": {0xc5, 0xf9, 0x71, 0xc0, 1}, + "wrong map": {0xc4, 0xe2, 0x79, 0x70, 0xc0, 1}, + "unrelated pp": {0xc5, 0xf8, 0x70, 0xc0, 1}, + "EVEX D with W1": {0x62, 0xf1, 0xfd, 0x08, 0x70, 0xc0, 1}, + } { + if instruction, _, matched, decodeErr := decodedX86PackedShuffleInstruction(code, 64); matched || decodeErr != nil { + t.Fatalf("%s encoding %x decoded as %+v, ok=%v, err=%v", name, code, instruction, matched, decodeErr) + } + } + if _, _, matched, decodeErr := decodedX86PackedShuffleInstruction(invalidVVVV, 64); !matched || decodeErr == nil { + t.Fatalf("non-reserved VEX.vvvv encoding %x returned ok=%v err=%v", invalidVVVV, matched, decodeErr) + } + extended := encodeX86VEXPackedShuffle(1, true, false, false, 8, 8, 1) + if _, _, matched, decodeErr := decodedX86PackedShuffleInstruction(extended, 32); !matched || decodeErr == nil { + t.Fatalf("32-bit extended-register form returned ok=%v err=%v", matched, decodeErr) + } + invalidBroadcast := []byte{0x62, 0xf1, 0x7e, 0x5b, 0x70, 0x50, 0x7f, 1} + if _, _, matched, decodeErr := decodedX86PackedShuffleInstruction(invalidBroadcast, 64); !matched || decodeErr == nil { + t.Fatalf("VPSHUFHW broadcast returned ok=%v err=%v", matched, decodeErr) + } +} diff --git a/amd64_raw_vextract128_test.go b/amd64_raw_vextract128_test.go new file mode 100644 index 00000000..67b03bf0 --- /dev/null +++ b/amd64_raw_vextract128_test.go @@ -0,0 +1,250 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86VEXTRACT128(opcode, immediate byte, source, destination int) []byte { + vex0 := byte((1-source/8)<<7 | 1<<6 | (1-destination/8)<<5 | 3) + modRM := byte(0xc0 | (source&7)<<3 | destination&7) + return []byte{0xc4, vex0, 0x7d, opcode, modRM, immediate} +} + +func encodeX86EVEXTRACT(opcode, immediate byte, width64 bool, vectorBits byte, mask int, zeroing bool, source, destination int) []byte { + p0 := byte((1-source/8&1)<<7 | (1-destination/16)<<6 | (1-destination/8&1)<<5 | (1-source/16)<<4 | 3) + p1 := byte(0x7d) + if width64 { + p1 |= 0x80 + } + p2 := byte(vectorBits<<5 | 1<<3 | byte(mask)) + if zeroing { + p2 |= 0x80 + } + modRM := byte(0xc0 | (source&7)<<3 | destination&7) + return []byte{0x62, p0, p1, p2, opcode, modRM, immediate} +} + +func TestTranslateRawVEXTRACT128WeaviateRegression(t *testing.T) { + const source = `TEXT rawExtract(SB), $0-0 + LONG $0x197de3c4; WORD $0x01c1 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawExtract": {Name: "rawExtract", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "shufflevector <32 x i8>") { + t.Fatalf("raw VEXTRACTF128 lowering omitted vector extract:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-vextract128.ll", "amd64-raw-vextract128.o", ir) +} + +func TestDecodedX86VEXTRACT128CompleteRegisterFamily(t *testing.T) { + count := 0 + for opcode, wantOp := range map[byte]Op{0x19: "VEXTRACTF128", 0x39: "VEXTRACTI128"} { + for source := 0; source < 16; source++ { + for destination := 0; destination < 16; destination++ { + for immediate := 0; immediate < 256; immediate++ { + code := encodeX86VEXTRACT128(opcode, byte(immediate), source, destination) + got, length, ok, err := decodedX86VEXTRACT128Instruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + if got.Op != wantOp || len(got.Args) != 3 || got.Args[0].Imm != int64(immediate) || got.Args[1].String() != fmt.Sprintf("Y%d", source) || got.Args[2].String() != fmt.Sprintf("X%d", destination) { + t.Fatalf("decode %x = %+v, want %s $%d, Y%d, X%d", code, got, wantOp, immediate, source, destination) + } + count++ + } + } + } + } + if count != 131072 { + t.Fatalf("covered %d VEXTRACT128 register encodings, want 131072", count) + } +} + +func TestDecodedX86VEXTRACT128MemoryAndInvalidForms(t *testing.T) { + code := []byte{0x64, 0xc4, 0x03, 0x7d, 0x39, 0x64, 0x88, 0x20, 0xff} + got, length, ok, err := decodedX86VEXTRACT128Instruction(code, 64) + wantDestination := MemRef{Segment: FS, Base: "R8", Index: "R9", Scale: 4, Off: 32} + if err != nil || !ok || length != len(code) || got.Op != "VEXTRACTI128" || len(got.Args) != 3 || got.Args[0].Imm != 0xff || got.Args[1].String() != "Y12" || got.Args[2].Kind != OpMem || got.Args[2].Mem != wantDestination { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + + valid := encodeX86VEXTRACT128(0x19, 1, 0, 0) + for _, invalid := range [][]byte{ + {0xc4}, + {valid[0], valid[1] ^ 1, valid[2], valid[3], valid[4], valid[5]}, + encodeX86VEXTRACT128(0x18, 1, 0, 0), + } { + if instruction, _, matched, decodeErr := decodedX86VEXTRACT128Instruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("invalid encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + for _, invalid := range [][]byte{ + {valid[0], valid[1], valid[2] &^ 1, valid[3], valid[4], valid[5]}, + {valid[0], valid[1], valid[2] &^ 4, valid[3], valid[4], valid[5]}, + {valid[0], valid[1], valid[2] | 0x80, valid[3], valid[4], valid[5]}, + } { + if _, _, matched, decodeErr := decodedX86VEXTRACT128Instruction(invalid, 64); !matched || decodeErr == nil { + t.Fatalf("reserved encoding %x returned ok=%v err=%v", invalid, matched, decodeErr) + } + } + extended := encodeX86VEXTRACT128(0x19, 1, 8, 8) + if _, _, matched, decodeErr := decodedX86VEXTRACT128Instruction(extended, 32); !matched || decodeErr == nil { + t.Fatalf("32-bit extended-register form returned ok=%v err=%v", matched, decodeErr) + } +} + +func TestTranslateRawEVEXTRACTWeaviateRegression(t *testing.T) { + const source = `TEXT rawEVEXTRACT(SB), $0-0 + LONG $0x48fdf362 + WORD $0xc13b + BYTE $0x01 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawEVEXTRACT": {Name: "rawEVEXTRACT", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "shufflevector <64 x i8>") { + t.Fatalf("raw VEXTRACTI64X4 lowering omitted 256-bit block extract:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-evextract.ll", "amd64-raw-evextract.o", ir) +} + +func TestDecodedX86VEXTRACTCompleteEVEXRegisterFamily(t *testing.T) { + tests := []struct { + opcode byte + width64 bool + op Op + outputBytes int + vectorBits []byte + }{ + {opcode: 0x19, op: "VEXTRACTF32X4", outputBytes: 16, vectorBits: []byte{1, 2}}, + {opcode: 0x19, width64: true, op: "VEXTRACTF64X2", outputBytes: 16, vectorBits: []byte{1, 2}}, + {opcode: 0x1b, op: "VEXTRACTF32X8", outputBytes: 32, vectorBits: []byte{2}}, + {opcode: 0x1b, width64: true, op: "VEXTRACTF64X4", outputBytes: 32, vectorBits: []byte{2}}, + {opcode: 0x39, op: "VEXTRACTI32X4", outputBytes: 16, vectorBits: []byte{1, 2}}, + {opcode: 0x39, width64: true, op: "VEXTRACTI64X2", outputBytes: 16, vectorBits: []byte{1, 2}}, + {opcode: 0x3b, op: "VEXTRACTI32X8", outputBytes: 32, vectorBits: []byte{2}}, + {opcode: 0x3b, width64: true, op: "VEXTRACTI64X4", outputBytes: 32, vectorBits: []byte{2}}, + } + count := 0 + for _, test := range tests { + for _, vectorBits := range test.vectorBits { + sourcePrefix := [...]string{"", "Y", "Z"}[vectorBits] + destinationPrefix := "X" + if test.outputBytes == 32 { + destinationPrefix = "Y" + } + for _, masking := range []struct { + mask int + zeroing bool + suffix string + }{ + {}, + {mask: 3}, + {mask: 7, zeroing: true, suffix: ".Z"}, + } { + for source := 0; source < 32; source++ { + for destination := 0; destination < 32; destination++ { + immediate := byte(source<<3 | destination&7) + code := encodeX86EVEXTRACT(test.opcode, immediate, test.width64, vectorBits, masking.mask, masking.zeroing, source, destination) + got, length, ok, err := decodedX86VEXTRACT128Instruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("$%d", immediate), fmt.Sprintf("%s%d", sourcePrefix, source)} + if masking.mask != 0 { + wantArgs = append(wantArgs, fmt.Sprintf("K%d", masking.mask)) + } + wantArgs = append(wantArgs, fmt.Sprintf("%s%d", destinationPrefix, destination)) + wantOp := test.op + Op(masking.suffix) + if got.Op != wantOp || len(got.Args) != len(wantArgs) { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + for index := range wantArgs { + if got.Args[index].String() != wantArgs[index] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + } + count++ + } + } + } + } + } + if count != 36864 { + t.Fatalf("covered %d EVEX vector extract register encodings, want 36864", count) + } +} + +func TestDecodedX86VEXTRACTCompleteEVEXMemoryAndInvalidForms(t *testing.T) { + tests := []struct { + opcode byte + width64 bool + op Op + outputBytes int + vectorBits byte + }{ + {opcode: 0x19, op: "VEXTRACTF32X4", outputBytes: 16, vectorBits: 1}, + {opcode: 0x19, width64: true, op: "VEXTRACTF64X2", outputBytes: 16, vectorBits: 2}, + {opcode: 0x1b, op: "VEXTRACTF32X8", outputBytes: 32, vectorBits: 2}, + {opcode: 0x1b, width64: true, op: "VEXTRACTF64X4", outputBytes: 32, vectorBits: 2}, + {opcode: 0x39, op: "VEXTRACTI32X4", outputBytes: 16, vectorBits: 1}, + {opcode: 0x39, width64: true, op: "VEXTRACTI64X2", outputBytes: 16, vectorBits: 2}, + {opcode: 0x3b, op: "VEXTRACTI32X8", outputBytes: 32, vectorBits: 2}, + {opcode: 0x3b, width64: true, op: "VEXTRACTI64X4", outputBytes: 32, vectorBits: 2}, + } + for _, test := range tests { + code := encodeX86EVEXTRACT(test.opcode, 0xff, test.width64, test.vectorBits, 2, false, 21, 0) + code[5] = 0x68 + code = append(code[:6], append([]byte{0x7f}, code[6:]...)...) + got, length, ok, err := decodedX86VEXTRACT128Instruction(code, 64) + wantSourcePrefix := [...]string{"", "Y", "Z"}[test.vectorBits] + wantDestination := fmt.Sprintf("%d(AX)", test.outputBytes*127) + if err != nil || !ok || length != len(code) || got.Op != test.op || len(got.Args) != 4 || got.Args[0].Imm != 0xff || got.Args[1].String() != fmt.Sprintf("%s21", wantSourcePrefix) || got.Args[2].String() != "K2" || got.Args[3].String() != wantDestination { + t.Fatalf("decode %x = %+v, length=%d ok=%v err=%v; want %s $255, %s21, K2, %s", code, got, length, ok, err, test.op, wantSourcePrefix, wantDestination) + } + } + + valid := encodeX86EVEXTRACT(0x3b, 1, true, 2, 1, false, 0, 0) + for name, mutate := range map[string]func([]byte){ + "used vvvv": func(code []byte) { code[2] &^= 0x08 }, + "broadcast": func(code []byte) { code[3] |= 0x10 }, + "reserved length": func(code []byte) { code[3] |= 0x20 }, + } { + code := append([]byte(nil), valid...) + mutate(code) + if _, _, matched, decodeErr := decodedX86VEXTRACT128Instruction(code, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x returned ok=%v err=%v", name, code, matched, decodeErr) + } + } + memoryZero := encodeX86EVEXTRACT(0x3b, 1, true, 2, 1, true, 0, 0) + memoryZero[5] = 0x00 + memoryZero = append(memoryZero[:6], append([]byte{0, 0, 0, 0}, memoryZero[6:]...)...) + if _, _, matched, decodeErr := decodedX86VEXTRACT128Instruction(memoryZero, 64); !matched || decodeErr == nil { + t.Fatalf("zeroing memory encoding returned ok=%v err=%v", matched, decodeErr) + } +} diff --git a/amd64_raw_vinserti128_test.go b/amd64_raw_vinserti128_test.go new file mode 100644 index 00000000..122fbff6 --- /dev/null +++ b/amd64_raw_vinserti128_test.go @@ -0,0 +1,226 @@ +package plan9asm + +import ( + "fmt" + "reflect" + "strings" + "testing" +) + +func encodeX86VINSERT128(opcode, immediate byte, firstSource, secondSource, destination int) []byte { + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-firstSource/8)<<5 | 3) + vexBits := byte((^secondSource&15)<<3 | 1<<2 | 1) + modRM := byte(0xc0 | (destination&7)<<3 | firstSource&7) + return []byte{0xc4, vex0, vexBits, opcode, modRM, immediate} +} + +func encodeX86VEXPackedBroadcast(opcode byte, wide bool, source, destination int) []byte { + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-source/8)<<5 | 2) + vexBits := byte(0x79) + if wide { + vexBits |= 1 << 2 + } + modRM := byte(0xc0 | (destination&7)<<3 | source&7) + return []byte{0xc4, vex0, vexBits, opcode, modRM} +} + +func TestDecodeX86RawDirectiveGroupReportedInfectiousVINSERTI128(t *testing.T) { + code := []byte{ + 0xc4, 0xe3, 0x4d, 0x38, 0xf6, 0x01, + 0xc4, 0xe3, 0x45, 0x38, 0xff, 0x01, + 0xc4, 0x62, 0x7d, 0x78, 0xc5, + } + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "infectious VINSERTI128 sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + want := []string{ + "VINSERTI128 $1, X6, Y6, Y6", + "VINSERTI128 $1, X7, Y7, Y7", + "VPBROADCASTB X5, Y8", + } + if len(decoded) != len(want) { + t.Fatalf("decoded %d instructions as %#v, want %d", len(decoded), decoded, len(want)) + } + for index := range want { + if !strings.HasPrefix(decoded[index].Raw, want[index]+" ") { + t.Fatalf("instruction %d decoded as %q, want %q", index, decoded[index].Raw, want[index]) + } + } +} + +func TestDecodedX86RawVINSERTI128Go127OracleCases(t *testing.T) { + for _, test := range []struct { + code []byte + want string + }{ + {code: []byte{0xc4, 0xe3, 0x05, 0x38, 0x13, 0x07}, want: "VINSERTI128 $7, 0(BX), Y15, Y2"}, + {code: []byte{0xc4, 0xc3, 0x05, 0x38, 0x13, 0x07}, want: "VINSERTI128 $7, 0(R11), Y15, Y2"}, + {code: []byte{0xc4, 0xe3, 0x05, 0x38, 0xd2, 0x07}, want: "VINSERTI128 $7, X2, Y15, Y2"}, + {code: []byte{0xc4, 0x43, 0x05, 0x38, 0xdb, 0x07}, want: "VINSERTI128 $7, X11, Y15, Y11"}, + } { + instruction, length, ok, err := decodedX86VINSERT128Instruction(test.code, 64) + if !ok || err != nil || length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as (%#v, %d, %v, %v), want %q", test.code, instruction, length, ok, err, test.want) + } + } +} + +func TestDecodedX86RawVINSERT128CompleteRegisterFamily(t *testing.T) { + count := 0 + for opcode, wantOp := range map[byte]Op{0x18: "VINSERTF128", 0x38: "VINSERTI128"} { + for firstSource := 0; firstSource < 16; firstSource++ { + for secondSource := 0; secondSource < 16; secondSource++ { + for destination := 0; destination < 16; destination++ { + immediate := byte(firstSource*16 + destination) + code := encodeX86VINSERT128(opcode, immediate, firstSource, secondSource, destination) + got, length, ok, err := decodedX86VINSERT128Instruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{ + fmt.Sprintf("$%d", immediate), + fmt.Sprintf("X%d", firstSource), + fmt.Sprintf("Y%d", secondSource), + fmt.Sprintf("Y%d", destination), + } + if got.Op != wantOp || len(got.Args) != len(wantArgs) { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + for index := range wantArgs { + if got.Args[index].String() != wantArgs[index] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + } + count++ + } + } + } + } + if count != 8192 { + t.Fatalf("covered %d VINSERT128 register encodings, want 8192", count) + } +} + +func TestDecodedX86RawVINSERT128MemoryAndInvalidForms(t *testing.T) { + code := []byte{0x64, 0xc4, 0x03, 0x15, 0x38, 0x64, 0x8b, 0x20, 0xff} + got, length, ok, err := decodedX86VINSERT128Instruction(code, 64) + wantMemory := MemRef{Segment: FS, Base: "R11", Index: "R9", Scale: 4, Off: 32} + if err != nil || !ok || length != len(code) || got.Op != "VINSERTI128" || len(got.Args) != 4 || got.Args[0].Imm != 0xff || got.Args[1].Kind != OpMem || !reflect.DeepEqual(got.Args[1].Mem, wantMemory) || got.Args[2].String() != "Y13" || got.Args[3].String() != "Y12" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + + valid := encodeX86VINSERT128(0x38, 1, 0, 0, 0) + for _, invalid := range [][]byte{ + {0xc4}, + {valid[0], valid[1] ^ 1, valid[2], valid[3], valid[4], valid[5]}, + encodeX86VINSERT128(0x39, 1, 0, 0, 0), + } { + if instruction, _, matched, decodeErr := decodedX86VINSERT128Instruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("invalid encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + for name, mutate := range map[string]func([]byte){ + "wrong pp": func(code []byte) { code[2] &^= 1 }, + "VEX.W": func(code []byte) { code[2] |= 0x80 }, + "VEX.128": func(code []byte) { code[2] &^= 4 }, + "address override": func(code []byte) { copy(code[1:], code); code[0] = 0x67 }, + } { + code := append([]byte(nil), valid...) + if name == "address override" { + code = append(code, 0) + } + mutate(code) + if _, _, matched, decodeErr := decodedX86VINSERT128Instruction(code, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x returned ok=%v err=%v", name, code, matched, decodeErr) + } + } + truncatedImmediate := valid[:len(valid)-1] + if _, _, matched, decodeErr := decodedX86VINSERT128Instruction(truncatedImmediate, 64); !matched || decodeErr == nil { + t.Fatalf("truncated immediate returned ok=%v err=%v", matched, decodeErr) + } + if _, _, matched, decodeErr := decodedX86VINSERT128Instruction(valid, 32); !matched || decodeErr == nil { + t.Fatalf("386 VINSERT128 returned ok=%v err=%v", matched, decodeErr) + } +} + +func TestDecodedX86RawVEXPackedBroadcastCompleteRegisterFamily(t *testing.T) { + operations := map[byte]Op{ + 0x78: "VPBROADCASTB", + 0x79: "VPBROADCASTW", + 0x58: "VPBROADCASTD", + 0x59: "VPBROADCASTQ", + } + count := 0 + for opcode, wantOp := range operations { + for _, wide := range []bool{false, true} { + for source := 0; source < 16; source++ { + for destination := 0; destination < 16; destination++ { + code := encodeX86VEXPackedBroadcast(opcode, wide, source, destination) + got, length, ok, err := decodedX86VEXPackedBroadcastInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + prefix := "X" + if wide { + prefix = "Y" + } + wantArgs := []string{fmt.Sprintf("X%d", source), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != wantOp || len(got.Args) != 2 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, wantOp, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + if count != 2048 { + t.Fatalf("covered %d VEX packed-broadcast register encodings, want 2048", count) + } +} + +func TestDecodedX86RawVEXPackedBroadcastMemoryAndInvalidForms(t *testing.T) { + for opcode, wantOp := range map[byte]Op{0x78: "VPBROADCASTB", 0x79: "VPBROADCASTW", 0x58: "VPBROADCASTD", 0x59: "VPBROADCASTQ"} { + code := []byte{0x65, 0xc4, 0x02, 0x7d, opcode, 0x64, 0x8b, 0x20} + got, length, ok, err := decodedX86VEXPackedBroadcastInstruction(code, 64) + wantMemory := MemRef{Segment: GS, Base: "R11", Index: "R9", Scale: 4, Off: 32} + if err != nil || !ok || length != len(code) || got.Op != wantOp || len(got.Args) != 2 || got.Args[0].Kind != OpMem || !reflect.DeepEqual(got.Args[0].Mem, wantMemory) || got.Args[1].String() != "Y12" { + t.Fatalf("decode %x = %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + } + + valid := encodeX86VEXPackedBroadcast(0x78, true, 0, 0) + for _, invalid := range [][]byte{ + {0xc4}, + {valid[0], valid[1] ^ 1, valid[2], valid[3], valid[4]}, + encodeX86VEXPackedBroadcast(0x77, true, 0, 0), + } { + if instruction, _, matched, decodeErr := decodedX86VEXPackedBroadcastInstruction(invalid, 64); matched || decodeErr != nil { + t.Fatalf("invalid encoding %x decoded as %+v, ok=%v, err=%v", invalid, instruction, matched, decodeErr) + } + } + for name, mutate := range map[string]func([]byte){ + "wrong pp": func(code []byte) { code[2] &^= 1 }, + "VEX.W": func(code []byte) { code[2] |= 0x80 }, + "used vvvv": func(code []byte) { code[2] &^= 0x08 }, + } { + code := append([]byte(nil), valid...) + mutate(code) + if _, _, matched, decodeErr := decodedX86VEXPackedBroadcastInstruction(code, 64); !matched || decodeErr == nil { + t.Fatalf("%s encoding %x returned ok=%v err=%v", name, code, matched, decodeErr) + } + } + ripRelative := []byte{0xc4, 0xe2, 0x7d, 0x78, 0x05, 0, 0, 0, 0} + if _, _, matched, decodeErr := decodedX86VEXPackedBroadcastInstruction(ripRelative, 64); !matched || decodeErr == nil { + t.Fatalf("RIP-relative encoding returned ok=%v err=%v", matched, decodeErr) + } + extended := encodeX86VEXPackedBroadcast(0x78, true, 8, 8) + if _, _, matched, decodeErr := decodedX86VEXPackedBroadcastInstruction(extended, 32); !matched || decodeErr == nil { + t.Fatalf("386 extended-register form returned ok=%v err=%v", matched, decodeErr) + } + valid386 := encodeX86VEXPackedBroadcast(0x78, true, 7, 7) + got, length, matched, decodeErr := decodedX86VEXPackedBroadcastInstruction(valid386, 32) + if decodeErr != nil || !matched || length != len(valid386) || got.Raw != "VPBROADCASTB X7, Y7" { + t.Fatalf("386 base-register form decoded as %+v, length=%d ok=%v err=%v", got, length, matched, decodeErr) + } +} diff --git a/amd64_raw_vmovq_test.go b/amd64_raw_vmovq_test.go new file mode 100644 index 00000000..9b8fb18e --- /dev/null +++ b/amd64_raw_vmovq_test.go @@ -0,0 +1,191 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateRawVEXVMOVDWeaviateRegression(t *testing.T) { + const source = `TEXT rawVMOVD(SB), $0-0 + LONG $0x7e79c1c4 + BYTE $0xc7 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawVMOVD": {Name: "rawVMOVD", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "extractelement <4 x i32>") { + t.Fatalf("raw VMOVD lowering omitted scalar extraction:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-vex-vmovd.ll", "amd64-raw-vex-vmovd.o", ir) +} + +func TestDecodedX86VMOVQInstructionCompleteVEXForms(t *testing.T) { + tests := []struct { + name string + code []byte + want string + }{ + {name: "x_to_gp", code: []byte{0xc4, 0xe1, 0xf9, 0x7e, 0xc8}, want: "VMOVQ X1, AX"}, + {name: "x_to_x", code: []byte{0xc4, 0xe1, 0x79, 0xd6, 0xc8}, want: "VMOVQ X1, X0"}, + {name: "gp_to_x", code: []byte{0xc4, 0xe1, 0xf9, 0x6e, 0xc8}, want: "VMOVQ AX, X1"}, + {name: "x_to_x_f3", code: []byte{0xc5, 0xfa, 0x7e, 0xc8}, want: "VMOVQ X0, X1"}, + {name: "memory_to_extended_x", code: []byte{0xc5, 0x7a, 0x7e, 0x5e, 0x20}, want: "VMOVQ 32(SI), X11"}, + {name: "extended_x_to_sib_memory", code: []byte{0xc4, 0x21, 0xf9, 0x7e, 0x94, 0x8c, 0x78, 0x56, 0x34, 0x12}, want: "VMOVQ X10, 305419896(SP)(R9*4)"}, + {name: "reported_weaviate_vmovd", code: []byte{0xc4, 0xc1, 0x79, 0x7e, 0xc7}, want: "VMOVD X0, R15"}, + {name: "vmovd_extended_gp_to_x", code: []byte{0xc4, 0xc1, 0x79, 0x6e, 0xcf}, want: "VMOVD R15, X1"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VMOVQInstruction(test.code, 64) + if err != nil { + t.Fatal(err) + } + if !ok { + t.Fatal("encoding was not recognized") + } + if length != len(test.code) { + t.Fatalf("length = %d, want %d", length, len(test.code)) + } + if instruction.Raw != test.want { + t.Fatalf("instruction = %q, want %q", instruction.Raw, test.want) + } + }) + } +} + +func encodeX86VEXVMOVDQ(opcode, pp byte, vex3, width64 bool, vector, rm int) []byte { + modRM := byte(0xc0 | (vector&7)<<3 | rm&7) + if !vex3 { + vex1 := byte((1-vector/8)<<7 | 15<<3 | int(pp)) + return []byte{0xc5, vex1, opcode, modRM} + } + vex0 := byte((1-vector/8)<<7 | 1<<6 | (1-rm/8)<<5 | 1) + vex1 := byte(15<<3 | int(pp)) + if width64 { + vex1 |= 0x80 + } + return []byte{0xc4, vex0, vex1, opcode, modRM} +} + +func TestDecodedX86VMOVDQCompleteVEXRegisterFamily(t *testing.T) { + tests := []struct { + opcode byte + pp byte + width64 bool + op Op + reverse bool + vectorRM bool + vex2 bool + }{ + {opcode: 0x7e, pp: 1, op: "VMOVD", vex2: true}, + {opcode: 0x6e, pp: 1, op: "VMOVD", reverse: true, vex2: true}, + {opcode: 0x7e, pp: 1, width64: true, op: "VMOVQ"}, + {opcode: 0xd6, pp: 1, op: "VMOVQ", vectorRM: true, vex2: true}, + {opcode: 0x6e, pp: 1, width64: true, op: "VMOVQ", reverse: true}, + {opcode: 0x7e, pp: 2, op: "VMOVQ", reverse: true, vectorRM: true, vex2: true}, + } + count := 0 + for _, test := range tests { + for _, vex3 := range []bool{false, true} { + if !vex3 && !test.vex2 { + continue + } + rmLimit := 16 + if !vex3 { + rmLimit = 8 + } + for vector := 0; vector < 16; vector++ { + for rm := 0; rm < rmLimit; rm++ { + code := encodeX86VEXVMOVDQ(test.opcode, test.pp, vex3, test.width64, vector, rm) + got, length, ok, err := decodedX86VMOVQInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + rmName := fmt.Sprintf("R%d", rm) + if rm < 8 { + rmName = [...]string{"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}[rm] + } + if test.vectorRM { + rmName = fmt.Sprintf("X%d", rm) + } + wantArgs := []string{fmt.Sprintf("X%d", vector), rmName} + if test.reverse { + wantArgs[0], wantArgs[1] = wantArgs[1], wantArgs[0] + } + if got.Op != test.op || len(got.Args) != 2 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, test.op, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + if count != 2048 { + t.Fatalf("covered %d VEX VMOVD/VMOVQ register encodings, want 2048", count) + } +} + +func TestDecodedX86VMOVDQCompleteGo127EVEXForms(t *testing.T) { + tests := []struct { + name string + code []byte + want string + }{ + {name: "d high x to gp", code: []byte{0x62, 0x61, 0x7d, 0x08, 0x7e, 0xf8}, want: "VMOVD X31, AX"}, + {name: "d gp to high x", code: []byte{0x62, 0x61, 0x7d, 0x08, 0x6e, 0xf8}, want: "VMOVD AX, X31"}, + {name: "q high x to gp", code: []byte{0x62, 0x61, 0xfd, 0x08, 0x7e, 0xf8}, want: "VMOVQ X31, AX"}, + {name: "q x to high x", code: []byte{0x62, 0x91, 0xfd, 0x08, 0xd6, 0xc7}, want: "VMOVQ X0, X31"}, + {name: "q gp to high x", code: []byte{0x62, 0x61, 0xfd, 0x08, 0x6e, 0xf8}, want: "VMOVQ AX, X31"}, + {name: "q high x to x alternate", code: []byte{0x62, 0xf1, 0xfe, 0x08, 0x7e, 0xc7}, want: "VMOVQ X7, X0"}, + {name: "d high x to compressed memory", code: []byte{0x62, 0x61, 0x7d, 0x08, 0x7e, 0x78, 0x7f}, want: "VMOVD X31, 508(AX)"}, + {name: "q compressed memory to high x", code: []byte{0x62, 0x61, 0xfd, 0x08, 0x6e, 0x78, 0x7f}, want: "VMOVQ 1016(AX), X31"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VMOVQInstruction(test.code, 64) + if err != nil { + t.Fatal(err) + } + if !ok || length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as %+v length=%d ok=%v, want %q", test.code, instruction, length, ok, test.want) + } + }) + } +} + +func TestDecodedX86VMOVQInstructionRejectsInvalidVEXForms(t *testing.T) { + tests := []struct { + name string + code []byte + mode int + }{ + {name: "truncated_modrm", code: []byte{0xc5, 0xfa, 0x7e}, mode: 64}, + {name: "vex_l_one", code: []byte{0xc5, 0xfe, 0x7e, 0xc8}, mode: 64}, + {name: "used_vvvv", code: []byte{0xc5, 0xf2, 0x7e, 0xc8}, mode: 64}, + {name: "w_one_in_386", code: []byte{0xc4, 0xe1, 0xf9, 0x6e, 0xc8}, mode: 32}, + {name: "extended_register_in_386", code: []byte{0xc5, 0x7a, 0x7e, 0xc0}, mode: 32}, + {name: "rip_relative", code: []byte{0xc5, 0xfa, 0x7e, 0x05, 0, 0, 0, 0}, mode: 64}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86VMOVQInstruction(test.code, test.mode) + if !ok { + t.Fatal("VMOVQ-family encoding was not recognized") + } + if err == nil { + t.Fatal("invalid encoding was accepted") + } + }) + } +} diff --git a/amd64_raw_vnni_test.go b/amd64_raw_vnni_test.go new file mode 100644 index 00000000..29b03b3d --- /dev/null +++ b/amd64_raw_vnni_test.go @@ -0,0 +1,125 @@ +package plan9asm + +import "testing" + +func TestDecodedX86VNNIInstructionCompleteVEXFamily(t *testing.T) { + for _, test := range []struct { + opcode byte + op Op + }{ + {0x50, "VPDPBUSD"}, + {0x51, "VPDPBUSDS"}, + {0x52, "VPDPWSSD"}, + {0x53, "VPDPWSSDS"}, + } { + t.Run(string(test.op), func(t *testing.T) { + code := []byte{0xc4, 0xe2, 0x71, test.opcode, 0xc2} + instruction, length, ok, err := decodedX86VNNIInstruction(code, 64) + if err != nil { + t.Fatal(err) + } + if !ok { + t.Fatal("encoding was not recognized") + } + if length != len(code) { + t.Fatalf("length = %d, want %d", length, len(code)) + } + want := string(test.op) + " X2, X1, X0" + if instruction.Op != test.op || instruction.Raw != want { + t.Fatalf("instruction = %#v, want %q", instruction, want) + } + }) + } + + for _, test := range []struct { + name string + code []byte + mode int + want string + }{ + { + name: "y_extended_registers", + code: []byte{0xc4, 0x42, 0x15, 0x50, 0xdc}, + mode: 64, + want: "VPDPBUSD Y12, Y13, Y11", + }, + { + name: "x_memory_sib_disp8", + code: []byte{0xc4, 0x62, 0x11, 0x50, 0x5c, 0x88, 0x20}, + mode: 64, + want: "VPDPBUSD 32(AX)(CX*4), X13, X11", + }, + { + name: "y_memory_negative_disp8", + code: []byte{0xc4, 0x62, 0x65, 0x51, 0x64, 0x35, 0xef}, + mode: 64, + want: "VPDPBUSDS -17(BP)(SI*1), Y3, Y12", + }, + { + name: "x_memory_extended_address", + code: []byte{0xc4, 0x82, 0x39, 0x52, 0x74, 0x7e, 0x07}, + mode: 64, + want: "VPDPWSSD 7(R14)(R15*2), X8, X6", + }, + { + name: "y_386_memory", + code: []byte{0xc4, 0xe2, 0x65, 0x53, 0x64, 0x35, 0xef}, + mode: 32, + want: "VPDPWSSDS -17(BP)(SI*1), Y3, Y4", + }, + } { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VNNIInstruction(test.code, test.mode) + if err != nil { + t.Fatal(err) + } + if !ok || length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decode = (%#v, %d, %v), want %q", instruction, length, ok, test.want) + } + }) + } +} + +func TestDecodedX86VNNIInstructionRejectsInvalidVEXForms(t *testing.T) { + for _, test := range []struct { + name string + code []byte + mode int + }{ + {name: "truncated_modrm", code: []byte{0xc4, 0xe2, 0x71, 0x50}, mode: 64}, + {name: "vex_pp_zero", code: []byte{0xc4, 0xe2, 0x70, 0x50, 0xc2}, mode: 64}, + {name: "vex_w_one", code: []byte{0xc4, 0xe2, 0xf1, 0x50, 0xc2}, mode: 64}, + {name: "address_override", code: []byte{0x67, 0xc4, 0xe2, 0x71, 0x50, 0xc2}, mode: 64}, + {name: "extended_register_in_386", code: []byte{0xc4, 0x42, 0x15, 0x50, 0xdc}, mode: 32}, + {name: "rip_relative", code: []byte{0xc4, 0xe2, 0x71, 0x50, 0x05, 0, 0, 0, 0}, mode: 64}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86VNNIInstruction(test.code, test.mode) + if !ok { + t.Fatal("VNNI encoding was not recognized") + } + if err == nil { + t.Fatal("invalid encoding was accepted") + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupVNNIReportedSequence(t *testing.T) { + code := []byte{ + 0xc4, 0x42, 0x15, 0x50, 0xdc, + 0xc4, 0x62, 0x7d, 0x50, 0xc7, + } + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "go-pherence VEX VNNI sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 2 { + t.Fatalf("decoded %d instructions, want 2: %#v", len(decoded), decoded) + } + for _, instruction := range decoded { + if instruction.Op != "VPDPBUSD" { + t.Fatalf("decoded op = %s, want VPDPBUSD", instruction.Op) + } + } +} diff --git a/amd64_raw_vpadd_test.go b/amd64_raw_vpadd_test.go new file mode 100644 index 00000000..75be16de --- /dev/null +++ b/amd64_raw_vpadd_test.go @@ -0,0 +1,233 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeX86VEXPackedIntegerArithmetic(opcode byte, vex3, width256, widthIgnored bool, destination, source1, source2 int) []byte { + l := byte(0) + if width256 { + l = 1 + } + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + if !vex3 { + vex1 := byte((1-destination/8)<<7 | ((^source1)&15)<<3 | int(l)<<2 | 1) + return []byte{0xc5, vex1, opcode, modRM} + } + vex0 := byte((1-destination/8)<<7 | 1<<6 | (1-source2/8)<<5 | 1) + vex1 := byte(((^source1)&15)<<3 | int(l)<<2 | 1) + if widthIgnored { + vex1 |= 0x80 + } + return []byte{0xc4, vex0, vex1, opcode, modRM} +} + +func TestDecodedX86PackedIntegerAddCompleteVEXRegisterFamily(t *testing.T) { + count := 0 + for opcode, properties := range decodedX86PackedIntegerArithmeticOps { + if !strings.HasPrefix(string(properties.op), "VPADD") { + continue + } + for _, vex3 := range []bool{false, true} { + for _, width256 := range []bool{false, true} { + prefix := "X" + if width256 { + prefix = "Y" + } + for _, widthIgnored := range []bool{false, true} { + if !vex3 && widthIgnored { + continue + } + source2Limit := 16 + if !vex3 { + source2Limit = 8 + } + for destination := 0; destination < 16; destination++ { + for source1 := 0; source1 < 16; source1++ { + for source2 := 0; source2 < source2Limit; source2++ { + code := encodeX86VEXPackedIntegerArithmetic(opcode, vex3, width256, widthIgnored, destination, source1, source2) + got, length, ok, err := decodedX86PackedIntegerArithmeticInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != properties.op || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, properties.op, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + } + if count != 163840 { + t.Fatalf("covered %d VEX packed integer add register encodings, want 163840", count) + } +} + +func TestDecodedX86PackedIntegerSubtractCompleteVEXRegisterFamily(t *testing.T) { + subtractOps := map[byte]struct { + op Op + laneBytes int + }{ + 0xf8: {op: "VPSUBB", laneBytes: 1}, + 0xf9: {op: "VPSUBW", laneBytes: 2}, + 0xfa: {op: "VPSUBD", laneBytes: 4}, + 0xfb: {op: "VPSUBQ", laneBytes: 8}, + 0xe8: {op: "VPSUBSB", laneBytes: 1}, + 0xe9: {op: "VPSUBSW", laneBytes: 2}, + 0xd8: {op: "VPSUBUSB", laneBytes: 1}, + 0xd9: {op: "VPSUBUSW", laneBytes: 2}, + } + count := 0 + for opcode, properties := range subtractOps { + for _, vex3 := range []bool{false, true} { + for _, width256 := range []bool{false, true} { + prefix := "X" + if width256 { + prefix = "Y" + } + for _, widthIgnored := range []bool{false, true} { + if !vex3 && widthIgnored { + continue + } + source2Limit := 16 + if !vex3 { + source2Limit = 8 + } + for destination := 0; destination < 16; destination++ { + for source1 := 0; source1 < 16; source1++ { + for source2 := 0; source2 < source2Limit; source2++ { + code := encodeX86VEXPackedIntegerArithmetic(opcode, vex3, width256, widthIgnored, destination, source1, source2) + got, length, ok, err := decodedX86PackedIntegerArithmeticInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != properties.op || len(got.Args) != 3 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, properties.op, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + } + } + if count != 163840 { + t.Fatalf("covered %d VEX packed integer subtract register encodings, want 163840", count) + } +} + +func TestDecodedX86PackedIntegerArithmeticCompleteEVEXRegisterFamily(t *testing.T) { + count := 0 + for opcode, properties := range decodedX86PackedIntegerArithmeticOps { + for vectorBits := byte(0); vectorBits < 3; vectorBits++ { + prefix := [...]string{"X", "Y", "Z"}[vectorBits] + for destination := 0; destination < 32; destination++ { + for source1 := 0; source1 < 32; source1++ { + for source2 := 0; source2 < 32; source2++ { + p0 := byte((1-(destination>>3)&1)<<7 | (1-(source2>>4)&1)<<6 | (1-(source2>>3)&1)<<5 | (1-(destination>>4)&1)<<4 | 1) + p1 := byte((^source1&15)<<3 | 1<<2 | 1) + if properties.laneBytes == 8 { + p1 |= 0x80 + } + p2 := byte(int(vectorBits)<<5 | (^source1>>4&1)<<3 | 1) + modRM := byte(0xc0 | (destination&7)<<3 | source2&7) + code := []byte{0x62, p0, p1, p2, opcode, modRM} + got, length, ok, err := decodedX86PackedIntegerArithmeticInstruction(code, 64) + if err != nil || !ok || length != len(code) { + t.Fatalf("decode %x returned %+v, length=%d, ok=%v, err=%v", code, got, length, ok, err) + } + wantArgs := []string{fmt.Sprintf("%s%d", prefix, source2), fmt.Sprintf("%s%d", prefix, source1), "K1", fmt.Sprintf("%s%d", prefix, destination)} + if got.Op != properties.op || len(got.Args) != 4 || got.Args[0].String() != wantArgs[0] || got.Args[1].String() != wantArgs[1] || got.Args[2].String() != wantArgs[2] || got.Args[3].String() != wantArgs[3] { + t.Fatalf("decode %x = %+v, want %s %s", code, got, properties.op, strings.Join(wantArgs, ", ")) + } + count++ + } + } + } + } + } + if count != 1572864 { + t.Fatalf("covered %d EVEX packed integer arithmetic encodings, want 1572864", count) + } +} + +func TestTranslateRawVPSUBDWeaviateRegression(t *testing.T) { + const source = `TEXT rawPackedSubtract(SB), $0-0 + LONG $0xd5faedc5 + RET +` + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: "x86_64-unknown-linux-gnu", Sigs: map[string]FuncSig{"rawPackedSubtract": {Name: "rawPackedSubtract", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "sub <8 x i32>") { + t.Fatalf("raw VPSUBD lowering omitted vector subtraction:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "x86_64-unknown-linux-gnu", "amd64-raw-packed-subtract.ll", "amd64-raw-packed-subtract.o", ir) +} + +func TestDecodedX86PackedIntegerArithmeticCompleteGo127Family(t *testing.T) { + // Go 1.27 uses _yvandnpd for all sixteen VPADD/VPSUB variants. These LLVM 22 + // encodings cover every opcode plus VEX/EVEX X/Y/Z, high registers, + // memory, masking, zeroing, D/Q broadcast, and compressed disp8. + tests := []struct { + name string + code []byte + want string + }{ + {name: "vex byte x high", code: []byte{0xc5, 0x79, 0xfc, 0xc1}, want: "VPADDB X1, X0, X8"}, + {name: "vex qword y high memory", code: []byte{0xc4, 0x41, 0x6d, 0xd4, 0x4c, 0x24, 0x20}, want: "VPADDQ 32(R12), Y2, Y9"}, + {name: "byte x high masked", code: []byte{0x62, 0xa1, 0x55, 0x01, 0xfc, 0xf4}, want: "VPADDB X20, X21, K1, X22"}, + {name: "word y memory zeroing", code: []byte{0x62, 0xd1, 0x75, 0xaa, 0xfd, 0x50, 0x03}, want: "VPADDW.Z 96(R8), Y1, K2, Y2"}, + {name: "dword reported minio", code: []byte{0x62, 0x51, 0x45, 0x48, 0xfe, 0xc4}, want: "VPADDD Z12, Z7, Z8"}, + {name: "qword z broadcast zeroing", code: []byte{0x62, 0xf1, 0xf5, 0xdb, 0xd4, 0x50, 0x7f}, want: "VPADDQ.BCST.Z 1016(AX), Z1, K3, Z2"}, + {name: "signed byte z high", code: []byte{0x62, 0x31, 0x7d, 0x40, 0xec, 0xc9}, want: "VPADDSB Z17, Z16, Z9"}, + {name: "signed word x high memory masked", code: []byte{0x62, 0x41, 0x3d, 0x04, 0xed, 0x4c, 0x24, 0x02}, want: "VPADDSW 32(R12), X24, K4, X25"}, + {name: "unsigned byte y high masked", code: []byte{0x62, 0xa1, 0x55, 0x21, 0xdc, 0xf4}, want: "VPADDUSB Y20, Y21, K1, Y22"}, + {name: "unsigned word z memory zeroing", code: []byte{0x62, 0xf1, 0x75, 0xcb, 0xdd, 0x50, 0x7f}, want: "VPADDUSW.Z 8128(AX), Z1, K3, Z2"}, + {name: "subtract dword weaviate", code: []byte{0xc5, 0xed, 0xfa, 0xd5}, want: "VPSUBD Y5, Y2, Y2"}, + {name: "subtract qword broadcast zeroing", code: []byte{0x62, 0xf1, 0xf5, 0xdb, 0xfb, 0x50, 0x7f}, want: "VPSUBQ.BCST.Z 1016(AX), Z1, K3, Z2"}, + {name: "subtract unsigned word z memory zeroing", code: []byte{0x62, 0xf1, 0x75, 0xcb, 0xd9, 0x50, 0x7f}, want: "VPSUBUSW.Z 8128(AX), Z1, K3, Z2"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86PackedIntegerArithmeticInstruction(test.code, 64) + if !ok { + t.Fatal("VPADD encoding was not recognized") + } + if err != nil { + t.Fatal(err) + } + if length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as length=%d raw=%q, want length=%d raw=%q", test.code, length, instruction.Raw, len(test.code), test.want) + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupReportedMinioVPADDD(t *testing.T) { + code := []byte{0x62, 0x51, 0x45, 0x48, 0xfe, 0xc4} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "minio VPADDD", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "VPADDD" || !strings.HasPrefix(decoded[0].Raw, "VPADDD Z12, Z7, Z8 ") { + t.Fatalf("decoded reported minio bytes as %#v", decoded) + } +} diff --git a/amd64_raw_vpermd_test.go b/amd64_raw_vpermd_test.go new file mode 100644 index 00000000..ae24868c --- /dev/null +++ b/amd64_raw_vpermd_test.go @@ -0,0 +1,119 @@ +package plan9asm + +import "testing" + +func TestDecodedX86VariableDwordPermuteInstructionCompleteVEXFamily(t *testing.T) { + for _, test := range []struct { + opcode byte + op Op + }{ + {0x36, "VPERMD"}, + {0x16, "VPERMPS"}, + } { + t.Run(string(test.op), func(t *testing.T) { + code := []byte{0xc4, 0xe2, 0x25, test.opcode, 0xd6} + instruction, length, ok, err := decodedX86VariableDwordPermuteInstruction(code, 64) + if err != nil { + t.Fatal(err) + } + if !ok { + t.Fatal("encoding was not recognized") + } + if length != len(code) { + t.Fatalf("length = %d, want %d", length, len(code)) + } + want := string(test.op) + " Y6, Y11, Y2" + if instruction.Op != test.op || instruction.Raw != want { + t.Fatalf("instruction = %#v, want %q", instruction, want) + } + }) + } + + for _, test := range []struct { + name string + code []byte + mode int + want string + }{ + { + name: "extended_registers", + code: []byte{0xc4, 0x42, 0x05, 0x36, 0xdb}, + mode: 64, + want: "VPERMD Y11, Y15, Y11", + }, + { + name: "memory_sib_disp8", + code: []byte{0xc4, 0x62, 0x15, 0x36, 0x5c, 0x88, 0x20}, + mode: 64, + want: "VPERMD 32(AX)(CX*4), Y13, Y11", + }, + { + name: "memory_negative_disp8", + code: []byte{0xc4, 0x62, 0x65, 0x16, 0x64, 0x35, 0xef}, + mode: 64, + want: "VPERMPS -17(BP)(SI*1), Y3, Y12", + }, + { + name: "386_registers", + code: []byte{0xc4, 0xe2, 0x65, 0x36, 0xe5}, + mode: 32, + want: "VPERMD Y5, Y3, Y4", + }, + } { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VariableDwordPermuteInstruction(test.code, test.mode) + if err != nil { + t.Fatal(err) + } + if !ok || length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decode = (%#v, %d, %v), want %q", instruction, length, ok, test.want) + } + }) + } +} + +func TestDecodedX86VariableDwordPermuteInstructionRejectsInvalidVEXForms(t *testing.T) { + for _, test := range []struct { + name string + code []byte + mode int + }{ + {name: "truncated_modrm", code: []byte{0xc4, 0xe2, 0x25, 0x36}, mode: 64}, + {name: "vex_l_zero", code: []byte{0xc4, 0xe2, 0x21, 0x36, 0xd6}, mode: 64}, + {name: "vex_pp_zero", code: []byte{0xc4, 0xe2, 0x24, 0x36, 0xd6}, mode: 64}, + {name: "vex_w_one", code: []byte{0xc4, 0xe2, 0xa5, 0x36, 0xd6}, mode: 64}, + {name: "address_override", code: []byte{0x67, 0xc4, 0xe2, 0x25, 0x36, 0xd6}, mode: 64}, + {name: "extended_register_in_386", code: []byte{0xc4, 0x42, 0x05, 0x36, 0xdb}, mode: 32}, + {name: "rip_relative", code: []byte{0xc4, 0xe2, 0x25, 0x36, 0x05, 0, 0, 0, 0}, mode: 64}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86VariableDwordPermuteInstruction(test.code, test.mode) + if !ok { + t.Fatal("VPERMD/VPERMPS encoding was not recognized") + } + if err == nil { + t.Fatal("invalid encoding was accepted") + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupVPERMDReportedSequence(t *testing.T) { + code := []byte{ + 0xc4, 0xe2, 0x25, 0x36, 0xd6, + 0xc4, 0xe2, 0x7d, 0x36, 0xd6, + 0xc4, 0xe2, 0x35, 0x36, 0xd6, + } + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "go-pherence VEX VPERMD sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 3 { + t.Fatalf("decoded %d instructions, want 3: %#v", len(decoded), decoded) + } + for _, instruction := range decoded { + if instruction.Op != "VPERMD" { + t.Fatalf("decoded op = %s, want VPERMD", instruction.Op) + } + } +} diff --git a/amd64_raw_vpermi2_test.go b/amd64_raw_vpermi2_test.go new file mode 100644 index 00000000..d9ae41e8 --- /dev/null +++ b/amd64_raw_vpermi2_test.go @@ -0,0 +1,51 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestDecodedX86VPERMI2CompleteGo127Family(t *testing.T) { + // Go 1.27 shares _yvblendmpd across VPERMI2B/W/D/Q/PS/PD. These + // LLVM-verified bytes cover all six opcodes, X/Y/Z widths, high registers, + // memory, masking, zeroing, broadcast, and compressed disp8 scaling. + tests := []struct { + name string + code []byte + want string + }{ + {name: "b x high masked", code: []byte{0x62, 0xa2, 0x55, 0x01, 0x75, 0xf4}, want: "VPERMI2B X20, X21, K1, X22"}, + {name: "w y memory zeroing", code: []byte{0x62, 0xd2, 0xf5, 0xaa, 0x75, 0x50, 0x03}, want: "VPERMI2W.Z 96(R8), Y1, K2, Y2"}, + {name: "d z high", code: []byte{0x62, 0x32, 0x7d, 0x40, 0x76, 0xc9}, want: "VPERMI2D Z17, Z16, Z9"}, + {name: "d z broadcast zeroing", code: []byte{0x62, 0xf2, 0x75, 0xdb, 0x76, 0x50, 0x7f}, want: "VPERMI2D.BCST.Z 508(AX), Z1, K3, Z2"}, + {name: "q reported minio", code: []byte{0x62, 0x22, 0xb5, 0x48, 0x76, 0xf2}, want: "VPERMI2Q Z18, Z9, Z30"}, + {name: "q y high memory masked", code: []byte{0x62, 0x42, 0xbd, 0x24, 0x76, 0x4c, 0x24, 0x02}, want: "VPERMI2Q 64(R12), Y24, K4, Y25"}, + {name: "ps x high masked", code: []byte{0x62, 0xa2, 0x55, 0x01, 0x77, 0xf4}, want: "VPERMI2PS X20, X21, K1, X22"}, + {name: "pd z broadcast zeroing", code: []byte{0x62, 0xf2, 0xf5, 0xdb, 0x77, 0x50, 0x7f}, want: "VPERMI2PD.BCST.Z 1016(AX), Z1, K3, Z2"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VPERMI2Instruction(test.code, 64) + if !ok { + t.Fatal("VPERMI2 encoding was not recognized") + } + if err != nil { + t.Fatal(err) + } + if length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as length=%d raw=%q, want length=%d raw=%q", test.code, length, instruction.Raw, len(test.code), test.want) + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupReportedMinioVPERMI2Q(t *testing.T) { + code := []byte{0x62, 0x22, 0xb5, 0x48, 0x76, 0xf2} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "minio VPERMI2Q", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "VPERMI2Q" || !strings.HasPrefix(decoded[0].Raw, "VPERMI2Q Z18, Z9, Z30 ") { + t.Fatalf("decoded reported minio bytes as %#v", decoded) + } +} diff --git a/amd64_raw_vpermq_test.go b/amd64_raw_vpermq_test.go new file mode 100644 index 00000000..61ca796f --- /dev/null +++ b/amd64_raw_vpermq_test.go @@ -0,0 +1,79 @@ +package plan9asm + +import "testing" + +func TestDecodedX86VPERMQInstructionCompleteVEXForms(t *testing.T) { + tests := []struct { + name string + code []byte + mode int + want string + }{ + {name: "register", code: []byte{0xc4, 0xe3, 0xfd, 0x00, 0xc9, 0x39}, mode: 64, want: "VPERMQ $57, Y1, Y1"}, + {name: "extended_registers", code: []byte{0xc4, 0x43, 0xfd, 0x00, 0xca, 0xff}, mode: 64, want: "VPERMQ $255, Y10, Y9"}, + {name: "memory_disp8", code: []byte{0xc4, 0xe3, 0xfd, 0x00, 0x4e, 0x20, 0x01}, mode: 64, want: "VPERMQ $1, 32(SI), Y1"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VPERMQInstruction(test.code, test.mode) + if err != nil { + t.Fatal(err) + } + if !ok { + t.Fatal("encoding was not recognized") + } + if length != len(test.code) { + t.Fatalf("length = %d, want %d", length, len(test.code)) + } + if instruction.Raw != test.want { + t.Fatalf("instruction = %q, want %q", instruction.Raw, test.want) + } + }) + } +} + +func TestDecodedX86VPERMQInstructionRejectsInvalidVEXForms(t *testing.T) { + tests := []struct { + name string + code []byte + mode int + }{ + {name: "truncated_modrm", code: []byte{0xc4, 0xe3, 0xfd, 0x00}, mode: 64}, + {name: "truncated_immediate", code: []byte{0xc4, 0xe3, 0xfd, 0x00, 0xc9}, mode: 64}, + {name: "vex_l_zero", code: []byte{0xc4, 0xe3, 0xf9, 0x00, 0xc9, 0x39}, mode: 64}, + {name: "used_vvvv", code: []byte{0xc4, 0xe3, 0xed, 0x00, 0xc9, 0x39}, mode: 64}, + {name: "extended_register_in_386", code: []byte{0xc4, 0x43, 0xfd, 0x00, 0xca, 0xff}, mode: 32}, + {name: "rip_relative", code: []byte{0xc4, 0xe3, 0xfd, 0x00, 0x0d, 0, 0, 0, 0, 0x39}, mode: 64}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86VPERMQInstruction(test.code, test.mode) + if !ok { + t.Fatal("VPERMQ encoding was not recognized") + } + if err == nil { + t.Fatal("invalid encoding was accepted") + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupVPERMQSequence(t *testing.T) { + code := []byte{ + 0xc4, 0xe3, 0xfd, 0x00, 0xc9, 0x39, + 0xc4, 0xe3, 0xfd, 0x00, 0xd2, 0x4e, + 0xc4, 0xe3, 0xfd, 0x00, 0xdb, 0x93, + } + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "VPERMQ raw sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 3 { + t.Fatalf("decoded %d instructions, want 3: %#v", len(decoded), decoded) + } + for _, instruction := range decoded { + if instruction.Op != "VPERMQ" { + t.Fatalf("decoded op = %s, want VPERMQ", instruction.Op) + } + } +} diff --git a/amd64_raw_vpinsr_test.go b/amd64_raw_vpinsr_test.go new file mode 100644 index 00000000..56b13e98 --- /dev/null +++ b/amd64_raw_vpinsr_test.go @@ -0,0 +1,74 @@ +package plan9asm + +import "testing" + +func TestDecodedX86VPINSRInstructionCompleteVEXFamily(t *testing.T) { + tests := []struct { + name string + code []byte + mode int + want string + }{ + {name: "byte_register", code: []byte{0xc4, 0xe3, 0x79, 0x20, 0xc1, 0x02}, mode: 64, want: "VPINSRB $2, CX, X0, X0"}, + {name: "word_two_byte_vex", code: []byte{0xc5, 0xf9, 0xc4, 0xc1, 0x02}, mode: 64, want: "VPINSRW $2, CX, X0, X0"}, + {name: "dword_register", code: []byte{0xc4, 0xe3, 0x79, 0x22, 0xc1, 0x02}, mode: 64, want: "VPINSRD $2, CX, X0, X0"}, + {name: "qword_register", code: []byte{0xc4, 0xe3, 0xf9, 0x22, 0xc1, 0x02}, mode: 64, want: "VPINSRQ $2, CX, X0, X0"}, + {name: "qword_memory_disp8", code: []byte{0xc4, 0x63, 0xa1, 0x22, 0x5e, 0x28, 0x01}, mode: 64, want: "VPINSRQ $1, 40(SI), X11, X11"}, + {name: "extended_registers", code: []byte{0xc4, 0x43, 0x31, 0x22, 0xca, 0x01}, mode: 64, want: "VPINSRD $1, R10, X9, X9"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VPINSRInstruction(test.code, test.mode) + if err != nil { + t.Fatal(err) + } + if !ok { + t.Fatal("encoding was not recognized") + } + if length != len(test.code) { + t.Fatalf("length = %d, want %d", length, len(test.code)) + } + if instruction.Raw != test.want { + t.Fatalf("instruction = %q, want %q", instruction.Raw, test.want) + } + }) + } +} + +func TestDecodedX86VPINSRInstructionRejectsInvalidVEXForms(t *testing.T) { + tests := []struct { + name string + code []byte + mode int + }{ + {name: "truncated_modrm", code: []byte{0xc4, 0xe3, 0xf9, 0x22}, mode: 64}, + {name: "truncated_immediate", code: []byte{0xc4, 0xe3, 0xf9, 0x22, 0xc1}, mode: 64}, + {name: "vex_l_one", code: []byte{0xc4, 0xe3, 0xfd, 0x22, 0xc1, 0x02}, mode: 64}, + {name: "vex_pp_zero", code: []byte{0xc4, 0xe3, 0xf8, 0x22, 0xc1, 0x02}, mode: 64}, + {name: "qword_in_386", code: []byte{0xc4, 0xe3, 0xf9, 0x22, 0xc1, 0x02}, mode: 32}, + {name: "extended_register_in_386", code: []byte{0xc4, 0x43, 0x31, 0x22, 0xca, 0x01}, mode: 32}, + {name: "rip_relative", code: []byte{0xc4, 0xe3, 0xf9, 0x22, 0x05, 0, 0, 0, 0, 0x02}, mode: 64}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86VPINSRInstruction(test.code, test.mode) + if !ok { + t.Fatal("VPINSR encoding was not recognized") + } + if err == nil { + t.Fatal("invalid encoding was accepted") + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupVPINSRQSequence(t *testing.T) { + code := []byte{0xc4, 0x63, 0xa1, 0x22, 0x5e, 0x28, 0x01} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "VPINSRQ raw sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "VPINSRQ" { + t.Fatalf("decoded = %#v, want one VPINSRQ", decoded) + } +} diff --git a/amd64_raw_vpror_test.go b/amd64_raw_vpror_test.go new file mode 100644 index 00000000..ec8393ff --- /dev/null +++ b/amd64_raw_vpror_test.go @@ -0,0 +1,48 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestDecodedX86PackedImmediateRotateCompleteGo127Family(t *testing.T) { + // Go 1.27's _yvprold table covers the four EVEX immediate rotate + // instructions across X/Y/Z, memory, masks, zeroing, broadcast, high + // registers, and compressed disp8. LLVM 22 verified these bytes. + tests := []struct { + name string + code []byte + want string + }{ + {name: "left dword x high masked", code: []byte{0x62, 0xb1, 0x4d, 0x01, 0x72, 0xcc, 0x06}, want: "VPROLD $6, X20, K1, X22"}, + {name: "left qword y memory zeroing", code: []byte{0x62, 0xd1, 0xed, 0xaa, 0x72, 0x48, 0x03, 0x07}, want: "VPROLQ.Z $7, 96(R8), K2, Y2"}, + {name: "right dword reported minio", code: []byte{0x62, 0xf1, 0x2d, 0x48, 0x72, 0xc4, 0x06}, want: "VPRORD $6, Z4, Z10"}, + {name: "right dword z broadcast high masked", code: []byte{0x62, 0xd1, 0x35, 0x5c, 0x72, 0x44, 0x24, 0x7f, 0x44}, want: "VPRORD.BCST $68, 508(R12), K4, Z9"}, + {name: "right qword z broadcast zeroing", code: []byte{0x62, 0xf1, 0xed, 0xdb, 0x72, 0x40, 0x7f, 0x09}, want: "VPRORQ.BCST.Z $9, 1016(AX), K3, Z2"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86PackedImmediateRotateInstruction(test.code, 64) + if !ok { + t.Fatal("packed immediate rotate encoding was not recognized") + } + if err != nil { + t.Fatal(err) + } + if length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as length=%d raw=%q, want length=%d raw=%q", test.code, length, instruction.Raw, len(test.code), test.want) + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupReportedMinioVPRORD(t *testing.T) { + code := []byte{0x62, 0xf1, 0x2d, 0x48, 0x72, 0xc4, 0x06} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "minio VPRORD", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "VPRORD" || !strings.HasPrefix(decoded[0].Raw, "VPRORD $6, Z4, Z10 ") { + t.Fatalf("decoded reported minio bytes as %#v", decoded) + } +} diff --git a/amd64_raw_vpshift_test.go b/amd64_raw_vpshift_test.go new file mode 100644 index 00000000..45c1e4e7 --- /dev/null +++ b/amd64_raw_vpshift_test.go @@ -0,0 +1,58 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestDecodedX86PackedLogicalShiftCompleteGo127Family(t *testing.T) { + // Go 1.27's _yvpslld table covers six logical shifts with both immediate + // and XMM/m128 uniform-count encodings. These LLVM 22 bytes also cover + // VEX/EVEX, every width, masks, zeroing, broadcast, high registers, and + // compressed disp8. + tests := []struct { + name string + code []byte + want string + }{ + {name: "vex immediate right dword", code: []byte{0xc5, 0xb5, 0x72, 0xd2, 0x07}, want: "VPSRLD $7, Y2, Y9"}, + {name: "vex count left qword memory", code: []byte{0xc4, 0x41, 0x6d, 0xf3, 0x4c, 0x24, 0x20}, want: "VPSLLQ 32(R12), Y2, Y9"}, + {name: "immediate left word", code: []byte{0x62, 0xb1, 0x4d, 0x01, 0x71, 0xf4, 0x06}, want: "VPSLLW $6, X20, K1, X22"}, + {name: "immediate left dword", code: []byte{0x62, 0xd1, 0x6d, 0xaa, 0x72, 0x70, 0x03, 0x07}, want: "VPSLLD.Z $7, 96(R8), K2, Y2"}, + {name: "immediate left qword", code: []byte{0x62, 0xb1, 0xb5, 0x48, 0x73, 0xf1, 0x44}, want: "VPSLLQ $68, Z17, Z9"}, + {name: "immediate right word", code: []byte{0x62, 0xd1, 0x35, 0x24, 0x71, 0x54, 0x24, 0x02, 0x0a}, want: "VPSRLW $10, 64(R12), K4, Y25"}, + {name: "immediate right dword reported minio", code: []byte{0x62, 0x91, 0x05, 0x48, 0x72, 0xd6, 0x0a}, want: "VPSRLD $10, Z30, Z15"}, + {name: "immediate right qword broadcast", code: []byte{0x62, 0xf1, 0xed, 0xdb, 0x73, 0x50, 0x7f, 0x09}, want: "VPSRLQ.BCST.Z $9, 1016(AX), K3, Z2"}, + {name: "count left word", code: []byte{0x62, 0xa1, 0x55, 0x01, 0xf1, 0xf4}, want: "VPSLLW X20, X21, K1, X22"}, + {name: "count left dword memory", code: []byte{0x62, 0xd1, 0x75, 0xaa, 0xf2, 0x50, 0x03}, want: "VPSLLD.Z 48(R8), Y1, K2, Y2"}, + {name: "count left qword", code: []byte{0x62, 0x31, 0xfd, 0x40, 0xf3, 0xc9}, want: "VPSLLQ X17, Z16, Z9"}, + {name: "count right word memory", code: []byte{0x62, 0x41, 0x3d, 0x04, 0xd1, 0x4c, 0x24, 0x02}, want: "VPSRLW 32(R12), X24, K4, X25"}, + {name: "count right dword", code: []byte{0x62, 0xa1, 0x55, 0x21, 0xd2, 0xf4}, want: "VPSRLD X20, Y21, K1, Y22"}, + {name: "count right qword memory", code: []byte{0x62, 0xf1, 0xf5, 0xcb, 0xd3, 0x50, 0x7f}, want: "VPSRLQ.Z 2032(AX), Z1, K3, Z2"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86PackedLogicalShiftInstruction(test.code, 64) + if !ok { + t.Fatal("packed logical shift encoding was not recognized") + } + if err != nil { + t.Fatal(err) + } + if length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as length=%d raw=%q, want length=%d raw=%q", test.code, length, instruction.Raw, len(test.code), test.want) + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupReportedMinioVPSRLD(t *testing.T) { + code := []byte{0x62, 0x91, 0x05, 0x48, 0x72, 0xd6, 0x0a} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "minio VPSRLD", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "VPSRLD" || !strings.HasPrefix(decoded[0].Raw, "VPSRLD $10, Z30, Z15 ") { + t.Fatalf("decoded reported minio bytes as %#v", decoded) + } +} diff --git a/amd64_raw_vpshufb_test.go b/amd64_raw_vpshufb_test.go new file mode 100644 index 00000000..fb8282dd --- /dev/null +++ b/amd64_raw_vpshufb_test.go @@ -0,0 +1,50 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestDecodedX86VPSHUFBCompleteGo127Family(t *testing.T) { + // Go 1.27's _yvandnpd table gives VPSHUFB VEX X/Y forms and EVEX + // X/Y/Z forms, including high registers, memory, K masking, zeroing, + // and EVEX compressed disp8 scaling. LLVM 22 verified these bytes. + tests := []struct { + name string + code []byte + want string + }{ + {name: "vex x high destination", code: []byte{0xc4, 0x62, 0x79, 0x00, 0xc1}, want: "VPSHUFB X1, X0, X8"}, + {name: "vex y high memory", code: []byte{0xc4, 0x42, 0x6d, 0x00, 0x4c, 0x24, 0x20}, want: "VPSHUFB 32(R12), Y2, Y9"}, + {name: "evex x high masked", code: []byte{0x62, 0xa2, 0x55, 0x01, 0x00, 0xf4}, want: "VPSHUFB X20, X21, K1, X22"}, + {name: "evex y memory zeroing", code: []byte{0x62, 0xd2, 0x75, 0xaa, 0x00, 0x50, 0x03}, want: "VPSHUFB.Z 96(R8), Y1, K2, Y2"}, + {name: "evex z high", code: []byte{0x62, 0x32, 0x7d, 0x40, 0x00, 0xc9}, want: "VPSHUFB Z17, Z16, Z9"}, + {name: "evex z compressed memory zeroing", code: []byte{0x62, 0xf2, 0x75, 0xcb, 0x00, 0x50, 0x7f}, want: "VPSHUFB.Z 8128(AX), Z1, K3, Z2"}, + {name: "reported minio", code: []byte{0x62, 0xc2, 0x7d, 0x40, 0x00, 0xc3}, want: "VPSHUFB Z11, Z16, Z16"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VPSHUFBInstruction(test.code, 64) + if !ok { + t.Fatal("VPSHUFB encoding was not recognized") + } + if err != nil { + t.Fatal(err) + } + if length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as length=%d raw=%q, want length=%d raw=%q", test.code, length, instruction.Raw, len(test.code), test.want) + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupReportedMinioVPSHUFB(t *testing.T) { + code := []byte{0x62, 0xc2, 0x7d, 0x40, 0x00, 0xc3} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "minio VPSHUFB", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "VPSHUFB" || !strings.HasPrefix(decoded[0].Raw, "VPSHUFB Z11, Z16, Z16 ") { + t.Fatalf("decoded reported minio bytes as %#v", decoded) + } +} diff --git a/amd64_raw_vpternlog_test.go b/amd64_raw_vpternlog_test.go new file mode 100644 index 00000000..c25b2bb4 --- /dev/null +++ b/amd64_raw_vpternlog_test.go @@ -0,0 +1,48 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestDecodedX86TernaryLogicCompleteGo127Family(t *testing.T) { + // Go 1.27 shares _yvalignd between VPTERNLOGD/Q. These LLVM 22 bytes + // cover X/Y/Z, high registers, memory, masks, zeroing, broadcast, and + // compressed disp8 for both lane widths. + tests := []struct { + name string + code []byte + want string + }{ + {name: "dword x high masked", code: []byte{0x62, 0xa3, 0x55, 0x01, 0x25, 0xf4, 0xca}, want: "VPTERNLOGD $202, X20, X21, K1, X22"}, + {name: "qword y memory zeroing", code: []byte{0x62, 0xd3, 0xf5, 0xaa, 0x25, 0x50, 0x03, 0x96}, want: "VPTERNLOGQ.Z $150, 96(R8), Y1, K2, Y2"}, + {name: "dword reported minio", code: []byte{0x62, 0x73, 0x55, 0x48, 0x25, 0xce, 0xca}, want: "VPTERNLOGD $202, Z6, Z5, Z9"}, + {name: "dword z broadcast high masked", code: []byte{0x62, 0x53, 0x7d, 0x54, 0x25, 0x4c, 0x24, 0x7f, 0x44}, want: "VPTERNLOGD.BCST $68, 508(R12), Z16, K4, Z9"}, + {name: "qword z broadcast zeroing", code: []byte{0x62, 0xf3, 0xf5, 0xdb, 0x25, 0x50, 0x7f, 0x09}, want: "VPTERNLOGQ.BCST.Z $9, 1016(AX), Z1, K3, Z2"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86TernaryLogicInstruction(test.code, 64) + if !ok { + t.Fatal("ternary-logic encoding was not recognized") + } + if err != nil { + t.Fatal(err) + } + if length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as length=%d raw=%q, want length=%d raw=%q", test.code, length, instruction.Raw, len(test.code), test.want) + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupReportedMinioVPTERNLOGD(t *testing.T) { + code := []byte{0x62, 0x73, 0x55, 0x48, 0x25, 0xce, 0xca} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "minio VPTERNLOGD", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "VPTERNLOGD" || !strings.HasPrefix(decoded[0].Raw, "VPTERNLOGD $202, Z6, Z5, Z9 ") { + t.Fatalf("decoded reported minio bytes as %#v", decoded) + } +} diff --git a/amd64_raw_vpunpck_test.go b/amd64_raw_vpunpck_test.go new file mode 100644 index 00000000..166dffb4 --- /dev/null +++ b/amd64_raw_vpunpck_test.go @@ -0,0 +1,103 @@ +package plan9asm + +import "testing" + +func TestDecodedX86VPUNPCKInstructionCompleteVEXFamily(t *testing.T) { + for _, test := range []struct { + opcode byte + op Op + }{ + {0x60, "VPUNPCKLBW"}, + {0x61, "VPUNPCKLWD"}, + {0x62, "VPUNPCKLDQ"}, + {0x6c, "VPUNPCKLQDQ"}, + {0x68, "VPUNPCKHBW"}, + {0x69, "VPUNPCKHWD"}, + {0x6a, "VPUNPCKHDQ"}, + {0x6d, "VPUNPCKHQDQ"}, + } { + t.Run(string(test.op), func(t *testing.T) { + code := []byte{0xc5, 0xe9, test.opcode, 0xcb} + instruction, length, ok, err := decodedX86VPUNPCKInstruction(code, 64) + if err != nil { + t.Fatal(err) + } + if !ok { + t.Fatal("encoding was not recognized") + } + if length != len(code) { + t.Fatalf("length = %d, want %d", length, len(code)) + } + if instruction.Op != test.op || instruction.Raw != string(test.op)+" X3, X2, X1" { + t.Fatalf("instruction = %#v", instruction) + } + }) + } + + for _, test := range []struct { + name string + code []byte + want string + }{ + {name: "y_memory", code: []byte{0xc5, 0xed, 0x6d, 0x4e, 0x20}, want: "VPUNPCKHQDQ 32(SI), Y2, Y1"}, + {name: "extended_registers", code: []byte{0xc4, 0x41, 0x41, 0x6d, 0xf7}, want: "VPUNPCKHQDQ X15, X7, X14"}, + } { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VPUNPCKInstruction(test.code, 64) + if err != nil { + t.Fatal(err) + } + if !ok || length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decode = (%#v, %d, %v), want %q", instruction, length, ok, test.want) + } + }) + } +} + +func TestDecodedX86VPUNPCKInstructionRejectsInvalidVEXForms(t *testing.T) { + for _, test := range []struct { + name string + code []byte + mode int + }{ + {name: "truncated_modrm", code: []byte{0xc5, 0xe9, 0x6d}, mode: 64}, + {name: "vex_pp_zero", code: []byte{0xc5, 0xe8, 0x6d, 0xcb}, mode: 64}, + {name: "vex_w_one", code: []byte{0xc4, 0xe1, 0xe9, 0x6d, 0xcb}, mode: 64}, + {name: "extended_register_in_386", code: []byte{0xc4, 0x41, 0x41, 0x6d, 0xf7}, mode: 32}, + {name: "rip_relative", code: []byte{0xc5, 0xe9, 0x6d, 0x0d, 0, 0, 0, 0}, mode: 64}, + } { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86VPUNPCKInstruction(test.code, test.mode) + if !ok { + t.Fatal("VPUNPCK encoding was not recognized") + } + if err == nil { + t.Fatal("invalid encoding was accepted") + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupVPUNPCKSequence(t *testing.T) { + code := []byte{ + 0xc4, 0xc1, 0x41, 0x6d, 0xf7, + 0xc5, 0x41, 0x6c, 0xff, + 0xc4, 0xc1, 0x11, 0x6d, 0xff, + 0xc5, 0x61, 0x6c, 0xfb, + 0xc4, 0xc1, 0x69, 0x6d, 0xd7, + 0xc4, 0x41, 0x09, 0x6c, 0xfe, + 0xc4, 0xc1, 0x61, 0x6d, 0xdf, + } + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "VPUNPCK raw sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 7 { + t.Fatalf("decoded %d instructions, want 7: %#v", len(decoded), decoded) + } + for _, instruction := range decoded { + if instruction.Op != "VPUNPCKHQDQ" && instruction.Op != "VPUNPCKLQDQ" { + t.Fatalf("decoded unexpected op %s", instruction.Op) + } + } +} diff --git a/amd64_raw_vshuff_blocks_test.go b/amd64_raw_vshuff_blocks_test.go new file mode 100644 index 00000000..9a508d67 --- /dev/null +++ b/amd64_raw_vshuff_blocks_test.go @@ -0,0 +1,51 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestDecodedX86Shuffle128BitBlocksCompleteGo127Family(t *testing.T) { + // Go 1.27 shares _yvshuff32x4 across these four instructions. Its + // EVEX-only rows cover Y/Z register or memory sources, high registers, + // K masking, zeroing, scalar broadcast, and compressed disp8 scaling. + tests := []struct { + name string + code []byte + want string + }{ + {name: "f32 y high masked", code: []byte{0x62, 0xa3, 0x55, 0x21, 0x23, 0xf4, 0x06}, want: "VSHUFF32X4 $6, Y20, Y21, K1, Y22"}, + {name: "f32 z memory zeroing", code: []byte{0x62, 0xd3, 0x75, 0xca, 0x23, 0x50, 0x03, 0x07}, want: "VSHUFF32X4.Z $7, 192(R8), Z1, K2, Z2"}, + {name: "f64 reported minio", code: []byte{0x62, 0x23, 0x8d, 0x40, 0x23, 0xc0, 0xee}, want: "VSHUFF64X2 $238, Z16, Z30, Z24"}, + {name: "f64 z broadcast zeroing", code: []byte{0x62, 0xf3, 0xf5, 0xdb, 0x23, 0x50, 0x7f, 0x09}, want: "VSHUFF64X2.BCST.Z $9, 1016(AX), Z1, K3, Z2"}, + {name: "i32 y high memory masked", code: []byte{0x62, 0x43, 0x3d, 0x24, 0x43, 0x4c, 0x24, 0x02, 0x0a}, want: "VSHUFI32X4 $10, 64(R12), Y24, K4, Y25"}, + {name: "i32 z high", code: []byte{0x62, 0x33, 0x7d, 0x40, 0x43, 0xc9, 0x44}, want: "VSHUFI32X4 $68, Z17, Z16, Z9"}, + {name: "i64 y high masked", code: []byte{0x62, 0xa3, 0xd5, 0x21, 0x43, 0xf4, 0x06}, want: "VSHUFI64X2 $6, Y20, Y21, K1, Y22"}, + {name: "i64 z broadcast zeroing", code: []byte{0x62, 0xf3, 0xf5, 0xdb, 0x43, 0x50, 0x7f, 0x09}, want: "VSHUFI64X2.BCST.Z $9, 1016(AX), Z1, K3, Z2"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86Shuffle128BitBlocksInstruction(test.code, 64) + if !ok { + t.Fatal("shuffle-block encoding was not recognized") + } + if err != nil { + t.Fatal(err) + } + if length != len(test.code) || instruction.Raw != test.want { + t.Fatalf("decoded %x as length=%d raw=%q, want length=%d raw=%q", test.code, length, instruction.Raw, len(test.code), test.want) + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupReportedMinioVSHUFF64X2(t *testing.T) { + code := []byte{0x62, 0x23, 0x8d, 0x40, 0x23, 0xc0, 0xee} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "minio VSHUFF64X2", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "VSHUFF64X2" || !strings.HasPrefix(decoded[0].Raw, "VSHUFF64X2 $238, Z16, Z30, Z24 ") { + t.Fatalf("decoded reported minio bytes as %#v", decoded) + } +} diff --git a/amd64_raw_vshufps_test.go b/amd64_raw_vshufps_test.go new file mode 100644 index 00000000..70960c67 --- /dev/null +++ b/amd64_raw_vshufps_test.go @@ -0,0 +1,135 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestDecodedX86VSHUFPSInstructionCompleteVEXForms(t *testing.T) { + tests := []struct { + name string + code []byte + mode int + want string + }{ + {name: "x_register", code: []byte{0xc5, 0x78, 0xc6, 0xc1, 0x44}, mode: 64, want: "VSHUFPS $68, X1, X0, X8"}, + {name: "y_register", code: []byte{0xc5, 0x6c, 0xc6, 0xcb, 0x44}, mode: 64, want: "VSHUFPS $68, Y3, Y2, Y9"}, + {name: "extended_registers", code: []byte{0xc4, 0x41, 0x3c, 0xc6, 0xd1, 0xdd}, mode: 64, want: "VSHUFPS $221, Y9, Y8, Y10"}, + {name: "memory_disp8", code: []byte{0xc5, 0xec, 0xc6, 0x56, 0x20, 0x01}, mode: 64, want: "VSHUFPS $1, 32(SI), Y2, Y2"}, + {name: "pd extended registers", code: []byte{0xc4, 0x41, 0x3d, 0xc6, 0xd1, 0xdd}, mode: 64, want: "VSHUFPD $221, Y9, Y8, Y10"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VSHUFPSInstruction(test.code, test.mode) + if err != nil { + t.Fatal(err) + } + if !ok { + t.Fatal("encoding was not recognized") + } + if length != len(test.code) { + t.Fatalf("length = %d, want %d", length, len(test.code)) + } + if instruction.Raw != test.want { + t.Fatalf("instruction = %q, want %q", instruction.Raw, test.want) + } + }) + } +} + +func TestDecodedX86PackedFloatShuffleCompleteEVEXFamily(t *testing.T) { + // Go 1.27 assigns VSHUFPS and VSHUFPD the shared + // _yvgf2p8affineinvqb table. Its EVEX rows cover X/Y/Z register or + // memory sources, high registers, K masking, zeroing, and scalar + // broadcast. The byte sequences below are verified by LLVM 22. + tests := []struct { + name string + code []byte + want string + }{ + {name: "ps x high masked", code: []byte{0x62, 0xa1, 0x54, 0x01, 0xc6, 0xf4, 0x06}, want: "VSHUFPS $6, X20, X21, K1, X22"}, + {name: "ps y memory zeroing", code: []byte{0x62, 0xd1, 0x74, 0xaa, 0xc6, 0x50, 0x03, 0x07}, want: "VSHUFPS.Z $7, 96(R8), Y1, K2, Y2"}, + {name: "ps z high", code: []byte{0x62, 0x31, 0x7c, 0x40, 0xc6, 0xc9, 0x44}, want: "VSHUFPS $68, Z17, Z16, Z9"}, + {name: "ps z broadcast zeroing", code: []byte{0x62, 0xf1, 0x74, 0xdb, 0xc6, 0x50, 0x7f, 0x09}, want: "VSHUFPS.BCST.Z $9, 508(AX), Z1, K3, Z2"}, + {name: "pd x high masked", code: []byte{0x62, 0xa1, 0xd5, 0x01, 0xc6, 0xf4, 0x06}, want: "VSHUFPD $6, X20, X21, K1, X22"}, + {name: "pd y memory zeroing", code: []byte{0x62, 0xd1, 0xf5, 0xaa, 0xc6, 0x50, 0x03, 0x07}, want: "VSHUFPD.Z $7, 96(R8), Y1, K2, Y2"}, + {name: "pd z high", code: []byte{0x62, 0x31, 0xfd, 0x40, 0xc6, 0xc9, 0x44}, want: "VSHUFPD $68, Z17, Z16, Z9"}, + {name: "pd z broadcast zeroing", code: []byte{0x62, 0xf1, 0xf5, 0xdb, 0xc6, 0x50, 0x7f, 0x09}, want: "VSHUFPD.BCST.Z $9, 1016(AX), Z1, K3, Z2"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + instruction, length, ok, err := decodedX86VSHUFPSInstruction(test.code, 64) + if !ok { + t.Fatal("packed float shuffle encoding was not recognized") + } + if err != nil { + t.Fatal(err) + } + if length != len(test.code) { + t.Fatalf("decoded length = %d, want %d", length, len(test.code)) + } + if instruction.Raw != test.want { + t.Fatalf("decoded %x as %q, want %q", test.code, instruction.Raw, test.want) + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupReportedMinioEVEXVSHUFPS(t *testing.T) { + code := []byte{0x62, 0x31, 0x7c, 0x40, 0xc6, 0xc9, 0x44} + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "minio EVEX VSHUFPS", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 1 || decoded[0].Op != "VSHUFPS" || !strings.HasPrefix(decoded[0].Raw, "VSHUFPS $68, Z17, Z16, Z9 ") { + t.Fatalf("decoded reported minio bytes as %#v", decoded) + } +} + +func TestDecodedX86VSHUFPSInstructionRejectsInvalidVEXForms(t *testing.T) { + tests := []struct { + name string + code []byte + mode int + }{ + {name: "truncated_modrm", code: []byte{0xc5, 0x7c, 0xc6}, mode: 64}, + {name: "truncated_immediate", code: []byte{0xc5, 0x7c, 0xc6, 0xc1}, mode: 64}, + {name: "vex_pp_f3", code: []byte{0xc5, 0x7e, 0xc6, 0xc1, 0x44}, mode: 64}, + {name: "vex_w_one", code: []byte{0xc4, 0xe1, 0xbc, 0xc6, 0xc1, 0x44}, mode: 64}, + {name: "extended_register_in_386", code: []byte{0xc5, 0x78, 0xc6, 0xc1, 0x44}, mode: 32}, + {name: "rip_relative", code: []byte{0xc5, 0xfc, 0xc6, 0x05, 0, 0, 0, 0, 0x44}, mode: 64}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + _, _, ok, err := decodedX86VSHUFPSInstruction(test.code, test.mode) + if !ok { + t.Fatal("VSHUFPS encoding was not recognized") + } + if err == nil { + t.Fatal("invalid encoding was accepted") + } + }) + } +} + +func TestDecodeX86RawDirectiveGroupVSHUFPSSequence(t *testing.T) { + code := []byte{ + 0xc5, 0x7c, 0xc6, 0xc1, 0x44, + 0xc5, 0xfc, 0xc6, 0xc1, 0xee, + 0xc5, 0x6c, 0xc6, 0xcb, 0x44, + 0xc5, 0xec, 0xc6, 0xd3, 0xee, + 0xc4, 0xc1, 0x3c, 0xc6, 0xd9, 0xdd, + } + decoded, err := decodeX86RawDirectiveGroup(code, 64, 0, "VSHUFPS raw sequence", map[string]bool{}) + if err != nil { + t.Fatal(err) + } + if len(decoded) != 5 { + t.Fatalf("decoded %d instructions, want 5: %#v", len(decoded), decoded) + } + for _, instruction := range decoded { + if instruction.Op != "VSHUFPS" { + t.Fatalf("decoded op = %s, want VSHUFPS", instruction.Op) + } + } +} diff --git a/amd64_tailcall_aggregate_test.go b/amd64_tailcall_aggregate_test.go new file mode 100644 index 00000000..5c2b2f2a --- /dev/null +++ b/amd64_tailcall_aggregate_test.go @@ -0,0 +1,107 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestAMD64TailCallAdaptsABIEquivalentAggregateReturns(t *testing.T) { + tests := []struct { + name string + callerRet LLVMType + calleeRet LLVMType + cast string + }{ + { + name: "integer slot to pointer slot", + callerRet: LLVMType("{ i64, ptr }"), + calleeRet: LLVMType("{ i64, i64 }"), + cast: "inttoptr i64", + }, + { + name: "pointer slot to integer slot", + callerRet: LLVMType("{ i64, i64 }"), + calleeRet: LLVMType("{ i64, ptr }"), + cast: "ptrtoint ptr", + }, + } + + for _, tt := range tests { + t.Run(tt.name, func(t *testing.T) { + caller := FuncSig{Name: "example.wrapper", Args: []LLVMType{Ptr}, Ret: tt.callerRet} + callee := FuncSig{Name: "example.words", Args: []LLVMType{Ptr}, Ret: tt.calleeRet} + c, b := newAMD64CtxWithFuncForTest(t, Func{}, caller, map[string]FuncSig{ + "example.words": callee, + }) + + if err := c.tailCallAndRet(Operand{Kind: OpSym, Sym: "words(SB)"}); err != nil { + t.Fatalf("tailCallAndRet() error = %v", err) + } + got := b.String() + for _, want := range []string{ + "call " + string(tt.calleeRet) + " @\"example.words\"(ptr %arg0)", + "extractvalue " + string(tt.calleeRet), + tt.cast, + "insertvalue " + string(tt.callerRet), + "ret " + string(tt.callerRet), + } { + if !strings.Contains(got, want) { + t.Fatalf("tailCallAndRet() missing %q:\n%s", want, got) + } + } + }) + } +} + +func TestAMD64TailCallRejectsABIIncompatibleAggregateReturns(t *testing.T) { + tests := []struct { + name string + callerRet LLVMType + calleeRet LLVMType + }{ + {name: "different field count", callerRet: LLVMType("{ i64, ptr }"), calleeRet: LLVMType("{ i64 }")}, + {name: "floating slot", callerRet: LLVMType("{ i64, ptr }"), calleeRet: LLVMType("{ i64, double }")}, + {name: "different integer width", callerRet: LLVMType("{ i64, ptr }"), calleeRet: LLVMType("{ i64, i32 }")}, + } + + for _, tt := range tests { + t.Run(tt.name, func(t *testing.T) { + caller := FuncSig{Name: "example.wrapper", Args: []LLVMType{Ptr}, Ret: tt.callerRet} + callee := FuncSig{Name: "example.words", Args: []LLVMType{Ptr}, Ret: tt.calleeRet} + c, _ := newAMD64CtxWithFuncForTest(t, Func{}, caller, map[string]FuncSig{ + "example.words": callee, + }) + + if err := c.tailCallAndRet(Operand{Kind: OpSym, Sym: "words(SB)"}); err == nil { + t.Fatal("tailCallAndRet() unexpectedly accepted ABI-incompatible aggregate returns") + } + }) + } +} + +func Test386TailCallAdaptsABIEquivalentAggregateReturns(t *testing.T) { + caller := FuncSig{Name: "example.wrapper", Args: []LLVMType{Ptr}, Ret: LLVMType("{ i32, ptr }")} + callee := FuncSig{Name: "example.words", Args: []LLVMType{Ptr}, Ret: LLVMType("{ i32, i32 }")} + var b strings.Builder + c := newX86Ctx(&b, Func{}, caller, testResolveSym("example"), map[string]FuncSig{ + "example.words": callee, + }, "386", "i386-unknown-linux-gnu", false) + if err := c.emitEntryAllocas(); err != nil { + t.Fatalf("emitEntryAllocas() error = %v", err) + } + + if err := c.tailCallAndRet(Operand{Kind: OpSym, Sym: "words(SB)"}); err != nil { + t.Fatalf("tailCallAndRet() error = %v", err) + } + got := b.String() + for _, want := range []string{ + "call { i32, i32 } @\"example.words\"(ptr %arg0)", + "inttoptr i32", + "insertvalue { i32, ptr }", + "ret { i32, ptr }", + } { + if !strings.Contains(got, want) { + t.Fatalf("tailCallAndRet() missing %q:\n%s", want, got) + } + } +} diff --git a/amd64_translate.go b/amd64_translate.go index 64ae5abe..2a72fdaf 100644 --- a/amd64_translate.go +++ b/amd64_translate.go @@ -14,18 +14,149 @@ func emitAMD64Prelude(b *strings.Builder, goarch string, file *File) { // Generic LLVM intrinsics used by amd64 lowering. b.WriteString("declare i64 @llvm.cttz.i64(i64, i1)\n") b.WriteString("declare i32 @llvm.cttz.i32(i32, i1)\n") + b.WriteString("declare i16 @llvm.cttz.i16(i16, i1)\n") b.WriteString("declare i64 @llvm.ctlz.i64(i64, i1)\n") b.WriteString("declare i32 @llvm.ctlz.i32(i32, i1)\n") + b.WriteString("declare i16 @llvm.ctlz.i16(i16, i1)\n") b.WriteString("declare i64 @llvm.ctpop.i64(i64)\n") b.WriteString("declare i32 @llvm.ctpop.i32(i32)\n") + b.WriteString("declare i16 @llvm.ctpop.i16(i16)\n") + b.WriteString("declare i32 @llvm.x86.rdpid()\n") + b.WriteString("declare i32 @llvm.x86.xbegin()\n") + b.WriteString("declare void @llvm.x86.xabort(i8 immarg)\n") + b.WriteString("declare void @llvm.x86.xend()\n") + b.WriteString("declare i32 @llvm.x86.xtest()\n") + for _, family := range []string{"rdrand", "rdseed"} { + for _, bits := range []int{16, 32, 64} { + fmt.Fprintf(b, "declare { i%d, i32 } @llvm.x86.%s.%d()\n", bits, family, bits) + } + } + for _, laneBits := range []int{8, 16, 32, 64} { + for _, byteWidth := range []int{16, 32, 64} { + lanes := byteWidth * 8 / laneBits + fmt.Fprintf(b, "declare <%d x i%d> @llvm.ctpop.v%di%d(<%d x i%d>)\n", lanes, laneBits, lanes, laneBits, lanes, laneBits) + fmt.Fprintf(b, "declare <%d x i%d> @llvm.ctlz.v%di%d(<%d x i%d>, i1)\n", lanes, laneBits, lanes, laneBits, lanes, laneBits) + fmt.Fprintf(b, "declare <%d x i%d> @llvm.experimental.vector.compress.v%di%d(<%d x i%d>, <%d x i1>, <%d x i%d>)\n", lanes, laneBits, lanes, laneBits, lanes, laneBits, lanes, lanes, laneBits) + fmt.Fprintf(b, "declare void @llvm.masked.compressstore.v%di%d(<%d x i%d>, ptr, <%d x i1>)\n", lanes, laneBits, lanes, laneBits, lanes) + fmt.Fprintf(b, "declare void @llvm.masked.compressstore.v%di%d.p256(<%d x i%d>, ptr addrspace(256), <%d x i1>)\n", lanes, laneBits, lanes, laneBits, lanes) + fmt.Fprintf(b, "declare void @llvm.masked.compressstore.v%di%d.p257(<%d x i%d>, ptr addrspace(257), <%d x i1>)\n", lanes, laneBits, lanes, laneBits, lanes) + fmt.Fprintf(b, "declare <%d x i%d> @llvm.masked.expandload.v%di%d(ptr, <%d x i1>, <%d x i%d>)\n", lanes, laneBits, lanes, laneBits, lanes, lanes, laneBits) + fmt.Fprintf(b, "declare <%d x i%d> @llvm.masked.expandload.v%di%d.p256(ptr addrspace(256), <%d x i1>, <%d x i%d>)\n", lanes, laneBits, lanes, laneBits, lanes, lanes, laneBits) + fmt.Fprintf(b, "declare <%d x i%d> @llvm.masked.expandload.v%di%d.p257(ptr addrspace(257), <%d x i1>, <%d x i%d>)\n", lanes, laneBits, lanes, laneBits, lanes, lanes, laneBits) + if laneBits >= 16 { + vectorType := fmt.Sprintf("<%d x i%d>", lanes, laneBits) + fmt.Fprintf(b, "declare %s @llvm.fshl.v%di%d(%s, %s, %s)\n", vectorType, lanes, laneBits, vectorType, vectorType, vectorType) + fmt.Fprintf(b, "declare %s @llvm.fshr.v%di%d(%s, %s, %s)\n", vectorType, lanes, laneBits, vectorType, vectorType, vectorType) + } + } + } b.WriteString("declare i64 @llvm.bswap.i64(i64)\n") b.WriteString("declare i32 @llvm.bswap.i32(i32)\n") + b.WriteString("declare i16 @llvm.bswap.i16(i16)\n") + b.WriteString("declare float @llvm.sqrt.f32(float)\n") b.WriteString("declare double @llvm.sqrt.f64(double)\n") + b.WriteString("declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)\n") + b.WriteString("declare <8 x float> @llvm.sqrt.v8f32(<8 x float>)\n") + b.WriteString("declare <16 x float> @llvm.sqrt.v16f32(<16 x float>)\n") + b.WriteString("declare <2 x double> @llvm.sqrt.v2f64(<2 x double>)\n") + b.WriteString("declare <4 x double> @llvm.sqrt.v4f64(<4 x double>)\n") + b.WriteString("declare <8 x double> @llvm.sqrt.v8f64(<8 x double>)\n") + b.WriteString("declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>)\n") + b.WriteString("declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>)\n") + b.WriteString("declare <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float>)\n") + b.WriteString("declare <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float>)\n") + b.WriteString("declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i8 immarg)\n") + b.WriteString("declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i8 immarg)\n") + b.WriteString("declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i8 immarg)\n") + b.WriteString("declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i8 immarg)\n") + b.WriteString("declare <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8>, <32 x i8>, i8 immarg)\n") + b.WriteString("declare i32 @llvm.x86.sse42.pcmpestri128(<16 x i8>, i32, <16 x i8>, i32, i8 immarg)\n") + b.WriteString("declare <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8>, i32, <16 x i8>, i32, i8 immarg)\n") + b.WriteString("declare i32 @llvm.x86.sse42.pcmpistri128(<16 x i8>, <16 x i8>, i8 immarg)\n") + b.WriteString("declare <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8>, <16 x i8>, i8 immarg)\n") + for _, family := range []string{"pcmpestri", "pcmpistri"} { + for _, flag := range []string{"c", "o", "s", "z"} { + if family == "pcmpestri" { + fmt.Fprintf(b, "declare i32 @llvm.x86.sse42.%s%s128(<16 x i8>, i32, <16 x i8>, i32, i8 immarg)\n", family, flag) + } else { + fmt.Fprintf(b, "declare i32 @llvm.x86.sse42.%s%s128(<16 x i8>, <16 x i8>, i8 immarg)\n", family, flag) + } + } + } + for _, family := range []string{"rcp14", "rsqrt14"} { + for _, vector := range []struct { + kind string + bits int + lanes int + laneType string + maskType string + }{ + {kind: "ps", bits: 128, lanes: 4, laneType: "float", maskType: "i8"}, + {kind: "ps", bits: 256, lanes: 8, laneType: "float", maskType: "i8"}, + {kind: "ps", bits: 512, lanes: 16, laneType: "float", maskType: "i16"}, + {kind: "pd", bits: 128, lanes: 2, laneType: "double", maskType: "i8"}, + {kind: "pd", bits: 256, lanes: 4, laneType: "double", maskType: "i8"}, + {kind: "pd", bits: 512, lanes: 8, laneType: "double", maskType: "i8"}, + } { + typ := fmt.Sprintf("<%d x %s>", vector.lanes, vector.laneType) + fmt.Fprintf(b, "declare %s @llvm.x86.avx512.%s.%s.%d(%s, %s, %s)\n", typ, family, vector.kind, vector.bits, typ, typ, vector.maskType) + } + for _, scalar := range []struct { + kind string + lanes int + laneType string + }{ + {kind: "ss", lanes: 4, laneType: "float"}, + {kind: "sd", lanes: 2, laneType: "double"}, + } { + typ := fmt.Sprintf("<%d x %s>", scalar.lanes, scalar.laneType) + fmt.Fprintf(b, "declare %s @llvm.x86.avx512.%s.%s(%s, %s, %s, i8)\n", typ, family, scalar.kind, typ, typ, typ) + } + } + for _, declaration := range []string{ + "float @llvm.fma.f32(float, float, float)", + "double @llvm.fma.f64(double, double, double)", + "<4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)", + "<8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>)", + "<16 x float> @llvm.fma.v16f32(<16 x float>, <16 x float>, <16 x float>)", + "<2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)", + "<4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>)", + "<8 x double> @llvm.fma.v8f64(<8 x double>, <8 x double>, <8 x double>)", + } { + b.WriteString("declare " + declaration + "\n") + } + for _, declaration := range []string{ + "float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)", + "double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata)", + "<16 x float> @llvm.experimental.constrained.fma.v16f32(<16 x float>, <16 x float>, <16 x float>, metadata, metadata)", + "<8 x double> @llvm.experimental.constrained.fma.v8f64(<8 x double>, <8 x double>, <8 x double>, metadata, metadata)", + } { + b.WriteString("declare " + declaration + "\n") + } + for _, operation := range []string{"fadd", "fsub", "fmul", "fdiv"} { + for _, signature := range []string{ + "float @llvm.experimental.constrained.%s.f32(float, float, metadata, metadata)", + "double @llvm.experimental.constrained.%s.f64(double, double, metadata, metadata)", + "<16 x float> @llvm.experimental.constrained.%s.v16f32(<16 x float>, <16 x float>, metadata, metadata)", + "<8 x double> @llvm.experimental.constrained.%s.v8f64(<8 x double>, <8 x double>, metadata, metadata)", + } { + b.WriteString("declare " + fmt.Sprintf(signature, operation) + "\n") + } + } b.WriteString("declare double @llvm.rint.f64(double)\n") + b.WriteString("declare double @llvm.roundeven.f64(double)\n") + b.WriteString("declare double @llvm.floor.f64(double)\n") + b.WriteString("declare double @llvm.ceil.f64(double)\n") + b.WriteString("declare double @llvm.trunc.f64(double)\n") + b.WriteString("declare double @llvm.sin.f64(double)\n") + b.WriteString("declare double @llvm.cos.f64(double)\n") + b.WriteString("declare double @llvm.exp2.f64(double)\n") + b.WriteString("declare double @llvm.log2.f64(double)\n") + b.WriteString("declare double @atan2(double, double)\n") + b.WriteString("declare double @fmod(double, double)\n") + b.WriteString("declare double @remainder(double, double)\n") + b.WriteString("declare double @tan(double)\n") if goarch == "386" { - b.WriteString("declare double @llvm.floor.f64(double)\n") - b.WriteString("declare double @llvm.ceil.f64(double)\n") - b.WriteString("declare double @llvm.trunc.f64(double)\n") b.WriteString("declare double @llvm.fabs.f64(double)\n") } b.WriteString("declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)\n") @@ -35,6 +166,42 @@ func emitAMD64Prelude(b *strings.Builder, goarch string, file *File) { b.WriteString("declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>)\n") b.WriteString("declare <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64>)\n") b.WriteString("declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8 immarg)\n") + b.WriteString("declare void @llvm.x86.sse.ldmxcsr(ptr)\n") + b.WriteString("declare void @llvm.x86.sse.stmxcsr(ptr)\n") + b.WriteString("declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>)\n") + b.WriteString("declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>)\n") + b.WriteString("declare <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float>)\n") + b.WriteString("declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>)\n") + b.WriteString("declare <16 x float> @llvm.experimental.constrained.sitofp.v16f32.v16i32(<16 x i32>, metadata, metadata)\n") + b.WriteString("declare <8 x float> @llvm.experimental.constrained.fptrunc.v8f32.v8f64(<8 x double>, metadata, metadata)\n") + for _, lanes := range []int{4, 8, 16} { + fmt.Fprintf(b, "declare <%d x half> @llvm.experimental.constrained.fptrunc.v%df16.v%df32(<%d x float>, metadata, metadata)\n", lanes, lanes, lanes, lanes) + } + b.WriteString("declare float @llvm.rint.f32(float)\n") + b.WriteString("declare float @llvm.roundeven.f32(float)\n") + b.WriteString("declare float @llvm.trunc.f32(float)\n") + b.WriteString("declare float @llvm.floor.f32(float)\n") + b.WriteString("declare float @llvm.ceil.f32(float)\n") + b.WriteString("declare <16 x float> @llvm.experimental.constrained.sqrt.v16f32(<16 x float>, metadata, metadata)\n") + b.WriteString("declare <8 x double> @llvm.experimental.constrained.sqrt.v8f64(<8 x double>, metadata, metadata)\n") + b.WriteString("declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)\n") + b.WriteString("declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata)\n") + b.WriteString("declare i32 @llvm.fptosi.sat.i32.f32(float)\n") + b.WriteString("declare i32 @llvm.fptosi.sat.i32.f64(double)\n") + for _, conversion := range []struct { + name string + resultType string + sourceType string + }{ + {name: "fptoui.sat.i32.f32", resultType: "i32", sourceType: "float"}, + {name: "fptoui.sat.i32.f64", resultType: "i32", sourceType: "double"}, + {name: "fptosi.sat.i64.f32", resultType: "i64", sourceType: "float"}, + {name: "fptosi.sat.i64.f64", resultType: "i64", sourceType: "double"}, + {name: "fptoui.sat.i64.f32", resultType: "i64", sourceType: "float"}, + {name: "fptoui.sat.i64.f64", resultType: "i64", sourceType: "double"}, + } { + fmt.Fprintf(b, "declare %s @llvm.%s(%s)\n", conversion.resultType, conversion.name, conversion.sourceType) + } b.WriteString("\n") // x86-64 CRC32 (SSE4.2) and PCLMULQDQ intrinsics. b.WriteString("declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64)\n") @@ -44,39 +211,85 @@ func emitAMD64Prelude(b *strings.Builder, goarch string, file *File) { b.WriteString("declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8 immarg)\n") // SSE2 helpers used by stdlib asm (e.g. internal/bytealg). b.WriteString("declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>)\n") + b.WriteString("declare void @llvm.masked.store.v8i8.p0(<8 x i8>, ptr nocapture, i32 immarg, <8 x i1>)\n") + b.WriteString("declare void @llvm.masked.store.v16i8.p0(<16 x i8>, ptr nocapture, i32 immarg, <16 x i1>)\n") + for _, shape := range []struct{ lanes, bits int }{{4, 32}, {8, 32}, {2, 64}, {4, 64}} { + for _, addressSpace := range []struct { + suffix, pointer string + }{{".p0", "ptr"}, {".p256", "ptr addrspace(256)"}, {".p257", "ptr addrspace(257)"}} { + fmt.Fprintf(b, "declare <%d x i%d> @llvm.masked.load.v%di%d%s(%s, <%d x i1>, <%d x i%d>)\n", shape.lanes, shape.bits, shape.lanes, shape.bits, addressSpace.suffix, addressSpace.pointer, shape.lanes, shape.lanes, shape.bits) + fmt.Fprintf(b, "declare void @llvm.masked.store.v%di%d%s(<%d x i%d>, %s, <%d x i1>)\n", shape.lanes, shape.bits, addressSpace.suffix, shape.lanes, shape.bits, addressSpace.pointer, shape.lanes) + } + } b.WriteString("\n") b.WriteString("\n") - if goarch == "386" { - emit386StringHelpers(b, file) - } + emitX86StringHelpers(b, file) } -func emit386StringHelpers(b *strings.Builder, file *File) { - needMOVSB, needMOVSL, needSTOSL, needSCASB := false, false, false, false +func emitX86StringHelpers(b *strings.Builder, file *File) { + needed := make(map[string]struct{}) for _, fn := range file.Funcs { for _, ins := range fn.Instrs { - switch strings.ToUpper(string(ins.Op)) { - case "MOVSB": - needMOVSB = true - case "MOVSL": - needMOVSL = true - case "STOSL": - needSTOSL = true - case "SCASB": - needSCASB = true + kind, typ, width, ok := x86StringProperties(ins.Op) + if !ok { + continue + } + name := x86StringHelperName(kind, width) + if _, ok := needed[name]; ok { + continue + } + needed[name] = struct{}{} + switch kind { + case "movs": + emitX86MOVSHelper(b, name, string(typ), width) + case "stos": + emitX86STOSHelper(b, name, string(typ), width) + case "scas": + emitX86SCASHelper(b, name, string(typ), width) + case "cmps": + emitX86CMPSHelper(b, name, string(typ), width) + case "lods": + emitX86LODSHelper(b, name, string(typ), width) } } } - if needMOVSB { - emit386MOVSHelper(b, "__plan9asm_movsb", "i8", 1) - } - if needMOVSL { - emit386MOVSHelper(b, "__plan9asm_movsl", "i32", 4) - } - if needSTOSL { - b.WriteString(`define internal void @__plan9asm_rep_stosl(i64 %addr, i32 %value, i64 %count, i1 %backward) { -entry: +} + +func emitX86MOVSHelper(b *strings.Builder, name, ty string, width int) { + fmt.Fprintf(b, "define internal void @%s(i64 %%dst, i64 %%src, i64 %%count, i1 %%backward) {\n", name) + b.WriteString(`entry: + %step = select i1 %backward, i64 `) + fmt.Fprintf(b, "-%d, i64 %d\n", width, width) + b.WriteString(` br label %loop +loop: + %cur_dst = phi i64 [ %dst, %entry ], [ %next_dst, %body ] + %cur_src = phi i64 [ %src, %entry ], [ %next_src, %body ] + %left = phi i64 [ %count, %entry ], [ %remaining, %body ] + %done = icmp eq i64 %left, 0 + br i1 %done, label %exit, label %body +body: + %dst_ptr = inttoptr i64 %cur_dst to ptr + %src_ptr = inttoptr i64 %cur_src to ptr +`) + fmt.Fprintf(b, " %%value = load %s, ptr %%src_ptr, align 1\n", ty) + fmt.Fprintf(b, " store %s %%value, ptr %%dst_ptr, align 1\n", ty) + b.WriteString(` %next_dst = add i64 %cur_dst, %step + %next_src = add i64 %cur_src, %step + %remaining = sub i64 %left, 1 br label %loop +exit: + ret void +} + +`) +} + +func emitX86STOSHelper(b *strings.Builder, name, typ string, width int) { + fmt.Fprintf(b, "define internal void @%s(i64 %%addr, %s %%value, i64 %%count, i1 %%backward) {\n", name, typ) + b.WriteString(`entry: + %step = select i1 %backward, i64 `) + fmt.Fprintf(b, "-%d, i64 %d\n", width, width) + b.WriteString(` br label %loop loop: %cur = phi i64 [ %addr, %entry ], [ %next, %body ] %left = phi i64 [ %count, %entry ], [ %remaining, %body ] @@ -84,9 +297,9 @@ loop: br i1 %done, label %exit, label %body body: %ptr = inttoptr i64 %cur to ptr - store i32 %value, ptr %ptr, align 1 - %step = select i1 %backward, i64 -4, i64 4 - %next = add i64 %cur, %step +`) + fmt.Fprintf(b, " store %s %%value, ptr %%ptr, align 1\n", typ) + b.WriteString(` %next = add i64 %cur, %step %remaining = sub i64 %left, 1 br label %loop exit: @@ -94,77 +307,166 @@ exit: } `) - } - if needSCASB { - b.WriteString(`define internal { i64, i64, i1 } @__plan9asm_repne_scasb(i64 %addr, i8 %needle, i64 %count, i1 %backward) { -entry: - br label %loop +} + +func emitX86SCASHelper(b *strings.Builder, name, typ string, width int) { + fmt.Fprintf(b, "define internal { i64, i64, i1 } @%s(i64 %%addr, %s %%needle, i64 %%count, i1 %%backward, i1 %%while_equal) {\n", name, typ) + b.WriteString(`entry: + %step = select i1 %backward, i64 `) + fmt.Fprintf(b, "-%d, i64 %d\n", width, width) + b.WriteString(` br label %loop loop: - %cur = phi i64 [ %addr, %entry ], [ %next, %miss ] - %left = phi i64 [ %count, %entry ], [ %remaining, %miss ] + %cur = phi i64 [ %addr, %entry ], [ %scan_next, %scan ] + %left = phi i64 [ %count, %entry ], [ %scan_remaining, %scan ] %empty = icmp eq i64 %left, 0 - br i1 %empty, label %not_found, label %scan + br i1 %empty, label %empty_exit, label %scan scan: %ptr = inttoptr i64 %cur to ptr - %value = load i8, ptr %ptr, align 1 - %equal = icmp eq i8 %value, %needle - %step = select i1 %backward, i64 -1, i64 1 +`) + fmt.Fprintf(b, " %%value = load %s, ptr %%ptr, align 1\n", typ) + fmt.Fprintf(b, " %%equal = icmp eq %s %%value, %%needle\n", typ) + b.WriteString(` %not_equal = xor i1 %equal, true + %repeat_condition = select i1 %while_equal, i1 %equal, i1 %not_equal %scan_next = add i64 %cur, %step %scan_remaining = sub i64 %left, 1 - br i1 %equal, label %found, label %miss -miss: - %next = phi i64 [ %scan_next, %scan ] - %remaining = phi i64 [ %scan_remaining, %scan ] - br label %loop -found: - %found0 = insertvalue { i64, i64, i1 } undef, i64 %scan_next, 0 - %found1 = insertvalue { i64, i64, i1 } %found0, i64 %scan_remaining, 1 - %found2 = insertvalue { i64, i64, i1 } %found1, i1 true, 2 - ret { i64, i64, i1 } %found2 -not_found: - %miss0 = insertvalue { i64, i64, i1 } undef, i64 %cur, 0 - %miss1 = insertvalue { i64, i64, i1 } %miss0, i64 %left, 1 - %miss2 = insertvalue { i64, i64, i1 } %miss1, i1 false, 2 - ret { i64, i64, i1 } %miss2 + %more = icmp ne i64 %scan_remaining, 0 + %continue = and i1 %repeat_condition, %more + br i1 %continue, label %loop, label %done +done: + %done0 = insertvalue { i64, i64, i1 } undef, i64 %scan_next, 0 + %done1 = insertvalue { i64, i64, i1 } %done0, i64 %scan_remaining, 1 + %done2 = insertvalue { i64, i64, i1 } %done1, i1 %equal, 2 + ret { i64, i64, i1 } %done2 +empty_exit: + %empty0 = insertvalue { i64, i64, i1 } undef, i64 %cur, 0 + %empty1 = insertvalue { i64, i64, i1 } %empty0, i64 %left, 1 + %empty2 = insertvalue { i64, i64, i1 } %empty1, i1 false, 2 + ret { i64, i64, i1 } %empty2 } `) - } } -func emit386MOVSHelper(b *strings.Builder, name, ty string, width int) { - fmt.Fprintf(b, "define internal void @%s(i64 %%dst, i64 %%src, i64 %%count, i1 %%backward) {\n", name) +func emitX86CMPSHelper(b *strings.Builder, name, typ string, width int) { + resultType := fmt.Sprintf("{ i64, i64, i64, %s, %s, i1 }", typ, typ) + fmt.Fprintf(b, "define internal %s @%s(i64 %%src, i64 %%dst, i64 %%count, i1 %%backward, i1 %%while_equal) {\n", resultType, name) b.WriteString(`entry: %step = select i1 %backward, i64 `) fmt.Fprintf(b, "-%d, i64 %d\n", width, width) b.WriteString(` br label %loop loop: - %cur_dst = phi i64 [ %dst, %entry ], [ %next_dst, %body ] - %cur_src = phi i64 [ %src, %entry ], [ %next_src, %body ] - %left = phi i64 [ %count, %entry ], [ %remaining, %body ] - %done = icmp eq i64 %left, 0 - br i1 %done, label %exit, label %body -body: - %dst_ptr = inttoptr i64 %cur_dst to ptr + %cur_src = phi i64 [ %src, %entry ], [ %next_src, %scan ] + %cur_dst = phi i64 [ %dst, %entry ], [ %next_dst, %scan ] + %left = phi i64 [ %count, %entry ], [ %remaining, %scan ] + %empty = icmp eq i64 %left, 0 + br i1 %empty, label %empty_exit, label %scan +scan: %src_ptr = inttoptr i64 %cur_src to ptr + %dst_ptr = inttoptr i64 %cur_dst to ptr `) - fmt.Fprintf(b, " %%value = load %s, ptr %%src_ptr, align 1\n", ty) - fmt.Fprintf(b, " store %s %%value, ptr %%dst_ptr, align 1\n", ty) - b.WriteString(` %next_dst = add i64 %cur_dst, %step + fmt.Fprintf(b, " %%src_value = load %s, ptr %%src_ptr, align 1\n", typ) + fmt.Fprintf(b, " %%dst_value = load %s, ptr %%dst_ptr, align 1\n", typ) + fmt.Fprintf(b, " %%equal = icmp eq %s %%src_value, %%dst_value\n", typ) + b.WriteString(` %not_equal = xor i1 %equal, true + %repeat_condition = select i1 %while_equal, i1 %equal, i1 %not_equal %next_src = add i64 %cur_src, %step + %next_dst = add i64 %cur_dst, %step %remaining = sub i64 %left, 1 - br label %loop -exit: - ret void + %more = icmp ne i64 %remaining, 0 + %continue = and i1 %repeat_condition, %more + br i1 %continue, label %loop, label %done +done: +`) + fmt.Fprintf(b, " %%done0 = insertvalue %s undef, i64 %%next_src, 0\n", resultType) + fmt.Fprintf(b, " %%done1 = insertvalue %s %%done0, i64 %%next_dst, 1\n", resultType) + fmt.Fprintf(b, " %%done2 = insertvalue %s %%done1, i64 %%remaining, 2\n", resultType) + fmt.Fprintf(b, " %%done3 = insertvalue %s %%done2, %s %%src_value, 3\n", resultType, typ) + fmt.Fprintf(b, " %%done4 = insertvalue %s %%done3, %s %%dst_value, 4\n", resultType, typ) + fmt.Fprintf(b, " %%done5 = insertvalue %s %%done4, i1 true, 5\n", resultType) + fmt.Fprintf(b, " ret %s %%done5\n", resultType) + b.WriteString("empty_exit:\n") + fmt.Fprintf(b, " %%empty0 = insertvalue %s undef, i64 %%cur_src, 0\n", resultType) + fmt.Fprintf(b, " %%empty1 = insertvalue %s %%empty0, i64 %%cur_dst, 1\n", resultType) + fmt.Fprintf(b, " %%empty2 = insertvalue %s %%empty1, i64 %%left, 2\n", resultType) + fmt.Fprintf(b, " %%empty3 = insertvalue %s %%empty2, %s 0, 3\n", resultType, typ) + fmt.Fprintf(b, " %%empty4 = insertvalue %s %%empty3, %s 0, 4\n", resultType, typ) + fmt.Fprintf(b, " %%empty5 = insertvalue %s %%empty4, i1 false, 5\n", resultType) + fmt.Fprintf(b, " ret %s %%empty5\n}\n\n", resultType) } +func emitX86LODSHelper(b *strings.Builder, name, typ string, width int) { + resultType := fmt.Sprintf("{ i64, i64, %s, i1 }", typ) + fmt.Fprintf(b, "define internal %s @%s(i64 %%src, i64 %%count, i1 %%backward) {\n", resultType, name) + b.WriteString(`entry: + %step = select i1 %backward, i64 `) + fmt.Fprintf(b, "-%d, i64 %d\n", width, width) + b.WriteString(` br label %loop +loop: + %cur = phi i64 [ %src, %entry ], [ %next, %load ] + %left = phi i64 [ %count, %entry ], [ %remaining, %load ] + %empty = icmp eq i64 %left, 0 + br i1 %empty, label %empty_exit, label %load +load: + %ptr = inttoptr i64 %cur to ptr +`) + fmt.Fprintf(b, " %%value = load %s, ptr %%ptr, align 1\n", typ) + b.WriteString(` %next = add i64 %cur, %step + %remaining = sub i64 %left, 1 + %more = icmp ne i64 %remaining, 0 + br i1 %more, label %loop, label %done +done: `) + fmt.Fprintf(b, " %%done0 = insertvalue %s undef, i64 %%next, 0\n", resultType) + fmt.Fprintf(b, " %%done1 = insertvalue %s %%done0, i64 %%remaining, 1\n", resultType) + fmt.Fprintf(b, " %%done2 = insertvalue %s %%done1, %s %%value, 2\n", resultType, typ) + fmt.Fprintf(b, " %%done3 = insertvalue %s %%done2, i1 true, 3\n", resultType) + fmt.Fprintf(b, " ret %s %%done3\n", resultType) + b.WriteString("empty_exit:\n") + fmt.Fprintf(b, " %%empty0 = insertvalue %s undef, i64 %%cur, 0\n", resultType) + fmt.Fprintf(b, " %%empty1 = insertvalue %s %%empty0, i64 %%left, 1\n", resultType) + fmt.Fprintf(b, " %%empty2 = insertvalue %s %%empty1, %s 0, 2\n", resultType, typ) + fmt.Fprintf(b, " %%empty3 = insertvalue %s %%empty2, i1 false, 3\n", resultType) + fmt.Fprintf(b, " ret %s %%empty3\n}\n\n", resultType) } func translateFuncAMD64(b *strings.Builder, fn Func, sig FuncSig, resolve func(string) string, sigs map[string]FuncSig, annotateSource bool) error { return translateFuncX86(b, fn, sig, resolve, sigs, "amd64", "", X87Auto, annotateSource) } +// emitX86AddressSensitiveRawText emits an exact raw TEXT body as a naked +// function. Naked inline assembly is intentionally limited to bodies selected +// by preserveAddressSensitiveX86RawText: their byte addresses are observable, +// so semantic IR lowering cannot preserve symbol+offset references. The +// unreachable terminator adds no machine bytes on LLVM 22. +func emitX86AddressSensitiveRawText(b *strings.Builder, fn Func, sig FuncSig) error { + if len(fn.X86RawText) == 0 { + return fmt.Errorf("empty address-sensitive raw TEXT body") + } + fmt.Fprintf(b, "define %s %s(", sig.Ret, llvmGlobal(sig.Name)) + for index, typ := range sig.Args { + if index != 0 { + b.WriteString(", ") + } + fmt.Fprintf(b, "%s %%arg%d", typ, index) + } + b.WriteString(") naked noinline") + if sig.Attrs != "" { + b.WriteString(" " + sig.Attrs) + } + b.WriteString(" {\nentry:\n") + var assembly strings.Builder + assembly.WriteString(".byte ") + for index, value := range fn.X86RawText { + if index != 0 { + assembly.WriteString(", ") + } + fmt.Fprintf(&assembly, "%d", value) + } + fmt.Fprintf(b, " call void asm sideeffect %q, %q()\n", assembly.String(), "~{memory}") + b.WriteString(" unreachable\n}\n") + return nil +} + func translateFuncX86(b *strings.Builder, fn Func, sig FuncSig, resolve func(string) string, sigs map[string]FuncSig, goarch, targetTriple string, x87Mode X87Mode, annotateSource bool) error { fmt.Fprintf(b, "define %s %s(", sig.Ret, llvmGlobal(sig.Name)) for i, t := range sig.Args { @@ -225,7 +527,7 @@ func (c *amd64Ctx) lowerBlocks() error { if c.repeatPrefix != "" && bi+1 == len(c.blocks) { prefix := c.repeatPrefix c.repeatPrefix = "" - return fmt.Errorf("386 %s prefix has no following string instruction", prefix) + return fmt.Errorf("%s %s prefix has no following string instruction", c.goarch, prefix) } // Fallthrough. if bi+1 < len(c.blocks) { @@ -240,19 +542,28 @@ func (c *amd64Ctx) lowerBlocks() error { func (c *amd64Ctx) lowerInstr(bi int, ii int, ins Instr, emitBr amd64EmitBr, emitCondBr amd64EmitCondBr) (terminated bool, err error) { c.allowSPWrite = models386SPWrite(ins) defer func() { c.allowSPWrite = false }() + for i := range ins.Args { + if ins.Args[i].Kind == OpFP || ins.Args[i].Kind == OpFPAddr { + ins.Args[i].FPOffset = c.namedFPResultOffset(ins.Args[i].FPName, ins.Args[i].FPOffset) + } + } op := strings.ToUpper(string(ins.Op)) - if c.repeatPrefix != "" && op != "MOVSB" && op != "MOVSL" && op != "STOSL" && op != "SCASB" { + _, _, _, regularString := x86StringProperties(Op(op)) + _, _, portString := x86PortStringProperties(Op(op)) + if c.repeatPrefix != "" && !regularString && !portString { prefix := c.repeatPrefix c.repeatPrefix = "" - return false, fmt.Errorf("386 %s prefix is unsupported for %s", prefix, op) + return false, fmt.Errorf("%s %s prefix is unsupported for %s", c.goarch, prefix, op) } if strings.HasPrefix(op, "GET_TLS(") { // Macro-expanded helper from go_tls.h. Keep current simplified model. return false, nil } switch Op(op) { - case OpTEXT, OpBYTE, OpWORD: + case OpTEXT: return false, nil + case OpBYTE, OpWORD, "LONG", "QUAD": + return false, fmt.Errorf("%s %s cannot be lowered safely as opaque machine code: %q", c.goarch, op, ins.Raw) case OpRET: if len(ins.Args) == 1 && ins.Args[0].Kind == OpSym && strings.HasSuffix(ins.Args[0].Sym, "(SB)") { return true, c.tailCallAndRet(ins.Args[0]) @@ -261,10 +572,75 @@ func (c *amd64Ctx) lowerInstr(bi int, ii int, ins Instr, emitBr amd64EmitBr, emi return true, fmt.Errorf("amd64 RET expects at most 1 operand: %q", ins.Raw) } return true, c.lowerRET() + case "NOPW", "NOPL": + if len(ins.Args) != 1 { + return false, fmt.Errorf("%s %s expects one Yml register/memory operand: %q", c.goarch, op, ins.Raw) + } + operand := ins.Args[0] + if operand.Kind == OpReg { + if !isX86YrlRegisterForArch(operand.Reg, c.goarch) { + return false, fmt.Errorf("%s %s register is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + } else if !isAMD64MemoryOperand(operand) { + return false, fmt.Errorf("%s %s operand is outside Go 1.27's Yml class: %q", c.goarch, op, ins.Raw) + } + return false, nil case "PCALIGN", "NO_LOCAL_POINTERS", "PCDATA", "FUNCDATA", "NOP", "PUSH_REGS_HOST_TO_ABI0()", "POP_REGS_HOST_TO_ABI0()": // Alignment directive emitted by stdlib asm; no semantic effect in our IR. return false, nil + case "LAHF": + if len(ins.Args) != 0 { + return false, fmt.Errorf("%s LAHF takes no operands: %q", c.goarch, ins.Raw) + } + packed := c.packX86Flags() + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i8\n", value, packed) + return false, c.storeRegSized(AH, I8, "%"+value) + case "SAHF": + if len(ins.Args) != 0 { + return false, fmt.Errorf("%s SAHF takes no operands: %q", c.goarch, ins.Raw) + } + value, err := c.evalIntSized(Operand{Kind: OpReg, Reg: AH}, I8) + if err != nil { + return false, err + } + flagBit := func(bit uint) string { + shifted := value + if bit != 0 { + tmp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i8 %s, %d\n", tmp, value, bit) + shifted = "%" + tmp + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i8 %s to i1\n", result, shifted) + return "%" + result + } + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", flagBit(0), c.flagsCFSlot) + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", flagBit(2), c.flagsPFSlot) + fmt.Fprintf(c.b, " store i1 %s, ptr %s\n", flagBit(6), c.flagsZSlot) + sign := flagBit(7) + overflow := c.loadFlag(c.flagsOFSlot) + signedLess := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %s, %s\n", signedLess, sign, overflow) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", signedLess, c.flagsSltSlot) + return false, nil + case "CLC", "STC", "CMC": + if len(ins.Args) != 0 { + return false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, op, ins.Raw) + } + switch op { + case "CLC": + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.flagsCFSlot) + case "STC": + fmt.Fprintf(c.b, " store i1 true, ptr %s\n", c.flagsCFSlot) + case "CMC": + oldCarry := c.loadFlag(c.flagsCFSlot) + newCarry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", newCarry, oldCarry) + fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", newCarry, c.flagsCFSlot) + } + return false, nil case "ADJSP": if c.goarch != "386" { return false, nil @@ -280,42 +656,278 @@ func (c *amd64Ctx) lowerInstr(bi int, ii int, ins Instr, emitBr amd64EmitBr, emi fmt.Fprintf(c.b, " %%%s = sub i64 %s, %d\n", next, sp, int64(ins.Args[0].Imm)) return false, c.storeRegUnchecked(SP, "%"+next) case "CLD": - if c.goarch != "386" { - return false, nil - } if len(ins.Args) != 0 { - return false, fmt.Errorf("386 CLD takes no operands: %q", ins.Raw) + return false, fmt.Errorf("%s CLD takes no operands: %q", c.goarch, ins.Raw) } - fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.directionSlot) + if c.directionSlot != "" { + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.directionSlot) + } + c.b.WriteString(" call void asm sideeffect \"cld\", \"~{dirflag}\"()\n") return false, nil case "STD": - if c.goarch != "386" { - return false, nil - } if len(ins.Args) != 0 { - return false, fmt.Errorf("386 STD takes no operands: %q", ins.Raw) + return false, fmt.Errorf("%s STD takes no operands: %q", c.goarch, ins.Raw) + } + if c.directionSlot != "" { + fmt.Fprintf(c.b, " store i1 true, ptr %s\n", c.directionSlot) } - fmt.Fprintf(c.b, " store i1 true, ptr %s\n", c.directionSlot) + c.b.WriteString(" call void asm sideeffect \"std\", \"~{dirflag}\"()\n") return false, nil case "REP", "REPN": - if c.goarch != "386" { - return false, nil - } if len(ins.Args) != 0 { - return false, fmt.Errorf("386 %s takes no operands: %q", op, ins.Raw) + return false, fmt.Errorf("%s %s takes no operands: %q", c.goarch, op, ins.Raw) } c.repeatPrefix = op return false, nil } + // Scalar ADD/SUB spellings overlap with vector and generic arithmetic + // lowerers. Validate the complete Go assembler operand table before those + // broader handlers get a chance to accept an illegal form. + if ok, term, err := c.lowerScalarAddSub(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerRTM(bi, ii, Op(op), ins, emitCondBr); ok { + return term, err + } + if ok, term, err := c.lowerFarReturn(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerLeave(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerXLAT(Op(op), ins); ok { + return term, err + } if ok, term, err := c.lowerBranch(bi, ii, Op(op), ins, emitBr, emitCondBr); ok { return term, err } + // Segment-register MOVW shares scalar MOV spellings with broad vector and + // generic move handlers, so validate its narrow ymovtab forms first. + if ok, term, err := c.lowerSegmentRegisterMove(Op(op), ins); ok { + return term, err + } if ok, term, err := c.lowerCmpBt(Op(op), ins); ok { return term, err } if ok, term, err := c.lowerX87(Op(op), ins); ok { return term, err } + if ok, term, err := c.lowerDuplicateMove(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedDwordMultiply(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedQwordMultiply(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerDwordToQwordMultiply(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedWordMultiply(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedWordMultiplyAdd(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedDotProduct(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedIntegerMinMax(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedUnsignedAverage(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerHorizontalInteger(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedUnsignedWordMinimumPosition(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerImplicitMaskMove(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedLogicalShift(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPerLaneVariableShift(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedArithmeticRightShift(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedFloatShuffle(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerShuffle128BitBlocks(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerImmediatePackedBlend(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerVariableBlend(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerMaskBlend(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedUnpack(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerQwordPermute(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerInLaneFloatingPermute(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerIndexedPermute(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerLegacyMMXMove(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerNonTemporalVectorMove(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerUnalignedVectorLoad(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedVectorMove(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedVectorInsert(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerInsertPackedSingle(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedByteShuffle(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerScatter(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerAlternatingFloatingAddSubtract(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedNumericConversion(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerSameWidthPackedConversion(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedHalfConversion(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedDoubleDword(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedAbsSign(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerVectorScalarIntegerMove(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerScalarIntegerToFloat(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerLegacyIntegerToFloat(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedExtendMove(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerParallelBitDepositExtract(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerMXCSR(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedFloatToDword(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedSingleToDouble(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedDoubleToSingle(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedScalarExtract(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedMoveMask(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerMoveHighLowPackedSingle(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerVectorLaneExtract(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedSumAbsoluteDifferences(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedFloatingDot(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedIntegerAdd(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedIntegerSubtract(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedScalarBroadcast(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerMaskRegisterBroadcast(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedBlockBroadcast(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedFloatingLogical(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerFMA3(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerEVEXPackedLogical(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedAndNot(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedIntegerCompare(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerImmediatePackedCompare(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedTestMask(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerFloatingCompare(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerPackedSaturatingNarrow(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerVariableDwordPermute(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerConditionalSet(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerVectorScalarMove(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerVectorScalarFlagCompare(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerConditionalMove(Op(op), ins); ok { + return term, err + } if ok, term, err := c.lowerFP(Op(op), ins); ok { return term, err } @@ -325,18 +937,66 @@ func (c *amd64Ctx) lowerInstr(bi int, ii int, ins Instr, emitBr amd64EmitBr, emi if ok, term, err := c.lowerVec(Op(op), ins); ok { return term, err } + if ok, term, err := c.lowerCompareExchange(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerBound(Op(op), ins); ok { + return term, err + } if ok, term, err := c.lowerAtomic(Op(op), ins); ok { return term, err } + if ok, term, err := c.lowerMSRAccess(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerImplicitSystem(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerDescriptorTable(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerSegmentBase(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerXState(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerSystemAddress(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerCacheLineWriteback(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerFixedSystem(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerSystemTransfer(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerAMDSystemManagement(Op(op), ins); ok { + return term, err + } if ok, term, err := c.lowerSyscall(Op(op), ins); ok { return term, err } + if ok, term, err := c.lowerPortIO(Op(op), ins); ok { + return term, err + } if ok, term, err := c.lowerString(Op(op), ins); ok { return term, err } + if ok, term, err := c.lowerMachineRegisterMove(Op(op), ins); ok { + return term, err + } if ok, term, err := c.lowerMov(Op(op), ins); ok { return term, err } + if ok, term, err := c.lowerScalarShiftRotate(Op(op), ins); ok { + return term, err + } + if ok, term, err := c.lowerScalarIncDec(Op(op), ins); ok { + return term, err + } if ok, term, err := c.lowerArith(Op(op), ins); ok { return term, err } diff --git a/arm64_abi.go b/arm64_abi.go new file mode 100644 index 00000000..d5711bba --- /dev/null +++ b/arm64_abi.go @@ -0,0 +1,148 @@ +package plan9asm + +import "fmt" + +type arm64ABIRegisterCursor struct { + integer int + floating int +} + +func isARM64ABIFloatingType(typ LLVMType) bool { + return typ == LLVMType("float") || typ == LLVMType("double") +} + +func isARM64ABIIntegerType(typ LLVMType) bool { + switch typ { + case I1, I8, I16, I32, I64, Ptr: + return true + default: + return false + } +} + +func (cursor *arm64ABIRegisterCursor) next(typ LLVMType) (Reg, error) { + if isARM64ABIFloatingType(typ) { + if cursor.floating >= 16 { + return "", fmt.Errorf("floating argument exceeds F0-F15") + } + reg := Reg(fmt.Sprintf("F%d", cursor.floating)) + cursor.floating++ + return reg, nil + } + if !isARM64ABIIntegerType(typ) { + return "", fmt.Errorf("unsupported ABI scalar type %s", typ) + } + if cursor.integer >= 16 { + return "", fmt.Errorf("integer argument exceeds R0-R15") + } + reg := Reg(fmt.Sprintf("R%d", cursor.integer)) + cursor.integer++ + return reg, nil +} + +func (c *arm64Ctx) loadABIRegisterValue(reg Reg, typ LLVMType) (string, error) { + raw, err := c.loadReg(reg) + if err != nil { + return "", err + } + switch typ { + case LLVMType("float"): + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", bits, raw) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", value, bits) + return "%" + value, nil + case LLVMType("double"): + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to double\n", value, raw) + return "%" + value, nil + default: + return c.castI64RegToArg(raw, typ) + } +} + +func (c *arm64Ctx) storeABIRegisterValue(reg Reg, typ LLVMType, value string) error { + raw, scalar, err := arm64ValueAsI64(c, typ, value) + if err != nil { + return err + } + if !scalar { + return fmt.Errorf("unsupported ABI scalar type %s", typ) + } + return c.storeReg(reg, raw) +} + +func (c *arm64Ctx) abiRegisterCallArgs(callee string, sig FuncSig) ([]string, error) { + args := make([]string, 0, len(sig.Args)) + cursor := arm64ABIRegisterCursor{} + for argIndex, argType := range sig.Args { + if len(sig.ArgRegs) != 0 { + if argIndex >= len(sig.ArgRegs) { + return nil, fmt.Errorf("arm64 call %q: missing explicit register for argument %d", callee, argIndex) + } + if _, aggregate := parseLiteralStructFields(argType); aggregate { + return nil, fmt.Errorf("arm64 call %q: explicit register for aggregate argument %d is ambiguous", callee, argIndex) + } + value, err := c.loadABIRegisterValue(sig.ArgRegs[argIndex], argType) + if err != nil { + return nil, err + } + args = append(args, fmt.Sprintf("%s %s", argType, value)) + continue + } + if fields, aggregate := parseLiteralStructFields(argType); aggregate { + value := "undef" + for fieldIndex, fieldType := range fields { + reg, err := cursor.next(fieldType) + if err != nil { + return nil, fmt.Errorf("arm64 call %q argument %d field %d: %w", callee, argIndex, fieldIndex, err) + } + field, err := c.loadABIRegisterValue(reg, fieldType) + if err != nil { + return nil, err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertvalue %s %s, %s %s, %d\n", inserted, argType, value, fieldType, field, fieldIndex) + value = "%" + inserted + } + args = append(args, fmt.Sprintf("%s %s", argType, value)) + continue + } + reg, err := cursor.next(argType) + if err != nil { + return nil, fmt.Errorf("arm64 call %q argument %d: %w", callee, argIndex, err) + } + value, err := c.loadABIRegisterValue(reg, argType) + if err != nil { + return nil, err + } + args = append(args, fmt.Sprintf("%s %s", argType, value)) + } + if len(sig.ArgRegs) > len(sig.Args) { + return nil, fmt.Errorf("arm64 call %q: %d explicit argument registers for %d arguments", callee, len(sig.ArgRegs), len(sig.Args)) + } + return args, nil +} + +func (c *arm64Ctx) storeABIRegisterResult(callee string, typ LLVMType, result string) error { + cursor := arm64ABIRegisterCursor{} + if fields, aggregate := parseLiteralStructFields(typ); aggregate { + for fieldIndex, fieldType := range fields { + reg, err := cursor.next(fieldType) + if err != nil { + return fmt.Errorf("arm64 call %q return field %d: %w", callee, fieldIndex, err) + } + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", extracted, typ, result, fieldIndex) + if err := c.storeABIRegisterValue(reg, fieldType, "%"+extracted); err != nil { + return err + } + } + return nil + } + reg, err := cursor.next(typ) + if err != nil { + return fmt.Errorf("arm64 call %q unsupported return type %s", callee, typ) + } + return c.storeABIRegisterValue(reg, typ, result) +} diff --git a/arm64_atomic_pair_test.go b/arm64_atomic_pair_test.go new file mode 100644 index 00000000..f8d7226a --- /dev/null +++ b/arm64_atomic_pair_test.go @@ -0,0 +1,176 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func translateARM64AtomicPairSource(src string) (string, error) { + file, err := Parse(ArchARM64, src) + if err != nil { + return "", err + } + return Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "atomicpairforms": {Name: "atomicpairforms", Ret: Void}, + }, + }) +} + +func TestTranslateARM64AtomicPairFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 has ten paired-atomic opcodes. CASP accepts C_ZOREG and + // C_ZAUTO memory, while paired exclusive loads/stores accept C_ZOREG. + // Register pairs for LDXP/STXP need not be contiguous; SP/RSP in a data + // pair encodes register 31 (ZR), rather than changing the stack pointer. + src := ` +TEXT atomicpairforms(SB),NOSPLIT,$16-0 + CASPW (R0, R1), (R2), (R4, R5) + CASPW (R6, R7), local+0(SP), (R10, R11) + CASPD (R12, R13), (ZR), (R14, R15) + CASPD (R30, ZR), (RSP), (R28, R29) + LDXPW (R16), (R0, R7) + LDXP (RSP), (R30, ZR) + LDAXPW (ZR), (RSP, R1) + LDAXP (R18), (R2, R17) + STXPW (R3, R3), (R19), R20 + STXP (RSP, R21), (RSP), ZR + STLXPW (ZR, R22), (R23), R24 + STLXP (R25, R26), (ZR), R27 + RET +` + ll, err := translateARM64AtomicPairSource(src) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"cmpxchg ptr", "load atomic i64", "load atomic i128", "%exclusive_value"} { + if !strings.Contains(ll, want) { + t.Fatalf("paired atomic lowering omitted %q:\n%s", want, ll) + } + } + + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + goos string + triple string + }{ + {goos: "darwin", triple: "arm64-apple-macosx"}, + {goos: "linux", triple: "aarch64-unknown-linux-gnu"}, + {goos: "windows", triple: "aarch64-pc-windows-msvc"}, + } { + t.Run(target.goos, func(t *testing.T) { + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "atomicpairforms": {Name: "atomicpairforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "atomic-pair.ll", "atomic-pair.o", ir) + }) + } +} + +func TestTranslateARM64AtomicPairFamilyRejectsFormsOutsideGoOptabs(t *testing.T) { + invalid := []string{ + // CASP requires two even-starting contiguous pairs and zero-offset + // C_ZOREG/C_ZAUTO memory. + "CASPD (R1, R2), (R3), (R4, R5)", + "CASPW (R0, R1), (R3), (R5, R6)", + "CASPD (R0, R2), (R3), (R4, R5)", + "CASPW (R0, R1), (R3), (R4, R6)", + "CASPD (R30, RSP), (R3), (R4, R5)", + "CASPW R0, (R3), (R4, R5)", + "CASPD (R0, R1), (R3), R4", + "CASPW (R0, R1), 8(R3), (R4, R5)", + "CASPD (R0, R1), local+8(SP), (R4, R5)", + "CASPW (R0, R1), value+0(FP), (R4, R5)", + "CASPD (R0, R1), value(SB), (R4, R5)", + "CASPW.P (R0, R1), (R3), (R4, R5)", + + // Paired exclusive loads require zero-offset register memory, exactly + // two distinct GPR/ZR data registers, and no opcode suffix. + "LDXP (R3), (R4, R4)", + "LDAXPW (R3), (R4, R4)", + "LDXPW 8(R3), (R4, R5)", + "LDAXP local+0(SP), (R4, R5)", + "LDXP value+0(FP), (R4, R5)", + "LDAXPW value(SB), (R4, R5)", + "LDXP (R3), R4", + "LDAXP (R3), (R4, R5, R6)", + "LDXP (R3), (F0, R4)", + "LDAXPW.P (R3), (R4, R5)", + + // Paired exclusive stores allow repeated data registers, but the + // status register cannot be SP/RSP or overlap either data register or + // a non-RSP base register. + "STXP (R4, R5), (R6), R4", + "STLXPW (R4, R5), (R6), R5", + "STXPW (R4, R5), (R6), R6", + "STLXP (R4, R5), (ZR), ZR", + "STXP (R4, R5), (R6), RSP", + "STLXPW R4, (R6), R7", + "STXP (R4, R5, R6), (R7), R8", + "STLXP (R4, F0), (R6), R7", + "STXPW (R4, R5), 8(R6), R7", + "STLXP (R4, R5), local+0(SP), R7", + "STXP (R4, R5), value+0(FP), R7", + "STLXPW (R4, R5), value(SB), R7", + "STXP.P (R4, R5), (R6), R7", + } + + for _, instruction := range invalid { + t.Run(strings.NewReplacer(" ", "_", "(", "", ")", "", ",", "_").Replace(instruction), func(t *testing.T) { + src := fmt.Sprintf("TEXT atomicpairforms(SB),NOSPLIT,$16-0\n\t%s\n\tRET\n", instruction) + if _, err := translateARM64AtomicPairSource(src); err == nil { + t.Fatalf("Translate accepted %q, which is outside the Go 1.27 paired-atomic optabs", instruction) + } + }) + } +} + +func TestParseARM64AtomicPairPreservesRSPAndNamedSP(t *testing.T) { + file, err := Parse(ArchARM64, ` +TEXT atomicpairforms(SB),NOSPLIT,$16-0 + CASPD (R0, R1), local+0(SP), (R2, R3) + LDAXP (RSP), (RSP, R4) + RET +`) + if err != nil { + t.Fatal(err) + } + casMem := file.Funcs[0].Instrs[1].Args[1].Mem + if casMem.Base != SP || casMem.OffRaw == "" { + t.Fatalf("named SP memory = %+v, want pseudo-SP plus preserved name", casMem) + } + load := file.Funcs[0].Instrs[2] + if load.Args[0].Mem.Base != Reg("RSP") || load.Args[1].RegList[0] != Reg("RSP") { + t.Fatalf("physical RSP was not preserved: %+v", load.Args) + } +} + +func TestARM64AtomicPairInstructionFamily(t *testing.T) { + for _, op := range []string{ + "CASPW", "CASPD", + "LDXPW", "LDXP", "LDAXPW", "LDAXP", + "STXPW", "STXP", "STLXPW", "STLXP", + } { + if got := InstructionFamily(ArchARM64, op); got != "atomic-memory" { + t.Errorf("InstructionFamily(arm64, %s) = %q, want atomic-memory", op, got) + } + } +} diff --git a/arm64_blocks.go b/arm64_blocks.go index 537d7b54..0035a0dc 100644 --- a/arm64_blocks.go +++ b/arm64_blocks.go @@ -30,8 +30,10 @@ func arm64SplitBlocks(fn Func) []arm64Block { op = op[:dot] } switch Op(op) { + case "BL", "BLR", "CALL": + return arm64IsLocalBranchLink(ins) case "B", "JMP", "BEQ", "BNE", "BLO", "BHI", "BLT", "BGE", "BLE", "BGT", "BHS", "BLS", "BMI", "BPL", "BVS", "BVC", - "BCC", "CBZ", "CBNZ", "TBZ", "TBNZ": + "BCC", "BCS", "CBZ", "CBNZ", "CBZW", "CBNZW", "TBZ", "TBNZ": return true default: return false @@ -61,11 +63,35 @@ func arm64SplitBlocks(fn Func) []arm64Block { // Drop trailing empty synthetic block if present. if len(blocks) > 1 && len(blocks[len(blocks)-1].instrs) == 0 && strings.HasPrefix(blocks[len(blocks)-1].name, "anon_") { - blocks = blocks[:len(blocks)-1] + previous := blocks[len(blocks)-2] + if len(previous.instrs) == 0 || !arm64IsLocalBranchLink(previous.instrs[len(previous.instrs)-1]) { + blocks = blocks[:len(blocks)-1] + } } return blocks } +func arm64IsLocalBranchLink(ins Instr) bool { + op := strings.ToUpper(string(ins.Op)) + if dot := strings.IndexByte(op, '.'); dot >= 0 { + op = op[:dot] + } + if op != "BL" && op != "BLR" && op != "CALL" || len(ins.Args) != 1 { + return false + } + target := ins.Args[0] + switch target.Kind { + case OpIdent: + return true + case OpSym: + return !strings.HasSuffix(target.Sym, "(SB)") + case OpMem: + return target.Mem.Base == PC + default: + return false + } +} + func arm64LLVMBlockName(src string) string { if src == "" { return "bb" diff --git a/arm64_blocks_test.go b/arm64_blocks_test.go new file mode 100644 index 00000000..e2363f69 --- /dev/null +++ b/arm64_blocks_test.go @@ -0,0 +1,24 @@ +package plan9asm + +import "testing" + +func TestARM64SplitBlocksRecognizesEveryConditionalBranchTerminator(t *testing.T) { + ops := []Op{ + "BEQ", "BNE", "BLO", "BLT", "BHI", "BHS", "BLS", "BGE", "BGT", "BLE", + "BCC", "BCS", "BMI", "BPL", "BVS", "BVC", + "CBZ", "CBNZ", "CBZW", "CBNZW", "TBZ", "TBNZ", + } + for _, op := range ops { + t.Run(string(op), func(t *testing.T) { + blocks := arm64SplitBlocks(Func{Instrs: []Instr{ + {Op: op, Raw: string(op)}, + {Op: "NOP", Raw: "NOP"}, + {Op: OpLABEL, Args: []Operand{{Kind: OpLabel, Sym: "target"}}}, + {Op: "NOP", Raw: "NOP"}, + }}) + if len(blocks) != 3 || len(blocks[0].instrs) != 1 || len(blocks[1].instrs) != 1 || blocks[2].name != "target" { + t.Fatalf("arm64SplitBlocks(%s) = %#v, want branch/fallthrough/target blocks", op, blocks) + } + }) + } +} diff --git a/arm64_conformance_test.go b/arm64_conformance_test.go index 87680aa8..863ead48 100644 --- a/arm64_conformance_test.go +++ b/arm64_conformance_test.go @@ -12,6 +12,12 @@ import ( ) func TestARM64ConformanceNativeGo(t *testing.T) { + if !currentGoMinorAtLeast(27) { + // The translated conformance test still runs on every supported Go + // version. Only the native oracle needs the Go 1.27 assembler because + // its source intentionally exercises Go 1.27-only aliases. + return + } crossLinux := runtime.GOOS == "linux" && runtime.GOARCH == "amd64" && os.Getenv("PLAN9ASM_CROSS_EXEC") == "1" if runtime.GOARCH != "arm64" && !crossLinux { t.Skip("native Go assembler oracle requires an arm64 host") @@ -60,6 +66,78 @@ func translateARM64Conformance(t *testing.T, triple string) string { {Offset: 8, Type: Ptr, Index: 1, Field: -1}, }}, }, + "scalarFloatSquareRoots": { + Name: "scalarFloatSquareRoots", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + }}, + }, + "fusedMultiplyAddSemantics": { + Name: "fusedMultiplyAddSemantics", + Args: []LLVMType{Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + }}, + }, + "pairedAtomicSemantics": { + Name: "pairedAtomicSemantics", + Args: []LLVMType{Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + "vectorPermuteSemantics": { + Name: "vectorPermuteSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "vectorWideningShiftSemantics": { + Name: "vectorWideningShiftSemantics", + Args: []LLVMType{Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + "scalarExtendSemantics": { + Name: "scalarExtendSemantics", + Args: []LLVMType{Ptr, I64}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + }}, + }, + "vectorCountBitsSemantics": { + Name: "vectorCountBitsSemantics", + Args: []LLVMType{Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + "unsignedWideningAddSemantics": { + Name: "unsignedWideningAddSemantics", + Args: []LLVMType{Ptr, Ptr, Ptr}, + Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, }, }) if err != nil { @@ -87,7 +165,7 @@ func TestARM64ConformanceLLVMRuntime(t *testing.T) { } else { _, clang, ok := findLlcAndClang(t) if !ok { - t.Skip("clang not found") + t.Fatal("clang not found") } compiler = []string{clang} } @@ -96,6 +174,14 @@ func TestARM64ConformanceLLVMRuntime(t *testing.T) { mainC := ` #include extern void families(uint64_t *out, uint64_t *data); +extern void scalarFloatSquareRoots(uint8_t *out); +extern void fusedMultiplyAddSemantics(uint8_t *out); +extern void pairedAtomicSemantics(uint64_t *out, uint64_t *data); +extern void vectorPermuteSemantics(uint8_t *out, uint8_t *n, uint8_t *m); +extern void vectorWideningShiftSemantics(uint8_t *out, uint8_t *source); +extern void scalarExtendSemantics(uint64_t *out, uint64_t value); +extern void vectorCountBitsSemantics(uint8_t *out, uint8_t *source); +extern void unsignedWideningAddSemantics(uint8_t *out, uint8_t *narrow, uint8_t *addend); int main(void) { uint64_t data[8] = {0x0123456789abcdefULL, 0xfedcba9876543210ULL, 0x1122334455667788ULL, 0x8877665544332211ULL}; uint64_t want[76] = { @@ -121,6 +207,115 @@ int main(void) { for (int i = 0; i < 76; i++) if (got[i] != want[i]) return i + 1; + union { + uint8_t bytes[16]; + struct { float s0, s1; double d; } values; + } scalar = {0}; + scalarFloatSquareRoots(scalar.bytes); + if (scalar.values.s0 != 2.0f) return 80; + if (scalar.values.s1 != 2.0f) return 81; + if (scalar.values.d != 4.0) return 82; + union { + uint8_t bytes[48]; + struct { float s[4]; double d[4]; } values; + } fma = {0}; + fusedMultiplyAddSemantics(fma.bytes); + float fma_s_want[4] = {11.0f, -1.0f, -11.0f, 1.0f}; + double fma_d_want[4] = {11.0, -1.0, -11.0, 1.0}; + for (int i = 0; i < 4; i++) { + if (fma.values.s[i] != fma_s_want[i]) return 83 + i; + if (fma.values.d[i] != fma_d_want[i]) return 87 + i; + } + uint8_t permute_n[16], permute_m[16], permute_got[96] = {0}; + for (int i = 0; i < 16; i++) { + permute_n[i] = (uint8_t)i; + permute_m[i] = (uint8_t)(0x80 + i); + } + uint8_t widen_narrow[16] = {1, 2, 3, 4, 5, 6, 7, 8, 0xf1, 0xe2, 0xd3, 0xc4, 0xb5, 0xa6, 0x97, 0x88}; + uint8_t widen_addend[16] = {0xff, 0x00, 0xfe, 0xff, 0x78, 0x56, 0x34, 0x12, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12}; + uint8_t widen_add_got[96] = {0}; + unsignedWideningAddSemantics(widen_add_got, widen_narrow, widen_addend); + int narrow_widths[6] = {1, 2, 4, 1, 2, 4}; + for (int group = 0; group < 6; group++) { + int narrow_bytes = narrow_widths[group], wide_bytes = 2*narrow_bytes, lanes = 16/wide_bytes; + int source_offset = group >= 3 ? 8 : 0; + for (int lane = 0; lane < lanes; lane++) { + uint64_t narrow_value = 0, addend_value = 0, got = 0; + for (int b = 0; b < narrow_bytes; b++) narrow_value |= (uint64_t)widen_narrow[source_offset+lane*narrow_bytes+b] << (8*b); + for (int b = 0; b < wide_bytes; b++) { + addend_value |= (uint64_t)widen_addend[lane*wide_bytes+b] << (8*b); + got |= (uint64_t)widen_add_got[group*16+lane*wide_bytes+b] << (8*b); + } + uint64_t sum = addend_value + narrow_value; + if (wide_bytes < 8) sum &= (1ULL << (8*wide_bytes)) - 1; + if (got != sum) return 190 + group; + } + } + vectorPermuteSemantics(permute_got, permute_n, permute_m); + for (int i = 0; i < 8; i++) { + if (permute_got[2*i] != permute_n[i] || permute_got[2*i+1] != permute_m[i]) return 100; + if (permute_got[16+2*i] != permute_n[8+i] || permute_got[16+2*i+1] != permute_m[8+i]) return 101; + if (permute_got[32+i] != permute_n[2*i] || permute_got[40+i] != permute_m[2*i]) return 102; + if (permute_got[48+i] != permute_n[2*i+1] || permute_got[56+i] != permute_m[2*i+1]) return 103; + if (permute_got[64+2*i] != permute_n[2*i] || permute_got[64+2*i+1] != permute_m[2*i]) return 104; + if (permute_got[80+2*i] != permute_n[2*i+1] || permute_got[80+2*i+1] != permute_m[2*i+1]) return 105; + } + uint64_t scalar_extend_got[10] = {0}; + uint64_t scalar_extend_value = 0x88776655fedcba98ULL; + uint64_t scalar_extend_want[10] = { + (uint64_t)(int64_t)(int8_t)scalar_extend_value, + (uint64_t)(uint32_t)(int32_t)(int8_t)scalar_extend_value, + (uint64_t)(int64_t)(int16_t)scalar_extend_value, + (uint64_t)(uint32_t)(int32_t)(int16_t)scalar_extend_value, + (uint64_t)(int64_t)(int32_t)scalar_extend_value, + (uint64_t)(uint8_t)scalar_extend_value, + (uint64_t)(uint32_t)(uint8_t)scalar_extend_value, + (uint64_t)(uint16_t)scalar_extend_value, + (uint64_t)(uint32_t)(uint16_t)scalar_extend_value, + (uint64_t)(uint32_t)scalar_extend_value, + }; + scalarExtendSemantics(scalar_extend_got, scalar_extend_value); + for (int i = 0; i < 10; i++) + if (scalar_extend_got[i] != scalar_extend_want[i]) return 120 + i; + uint8_t count_source[16] = {0, 1, 2, 3, 7, 15, 31, 63, 127, 128, 129, 0xaa, 0x55, 0xfe, 0xff, 0x81}; + uint8_t count_got[32] = {0}; + vectorCountBitsSemantics(count_got, count_source); + for (int i = 0; i < 16; i++) { + uint8_t value = count_source[i], count = 0; + while (value) { count += value & 1; value >>= 1; } + if (count_got[16+i] != count) return 140 + i; + if (i < 8 && count_got[i] != count) return 160 + i; + if (i >= 8 && count_got[i] != 0) return 170 + i; + } + uint8_t widening_source[16] = {0, 1, 0x7f, 0x80, 0xff, 2, 0x55, 0xaa, 3, 4, 0x40, 0xc0, 0xfe, 0x81, 0x11, 0xee}; + uint16_t widening_got[64] = {0}; + vectorWideningShiftSemantics((uint8_t *)widening_got, widening_source); + for (int i = 0; i < 8; i++) { + uint16_t low = widening_source[i], high = widening_source[8+i]; + uint16_t signed_low = (uint16_t)(int16_t)(int8_t)widening_source[i]; + uint16_t signed_high = (uint16_t)(int16_t)(int8_t)widening_source[8+i]; + uint16_t want_widening[8] = {low, high, signed_low, signed_high, (uint16_t)(low << 7), (uint16_t)(high << 1), (uint16_t)(signed_low << 3), (uint16_t)(signed_high << 2)}; + for (int group = 0; group < 8; group++) + if (widening_got[group*8+i] != want_widening[group]) return 110 + group; + } + uint64_t atomic_data[9] __attribute__((aligned(16))) = { + 0x11, 0x22, 0x33, 0x44, + 0x0000002200000011ULL, 0x0000004400000033ULL, + 0x55, 0x66, 0x0000008800000077ULL + }; + uint64_t atomic_want[23] = { + 0x11, 0x22, 0xaa, 0xbb, + 0x33, 0x44, 0x33, 0x44, + 0x11, 0x22, 0x000000bb000000aaULL, + 0x33, 0x44, 0x0000004400000033ULL, + 0x55, 0x66, 0, 0xcc, 0xdd, + 0x77, 0x88, 1, 0x000000aa00000099ULL + }; + uint64_t atomic_got[23] = {0}; + pairedAtomicSemantics(atomic_got, atomic_data); + for (int i = 0; i < 23; i++) + if (atomic_got[i] != atomic_want[i]) + return 100 + i; return 0; } ` diff --git a/arm64_ctx.go b/arm64_ctx.go index e3b64462..c7402b37 100644 --- a/arm64_ctx.go +++ b/arm64_ctx.go @@ -18,11 +18,20 @@ type arm64Ctx struct { blocks []arm64Block + rawDataGlobals map[string]string // local source label -> LLVM global + usedRegs map[Reg]bool regSlot map[Reg]string // reg -> alloca name - usedVRegs map[int]bool - vRegSlot map[int]string // vreg index -> alloca name (<16 x i8>) + usedVRegs map[int]bool + vRegSlot map[int]string // vreg index -> alloca name (<16 x i8>) + usedZRegs map[int]bool + zRegSlot map[int]string // SVE zreg index -> alloca name () + usedPRegs map[int]bool + pRegSlot map[int]string // SVE preg index -> alloca name () + usedPNRegs map[int]bool + pnRegSlot map[int]string // SVE predicate-as-counter index -> alloca name (target("aarch64.svcount")) + localStackSlot string flagsNSlot string flagsZSlot string @@ -36,6 +45,7 @@ type arm64Ctx struct { exclusiveValueSlot string fpParams map[int64]FrameSlot // off(FP) -> slot + fpParamAlloca map[int64]string // parameter off(FP) -> mutable alloca fpResults []FrameSlot // result slots (Index is result index) fpResAllocaOff map[int64]string // off(FP) -> alloca fpResAllocaIdx map[int]string // result index -> alloca @@ -55,7 +65,14 @@ func newARM64Ctx(b *strings.Builder, fn Func, sig FuncSig, resolve func(string) regSlot: map[Reg]string{}, usedVRegs: map[int]bool{}, vRegSlot: map[int]string{}, + usedZRegs: map[int]bool{}, + zRegSlot: map[int]string{}, + usedPRegs: map[int]bool{}, + pRegSlot: map[int]string{}, + usedPNRegs: map[int]bool{}, + pnRegSlot: map[int]string{}, fpParams: map[int64]FrameSlot{}, + fpParamAlloca: map[int64]string{}, fpResAllocaOff: map[int64]string{}, fpResAllocaIdx: map[int]string{}, fpResWritten: map[int]bool{}, @@ -95,8 +112,8 @@ func arm64ParseVReg(r Reg) (idx int, ok bool) { return 0, false } // Strip optional lane suffix: V8.D[0], V5.B16, etc. - if dot := strings.IndexByte(s, '.'); dot >= 0 { - s = s[:dot] + if suffix := strings.IndexAny(s, ".["); suffix >= 0 { + s = s[:suffix] } n, err := strconv.Atoi(strings.TrimPrefix(s, "V")) if err != nil || n < 0 || n > 31 { @@ -117,11 +134,62 @@ func arm64ParseFReg(r Reg) (idx int, ok bool) { return n, true } +func arm64ParseZReg(r Reg) (idx int, ok bool) { + s := strings.ToUpper(strings.TrimSpace(string(r))) + if !strings.HasPrefix(s, "Z") { + return 0, false + } + if suffix := strings.IndexAny(s, ".["); suffix >= 0 { + s = s[:suffix] + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "Z")) + return n, err == nil && n >= 0 && n <= 31 +} + +func arm64ParsePReg(r Reg) (idx int, ok bool) { + s := strings.ToUpper(strings.TrimSpace(string(r))) + if !strings.HasPrefix(s, "P") { + return 0, false + } + if dot := strings.IndexByte(s, '.'); dot >= 0 { + s = s[:dot] + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "P")) + return n, err == nil && n >= 0 && n <= 15 +} + +func arm64ParsePNReg(r Reg) (idx int, ok bool) { + s := strings.ToUpper(strings.TrimSpace(string(r))) + if !strings.HasPrefix(s, "PN") { + return 0, false + } + if suffix := strings.IndexAny(s, ".["); suffix >= 0 { + s = s[:suffix] + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "PN")) + return n, err == nil && n >= 0 && n <= 15 +} + func (c *arm64Ctx) scanUsedRegs() { markReg := func(r Reg) { if r == "" { return } + if r == Reg("RSP") { + r = SP + } + if idx, ok := arm64ParseZReg(r); ok { + c.usedZRegs[idx] = true + return + } + if idx, ok := arm64ParsePNReg(r); ok { + c.usedPNRegs[idx] = true + return + } + if idx, ok := arm64ParsePReg(r); ok { + c.usedPRegs[idx] = true + return + } if idx, ok := arm64ParseVReg(r); ok { c.usedVRegs[idx] = true return @@ -156,6 +224,393 @@ func (c *arm64Ctx) scanUsedRegs() { for _, op := range ins.Args { markOp(op) } + if ins.Op == OpWORD && len(ins.Args) == 1 && ins.Args[0].Kind == OpImm && ins.Args[0].ImmRaw == "" { + if form, ok := decodeARM64RawSystemRegister(uint32(ins.Args[0].Imm)); ok && form.reg != 31 { + markReg(Reg(fmt.Sprintf("R%d", form.reg))) + } + if form, ok := decodeARM64RawCASP(uint32(ins.Args[0].Imm)); ok { + for _, reg := range arm64RawCASPRegisterPair(form.expected) { + markReg(reg) + } + for _, reg := range arm64RawCASPRegisterPair(form.newValue) { + markReg(reg) + } + if form.base == 31 { + markReg(Reg("RSP")) + } else { + markReg(Reg(fmt.Sprintf("R%d", form.base))) + } + } + // Specialized raw decoders below predate the shared Go-table + // fallback. Also scan the official decoded operands so any + // instruction handled by that fallback receives register storage. + if decoded, err := decodeARM64RawWordInstruction(ins); err == nil { + for _, op := range decoded.Args { + markOp(op) + } + } + word := uint32(ins.Args[0].Imm) + if form, ok := decodeARM64RawStructureLane(word); ok { + if form.base == 31 { + markReg(SP) + } else { + markReg(Reg(fmt.Sprintf("R%d", form.base))) + } + if form.post && form.postRegister != 31 { + markReg(Reg(fmt.Sprintf("R%d", form.postRegister))) + } + for i := 0; i < form.count; i++ { + markReg(Reg(fmt.Sprintf("V%d", (form.firstRegister+i)%32))) + } + } + if form, ok := decodeARM64RawAES(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.source))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawDotProduct(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.left))) + markReg(Reg(fmt.Sprintf("V%d", form.right))) + } + if form, ok := decodeARM64RawMatrixMultiply(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.left))) + markReg(Reg(fmt.Sprintf("V%d", form.right))) + } + if form, ok := decodeARM64RawFloatMultiplyLong(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawVectorFloatNarrow(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.source))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawVectorFloatWiden(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.source))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawFADDP(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.first))) + if !form.scalar { + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawFloatPairwiseMinMax(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.first))) + if !form.scalar { + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawTableLookup(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.index))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + for i := 0; i < form.tableCount; i++ { + markReg(Reg(fmt.Sprintf("V%d", (form.firstTable+i)%32))) + } + } + if form, ok := decodeARM64RawSQDMULH(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawMUL(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawSHSUB(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawCMGT(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + if !form.zero { + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + } + if form, ok := decodeARM64RawMLS(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawPairwiseAddLong(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.sourceReg))) + markReg(Reg(fmt.Sprintf("V%d", form.destReg))) + } + if form, ok := decodeARM64RawUMULL(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destReg))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawUZP(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawSSHR(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.source))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawUHADD(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawUSHLL(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.source))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawLDnR(word); ok { + for i := 0; i < form.count; i++ { + markReg(Reg(fmt.Sprintf("V%d", (form.firstRegister+i)%32))) + } + if form.base == 31 { + markReg(SP) + } else { + markReg(Reg(fmt.Sprintf("R%d", form.base))) + } + if form.post && form.postRegister != 31 { + markReg(Reg(fmt.Sprintf("R%d", form.postRegister))) + } + } + if form, ok := decodeARM64RawUMLAL(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destReg))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawDUPElement(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.source))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawMLA(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawCVTF(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.source))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawFMLA(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.elementReg))) + markReg(Reg(fmt.Sprintf("V%d", form.sourceReg))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawFMULByElement(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.elementReg))) + markReg(Reg(fmt.Sprintf("V%d", form.sourceReg))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawFloatBinary(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + if form, ok := decodeARM64RawFSQRT(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.source))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawFloatAbsNeg(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.source))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawFloatCompare(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.first))) + if !form.zero { + markReg(Reg(fmt.Sprintf("V%d", form.second))) + } + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawLogical(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.first))) + markReg(Reg(fmt.Sprintf("V%d", form.second))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawModifiedImmediate(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawFCVTZ(word); ok { + markReg(Reg(fmt.Sprintf("V%d", form.source))) + markReg(Reg(fmt.Sprintf("V%d", form.destination))) + } + if form, ok := decodeARM64RawMoveWide(word); ok && form.destination != 31 { + markReg(Reg(fmt.Sprintf("R%d", form.destination))) + } + if form, ok := decodeARM64RawSVEAddress(word); ok { + if form.op != "RDVL" { + if form.source == 31 { + markReg(SP) + } else { + markReg(Reg(fmt.Sprintf("R%d", form.source))) + } + } + if form.destination == 31 { + markReg(SP) + } else { + markReg(Reg(fmt.Sprintf("R%d", form.destination))) + } + } + if form, ok := decodeARM64RawSVECnt(word); ok && form.destination != 31 { + markReg(Reg(fmt.Sprintf("R%d", form.destination))) + } + if form, ok := decodeARM64RawBitfield(word); ok { + if form.source != 31 { + markReg(Reg(fmt.Sprintf("R%d", form.source))) + } + if form.destination != 31 { + markReg(Reg(fmt.Sprintf("R%d", form.destination))) + } + } + if form, ok := decodeARM64RawSVEPTrue(word); ok { + markReg(Reg(fmt.Sprintf("P%d", form.destination))) + } + if form, ok := decodeARM64RawSVELDST1D(word); ok { + markReg(Reg(fmt.Sprintf("P%d", form.predicate))) + markReg(Reg(fmt.Sprintf("Z%d", form.vector))) + if form.base == 31 { + markReg(SP) + } else { + markReg(Reg(fmt.Sprintf("R%d", form.base))) + } + if form.registerOffset && form.index != 31 { + markReg(Reg(fmt.Sprintf("R%d", form.index))) + } + } + if form, ok := decodeARM64RawSVELDST1W(word); ok { + markReg(Reg(fmt.Sprintf("P%d", form.predicate))) + markReg(Reg(fmt.Sprintf("Z%d", form.vector))) + if form.base == 31 { + markReg(SP) + } else { + markReg(Reg(fmt.Sprintf("R%d", form.base))) + } + if form.registerOffset && form.index != 31 { + markReg(Reg(fmt.Sprintf("R%d", form.index))) + } + } + if form, ok := decodeARM64RawSVEFloat(word); ok { + markReg(Reg(fmt.Sprintf("P%d", form.predicate))) + switch form.kind { + case arm64RawSVEFloatFADDV, arm64RawSVEFloatFADDA: + markReg(Reg(fmt.Sprintf("F%d", form.destination))) + markReg(Reg(fmt.Sprintf("Z%d", form.first))) + default: + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + markReg(Reg(fmt.Sprintf("Z%d", form.first))) + if form.kind == arm64RawSVEFloatFMLA || form.kind == arm64RawSVEFloatFMAD || form.second != form.first { + markReg(Reg(fmt.Sprintf("Z%d", form.second))) + } + } + } + if form, ok := decodeARM64RawSVELoadStore(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.vector))) + if form.base == 31 { + markReg(SP) + } else { + markReg(Reg(fmt.Sprintf("R%d", form.base))) + } + } + if form, ok := decodeARM64RawSVEDupImmediate(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + if form, ok := decodeARM64RawSVEDupGeneral(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + if form.source == 31 { + markReg(SP) + } else { + markReg(Reg(fmt.Sprintf("R%d", form.source))) + } + } + if form, ok := decodeARM64RawSVEDupElement(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.source))) + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + if form, ok := decodeARM64RawSVEAdd(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.first))) + if form.mode != arm64SVEAddImmediate { + markReg(Reg(fmt.Sprintf("Z%d", form.second))) + } + if form.mode == arm64SVEAddPredicated { + markReg(Reg(fmt.Sprintf("P%d", form.predicate))) + } + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + if form, ok := decodeARM64RawSVELSR(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.source))) + if form.mode == arm64SVELSRWidePredicated || form.mode == arm64SVELSRWideUnpredicated || form.mode == arm64SVELSRVectorPredicated { + markReg(Reg(fmt.Sprintf("Z%d", form.shifts))) + } + if form.mode == arm64SVELSRWidePredicated || form.mode == arm64SVELSRVectorPredicated || form.mode == arm64SVELSRImmediatePredicated { + markReg(Reg(fmt.Sprintf("P%d", form.predicate))) + } + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + if form, ok := decodeARM64RawSVESelect(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.falseValue))) + markReg(Reg(fmt.Sprintf("Z%d", form.trueValue))) + markReg(Reg(fmt.Sprintf("P%d", form.predicate))) + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + if form, ok := decodeARM64RawSVEMultiply(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.first))) + switch form.mode { + case arm64SVEMultiplyPredicated: + markReg(Reg(fmt.Sprintf("Z%d", form.second))) + markReg(Reg(fmt.Sprintf("P%d", form.predicate))) + case arm64SVEMultiplyUnpredicated: + markReg(Reg(fmt.Sprintf("Z%d", form.second))) + case arm64SVEMultiplyLane: + markReg(Reg(fmt.Sprintf("Z%d", form.laneVector))) + } + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + if form, ok := decodeARM64RawSVEEOR(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.first))) + if form.mode != arm64SVEEORImmediate { + markReg(Reg(fmt.Sprintf("Z%d", form.second))) + } + if form.mode == arm64SVEEORPredicated { + markReg(Reg(fmt.Sprintf("P%d", form.predicate))) + } + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + if form, ok := decodeARM64RawSVETable(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.index))) + markReg(Reg(fmt.Sprintf("Z%d", form.firstTable))) + if form.tableCount == 2 { + markReg(Reg(fmt.Sprintf("Z%d", (form.firstTable+1)%32))) + } + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + if form, ok := decodeARM64RawSVEUMULLB(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.first))) + if form.mode == arm64SVEUMULLBVector { + markReg(Reg(fmt.Sprintf("Z%d", form.second))) + } else { + markReg(Reg(fmt.Sprintf("Z%d", form.laneVector))) + } + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + if form, ok := decodeARM64RawSVEMultiplyAccumulateLong(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.first))) + if form.mode == arm64SVEUMULLBVector { + markReg(Reg(fmt.Sprintf("Z%d", form.second))) + } else { + markReg(Reg(fmt.Sprintf("Z%d", form.laneVector))) + } + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + if form, ok := decodeARM64RawSVEPermute(word); ok { + markReg(Reg(fmt.Sprintf("Z%d", form.first))) + markReg(Reg(fmt.Sprintf("Z%d", form.second))) + markReg(Reg(fmt.Sprintf("Z%d", form.destination))) + } + } } } // Ensure arg regs exist. @@ -164,23 +619,36 @@ func (c *arm64Ctx) scanUsedRegs() { markReg(c.sig.ArgRegs[i]) } } else { - // Go internal ABI on arm64 uses up to 16 integer argument registers. - // For aggregate args like {ptr,len,cap} we need registers for each word, - // since ABIInternal asm expects those words in consecutive registers. - n := 0 - for _, ty := range c.sig.Args { - if fields, ok := parseLiteralStructFields(ty); ok && literalFieldsAllScalar(fields) { - n += len(fields) - } else { - n++ + cursor := arm64ABIRegisterCursor{} + for _, typ := range c.sig.Args { + if fields, aggregate := parseLiteralStructFields(typ); aggregate { + for _, fieldType := range fields { + reg, err := cursor.next(fieldType) + if err != nil { + break + } + markReg(reg) + } + continue + } + if reg, err := cursor.next(typ); err == nil { + markReg(reg) } } - for i := 0; i < n && i < 16; i++ { - markReg(Reg(fmt.Sprintf("R%d", i))) + } + // Ensure register-return storage exists for all scalar result classes. + if len(c.fpResults) == 0 && c.sig.Ret != Void { + cursor := arm64ABIRegisterCursor{} + if fields, aggregate := parseLiteralStructFields(c.sig.Ret); aggregate { + for _, fieldType := range fields { + if reg, err := cursor.next(fieldType); err == nil { + markReg(reg) + } + } + } else if reg, err := cursor.next(c.sig.Ret); err == nil { + markReg(reg) } } - // Ensure return reg exists. - markReg(Reg("R0")) // Keep lowering permissive for hand-written stubs that reference ad-hoc // registers via macros/aliases not captured in signatures. for i := 0; i <= 31; i++ { @@ -197,7 +665,10 @@ func (c *arm64Ctx) emitEntryAllocasAndArgInit() error { } sort.Strings(regs) - c.b.WriteString(arm64LLVMBlockName("entry") + ":\n") + // Keep allocas in LLVM's entry block and lower the source-level entry as a + // separate block. LLVM forbids blockaddress constants that name the actual + // entry block, while ARM64 ADR may legally address the first source block. + c.b.WriteString("entry:\n") for _, rs := range regs { r := Reg(rs) name := c.slotName(r) @@ -205,6 +676,22 @@ func (c *arm64Ctx) emitEntryAllocasAndArgInit() error { fmt.Fprintf(c.b, " %s = alloca i64\n", name) fmt.Fprintf(c.b, " store i64 0, ptr %s\n", name) } + if spSlot := c.regSlot[SP]; spSlot != "" { + minOff, maxOff := c.stackOffsetRange() + const guard = int64(64) + bias := guard - minOff + size := bias + maxOff + guard + if size < 256 { + size = 256 + } + c.localStackSlot = "%local_stack" + fmt.Fprintf(c.b, " %s = alloca [%d x i8]\n", c.localStackSlot, size) + base := c.newTmp() + fmt.Fprintf(c.b, " %%%s = getelementptr inbounds [%d x i8], ptr %s, i32 0, i64 %d\n", base, size, c.localStackSlot, bias) + addr := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %%%s to i64\n", addr, base) + fmt.Fprintf(c.b, " store i64 %%%s, ptr %s\n", addr, spSlot) + } // Vector registers: keep as <16 x i8> to cover most stdlib NEON byte ops. vIdx := make([]int, 0, len(c.usedVRegs)) @@ -219,6 +706,41 @@ func (c *arm64Ctx) emitEntryAllocasAndArgInit() error { fmt.Fprintf(c.b, " store <16 x i8> zeroinitializer, ptr %s\n", name) } + zIdx := make([]int, 0, len(c.usedZRegs)) + for i := range c.usedZRegs { + zIdx = append(zIdx, i) + } + sort.Ints(zIdx) + for _, i := range zIdx { + name := fmt.Sprintf("%%z%d", i) + c.zRegSlot[i] = name + fmt.Fprintf(c.b, " %s = alloca \n", name) + fmt.Fprintf(c.b, " store zeroinitializer, ptr %s\n", name) + } + + pIdx := make([]int, 0, len(c.usedPRegs)) + for i := range c.usedPRegs { + pIdx = append(pIdx, i) + } + sort.Ints(pIdx) + for _, i := range pIdx { + name := fmt.Sprintf("%%p%d", i) + c.pRegSlot[i] = name + fmt.Fprintf(c.b, " %s = alloca \n", name) + fmt.Fprintf(c.b, " store zeroinitializer, ptr %s\n", name) + } + + pnIdx := make([]int, 0, len(c.usedPNRegs)) + for i := range c.usedPNRegs { + pnIdx = append(pnIdx, i) + } + sort.Ints(pnIdx) + for _, i := range pnIdx { + name := fmt.Sprintf("%%pn%d", i) + c.pnRegSlot[i] = name + fmt.Fprintf(c.b, " %s = alloca target(\"aarch64.svcount\")\n", name) + } + // Flags state: model "last CMP/SUBS/ANDS result" as two i64 slots. // This avoids SSA-phi complexity across CFG edges while we bootstrap. // We keep the actual NZCV bits, since stdlib asm relies on carry-based @@ -247,11 +769,29 @@ func (c *arm64Ctx) emitEntryAllocasAndArgInit() error { fmt.Fprintf(c.b, " store ptr null, ptr %s\n", c.exclusivePtrSlot) fmt.Fprintf(c.b, " %s = alloca i8\n", c.exclusiveSizeSlot) fmt.Fprintf(c.b, " store i8 0, ptr %s\n", c.exclusiveSizeSlot) - fmt.Fprintf(c.b, " %s = alloca i64\n", c.exclusiveValueSlot) - fmt.Fprintf(c.b, " store i64 0, ptr %s\n", c.exclusiveValueSlot) + fmt.Fprintf(c.b, " %s = alloca i128\n", c.exclusiveValueSlot) + fmt.Fprintf(c.b, " store i128 0, ptr %s\n", c.exclusiveValueSlot) // Frame result slots: allocate addressable storage so patterns like // `$ret+off(FP)` and `MOVD x, ret+off(FP)` can work. + // ABI0 parameter slots are writable as well: generated assembly commonly + // spills an argument back to its own +off(FP) slot across nested calls. + for i, p := range c.sig.Frame.Params { + if p.Index < 0 || p.Index >= len(c.sig.Args) { + return fmt.Errorf("arm64 entry %q: FP parameter slot +%d has invalid argument index %d", c.sig.Name, p.Offset, p.Index) + } + name := fmt.Sprintf("%%fp_param_%d", i) + c.fpParamAlloca[p.Offset] = name + fmt.Fprintf(c.b, " %s = alloca %s\n", name, p.Type) + value := fmt.Sprintf("%%arg%d", p.Index) + if fields := frameSlotFields(p); len(fields) != 0 { + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %s%s\n", extracted, c.sig.Args[p.Index], value, frameSlotExtractSuffix(p)) + value = "%" + extracted + } + fmt.Fprintf(c.b, " store %s %s, ptr %s\n", p.Type, value, name) + } + for _, r := range c.fpResults { name := fmt.Sprintf("%%fp_ret_%d", r.Index) c.fpResAllocaIdx[r.Index] = name @@ -260,76 +800,92 @@ func (c *arm64Ctx) emitEntryAllocasAndArgInit() error { fmt.Fprintf(c.b, " store %s %s, ptr %s\n", r.Type, llvmZeroValue(r.Type), name) } - // Map args -> regs (best-effort for ABIInternal-style asm, and for helper<> reg assignments). + // Map args -> the independent integer and floating-point ABIInternal banks, + // or to an explicit helper register assignment. if len(c.sig.ArgRegs) > 0 { - // Custom arg->reg assignment (used by helper<> bodies). - for i := 0; i < len(c.sig.Args) && i < len(c.sig.ArgRegs); i++ { - r := c.sig.ArgRegs[i] - arg := fmt.Sprintf("%%arg%d", i) - argTy := c.sig.Args[i] - v, ok, err := arm64ValueAsI64(c, argTy, arg) - if err != nil { - return err - } - if !ok { - continue + if len(c.sig.ArgRegs) != len(c.sig.Args) { + return fmt.Errorf("arm64 entry %q: %d explicit argument registers for %d arguments", c.sig.Name, len(c.sig.ArgRegs), len(c.sig.Args)) + } + for i, reg := range c.sig.ArgRegs { + if _, aggregate := parseLiteralStructFields(c.sig.Args[i]); aggregate { + return fmt.Errorf("arm64 entry %q: explicit register for aggregate argument %d is ambiguous", c.sig.Name, i) } - if err := c.storeReg(r, v); err != nil { + if err := c.storeABIRegisterValue(reg, c.sig.Args[i], fmt.Sprintf("%%arg%d", i)); err != nil { return err } } return nil } - // Default: flatten aggregate args into consecutive argument registers - // following the Go internal ABI word ordering. - regIdx := 0 - for ai := 0; ai < len(c.sig.Args) && regIdx < 16; ai++ { + cursor := arm64ABIRegisterCursor{} + for ai := 0; ai < len(c.sig.Args); ai++ { arg := fmt.Sprintf("%%arg%d", ai) argTy := c.sig.Args[ai] - if fields, ok := parseLiteralStructFields(argTy); ok && literalFieldsAllScalar(fields) { + if fields, aggregate := parseLiteralStructFields(argTy); aggregate { for fi, fTy := range fields { - if regIdx >= 16 { - break - } - r := Reg(fmt.Sprintf("R%d", regIdx)) - regIdx++ - slot, ok := c.regSlot[r] - if !ok { - continue + r, err := cursor.next(fTy) + if err != nil { + return nil } t := c.newTmp() fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", t, argTy, arg, fi) - v, ok, err := arm64ValueAsI64(c, fTy, "%"+t) - if err != nil { + if err := c.storeABIRegisterValue(r, fTy, "%"+t); err != nil { return err } - if !ok { - continue - } - fmt.Fprintf(c.b, " store i64 %s, ptr %s\n", v, slot) } continue } - r := Reg(fmt.Sprintf("R%d", regIdx)) - regIdx++ - slot, ok := c.regSlot[r] - if !ok { - continue - } - v, ok, err := arm64ValueAsI64(c, argTy, arg) + r, err := cursor.next(argTy) if err != nil { - return err + return nil } - if !ok { - continue + if err := c.storeABIRegisterValue(r, argTy, arg); err != nil { + return err } - fmt.Fprintf(c.b, " store i64 %s, ptr %s\n", v, slot) } return nil } +func (c *arm64Ctx) stackOffsetRange() (minOff, maxOff int64) { + add := func(off, size int64) { + if off < minOff { + minOff = off + } + if end := off + size; end > maxOff { + maxOff = end + } + } + for _, block := range c.blocks { + for _, ins := range block.instrs { + for _, arg := range ins.Args { + if arg.Kind == OpMem && (arg.Mem.Base == SP || arg.Mem.Base == Reg("RSP") || arg.Mem.Base == ZR) { + add(arg.Mem.Off, 16) + } + } + op := strings.ToUpper(string(ins.Op)) + if (op != "BL" && op != "CALL") || len(ins.Args) != 1 || ins.Args[0].Kind != OpSym { + continue + } + symbol := strings.TrimSpace(ins.Args[0].Sym) + if !strings.HasSuffix(symbol, "(SB)") || strings.HasSuffix(symbol, "(SB)") { + continue + } + sig, ok := c.sigs[c.resolve(strings.TrimSuffix(symbol, "(SB)"))] + if !ok || len(sig.ArgRegs) != 0 { + continue + } + for _, slot := range sig.Frame.Params { + add(slot.Offset, frameTypeSize(slot.Type, 8)) + } + for _, slot := range sig.Frame.Results { + add(slot.Offset, frameTypeSize(slot.Type, 8)) + } + } + } + return minOff, maxOff +} + func arm64ValueAsI64(c *arm64Ctx, ty LLVMType, v string) (out string, ok bool, err error) { switch ty { case Ptr: @@ -424,6 +980,9 @@ func (c *arm64Ctx) loadReg(r Reg) (string, error) { if r == ZR { return "0", nil } + if r == Reg("RSP") { + r = SP + } if _, ok := arm64ParseFReg(r); ok { v, err := c.loadVReg(r) if err != nil { @@ -469,6 +1028,9 @@ func (c *arm64Ctx) storeReg(r Reg, v string) error { if r == ZR { return nil } + if r == Reg("RSP") { + r = SP + } if _, ok := arm64ParseFReg(r); ok { lanes := c.newTmp() fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> zeroinitializer, i64 %s, i64 0\n", lanes, v) diff --git a/arm64_eval.go b/arm64_eval.go index a68bf397..0db933ce 100644 --- a/arm64_eval.go +++ b/arm64_eval.go @@ -14,6 +14,12 @@ func (c *arm64Ctx) imm64(n int64) string { // If postInc is true, mem.Off is treated as post-increment (address displacement is 0). func (c *arm64Ctx) addrI64(mem MemRef, postInc bool) (addr string, base Reg, inc int64, err error) { base = mem.Base + // Register encoding 31 denotes SP in an address operand even when the Go + // source spells it ZR. RSP is the explicit hardware-stack-pointer spelling; + // both use the same modeled stack-pointer slot. + if base == ZR || base == Reg("RSP") { + base = SP + } baseVal, err := c.loadReg(base) if err != nil { return "", "", 0, err @@ -372,19 +378,11 @@ func (c *arm64Ctx) evalFPValue64(op Operand) (string, error) { if !ok { return "", fmt.Errorf("arm64: unsupported FP param slot: %s", op.String()) } - idx := slot.Index - if idx < 0 || idx >= len(c.sig.Args) { - return "", fmt.Errorf("arm64: FP slot %s invalid arg index %d", op.String(), idx) + arg, err := c.loadFPParameter(slot) + if err != nil { + return "", err } - arg := fmt.Sprintf("%%arg%d", idx) - ty := slot.Type - if slot.Field >= 0 { - aggTy := c.sig.Args[idx] - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", t, aggTy, arg, slot.Field) - arg = "%" + t - } switch string(ty) { case "i64": @@ -414,10 +412,16 @@ func (c *arm64Ctx) evalFPValue64(op Operand) (string, error) { func (c *arm64Ctx) evalFPAddr64(op Operand) (string, error) { p, ok := c.fpResAllocaOff[op.FPOffset] + result := ok + if !ok { + p, ok = c.fpParamAlloca[op.FPOffset] + } if !ok { return "0", nil } - c.markFPResultAddrTaken(op.FPOffset) + if result { + c.markFPResultAddrTaken(op.FPOffset) + } t := c.newTmp() fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %s to i64\n", t, p) return "%" + t, nil diff --git a/arm64_flags.go b/arm64_flags.go index e5873665..4f10cc4c 100644 --- a/arm64_flags.go +++ b/arm64_flags.go @@ -10,6 +10,10 @@ func (c *arm64Ctx) storeFlag(slot string, v string) { } func (c *arm64Ctx) setFlagsSub(dst, src, res string) { + c.setFlagsSubWithCarry(dst, src, res, "") +} + +func (c *arm64Ctx) setFlagsSubWithCarry(dst, src, res, carryValue string) { // NZCV for subtraction: // Z: res==0 // N: res<0 (signed) @@ -21,8 +25,12 @@ func (c *arm64Ctx) setFlagsSub(dst, src, res string) { fmt.Fprintf(c.b, " %%%s = icmp eq i64 %s, 0\n", z, res) n := c.newTmp() fmt.Fprintf(c.b, " %%%s = icmp slt i64 %s, 0\n", n, res) - carry := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp uge i64 %s, %s\n", carry, dst, src) + carry := carryValue + if carry == "" { + t := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp uge i64 %s, %s\n", t, dst, src) + carry = "%" + t + } // overflow = ((dst ^ src) & (dst ^ res)) < 0 x1 := c.newTmp() @@ -36,11 +44,15 @@ func (c *arm64Ctx) setFlagsSub(dst, src, res string) { c.storeFlag(c.flagsZSlot, "%"+z) c.storeFlag(c.flagsNSlot, "%"+n) - c.storeFlag(c.flagsCSlot, "%"+carry) + c.storeFlag(c.flagsCSlot, carry) c.storeFlag(c.flagsVSlot, "%"+ov) } func (c *arm64Ctx) setFlagsSub32(dst, src, res string) { + c.setFlagsSub32WithCarry(dst, src, res, "") +} + +func (c *arm64Ctx) setFlagsSub32WithCarry(dst, src, res, carryValue string) { // SUBSW computes NZCV from the low 32 bits, before the architectural // zero-extension of the result into the 64-bit register file. c.flagsWritten = true @@ -49,8 +61,12 @@ func (c *arm64Ctx) setFlagsSub32(dst, src, res string) { fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 0\n", z, res) n := c.newTmp() fmt.Fprintf(c.b, " %%%s = icmp slt i32 %s, 0\n", n, res) - carry := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp uge i32 %s, %s\n", carry, dst, src) + carry := carryValue + if carry == "" { + t := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp uge i32 %s, %s\n", t, dst, src) + carry = "%" + t + } x1 := c.newTmp() fmt.Fprintf(c.b, " %%%s = xor i32 %s, %s\n", x1, dst, src) x2 := c.newTmp() @@ -62,11 +78,15 @@ func (c *arm64Ctx) setFlagsSub32(dst, src, res string) { c.storeFlag(c.flagsZSlot, "%"+z) c.storeFlag(c.flagsNSlot, "%"+n) - c.storeFlag(c.flagsCSlot, "%"+carry) + c.storeFlag(c.flagsCSlot, carry) c.storeFlag(c.flagsVSlot, "%"+ov) } func (c *arm64Ctx) setFlagsAdd(dst, src, res string) { + c.setFlagsAddWithCarry(dst, src, res, "") +} + +func (c *arm64Ctx) setFlagsAddWithCarry(dst, src, res, carryValue string) { // NZCV for addition: // Z: res==0 // N: res<0 (signed) @@ -78,8 +98,12 @@ func (c *arm64Ctx) setFlagsAdd(dst, src, res string) { fmt.Fprintf(c.b, " %%%s = icmp eq i64 %s, 0\n", z, res) n := c.newTmp() fmt.Fprintf(c.b, " %%%s = icmp slt i64 %s, 0\n", n, res) - carry := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ult i64 %s, %s\n", carry, res, dst) + carry := carryValue + if carry == "" { + t := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i64 %s, %s\n", t, res, dst) + carry = "%" + t + } // overflow = (~(dst ^ src) & (dst ^ res)) < 0 x1 := c.newTmp() @@ -95,7 +119,42 @@ func (c *arm64Ctx) setFlagsAdd(dst, src, res string) { c.storeFlag(c.flagsZSlot, "%"+z) c.storeFlag(c.flagsNSlot, "%"+n) - c.storeFlag(c.flagsCSlot, "%"+carry) + c.storeFlag(c.flagsCSlot, carry) + c.storeFlag(c.flagsVSlot, "%"+ov) +} + +func (c *arm64Ctx) setFlagsAdd32(dst, src, res string) { + c.setFlagsAdd32WithCarry(dst, src, res, "") +} + +func (c *arm64Ctx) setFlagsAdd32WithCarry(dst, src, res, carryValue string) { + // ADDSW/CMNW compute flags from the low 32-bit sum. + c.flagsWritten = true + + z := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 0\n", z, res) + n := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i32 %s, 0\n", n, res) + carry := carryValue + if carry == "" { + t := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i32 %s, %s\n", t, res, dst) + carry = "%" + t + } + x1 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i32 %s, %s\n", x1, dst, src) + nx1 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i32 %%%s, -1\n", nx1, x1) + x2 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i32 %s, %s\n", x2, dst, res) + x3 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i32 %%%s, %%%s\n", x3, nx1, x2) + ov := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt i32 %%%s, 0\n", ov, x3) + + c.storeFlag(c.flagsZSlot, "%"+z) + c.storeFlag(c.flagsNSlot, "%"+n) + c.storeFlag(c.flagsCSlot, carry) c.storeFlag(c.flagsVSlot, "%"+ov) } diff --git a/arm64_fp.go b/arm64_fp.go index f067d64e..967151a7 100644 --- a/arm64_fp.go +++ b/arm64_fp.go @@ -11,6 +11,16 @@ func (c *arm64Ctx) fpResultSlotByOffset(off int64) (slot FrameSlot, ok bool) { return FrameSlot{}, false } +func (c *arm64Ctx) loadFPParameter(slot FrameSlot) (string, error) { + p, ok := c.fpParamAlloca[slot.Offset] + if !ok { + return "", fmt.Errorf("arm64: missing FP parameter alloca for +%d(FP)", slot.Offset) + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s\n", value, slot.Type, p) + return "%" + value, nil +} + func (c *arm64Ctx) markFPResultWritten(off int64) { if s, ok := c.fpResultSlotByOffset(off); ok { c.fpResWritten[s.Index] = true @@ -25,38 +35,50 @@ func (c *arm64Ctx) markFPResultAddrTaken(off int64) { func (c *arm64Ctx) storeFPResult64(off int64, v64 string) error { slot, ok := c.fpResAllocaOff[off] + meta, isResult := c.fpResultSlotByOffset(off) if !ok { - return fmt.Errorf("arm64: unsupported FP result slot +%d(FP)", off) + slot, ok = c.fpParamAlloca[off] + var found bool + meta, found = c.fpParams[off] + if !ok || !found { + return fmt.Errorf("arm64: unsupported FP slot +%d(FP)", off) + } } - // Find the element type via FrameSlot. - meta, found := c.fpResultSlotByOffset(off) - if !found { - return fmt.Errorf("arm64: missing FP result metadata for +%d(FP)", off) + if meta.Type == "" { + return fmt.Errorf("arm64: unsupported FP slot +%d(FP)", off) } ty := meta.Type switch string(ty) { case "i64": fmt.Fprintf(c.b, " store i64 %s, ptr %s\n", v64, slot) - c.markFPResultWritten(off) + if isResult { + c.markFPResultWritten(off) + } return nil case "i32", "i16", "i8", "i1": t := c.newTmp() fmt.Fprintf(c.b, " %%%s = trunc i64 %s to %s\n", t, v64, ty) fmt.Fprintf(c.b, " store %s %%%s, ptr %s\n", ty, t, slot) - c.markFPResultWritten(off) + if isResult { + c.markFPResultWritten(off) + } return nil case "ptr": t := c.newTmp() fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", t, v64) fmt.Fprintf(c.b, " store ptr %%%s, ptr %s\n", t, slot) - c.markFPResultWritten(off) + if isResult { + c.markFPResultWritten(off) + } return nil case "double": t := c.newTmp() fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to double\n", t, v64) fmt.Fprintf(c.b, " store double %%%s, ptr %s\n", t, slot) - c.markFPResultWritten(off) + if isResult { + c.markFPResultWritten(off) + } return nil case "float": t := c.newTmp() @@ -64,7 +86,9 @@ func (c *arm64Ctx) storeFPResult64(off int64, v64 string) error { b := c.newTmp() fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", b, t) fmt.Fprintf(c.b, " store float %%%s, ptr %s\n", b, slot) - c.markFPResultWritten(off) + if isResult { + c.markFPResultWritten(off) + } return nil default: return fmt.Errorf("arm64: unsupported FP result slot type %q", ty) diff --git a/arm64_fp_parameter_test.go b/arm64_fp_parameter_test.go new file mode 100644 index 00000000..69ace9ec --- /dev/null +++ b/arm64_fp_parameter_test.go @@ -0,0 +1,84 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64WritableFPParameterSource = ` +TEXT writablefpparameter(SB),$0-16 + MOVD value+0(FP), R0 + ADD $1, R0 + MOVD R0, value+0(FP) + MOVD value+0(FP), R1 + MOVD R1, result+8(FP) + RET +` + +func arm64WritableFPParameterSignature() FuncSig { + return FuncSig{ + Name: "writablefpparameter", Args: []LLVMType{I64}, Ret: I64, + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: I64, Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 8, Type: I64, Index: 0, Field: -1}}, + }, + } +} + +func TestTranslateARM64WritableFPParameterSlot(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64WritableFPParameterSource, true) + file, err := Parse(ArchARM64, arm64WritableFPParameterSource) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"writablefpparameter": arm64WritableFPParameterSignature()}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "%fp_param_0 = alloca i64") || !strings.Contains(ir, "store i64 %arg0, ptr %fp_param_0") { + t.Fatalf("writable FP parameter slot was not materialized for %s:\n%s", triple, ir) + } + compileLLVMToObject(t, llc, triple, "arm64-writable-fp-parameter.ll", "arm64-writable-fp-parameter.o", ir) + }) + } +} + +func TestARM64WritableFPParameterRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + file, err := Parse(ArchARM64, arm64WritableFPParameterSource) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"writablefpparameter": arm64WritableFPParameterSignature()}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern uint64_t writablefpparameter(uint64_t); +int main(void) { return writablefpparameter(41) == 42 ? 0 : 1; } +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_writable_fp_parameter", triple, ir, mainC, nil) +} diff --git a/arm64_helper_edge_test.go b/arm64_helper_edge_test.go index 741b7ae5..fed04e56 100644 --- a/arm64_helper_edge_test.go +++ b/arm64_helper_edge_test.go @@ -127,7 +127,7 @@ func TestARM64AtomicCoverage(t *testing.T) { } } - mem := arm64MemOp("R10", 32) + mem := arm64MemOp("R10", 0) for _, tc := range []Instr{ {Op: "LDARW", Args: []Operand{mem, arm64RegOp("R0")}, Raw: "LDARW 32(R10), R0"}, {Op: "LDARB", Args: []Operand{mem, arm64RegOp("R1")}, Raw: "LDARB 32(R10), R1"}, @@ -141,19 +141,19 @@ func TestARM64AtomicCoverage(t *testing.T) { {Op: "STLXRW", Args: []Operand{arm64RegOp("R3"), mem, arm64RegOp("R6")}, Raw: "STLXRW R3, 32(R10), R6"}, {Op: "STLXRB", Args: []Operand{arm64RegOp("R4"), mem, arm64RegOp("R7")}, Raw: "STLXRB R4, 32(R10), R7"}, {Op: "STLXR", Args: []Operand{arm64RegOp("R5"), mem, arm64RegOp("R8")}, Raw: "STLXR R5, 32(R10), R8"}, - {Op: "SWPALB", Args: []Operand{arm64RegOp("R0"), mem, arm64RegOp("R1")}, Raw: "SWPALB R0, 32(R10), R1"}, - {Op: "SWPALW", Args: []Operand{arm64RegOp("R2"), mem, arm64RegOp("R3")}, Raw: "SWPALW R2, 32(R10), R3"}, - {Op: "SWPALD", Args: []Operand{arm64RegOp("R4"), mem, arm64RegOp("R5")}, Raw: "SWPALD R4, 32(R10), R5"}, - {Op: "LDADDALW", Args: []Operand{arm64RegOp("R0"), mem, arm64RegOp("R1")}, Raw: "LDADDALW R0, 32(R10), R1"}, - {Op: "LDADDALD", Args: []Operand{arm64RegOp("R2"), mem, arm64RegOp("R3")}, Raw: "LDADDALD R2, 32(R10), R3"}, - {Op: "LDORALB", Args: []Operand{arm64RegOp("R4"), mem, arm64RegOp("R5")}, Raw: "LDORALB R4, 32(R10), R5"}, - {Op: "LDORALW", Args: []Operand{arm64RegOp("R6"), mem, arm64RegOp("R7")}, Raw: "LDORALW R6, 32(R10), R7"}, - {Op: "LDORALD", Args: []Operand{arm64RegOp("R8"), mem, arm64RegOp("R9")}, Raw: "LDORALD R8, 32(R10), R9"}, - {Op: "LDCLRALB", Args: []Operand{arm64RegOp("R0"), mem, arm64RegOp("R1")}, Raw: "LDCLRALB R0, 32(R10), R1"}, - {Op: "LDCLRALW", Args: []Operand{arm64RegOp("R2"), mem, arm64RegOp("R3")}, Raw: "LDCLRALW R2, 32(R10), R3"}, - {Op: "LDCLRALD", Args: []Operand{arm64RegOp("R4"), mem, arm64RegOp("R5")}, Raw: "LDCLRALD R4, 32(R10), R5"}, - {Op: "CASALW", Args: []Operand{arm64RegOp("R6"), mem, arm64RegOp("R7")}, Raw: "CASALW R6, 32(R10), R7"}, - {Op: "CASALD", Args: []Operand{arm64RegOp("R8"), mem, arm64RegOp("R9")}, Raw: "CASALD R8, 32(R10), R9"}, + {Op: "SWPALB", Args: []Operand{arm64RegOp("R0"), mem, arm64RegOp("R1")}, Raw: "SWPALB R0, (R10), R1"}, + {Op: "SWPALW", Args: []Operand{arm64RegOp("R2"), mem, arm64RegOp("R3")}, Raw: "SWPALW R2, (R10), R3"}, + {Op: "SWPALD", Args: []Operand{arm64RegOp("R4"), mem, arm64RegOp("R5")}, Raw: "SWPALD R4, (R10), R5"}, + {Op: "LDADDALW", Args: []Operand{arm64RegOp("R0"), mem, arm64RegOp("R1")}, Raw: "LDADDALW R0, (R10), R1"}, + {Op: "LDADDALD", Args: []Operand{arm64RegOp("R2"), mem, arm64RegOp("R3")}, Raw: "LDADDALD R2, (R10), R3"}, + {Op: "LDORALB", Args: []Operand{arm64RegOp("R4"), mem, arm64RegOp("R5")}, Raw: "LDORALB R4, (R10), R5"}, + {Op: "LDORALW", Args: []Operand{arm64RegOp("R6"), mem, arm64RegOp("R7")}, Raw: "LDORALW R6, (R10), R7"}, + {Op: "LDORALD", Args: []Operand{arm64RegOp("R8"), mem, arm64RegOp("R9")}, Raw: "LDORALD R8, (R10), R9"}, + {Op: "LDCLRALB", Args: []Operand{arm64RegOp("R0"), mem, arm64RegOp("R1")}, Raw: "LDCLRALB R0, (R10), R1"}, + {Op: "LDCLRALW", Args: []Operand{arm64RegOp("R2"), mem, arm64RegOp("R3")}, Raw: "LDCLRALW R2, (R10), R3"}, + {Op: "LDCLRALD", Args: []Operand{arm64RegOp("R4"), mem, arm64RegOp("R5")}, Raw: "LDCLRALD R4, (R10), R5"}, + {Op: "CASALW", Args: []Operand{arm64RegOp("R6"), mem, arm64RegOp("R7")}, Raw: "CASALW R6, (R10), R7"}, + {Op: "CASALD", Args: []Operand{arm64RegOp("R8"), mem, arm64RegOp("R9")}, Raw: "CASALD R8, (R10), R9"}, } { ok, _, err := c.lowerAtomic(tc.Op, tc) mustLowerARM64(t, "lowerAtomic", tc, ok, err) @@ -251,10 +251,10 @@ func TestARM64ArithmeticCoverage(t *testing.T) { {Op: "ADD", Args: []Operand{arm64ImmOp(2), arm64RegOp("R0")}, Raw: "ADD $2, R0"}, {Op: "SUB", Args: []Operand{arm64ImmOp(3), arm64RegOp("R1"), arm64RegOp("R2")}, Raw: "SUB $3, R1, R2"}, {Op: "ADDS", Args: []Operand{arm64ImmOp(4), arm64RegOp("R2"), arm64RegOp("R3")}, Raw: "ADDS $4, R2, R3"}, - {Op: "ADC", Args: []Operand{arm64ImmOp(5), arm64RegOp("R3")}, Raw: "ADC $5, R3"}, - {Op: "ADCS", Args: []Operand{arm64ImmOp(6), arm64RegOp("R3"), arm64RegOp("R4")}, Raw: "ADCS $6, R3, R4"}, - {Op: "SBC", Args: []Operand{arm64ImmOp(1), arm64RegOp("R4")}, Raw: "SBC $1, R4"}, - {Op: "SBCS", Args: []Operand{arm64ImmOp(2), arm64RegOp("R4"), arm64RegOp("R5")}, Raw: "SBCS $2, R4, R5"}, + {Op: "ADC", Args: []Operand{arm64RegOp("R5"), arm64RegOp("R3")}, Raw: "ADC R5, R3"}, + {Op: "ADCS", Args: []Operand{arm64RegOp("R6"), arm64RegOp("R3"), arm64RegOp("R4")}, Raw: "ADCS R6, R3, R4"}, + {Op: "SBC", Args: []Operand{arm64RegOp("R1"), arm64RegOp("R4")}, Raw: "SBC R1, R4"}, + {Op: "SBCS", Args: []Operand{arm64RegOp("R2"), arm64RegOp("R4"), arm64RegOp("R5")}, Raw: "SBCS R2, R4, R5"}, {Op: "ADDW", Args: []Operand{arm64ImmOp(7), arm64RegOp("R5"), arm64RegOp("R6")}, Raw: "ADDW $7, R5, R6"}, {Op: "SUBW", Args: []Operand{arm64ImmOp(3), arm64RegOp("R6")}, Raw: "SUBW $3, R6"}, {Op: "AND", Args: []Operand{arm64ImmOp(15), arm64RegOp("R6"), arm64RegOp("R7")}, Raw: "AND $15, R6, R7"}, @@ -467,20 +467,20 @@ func TestARM64DataVectorAndBranchCoverage(t *testing.T) { {"VMOV", false, Instr{Op: "VMOV", Args: []Operand{arm64RegOp("R2"), arm64RegOp("V2.D[1]")}, Raw: "VMOV R2, V2.D[1]"}, "vec"}, {"VMOV", false, Instr{Op: "VMOV", Args: []Operand{arm64RegOp("V2.D[1]"), arm64RegOp("R3")}, Raw: "VMOV V2.D[1], R3"}, "vec"}, {"VMOV", false, Instr{Op: "VMOV", Args: []Operand{arm64RegOp("V1"), arm64RegOp("V3")}, Raw: "VMOV V1, V3"}, "vec"}, - {"VEOR", false, Instr{Op: "VEOR", Args: []Operand{arm64RegOp("V0"), arm64RegOp("V1"), arm64RegOp("V4")}, Raw: "VEOR V0, V1, V4"}, "vec"}, - {"VORR", false, Instr{Op: "VORR", Args: []Operand{arm64RegOp("V1"), arm64RegOp("V2"), arm64RegOp("V5")}, Raw: "VORR V1, V2, V5"}, "vec"}, + {"VEOR", false, Instr{Op: "VEOR", Args: []Operand{arm64RegOp("V0.B16"), arm64RegOp("V1.B16"), arm64RegOp("V4.B16")}, Raw: "VEOR V0.B16, V1.B16, V4.B16"}, "vec"}, + {"VORR", false, Instr{Op: "VORR", Args: []Operand{arm64RegOp("V1.B16"), arm64RegOp("V2.B16"), arm64RegOp("V5.B16")}, Raw: "VORR V1.B16, V2.B16, V5.B16"}, "vec"}, {"VLD1", true, Instr{Op: "VLD1.P", Args: []Operand{arm64MemOp("R21", 0), arm64RegOp("V4.B[3]")}, Raw: "VLD1.P (R21), V4.B[3]"}, "vec"}, - {"VLD1", true, Instr{Op: "VLD1.P", Args: []Operand{arm64MemOp("R21", 0), arm64RegListOp("V4", "V5", "V6", "V7")}, Raw: "VLD1.P (R21), [V4, V5, V6, V7]"}, "vec"}, - {"VST1", true, Instr{Op: "VST1.P", Args: []Operand{arm64RegListOp("V4", "V5"), arm64MemOp("R21", 0)}, Raw: "VST1.P [V4, V5], (R21)"}, "vec"}, + {"VLD1", true, Instr{Op: "VLD1.P", Args: []Operand{arm64MemOp("R21", 0), arm64RegListOp("V4.B16", "V5.B16", "V6.B16", "V7.B16")}, Raw: "VLD1.P (R21), [V4.B16, V5.B16, V6.B16, V7.B16]"}, "vec"}, + {"VST1", true, Instr{Op: "VST1.P", Args: []Operand{arm64RegListOp("V4.B16", "V5.B16"), arm64MemOp("R21", 0)}, Raw: "VST1.P [V4.B16, V5.B16], (R21)"}, "vec"}, {"VCMEQ", false, Instr{Op: "VCMEQ", Args: []Operand{arm64RegOp("V4.B16"), arm64RegOp("V5.B16"), arm64RegOp("V6.B16")}, Raw: "VCMEQ V4.B16, V5.B16, V6.B16"}, "vec"}, {"VCMEQ", false, Instr{Op: "VCMEQ", Args: []Operand{arm64RegOp("V4.D2"), arm64RegOp("V5.D2"), arm64RegOp("V7.D2")}, Raw: "VCMEQ V4.D2, V5.D2, V7.D2"}, "vec"}, - {"VAND", false, Instr{Op: "VAND", Args: []Operand{arm64RegOp("V4"), arm64RegOp("V5"), arm64RegOp("V6")}, Raw: "VAND V4, V5, V6"}, "vec"}, + {"VAND", false, Instr{Op: "VAND", Args: []Operand{arm64RegOp("V4.B16"), arm64RegOp("V5.B16"), arm64RegOp("V6.B16")}, Raw: "VAND V4.B16, V5.B16, V6.B16"}, "vec"}, {"VADDP", false, Instr{Op: "VADDP", Args: []Operand{arm64RegOp("V4.B16"), arm64RegOp("V5.B16"), arm64RegOp("V6.B16")}, Raw: "VADDP V4.B16, V5.B16, V6.B16"}, "vec"}, {"VADDP", false, Instr{Op: "VADDP", Args: []Operand{arm64RegOp("V4.D2"), arm64RegOp("V5.D2"), arm64RegOp("V7.D2")}, Raw: "VADDP V4.D2, V5.D2, V7.D2"}, "vec"}, {"VUADDLV", false, Instr{Op: "VUADDLV", Args: []Operand{arm64RegOp("V6.B16"), arm64RegOp("V7")}, Raw: "VUADDLV V6.B16, V7"}, "vec"}, {"VADD", false, Instr{Op: "VADD", Args: []Operand{arm64RegOp("V4.S4"), arm64RegOp("V5.S4"), arm64RegOp("V6.S4")}, Raw: "VADD V4.S4, V5.S4, V6.S4"}, "vec"}, - {"VADD", false, Instr{Op: "VADD", Args: []Operand{arm64RegOp("V6.D2"), arm64RegOp("V7.D2")}, Raw: "VADD V6.D2, V7.D2"}, "vec"}, - {"AESE", false, Instr{Op: "AESE", Args: []Operand{arm64RegOp("V0"), arm64RegOp("V1"), arm64RegOp("V2")}, Raw: "AESE V0, V1, V2"}, "vec"}, + {"VADD", false, Instr{Op: "VADD", Args: []Operand{arm64RegOp("V5.D2"), arm64RegOp("V6.D2"), arm64RegOp("V7.D2")}, Raw: "VADD V5.D2, V6.D2, V7.D2"}, "vec"}, + {"VDUP", false, Instr{Op: "VDUP", Args: []Operand{arm64RegOp("V0.B[0]"), arm64RegOp("V1.B16")}, Raw: "VDUP V0.B[0], V1.B16"}, "vec"}, } { switch tc.kind { case "data": @@ -516,7 +516,7 @@ func TestARM64DataVectorAndBranchCoverage(t *testing.T) { emitCondBr := arm64TestEmitCondBr(c) for _, tc := range []Instr{ {Op: "BL", Args: []Operand{arm64RegOp("R0")}, Raw: "BL R0"}, - {Op: "CALL", Args: []Operand{arm64MemOp("R20", 8)}, Raw: "CALL 8(R20)"}, + {Op: "CALL", Args: []Operand{arm64MemOp("R20", 0)}, Raw: "CALL (R20)"}, {Op: "BL", Args: []Operand{arm64SymOp("helper(SB)")}, Raw: "BL helper(SB)"}, {Op: "B", Args: []Operand{arm64RegOp("R1")}, Raw: "B R1"}, {Op: "JMP", Args: []Operand{arm64MemOp("R20", 8)}, Raw: "JMP 8(R20)"}, @@ -627,7 +627,12 @@ func TestARM64FPOpsCoverage(t *testing.T) { }, }, } - c, b := newARM64CtxWithFuncForTest(t, Func{}, sig, nil) + c, b := newARM64CtxWithFuncForTest(t, Func{Instrs: []Instr{{ + Op: "FMOVD", + Args: []Operand{ + arm64RegOp("F0"), arm64RegOp("F1"), arm64RegOp("F2"), arm64RegOp("F3"), arm64RegOp("F4"), + }, + }}}, sig, nil) check := func(kind string, ins Instr, ok bool, err error) { t.Helper() if err != nil { @@ -653,27 +658,27 @@ func TestARM64FPOpsCoverage(t *testing.T) { } for _, ins := range []Instr{ - {Op: "FMOVD", Args: []Operand{arm64SymOp("$1.5"), arm64RegOp("R0")}, Raw: "FMOVD $1.5, R0"}, - {Op: "FMOVD", Args: []Operand{arm64SymOp("$0x10"), arm64FPOp(48)}, Raw: "FMOVD $0x10, ret+48(FP)"}, - {Op: "FCMPD", Args: []Operand{arm64FPOp(0), arm64RegOp("R0")}, Raw: "FCMPD arg+0(FP), R0"}, - {Op: "FCSELD", Args: []Operand{arm64IdentOp("EQ"), arm64FPOp(0), arm64FPOp(8), arm64RegOp("R1")}, Raw: "FCSELD EQ, arg+0(FP), arg+8(FP), R1"}, - {Op: "FADDD", Args: []Operand{arm64FPOp(0), arm64RegOp("R1")}, Raw: "FADDD arg+0(FP), R1"}, - {Op: "FSUBD", Args: []Operand{arm64FPOp(8), arm64RegOp("R1"), arm64RegOp("R2")}, Raw: "FSUBD arg+8(FP), R1, R2"}, - {Op: "FMULD", Args: []Operand{arm64FPOp(16), arm64RegOp("R2")}, Raw: "FMULD arg+16(FP), R2"}, - {Op: "FDIVD", Args: []Operand{arm64FPOp(24), arm64RegOp("R2"), arm64FPOp(48)}, Raw: "FDIVD arg+24(FP), R2, ret+48(FP)"}, - {Op: "FMAXD", Args: []Operand{arm64FPOp(32), arm64RegOp("R2")}, Raw: "FMAXD arg+32(FP), R2"}, - {Op: "FMIND", Args: []Operand{arm64FPOp(40), arm64RegOp("R2"), arm64RegOp("R3")}, Raw: "FMIND arg+40(FP), R2, R3"}, - {Op: "FMADDD", Args: []Operand{arm64FPOp(0), arm64FPOp(8), arm64FPOp(16), arm64RegOp("R3")}, Raw: "FMADDD arg+0(FP), arg+8(FP), arg+16(FP), R3"}, - {Op: "FMSUBD", Args: []Operand{arm64FPOp(8), arm64FPOp(16), arm64FPOp(24), arm64RegOp("R4")}, Raw: "FMSUBD arg+8(FP), arg+16(FP), arg+24(FP), R4"}, - {Op: "FNMSUBD", Args: []Operand{arm64FPOp(16), arm64FPOp(24), arm64FPOp(32), arm64FPOp(56)}, Raw: "FNMSUBD arg+16(FP), arg+24(FP), arg+32(FP), ret+56(FP)"}, - {Op: "FNMULD", Args: []Operand{arm64FPOp(0), arm64RegOp("R3")}, Raw: "FNMULD arg+0(FP), R3"}, - {Op: "FNMULD", Args: []Operand{arm64FPOp(8), arm64FPOp(16), arm64RegOp("R4")}, Raw: "FNMULD arg+8(FP), arg+16(FP), R4"}, - {Op: "FABSD", Args: []Operand{arm64RegOp("R4"), arm64FPOp(48)}, Raw: "FABSD R4, ret+48(FP)"}, - {Op: "FRINTZD", Args: []Operand{arm64FPOp(0), arm64RegOp("R0")}, Raw: "FRINTZD arg+0(FP), R0"}, - {Op: "FRINTMD", Args: []Operand{arm64FPOp(8), arm64RegOp("R1")}, Raw: "FRINTMD arg+8(FP), R1"}, - {Op: "FRINTPD", Args: []Operand{arm64FPOp(16), arm64FPOp(56)}, Raw: "FRINTPD arg+16(FP), ret+56(FP)"}, - {Op: "FCVTZSD", Args: []Operand{arm64FPOp(0), arm64RegOp("R2")}, Raw: "FCVTZSD arg+0(FP), R2"}, - {Op: "SCVTFD", Args: []Operand{arm64RegOp("R2"), arm64RegOp("R3")}, Raw: "SCVTFD R2, R3"}, + {Op: "FMOVD", Args: []Operand{arm64ImmOp(0), arm64RegOp("F0")}, Raw: "FMOVD $0, F0"}, + {Op: "FMOVD", Args: []Operand{arm64RegOp("F0"), arm64FPOp(48)}, Raw: "FMOVD F0, ret+48(FP)"}, + {Op: "FCMPD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F1")}, Raw: "FCMPD F0, F1"}, + {Op: "FCSELD", Args: []Operand{arm64IdentOp("EQ"), arm64RegOp("F0"), arm64RegOp("F1"), arm64RegOp("F2")}, Raw: "FCSELD EQ, F0, F1, F2"}, + {Op: "FADDD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F1")}, Raw: "FADDD F0, F1"}, + {Op: "FSUBD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F1"), arm64RegOp("F2")}, Raw: "FSUBD F0, F1, F2"}, + {Op: "FMULD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F2")}, Raw: "FMULD F0, F2"}, + {Op: "FDIVD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F2"), arm64RegOp("F3")}, Raw: "FDIVD F0, F2, F3"}, + {Op: "FMAXD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F2")}, Raw: "FMAXD F0, F2"}, + {Op: "FMIND", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F2"), arm64RegOp("F3")}, Raw: "FMIND F0, F2, F3"}, + {Op: "FMADDD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F1"), arm64RegOp("F2"), arm64RegOp("F3")}, Raw: "FMADDD F0, F1, F2, F3"}, + {Op: "FMSUBD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F1"), arm64RegOp("F2"), arm64RegOp("F4")}, Raw: "FMSUBD F0, F1, F2, F4"}, + {Op: "FNMSUBD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F1"), arm64RegOp("F2"), arm64RegOp("F4")}, Raw: "FNMSUBD F0, F1, F2, F4"}, + {Op: "FNMULD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F3")}, Raw: "FNMULD F0, F3"}, + {Op: "FNMULD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F1"), arm64RegOp("F4")}, Raw: "FNMULD F0, F1, F4"}, + {Op: "FABSD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("F4")}, Raw: "FABSD F0, F4"}, + {Op: "FRINTZD", Args: []Operand{arm64RegOp("F1"), arm64RegOp("F2")}, Raw: "FRINTZD F1, F2"}, + {Op: "FRINTMD", Args: []Operand{arm64RegOp("F2"), arm64RegOp("F3")}, Raw: "FRINTMD F2, F3"}, + {Op: "FRINTPD", Args: []Operand{arm64RegOp("F3"), arm64RegOp("F4")}, Raw: "FRINTPD F3, F4"}, + {Op: "FCVTZSD", Args: []Operand{arm64RegOp("F0"), arm64RegOp("R2")}, Raw: "FCVTZSD F0, R2"}, + {Op: "SCVTFD", Args: []Operand{arm64RegOp("R2"), arm64RegOp("F3")}, Raw: "SCVTFD R2, F3"}, } { ok, _, err := c.lowerFP(ins.Op, ins) check("lowerFP", ins, ok, err) @@ -753,13 +758,13 @@ func TestARM64FPOpsCoverage(t *testing.T) { "fmul double", "fdiv double", "fneg double", - "@llvm.maxnum.f64", - "@llvm.minnum.f64", + "@llvm.maximum.f64", + "@llvm.minimum.f64", "@llvm.fabs.f64", "@llvm.trunc.f64", "@llvm.floor.f64", "@llvm.ceil.f64", - "fptosi double", + "@llvm.fptosi.sat.i64.f64", "sitofp i64", "fpext float", "ptrtoint ptr", @@ -852,8 +857,8 @@ func TestARM64BranchAndReturnEdgeCoverage(t *testing.T) { sigs := map[string]FuncSig{ "example.structSink": {Name: "example.structSink", Args: []LLVMType{LLVMType("{ i32, i64 }")}, Ret: Void}, - "example.badarg": {Name: "example.badarg", Args: []LLVMType{LLVMType("double")}, Ret: Void}, - "example.badret": {Name: "example.badret", Args: []LLVMType{I64}, Ret: LLVMType("double")}, + "example.badarg": {Name: "example.badarg", Args: []LLVMType{LLVMType("<2 x i64>")}, Ret: Void}, + "example.badret": {Name: "example.badret", Args: []LLVMType{I64}, Ret: LLVMType("<2 x i64>")}, "example.aggregate": {Name: "example.aggregate", Ret: LLVMType("{ ptr, i64 }")}, "example.voidsame": {Name: "example.voidsame", Args: []LLVMType{I64}, Ret: Void}, "example.badtailret": {Name: "example.badtailret", Args: []LLVMType{I64}, Ret: LLVMType("double")}, @@ -951,6 +956,68 @@ func TestARM64FPEdgeErrors(t *testing.T) { } } +func TestARM64TailCallReturnIntegerWidths(t *testing.T) { + integerTypes := []LLVMType{I1, I8, I16, I32, I64} + for _, calleeType := range integerTypes { + for _, callerType := range integerTypes { + if calleeType == callerType { + continue + } + name := fmt.Sprintf("%s_to_%s", calleeType, callerType) + t.Run(name, func(t *testing.T) { + callee := "example.return_" + name + c, b := newARM64CtxWithFuncForTest(t, Func{}, FuncSig{ + Name: "example.caller_" + name, + Ret: callerType, + }, map[string]FuncSig{ + callee: {Name: callee, Ret: calleeType}, + }) + if err := c.tailCallAndRet(arm64SymOp(callee + "(SB)")); err != nil { + t.Fatalf("tailCallAndRet(%s -> %s) error = %v", calleeType, callerType, err) + } + conversion := "zext" + calleeBits, _ := armIntegerTypeWidth(calleeType) + callerBits, _ := armIntegerTypeWidth(callerType) + if calleeBits > callerBits { + conversion = "trunc" + } + for _, want := range []string{ + fmt.Sprintf("%s %s", conversion, calleeType), + fmt.Sprintf("to %s", callerType), + fmt.Sprintf("ret %s %%", callerType), + } { + if !strings.Contains(b.String(), want) { + t.Fatalf("tailCallAndRet(%s -> %s) missing %q:\n%s", calleeType, callerType, want, b.String()) + } + } + }) + } + } + + for _, tc := range []struct { + name string + calleeType LLVMType + callerType LLVMType + conversion string + }{ + {name: "pointer_to_integer", calleeType: Ptr, callerType: I64, conversion: "ptrtoint ptr"}, + {name: "integer_to_pointer", calleeType: I64, callerType: Ptr, conversion: "inttoptr i64"}, + } { + t.Run(tc.name, func(t *testing.T) { + callee := "example." + tc.name + c, b := newARM64CtxWithFuncForTest(t, Func{}, FuncSig{Name: "example.caller_" + tc.name, Ret: tc.callerType}, map[string]FuncSig{ + callee: {Name: callee, Ret: tc.calleeType}, + }) + if err := c.tailCallAndRet(arm64SymOp(callee + "(SB)")); err != nil { + t.Fatalf("tailCallAndRet(%s -> %s) error = %v", tc.calleeType, tc.callerType, err) + } + if got := b.String(); !strings.Contains(got, tc.conversion) || !strings.Contains(got, fmt.Sprintf("ret %s %%", tc.callerType)) { + t.Fatalf("tailCallAndRet(%s -> %s) output:\n%s", tc.calleeType, tc.callerType, got) + } + }) + } +} + func TestARM64SyscallCoverage(t *testing.T) { c, b := newARM64CtxWithFuncForTest(t, Func{}, FuncSig{Name: "example.syscall", Ret: Void}, nil) for _, tc := range []struct { @@ -1072,7 +1139,7 @@ func TestARM64ArithmeticErrorCoverage(t *testing.T) { {Op: "MUL", Raw: "MUL $1", Args: []Operand{arm64ImmOp(1)}}, {Op: "MUL", Raw: "MUL $1, label", Args: []Operand{arm64ImmOp(1), arm64IdentOp("label")}}, {Op: "MUL", Raw: "MUL $1, R0, label", Args: []Operand{arm64ImmOp(1), arm64RegOp("R0"), arm64IdentOp("label")}}, - {Op: "UMULH", Raw: "UMULH R0, R1", Args: []Operand{arm64RegOp("R0"), arm64RegOp("R1")}}, + {Op: "UMULH", Raw: "UMULH R0", Args: []Operand{arm64RegOp("R0")}}, {Op: "MADDW", Raw: "MADDW R0, R1, R2", Args: []Operand{arm64RegOp("R0"), arm64RegOp("R1"), arm64RegOp("R2")}}, {Op: "MADDW", Raw: "MADDW label, R1, R2, R3", Args: []Operand{arm64IdentOp("label"), arm64RegOp("R1"), arm64RegOp("R2"), arm64RegOp("R3")}}, {Op: "MADDW", Raw: "MADDW R0, label, R2, R3", Args: []Operand{arm64RegOp("R0"), arm64IdentOp("label"), arm64RegOp("R2"), arm64RegOp("R3")}}, @@ -1245,7 +1312,6 @@ func TestARM64VectorEdgeCoverage(t *testing.T) { } } - check("VLD1R", false, Instr{Op: "VLD1R", Raw: "VLD1R (R20), V0"}) check("VMOV", false, Instr{Op: "VMOV", Raw: "VMOV R0, V0.S4", Args: []Operand{arm64RegOp("R0"), arm64RegOp("V0.S4")}}) check("VMOV", false, Instr{Op: "VMOV", Raw: "VMOV V0.S[2], R3", Args: []Operand{arm64RegOp("V0.S[2]"), arm64RegOp("R3")}}) check("VMOV", false, Instr{Op: "VMOV", Raw: "VMOV V1.H[4], R4", Args: []Operand{arm64RegOp("V1.H[4]"), arm64RegOp("R4")}}) @@ -1254,10 +1320,10 @@ func TestARM64VectorEdgeCoverage(t *testing.T) { check("VLD1", true, Instr{Op: "VLD1.P", Raw: "VLD1.P (R20), V3.D[1]", Args: []Operand{arm64MemOp("R20", 0), arm64RegOp("V3.D[1]")}}) check("VLD1", true, Instr{Op: "VLD1.P", Raw: "VLD1.P (R20), V4.S[1]", Args: []Operand{arm64MemOp("R20", 0), arm64RegOp("V4.S[1]")}}) check("VLD1", true, Instr{Op: "VLD1.P", Raw: "VLD1.P (R20), V5.H[3]", Args: []Operand{arm64MemOp("R20", 0), arm64RegOp("V5.H[3]")}}) - check("VLD1", true, Instr{Op: "VLD1.P", Raw: "VLD1.P (R20), [V6]", Args: []Operand{arm64MemOp("R20", 0), arm64RegListOp("V6")}}) - check("VLD1", true, Instr{Op: "VLD1.P", Raw: "VLD1.P (R20), [V7, V8, V9]", Args: []Operand{arm64MemOp("R20", 0), arm64RegListOp("V7", "V8", "V9")}}) - check("VST1", true, Instr{Op: "VST1.P", Raw: "VST1.P [V0], (R20)", Args: []Operand{arm64RegListOp("V0"), arm64MemOp("R20", 0)}}) - check("VST1", true, Instr{Op: "VST1.P", Raw: "VST1.P [V1, V2, V3], (R20)", Args: []Operand{arm64RegListOp("V1", "V2", "V3"), arm64MemOp("R20", 0)}}) + check("VLD1", true, Instr{Op: "VLD1.P", Raw: "VLD1.P (R20), [V6.B16]", Args: []Operand{arm64MemOp("R20", 0), arm64RegListOp("V6.B16")}}) + check("VLD1", true, Instr{Op: "VLD1.P", Raw: "VLD1.P (R20), [V7.B16, V8.B16, V9.B16]", Args: []Operand{arm64MemOp("R20", 0), arm64RegListOp("V7.B16", "V8.B16", "V9.B16")}}) + check("VST1", true, Instr{Op: "VST1.P", Raw: "VST1.P [V0.B16], (R20)", Args: []Operand{arm64RegListOp("V0.B16"), arm64MemOp("R20", 0)}}) + check("VST1", true, Instr{Op: "VST1.P", Raw: "VST1.P [V1.B16, V2.B16, V3.B16], (R20)", Args: []Operand{arm64RegListOp("V1.B16", "V2.B16", "V3.B16"), arm64MemOp("R20", 0)}}) for _, tc := range []Instr{ {Op: "VMOV", Raw: "VMOV R0", Args: []Operand{arm64RegOp("R0")}}, @@ -1310,12 +1376,12 @@ func TestARM64BranchErrorCoverage(t *testing.T) { sigs := map[string]FuncSig{ "example.ret8": {Name: "example.ret8", Args: []LLVMType{I64}, Ret: I8}, "example.retptr": {Name: "example.retptr", Args: []LLVMType{I64}, Ret: Ptr}, - "example.badarg": {Name: "example.badarg", Args: []LLVMType{LLVMType("double")}, Ret: Void}, - "example.badret": {Name: "example.badret", Args: []LLVMType{I64}, Ret: LLVMType("double")}, + "example.badarg": {Name: "example.badarg", Args: []LLVMType{LLVMType("<2 x i64>")}, Ret: Void}, + "example.badret": {Name: "example.badret", Args: []LLVMType{I64}, Ret: LLVMType("<2 x i64>")}, "example.badagg": {Name: "example.badagg", Args: []LLVMType{LLVMType("{ i32, double }")}, Ret: Void}, "example.badargreg": {Name: "example.badargreg", Args: []LLVMType{I64}, ArgRegs: []Reg{"BAD"}, Ret: Void}, "example.casttail": {Name: "example.casttail", Args: []LLVMType{I32, I64, I64, Ptr}, Ret: I64}, - "example.badtailtype": {Name: "example.badtailtype", Args: []LLVMType{LLVMType("double")}, ArgRegs: []Reg{"R0"}, Ret: I64}, + "example.badtailtype": {Name: "example.badtailtype", Args: []LLVMType{LLVMType("<2 x i64>")}, ArgRegs: []Reg{"R0"}, Ret: I64}, "example.structtail": {Name: "example.structtail", Args: []LLVMType{LLVMType("{ i32, i64 }")}, Ret: I64}, "example.badtailreg": {Name: "example.badtailreg", Args: []LLVMType{LLVMType("double")}, ArgRegs: []Reg{"BAD"}, Ret: I64}, "example.voidsink2": {Name: "example.voidsink2", Args: []LLVMType{I64}, Ret: Void}, @@ -1477,10 +1543,11 @@ func TestARM64BranchErrorCoverage(t *testing.T) { t.Fatalf("tailCallAndRet(casttail) error = %v", err) } for _, want := range []string{ - "trunc i64 %t3 to i32", + "trunc i64", + "to i32", "load i64, ptr %reg_R1", "load i64, ptr %reg_R2", - "inttoptr i64 %t7 to ptr", + "inttoptr i64", } { if !strings.Contains(bTailCast.String(), want) { t.Fatalf("tailCallAndRet(casttail) missing %q:\n%s", want, bTailCast.String()) @@ -1752,18 +1819,20 @@ func TestARM64EvalCoverage(t *testing.T) { t.Fatalf("eval64(bad field type) unexpectedly succeeded") } - cBadIndex, _ := newARM64CtxWithFuncForTest(t, Func{}, FuncSig{ + badIndexSig := FuncSig{ Name: "example.badidx", Args: []LLVMType{I64}, Ret: Void, Frame: FrameLayout{ Params: []FrameSlot{{Offset: 0, Type: I64, Index: 2}}, }, - }, nil) - if _, err := cBadIndex.eval64(Operand{Kind: OpFP, FPOffset: 0}, false); err == nil { - t.Fatalf("eval64(bad fp index) unexpectedly succeeded") } - if _, err := cBadIndex.eval64(Operand{Kind: OpMem, Mem: MemRef{Base: "BAD"}}, false); err == nil { + var badIndexOutput strings.Builder + cBadIndex := newARM64Ctx(&badIndexOutput, Func{}, badIndexSig, testResolveSym("example"), nil, false) + if err := cBadIndex.emitEntryAllocasAndArgInit(); err == nil { + t.Fatalf("entry initialization with bad FP argument index unexpectedly succeeded") + } + if _, err := c.eval64(Operand{Kind: OpMem, Mem: MemRef{Base: "BAD"}}, false); err == nil { t.Fatalf("eval64(bad mem base) unexpectedly succeeded") } diff --git a/arm64_lower_acquire_release_complete_test.go b/arm64_lower_acquire_release_complete_test.go new file mode 100644 index 00000000..9791668e --- /dev/null +++ b/arm64_lower_acquire_release_complete_test.go @@ -0,0 +1,68 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64AcquireReleaseCompleteFormats(t *testing.T) { + const source = `TEXT acquireReleaseComplete(SB),$0-0 + LDARB (R6), R7 + LDARH (R6), R7 + LDARW (R6), R7 + LDAR (R6), R7 + STLRB R5, (R6) + STLRH R5, (R6) + STLRW R5, (R6) + STLR R5, (R6) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "acquireReleaseComplete": {Name: "acquireReleaseComplete", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "load atomic i8", "load atomic i16", "load atomic i32", "load atomic i64", + "store atomic i8", "store atomic i16", "store atomic i32", "store atomic i64", " acquire", " release", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 acquire/release lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-acquire-release.ll", "arm64-acquire-release.o", ll) +} + +func TestTranslateARM64AcquireReleaseRejectsOffsetMemory(t *testing.T) { + for _, instruction := range []string{"LDARH 2(R1), R2", "STLRH R0, 2(R1)"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 acquire/release optab", instruction) + } + } +} diff --git a/arm64_lower_add_flags.go b/arm64_lower_add_flags.go new file mode 100644 index 00000000..bc49d390 --- /dev/null +++ b/arm64_lower_add_flags.go @@ -0,0 +1,112 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64AddFlags(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ADDS" && op != "ADDSW" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects 2 or 3 operands: %q", op, ins.Raw) + } + word := op == "ADDSW" + if !arm64AddFlagsSourceValid(ins.Args[0], word) { + return true, false, fmt.Errorf("arm64 %s invalid first operand: %q", op, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg || !isARM64GeneralOrZeroReg(destination.Reg) { + return true, false, fmt.Errorf("arm64 %s destination must be a general register: %q", op, ins.Raw) + } + leftOperand := destination + if len(ins.Args) == 3 { + leftOperand = ins.Args[1] + leftGeneral := leftOperand.Kind == OpReg && isARM64GeneralOrZeroReg(leftOperand.Reg) + leftStack := leftOperand.Kind == OpReg && (leftOperand.Reg == SP || leftOperand.Reg == Reg("RSP")) + if !leftGeneral && !leftStack { + return true, false, fmt.Errorf("arm64 %s second operand must be a general or stack register: %q", op, ins.Raw) + } + if leftStack && ins.Args[0].Kind == OpRegShift && + (ins.Args[0].ShiftOp != ShiftLeft || ins.Args[0].ShiftAmount > 4) { + return true, false, fmt.Errorf("arm64 %s with RSP accepts only a left-shifted register by 0..4: %q", op, ins.Raw) + } + } + + if word { + right, err := c.eval32(ins.Args[0]) + if err != nil { + return true, false, err + } + left, err := c.eval32(leftOperand) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %s\n", result, left, right) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, result) + if err := c.storeReg(destination.Reg, "%"+wide); err != nil { + return true, false, err + } + c.setFlagsAdd32(left, right, "%"+result) + return true, false, nil + } + + right, err := c.eval64(ins.Args[0], false) + if err != nil { + return true, false, err + } + left, err := c.eval64(leftOperand, false) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", result, left, right) + if err := c.storeReg(destination.Reg, "%"+result); err != nil { + return true, false, err + } + c.setFlagsAdd(left, right, "%"+result) + return true, false, nil +} + +func arm64AddFlagsSourceValid(operand Operand, word bool) bool { + switch operand.Kind { + case OpImm: + return operand.ImmRaw == "" + case OpReg: + return isARM64GeneralOrZeroReg(operand.Reg) + case OpRegShift: + if !isARM64GeneralOrZeroReg(operand.Reg) || operand.ShiftReg != "" { + return false + } + switch operand.ShiftOp { + case ShiftLeft, ShiftRight, ShiftArith: + default: + return false + } + limit := int64(63) + if word { + limit = 31 + } + return operand.ShiftAmount >= 0 && operand.ShiftAmount <= limit + case OpRegExtend: + if !isARM64GeneralOrZeroReg(operand.Reg) || operand.ShiftReg != "" { + return false + } + switch operand.Ext { + case ExtendUXTB, ExtendUXTH, ExtendUXTW, ExtendUXTX, + ExtendSXTB, ExtendSXTH, ExtendSXTW, ExtendSXTX: + default: + return false + } + return (operand.ShiftOp == "" || operand.ShiftOp == ShiftLeft) && operand.ShiftAmount >= 0 && operand.ShiftAmount <= 4 + default: + return false + } +} diff --git a/arm64_lower_add_flags_test.go b/arm64_lower_add_flags_test.go new file mode 100644 index 00000000..a4395d05 --- /dev/null +++ b/arm64_lower_add_flags_test.go @@ -0,0 +1,176 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64AddFlagsCompleteGo127Forms(t *testing.T) { + const source = `TEXT addFlagsForms(SB), $0-0 + ADDS R0, R1 + ADDS R2, R3, R4 + ADDS $4095, R5, R6 + ADDS R7>>8, R8, R9 + ADDS R10.UXTX<<4, R11, R12 + ADDS $1, RSP, R13 + ADDS R1<<1, RSP, R4 + ADDS R2<<4, RSP, R5 + ADDSW R14, R15 + ADDSW R16, R17, R19 + ADDSW $(3525<<12), R20, R21 + ADDSW R22->7, R23, R24 + ADDSW R25.SXTX<<1, R29, R26 + ADDSW $1, RSP, R27 + ADDSW R3<<4, RSP, R6 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "addFlagsForms": {Name: "addFlagsForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"add i64", "add i32", "icmp ult i64", "icmp ult i32", "icmp slt i64", "icmp slt i32"} { + if !strings.Contains(ir, want) { + t.Fatalf("add-with-flags lowering omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-add-flags.ll", "arm64-add-flags.o", ir) + }) + } +} + +func TestTranslateARM64AddFlagsRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, instruction := range []string{ + "ADDS R0", + "ADDS R0, R1, R2, R3", + "ADDS (R0), R1", + "ADDS R0, R1, RSP", + "ADDS R0>>64, R1, R2", + "ADDS R0>>1, RSP, R2", + "ADDS R0->1, RSP, R2", + "ADDS R0<<5, RSP, R2", + "ADDSW R0<<32, R1, R2", + "ADDSW R0>>1, RSP, R2", + "ADDSW R0.UXTB<<5, R1, R2", + "ADDSW.P R0, R1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badAddFlags(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badAddFlags": {Name: "badAddFlags", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ADDS optab", instruction) + } + }) + } +} + +func TestARM64AddFlagsRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT addFlagsRuntime(SB), $0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD out+16(FP), R2 + ADDS R0, R1, R3 + MOVD R3, 0(R2) + CSET MI, R4 + MOVD R4, 8(R2) + CSET EQ, R4 + MOVD R4, 16(R2) + CSET CS, R4 + MOVD R4, 24(R2) + CSET VS, R4 + MOVD R4, 32(R2) + ADDSW R0, R1, R3 + MOVD R3, 40(R2) + CSET MI, R4 + MOVD R4, 48(R2) + CSET EQ, R4 + MOVD R4, 56(R2) + CSET CS, R4 + MOVD R4, 64(R2) + CSET VS, R4 + MOVD R4, 72(R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "addFlagsRuntime": { + Name: "addFlagsRuntime", Args: []LLVMType{I64, I64, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void addFlagsRuntime(uint64_t, uint64_t, uint64_t *); +int main(void) { + const uint64_t a = UINT64_C(0x8000000000000001); + const uint64_t b = UINT64_C(0x8000000000000002); + uint64_t got[10] = {0}; + addFlagsRuntime(a, b, got); + const uint64_t r = a + b; + const uint32_t aw = (uint32_t)a, bw = (uint32_t)b, rw = aw + bw; + const uint64_t want[10] = { + r, r >> 63, r == 0, r < a, ((~(a ^ b) & (a ^ r)) >> 63), + rw, rw >> 31, rw == 0, rw < aw, ((~(aw ^ bw) & (aw ^ rw)) >> 31), + }; + for (int i = 0; i < 10; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_add_flags", triple, ir, mainC, nil) +} diff --git a/arm64_lower_addsub_carry.go b/arm64_lower_addsub_carry.go new file mode 100644 index 00000000..0fda9b9c --- /dev/null +++ b/arm64_lower_addsub_carry.go @@ -0,0 +1,163 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64AddSubCarry(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "ADC", "ADCW", "ADCS", "ADCSW", "SBC", "SBCW", "SBCS", "SBCSW": + default: + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects 2 or 3 operands: %q", op, ins.Raw) + } + if !arm64AddSubCarryRegisterOrZero(ins.Args[0], true) { + return true, false, fmt.Errorf("arm64 %s first operand must be a general register or zero: %q", op, ins.Raw) + } + destination := ins.Args[len(ins.Args)-1] + if !arm64AddSubCarryRegisterOrZero(destination, false) { + return true, false, fmt.Errorf("arm64 %s destination must be a general register: %q", op, ins.Raw) + } + leftOperand := destination + if len(ins.Args) == 3 { + leftOperand = ins.Args[1] + if !arm64AddSubCarryRegisterOrZero(leftOperand, false) { + return true, false, fmt.Errorf("arm64 %s second operand must be a general register: %q", op, ins.Raw) + } + } + + word := strings.HasSuffix(string(op), "W") + subtract := strings.HasPrefix(string(op), "SBC") + setFlags := op == "ADCS" || op == "ADCSW" || op == "SBCS" || op == "SBCSW" + if word { + return c.lowerARM64AddSubCarry32(op, ins, leftOperand, destination, subtract, setFlags) + } + return c.lowerARM64AddSubCarry64(op, ins, leftOperand, destination, subtract, setFlags) +} + +func arm64AddSubCarryRegisterOrZero(operand Operand, allowImmediateZero bool) bool { + if operand.Kind == OpReg { + return isARM64GeneralOrZeroReg(operand.Reg) + } + return allowImmediateZero && operand.Kind == OpImm && operand.Imm == 0 && operand.ImmRaw == "" +} + +func (c *arm64Ctx) lowerARM64AddSubCarry32(op Op, ins Instr, leftOperand, destination Operand, subtract, setFlags bool) (bool, bool, error) { + right, err := c.eval32(ins.Args[0]) + if err != nil { + return true, false, err + } + left, err := c.eval32(leftOperand) + if err != nil { + return true, false, err + } + carryFlag := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i1, ptr %s\n", carryFlag, c.flagsCSlot) + carryOrBorrow := "%" + carryFlag + if subtract { + borrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", borrow, carryFlag) + carryOrBorrow = "%" + borrow + } + amount := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %s to i32\n", amount, carryOrBorrow) + intermediate := c.newTmp() + result := c.newTmp() + if subtract { + fmt.Fprintf(c.b, " %%%s = sub i32 %s, %s\n", intermediate, left, right) + fmt.Fprintf(c.b, " %%%s = sub i32 %%%s, %%%s\n", result, intermediate, amount) + } else { + fmt.Fprintf(c.b, " %%%s = add i32 %s, %s\n", intermediate, left, right) + fmt.Fprintf(c.b, " %%%s = add i32 %%%s, %%%s\n", result, intermediate, amount) + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, result) + if err := c.storeReg(destination.Reg, "%"+wide); err != nil { + return true, false, err + } + if !setFlags { + return true, false, nil + } + if subtract { + borrow0 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i32 %s, %s\n", borrow0, left, right) + borrow1 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i32 %%%s, %%%s\n", borrow1, intermediate, amount) + borrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", borrow, borrow0, borrow1) + noBorrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", noBorrow, borrow) + c.setFlagsSub32WithCarry(left, right, "%"+result, "%"+noBorrow) + } else { + carry0 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i32 %%%s, %s\n", carry0, intermediate, left) + carry1 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i32 %%%s, %%%s\n", carry1, result, intermediate) + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", carry, carry0, carry1) + c.setFlagsAdd32WithCarry(left, right, "%"+result, "%"+carry) + } + return true, false, nil +} + +func (c *arm64Ctx) lowerARM64AddSubCarry64(op Op, ins Instr, leftOperand, destination Operand, subtract, setFlags bool) (bool, bool, error) { + right, err := c.eval64(ins.Args[0], false) + if err != nil { + return true, false, err + } + left, err := c.eval64(leftOperand, false) + if err != nil { + return true, false, err + } + carryFlag := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i1, ptr %s\n", carryFlag, c.flagsCSlot) + carryOrBorrow := "%" + carryFlag + if subtract { + borrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", borrow, carryFlag) + carryOrBorrow = "%" + borrow + } + amount := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %s to i64\n", amount, carryOrBorrow) + intermediate := c.newTmp() + result := c.newTmp() + if subtract { + fmt.Fprintf(c.b, " %%%s = sub i64 %s, %s\n", intermediate, left, right) + fmt.Fprintf(c.b, " %%%s = sub i64 %%%s, %%%s\n", result, intermediate, amount) + } else { + fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", intermediate, left, right) + fmt.Fprintf(c.b, " %%%s = add i64 %%%s, %%%s\n", result, intermediate, amount) + } + if err := c.storeReg(destination.Reg, "%"+result); err != nil { + return true, false, err + } + if !setFlags { + return true, false, nil + } + if subtract { + borrow0 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i64 %s, %s\n", borrow0, left, right) + borrow1 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i64 %%%s, %%%s\n", borrow1, intermediate, amount) + borrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", borrow, borrow0, borrow1) + noBorrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", noBorrow, borrow) + c.setFlagsSubWithCarry(left, right, "%"+result, "%"+noBorrow) + } else { + carry0 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i64 %%%s, %s\n", carry0, intermediate, left) + carry1 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ult i64 %%%s, %%%s\n", carry1, result, intermediate) + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", carry, carry0, carry1) + c.setFlagsAddWithCarry(left, right, "%"+result, "%"+carry) + } + return true, false, nil +} diff --git a/arm64_lower_addsub_carry_test.go b/arm64_lower_addsub_carry_test.go new file mode 100644 index 00000000..a0001f55 --- /dev/null +++ b/arm64_lower_addsub_carry_test.go @@ -0,0 +1,183 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func arm64AddSubCarryCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT addSubCarryComplete(SB),$0-0\n") + for _, op := range []string{"ADC", "ADCW", "ADCS", "ADCSW", "SBC", "SBCW", "SBCS", "SBCSW"} { + source.WriteString("\t" + op + " R1, R2\n") + source.WriteString("\t" + op + " R3, R4, R5\n") + source.WriteString("\t" + op + " ZR, R6, R7\n") + source.WriteString("\t" + op + " $0, R8\n") + source.WriteString("\t" + op + " R9, ZR, ZR\n") + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64AddSubCarryCompleteFormats(t *testing.T) { + source := arm64AddSubCarryCompleteForms() + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "addSubCarryComplete": {Name: "addSubCarryComplete", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "add i64", "add i32", "sub i64", "sub i32", + "zext i32", "icmp ult i64", "icmp ult i32", + "icmp slt i64", "icmp slt i32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 add/sub-with-carry lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-addsub-carry.ll", "arm64-addsub-carry.o", ll) +} + +func TestTranslateARM64AddSubCarryRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "ADCW R0", + "ADCW R0, R1, R2, R3", + "ADCW (R0), R1", + "ADCW R0<<1, R1, R2", + "ADCW R0, RSP, R2", + "ADCW R0, R1, RSP", + "ADCW $1, R1", + "ADCSW.P R0, R1", + "SBCW R0, 8(R1), R2", + "SBCSW R0.UXTW, R1, R2", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 ADC/SBC optab", instruction) + } + } +} + +func TestARM64AddSubCarryRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT addSubCarryRuntime(SB),$0-8 + MOVD out+0(FP), R10 + MOVD $0xffffffff, R0 + MOVD $0, R1 + CMP R1, R1 + ADCSW R1, R0, R2 + MOVD R2, 0(R10) + CSET CS, R3 + MOVD R3, 8(R10) + CSET EQ, R3 + MOVD R3, 16(R10) + CSET MI, R3 + MOVD R3, 24(R10) + CSET VS, R3 + MOVD R3, 32(R10) + CMP $1, R1 + SBCSW R1, R1, R2 + MOVD R2, 40(R10) + CSET CS, R3 + MOVD R3, 48(R10) + CSET EQ, R3 + MOVD R3, 56(R10) + CSET MI, R3 + MOVD R3, 64(R10) + CSET VS, R3 + MOVD R3, 72(R10) + MOVD $0x7fffffff, R0 + CMP R1, R1 + ADCSW R1, R0, R2 + MOVD R2, 80(R10) + CSET CS, R3 + MOVD R3, 88(R10) + CSET EQ, R3 + MOVD R3, 96(R10) + CSET MI, R3 + MOVD R3, 104(R10) + CSET VS, R3 + MOVD R3, 112(R10) + MOVD $0x80000000, R0 + CMP $1, R1 + SBCSW R1, R0, R2 + MOVD R2, 120(R10) + CSET CS, R3 + MOVD R3, 128(R10) + CSET EQ, R3 + MOVD R3, 136(R10) + CSET MI, R3 + MOVD R3, 144(R10) + CSET VS, R3 + MOVD R3, 152(R10) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "addSubCarryRuntime": { + Name: "addSubCarryRuntime", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void addSubCarryRuntime(uint64_t *); +int main(void) { + uint64_t got[20] = {0}; + addSubCarryRuntime(got); + const uint64_t want[20] = { + 0, 1, 1, 0, 0, + UINT64_C(0xffffffff), 0, 0, 1, 0, + UINT64_C(0x80000000), 0, 0, 1, 1, + UINT64_C(0x7fffffff), 1, 0, 0, 1, + }; + for (int i = 0; i < 20; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_addsub_carry", triple, ir, mainC, nil) +} diff --git a/arm64_lower_aes.go b/arm64_lower_aes.go new file mode 100644 index 00000000..cd62a887 --- /dev/null +++ b/arm64_lower_aes.go @@ -0,0 +1,103 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64RawAES struct { + op Op + source int + destination int +} + +func decodeARM64RawAES(word uint32) (arm64RawAES, bool) { + var op Op + switch word & 0xfffffc00 { + case 0x4e284800: + op = "AESE" + case 0x4e285800: + op = "AESD" + case 0x4e286800: + op = "AESMC" + case 0x4e287800: + op = "AESIMC" + default: + return arm64RawAES{}, false + } + return arm64RawAES{ + op: op, + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawAES(form arm64RawAES) error { + reg := func(index int) Operand { + return Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.B16", index))} + } + ins := Instr{ + Op: form.op, + Raw: "decoded ARM64 WORD as " + string(form.op), + Args: []Operand{reg(form.source), reg(form.destination)}, + } + ok, _, err := c.lowerARM64AES(form.op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", form.op) + } + return err +} + +func (c *arm64Ctx) lowerARM64AES(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "AESE", "AESD", "AESMC", "AESIMC": + default: + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects two bare V registers or two V.B16 registers with no suffix: %q", op, ins.Raw) + } + + bare := false + arranged := false + for _, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects two vector registers: %q", op, ins.Raw) + } + if _, valid := arm64ParseVReg(arg.Reg); !valid { + return true, false, fmt.Errorf("arm64 %s expects two vector registers: %q", op, ins.Raw) + } + if strings.Contains(string(arg.Reg), ".") { + arrangement, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || arrangement != (arm64VectorArrangement{elementBits: 8, lanes: 16}) { + return true, false, fmt.Errorf("arm64 %s expects V.B16 operands: %q", op, ins.Raw) + } + arranged = true + } else { + bare = true + } + } + if bare && arranged { + return true, false, fmt.Errorf("arm64 %s cannot mix bare and arranged vector registers: %q", op, ins.Raw) + } + + source, err := c.loadVReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + var result string + if op == "AESE" || op == "AESD" { + destination, err := c.loadVReg(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <16 x i8> @llvm.aarch64.crypto.%s(<16 x i8> %s, <16 x i8> %s)\n", value, strings.ToLower(string(op)), destination, source) + result = "%" + value + } else { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <16 x i8> @llvm.aarch64.crypto.%s(<16 x i8> %s)\n", value, strings.ToLower(string(op)), source) + result = "%" + value + } + return true, false, c.storeVReg(ins.Args[1].Reg, result) +} diff --git a/arm64_lower_aes_test.go b/arm64_lower_aes_test.go new file mode 100644 index 00000000..de53d22a --- /dev/null +++ b/arm64_lower_aes_test.go @@ -0,0 +1,278 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64AESNamedForms = ` +TEXT aesnamedforms(SB),$0-0 + AESE V0, V1 + AESD V2, V3 + AESMC V4, V5 + AESIMC V6, V7 + AESE V8.B16, V9.B16 + AESD V10.B16, V11.B16 + AESMC V12.B16, V13.B16 + AESIMC V14.B16, V15.B16 + RET +` + +const arm64AESRawForms = ` +TEXT aesrawforms(SB),$0-0 + WORD $0x4e284bfd // AESE V31.B16, V29.B16 + WORD $0x4e285ad3 // AESD V22.B16, V19.B16 + WORD $0x4e2869dc // AESMC V14.B16, V28.B16 + WORD $0x4e28799b // AESIMC V12.B16, V27.B16 + RET +` + +func TestTranslateARM64AESCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64AESNamedForms, true) + requireARM64GoAssemblerResult(t, arm64AESRawForms, true) + for name, source := range map[string]string{ + "named": arm64AESNamedForms, + "raw": arm64AESRawForms, + } { + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + function := "aesnamedforms" + if name == "raw" { + function = "aesrawforms" + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + function: {Name: function, Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "@llvm.aarch64.crypto.aese", + "@llvm.aarch64.crypto.aesd", + "@llvm.aarch64.crypto.aesmc", + "@llvm.aarch64.crypto.aesimc", + `"target-features"="+aes"`, + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 AES lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-aes.ll", "arm64-aes.o", ll) + }) + } + }) + } +} + +func TestTranslateARM64AESRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "AESD V1.B8, V2.B8", + "AESE V1.D2, V2.D2", + "AESIMC V1.S4, V2.S4", + "AESE V1.B16, V2.B8", + "AESMC V1.B16, V2", + "AESE V1.B16, V2.B16, V3.B16", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badaes(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badaes": {Name: "badaes", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's AES optab", instruction) + } + }) + } +} + +func TestARM64RawAESDecoderCoversRegistersAndRejectsAdjacentEncodings(t *testing.T) { + bases := map[string]uint32{ + "AESE": 0x4e284800, + "AESD": 0x4e285800, + "AESMC": 0x4e286800, + "AESIMC": 0x4e287800, + } + for op, base := range bases { + for source := 0; source < 32; source++ { + for destination := 0; destination < 32; destination++ { + word := base | uint32(source<<5) | uint32(destination) + form, ok := decodeARM64RawAES(word) + if !ok || form.op != Op(op) || form.source != source || form.destination != destination { + t.Fatalf("decode %#08x = %#v, %v; want %s V%d, V%d", word, form, ok, op, source, destination) + } + } + } + } + for _, word := range []uint32{ + 0x0e284800, // invalid Q/opcode prefix + 0x4e284c00, // adjacent opcode field + 0x4e285400, // adjacent opcode field + 0x4e287c00, // adjacent opcode field + } { + if form, ok := decodeARM64RawAES(word); ok { + t.Fatalf("AES decoder accepted adjacent encoding %#08x as %#v", word, form) + } + } +} + +func TestARM64AESRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host; the complete-form test independently compiles every target") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT aessemantics(SB),$0-24 + MOVD state+0(FP), R0 + MOVD key+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V2.B16] + VLD1 (R0), [V3.B16] + VLD1 (R0), [V4.B16] + VLD1 (R0), [V5.B16] + VLD1 (R1), [V1.B16] + AESE V1.B16, V2.B16 + AESD V1.B16, V3.B16 + AESMC V4.B16, V4.B16 + AESIMC V5.B16, V5.B16 + VST1.P [V2.B16], 16(R2) + VST1.P [V3.B16], 16(R2) + VST1.P [V4.B16], 16(R2) + VST1.P [V5.B16], 16(R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "aessemantics": { + Name: "aessemantics", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void aessemantics(const uint8_t *, const uint8_t *, uint8_t *); + +static const uint8_t sbox[256] = { +0x63,0x7c,0x77,0x7b,0xf2,0x6b,0x6f,0xc5,0x30,0x01,0x67,0x2b,0xfe,0xd7,0xab,0x76, +0xca,0x82,0xc9,0x7d,0xfa,0x59,0x47,0xf0,0xad,0xd4,0xa2,0xaf,0x9c,0xa4,0x72,0xc0, +0xb7,0xfd,0x93,0x26,0x36,0x3f,0xf7,0xcc,0x34,0xa5,0xe5,0xf1,0x71,0xd8,0x31,0x15, +0x04,0xc7,0x23,0xc3,0x18,0x96,0x05,0x9a,0x07,0x12,0x80,0xe2,0xeb,0x27,0xb2,0x75, +0x09,0x83,0x2c,0x1a,0x1b,0x6e,0x5a,0xa0,0x52,0x3b,0xd6,0xb3,0x29,0xe3,0x2f,0x84, +0x53,0xd1,0x00,0xed,0x20,0xfc,0xb1,0x5b,0x6a,0xcb,0xbe,0x39,0x4a,0x4c,0x58,0xcf, +0xd0,0xef,0xaa,0xfb,0x43,0x4d,0x33,0x85,0x45,0xf9,0x02,0x7f,0x50,0x3c,0x9f,0xa8, +0x51,0xa3,0x40,0x8f,0x92,0x9d,0x38,0xf5,0xbc,0xb6,0xda,0x21,0x10,0xff,0xf3,0xd2, +0xcd,0x0c,0x13,0xec,0x5f,0x97,0x44,0x17,0xc4,0xa7,0x7e,0x3d,0x64,0x5d,0x19,0x73, +0x60,0x81,0x4f,0xdc,0x22,0x2a,0x90,0x88,0x46,0xee,0xb8,0x14,0xde,0x5e,0x0b,0xdb, +0xe0,0x32,0x3a,0x0a,0x49,0x06,0x24,0x5c,0xc2,0xd3,0xac,0x62,0x91,0x95,0xe4,0x79, +0xe7,0xc8,0x37,0x6d,0x8d,0xd5,0x4e,0xa9,0x6c,0x56,0xf4,0xea,0x65,0x7a,0xae,0x08, +0xba,0x78,0x25,0x2e,0x1c,0xa6,0xb4,0xc6,0xe8,0xdd,0x74,0x1f,0x4b,0xbd,0x8b,0x8a, +0x70,0x3e,0xb5,0x66,0x48,0x03,0xf6,0x0e,0x61,0x35,0x57,0xb9,0x86,0xc1,0x1d,0x9e, +0xe1,0xf8,0x98,0x11,0x69,0xd9,0x8e,0x94,0x9b,0x1e,0x87,0xe9,0xce,0x55,0x28,0xdf, +0x8c,0xa1,0x89,0x0d,0xbf,0xe6,0x42,0x68,0x41,0x99,0x2d,0x0f,0xb0,0x54,0xbb,0x16}; +static const uint8_t invsbox[256] = { +0x52,0x09,0x6a,0xd5,0x30,0x36,0xa5,0x38,0xbf,0x40,0xa3,0x9e,0x81,0xf3,0xd7,0xfb, +0x7c,0xe3,0x39,0x82,0x9b,0x2f,0xff,0x87,0x34,0x8e,0x43,0x44,0xc4,0xde,0xe9,0xcb, +0x54,0x7b,0x94,0x32,0xa6,0xc2,0x23,0x3d,0xee,0x4c,0x95,0x0b,0x42,0xfa,0xc3,0x4e, +0x08,0x2e,0xa1,0x66,0x28,0xd9,0x24,0xb2,0x76,0x5b,0xa2,0x49,0x6d,0x8b,0xd1,0x25, +0x72,0xf8,0xf6,0x64,0x86,0x68,0x98,0x16,0xd4,0xa4,0x5c,0xcc,0x5d,0x65,0xb6,0x92, +0x6c,0x70,0x48,0x50,0xfd,0xed,0xb9,0xda,0x5e,0x15,0x46,0x57,0xa7,0x8d,0x9d,0x84, +0x90,0xd8,0xab,0x00,0x8c,0xbc,0xd3,0x0a,0xf7,0xe4,0x58,0x05,0xb8,0xb3,0x45,0x06, +0xd0,0x2c,0x1e,0x8f,0xca,0x3f,0x0f,0x02,0xc1,0xaf,0xbd,0x03,0x01,0x13,0x8a,0x6b, +0x3a,0x91,0x11,0x41,0x4f,0x67,0xdc,0xea,0x97,0xf2,0xcf,0xce,0xf0,0xb4,0xe6,0x73, +0x96,0xac,0x74,0x22,0xe7,0xad,0x35,0x85,0xe2,0xf9,0x37,0xe8,0x1c,0x75,0xdf,0x6e, +0x47,0xf1,0x1a,0x71,0x1d,0x29,0xc5,0x89,0x6f,0xb7,0x62,0x0e,0xaa,0x18,0xbe,0x1b, +0xfc,0x56,0x3e,0x4b,0xc6,0xd2,0x79,0x20,0x9a,0xdb,0xc0,0xfe,0x78,0xcd,0x5a,0xf4, +0x1f,0xdd,0xa8,0x33,0x88,0x07,0xc7,0x31,0xb1,0x12,0x10,0x59,0x27,0x80,0xec,0x5f, +0x60,0x51,0x7f,0xa9,0x19,0xb5,0x4a,0x0d,0x2d,0xe5,0x7a,0x9f,0x93,0xc9,0x9c,0xef, +0xa0,0xe0,0x3b,0x4d,0xae,0x2a,0xf5,0xb0,0xc8,0xeb,0xbb,0x3c,0x83,0x53,0x99,0x61, +0x17,0x2b,0x04,0x7e,0xba,0x77,0xd6,0x26,0xe1,0x69,0x14,0x63,0x55,0x21,0x0c,0x7d}; +static uint8_t xtime(uint8_t x) { return (uint8_t)((x << 1) ^ ((x >> 7) * 0x1b)); } +static uint8_t mul(uint8_t a, uint8_t b) { + uint8_t r = 0; + while (b) { if (b & 1) r ^= a; a = xtime(a); b >>= 1; } + return r; +} +static void shift_sub(uint8_t out[16], const uint8_t in[16], const uint8_t box[256], int inverse) { + for (int c = 0; c < 4; c++) for (int r = 0; r < 4; r++) { + int source_column = inverse ? (c - r + 4) & 3 : (c + r) & 3; + out[4*c+r] = box[in[4*source_column+r]]; + } +} +static void mix(uint8_t out[16], const uint8_t in[16], int inverse) { + for (int c = 0; c < 4; c++) { + const uint8_t *x = in + 4*c; uint8_t *y = out + 4*c; + if (!inverse) { + y[0]=mul(x[0],2)^mul(x[1],3)^x[2]^x[3]; + y[1]=x[0]^mul(x[1],2)^mul(x[2],3)^x[3]; + y[2]=x[0]^x[1]^mul(x[2],2)^mul(x[3],3); + y[3]=mul(x[0],3)^x[1]^x[2]^mul(x[3],2); + } else { + y[0]=mul(x[0],14)^mul(x[1],11)^mul(x[2],13)^mul(x[3],9); + y[1]=mul(x[0],9)^mul(x[1],14)^mul(x[2],11)^mul(x[3],13); + y[2]=mul(x[0],13)^mul(x[1],9)^mul(x[2],14)^mul(x[3],11); + y[3]=mul(x[0],11)^mul(x[1],13)^mul(x[2],9)^mul(x[3],14); + } + } +} +int main(void) { + const uint8_t state[16] = {0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0xaa,0xbb,0xcc,0xdd,0xee,0xff}; + const uint8_t key[16] = {0x0f,0x0e,0x0d,0x0c,0x0b,0x0a,0x09,0x08,0x07,0x06,0x05,0x04,0x03,0x02,0x01,0x00}; + uint8_t got[64], xored[16], want[64]; + for (int i = 0; i < 16; i++) xored[i] = state[i] ^ key[i]; + shift_sub(want, xored, sbox, 0); + shift_sub(want+16, xored, invsbox, 1); + mix(want+32, state, 0); + mix(want+48, state, 1); + aessemantics(state, key, got); + for (int i = 0; i < 64; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_aes", triple, ll, mainC, nil) +} diff --git a/arm64_lower_arith.go b/arm64_lower_arith.go index 6a49bc9c..19e8e401 100644 --- a/arm64_lower_arith.go +++ b/arm64_lower_arith.go @@ -6,6 +6,33 @@ import ( ) func (c *arm64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err error) { + if ok, terminated, err := c.lowerARM64DivideRemainder(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerNegate(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64ScalarMultiply(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64BitReverse(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64CountLeading(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64InvertedLogical(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64BitClear(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64AddFlags(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64AddSubCarry(op, ins); ok { + return ok, terminated, err + } switch op { case "MRS_TPIDR_R0": // Pseudo-op used in runtime tls stubs. @@ -103,72 +130,6 @@ func (c *arm64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e } return true, false, nil - case "ADC", "ADCS", "SBC", "SBCS": - if len(ins.Args) != 2 && len(ins.Args) != 3 { - return true, false, fmt.Errorf("arm64 %s expects 2 or 3 operands: %q", op, ins.Raw) - } - var a, bval string - var dst Reg - if len(ins.Args) == 2 { - a, err = c.eval64(ins.Args[0], false) - if err != nil { - return true, false, err - } - if ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("arm64 %s dst must be reg: %q", op, ins.Raw) - } - dst = ins.Args[1].Reg - bval, err = c.loadReg(dst) - if err != nil { - return true, false, err - } - } else { - a, err = c.eval64(ins.Args[0], false) - if err != nil { - return true, false, err - } - bval, err = c.eval64(ins.Args[1], false) - if err != nil { - return true, false, err - } - if ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("arm64 %s dst must be reg: %q", op, ins.Raw) - } - dst = ins.Args[2].Reg - } - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i1, ptr %s\n", cf, c.flagsCSlot) - cin := c.newTmp() - if op == "SBC" || op == "SBCS" { - ncf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", ncf, cf) - fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to i64\n", cin, ncf) - } else { - fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to i64\n", cin, cf) - } - t0 := c.newTmp() - if op == "SBC" || op == "SBCS" { - fmt.Fprintf(c.b, " %%%s = sub i64 %s, %s\n", t0, bval, a) - } else { - fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", t0, bval, a) - } - t := c.newTmp() - if op == "SBC" || op == "SBCS" { - fmt.Fprintf(c.b, " %%%s = sub i64 %%%s, %%%s\n", t, t0, cin) - } else { - fmt.Fprintf(c.b, " %%%s = add i64 %%%s, %%%s\n", t, t0, cin) - } - if err := c.storeReg(dst, "%"+t); err != nil { - return true, false, err - } - if op == "ADCS" { - c.setFlagsAdd(bval, a, "%"+t) - } - if op == "SBCS" { - c.setFlagsSub(bval, a, "%"+t) - } - return true, false, nil - case "ADDW": if len(ins.Args) != 2 && len(ins.Args) != 3 { return true, false, fmt.Errorf("arm64 ADDW expects 2 or 3 operands: %q", ins.Raw) @@ -484,78 +445,6 @@ func (c *arm64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, res) return true, false, c.storeReg(dst, "%"+z) - case "BIC": - // BIC src, src2, dst => dst = src2 & ~src - if len(ins.Args) != 2 && len(ins.Args) != 3 { - return true, false, fmt.Errorf("arm64 BIC expects 2 or 3 operands: %q", ins.Raw) - } - src, err := c.eval64(ins.Args[0], false) - if err != nil { - return true, false, err - } - var src2 string - var dst Reg - if len(ins.Args) == 2 { - if ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("arm64 BIC 2-operand form expects reg dst: %q", ins.Raw) - } - dst = ins.Args[1].Reg - src2, err = c.loadReg(dst) - } else { - if ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("arm64 BIC 3-operand form expects reg dst: %q", ins.Raw) - } - dst = ins.Args[2].Reg - src2, err = c.eval64(ins.Args[1], false) - } - if err != nil { - return true, false, err - } - nt := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i64 %s, -1\n", nt, src) - at := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i64 %s, %%%s\n", at, src2, nt) - return true, false, c.storeReg(dst, "%"+at) - - case "BICW": - // BICW src, src2, dst => dst = src2 & ~src (32-bit, zero-extended) - if len(ins.Args) != 2 && len(ins.Args) != 3 { - return true, false, fmt.Errorf("arm64 BICW expects 2 or 3 operands: %q", ins.Raw) - } - src, err := c.eval64(ins.Args[0], false) - if err != nil { - return true, false, err - } - var src2 string - var dst Reg - if len(ins.Args) == 2 { - if ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("arm64 BICW 2-operand form expects reg dst: %q", ins.Raw) - } - dst = ins.Args[1].Reg - src2, err = c.loadReg(dst) - } else { - if ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("arm64 BICW 3-operand form expects reg dst: %q", ins.Raw) - } - dst = ins.Args[2].Reg - src2, err = c.eval64(ins.Args[1], false) - } - if err != nil { - return true, false, err - } - sw := c.newTmp() - s2w := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", sw, src) - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", s2w, src2) - nt := c.newTmp() - fmt.Fprintf(c.b, " %%%s = xor i32 %%%s, -1\n", nt, sw) - at := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i32 %%%s, %%%s\n", at, s2w, nt) - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", z, at) - return true, false, c.storeReg(dst, "%"+z) - case "MVN": // MVN src, dst => dst = ~src if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { @@ -587,18 +476,29 @@ func (c *arm64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e return true, false, c.storeReg(ins.Args[1].Reg, "%"+z) case "CRC32B", "CRC32H", "CRC32W", "CRC32X", "CRC32CB", "CRC32CH", "CRC32CW", "CRC32CX": - // CRC32{B,H,W,X} srcReg, dstReg - // CRC32C{B,H,W,X} srcReg, dstReg - // Semantics: dst = crc32(dst, src) - if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("arm64 %s expects reg, reg: %q", op, ins.Raw) + // CRC32{C}{B,H,W,X} src, crc, dst, with the two-operand form + // taking the incoming CRC from dst. + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects 2 or 3 registers: %q", op, ins.Raw) + } + for _, operand := range ins.Args { + if operand.Kind != OpReg || !isARM64GeneralOrZeroReg(operand.Reg) { + return true, false, fmt.Errorf("arm64 %s operands must be general registers: %q", op, ins.Raw) + } } src64, err := c.loadReg(ins.Args[0].Reg) if err != nil { return true, false, err } - dstReg := ins.Args[1].Reg - crc64, err := c.loadReg(dstReg) + dstReg := ins.Args[len(ins.Args)-1].Reg + crcReg := dstReg + if len(ins.Args) == 3 { + crcReg = ins.Args[1].Reg + } + crc64, err := c.loadReg(crcReg) if err != nil { return true, false, err } @@ -695,12 +595,39 @@ func (c *arm64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e return true, false, nil case "CCMP", "CCMPW", "CCMN", "CCMNW": - if len(ins.Args) != 4 || ins.Args[0].Kind != OpIdent || ins.Args[3].Kind != OpImm { + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 || + ins.Args[3].Kind != OpImm || ins.Args[3].ImmRaw != "" { return true, false, fmt.Errorf("arm64 %s expects condition, lhs, rhs, $nzcv: %q", op, ins.Raw) } + condition := "" + switch ins.Args[0].Kind { + case OpIdent: + condition = ins.Args[0].Ident + case OpReg: + // AL is also a register spelling in the Plan 9 parser, but in + // this operand position Go's optab classifies it as C_COND. + condition = string(ins.Args[0].Reg) + default: + return true, false, fmt.Errorf("arm64 %s first operand must be a condition: %q", op, ins.Raw) + } if ins.Args[3].Imm < 0 || ins.Args[3].Imm > 15 { return true, false, fmt.Errorf("arm64 %s NZCV immediate is outside 0..15: %q", op, ins.Raw) } + if ins.Args[1].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm64 %s lhs must be a general register: %q", op, ins.Raw) + } + switch ins.Args[2].Kind { + case OpReg: + if !isARM64GeneralOrZeroReg(ins.Args[2].Reg) { + return true, false, fmt.Errorf("arm64 %s rhs must be a general register: %q", op, ins.Raw) + } + case OpImm: + if ins.Args[2].ImmRaw != "" || ins.Args[2].Imm < 0 || ins.Args[2].Imm > 31 { + return true, false, fmt.Errorf("arm64 %s rhs immediate is outside 0..31: %q", op, ins.Raw) + } + default: + return true, false, fmt.Errorf("arm64 %s rhs must be a register or immediate: %q", op, ins.Raw) + } word := op == "CCMPW" || op == "CCMNW" add := op == "CCMN" || op == "CCMNW" var lhs, rhs string @@ -719,11 +646,32 @@ func (c *arm64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e if err != nil { return true, false, err } - return true, false, c.setConditionalCompareFlags(ins.Args[0].Ident, lhs, rhs, ins.Args[3].Imm, word, add) + return true, false, c.setConditionalCompareFlags(condition, lhs, rhs, ins.Args[3].Imm, word, add) - case "CMN": + case "CMN", "CMNW": + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept instruction suffixes: %q", op, ins.Raw) + } if len(ins.Args) != 2 { - return true, false, fmt.Errorf("arm64 CMN expects 2 operands: %q", ins.Raw) + return true, false, fmt.Errorf("arm64 %s expects 2 operands: %q", op, ins.Raw) + } + word := op == "CMNW" + if err := validateARM64CompareNegativeOperands(ins.Args[0], ins.Args[1], word); err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + if word { + src, err := c.eval32(ins.Args[0]) + if err != nil { + return true, false, err + } + dst, err := c.eval32(ins.Args[1]) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %s\n", result, dst, src) + c.setFlagsAdd32(dst, src, "%"+result) + return true, false, nil } src, err := c.eval64(ins.Args[0], false) if err != nil { @@ -1079,57 +1027,47 @@ func (c *arm64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e fmt.Fprintf(c.b, " %%%s = ashr i64 %s, %s\n", t, src, shv) return true, false, c.storeReg(dstReg, "%"+t) - case "UDIV": - if len(ins.Args) != 2 && len(ins.Args) != 3 { - return true, false, fmt.Errorf("arm64 UDIV expects 2 or 3 operands: %q", ins.Raw) + case "EXTR", "EXTRW": + // EXTR shift, hi, lo, dst + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 || + ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 %s expects $shift, hi, lo, dstReg: %q", op, ins.Raw) } - var a, bval string - var dst Reg - if len(ins.Args) == 2 { - a, err = c.eval64(ins.Args[0], false) - if err != nil { - return true, false, err - } - if ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("arm64 UDIV expects src, dstReg: %q", ins.Raw) - } - dst = ins.Args[1].Reg - bval, err = c.loadReg(dst) - if err != nil { - return true, false, err + for _, operand := range ins.Args[1:] { + if operand.Kind != OpReg || !isARM64GeneralOrZeroReg(operand.Reg) { + return true, false, fmt.Errorf("arm64 %s operands must be general registers: %q", op, ins.Raw) } - } else { - a, err = c.eval64(ins.Args[0], false) + } + width := int64(64) + if op == "EXTRW" { + width = 32 + } + shift := ins.Args[0].Imm + if shift < 0 || shift >= width { + return true, false, fmt.Errorf("arm64 %s shift must be in [0,%d): %q", op, width, ins.Raw) + } + if op == "EXTRW" { + hi, err := c.eval32(ins.Args[1]) if err != nil { return true, false, err } - bval, err = c.eval64(ins.Args[1], false) + lo, err := c.eval32(ins.Args[2]) if err != nil { return true, false, err } - if ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("arm64 UDIV expects src, src2, dstReg: %q", ins.Raw) + result := lo + if shift != 0 { + loPart := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i32 %s, %d\n", loPart, lo, shift) + hiPart := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i32 %s, %d\n", hiPart, hi, width-shift) + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i32 %%%s, %%%s\n", combined, loPart, hiPart) + result = "%" + combined } - dst = ins.Args[2].Reg - } - nonzero := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp ne i64 %s, 0\n", nonzero, a) - div := c.newTmp() - fmt.Fprintf(c.b, " %%%s = udiv i64 %s, %s\n", div, bval, a) - out := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i64 %%%s, i64 0\n", out, nonzero, div) - return true, false, c.storeReg(dst, "%"+out) - - case "EXTR": - // EXTR shift, hi, lo, dst - if len(ins.Args) != 4 || ins.Args[3].Kind != OpReg { - return true, false, fmt.Errorf("arm64 EXTR expects shift, hi, lo, dstReg: %q", ins.Raw) - } - var sh int64 - if ins.Args[0].Kind == OpImm { - sh = ins.Args[0].Imm & 63 - } else { - return true, false, fmt.Errorf("arm64 EXTR expects immediate shift: %q", ins.Raw) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, result) + return true, false, c.storeReg(ins.Args[3].Reg, "%"+wide) } hi, err := c.eval64(ins.Args[1], false) if err != nil { @@ -1139,13 +1077,17 @@ func (c *arm64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e if err != nil { return true, false, err } - loPart := c.newTmp() - fmt.Fprintf(c.b, " %%%s = lshr i64 %s, %d\n", loPart, lo, sh) - hiPart := c.newTmp() - fmt.Fprintf(c.b, " %%%s = shl i64 %s, %d\n", hiPart, hi, (64-sh)&63) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", t, loPart, hiPart) - return true, false, c.storeReg(ins.Args[3].Reg, "%"+t) + result := lo + if shift != 0 { + loPart := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i64 %s, %d\n", loPart, lo, shift) + hiPart := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i64 %s, %d\n", hiPart, hi, width-shift) + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", combined, loPart, hiPart) + result = "%" + combined + } + return true, false, c.storeReg(ins.Args[3].Reg, result) case "RORW": // RORW shift, dstReg or RORW shift, srcReg, dstReg @@ -1262,30 +1204,6 @@ func (c *arm64Ctx) lowerArith(op Op, ins Instr) (ok bool, terminated bool, err e fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", out, right, left) return true, false, c.storeReg(dstReg, "%"+out) - case "RBIT": - if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("arm64 RBIT expects reg, reg: %q", ins.Raw) - } - src, err := c.loadReg(ins.Args[0].Reg) - if err != nil { - return true, false, err - } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i64 @llvm.bitreverse.i64(i64 %s)\n", t, src) - return true, false, c.storeReg(ins.Args[1].Reg, "%"+t) - - case "CLZ": - if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("arm64 CLZ expects reg, reg: %q", ins.Raw) - } - src, err := c.loadReg(ins.Args[0].Reg) - if err != nil { - return true, false, err - } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call i64 @llvm.ctlz.i64(i64 %s, i1 false)\n", t, src) - return true, false, c.storeReg(ins.Args[1].Reg, "%"+t) - case "REV": // REV src, dst (bswap) if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { diff --git a/arm64_lower_atomic.go b/arm64_lower_atomic.go index a2992a1d..a16649f5 100644 --- a/arm64_lower_atomic.go +++ b/arm64_lower_atomic.go @@ -1,20 +1,200 @@ package plan9asm -import "fmt" +import ( + "fmt" + "strings" +) + +type arm64AtomicRMWForm struct { + typeName LLVMType + operation string + ordering string + invert bool +} + +type arm64AtomicCASForm struct { + typeName LLVMType + successOrder string + failureOrder string +} + +type arm64ExclusiveForm struct { + typeName LLVMType + isLoad bool + successOrder string + failureOrder string +} + +func parseARM64ExclusiveOpcode(op Op) (arm64ExclusiveForm, bool) { + name := strings.ToUpper(string(op)) + form := arm64ExclusiveForm{failureOrder: "monotonic"} + prefix := "" + switch { + case strings.HasPrefix(name, "LDAXR"): + prefix, form.isLoad, form.successOrder = "LDAXR", true, "acquire" + case strings.HasPrefix(name, "LDXR"): + prefix, form.isLoad, form.successOrder = "LDXR", true, "monotonic" + case strings.HasPrefix(name, "STLXR"): + prefix, form.successOrder = "STLXR", "release" + case strings.HasPrefix(name, "STXR"): + prefix, form.successOrder = "STXR", "monotonic" + default: + return arm64ExclusiveForm{}, false + } + switch strings.TrimPrefix(name, prefix) { + case "": + form.typeName = I64 + case "B": + form.typeName = I8 + case "H": + form.typeName = I16 + case "W": + form.typeName = I32 + default: + return arm64ExclusiveForm{}, false + } + return form, true +} + +func parseARM64AtomicCASOpcode(op Op) (arm64AtomicCASForm, bool) { + name := strings.ToUpper(string(op)) + if !strings.HasPrefix(name, "CAS") || strings.HasPrefix(name, "CASP") || len(name) < 4 { + return arm64AtomicCASForm{}, false + } + tail := strings.TrimPrefix(name, "CAS") + typeName := LLVMType("") + width := tail[len(tail)-1] + switch width { + case 'B': + typeName = I8 + case 'H': + typeName = I16 + case 'W': + typeName = I32 + case 'D': + typeName = I64 + default: + return arm64AtomicCASForm{}, false + } + order := tail[:len(tail)-1] + form := arm64AtomicCASForm{typeName: typeName} + switch order { + case "": + form.successOrder, form.failureOrder = "monotonic", "monotonic" + case "A": + if width == 'B' || width == 'H' { + return arm64AtomicCASForm{}, false + } + form.successOrder, form.failureOrder = "acquire", "acquire" + case "L": + if width == 'B' || width == 'H' { + return arm64AtomicCASForm{}, false + } + form.successOrder, form.failureOrder = "release", "monotonic" + case "AL": + form.successOrder, form.failureOrder = "acq_rel", "acquire" + default: + return arm64AtomicCASForm{}, false + } + return form, true +} + +func parseARM64AtomicRMWOpcode(op Op) (arm64AtomicRMWForm, bool) { + name := strings.ToUpper(string(op)) + operation := "" + invert := false + prefix := "" + for _, candidate := range []struct { + prefix string + operation string + invert bool + }{ + {"LDADD", "add", false}, + {"LDCLR", "and", true}, + {"LDEOR", "xor", false}, + {"LDOR", "or", false}, + {"SWP", "xchg", false}, + } { + if strings.HasPrefix(name, candidate.prefix) { + prefix, operation, invert = candidate.prefix, candidate.operation, candidate.invert + break + } + } + if prefix == "" { + return arm64AtomicRMWForm{}, false + } + tail := strings.TrimPrefix(name, prefix) + if len(tail) < 1 { + return arm64AtomicRMWForm{}, false + } + typeName := LLVMType("") + switch tail[len(tail)-1] { + case 'B': + typeName = I8 + case 'H': + typeName = I16 + case 'W': + typeName = I32 + case 'D': + typeName = I64 + default: + return arm64AtomicRMWForm{}, false + } + ordering := "" + switch tail[:len(tail)-1] { + case "": + ordering = "monotonic" + case "A": + ordering = "acquire" + case "L": + ordering = "release" + case "AL": + ordering = "acq_rel" + default: + return arm64AtomicRMWForm{}, false + } + return arm64AtomicRMWForm{typeName: typeName, operation: operation, ordering: ordering, invert: invert}, true +} func (c *arm64Ctx) lowerAtomic(op Op, ins Instr) (ok bool, terminated bool, err error) { + if ok, terminated, err := c.lowerAtomicPair(op, ins); ok { + return ok, terminated, err + } + if form, matched := parseARM64AtomicRMWOpcode(op); matched { + return true, false, c.lowerAtomicRMWFamily(form, ins) + } + if form, matched := parseARM64AtomicCASOpcode(op); matched { + return true, false, c.lowerAtomicCASFamily(form, ins) + } + if form, matched := parseARM64ExclusiveOpcode(op); matched { + return true, false, c.lowerExclusiveFamily(form, ins) + } switch op { - case "LDARW", "LDARB", "LDAR", "LDAXRW", "LDAXRB", "LDAXR": + case "CLREX": + if arm64AtomicOpcodeHasSuffix(ins.Op) || len(ins.Args) > 1 || len(ins.Args) == 1 && ins.Args[0].Kind != OpImm { + return true, false, fmt.Errorf("arm64 CLREX expects no operand or one immediate: %q", ins.Raw) + } + // LLVM IR has no exposed exclusive-monitor primitive. The ARM64 + // backend models LDXR/STXR reservations explicitly, so clearing the + // validity bit implements both Go assembler forms exactly. The + // optional architectural immediate is only an implementation hint. + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.exclusiveValidSlot) + return true, false, nil + + case "LDARW", "LDARH", "LDARB", "LDAR", "LDAXRW", "LDAXRB", "LDAXR": if len(ins.Args) != 2 || ins.Args[0].Kind != OpMem || ins.Args[1].Kind != OpReg { return true, false, fmt.Errorf("arm64 %s expects mem, reg: %q", op, ins.Raw) } + if !arm64AtomicZeroOffsetMemory(ins.Args[0].Mem) { + return true, false, fmt.Errorf("arm64 %s memory must be a zero-offset general-register, RSP, or ZR address: %q", op, ins.Raw) + } ty, align := arm64AtomicLoadStoreType(op) ptr, err := c.atomicMemPtr(ins.Args[0].Mem) if err != nil { return true, false, err } ld := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load atomic %s, ptr %s seq_cst, align %d\n", ld, ty, ptr, align) + fmt.Fprintf(c.b, " %%%s = load atomic %s, ptr %s acquire, align %d\n", ld, ty, ptr, align) v, err := c.atomicExtendToI64("%"+ld, ty) if err != nil { return true, false, err @@ -31,10 +211,13 @@ func (c *arm64Ctx) lowerAtomic(op Op, ins Instr) (ok bool, terminated bool, err } return true, false, c.storeReg(ins.Args[1].Reg, v) - case "STLRW", "STLRB", "STLR": + case "STLRW", "STLRH", "STLRB", "STLR": if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpMem { return true, false, fmt.Errorf("arm64 %s expects reg, mem: %q", op, ins.Raw) } + if !arm64AtomicZeroOffsetMemory(ins.Args[1].Mem) { + return true, false, fmt.Errorf("arm64 %s memory must be a zero-offset general-register, RSP, or ZR address: %q", op, ins.Raw) + } ty, align := arm64AtomicLoadStoreType(op) src, err := c.loadReg(ins.Args[0].Reg) if err != nil { @@ -48,7 +231,7 @@ func (c *arm64Ctx) lowerAtomic(op Op, ins Instr) (ok bool, terminated bool, err if err != nil { return true, false, err } - fmt.Fprintf(c.b, " store atomic %s %s, ptr %s seq_cst, align %d\n", ty, v, ptr, align) + fmt.Fprintf(c.b, " store atomic %s %s, ptr %s release, align %d\n", ty, v, ptr, align) return true, false, nil case "STLXRW", "STLXRB", "STLXR": @@ -149,7 +332,11 @@ func (c *arm64Ctx) lowerAtomic(op Op, ins Instr) (ok bool, terminated bool, err } return true, false, c.storeReg(ins.Args[2].Reg, old64) - case "LDADDALW", "LDADDALD", "LDORALB", "LDORALW", "LDORALD", "LDCLRALB", "LDCLRALW", "LDCLRALD": + case "LDADDALW", "LDADDALD", "LDORALB", "LDORALW", "LDORALD", "LDCLRALB", "LDCLRALW", "LDCLRALD", + "LDEORB", "LDEORH", "LDEORW", "LDEORD", + "LDEORAB", "LDEORAH", "LDEORAW", "LDEORAD", + "LDEORLB", "LDEORLH", "LDEORLW", "LDEORLD", + "LDEORALB", "LDEORALH", "LDEORALW", "LDEORALD": if len(ins.Args) != 3 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpMem || ins.Args[2].Kind != OpReg { return true, false, fmt.Errorf("arm64 %s expects srcReg, mem, dstReg: %q", op, ins.Raw) } @@ -177,6 +364,11 @@ func (c *arm64Ctx) lowerAtomic(op Op, ins Instr) (ok bool, terminated bool, err rmwo = "add" case "LDORALB", "LDORALW", "LDORALD": rmwo = "or" + case "LDEORB", "LDEORH", "LDEORW", "LDEORD", + "LDEORAB", "LDEORAH", "LDEORAW", "LDEORAD", + "LDEORLB", "LDEORLH", "LDEORLW", "LDEORLD", + "LDEORALB", "LDEORALH", "LDEORALW", "LDEORALD": + rmwo = "xor" case "LDCLRALB", "LDCLRALW", "LDCLRALD": rmwo = "and" // LDCLR updates memory as: mem = mem & ~src. @@ -238,6 +430,194 @@ func (c *arm64Ctx) lowerAtomic(op Op, ins Instr) (ok bool, terminated bool, err return false, false, nil } +func (c *arm64Ctx) lowerAtomicRMWFamily(form arm64AtomicRMWForm, ins Instr) error { + if arm64AtomicOpcodeHasSuffix(ins.Op) || len(ins.Args) != 3 || + ins.Args[0].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[0].Reg) || + ins.Args[1].Kind != OpMem || + ins.Args[2].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[2].Reg) { + return fmt.Errorf("arm64 %s expects source register, zero-offset register memory, destination register: %q", ins.Op, ins.Raw) + } + mem := ins.Args[1].Mem + if mem.Sym != "" || mem.Segment != "" || mem.Index != "" || mem.Off != 0 || mem.OffRaw != "" || + (mem.Base != Reg("RSP") && !isARM64GeneralOrZeroReg(mem.Base)) { + return fmt.Errorf("arm64 %s memory must be exactly (R0-R30), (RSP), or (ZR): %q", ins.Op, ins.Raw) + } + source64, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return err + } + source, err := c.atomicTruncFromI64(source64, form.typeName) + if err != nil { + return err + } + argument := source + if form.invert { + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, -1\n", inverted, form.typeName, source) + argument = "%" + inverted + } + pointer, err := c.atomicMemPtr(mem) + if err != nil { + return err + } + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = atomicrmw %s ptr %s, %s %s %s\n", old, form.operation, pointer, form.typeName, argument, form.ordering) + old64, err := c.atomicExtendToI64("%"+old, form.typeName) + if err != nil { + return err + } + return c.storeReg(ins.Args[2].Reg, old64) +} + +func (c *arm64Ctx) lowerAtomicCASFamily(form arm64AtomicCASForm, ins Instr) error { + if arm64AtomicOpcodeHasSuffix(ins.Op) || len(ins.Args) != 3 || + ins.Args[0].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[0].Reg) || + ins.Args[1].Kind != OpMem || + ins.Args[2].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[2].Reg) { + return fmt.Errorf("arm64 %s expects expected register, zero-offset register memory, new-value register: %q", ins.Op, ins.Raw) + } + mem := ins.Args[1].Mem + if mem.Sym != "" || mem.Segment != "" || mem.Index != "" || mem.Off != 0 || mem.OffRaw != "" || + (mem.Base != Reg("RSP") && !isARM64GeneralOrZeroReg(mem.Base)) { + return fmt.Errorf("arm64 %s memory must be exactly (R0-R30), (RSP), or (ZR): %q", ins.Op, ins.Raw) + } + expected64, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return err + } + expected, err := c.atomicTruncFromI64(expected64, form.typeName) + if err != nil { + return err + } + new64, err := c.loadReg(ins.Args[2].Reg) + if err != nil { + return err + } + newValue, err := c.atomicTruncFromI64(new64, form.typeName) + if err != nil { + return err + } + pointer, err := c.atomicMemPtr(mem) + if err != nil { + return err + } + align, err := arm64AtomicTypeSize(form.typeName) + if err != nil { + return err + } + changed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = cmpxchg ptr %s, %s %s, %s %s %s %s, align %d\n", + changed, pointer, form.typeName, expected, form.typeName, newValue, form.successOrder, form.failureOrder, align) + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue {%s, i1} %%%s, 0\n", old, form.typeName, changed) + old64, err := c.atomicExtendToI64("%"+old, form.typeName) + if err != nil { + return err + } + return c.storeReg(ins.Args[0].Reg, old64) +} + +func (c *arm64Ctx) lowerExclusiveFamily(form arm64ExclusiveForm, ins Instr) error { + wantArgs := 3 + if form.isLoad { + wantArgs = 2 + } + if arm64AtomicOpcodeHasSuffix(ins.Op) || len(ins.Args) != wantArgs { + return fmt.Errorf("arm64 %s has invalid exclusive load/store operands: %q", ins.Op, ins.Raw) + } + memoryIndex := 1 + if form.isLoad { + memoryIndex = 0 + } + if ins.Args[memoryIndex].Kind != OpMem { + return fmt.Errorf("arm64 %s requires a zero-offset register memory operand: %q", ins.Op, ins.Raw) + } + mem := ins.Args[memoryIndex].Mem + if mem.Sym != "" || mem.Segment != "" || mem.Index != "" || mem.Off != 0 || mem.OffRaw != "" || + (mem.Base != Reg("RSP") && !isARM64GeneralOrZeroReg(mem.Base)) { + return fmt.Errorf("arm64 %s memory must be exactly (R0-R30), (RSP), or (ZR): %q", ins.Op, ins.Raw) + } + pointer, err := c.atomicMemPtr(mem) + if err != nil { + return err + } + size, err := arm64AtomicTypeSize(form.typeName) + if err != nil { + return err + } + if form.isLoad { + if ins.Args[1].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[1].Reg) { + return fmt.Errorf("arm64 %s destination must be a general register or ZR: %q", ins.Op, ins.Raw) + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load atomic %s, ptr %s %s, align %d\n", loaded, form.typeName, pointer, form.successOrder, size) + value64, err := c.atomicExtendToI64("%"+loaded, form.typeName) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store i1 true, ptr %s\n", c.exclusiveValidSlot) + fmt.Fprintf(c.b, " store ptr %s, ptr %s\n", pointer, c.exclusivePtrSlot) + fmt.Fprintf(c.b, " store i8 %d, ptr %s\n", size, c.exclusiveSizeSlot) + fmt.Fprintf(c.b, " store i64 %s, ptr %s\n", value64, c.exclusiveValueSlot) + return c.storeReg(ins.Args[1].Reg, value64) + } + if ins.Args[0].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[0].Reg) || + ins.Args[2].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[2].Reg) { + return fmt.Errorf("arm64 %s source and status must be general registers or ZR: %q", ins.Op, ins.Raw) + } + source64, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return err + } + newValue, err := c.atomicTruncFromI64(source64, form.typeName) + if err != nil { + return err + } + loadedValid := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i1, ptr %s\n", loadedValid, c.exclusiveValidSlot) + loadedPointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load ptr, ptr %s\n", loadedPointer, c.exclusivePtrSlot) + pointerMatches := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq ptr %%%s, %s\n", pointerMatches, loadedPointer, pointer) + loadedSize := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i8, ptr %s\n", loadedSize, c.exclusiveSizeSlot) + sizeMatches := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i8 %%%s, %d\n", sizeMatches, loadedSize, size) + validPointer := c.newTmp() + canTry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", validPointer, loadedValid, pointerMatches) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", canTry, validPointer, sizeMatches) + id := c.newTmp() + tryLabel := arm64LLVMBlockName("stxr_try_" + id) + failLabel := arm64LLVMBlockName("stxr_fail_" + id) + mergeLabel := arm64LLVMBlockName("stxr_merge_" + id) + fmt.Fprintf(c.b, " br i1 %%%s, label %%%s, label %%%s\n", canTry, tryLabel, failLabel) + fmt.Fprintf(c.b, "\n%s:\n", tryLabel) + expected64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i64, ptr %s\n", expected64, c.exclusiveValueSlot) + expected, err := c.atomicTruncFromI64("%"+expected64, form.typeName) + if err != nil { + return err + } + changed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = cmpxchg ptr %s, %s %s, %s %s %s %s, align %d\n", + changed, pointer, form.typeName, expected, form.typeName, newValue, form.successOrder, form.failureOrder, size) + succeeded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue {%s, i1} %%%s, 1\n", succeeded, form.typeName, changed) + failed := c.newTmp() + tryStatus := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", failed, succeeded) + fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to i64\n", tryStatus, failed) + fmt.Fprintf(c.b, " br label %%%s\n", mergeLabel) + fmt.Fprintf(c.b, "\n%s:\n", failLabel) + fmt.Fprintf(c.b, " br label %%%s\n", mergeLabel) + fmt.Fprintf(c.b, "\n%s:\n", mergeLabel) + status := c.newTmp() + fmt.Fprintf(c.b, " %%%s = phi i64 [ %%%s, %%%s ], [ 1, %%%s ]\n", status, tryStatus, tryLabel, failLabel) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.exclusiveValidSlot) + return c.storeReg(ins.Args[2].Reg, "%"+status) +} + func (c *arm64Ctx) atomicMemPtr(mem MemRef) (string, error) { addr, _, _, err := c.addrI64(mem, false) if err != nil { @@ -248,10 +628,17 @@ func (c *arm64Ctx) atomicMemPtr(mem MemRef) (string, error) { return "%" + pt, nil } +func arm64AtomicZeroOffsetMemory(mem MemRef) bool { + return mem.Sym == "" && mem.Segment == "" && mem.Index == "" && mem.Off == 0 && mem.OffRaw == "" && + (mem.Base == Reg("RSP") || isARM64GeneralOrZeroReg(mem.Base)) +} + func arm64AtomicLoadStoreType(op Op) (LLVMType, int) { switch op { case "LDARB", "STLRB": return I8, 1 + case "LDARH", "STLRH": + return I16, 2 case "LDARW", "LDAXRW", "STLRW": return I32, 4 default: @@ -271,12 +658,20 @@ func arm64AtomicStoreExclusiveType(op Op) (LLVMType, int) { } func arm64AtomicRMWType(op Op) (LLVMType, error) { + if form, ok := parseARM64AtomicRMWOpcode(op); ok { + return form.typeName, nil + } switch op { - case "SWPALB", "LDORALB", "LDCLRALB": + case "SWPALB", "LDORALB", "LDCLRALB", + "LDEORB", "LDEORAB", "LDEORLB", "LDEORALB": return I8, nil - case "SWPALW", "LDADDALW", "LDORALW", "LDCLRALW": + case "LDEORH", "LDEORAH", "LDEORLH", "LDEORALH": + return I16, nil + case "SWPALW", "LDADDALW", "LDORALW", "LDCLRALW", + "LDEORW", "LDEORAW", "LDEORLW", "LDEORALW": return I32, nil - case "SWPALD", "LDADDALD", "LDORALD", "LDCLRALD": + case "SWPALD", "LDADDALD", "LDORALD", "LDCLRALD", + "LDEORD", "LDEORAD", "LDEORLD", "LDEORALD": return I64, nil default: return "", fmt.Errorf("arm64: unsupported atomic rmw op %s", op) @@ -287,6 +682,8 @@ func arm64AtomicTypeSize(ty LLVMType) (int, error) { switch ty { case I8: return 1, nil + case I16: + return 2, nil case I32: return 4, nil case I64: diff --git a/arm64_lower_atomic_cas_complete_test.go b/arm64_lower_atomic_cas_complete_test.go new file mode 100644 index 00000000..7da98aed --- /dev/null +++ b/arm64_lower_atomic_cas_complete_test.go @@ -0,0 +1,76 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64AtomicCASCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT atomicCASComplete(SB),$0-0\n") + for _, width := range []string{"B", "H", "W", "D"} { + orders := []string{"", "AL"} + if width == "W" || width == "D" { + orders = []string{"", "A", "L", "AL"} + } + for _, order := range orders { + opcode := "CAS" + order + width + source.WriteString("\t" + opcode + " R5, (R6), R7\n") + source.WriteString("\t" + opcode + " ZR, (RSP), ZR\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64AtomicCASCompleteFormats(t *testing.T) { + source := arm64AtomicCASCompleteForms() + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "atomicCASComplete": {Name: "atomicCASComplete", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "cmpxchg ptr", " i8 ", " i16 ", " i32 ", " i64 ", + " monotonic monotonic", " acquire acquire", " release monotonic", " acq_rel acquire", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 complete CAS lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-cas-complete.ll", "arm64-cas-complete.o", ll) +} + +func TestTranslateARM64AtomicCASRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"CASD R0, 8(R1), R2", "CASW R0, (R1)", "CASQ R0, (R1), R2"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 LSE CAS optab", instruction) + } + } +} diff --git a/arm64_lower_atomic_eor_test.go b/arm64_lower_atomic_eor_test.go new file mode 100644 index 00000000..d1a8d39e --- /dev/null +++ b/arm64_lower_atomic_eor_test.go @@ -0,0 +1,51 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestARM64LDEORCompleteFamily(t *testing.T) { + c, b := newARM64CtxWithFuncForTest(t, Func{}, FuncSig{Name: "example.ldeor", Ret: Void}, nil) + for _, register := range []Reg{"R0", "R1", "R2"} { + if err := c.storeReg(register, "1"); err != nil { + t.Fatal(err) + } + } + mem := arm64MemOp("R1", 0) + ops := []Op{ + "LDEORB", "LDEORH", "LDEORW", "LDEORD", + "LDEORAB", "LDEORAH", "LDEORAW", "LDEORAD", + "LDEORLB", "LDEORLH", "LDEORLW", "LDEORLD", + "LDEORALB", "LDEORALH", "LDEORALW", "LDEORALD", + } + for _, op := range ops { + instruction := Instr{Op: op, Args: []Operand{arm64RegOp("R0"), mem, arm64RegOp("R2")}, Raw: string(op) + " R0, (R1), R2"} + ok, terminated, err := c.lowerAtomic(op, instruction) + if err != nil || !ok || terminated { + t.Fatalf("lowerAtomic(%s) = (%v, %v, %v)", op, ok, terminated, err) + } + } + out := b.String() + if got := strings.Count(out, "atomicrmw xor"); got != len(ops) { + t.Fatalf("atomicrmw xor count = %d, want %d\n%s", got, len(ops), out) + } + for _, ty := range []string{"i8", "i16", "i32", "i64"} { + if !strings.Contains(out, "atomicrmw xor ptr") || !strings.Contains(out, ", "+ty+" ") { + t.Fatalf("missing %s LDEOR lowering:\n%s", ty, out) + } + } +} + +func TestARM64LDEORRejectsInvalidForms(t *testing.T) { + c, _ := newARM64CtxWithFuncForTest(t, Func{}, FuncSig{Name: "example.ldeor.invalid", Ret: Void}, nil) + for _, instruction := range []Instr{ + {Op: "LDEORALW", Args: []Operand{arm64RegOp("R0"), arm64MemOp("R1", 0)}, Raw: "LDEORALW R0, (R1)"}, + {Op: "LDEORALW", Args: []Operand{arm64RegOp("R0"), arm64RegOp("R1"), arm64RegOp("R2")}, Raw: "LDEORALW R0, R1, R2"}, + } { + ok, _, err := c.lowerAtomic(instruction.Op, instruction) + if !ok || err == nil { + t.Fatalf("lowerAtomic(%q) = (%v, %v), want handled error", instruction.Raw, ok, err) + } + } +} diff --git a/arm64_lower_atomic_pair.go b/arm64_lower_atomic_pair.go new file mode 100644 index 00000000..c067aed4 --- /dev/null +++ b/arm64_lower_atomic_pair.go @@ -0,0 +1,382 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +func (c *arm64Ctx) lowerAtomicPair(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "CASPW", "CASPD": + if arm64AtomicOpcodeHasSuffix(ins.Op) { + return true, false, fmt.Errorf("arm64 %s does not accept an opcode suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 3 || !arm64AtomicRegisterPair(ins.Args[0]) || ins.Args[1].Kind != OpMem || !arm64AtomicRegisterPair(ins.Args[2]) { + return true, false, fmt.Errorf("arm64 %s expects register-pair, zero-offset memory, register-pair: %q", op, ins.Raw) + } + expectedRegs := ins.Args[0].RegList + newRegs := ins.Args[2].RegList + if err := validateARM64CASPRegisterPair("source", expectedRegs); err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + if err := validateARM64CASPRegisterPair("destination", newRegs); err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + ptr, err := c.atomicPairMemPtr(ins.Args[1].Mem, true) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + + elemBits := 32 + if op == "CASPD" { + elemBits = 64 + } + return true, false, c.lowerAtomicPairCompareExchange(expectedRegs, newRegs, elemBits, ptr, "seq_cst", "seq_cst") + + case "LDXPW", "LDXP", "LDAXPW", "LDAXP": + if arm64AtomicOpcodeHasSuffix(ins.Op) { + return true, false, fmt.Errorf("arm64 %s does not accept an opcode suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[0].Kind != OpMem || !arm64AtomicRegisterPair(ins.Args[1]) { + return true, false, fmt.Errorf("arm64 %s expects zero-offset memory, register-pair: %q", op, ins.Raw) + } + regs := ins.Args[1].RegList + if err := validateARM64ExclusiveLoadPair(regs); err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + ptr, err := c.atomicPairMemPtr(ins.Args[0].Mem, false) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + elemBits := 32 + typeName := "i64" + align := 8 + if op == "LDXP" || op == "LDAXP" { + elemBits = 64 + typeName = "i128" + align = 16 + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load atomic %s, ptr %s seq_cst, align %d\n", loaded, typeName, ptr, align) + if err := c.storeAtomicPairValue(regs, elemBits, "%"+loaded); err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store i1 true, ptr %s\n", c.exclusiveValidSlot) + fmt.Fprintf(c.b, " store ptr %s, ptr %s\n", ptr, c.exclusivePtrSlot) + fmt.Fprintf(c.b, " store i8 %d, ptr %s\n", align, c.exclusiveSizeSlot) + reserved, err := c.atomicPairValueAsI128("%"+loaded, typeName) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store i128 %s, ptr %s\n", reserved, c.exclusiveValueSlot) + return true, false, nil + + case "STXPW", "STXP", "STLXPW", "STLXP": + if arm64AtomicOpcodeHasSuffix(ins.Op) { + return true, false, fmt.Errorf("arm64 %s does not accept an opcode suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 3 || !arm64AtomicRegisterPair(ins.Args[0]) || ins.Args[1].Kind != OpMem || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects register-pair, zero-offset memory, status-register: %q", op, ins.Raw) + } + regs := ins.Args[0].RegList + status := ins.Args[2].Reg + if err := validateARM64ExclusiveStorePair(regs, ins.Args[1].Mem.Base, status); err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + ptr, err := c.atomicPairMemPtr(ins.Args[1].Mem, false) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + elemBits := 32 + typeName := "i64" + align := 8 + if op == "STXP" || op == "STLXP" { + elemBits = 64 + typeName = "i128" + align = 16 + } + newValue, err := c.loadAtomicPairValue(regs, elemBits) + if err != nil { + return true, false, err + } + statusValue, err := c.lowerAtomicPairExclusiveStore(typeName, align, ptr, newValue) + if err != nil { + return true, false, err + } + return true, false, c.storeReg(status, statusValue) + } + return false, false, nil +} + +func (c *arm64Ctx) lowerAtomicPairCompareExchange(expectedRegs, newRegs []Reg, elemBits int, ptr, successOrder, failureOrder string) error { + typeName := "i64" + align := 8 + if elemBits == 64 { + typeName = "i128" + align = 16 + } else if elemBits != 32 { + return fmt.Errorf("arm64: invalid CASP element width %d", elemBits) + } + expected, err := c.loadAtomicPairValue(expectedRegs, elemBits) + if err != nil { + return err + } + newValue, err := c.loadAtomicPairValue(newRegs, elemBits) + if err != nil { + return err + } + cx := c.newTmp() + fmt.Fprintf(c.b, " %%%s = cmpxchg ptr %s, %s %s, %s %s %s %s, align %d\n", + cx, ptr, typeName, expected, typeName, newValue, successOrder, failureOrder, align) + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue {%s, i1} %%%s, 0\n", old, typeName, cx) + return c.storeAtomicPairValue(expectedRegs, elemBits, "%"+old) +} + +func arm64AtomicOpcodeHasSuffix(op Op) bool { + return strings.Contains(string(op), ".") +} + +func arm64AtomicRegisterPair(op Operand) bool { + return op.Kind == OpRegList && len(op.RegList) == 2 +} + +func arm64AtomicDataRegister(reg Reg) bool { + s := strings.ToUpper(string(reg)) + if s == "ZR" || s == "RSP" { + return true + } + if !strings.HasPrefix(s, "R") { + return false + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "R")) + return err == nil && n >= 0 && n <= 30 +} + +func arm64AtomicNumberedRegister(reg Reg) (int, bool) { + s := strings.ToUpper(string(reg)) + if !strings.HasPrefix(s, "R") || s == "RSP" { + return 0, false + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "R")) + return n, err == nil && n >= 0 && n <= 30 +} + +func validateARM64CASPRegisterPair(role string, regs []Reg) error { + if len(regs) != 2 || !arm64AtomicDataRegister(regs[0]) || !arm64AtomicDataRegister(regs[1]) { + return fmt.Errorf("%s must be a pair of general-purpose registers", role) + } + first, ok := arm64AtomicNumberedRegister(regs[0]) + if !ok || first&1 != 0 { + return fmt.Errorf("%s register pair must start from an even numbered register", role) + } + wantSecond := Reg(fmt.Sprintf("R%d", first+1)) + if first == 30 { + wantSecond = ZR + } + if regs[1] != wantSecond { + return fmt.Errorf("%s register pair must be contiguous", role) + } + return nil +} + +func validateARM64ExclusiveLoadPair(regs []Reg) error { + if len(regs) != 2 || !arm64AtomicDataRegister(regs[0]) || !arm64AtomicDataRegister(regs[1]) { + return fmt.Errorf("destination must be a pair of general-purpose registers") + } + if regs[0] == regs[1] { + return fmt.Errorf("destination register pair has constrained unpredictable behavior") + } + return nil +} + +func validateARM64ExclusiveStorePair(regs []Reg, base Reg, status Reg) error { + if len(regs) != 2 || !arm64AtomicDataRegister(regs[0]) || !arm64AtomicDataRegister(regs[1]) { + return fmt.Errorf("source must be a pair of general-purpose registers") + } + if !arm64AtomicStatusRegister(status) { + return fmt.Errorf("status must be a general-purpose register or ZR") + } + if status == regs[0] || status == regs[1] || (base != Reg("RSP") && status == base) { + return fmt.Errorf("status register overlap has constrained unpredictable behavior") + } + return nil +} + +func arm64AtomicStatusRegister(reg Reg) bool { + if reg == ZR { + return true + } + _, ok := arm64AtomicNumberedRegister(reg) + return ok +} + +func (c *arm64Ctx) atomicPairMemPtr(mem MemRef, allowNamedSP bool) (string, error) { + if mem.Sym != "" || mem.Segment != "" || mem.Index != "" || mem.Off != 0 { + return "", fmt.Errorf("paired atomic memory must have zero displacement and no index") + } + if mem.OffRaw != "" { + if !allowNamedSP || mem.Base != SP { + return "", fmt.Errorf("named SP memory is only accepted by CASP") + } + } else if mem.Base == SP { + return "", fmt.Errorf("plain SP is a pseudo-register; use RSP for register-relative memory") + } + if mem.Base != SP && mem.Base != Reg("RSP") && mem.Base != ZR { + if _, ok := arm64AtomicNumberedRegister(mem.Base); !ok { + return "", fmt.Errorf("paired atomic memory base must be R0-R30, RSP, or ZR") + } + } + return c.atomicMemPtr(mem) +} + +func (c *arm64Ctx) loadAtomicPairDataReg(reg Reg) (string, error) { + if reg == ZR || reg == Reg("RSP") { + return "0", nil + } + return c.loadReg(reg) +} + +func (c *arm64Ctx) storeAtomicPairDataReg(reg Reg, value string) error { + if reg == ZR || reg == Reg("RSP") { + return nil + } + return c.storeReg(reg, value) +} + +func (c *arm64Ctx) loadAtomicPairValue(regs []Reg, elemBits int) (string, error) { + low64, err := c.loadAtomicPairDataReg(regs[0]) + if err != nil { + return "", err + } + high64, err := c.loadAtomicPairDataReg(regs[1]) + if err != nil { + return "", err + } + if elemBits == 32 { + low32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", low32, low64) + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", low, low32) + high32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", high32, high64) + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", high, high32) + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i64 %%%s, 32\n", shifted, high) + joined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", joined, low, shifted) + return "%" + joined, nil + } + if elemBits != 64 { + return "", fmt.Errorf("arm64: invalid atomic pair element width %d", elemBits) + } + low := c.newTmp() + msg := " %%%s = zext i64 %s to i128\n" + fmt.Fprintf(c.b, msg, low, low64) + high := c.newTmp() + fmt.Fprintf(c.b, msg, high, high64) + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i128 %%%s, 64\n", shifted, high) + joined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i128 %%%s, %%%s\n", joined, low, shifted) + return "%" + joined, nil +} + +func (c *arm64Ctx) storeAtomicPairValue(regs []Reg, elemBits int, value string) error { + if elemBits == 32 { + low32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", low32, value) + low64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", low64, low32) + highShift := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i64 %s, 32\n", highShift, value) + high32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", high32, highShift) + high64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", high64, high32) + if err := c.storeAtomicPairDataReg(regs[0], "%"+low64); err != nil { + return err + } + return c.storeAtomicPairDataReg(regs[1], "%"+high64) + } + if elemBits != 64 { + return fmt.Errorf("arm64: invalid atomic pair element width %d", elemBits) + } + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i128 %s to i64\n", low, value) + highShift := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i128 %s, 64\n", highShift, value) + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", high, highShift) + if err := c.storeAtomicPairDataReg(regs[0], "%"+low); err != nil { + return err + } + return c.storeAtomicPairDataReg(regs[1], "%"+high) +} + +func (c *arm64Ctx) atomicPairValueAsI128(value, typeName string) (string, error) { + if typeName == "i128" { + return value, nil + } + if typeName != "i64" { + return "", fmt.Errorf("arm64: invalid paired atomic value type %s", typeName) + } + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i64 %s to i128\n", extended, value) + return "%" + extended, nil +} + +func (c *arm64Ctx) lowerAtomicPairExclusiveStore(typeName string, align int, ptr, newValue string) (string, error) { + loadedValid := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i1, ptr %s\n", loadedValid, c.exclusiveValidSlot) + loadedPtr := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load ptr, ptr %s\n", loadedPtr, c.exclusivePtrSlot) + ptrMatch := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq ptr %%%s, %s\n", ptrMatch, loadedPtr, ptr) + loadedSize := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i8, ptr %s\n", loadedSize, c.exclusiveSizeSlot) + sizeMatch := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i8 %%%s, %d\n", sizeMatch, loadedSize, align) + precondition := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", precondition, loadedValid, ptrMatch) + canTry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", canTry, precondition, sizeMatch) + + id := c.newTmp() + tryLabel := arm64LLVMBlockName("stxp_try_" + id) + failLabel := arm64LLVMBlockName("stxp_fail_" + id) + mergeLabel := arm64LLVMBlockName("stxp_merge_" + id) + fmt.Fprintf(c.b, " br i1 %%%s, label %%%s, label %%%s\n", canTry, tryLabel, failLabel) + + fmt.Fprintf(c.b, "\n%s:\n", tryLabel) + expected128 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i128, ptr %s\n", expected128, c.exclusiveValueSlot) + expected := "%" + expected128 + if typeName == "i64" { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", truncated, expected128) + expected = "%" + truncated + } else if typeName != "i128" { + return "", fmt.Errorf("arm64: invalid paired atomic store type %s", typeName) + } + cx := c.newTmp() + fmt.Fprintf(c.b, " %%%s = cmpxchg ptr %s, %s %s, %s %s seq_cst seq_cst, align %d\n", cx, ptr, typeName, expected, typeName, newValue, align) + succeeded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue {%s, i1} %%%s, 1\n", succeeded, typeName, cx) + failed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", failed, succeeded) + tryStatus := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to i64\n", tryStatus, failed) + fmt.Fprintf(c.b, " br label %%%s\n", mergeLabel) + + fmt.Fprintf(c.b, "\n%s:\n", failLabel) + fmt.Fprintf(c.b, " br label %%%s\n", mergeLabel) + + fmt.Fprintf(c.b, "\n%s:\n", mergeLabel) + status := c.newTmp() + fmt.Fprintf(c.b, " %%%s = phi i64 [ %%%s, %%%s ], [ 1, %%%s ]\n", status, tryStatus, tryLabel, failLabel) + fmt.Fprintf(c.b, " store i1 false, ptr %s\n", c.exclusiveValidSlot) + return "%" + status, nil +} diff --git a/arm64_lower_atomic_rmw_complete_test.go b/arm64_lower_atomic_rmw_complete_test.go new file mode 100644 index 00000000..d5d4242c --- /dev/null +++ b/arm64_lower_atomic_rmw_complete_test.go @@ -0,0 +1,74 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64AtomicRMWCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT atomicRMWComplete(SB),$0-0\n") + for _, family := range []string{"SWP", "LDADD", "LDCLR", "LDOR", "LDEOR"} { + for _, order := range []string{"", "A", "L", "AL"} { + for _, width := range []string{"B", "H", "W", "D"} { + opcode := family + order + width + source.WriteString("\t" + opcode + " R5, (R6), R7\n") + source.WriteString("\t" + opcode + " R5, (RSP), ZR\n") + } + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64AtomicRMWCompleteFormats(t *testing.T) { + source := arm64AtomicRMWCompleteForms() + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "atomicRMWComplete": {Name: "atomicRMWComplete", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "atomicrmw xchg", "atomicrmw add", "atomicrmw and", "atomicrmw or", "atomicrmw xor", + " i8 ", " i16 ", " i32 ", " i64 ", " monotonic", " acquire", " release", " acq_rel", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 complete atomic RMW lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-atomic-rmw-complete.ll", "arm64-atomic-rmw-complete.o", ll) +} + +func TestTranslateARM64AtomicRMWRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"SWPD R0, 8(R1), R2", "LDADDW R0, (R1)", "LDCLRQ R0, (R1), R2"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 LSE atomic RMW optab", instruction) + } + } +} diff --git a/arm64_lower_barrier.go b/arm64_lower_barrier.go new file mode 100644 index 00000000..cffe13eb --- /dev/null +++ b/arm64_lower_barrier.go @@ -0,0 +1,34 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerARM64Barrier implements Go's ADMB optab row, the ADSB/AISB aliases +// installed from it, and the operand-free ASB row. +func (c *arm64Ctx) lowerARM64Barrier(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "SB": + if strings.ToUpper(string(ins.Op)) != "SB" || len(ins.Args) != 0 { + return true, false, fmt.Errorf("arm64 SB accepts no operands or suffix: %q", ins.Raw) + } + // SB is encoded as HINT #7. Spelling the backward-compatible encoding + // directly lets LLVM 22 compile the same object for every ARM64 baseline; + // the memory clobber preserves the compiler-barrier semantics. + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q()\n", "hint #7", "~{memory}") + return true, false, nil + case "DMB", "DSB", "ISB": + default: + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 1 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 %s expects exactly one constant operand with no suffix: %q", op, ins.Raw) + } + encoded := uint64(ins.Args[0].Imm) & 0xf + // Preserve the architectural operation instead of substituting a weaker + // generic LLVM fence. The memory clobber also prevents compiler reordering + // across DMB/DSB and is conservative for ISB. + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q()\n", strings.ToLower(string(op))+fmt.Sprintf(" #%d", encoded), "~{memory}") + return true, false, nil +} diff --git a/arm64_lower_barrier_test.go b/arm64_lower_barrier_test.go new file mode 100644 index 00000000..01d9da2b --- /dev/null +++ b/arm64_lower_barrier_test.go @@ -0,0 +1,102 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +const arm64BarrierForms = ` +TEXT barrierforms(SB),$0-0 + DMB $0 + DMB $1 + DMB $15 + DMB $255 + DMB $-1 + DSB $0 + DSB $7 + DSB $15 + DSB $255 + DSB $-1 + ISB $0 + ISB $1 + ISB $15 + ISB $255 + ISB $-1 + SB + RET +` + +func TestTranslateARM64BarrierCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64BarrierForms, true) + + for _, triple := range []string{ + "arm64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, arm64BarrierForms) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"barrierforms": {Name: "barrierforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `asm sideeffect "dmb #0"`, + `asm sideeffect "dmb #1"`, + `asm sideeffect "dmb #15"`, + `asm sideeffect "dsb #0"`, + `asm sideeffect "dsb #7"`, + `asm sideeffect "dsb #15"`, + `asm sideeffect "isb #0"`, + `asm sideeffect "isb #1"`, + `asm sideeffect "isb #15"`, + `asm sideeffect "hint #7"`, + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 barrier lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + // Go masks C_VCON values to the low four encoded bits. + if got := strings.Count(ll, `asm sideeffect "dmb #15"`); got != 3 { + t.Fatalf("DMB low-four-bit lowering count = %d, want 3:\n%s", got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-barriers.ll", "arm64-barriers.o", ll) + }) + } +} + +func TestTranslateARM64BarrierRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "DMB", + "DSB R0", + "ISB $1, $2", + "DMB.P $1", + "SB $1", + "SB.P", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's barrier forms", instruction) + } + } +} diff --git a/arm64_lower_bit_clear.go b/arm64_lower_bit_clear.go new file mode 100644 index 00000000..ce6d2547 --- /dev/null +++ b/arm64_lower_bit_clear.go @@ -0,0 +1,111 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64BitClear(op Op, ins Instr) (ok bool, terminated bool, err error) { + word := op == "BICW" || op == "BICSW" + setFlags := op == "BICS" || op == "BICSW" + if !word && !setFlags && op != "BIC" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects 2 or 3 operands: %q", op, ins.Raw) + } + if !arm64BitClearSourceValid(ins.Args[0], word) { + return true, false, fmt.Errorf("arm64 %s invalid first operand: %q", op, ins.Raw) + } + + destinationIndex := len(ins.Args) - 1 + destination := ins.Args[destinationIndex] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s destination must be a register: %q", op, ins.Raw) + } + destinationGeneral := isARM64GeneralOrZeroReg(destination.Reg) + destinationStack := destination.Reg == SP || destination.Reg == Reg("RSP") + if !destinationGeneral && !(len(ins.Args) == 3 && !setFlags && ins.Args[0].Kind == OpImm && destinationStack) { + return true, false, fmt.Errorf("arm64 %s invalid destination register: %q", op, ins.Raw) + } + + leftOperand := destination + if len(ins.Args) == 3 { + leftOperand = ins.Args[1] + if leftOperand.Kind != OpReg || !isARM64GeneralOrZeroReg(leftOperand.Reg) { + return true, false, fmt.Errorf("arm64 %s second operand must be a general register: %q", op, ins.Raw) + } + } + + if word { + right, err := c.eval32(ins.Args[0]) + if err != nil { + return true, false, err + } + left, err := c.eval32(leftOperand) + if err != nil { + return true, false, err + } + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i32 %s, -1\n", inverted, right) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i32 %s, %%%s\n", result, left, inverted) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, result) + if err := c.storeReg(destination.Reg, "%"+wide); err != nil { + return true, false, err + } + if setFlags { + c.setFlagsLogic32("%" + result) + } + return true, false, nil + } + + right, err := c.eval64(ins.Args[0], false) + if err != nil { + return true, false, err + } + left, err := c.eval64(leftOperand, false) + if err != nil { + return true, false, err + } + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i64 %s, -1\n", inverted, right) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %%%s\n", result, left, inverted) + if err := c.storeReg(destination.Reg, "%"+result); err != nil { + return true, false, err + } + if setFlags { + c.setFlagsLogic("%" + result) + } + return true, false, nil +} + +func arm64BitClearSourceValid(operand Operand, word bool) bool { + switch operand.Kind { + case OpImm: + return operand.ImmRaw == "" + case OpReg: + return isARM64GeneralOrZeroReg(operand.Reg) + case OpRegShift: + if !isARM64GeneralOrZeroReg(operand.Reg) || operand.ShiftReg != "" { + return false + } + switch operand.ShiftOp { + case ShiftLeft, ShiftRight, ShiftArith, ShiftRotate: + default: + return false + } + limit := int64(63) + if word { + limit = 31 + } + return operand.ShiftAmount >= 0 && operand.ShiftAmount <= limit + default: + return false + } +} diff --git a/arm64_lower_bit_clear_test.go b/arm64_lower_bit_clear_test.go new file mode 100644 index 00000000..3dee6961 --- /dev/null +++ b/arm64_lower_bit_clear_test.go @@ -0,0 +1,166 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64BitClearCompleteGo127Forms(t *testing.T) { + const source = `TEXT bitClearForms(SB), $0-0 + BIC R0, R1 + BIC R2, R3, R4 + BIC R5>>7, R6, R7 + BIC $255, R8, R9 + BIC $255, R9, RSP + BICW R10, R11 + BICW R12->3, R13, R14 + BICW $255, R15, R16 + BICS R17, R19 + BICS R20->12, R21, R22 + BICS $255, R23, R24 + BICSW R24, R25 + BICSW R26@>15, R27, R29 + BICSW $255, R30, R0 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "bitClearForms": {Name: "bitClearForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"xor i64", "and i64", "xor i32", "and i32", "icmp slt i64", "icmp slt i32"} { + if !strings.Contains(ir, want) { + t.Fatalf("bit-clear lowering omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-bit-clear.ll", "arm64-bit-clear.o", ir) + }) + } +} + +func TestTranslateARM64BitClearRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, instruction := range []string{ + "BIC R0", + "BIC R0, R1, R2, R3", + "BIC (R0), R1", + "BIC R0.UXTB, R1", + "BIC RSP, R1", + "BICW R0<<32, R1", + "BICS R0, RSP", + "BICSW.P R0, R1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badBitClear(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badBitClear": {Name: "badBitClear", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's BIC optab", instruction) + } + }) + } +} + +func TestARM64BitClearRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT bitClearRuntime(SB), $0-24 + MOVD mask+0(FP), R0 + MOVD value+8(FP), R1 + MOVD out+16(FP), R2 + BIC R0, R1, R3 + MOVD R3, 0(R2) + BICS R0, R1, R3 + MOVD R3, 8(R2) + CSET MI, R4 + MOVD R4, 16(R2) + CSET EQ, R4 + MOVD R4, 24(R2) + CSET CS, R4 + MOVD R4, 32(R2) + CSET VS, R4 + MOVD R4, 40(R2) + BICSW R0, R1, R3 + MOVD R3, 48(R2) + CSET MI, R4 + MOVD R4, 56(R2) + CSET EQ, R4 + MOVD R4, 64(R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "bitClearRuntime": { + Name: "bitClearRuntime", Args: []LLVMType{I64, I64, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void bitClearRuntime(uint64_t, uint64_t, uint64_t *); +int main(void) { + const uint64_t mask = UINT64_C(0x00ff00ff00ff00ff); + const uint64_t value = UINT64_C(0xf0f00000f0f00000); + uint64_t got[9] = {0}; + bitClearRuntime(mask, value, got); + const uint64_t result = value & ~mask; + const uint32_t word = (uint32_t)value & ~(uint32_t)mask; + const uint64_t want[9] = {result, result, result >> 63, result == 0, 0, 0, word, word >> 31, word == 0}; + for (int i = 0; i < 9; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_bit_clear", triple, ir, mainC, nil) +} diff --git a/arm64_lower_bit_reverse.go b/arm64_lower_bit_reverse.go new file mode 100644 index 00000000..a0c3ce8a --- /dev/null +++ b/arm64_lower_bit_reverse.go @@ -0,0 +1,39 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64BitReverse(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "RBIT" && op != "RBITW" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg || + !isARM64GeneralOrZeroReg(ins.Args[0].Reg) || !isARM64GeneralOrZeroReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm64 %s expects general register, general register: %q", op, ins.Raw) + } + + if op == "RBITW" { + source, err := c.eval32(ins.Args[0]) + if err != nil { + return true, false, err + } + reversed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.bitreverse.i32(i32 %s)\n", reversed, source) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, reversed) + return true, false, c.storeReg(ins.Args[1].Reg, "%"+wide) + } + + source, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + reversed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.bitreverse.i64(i64 %s)\n", reversed, source) + return true, false, c.storeReg(ins.Args[1].Reg, "%"+reversed) +} diff --git a/arm64_lower_bit_reverse_test.go b/arm64_lower_bit_reverse_test.go new file mode 100644 index 00000000..8aa08e8e --- /dev/null +++ b/arm64_lower_bit_reverse_test.go @@ -0,0 +1,139 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64BitReverseCompleteGo127Forms(t *testing.T) { + const source = `TEXT bitReverseForms(SB), $0-0 + RBIT R0, R1 + RBITW R2, R3 + RBIT ZR, ZR + RBITW ZR, ZR + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "bitReverseForms": {Name: "bitReverseForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"@llvm.bitreverse.i64", "@llvm.bitreverse.i32", "zext i32"} { + if !strings.Contains(ir, want) { + t.Fatalf("bit-reverse lowering omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-bit-reverse.ll", "arm64-bit-reverse.o", ir) + }) + } +} + +func TestTranslateARM64BitReverseRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, instruction := range []string{ + "RBIT R0", + "RBIT $1, R0", + "RBIT R0, R1, R2", + "RBIT R0, (R1)", + "RBIT RSP, R0", + "RBIT V0, R0", + "RBITW.P R0, R1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badBitReverse(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badBitReverse": {Name: "badBitReverse", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's RBIT optab", instruction) + } + }) + } +} + +func TestARM64BitReverseRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT bitReverseRuntime(SB), $0-16 + MOVD value+0(FP), R0 + MOVD out+8(FP), R1 + RBIT R0, R2 + MOVD R2, 0(R1) + RBITW R0, R2 + MOVD R2, 8(R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "bitReverseRuntime": { + Name: "bitReverseRuntime", Args: []LLVMType{I64, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void bitReverseRuntime(uint64_t, uint64_t *); +static uint64_t reverse64(uint64_t value, int bits) { + uint64_t result = 0; + for (int i = 0; i < bits; i++) result = (result << 1) | ((value >> i) & 1); + return result; +} +int main(void) { + const uint64_t value = UINT64_C(0x0123456789abcdef); + uint64_t got[2] = {0, 0}; + bitReverseRuntime(value, got); + return got[0] != reverse64(value, 64) || got[1] != reverse64((uint32_t)value, 32); +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_bit_reverse", triple, ir, mainC, nil) +} diff --git a/arm64_lower_branch.go b/arm64_lower_branch.go index f7073192..db5e9377 100644 --- a/arm64_lower_branch.go +++ b/arm64_lower_branch.go @@ -29,7 +29,40 @@ func (c *arm64Ctx) lowerBranch(bi int, op Op, ins Instr, emitBr arm64EmitBr, emi if len(ins.Args) != 1 { return true, false, fmt.Errorf("arm64 %s expects 1 operand: %q", op, ins.Raw) } + if strings.Contains(strings.ToUpper(string(ins.Op)), ".") { + return true, false, fmt.Errorf("arm64 %s does not accept a suffix: %q", op, ins.Raw) + } + if arm64IsLocalBranchLink(ins) { + target, targetOK := c.resolveBranchTarget(bi, ins.Args[0]) + if !targetOK { + return true, false, fmt.Errorf("arm64 %s invalid local target: %q", op, ins.Raw) + } + knownTarget := false + for _, block := range c.blocks { + if block.name == target { + knownTarget = true + break + } + } + if !knownTarget { + return true, false, fmt.Errorf("arm64 %s undefined local target %q: %q", op, target, ins.Raw) + } + if bi+1 >= len(c.blocks) { + return true, false, fmt.Errorf("arm64 %s local target has no continuation block: %q", op, ins.Raw) + } + continuation := c.blocks[bi+1].name + link := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ptrtoint ptr blockaddress(%s, %%%s) to i64\n", link, llvmGlobal(c.sig.Name), arm64LLVMBlockName(continuation)) + if err := c.storeReg(Reg("R30"), "%"+link); err != nil { + return true, false, err + } + emitBr(target) + return true, true, nil + } if ins.Args[0].Kind == OpReg { + if !isARM64GeneralOrZeroReg(ins.Args[0].Reg) { + return true, false, fmt.Errorf("arm64 %s expects general register: %q", op, ins.Raw) + } addr, err := c.loadReg(ins.Args[0].Reg) if err != nil { return true, false, err @@ -38,6 +71,11 @@ func (c *arm64Ctx) lowerBranch(bi int, op Op, ins Instr, emitBr arm64EmitBr, emi return true, false, nil } if ins.Args[0].Kind == OpMem { + mem := ins.Args[0].Mem + baseOK := isARM64GeneralOrZeroReg(mem.Base) || mem.Base == SP || mem.Base == Reg("RSP") + if !baseOK || mem.Off != 0 || mem.Index != "" { + return true, false, fmt.Errorf("arm64 %s expects (general register): %q", op, ins.Raw) + } addr, _, _, err := c.addrI64(ins.Args[0].Mem, false) if err != nil { return true, false, err @@ -289,6 +327,96 @@ func (c *arm64Ctx) structArgFromSequentialRegs(aggTy LLVMType, regCursor *int) ( return agg, nil } +func (c *arm64Ctx) abi0CallStackPtr(off int64) (string, error) { + sp, err := c.loadReg(SP) + if err != nil { + return "", fmt.Errorf("ABI0 call stack: %w", err) + } + // Go's arm64 ABI0 outgoing call frame reserves the first pointer-sized + // slot for the saved link register. Callee FP offset zero is therefore + // caller RSP+8, as emitted by the Go compiler before ABI0 wrapper calls. + const linkSlotSize = int64(8) + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %d\n", next, sp, off+linkSlotSize) + addr := "%" + next + ptr := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", ptr, addr) + return "%" + ptr, nil +} + +func (c *arm64Ctx) abi0CallArgs(callee string, sig FuncSig) ([]string, error) { + slotsByArg := make([][]FrameSlot, len(sig.Args)) + for _, slot := range sig.Frame.Params { + if slot.Index < 0 || slot.Index >= len(sig.Args) { + return nil, fmt.Errorf("arm64 call %q: ABI0 parameter at +%d has invalid argument index %d", callee, slot.Offset, slot.Index) + } + slotsByArg[slot.Index] = append(slotsByArg[slot.Index], slot) + } + args := make([]string, 0, len(sig.Args)) + for argIndex, argType := range sig.Args { + slots := slotsByArg[argIndex] + if len(slots) == 0 { + return nil, fmt.Errorf("arm64 call %q: ABI0 argument %d has no frame slot", callee, argIndex) + } + if len(slots) == 1 && len(frameSlotFields(slots[0])) == 0 { + if slots[0].Type != argType { + return nil, fmt.Errorf("arm64 call %q: ABI0 argument %d frame type %s does not match %s", callee, argIndex, slots[0].Type, argType) + } + ptr, err := c.abi0CallStackPtr(slots[0].Offset) + if err != nil { + return nil, err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", value, argType, ptr) + args = append(args, fmt.Sprintf("%s %%%s", argType, value)) + continue + } + aggregate := "undef" + for _, slot := range slots { + if len(frameSlotFields(slot)) == 0 { + return nil, fmt.Errorf("arm64 call %q: ABI0 aggregate argument %d has a scalar frame slot", callee, argIndex) + } + ptr, err := c.abi0CallStackPtr(slot.Offset) + if err != nil { + return nil, err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s, align 1\n", value, slot.Type, ptr) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertvalue %s %s, %s %%%s%s\n", inserted, argType, aggregate, slot.Type, value, frameSlotExtractSuffix(slot)) + aggregate = "%" + inserted + } + args = append(args, fmt.Sprintf("%s %s", argType, aggregate)) + } + return args, nil +} + +func (c *arm64Ctx) storeABI0CallResult(callee string, sig FuncSig, result string) error { + if len(sig.Frame.Results) == 0 { + return fmt.Errorf("arm64 call %q: ABI0 result %s has no frame slot", callee, sig.Ret) + } + fields, aggregate := parseLiteralStructFields(sig.Ret) + for _, slot := range sig.Frame.Results { + value := result + if aggregate { + if slot.Index < 0 || slot.Index >= len(fields) || fields[slot.Index] != slot.Type { + return fmt.Errorf("arm64 call %q: ABI0 result slot %d does not match %s", callee, slot.Index, sig.Ret) + } + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", extracted, sig.Ret, result, slot.Index) + value = "%" + extracted + } else if slot.Index != 0 || slot.Type != sig.Ret { + return fmt.Errorf("arm64 call %q: ABI0 scalar result frame does not match %s", callee, sig.Ret) + } + ptr, err := c.abi0CallStackPtr(slot.Offset) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s %s, ptr %s, align 1\n", slot.Type, value, ptr) + } + return nil +} + func (c *arm64Ctx) callSym(symOp Operand) error { if symOp.Kind != OpSym { return fmt.Errorf("arm64 call expects sym operand, got %s", symOp.String()) @@ -297,6 +425,7 @@ func (c *arm64Ctx) callSym(symOp Operand) error { if !strings.HasSuffix(s, "(SB)") { return fmt.Errorf("arm64 call expects (SB) symbol, got %q", s) } + internalABI := strings.HasSuffix(strings.TrimSuffix(s, "(SB)"), "") s = strings.TrimSuffix(s, "(SB)") callee := c.resolve(s) // Syscall stubs invoke runtime entersyscall/exitsyscall around SVC. @@ -310,40 +439,20 @@ func (c *arm64Ctx) callSym(symOp Operand) error { csig = FuncSig{Name: callee, Ret: Void} } callee = funcSigSymbol(callee, csig) - args := make([]string, 0, len(csig.Args)) - regCursor := 0 - for i := 0; i < len(csig.Args); i++ { - argTy := csig.Args[i] - if len(csig.ArgRegs) == 0 { - if fields, ok := parseLiteralStructFields(argTy); ok && literalFieldsAllScalar(fields) { - agg, err := c.structArgFromSequentialRegs(argTy, ®Cursor) - if err != nil { - return fmt.Errorf("arm64 call %q: %w", callee, err) - } - args = append(args, fmt.Sprintf("%s %s", argTy, agg)) - continue - } - } - - r := Reg("") - if len(csig.ArgRegs) > 0 { - r = Reg(fmt.Sprintf("R%d", i)) - if i < len(csig.ArgRegs) { - r = csig.ArgRegs[i] - } - } else { - r = Reg(fmt.Sprintf("R%d", regCursor)) - regCursor++ - } - v, err := c.loadReg(r) + stackABI := !internalABI && len(csig.ArgRegs) == 0 && len(csig.Frame.Params) != 0 + var args []string + if stackABI { + var err error + args, err = c.abi0CallArgs(callee, csig) if err != nil { return err } - val, err := c.castI64RegToArg(v, argTy) + } else { + var err error + args, err = c.abiRegisterCallArgs(callee, csig) if err != nil { - return fmt.Errorf("arm64 call %q unsupported arg type %s", callee, argTy) + return err } - args = append(args, fmt.Sprintf("%s %s", argTy, val)) } if csig.Ret == Void { fmt.Fprintf(c.b, " call void %s(%s)\n", llvmGlobal(callee), strings.Join(args, ", ")) @@ -351,41 +460,10 @@ func (c *arm64Ctx) callSym(symOp Operand) error { } t := c.newTmp() fmt.Fprintf(c.b, " %%%s = call %s %s(%s)\n", t, csig.Ret, llvmGlobal(callee), strings.Join(args, ", ")) - switch csig.Ret { - case I64: - return c.storeReg(Reg("R0"), "%"+t) - case I32, I16, I8, I1: - z := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext %s %%%s to i64\n", z, csig.Ret, t) - return c.storeReg(Reg("R0"), "%"+z) - case Ptr: - p := c.newTmp() - fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %%%s to i64\n", p, t) - return c.storeReg(Reg("R0"), "%"+p) - default: - fields, ok := parseLiteralStructFields(csig.Ret) - if !ok || !literalFieldsAllScalar(fields) { - return fmt.Errorf("arm64 call %q unsupported return type %s", callee, csig.Ret) - } - for i, fieldTy := range fields { - if i >= 8 { - return fmt.Errorf("arm64 call %q has %d scalar return fields, maximum is 8", callee, len(fields)) - } - extracted := c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, %d\n", extracted, csig.Ret, t, i) - value, scalar, err := arm64ValueAsI64(c, fieldTy, "%"+extracted) - if err != nil { - return err - } - if !scalar { - return fmt.Errorf("arm64 call %q unsupported return field type %s", callee, fieldTy) - } - if err := c.storeReg(Reg(fmt.Sprintf("R%d", i)), value); err != nil { - return err - } - } - return nil + if !internalABI && len(csig.ArgRegs) == 0 && len(csig.Frame.Results) != 0 { + return c.storeABI0CallResult(callee, csig, "%"+t) } + return c.storeABIRegisterResult(callee, csig.Ret, "%"+t) } func (c *arm64Ctx) tailCallAndRet(symOp Operand) error { @@ -396,6 +474,7 @@ func (c *arm64Ctx) tailCallAndRet(symOp Operand) error { if !strings.HasSuffix(s, "(SB)") { return fmt.Errorf("arm64 tailcall expects (SB) symbol, got %q", s) } + internalABI := strings.HasSuffix(strings.TrimSuffix(s, "(SB)"), "") s = strings.TrimSuffix(s, "(SB)") callee := c.resolve(s) csig, ok := c.sigs[callee] @@ -407,85 +486,32 @@ func (c *arm64Ctx) tailCallAndRet(symOp Operand) error { } callee = funcSigSymbol(callee, csig) - args := make([]string, 0, len(csig.Args)) - regCursor := 0 - for i := 0; i < len(csig.Args); i++ { - // If ArgRegs is empty, default to register-based passing (ABIInternal-ish) - // because most intra-asm tailcalls depend on explicit register setup. - // - // Exception: for tailcalls to Go functions with an identical signature, - // use the current function's LLVM args. This matches stdlib patterns like - // "B ·fooGeneric(SB)" that happen before any register shuffling and are - // stack-ABI tailcalls in the original asm. - useLLVMArgs := false - if len(csig.ArgRegs) == 0 && len(csig.Args) == len(c.sig.Args) && csig.Ret == c.sig.Ret { - same := true - for j := 0; j < len(csig.Args); j++ { - if csig.Args[j] != c.sig.Args[j] { - same = false - break - } - } - useLLVMArgs = same - } - if useLLVMArgs { - if i >= len(c.sig.Args) { - return fmt.Errorf("arm64 tailcall %q: need %d args, caller has %d", callee, len(csig.Args), len(c.sig.Args)) - } - fromTy := c.sig.Args[i] - fromVal := fmt.Sprintf("%%arg%d", i) - toTy := csig.Args[i] - if fromTy == toTy { - args = append(args, fmt.Sprintf("%s %s", toTy, fromVal)) - continue - } - t := c.newTmp() - switch { - case fromTy == I64 && (toTy == I1 || toTy == I8 || toTy == I16 || toTy == I32): - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to %s\n", t, fromVal, toTy) - args = append(args, fmt.Sprintf("%s %%%s", toTy, t)) - case (fromTy == I1 || fromTy == I8 || fromTy == I16 || fromTy == I32) && toTy == I64: - fmt.Fprintf(c.b, " %%%s = zext %s %s to i64\n", t, fromTy, fromVal) - args = append(args, "i64 %"+t) - case fromTy == I64 && toTy == Ptr: - fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", t, fromVal) - args = append(args, "ptr %"+t) - case fromTy == Ptr && toTy == I64: - fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %s to i64\n", t, fromVal) - args = append(args, "i64 %"+t) - default: - return fmt.Errorf("arm64 tailcall %q: unsupported arg cast %s -> %s", callee, fromTy, toTy) - } - continue - } - - if len(csig.ArgRegs) == 0 { - if fields, ok := parseLiteralStructFields(csig.Args[i]); ok && literalFieldsAllScalar(fields) { - agg, err := c.structArgFromSequentialRegs(csig.Args[i], ®Cursor) - if err != nil { - return fmt.Errorf("arm64 tailcall %q: %w", callee, err) - } - args = append(args, fmt.Sprintf("%s %s", csig.Args[i], agg)) - continue + useLLVMArgs := len(csig.ArgRegs) == 0 && len(csig.Args) == len(c.sig.Args) && csig.Ret == c.sig.Ret + if useLLVMArgs { + for i := range csig.Args { + if csig.Args[i] != c.sig.Args[i] { + useLLVMArgs = false + break } } - - r := Reg("") - if i < len(csig.ArgRegs) { - r = csig.ArgRegs[i] - } else { - r = Reg(fmt.Sprintf("R%d", regCursor)) - regCursor++ + } + args := make([]string, 0, len(csig.Args)) + if useLLVMArgs { + for i, typ := range csig.Args { + args = append(args, fmt.Sprintf("%s %%arg%d", typ, i)) } - v, err := c.loadReg(r) + } else if !internalABI && len(csig.ArgRegs) == 0 && len(csig.Frame.Params) != 0 { + var err error + args, err = c.abi0CallArgs(callee, csig) if err != nil { - return err + return fmt.Errorf("arm64 tailcall: %w", err) } - val, err := c.castI64RegToArg(v, csig.Args[i]) + } else { + var err error + args, err = c.abiRegisterCallArgs(callee, csig) if err != nil { - return fmt.Errorf("arm64 tailcall unsupported arg type %q", csig.Args[i]) + return fmt.Errorf("arm64 tailcall: %w", err) } - args = append(args, fmt.Sprintf("%s %s", csig.Args[i], val)) } if csig.Ret == Void { @@ -512,7 +538,23 @@ func (c *arm64Ctx) tailCallAndRet(symOp Operand) error { return nil } if csig.Ret != c.sig.Ret { - return fmt.Errorf("arm64 tailcall return mismatch: caller %s callee %s", c.sig.Ret, csig.Ret) + conv := c.newTmp() + calleeBits, calleeInteger := armIntegerTypeWidth(csig.Ret) + callerBits, callerInteger := armIntegerTypeWidth(c.sig.Ret) + switch { + case calleeInteger && callerInteger && calleeBits > callerBits: + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", conv, csig.Ret, call, c.sig.Ret) + case calleeInteger && callerInteger && calleeBits < callerBits: + fmt.Fprintf(c.b, " %%%s = zext %s %%%s to %s\n", conv, csig.Ret, call, c.sig.Ret) + case csig.Ret == Ptr && c.sig.Ret == I64: + fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %%%s to i64\n", conv, call) + case csig.Ret == I64 && c.sig.Ret == Ptr: + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %%%s to ptr\n", conv, call) + default: + return fmt.Errorf("arm64 tailcall return mismatch: caller %s callee %s", c.sig.Ret, csig.Ret) + } + fmt.Fprintf(c.b, " ret %s %%%s\n", c.sig.Ret, conv) + return nil } fmt.Fprintf(c.b, " ret %s %%%s\n", c.sig.Ret, call) return nil diff --git a/arm64_lower_branch_link_test.go b/arm64_lower_branch_link_test.go new file mode 100644 index 00000000..8260a77e --- /dev/null +++ b/arm64_lower_branch_link_test.go @@ -0,0 +1,97 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64BranchLinkCompleteGoAssemblerForms(t *testing.T) { + const source = ` +TEXT branchLinkForms(SB),$0-0 + BL local +resume: + BL 1(PC) +afterPC: + BL R3 + BL (R4) + BL global(SB) + CALL R5 + CALL (R6) + CALL global(SB) + B done +local: + MOVD R30, R0 + B resume +done: + RET +` + requireARM64GoAssemblerResult(t, source, true) + + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-arm64", triple: "arm64-apple-darwin"}, + {name: "linux-arm64", triple: "aarch64-unknown-linux-gnu"}, + {name: "windows-arm64", triple: "aarch64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "branchLinkForms": {Name: "branchLinkForms", Ret: Void}, + "global": {Name: "global", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, "blockaddress(@branchLinkForms, %resume)") || + !strings.Contains(ll, "store i64 %") || !strings.Contains(ll, "ptr %reg_R30") { + t.Fatalf("local BL did not materialize its continuation in R30:\n%s", ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "arm64-branch-link-"+target.name+".ll", "arm64-branch-link-"+target.name+".o", ll) + }) + } +} + +func TestTranslateARM64BranchLinkRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "BL 8(R1)", + "BL RSP", + "BL V0", + "BL $1", + "BL.P R1", + "CALL 8(R1)", + "BL target, R1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badBranchLink(SB),$0-0\n\t" + instruction + "\ntarget:\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badBranchLink": {Name: "badBranchLink", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 BL table", instruction) + } + }) + } +} diff --git a/arm64_lower_cache_maintenance.go b/arm64_lower_cache_maintenance.go new file mode 100644 index 00000000..de1485d7 --- /dev/null +++ b/arm64_lower_cache_maintenance.go @@ -0,0 +1,76 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64CacheOperation string + +type arm64SystemFields struct { + op1 uint8 + cm uint8 + op2 uint8 +} + +// arm64CacheOperations mirrors exactly the cn=7 entries in Go's ARM64 +// sysInstFields table. DC is a SYS alias whose second operand is mandatory for +// every operation currently accepted by Go. +var arm64CacheOperations = map[arm64CacheOperation]arm64SystemFields{ + "IVAC": {0, 6, 1}, + "ISW": {0, 6, 2}, + "CSW": {0, 10, 2}, + "CISW": {0, 14, 2}, + "ZVA": {3, 4, 1}, + "CVAC": {3, 10, 1}, + "CVAU": {3, 11, 1}, + "CIVAC": {3, 14, 1}, + "IGVAC": {0, 6, 3}, + "IGSW": {0, 6, 4}, + "IGDVAC": {0, 6, 5}, + "IGDSW": {0, 6, 6}, + "CGSW": {0, 10, 4}, + "CGDSW": {0, 10, 6}, + "CIGSW": {0, 14, 4}, + "CIGDSW": {0, 14, 6}, + "GVA": {3, 4, 3}, + "GZVA": {3, 4, 4}, + "CGVAC": {3, 10, 3}, + "CGDVAC": {3, 10, 5}, + "CGVAP": {3, 12, 3}, + "CGDVAP": {3, 12, 5}, + "CGVADP": {3, 13, 3}, + "CGDVADP": {3, 13, 5}, + "CIGVAC": {3, 14, 3}, + "CIGDVAC": {3, 14, 5}, + "CVAP": {3, 12, 1}, + "CVADP": {3, 13, 1}, +} + +func (c *arm64Ctx) lowerARM64CacheMaintenance(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "DC" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != "DC" || len(ins.Args) != 2 || + ins.Args[0].Kind != OpIdent || ins.Args[1].Kind != OpReg || + !isARM64GeneralOrZeroReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm64 DC expects a Go cache-operation name and one R/ZR operand, with no suffix: %q", ins.Raw) + } + operation := arm64CacheOperation(strings.ToUpper(strings.TrimSpace(ins.Args[0].Ident))) + fields, exists := arm64CacheOperations[operation] + if !exists { + return true, false, fmt.Errorf("arm64 DC operation %q is outside Go's sysInstFields table: %q", operation, ins.Raw) + } + + prefix := fmt.Sprintf("sys #%d, c7, c%d, #%d", fields.op1, fields.cm, fields.op2) + if ins.Args[1].Reg == ZR { + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q()\n", prefix+", xzr", "~{memory}") + return true, false, nil + } + value, err := c.loadReg(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(i64 %s)\n", prefix+", $0", "r,~{memory}", value) + return true, false, nil +} diff --git a/arm64_lower_cache_maintenance_test.go b/arm64_lower_cache_maintenance_test.go new file mode 100644 index 00000000..785c4ba9 --- /dev/null +++ b/arm64_lower_cache_maintenance_test.go @@ -0,0 +1,111 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +const arm64CacheMaintenanceForms = ` +TEXT cachemaintenanceforms(SB),$0-0 + DC IVAC, R0 + DC ISW, R1 + DC CSW, R2 + DC CISW, R3 + DC ZVA, R4 + DC CVAC, R5 + DC CVAU, R6 + DC CIVAC, R7 + DC IGVAC, R8 + DC IGSW, R9 + DC IGDVAC, R10 + DC IGDSW, R11 + DC CGSW, R12 + DC CGDSW, R13 + DC CIGSW, R14 + DC CIGDSW, R15 + DC GVA, R16 + DC GZVA, R17 + DC CGVAC, ZR + DC CGDVAC, R19 + DC CGVAP, R20 + DC CGDVAP, R21 + DC CGVADP, R22 + DC CGDVADP, R23 + DC CIGVAC, R24 + DC CIGDVAC, R25 + DC CVAP, R26 + DC CVADP, R27 + RET +` + +func TestTranslateARM64CacheMaintenanceCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64CacheMaintenanceForms, true) + + for _, triple := range []string{ + "arm64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, arm64CacheMaintenanceForms) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"cachemaintenanceforms": {Name: "cachemaintenanceforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if got := strings.Count(ll, `asm sideeffect "sys #`); got != 28 { + t.Fatalf("ARM64 DC lowering emitted %d system operations, want 28:\n%s", got, ll) + } + for _, want := range []string{ + `asm sideeffect "sys #0, c7, c6, #1, $0"`, // IVAC + `asm sideeffect "sys #3, c7, c4, #1, $0"`, // ZVA + `asm sideeffect "sys #3, c7, c14, #1, $0"`, // CIVAC + `asm sideeffect "sys #3, c7, c10, #3, xzr"`, // CGVAC ZR + `asm sideeffect "sys #3, c7, c13, #1, $0"`, // CVADP + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 DC lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-cache-maintenance.ll", "arm64-cache-maintenance.o", ll) + }) + } +} + +func TestTranslateARM64CacheMaintenanceRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "DC PLDL1KEEP", + "DC VMALLE1IS", + "DC VAE1IS, R0", + "DC IVAC", + "DC ZVA, SP", + "DC ZVA, R0, R1", + "DC.P ZVA, R0", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's DC forms", instruction) + } + } +} diff --git a/arm64_lower_call_abi0_test.go b/arm64_lower_call_abi0_test.go new file mode 100644 index 00000000..92a65dc6 --- /dev/null +++ b/arm64_lower_call_abi0_test.go @@ -0,0 +1,203 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestARM64ABI0CallUsesOutgoingStackFrameRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT ·arm64ABI0Callee(SB), $0-32 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + EOR R1, R0 + MOVD c+16(FP), R1 + EOR R1, R0 + MOVD R0, ret+24(FP) + RET + +TEXT ·arm64ABI0Caller(SB), $40-32 + MOVD a+0(FP), R10 + ADD $1, R10 + MOVD R10, 8(RSP) + MOVD b+8(FP), R10 + ADD $2, R10 + MOVD R10, 16(RSP) + MOVD c+16(FP), R10 + ADD $4, R10 + MOVD R10, 24(RSP) + BL ·arm64ABI0Callee(SB) + MOVD 32(RSP), R0 + MOVD R0, ret+24(FP) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + resolve := func(sym string) string { return strings.TrimPrefix(sym, "·") } + frame := FrameLayout{ + Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: -1, Name: "a"}, + {Offset: 8, Type: I64, Index: 1, Field: -1, Name: "b"}, + {Offset: 16, Type: I64, Index: 2, Field: -1, Name: "c"}, + }, + Results: []FrameSlot{{Offset: 24, Type: I64, Index: 0, Field: -1, Name: "ret"}}, + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: resolve, + Sigs: map[string]FuncSig{ + "arm64ABI0Callee": {Name: "arm64ABI0Callee", Args: []LLVMType{I64, I64, I64}, Ret: I64, Frame: frame}, + "arm64ABI0Caller": {Name: "arm64ABI0Caller", Args: []LLVMType{I64, I64, I64}, Ret: I64, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +extern uint64_t arm64ABI0Caller(uint64_t a, uint64_t b, uint64_t c); +int main(void) { + uint64_t got = arm64ABI0Caller(10, 20, 30); + uint64_t want = (10 + 1) ^ (20 + 2) ^ (30 + 4); + return got == want ? 0 : 1; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_abi0_call", triple, ll, mainC, nil) +} + +func TestARM64ABI0TailCallSupportsStackArgumentsBeyondRegisterBank(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + var source strings.Builder + source.WriteString("TEXT ·arm64ABI0StackTail(SB),$144-0\n") + for index := 0; index < 17; index++ { + fmt.Fprintf(&source, "\tMOVD $%d, R0\n\tMOVD R0, %d(RSP)\n", index+1, 8+index*8) + } + source.WriteString("\tJMP ·arm64ABI0TailTarget(SB)\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + args := make([]LLVMType, 17) + params := make([]FrameSlot, 17) + for index := range args { + args[index] = I64 + params[index] = FrameSlot{Offset: int64(index * 8), Type: I64, Index: index, Field: -1} + } + resolve := func(sym string) string { return strings.TrimPrefix(sym, "·") } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", ResolveSym: resolve, + Sigs: map[string]FuncSig{ + "arm64ABI0StackTail": {Name: "arm64ABI0StackTail", Ret: I64}, + "arm64ABI0TailTarget": {Name: "arm64ABI0TailTarget", Args: args, Ret: I64, Frame: FrameLayout{Params: params}}, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern uint64_t arm64ABI0StackTail(void); +uint64_t arm64ABI0TailTarget( + uint64_t a0, uint64_t a1, uint64_t a2, uint64_t a3, uint64_t a4, uint64_t a5, + uint64_t a6, uint64_t a7, uint64_t a8, uint64_t a9, uint64_t a10, uint64_t a11, + uint64_t a12, uint64_t a13, uint64_t a14, uint64_t a15, uint64_t a16) { + return a0+a1+a2+a3+a4+a5+a6+a7+a8+a9+a10+a11+a12+a13+a14+a15+a16; +} +int main(void) { return arm64ABI0StackTail() == 153 ? 0 : 1; } +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_abi0_stack_tail", triple, ir, mainC, nil) +} + +func TestARM64ABIInternalCallUsesIndependentRegisterBanks(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT ·arm64ABIRegisterForward(SB), $0-0 + BL ·arm64ABIRegisterCallee(SB) + RET + +TEXT ·arm64ABIFloatForward(SB), $0-0 + BL ·arm64ABIFloatCallee(SB) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + resolve := func(sym string) string { return strings.TrimPrefix(sym, "·") } + args := []LLVMType{I64, LLVMType("float"), LLVMType("double"), I64} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: resolve, + Sigs: map[string]FuncSig{ + "arm64ABIRegisterForward": {Name: "arm64ABIRegisterForward", Args: args, Ret: I64}, + "arm64ABIRegisterCallee": {Name: "arm64ABIRegisterCallee", Args: args, Ret: I64}, + "arm64ABIFloatForward": {Name: "arm64ABIFloatForward", Args: []LLVMType{LLVMType("float")}, Ret: LLVMType("float")}, + "arm64ABIFloatCallee": {Name: "arm64ABIFloatCallee", Args: []LLVMType{LLVMType("float")}, Ret: LLVMType("float")}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +#include +extern uint64_t arm64ABIRegisterForward(uint64_t first, float single, double dbl, uint64_t second); +extern float arm64ABIFloatForward(float value); +uint64_t arm64ABIRegisterCallee(uint64_t first, float single, double dbl, uint64_t second) { + uint32_t single_bits; + uint64_t double_bits; + memcpy(&single_bits, &single, sizeof(single_bits)); + memcpy(&double_bits, &dbl, sizeof(double_bits)); + return first ^ single_bits ^ double_bits ^ second; +} +float arm64ABIFloatCallee(float value) { return value * 2.0f; } +int main(void) { + const uint64_t first = UINT64_C(0x123456789abcdef0); + const uint64_t second = UINT64_C(0xfedcba9876543210); + const float single = -13.25f; + const double dbl = 91.5; + uint32_t single_bits; + uint64_t double_bits; + memcpy(&single_bits, &single, sizeof(single_bits)); + memcpy(&double_bits, &dbl, sizeof(double_bits)); + uint64_t want = first ^ single_bits ^ double_bits ^ second; + if (arm64ABIRegisterForward(first, single, dbl, second) != want) return 1; + if (arm64ABIFloatForward(1.25f) != 2.5f) return 2; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_abi_register_call", triple, ll, mainC, nil) +} diff --git a/arm64_lower_clrex_test.go b/arm64_lower_clrex_test.go new file mode 100644 index 00000000..4b778a12 --- /dev/null +++ b/arm64_lower_clrex_test.go @@ -0,0 +1,73 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64CLREXCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 accepts CLREX with no operand or with one C_VCON immediate. + // The encoder uses the low four immediate bits, so values outside 0..15 + // remain valid spellings even though the immediate does not affect our + // exclusive-monitor model. + source := ` +TEXT clrexforms(SB),NOSPLIT,$0-0 + CLREX + CLREX $0 + CLREX $15 + CLREX $255 + RET +` + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-arm64", triple: "arm64-apple-darwin"}, + {name: "linux-arm64", triple: "aarch64-unknown-linux-gnu"}, + {name: "windows-arm64", triple: "aarch64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"clrexforms": {Name: "clrexforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + // One initialization plus one clear for every CLREX instruction. + if got := strings.Count(ll, "store i1 false, ptr %exclusive_valid"); got != 5 { + t.Fatalf("exclusive monitor clear count = %d, want 5\n%s", got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "clrex-"+target.name+".ll", "clrex-"+target.name+".o", ll) + }) + } +} + +func TestTranslateARM64CLREXRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "CLREX R0", + "CLREX $1, $2", + "CLREX.Z", + } { + file, err := Parse(ArchARM64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's CLREX forms", instruction) + } + } +} diff --git a/arm64_lower_compare_negative.go b/arm64_lower_compare_negative.go new file mode 100644 index 00000000..d5ef60d3 --- /dev/null +++ b/arm64_lower_compare_negative.go @@ -0,0 +1,48 @@ +package plan9asm + +import "fmt" + +func validateARM64CompareNegativeOperands(source, destination Operand, word bool) error { + if destination.Kind != OpReg || !(isARM64GeneralOrZeroReg(destination.Reg) || destination.Reg == SP || destination.Reg == Reg("RSP")) { + return fmt.Errorf("destination is outside Go 1.27's C_ZREG/C_RSP classes") + } + switch source.Kind { + case OpImm: + return nil + case OpReg: + if !isARM64GeneralOrZeroReg(source.Reg) { + return fmt.Errorf("register source is outside Go 1.27's C_ZREG class") + } + return nil + case OpRegShift: + if !isARM64GeneralOrZeroReg(source.Reg) || source.ShiftReg != "" { + return fmt.Errorf("shifted source is outside Go 1.27's C_SHIFT class") + } + if source.ShiftOp != ShiftLeft && source.ShiftOp != ShiftRight && source.ShiftOp != ShiftArith { + return fmt.Errorf("shift operator %q is outside Go 1.27's C_SHIFT class", source.ShiftOp) + } + maximum := int64(63) + if word { + maximum = 31 + } + if source.ShiftAmount < 0 || source.ShiftAmount > maximum { + return fmt.Errorf("shift amount %d is outside 0..%d", source.ShiftAmount, maximum) + } + return nil + case OpRegExtend: + if !isARM64GeneralOrZeroReg(source.Reg) || source.ShiftReg != "" || source.ShiftAmount < 0 || source.ShiftAmount > 4 { + return fmt.Errorf("extended source is outside Go 1.27's C_EXTREG class") + } + switch source.Ext { + case ExtendUXTB, ExtendUXTH, ExtendUXTW, ExtendSXTB, ExtendSXTH, ExtendSXTW: + return nil + case ExtendUXTX, ExtendSXTX: + if !word { + return nil + } + } + return fmt.Errorf("extension %q is invalid for the %d-bit form", source.Ext, map[bool]int{true: 32, false: 64}[word]) + default: + return fmt.Errorf("source is outside Go 1.27's immediate/C_ZREG/C_SHIFT/C_EXTREG classes") + } +} diff --git a/arm64_lower_compare_negative_test.go b/arm64_lower_compare_negative_test.go new file mode 100644 index 00000000..dfe047da --- /dev/null +++ b/arm64_lower_compare_negative_test.go @@ -0,0 +1,145 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64CompareNegativeCompleteGo127Forms(t *testing.T) { + const source = `TEXT compareNegativeForms(SB), $0-0 + CMNW R21.UXTB<<4, R15 + CMN R0.UXTW<<4, R16 + CMNW R13>>8, R9 + CMN R6->17, R3 + CMNW $(2<<12), R5 + CMN $(8<<12), R12 + CMN R6->0, R3 + CMN R6, R3 + CMNW R30, R5 + CMNW $2, R5 + CMN ZR, R3 + CMN R1.SXTX<<2, R10 + CMNW R1.SXTB, R9 + CMN R1<<3, RSP + CMNW $0x3fffffc0, R2 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "compareNegativeForms": {Name: "compareNegativeForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"add i64", "add i32", "icmp ult i32", "icmp slt i32"} { + if !strings.Contains(ll, want) { + t.Fatalf("CMN/CMNW lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-cmn.ll", "arm64-cmn.o", ll) + }) + } +} + +func TestTranslateARM64CompareNegativeRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, instruction := range []string{ + "CMN R0", + "CMNW R0, R1, R2", + "CMN (R0), R1", + "CMNW R0@>1, R1", + "CMN R0.UXTB<<5, R1", + "CMNW.P R0, R1", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT badCompareNegative(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badCompareNegative": {Name: "badCompareNegative", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's CMN/CMNW optab", instruction) + } + }) + } +} + +func TestARM64CompareNegativeRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT compareNegativeRuntime(SB), $0-16 + MOVD value+0(FP), R0 + MOVD $0, R1 + CMNW $1, R0 + BNE notWordMinusOne + ORR $1, R1 +notWordMinusOne: + CMN $1, R0 + BNE done + ORR $2, R1 +done: + MOVD R1, ret+8(FP) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "compareNegativeRuntime": { + Name: "compareNegativeRuntime", Args: []LLVMType{I64}, Ret: I64, + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: I64, Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 8, Type: I64, Index: 0, Field: -1}}, + }, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern uint64_t compareNegativeRuntime(uint64_t); +int main(void) { + if (compareNegativeRuntime(UINT64_C(0xffffffffffffffff)) != 3) return 1; + if (compareNegativeRuntime(UINT64_C(0x00000000ffffffff)) != 1) return 2; + if (compareNegativeRuntime(7) != 0) return 3; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_cmn", triple, ll, mainC, nil) +} diff --git a/arm64_lower_conditional_compare_complete_test.go b/arm64_lower_conditional_compare_complete_test.go new file mode 100644 index 00000000..e08a1e7e --- /dev/null +++ b/arm64_lower_conditional_compare_complete_test.go @@ -0,0 +1,72 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64ConditionalCompareCompleteFormats(t *testing.T) { + const source = `TEXT conditionalCompareComplete(SB),$0-0 + CMP R0, R0 + CCMN MI, ZR, R1, $4 + CCMN PL, R2, $6, $1 + CCMNW AL, R3, $20, $11 + CCMNW EQ, R4, R5, $6 + CCMP LT, R6, R7, $7 + CCMP LE, R8, $19, $3 + CCMPW HS, R9, R10, $0 + CCMPW VS, R11, $15, $7 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "conditionalCompareComplete": {Name: "conditionalCompareComplete", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"add i64", "add i32", "sub i64", "sub i32", "select i1 true"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 conditional compare lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-conditional-compare.ll", "arm64-conditional-compare.o", ll) +} + +func TestTranslateARM64ConditionalCompareRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "CCMN BAD, R0, R1, $0", + "CCMN AL, RSP, R1, $0", + "CCMN AL, R0, (R1), $0", + "CCMN.P AL, R0, R1, $0", + "CCMPW AL, R0, R1", + } { + source := "TEXT bad(SB),$0-0\n\tCMP R0, R0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 conditional-compare optab", instruction) + } + } +} diff --git a/arm64_lower_count_bits.go b/arm64_lower_count_bits.go new file mode 100644 index 00000000..52fc80ac --- /dev/null +++ b/arm64_lower_count_bits.go @@ -0,0 +1,60 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64VectorCountBitsOps = map[Op]struct{}{ + "VCNT": {}, + "VCLS": {}, + "VCLZ": {}, +} + +func (c *arm64Ctx) lowerARM64VectorCountBits(op Op, ins Instr) (ok bool, terminated bool, err error) { + if _, ok := arm64VectorCountBitsOps[op]; !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects two same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + sourceArrangement, sourceOK := parseARM64VectorArrangement(ins.Args[0].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[1].Reg) + validArrangement := sourceArrangement.elementBits == 8 && (sourceArrangement.lanes == 8 || sourceArrangement.lanes == 16) + if op != "VCNT" { + validArrangement = (sourceArrangement.elementBits == 8 || sourceArrangement.elementBits == 16 || sourceArrangement.elementBits == 32) && + (sourceArrangement.lanes*sourceArrangement.elementBits == 64 || sourceArrangement.lanes*sourceArrangement.elementBits == 128) + } + if !sourceOK || !destinationOK || sourceArrangement != destinationArrangement || !validArrangement { + return true, false, fmt.Errorf("arm64 %s requires matching Go assembler vector arrangements: %q", op, ins.Raw) + } + source, err := c.loadARM64VectorInteger(ins.Args[0].Reg, sourceArrangement) + if err != nil { + return true, false, err + } + if op == "VCNT" { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <%d x i8> @llvm.ctpop.v%di8(<%d x i8> %s)\n", result, sourceArrangement.lanes, sourceArrangement.lanes, sourceArrangement.lanes, source) + return true, false, c.storeARM64VectorInteger(ins.Args[1].Reg, destinationArrangement, "%"+result) + } + + vectorType := fmt.Sprintf("<%d x i%d>", sourceArrangement.lanes, sourceArrangement.elementBits) + countSource := source + if op == "VCLS" { + sign := c.newTmp() + normalized := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ashr %s %s, %s\n", sign, vectorType, source, arm64VectorIntegerSplat(sourceArrangement, int64(sourceArrangement.elementBits-1))) + fmt.Fprintf(c.b, " %%%s = xor %s %s, %%%s\n", normalized, vectorType, source, sign) + countSource = "%" + normalized + } + count := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.ctlz.v%di%d(%s %s, i1 false)\n", + count, vectorType, sourceArrangement.lanes, sourceArrangement.elementBits, vectorType, countSource) + result := "%" + count + if op == "VCLS" { + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s %%%s, %s\n", adjusted, vectorType, count, arm64VectorIntegerSplat(sourceArrangement, 1)) + result = "%" + adjusted + } + return true, false, c.storeARM64VectorInteger(ins.Args[1].Reg, destinationArrangement, result) +} diff --git a/arm64_lower_count_bits_test.go b/arm64_lower_count_bits_test.go new file mode 100644 index 00000000..c6af336d --- /dev/null +++ b/arm64_lower_count_bits_test.go @@ -0,0 +1,72 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorCountBitsCompleteGoAssemblerForms(t *testing.T) { + source := `TEXT ·vectorCountBitsForms(SB), $0-0 + VCNT V0.B8, V1.B8 + VCNT V0.B16, V1.B16 + RET +` + requireARM64GoAssemblerResult(t, source, true) + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorCountBitsForms": {Name: "vectorCountBitsForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-count-bits.ll", "arm64-vector-count-bits.o", ll) + } +} + +func TestTranslateARM64VectorCountBitsRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VCNT V0.H4, V1.H4", + "VCNT V0.B8, V1.B16", + "VCNT V0.B16, V1.B8", + "VCNT V0.B8, V1.B8, V2.B8", + "VCNT.P V0.B16, V1.B16", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT ·badVectorCountBits(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badVectorCountBits": {Name: "badVectorCountBits", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VCNT forms", instruction) + } + }) + } +} diff --git a/arm64_lower_count_leading.go b/arm64_lower_count_leading.go new file mode 100644 index 00000000..baf34f81 --- /dev/null +++ b/arm64_lower_count_leading.go @@ -0,0 +1,69 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64CountLeading(op Op, ins Instr) (ok bool, terminated bool, err error) { + signed := op == "CLS" || op == "CLSW" + word := op == "CLZW" || op == "CLSW" + if !signed && !word && op != "CLZ" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg || + !isARM64GeneralOrZeroReg(ins.Args[0].Reg) || !isARM64GeneralOrZeroReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm64 %s expects general register, general register: %q", op, ins.Raw) + } + + if word { + source, err := c.eval32(ins.Args[0]) + if err != nil { + return true, false, err + } + value := source + if signed { + sign := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ashr i32 %s, 31\n", sign, source) + normalized := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i32 %s, %%%s\n", normalized, source, sign) + value = "%" + normalized + } + count := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.ctlz.i32(i32 %s, i1 false)\n", count, value) + result := "%" + count + if signed { + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 %s, 1\n", adjusted, result) + result = "%" + adjusted + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, result) + return true, false, c.storeReg(ins.Args[1].Reg, "%"+wide) + } + + source, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + value := source + if signed { + sign := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ashr i64 %s, 63\n", sign, source) + normalized := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor i64 %s, %%%s\n", normalized, source, sign) + value = "%" + normalized + } + count := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.ctlz.i64(i64 %s, i1 false)\n", count, value) + result := "%" + count + if signed { + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i64 %s, 1\n", adjusted, result) + result = "%" + adjusted + } + return true, false, c.storeReg(ins.Args[1].Reg, result) +} diff --git a/arm64_lower_count_leading_test.go b/arm64_lower_count_leading_test.go new file mode 100644 index 00000000..7196958a --- /dev/null +++ b/arm64_lower_count_leading_test.go @@ -0,0 +1,149 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64CountLeadingCompleteGo127Forms(t *testing.T) { + const source = `TEXT countLeadingForms(SB), $0-0 + CLZ R0, R1 + CLZW R2, R3 + CLS R4, R5 + CLSW R6, R7 + CLZ ZR, ZR + CLZW ZR, ZR + CLS ZR, ZR + CLSW ZR, ZR + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "countLeadingForms": {Name: "countLeadingForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"@llvm.ctlz.i64", "@llvm.ctlz.i32", "ashr i64", "ashr i32", "sub i64", "sub i32"} { + if !strings.Contains(ir, want) { + t.Fatalf("count-leading lowering omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-count-leading.ll", "arm64-count-leading.o", ir) + }) + } +} + +func TestTranslateARM64CountLeadingRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, instruction := range []string{ + "CLZ R0", + "CLZW $1, R0", + "CLS R0, R1, R2", + "CLSW R0, (R1)", + "CLZ RSP, R0", + "CLS V0, R0", + "CLZW.P R0, R1", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badCountLeading(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badCountLeading": {Name: "badCountLeading", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's count-leading optab", instruction) + } + }) + } +} + +func TestARM64CountLeadingRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT countLeadingRuntime(SB), $0-16 + MOVD value+0(FP), R0 + MOVD out+8(FP), R1 + CLZ R0, R2 + MOVD R2, 0(R1) + CLZW R0, R2 + MOVD R2, 8(R1) + CLS R0, R2 + MOVD R2, 16(R1) + CLSW R0, R2 + MOVD R2, 24(R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "countLeadingRuntime": { + Name: "countLeadingRuntime", Args: []LLVMType{I64, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void countLeadingRuntime(uint64_t, uint64_t *); +static uint64_t clz64(uint64_t value) { return value ? __builtin_clzll(value) : 64; } +static uint64_t clz32(uint32_t value) { return value ? __builtin_clz(value) : 32; } +int main(void) { + const uint64_t value = UINT64_C(0xf123456789abcdef); + const uint32_t word = (uint32_t)value; + uint64_t got[4] = {0, 0, 0, 0}; + countLeadingRuntime(value, got); + const uint64_t sign64 = (uint64_t)((int64_t)value >> 63); + const uint32_t sign32 = (uint32_t)((int32_t)word >> 31); + const uint64_t want[4] = {clz64(value), clz32(word), clz64(value ^ sign64) - 1, clz32(word ^ sign32) - 1}; + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_count_leading", triple, ir, mainC, nil) +} diff --git a/arm64_lower_crc_complete_test.go b/arm64_lower_crc_complete_test.go new file mode 100644 index 00000000..b97da8fe --- /dev/null +++ b/arm64_lower_crc_complete_test.go @@ -0,0 +1,77 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64CRCCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT crcComplete(SB),$0-0\n") + for _, op := range []string{"CRC32B", "CRC32H", "CRC32W", "CRC32X", "CRC32CB", "CRC32CH", "CRC32CW", "CRC32CX"} { + source.WriteString("\t" + op + " R1, R2\n") + source.WriteString("\t" + op + " R3, R4, R5\n") + source.WriteString("\t" + op + " ZR, R6, R7\n") + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64CRCCompleteFormats(t *testing.T) { + source := arm64CRCCompleteForms() + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"crcComplete": {Name: "crcComplete", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{ + "llvm.aarch64.crc32b", "llvm.aarch64.crc32h", "llvm.aarch64.crc32w", "llvm.aarch64.crc32x", + "llvm.aarch64.crc32cb", "llvm.aarch64.crc32ch", "llvm.aarch64.crc32cw", "llvm.aarch64.crc32cx", + } { + if !strings.Contains(ll, intrinsic) { + t.Fatalf("ARM64 CRC lowering omitted %q:\n%s", intrinsic, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-crc-complete.ll", "arm64-crc-complete.o", ll) +} + +func TestTranslateARM64CRCRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "CRC32B R0", + "CRC32H R0, R1, R2, R3", + "CRC32W (R0), R1", + "CRC32X R0, RSP, R2", + "CRC32CB R0<<1, R1, R2", + "CRC32CH R0, R1, RSP", + "CRC32CW.P R0, R1", + "CRC32CX $0, R1, R2", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 CRC optab", instruction) + } + } +} diff --git a/arm64_lower_cterm.go b/arm64_lower_cterm.go new file mode 100644 index 00000000..a24e74f6 --- /dev/null +++ b/arm64_lower_cterm.go @@ -0,0 +1,44 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64CTERMOps = map[Op]bool{ + "CTERMEQ": true, + "CTERMEQW": true, + "CTERMNE": true, + "CTERMNEW": true, +} + +func (c *arm64Ctx) lowerARM64CTERM(op Op, ins Instr) (ok bool, terminated bool, err error) { + if !arm64CTERMOps[op] { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg || + !isARM64GeneralOrZeroReg(ins.Args[0].Reg) || !isARM64GeneralOrZeroReg(ins.Args[1].Reg) || ins.Args[0].Reg == SP || ins.Args[0].Reg == Reg("RSP") || ins.Args[1].Reg == SP || ins.Args[1].Reg == Reg("RSP") { + return true, false, fmt.Errorf("arm64 %s requires two R0..R30 or ZR operands: %q", op, ins.Raw) + } + first, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + second, err := c.loadReg(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + typeName := "i64" + if strings.HasSuffix(string(op), "W") { + typeName = "i32" + first32 := c.newTmp() + second32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", first32, first) + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", second32, second) + first = "%" + first32 + second = "%" + second32 + } + mnemonic := strings.ToLower(strings.TrimSuffix(string(op), "W")) + fmt.Fprintf(c.b, " call void asm sideeffect %q, \"r,r\"(%s %s, %s %s)\n", mnemonic+" $0, $1", typeName, first, typeName, second) + return true, false, nil +} diff --git a/arm64_lower_cterm_test.go b/arm64_lower_cterm_test.go new file mode 100644 index 00000000..18005a27 --- /dev/null +++ b/arm64_lower_cterm_test.go @@ -0,0 +1,72 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64CTERMCompleteGo127Family(t *testing.T) { + source := `TEXT ctermforms(SB),$0-0 + CTERMEQ R3, R4 + CTERMEQ ZR, R25 + CTERMEQW R5, ZR + CTERMNE R6, R7 + CTERMNE ZR, ZR + CTERMNEW R8, R9 + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"ctermforms": {Name: "ctermforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + `asm sideeffect "ctermeq $0, $1"`, + `asm sideeffect "ctermne $0, $1"`, + "trunc i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s CTERM lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-cterm.ll", "arm64-cterm.o", ll) + }) + } +} + +func TestTranslateARM64CTERMRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "CTERMEQ R3", + "CTERMEQ R3, R4, R5", + "CTERMEQ RSP, R4", + "CTERMEQ R3, RSP", + "CTERMEQ $1, R4", + "CTERMEQ R3, 8(R4)", + "CTERMEQ.Z R3, R4", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badcterm(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badcterm": {Name: "badcterm", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's CTERM forms", instruction) + } + }) + } +} diff --git a/arm64_lower_data.go b/arm64_lower_data.go index ee8491ec..66b03a4a 100644 --- a/arm64_lower_data.go +++ b/arm64_lower_data.go @@ -6,37 +6,15 @@ import ( ) func (c *arm64Ctx) lowerData(op Op, postInc bool, ins Instr) (ok bool, terminated bool, err error) { + if ok, terminated, err := c.lowerARM64ScalarExtend(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64IntegerPair(op, ins); ok { + return ok, terminated, err + } switch op { - case "MOVKW": - if len(ins.Args) != 2 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("arm64 MOVKW expects $imm16[<<16], dstReg: %q", ins.Raw) - } - if ins.Args[0].Imm < 0 || uint64(ins.Args[0].Imm) > uint64(^uint32(0)) { - return true, false, fmt.Errorf("arm64 MOVKW immediate is outside 32 bits: %q", ins.Raw) - } - imm := uint32(ins.Args[0].Imm) - var keepMask uint32 - switch { - case imm <= 0xffff: - keepMask = 0xffff0000 - case imm&0xffff == 0: - keepMask = 0x0000ffff - default: - return true, false, fmt.Errorf("arm64 MOVKW immediate is not an imm16 or imm16<<16: %q", ins.Raw) - } - old, err := c.loadReg(ins.Args[1].Reg) - if err != nil { - return true, false, err - } - old32 := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", old32, old) - kept := c.newTmp() - fmt.Fprintf(c.b, " %%%s = and i32 %%%s, %d\n", kept, old32, keepMask) - merged := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i32 %%%s, %d\n", merged, kept, imm) - wide := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, merged) - return true, false, c.storeReg(ins.Args[1].Reg, "%"+wide) + case "MOVK", "MOVKW": + return true, false, c.lowerARM64MoveKeep(op, ins) case "MOVD": if len(ins.Args) != 2 { @@ -70,6 +48,13 @@ func (c *arm64Ctx) lowerData(op Op, postInc bool, ins Instr) (ok bool, terminate signed := op == "MOVB" || op == "MOVH" || op == "MOVW" return true, false, c.lowerNarrowMove(op, ins, bits, signed, postInc) + case "MOVBW", "MOVHW": + bits := 8 + if op == "MOVHW" { + bits = 16 + } + return true, false, c.lowerSignedNarrowLoadToWord(op, ins, bits, postInc) + case "LDP": if len(ins.Args) != 2 || ins.Args[1].Kind != OpRegList || len(ins.Args[1].RegList) != 2 { return true, false, fmt.Errorf("arm64 LDP expects src, (reg,reg): %q", ins.Raw) @@ -241,6 +226,75 @@ func (c *arm64Ctx) lowerData(op Op, postInc bool, ins Instr) (ok bool, terminate return false, false, nil } +func (c *arm64Ctx) lowerARM64MoveKeep(op Op, ins Instr) error { + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || + ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || + ins.Args[1].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[1].Reg) { + return fmt.Errorf("arm64 %s expects $imm16[<<16...], dstReg: %q", op, ins.Raw) + } + if ins.Args[0].Imm == 0 { + return fmt.Errorf("arm64 %s cannot encode a zero immediate: %q", op, ins.Raw) + } + value := uint64(ins.Args[0].Imm) + width := 64 + if op == "MOVKW" { + if ins.Args[0].Imm < 0 || value > uint64(^uint32(0)) { + return fmt.Errorf("arm64 MOVKW immediate is outside 32 bits: %q", ins.Raw) + } + width = 32 + } + shift := -1 + for candidate := 0; candidate < width; candidate += 16 { + fieldMask := uint64(0xffff) << candidate + if value & ^fieldMask == 0 { + shift = candidate + break + } + } + if shift < 0 { + return fmt.Errorf("arm64 %s immediate is not a shifted unsigned 16-bit value: %q", op, ins.Raw) + } + old, err := c.loadReg(ins.Args[1].Reg) + if err != nil { + return err + } + if width == 64 { + keepMask := ^(uint64(0xffff) << shift) + kept := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %d\n", kept, old, keepMask) + merged := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %d\n", merged, kept, value) + return c.storeReg(ins.Args[1].Reg, "%"+merged) + } + old32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", old32, old) + keepMask := ^(uint32(0xffff) << shift) + kept := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i32 %%%s, %d\n", kept, old32, keepMask) + merged := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i32 %%%s, %d\n", merged, kept, uint32(value)) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, merged) + return c.storeReg(ins.Args[1].Reg, "%"+wide) +} + +func (c *arm64Ctx) lowerSignedNarrowLoadToWord(op Op, ins Instr, bits int, postInc bool) error { + if len(ins.Args) != 2 || ins.Args[0].Kind != OpMem || ins.Args[1].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[1].Reg) { + return fmt.Errorf("arm64 %s expects memory, C_ZREG: %q", op, ins.Raw) + } + value, err := c.loadMem(ins.Args[0].Mem, bits, postInc) + if err != nil { + return err + } + narrow := c.newTmp() + signed := c.newTmp() + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrow, value, bits) + fmt.Fprintf(c.b, " %%%s = sext i%d %%%s to i32\n", signed, bits, narrow) + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, signed) + return c.storeReg(ins.Args[1].Reg, "%"+wide) +} + func (c *arm64Ctx) lowerNarrowMove(op Op, ins Instr, bits int, signed, postInc bool) error { if len(ins.Args) != 2 { return fmt.Errorf("arm64 %s expects 2 operands: %q", op, ins.Raw) diff --git a/arm64_lower_divide_remainder.go b/arm64_lower_divide_remainder.go new file mode 100644 index 00000000..fd17feb3 --- /dev/null +++ b/arm64_lower_divide_remainder.go @@ -0,0 +1,104 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64DivideRemainder(op Op, ins Instr) (ok bool, terminated bool, err error) { + var llvmOp string + var word, signed, remainder bool + switch op { + case "SDIV": + llvmOp, signed = "sdiv", true + case "SDIVW": + llvmOp, signed, word = "sdiv", true, true + case "UDIV": + llvmOp = "udiv" + case "UDIVW": + llvmOp, word = "udiv", true + case "REM": + llvmOp, signed, remainder = "srem", true, true + case "REMW": + llvmOp, signed, remainder, word = "srem", true, true, true + case "UREM": + llvmOp, remainder = "urem", true + case "UREMW": + llvmOp, remainder, word = "urem", true, true + default: + return false, false, nil + } + + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects 2 or 3 operands: %q", op, ins.Raw) + } + for _, operand := range ins.Args { + if operand.Kind != OpReg || !isARM64GeneralOrZeroReg(operand.Reg) { + return true, false, fmt.Errorf("arm64 %s expects only general registers: %q", op, ins.Raw) + } + } + + divisor, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + dividendOperand := ins.Args[1] + destination := ins.Args[1].Reg + if len(ins.Args) == 3 { + destination = ins.Args[2].Reg + } + dividend, err := c.loadReg(dividendOperand.Reg) + if err != nil { + return true, false, err + } + + typeName := "i64" + minimum := "-9223372036854775808" + if word { + typeName = "i32" + minimum = "-2147483648" + truncatedDivisor := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", truncatedDivisor, divisor) + divisor = "%" + truncatedDivisor + truncatedDividend := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", truncatedDividend, dividend) + dividend = "%" + truncatedDividend + } + + isZero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, 0\n", isZero, typeName, divisor) + unsafeDivisor := "%" + isZero + if signed { + isMinimum := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, %s\n", isMinimum, typeName, dividend, minimum) + isMinusOne := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, -1\n", isMinusOne, typeName, divisor) + isOverflow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", isOverflow, isMinimum, isMinusOne) + unsafe := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", unsafe, isZero, isOverflow) + unsafeDivisor = "%" + unsafe + } + + safeDivisor := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, %s 1, %s %s\n", safeDivisor, unsafeDivisor, typeName, typeName, divisor) + computed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %%%s\n", computed, llvmOp, typeName, dividend, safeDivisor) + result := "%" + computed + selected := c.newTmp() + if remainder { + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %s, %s %s\n", selected, isZero, typeName, dividend, typeName, result) + } else { + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s 0, %s %s\n", selected, isZero, typeName, typeName, result) + } + result = "%" + selected + if word { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, result) + result = "%" + wide + } + return true, false, c.storeReg(destination, result) +} diff --git a/arm64_lower_divide_remainder_test.go b/arm64_lower_divide_remainder_test.go new file mode 100644 index 00000000..9ae0cc16 --- /dev/null +++ b/arm64_lower_divide_remainder_test.go @@ -0,0 +1,175 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64DivideRemainderForms = ` +TEXT divideremainderforms(SB),$0-0 + SDIV R0, R1 + SDIV R2, R3, R4 + SDIVW R5, R6 + SDIVW R7, R8, R9 + UDIV R10, R11 + UDIV R12, R13, R14 + UDIVW R15, R16 + UDIVW R17, R19, R20 + REM R21, R22 + REM R23, R24, R25 + REMW R26, R27 + REMW R10, R11, R12 + UREM R0, R1 + UREM R2, R3, R4 + UREMW R5, R6 + UREMW R7, R8, ZR + RET +` + +func TestTranslateARM64DivideRemainderCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64DivideRemainderForms, true) + file, err := Parse(ArchARM64, arm64DivideRemainderForms) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"divideremainderforms": {Name: "divideremainderforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sdiv i64", "sdiv i32", "udiv i64", "udiv i32", "srem i64", "srem i32", "urem i64", "urem i32"} { + if !strings.Contains(ir, want) { + t.Fatalf("divide/remainder family for %s omitted %q:\n%s", triple, want, ir) + } + } + compileLLVMToObject(t, llc, triple, "arm64-divide-remainder.ll", "arm64-divide-remainder.o", ir) + }) + } +} + +func TestTranslateARM64DivideRemainderRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "SDIV R0", + "SDIV R0, R1, R2, R3", + "SDIV $2, R0", + "UDIV (R0), R1", + "REM R0, RSP", + "UREMW.P R0, R1", + } { + source := "TEXT baddivideremainder(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", + Sigs: map[string]FuncSig{"baddivideremainder": {Name: "baddivideremainder", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's divide/remainder optab", instruction) + } + } +} + +func TestARM64DivideRemainderRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT divideremainder(SB),$0-16 + MOVD input+0(FP), R10 + MOVD output+8(FP), R11 + MOVD 0(R10), R0 + MOVD 8(R10), R1 + MOVD 16(R10), R2 + MOVD 24(R10), R3 + MOVD 32(R10), R4 + MOVD 40(R10), R5 + MOVD 48(R10), R23 + SDIV R1, R0, R6 + SDIVW R1, R0, R7 + UDIV R3, R2, R8 + UDIVW R3, R2, R9 + REM R1, R0, R12 + REMW R1, R0, R13 + UREM R3, R2, R14 + UREMW R3, R2, R15 + SDIV ZR, R0, R16 + UDIV ZR, R2, R17 + REM ZR, R0, R19 + UREM ZR, R2, R20 + SDIV R5, R4, R21 + SDIVW R5, R23, R22 + MOVD R6, 0(R11) + MOVD R7, 8(R11) + MOVD R8, 16(R11) + MOVD R9, 24(R11) + MOVD R12, 32(R11) + MOVD R13, 40(R11) + MOVD R14, 48(R11) + MOVD R15, 56(R11) + MOVD R16, 64(R11) + MOVD R17, 72(R11) + MOVD R19, 80(R11) + MOVD R20, 88(R11) + MOVD R21, 96(R11) + MOVD R22, 104(R11) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"divideremainder": { + Name: "divideremainder", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void divideremainder(const uint64_t *, uint64_t *); +int main(void) { + const uint64_t input[7] = { + (uint64_t)-9, 2, 9, 2, + UINT64_C(0x8000000000000000), UINT64_MAX, UINT64_C(0x80000000) + }; + const uint64_t want[14] = { + (uint64_t)-4, UINT32_C(0xfffffffc), 4, 4, + UINT64_MAX, UINT32_MAX, 1, 1, + 0, 0, (uint64_t)-9, 9, + UINT64_C(0x8000000000000000), UINT32_C(0x80000000) + }; + uint64_t got[14] = {0}; + divideremainder(input, got); + for (int i = 0; i < 14; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_divide_remainder", triple, ir, mainC, nil) +} diff --git a/arm64_lower_duplicate.go b/arm64_lower_duplicate.go new file mode 100644 index 00000000..a627f5e2 --- /dev/null +++ b/arm64_lower_duplicate.go @@ -0,0 +1,105 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerARM64VectorDuplicate implements all three AVDUP rows in Go's ARM64 +// optab: vector lane to arranged vector, vector lane to scalar V register, and +// integer register to arranged vector. +func (c *arm64Ctx) lowerARM64VectorDuplicate(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VDUP" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != "VDUP" || len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 VDUP expects a vector lane or R/ZR source and a vector destination, with no suffix: %q", ins.Raw) + } + + src, dst := ins.Args[0].Reg, ins.Args[1].Reg + dstArrangement, arrangedDst := parseARM64VectorArrangement(dst) + if arrangedDst && !arm64VDUPArrangementAllowed(dstArrangement) { + return true, false, fmt.Errorf("arm64 VDUP destination arrangement is outside Go's optab: %q", ins.Raw) + } + + _, lane, laneSource := arm64ParseVRegLane(src) + if laneSource { + if arrangedDst { + // Go's case 79 encoder intentionally derives the source element width + // from the destination arrangement, not from the source's spelling. + // Match that behavior even for accepted mixed-suffix forms. + if lane >= 128/dstArrangement.elementBits { + return true, false, fmt.Errorf("arm64 VDUP source lane is out of range for destination arrangement: %q", ins.Raw) + } + element, err := c.arm64VDUPExtractLane(src, dstArrangement.elementBits, lane) + if err != nil { + return true, false, err + } + vector := c.arm64VDUPSplat(dstArrangement, element) + return true, false, c.storeARM64VectorInteger(dst, dstArrangement, vector) + } + + if strings.Contains(string(dst), ".") { + return true, false, fmt.Errorf("arm64 VDUP destination arrangement is outside Go's optab: %q", ins.Raw) + } + if _, valid := arm64ParseVReg(dst); !valid { + return true, false, fmt.Errorf("arm64 VDUP lane destination must be a bare V register: %q", ins.Raw) + } + kind, _, _ := arm64ParseVRegLane(src) + bits := map[byte]int{'B': 8, 'H': 16, 'S': 32, 'D': 64}[kind] + element, err := c.arm64VDUPExtractLane(src, bits, lane) + if err != nil { + return true, false, err + } + physicalLanes := 128 / bits + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> zeroinitializer, i%d %s, i32 0\n", inserted, physicalLanes, bits, bits, element) + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", bytes, physicalLanes, bits, inserted) + return true, false, c.storeVReg(dst, "%"+bytes) + } + + if !arrangedDst || !isARM64GeneralOrZeroReg(src) { + return true, false, fmt.Errorf("arm64 VDUP expects a vector lane or R/ZR source and a valid arranged vector destination: %q", ins.Raw) + } + value, err := c.loadReg(src) + if err != nil { + return true, false, err + } + if dstArrangement.elementBits < 64 { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", truncated, value, dstArrangement.elementBits) + value = "%" + truncated + } + vector := c.arm64VDUPSplat(dstArrangement, value) + return true, false, c.storeARM64VectorInteger(dst, dstArrangement, vector) +} + +func arm64VDUPArrangementAllowed(arrangement arm64VectorArrangement) bool { + return (arrangement.elementBits == 8 && (arrangement.lanes == 8 || arrangement.lanes == 16)) || + (arrangement.elementBits == 16 && (arrangement.lanes == 4 || arrangement.lanes == 8)) || + (arrangement.elementBits == 32 && (arrangement.lanes == 2 || arrangement.lanes == 4)) || + (arrangement.elementBits == 64 && arrangement.lanes == 2) +} + +func (c *arm64Ctx) arm64VDUPExtractLane(src Reg, bits, lane int) (string, error) { + bytes, err := c.loadVReg(src) + if err != nil { + return "", err + } + lanes := 128 / bits + typed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x i%d>\n", typed, bytes, lanes, bits) + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %%%s, i32 %d\n", element, lanes, bits, typed, lane) + return "%" + element, nil +} + +func (c *arm64Ctx) arm64VDUPSplat(arrangement arm64VectorArrangement, element string) string { + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> poison, i%d %s, i32 0\n", seed, arrangement.lanes, arrangement.elementBits, arrangement.elementBits, element) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %%%s, <%d x i%d> poison, <%d x i32> zeroinitializer\n", + result, arrangement.lanes, arrangement.elementBits, seed, arrangement.lanes, arrangement.elementBits, arrangement.lanes) + return "%" + result +} diff --git a/arm64_lower_duplicate_test.go b/arm64_lower_duplicate_test.go new file mode 100644 index 00000000..17465048 --- /dev/null +++ b/arm64_lower_duplicate_test.go @@ -0,0 +1,167 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64VectorDuplicateForms = ` +TEXT vectorduplicateforms(SB),$0-0 + VDUP V0.B[15], V1.B8 + VDUP V0.B[15], V2.B16 + VDUP V0.H[7], V3.H4 + VDUP V0.H[7], V4.H8 + VDUP V0.S[3], V5.S2 + VDUP V0.S[3], V6.S4 + VDUP V0.D[1], V7.D2 + VDUP V0.B[15], V8 + VDUP V0.H[7], V9 + VDUP V0.S[3], V10 + VDUP V0.D[1], V11 + VDUP R1, V12.B8 + VDUP R2, V13.B16 + VDUP R3, V14.H4 + VDUP R4, V15.H8 + VDUP R5, V16.S2 + VDUP R6, V17.S4 + VDUP R7, V18.D2 + // Go's case-79 encoder takes the source width from the arranged + // destination, so these mixed source suffixes are intentionally accepted. + VDUP V0.B[0], V19.D2 + VDUP V0.D[1], V20.B16 + VDUP ZR, V21.S4 + RET +` + +func TestTranslateARM64VectorDuplicateCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64VectorDuplicateForms, true) + file, err := Parse(ArchARM64, arm64VectorDuplicateForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorduplicateforms": {Name: "vectorduplicateforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"extractelement", "shufflevector", "insertelement"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 VDUP lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-duplicate.ll", "arm64-vector-duplicate.o", ll) + }) + } +} + +func TestTranslateARM64VectorDuplicateRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VDUP V0.B[16], V1.B16", + "VDUP V0.B[0], V1.D1", + "VDUP V0.S4, V1.S4", + "VDUP R1, V2", + "VDUP R1, V2.D1", + "VDUP R1, V2.S4, V3.S4", + "VDUP.P R1, V2.S4", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badvectorduplicate(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorduplicate": {Name: "badvectorduplicate", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VDUP table", instruction) + } + }) + } +} + +func TestARM64VectorDuplicateRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectorduplicate(SB),$0-8 + MOVD out+0(FP), R0 + VMOVQ $0x0706050403020100, $0x0f0e0d0c0b0a0908, V1 + VDUP V1.B[13], V2.B16 + VMOV V2.D[0], R1 + VMOV V2.D[1], R2 + MOVD R1, 0(R0) + MOVD R2, 8(R0) + VDUP V1.S[2], V3 + VMOV V3.D[0], R3 + VMOV V3.D[1], R4 + MOVD R3, 16(R0) + MOVD R4, 24(R0) + MOVD $0x123456789abcdef0, R5 + VDUP R5, V4.H4 + VMOV V4.D[0], R6 + VMOV V4.D[1], R7 + MOVD R6, 32(R0) + MOVD R7, 40(R0) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorduplicate": { + Name: "vectorduplicate", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void vectorduplicate(uint64_t *); +int main(void) { + uint64_t got[6] = {0}; + vectorduplicate(got); + if (got[0] != UINT64_C(0x0d0d0d0d0d0d0d0d) || got[1] != UINT64_C(0x0d0d0d0d0d0d0d0d)) return 1; + if (got[2] != UINT64_C(0x000000000b0a0908) || got[3] != 0) return 2; + if (got[4] != UINT64_C(0xdef0def0def0def0) || got[5] != 0) return 3; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_duplicate", triple, ll, mainC, nil) +} diff --git a/arm64_lower_exception.go b/arm64_lower_exception.go new file mode 100644 index 00000000..e662e86a --- /dev/null +++ b/arm64_lower_exception.go @@ -0,0 +1,35 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64Exception(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "BRK": + if strings.ToUpper(string(ins.Op)) != "BRK" || len(ins.Args) > 1 { + return true, false, fmt.Errorf("arm64 BRK accepts no operand or one constant operand, with no suffix: %q", ins.Raw) + } + var immediate uint64 + if len(ins.Args) == 1 { + if ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 BRK operand must be a constant: %q", ins.Raw) + } + immediate = uint64(ins.Args[0].Imm) & 0xffff + } + // A debugger or signal handler may resume after BRK, so keep the + // following source instructions reachable. + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q()\n", fmt.Sprintf("brk #%d", immediate), "~{memory}") + return true, false, nil + case "UNDEF": + if strings.ToUpper(string(ins.Op)) != "UNDEF" || len(ins.Args) != 0 { + return true, false, fmt.Errorf("arm64 UNDEF takes no operands or suffix: %q", ins.Raw) + } + c.b.WriteString(" call void asm sideeffect \"udf #0\", \"~{memory}\"()\n") + c.b.WriteString(" unreachable\n") + return true, true, nil + default: + return false, false, nil + } +} diff --git a/arm64_lower_exception_test.go b/arm64_lower_exception_test.go new file mode 100644 index 00000000..1210a6e6 --- /dev/null +++ b/arm64_lower_exception_test.go @@ -0,0 +1,120 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +const arm64ExceptionForms = ` +TEXT exceptionforms(SB),$0-0 + BRK + BRK $0 + BRK $65535 + BRK $65536 + BRK $-1 + RET + +TEXT undefinedform(SB),$0-0 + UNDEF +` + +func TestTranslateARM64ExceptionCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64ExceptionForms, true) + + for _, triple := range []string{ + "arm64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, arm64ExceptionForms) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "exceptionforms": {Name: "exceptionforms", Ret: Void}, + "undefinedform": {Name: "undefinedform", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if got := strings.Count(ll, `asm sideeffect "brk #0"`); got != 3 { + t.Fatalf("ARM64 BRK zero-immediate count = %d, want 3:\n%s", got, ll) + } + if got := strings.Count(ll, `asm sideeffect "brk #65535"`); got != 2 { + t.Fatalf("ARM64 BRK max-immediate count = %d, want 2:\n%s", got, ll) + } + if !strings.Contains(ll, `asm sideeffect "udf #0"`) || !strings.Contains(ll, "unreachable") { + t.Fatalf("ARM64 UNDEF did not lower to a terminating undefined instruction:\n%s", ll) + } + // BRK is resumable under a debugger, so exceptionforms must retain RET. + start := strings.Index(ll, "define void @exceptionforms()") + end := strings.Index(ll[start:], "define void @undefinedform()") + if start < 0 || end < 0 || !strings.Contains(ll[start:start+end], "ret void") { + t.Fatalf("ARM64 BRK incorrectly terminated the resumable function:\n%s", ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-exception.ll", "arm64-exception.o", ll) + }) + } +} + +func TestTranslateARM64ExceptionRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "BRK R0", + "BRK $1, $2", + "BRK.P $1", + "UNDEF $0", + "UNDEF.P", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's BRK/UNDEF forms", instruction) + } + } +} + +func TestTranslateARM64RejectsUnexpandedExceptionMacros(t *testing.T) { + for _, instruction := range []string{ + "BREAK", + "#UNDEF", + "SAVE_R19_TO_R28(32)", + "RESTORE_R19_TO_R28(32)", + "SAVE_F8_TO_F15(112)", + "RESTORE_F8_TO_F15(112)", + "P256ADDINLINE", + "P256MULBY2INLINE", + "STY", + "MOV", + } { + file, err := Parse(ArchARM64, "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate silently accepted unexpanded macro %q", instruction) + } + } +} diff --git a/arm64_lower_exclusive_complete_test.go b/arm64_lower_exclusive_complete_test.go new file mode 100644 index 00000000..fcc069b0 --- /dev/null +++ b/arm64_lower_exclusive_complete_test.go @@ -0,0 +1,76 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64ExclusiveCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT exclusiveComplete(SB),$0-0\n") + for _, prefix := range []string{"LDXR", "LDAXR"} { + for _, width := range []string{"B", "H", "W", ""} { + source.WriteString("\t" + prefix + width + " (R6), R7\n") + } + } + for _, prefix := range []string{"STXR", "STLXR"} { + for _, width := range []string{"B", "H", "W", ""} { + source.WriteString("\t" + prefix + width + " R5, (R6), R7\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64ExclusiveCompleteFormats(t *testing.T) { + source := arm64ExclusiveCompleteForms() + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "exclusiveComplete": {Name: "exclusiveComplete", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "load atomic i8", "load atomic i16", "load atomic i32", "load atomic i64", + " monotonic", " acquire", "cmpxchg ptr", " release monotonic", + "store i1 true, ptr %exclusive_valid", "store i1 false, ptr %exclusive_valid", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 exclusive lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-exclusive-complete.ll", "arm64-exclusive-complete.o", ll) +} + +func TestTranslateARM64ExclusiveRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"LDXR 8(R1), R2", "STXRH R0, (R1)", "LDXRQ (R1), R2"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 exclusive optab", instruction) + } + } +} diff --git a/arm64_lower_extend.go b/arm64_lower_extend.go new file mode 100644 index 00000000..76f25b2b --- /dev/null +++ b/arm64_lower_extend.go @@ -0,0 +1,61 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64ScalarExtendSpec struct { + sourceBits int + signed bool + wordDestination bool +} + +var arm64ScalarExtendSpecs = map[Op]arm64ScalarExtendSpec{ + "SXTB": {sourceBits: 8, signed: true}, + "SXTBW": {sourceBits: 8, signed: true, wordDestination: true}, + "SXTH": {sourceBits: 16, signed: true}, + "SXTHW": {sourceBits: 16, signed: true, wordDestination: true}, + "SXTW": {sourceBits: 32, signed: true}, + "UXTB": {sourceBits: 8}, + "UXTBW": {sourceBits: 8, wordDestination: true}, + "UXTH": {sourceBits: 16}, + "UXTHW": {sourceBits: 16, wordDestination: true}, + "UXTW": {sourceBits: 32}, +} + +func (c *arm64Ctx) lowerARM64ScalarExtend(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64ScalarExtendSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an opcode suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects source and destination registers: %q", op, ins.Raw) + } + source, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrow, source, spec.sourceBits) + destinationBits := 64 + if spec.wordDestination { + destinationBits = 32 + } + extended := c.newTmp() + extension := "zext" + if spec.signed { + extension = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s i%d %%%s to i%d\n", extended, extension, spec.sourceBits, narrow, destinationBits) + value := "%" + extended + if spec.wordDestination { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, value) + value = "%" + wide + } + return true, false, c.storeReg(ins.Args[1].Reg, value) +} diff --git a/arm64_lower_extend_test.go b/arm64_lower_extend_test.go new file mode 100644 index 00000000..d6a8c9c4 --- /dev/null +++ b/arm64_lower_extend_test.go @@ -0,0 +1,81 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64ScalarExtendCompleteGoAssemblerForms(t *testing.T) { + src := `TEXT ·scalarExtendForms(SB), $0-0 + SXTB R0, R1 + SXTBW R0, R1 + SXTH R0, R1 + SXTHW R0, R1 + SXTW R0, R1 + UXTB R0, R1 + UXTBW R0, R1 + UXTH R0, R1 + UXTHW R0, R1 + UXTW R0, R1 + RET +` + requireARM64GoAssemblerResult(t, src, true) + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "scalarExtendForms": {Name: "scalarExtendForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-scalar-extend.ll", "arm64-scalar-extend.o", ll) + } +} + +func TestTranslateARM64ScalarExtendRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "SXTH $1, R1", + "SXTH R0, 0(R1)", + "SXTH 0(R0), R1", + "SXTWW R0, R1", + "UXTWW R0, R1", + "SXTB.P R0, R1", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT ·badScalarExtend(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, src, false) + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badScalarExtend": {Name: "badScalarExtend", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scalar extend optab", instruction) + } + }) + } +} diff --git a/arm64_lower_extract.go b/arm64_lower_extract.go new file mode 100644 index 00000000..b4eff9f3 --- /dev/null +++ b/arm64_lower_extract.go @@ -0,0 +1,58 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorExtract(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VEXT" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != "VEXT" || len(ins.Args) != 4 || + ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 VEXT expects $offset, Vm.B8/B16, Vn.B8/B16, Vd.B8/B16: %q", ins.Raw) + } + + var arrangement arm64VectorArrangement + for index, operand := range ins.Args[1:] { + if operand.Kind != OpReg { + return true, false, fmt.Errorf("arm64 VEXT accepts only arranged vector registers: %q", ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(operand.Reg) + if !valid || parsed.elementBits != 8 || parsed.lanes != 8 && parsed.lanes != 16 { + return true, false, fmt.Errorf("arm64 VEXT arrangement must be B8 or B16: %q", ins.Raw) + } + if index == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 VEXT arrangements must match: %q", ins.Raw) + } + } + offset := int(ins.Args[0].Imm) + if offset < 0 || offset >= arrangement.lanes { + return true, false, fmt.Errorf("arm64 VEXT offset must be in [0,%d): %q", arrangement.lanes, ins.Raw) + } + + // Go's Plan 9 order is $offset, Vm, Vn, Vd. EXT concatenates Vn:Vm + // and selects one vector starting at the byte offset. + m, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + n, err := c.loadARM64VectorInteger(ins.Args[2].Reg, arrangement) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " ; arm64 vector extract\n") + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i8> %s, <%d x i8> %s, <%d x i32> <", result, arrangement.lanes, n, arrangement.lanes, m, arrangement.lanes) + for lane := 0; lane < arrangement.lanes; lane++ { + if lane != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", offset+lane) + } + c.b.WriteString(">\n") + return true, false, c.storeARM64VectorInteger(ins.Args[3].Reg, arrangement, "%"+result) +} diff --git a/arm64_lower_extract_general_test.go b/arm64_lower_extract_general_test.go new file mode 100644 index 00000000..7dff0f91 --- /dev/null +++ b/arm64_lower_extract_general_test.go @@ -0,0 +1,69 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64GeneralExtractCompleteFormats(t *testing.T) { + const source = `TEXT extractComplete(SB),$0-0 + EXTR $0, R1, R2, R3 + EXTR $63, R4, R5, R6 + EXTR $17, ZR, R7, R8 + EXTRW $0, R9, R10, R11 + EXTRW $31, R12, R13, R14 + EXTRW $7, R15, ZR, ZR + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"extractComplete": {Name: "extractComplete", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"lshr i64", "shl i64", "or i64", "lshr i32", "shl i32", "or i32", "zext i32"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 EXTR lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-extract-complete.ll", "arm64-extract-complete.o", ll) +} + +func TestTranslateARM64GeneralExtractRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "EXTR R0, R1, R2, R3", + "EXTR $64, R1, R2, R3", + "EXTR $1, RSP, R2, R3", + "EXTR $1, R1, R2, RSP", + "EXTR.P $1, R1, R2, R3", + "EXTRW $32, R1, R2, R3", + "EXTRW $1, (R1), R2, R3", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 EXTR optab", instruction) + } + } +} diff --git a/arm64_lower_extract_test.go b/arm64_lower_extract_test.go new file mode 100644 index 00000000..561353aa --- /dev/null +++ b/arm64_lower_extract_test.go @@ -0,0 +1,140 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64VectorExtractCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT vectorextractforms(SB),$0-0\n") + for _, form := range []struct { + arrangement string + maximum int + }{ + {arrangement: "B8", maximum: 7}, + {arrangement: "B16", maximum: 15}, + } { + for _, immediate := range []int{0, 1, form.maximum} { + fmt.Fprintf(&source, "\tVEXT $%d, V30.%s, V31.%s, V29.%s\n", immediate, form.arrangement, form.arrangement, form.arrangement) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"vectorextractforms": {Name: "vectorextractforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, "shufflevector") { + t.Fatalf("ARM64 VEXT lowering for %s omitted shuffle semantics:\n%s", triple, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-extract.ll", "arm64-vector-extract.o", ll) + }) + } +} + +func TestTranslateARM64VectorExtractRejectsInvalidForms(t *testing.T) { + for _, instruction := range []string{ + "VEXT $8, V0.B8, V1.B8, V2.B8", + "VEXT $16, V0.B16, V1.B16, V2.B16", + "VEXT $-1, V0.B16, V1.B16, V2.B16", + "VEXT $4, V0.B8, V1.B16, V2.B16", + "VEXT $4, V0.H8, V1.H8, V2.H8", + "VEXT V0.B16, V1.B16, V2.B16", + "VEXT.P $4, V0.B16, V1.B16, V2.B16", + } { + source := "TEXT badvectorextract(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"badvectorextract": {Name: "badvectorextract", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted invalid VEXT form %q", instruction) + } + } +} + +func TestARM64VectorExtractRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectorextract(SB),$0-24 + MOVD left+0(FP), R0 + MOVD right+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V0.B16] + VLD1 (R1), [V1.B16] + VEXT $5, V1.B16, V0.B16, V2.B16 + VST1.P [V2.B16], 16(R2) + VEXT $3, V1.B8, V0.B8, V3.B8 + VST1 [V3.B16], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"vectorextract": { + Name: "vectorextract", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void vectorextract(const uint8_t *, const uint8_t *, uint8_t *); +int main(void) { + uint8_t left[16], right[16], got[32]; + for (int i = 0; i < 16; i++) { left[i] = (uint8_t)i; right[i] = (uint8_t)(16+i); got[i] = got[16+i] = 0xff; } + vectorextract(left, right, got); + for (int i = 0; i < 16; i++) if (got[i] != (uint8_t)(i+5)) return i+1; + for (int i = 0; i < 8; i++) { + int lane = i + 3; + uint8_t want = lane < 8 ? left[lane] : right[lane-8]; + if (got[16+i] != want) return i+21; + } + for (int i = 8; i < 16; i++) if (got[16+i] != 0) return i+41; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_extract", triple, ll, mainC, nil) +} diff --git a/arm64_lower_float_binary.go b/arm64_lower_float_binary.go new file mode 100644 index 00000000..312280a4 --- /dev/null +++ b/arm64_lower_float_binary.go @@ -0,0 +1,127 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func arm64ScalarFloatBinaryKind(op Op) (kind string, bits int, ok bool) { + bits = 32 + if strings.HasSuffix(string(op), "D") { + bits = 64 + } + switch op { + case "FADDS", "FADDD": + return "add", bits, true + case "FSUBS", "FSUBD": + return "sub", bits, true + case "FMULS", "FMULD": + return "mul", bits, true + case "FNMULS", "FNMULD": + return "nmul", bits, true + case "FDIVS", "FDIVD": + return "div", bits, true + case "FMAXS", "FMAXD": + return "maximum", bits, true + case "FMINS", "FMIND": + return "minimum", bits, true + case "FMAXNMS", "FMAXNMD": + return "maxnum", bits, true + case "FMINNMS", "FMINNMD": + return "minnum", bits, true + default: + return "", 0, false + } +} + +func (c *arm64Ctx) loadARM64ScalarFloatReg(reg Reg, bits int) (string, error) { + encoded, err := c.loadReg(reg) + if err != nil { + return "", err + } + switch bits { + case 64: + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to double\n", value, encoded) + return "%" + value, nil + case 32: + narrow := c.newTmp() + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", narrow, encoded) + fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", value, narrow) + return "%" + value, nil + case 16: + narrow := c.newTmp() + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i16\n", narrow, encoded) + fmt.Fprintf(c.b, " %%%s = bitcast i16 %%%s to half\n", value, narrow) + return "%" + value, nil + default: + return "", fmt.Errorf("arm64 unsupported scalar float width %d", bits) + } +} + +func (c *arm64Ctx) storeARM64ScalarFloatReg(reg Reg, bits int, value string) error { + switch bits { + case 64: + encoded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", encoded, value) + return c.storeReg(reg, "%"+encoded) + case 32: + encoded := c.newTmp() + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %s to i32\n", encoded, value) + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, encoded) + return c.storeReg(reg, "%"+wide) + case 16: + encoded := c.newTmp() + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast half %s to i16\n", encoded, value) + fmt.Fprintf(c.b, " %%%s = zext i16 %%%s to i64\n", wide, encoded) + return c.storeReg(reg, "%"+wide) + default: + return fmt.Errorf("arm64 unsupported scalar float width %d", bits) + } +} + +func (c *arm64Ctx) lowerARM64ScalarFloatBinary(op Op, ins Instr) (ok bool, terminated bool, err error) { + kind, bits, handled := arm64ScalarFloatBinaryKind(op) + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || (len(ins.Args) != 2 && len(ins.Args) != 3) { + return true, false, fmt.Errorf("arm64 %s expects Fsrc,Fdst or Fsrc1,Fsrc2,Fdst and no suffix: %q", op, ins.Raw) + } + for _, arg := range ins.Args { + if arg.Kind != OpReg || !isARM64FReg(arg.Reg) { + return true, false, fmt.Errorf("arm64 %s accepts only F registers: %q", op, ins.Raw) + } + } + rhs, err := c.loadARM64ScalarFloatReg(ins.Args[0].Reg, bits) + if err != nil { + return true, false, err + } + lhs, err := c.loadARM64ScalarFloatReg(ins.Args[1].Reg, bits) + if err != nil { + return true, false, err + } + floatType := "float" + suffix := "f32" + if bits == 64 { + floatType = "double" + suffix = "f64" + } + result := c.newTmp() + switch kind { + case "add", "sub", "mul", "div": + fmt.Fprintf(c.b, " %%%s = f%s %s %s, %s\n", result, kind, floatType, lhs, rhs) + case "nmul": + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fmul %s %s, %s\n", product, floatType, lhs, rhs) + fmt.Fprintf(c.b, " %%%s = fneg %s %%%s\n", result, floatType, product) + case "maximum", "minimum", "maxnum", "minnum": + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.%s(%s %s, %s %s)\n", result, floatType, kind, suffix, floatType, lhs, floatType, rhs) + } + dst := ins.Args[len(ins.Args)-1].Reg + return true, false, c.storeARM64ScalarFloatReg(dst, bits, "%"+result) +} diff --git a/arm64_lower_float_compare.go b/arm64_lower_float_compare.go new file mode 100644 index 00000000..4b01d34e --- /dev/null +++ b/arm64_lower_float_compare.go @@ -0,0 +1,75 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorFloatCompare(op Op, ins Instr) (ok bool, terminated bool, err error) { + predicates := map[Op]string{ + "VFCMEQ": "oeq", + "VFCMGE": "oge", + "VFCMGT": "ogt", + "VFCMLE": "ole", + "VFCMLT": "olt", + } + predicate, handled := predicates[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects register compare or $(0.0) compare form and no suffix: %q", op, ins.Raw) + } + + zeroForm := ins.Args[0].Kind == OpImm + if zeroForm { + if ins.Args[0].Imm != 0 || ins.Args[0].ImmRaw != "" || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s immediate compare requires exactly $(0.0), Vsrc., Vdst.: %q", op, ins.Raw) + } + } else { + if op == "VFCMLE" || op == "VFCMLT" || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s register compare form is absent from Go 1.27's optab: %q", op, ins.Raw) + } + } + + sourceIndex := 1 + if !zeroForm { + sourceIndex = 0 + } + arrangement, valid := parseARM64VectorArrangement(ins.Args[sourceIndex].Reg) + if !valid || !((arrangement.elementBits == 32 && (arrangement.lanes == 2 || arrangement.lanes == 4)) || + (arrangement.elementBits == 64 && arrangement.lanes == 2)) { + return true, false, fmt.Errorf("arm64 %s accepts only S2, S4, or D2 arrangements: %q", op, ins.Raw) + } + start := 1 + if !zeroForm { + start = 0 + } + for i := start; i < len(ins.Args); i++ { + parsed, ok := parseARM64VectorArrangement(ins.Args[i].Reg) + if !ok || parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + + left, err := c.loadARM64VectorFloat(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + right := "zeroinitializer" + if !zeroForm { + right, err = c.loadARM64VectorFloat(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + } + floatType := "float" + if arrangement.elementBits == 64 { + floatType = "double" + } + compared := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp %s <%d x %s> %s, %s\n", compared, predicate, arrangement.lanes, floatType, left, right) + allBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext <%d x i1> %%%s to <%d x i%d>\n", allBits, arrangement.lanes, compared, arrangement.lanes, arrangement.elementBits) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, "%"+allBits) +} diff --git a/arm64_lower_float_conditional_compare.go b/arm64_lower_float_conditional_compare.go new file mode 100644 index 00000000..2eb2071b --- /dev/null +++ b/arm64_lower_float_conditional_compare.go @@ -0,0 +1,82 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64FloatConditionalCompare(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "FCCMPS", "FCCMPD", "FCCMPES", "FCCMPED": + default: + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects condition, Fsrc, Fdst, $NZCV(0..15) and no suffix: %q", op, ins.Raw) + } + condition, conditionOK := arm64FloatConditionalCompareCondition(ins.Args[0]) + if !conditionOK || + ins.Args[1].Kind != OpReg || !isARM64FReg(ins.Args[1].Reg) || + ins.Args[2].Kind != OpReg || !isARM64FReg(ins.Args[2].Reg) || + ins.Args[3].Kind != OpImm || ins.Args[3].ImmRaw != "" || ins.Args[3].Imm < 0 || ins.Args[3].Imm > 15 { + return true, false, fmt.Errorf("arm64 %s expects condition, Fsrc, Fdst, $NZCV(0..15) and no suffix: %q", op, ins.Raw) + } + predicate, err := c.condValue(condition) + if err != nil { + return true, false, err + } + + bits := 64 + typeName := "double" + if op == "FCCMPS" || op == "FCCMPES" { + bits = 32 + typeName = "float" + } + right, err := c.loadARM64ScalarFloatReg(ins.Args[1].Reg, bits) + if err != nil { + return true, false, err + } + left, err := c.loadARM64ScalarFloatReg(ins.Args[2].Reg, bits) + if err != nil { + return true, false, err + } + + equal := c.newTmp() + less := c.newTmp() + greater := c.newTmp() + unordered := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp oeq %s %s, %s\n", equal, typeName, left, right) + fmt.Fprintf(c.b, " %%%s = fcmp olt %s %s, %s\n", less, typeName, left, right) + fmt.Fprintf(c.b, " %%%s = fcmp ogt %s %s, %s\n", greater, typeName, left, right) + fmt.Fprintf(c.b, " %%%s = fcmp uno %s %s, %s\n", unordered, typeName, left, right) + greaterOrEqual := c.newTmp() + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", greaterOrEqual, greater, equal) + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", carry, greaterOrEqual, unordered) + + nzcv := ins.Args[3].Imm + selectFlag := func(computed string, fallback bool) string { + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i1 %s, i1 %t\n", selected, predicate, computed, fallback) + return "%" + selected + } + c.flagsWritten = true + c.storeFlag(c.flagsNSlot, selectFlag("%"+less, nzcv&8 != 0)) + c.storeFlag(c.flagsZSlot, selectFlag("%"+equal, nzcv&4 != 0)) + c.storeFlag(c.flagsCSlot, selectFlag("%"+carry, nzcv&2 != 0)) + c.storeFlag(c.flagsVSlot, selectFlag("%"+unordered, nzcv&1 != 0)) + return true, false, nil +} + +func arm64FloatConditionalCompareCondition(operand Operand) (string, bool) { + if operand.Kind == OpIdent { + return operand.Ident, true + } + // AL is both an ARM64 condition and an x86 byte register. The parser keeps + // machine-register spellings architecture independent, so this condition is + // the only C_COND value represented as OpReg in ARM64 assembly. + if operand.Kind == OpReg && strings.EqualFold(string(operand.Reg), "AL") { + return "AL", true + } + return "", false +} diff --git a/arm64_lower_float_conditional_compare_test.go b/arm64_lower_float_conditional_compare_test.go new file mode 100644 index 00000000..8b711df8 --- /dev/null +++ b/arm64_lower_float_conditional_compare_test.go @@ -0,0 +1,159 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64FloatConditionalCompareCompleteGo127Forms(t *testing.T) { + const source = `TEXT floatConditionalCompareForms(SB), $0-0 + CMP R0, R0 + FCCMPS LE, F17, F12, $14 + FCCMPD HI, F11, F15, $15 + FCCMPES EQ, F1, F2, $0 + FCCMPED NE, F3, F4, $9 + FCCMPS AL, F31, F5, $5 + FCCMPD AL, F0, F9, $0 + FCCMPES AL, F7, F14, $1 + FCCMPED AL, F0, F14, $11 + FCCMPS NV, F6, F8, $3 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "floatConditionalCompareForms": {Name: "floatConditionalCompareForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"fcmp oeq float", "fcmp uno float", "fcmp oeq double", "fcmp uno double", "select i1"} { + if !strings.Contains(ir, want) { + t.Fatalf("floating conditional compare lowering omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-float-conditional-compare.ll", "arm64-float-conditional-compare.o", ir) + }) + } +} + +func TestTranslateARM64FloatConditionalCompareRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, instruction := range []string{ + "FCCMPD EQ, F0, F1", + "FCCMPD BAD, F0, F1, $0", + "FCCMPD EQ, R0, F1, $0", + "FCCMPD EQ, F0, R1, $0", + "FCCMPD EQ, F0, F1, $16", + "FCCMPD EQ, F0, F1, R0", + "FCCMPD.P EQ, F0, F1, $0", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badFloatConditionalCompare(SB), $0-0\n\tCMP R0, R0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badFloatConditionalCompare": {Name: "badFloatConditionalCompare", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's FCCMP optab", instruction) + } + }) + } +} + +func TestARM64FloatConditionalCompareRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT floatConditionalCompareRuntime(SB), $0-24 + FMOVD a+0(FP), F0 + FMOVD b+8(FP), F1 + MOVD out+16(FP), R2 + CMP R0, R0 + FCCMPD EQ, F0, F1, $0 + CSET MI, R3 + MOVD R3, 0(R2) + CSET EQ, R3 + MOVD R3, 8(R2) + CSET CS, R3 + MOVD R3, 16(R2) + CSET VS, R3 + MOVD R3, 24(R2) + CMP R0, R0 + FCCMPED NE, F0, F1, $10 + CSET MI, R3 + MOVD R3, 32(R2) + CSET EQ, R3 + MOVD R3, 40(R2) + CSET CS, R3 + MOVD R3, 48(R2) + CSET VS, R3 + MOVD R3, 56(R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "floatConditionalCompareRuntime": { + Name: "floatConditionalCompareRuntime", Args: []LLVMType{"double", "double", Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: "double", Index: 0, Field: -1}, + {Offset: 8, Type: "double", Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void floatConditionalCompareRuntime(double, double, uint64_t *); +int main(void) { + uint64_t got[8] = {0}; + floatConditionalCompareRuntime(2.0, 1.0, got); + const uint64_t want[8] = {1, 0, 0, 0, 1, 0, 1, 0}; + for (int i = 0; i < 8; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_float_conditional_compare", triple, ir, mainC, nil) +} diff --git a/arm64_lower_float_minmax_across.go b/arm64_lower_float_minmax_across.go new file mode 100644 index 00000000..2dabe115 --- /dev/null +++ b/arm64_lower_float_minmax_across.go @@ -0,0 +1,46 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64VectorFloatMinMaxAcrossOps = map[Op]string{ + "VFMAXV": "maximum", + "VFMINV": "minimum", + "VFMAXNMV": "maxnum", + "VFMINNMV": "minnum", +} + +func (c *arm64Ctx) lowerARM64VectorFloatMinMaxAcross(op Op, ins Instr) (ok bool, terminated bool, err error) { + operation, handled := arm64VectorFloatMinMaxAcrossOps[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || + ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects Vsrc.S4, Vdst and no suffix: %q", op, ins.Raw) + } + arrangement, valid := parseARM64VectorArrangement(ins.Args[0].Reg) + destinationIndex, destinationValid := arm64ParseVReg(ins.Args[1].Reg) + if !valid || arrangement != (arm64VectorArrangement{elementBits: 32, lanes: 4}) || + !destinationValid || strings.Contains(string(ins.Args[1].Reg), ".") { + return true, false, fmt.Errorf("arm64 %s requires an S4 source and bare V destination: %q", op, ins.Raw) + } + source, err := c.loadARM64VectorFloat(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + first := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x float> %s, i32 0\n", first, source) + result := "%" + first + for lane := 1; lane < 4; lane++ { + element := c.newTmp() + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x float> %s, i32 %d\n", element, source, lane) + fmt.Fprintf(c.b, " %%%s = call float @llvm.%s.f32(float %s, float %%%s)\n", combined, operation, result, element) + result = "%" + combined + } + destination := Reg(fmt.Sprintf("F%d", destinationIndex)) + return true, false, c.storeARM64ScalarFloatReg(destination, 32, result) +} diff --git a/arm64_lower_float_minmax_across_test.go b/arm64_lower_float_minmax_across_test.go new file mode 100644 index 00000000..12d983a3 --- /dev/null +++ b/arm64_lower_float_minmax_across_test.go @@ -0,0 +1,152 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64VectorFloatMinMaxAcrossForms = ` +TEXT vectorfloatminmaxacrossforms(SB),$0-0 + VFMAXV V0.S4, V1 + VFMINV V2.S4, V3 + VFMAXNMV V4.S4, V5 + VFMINNMV V6.S4, V7 + RET +` + +func TestTranslateARM64VectorFloatMinMaxAcrossCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64VectorFloatMinMaxAcrossForms, true) + file, err := Parse(ArchARM64, arm64VectorFloatMinMaxAcrossForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"vectorfloatminmaxacrossforms": {Name: "vectorfloatminmaxacrossforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{"@llvm.maximum.f32", "@llvm.minimum.f32", "@llvm.maxnum.f32", "@llvm.minnum.f32"} { + if !strings.Contains(ir, intrinsic) { + t.Fatalf("ARM64 float min/max-across omitted %s:\n%s", intrinsic, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-float-minmax-across.ll", "arm64-vector-float-minmax-across.o", ir) + }) + } +} + +func TestTranslateARM64VectorFloatMinMaxAcrossRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VFMAXV V0.S2, V1", + "VFMINV V0.D2, V1", + "VFMAXNMV V0.H8, V1", + "VFMINNMV V0.S4, V1.D2", + "VFMAXV V0.S4", + "VFMINV.P V0.S4, V1", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badvectorfloatminmaxacross(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", + Sigs: map[string]FuncSig{"badvectorfloatminmaxacross": {Name: "badvectorfloatminmaxacross", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's float min/max-across forms", instruction) + } + }) + } +} + +func TestARM64VectorFloatMinMaxAcrossRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectorfloatminmaxacross(SB),$0-16 + MOVD input+0(FP), R0 + MOVD output+8(FP), R1 + VLD1 (R0), [V0.S4] + VFMAXV V0.S4, V1 + VFMINV V0.S4, V2 + VFMAXNMV V0.S4, V3 + VFMINNMV V0.S4, V4 + FMOVS F1, 0(R1) + FMOVS F2, 4(R1) + FMOVS F3, 8(R1) + FMOVS F4, 12(R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorfloatminmaxacross": { + Name: "vectorfloatminmaxacross", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +extern void vectorfloatminmaxacross(const float *, float *); +int main(void) { + const float input[4] = {-2.0f, 7.0f, 3.0f, 1.0f}; + const float want[4] = {7.0f, -2.0f, 7.0f, -2.0f}; + float got[4] = {0}; + vectorfloatminmaxacross(input, got); + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_float_minmax_across", triple, ir, mainC, nil) +} + +func TestARM64RawFloatMinMaxAcrossUsesNamedFamily(t *testing.T) { + const source = ` +TEXT rawfloatminmaxacross(SB),$0-0 + WORD $0x6e30f800 + WORD $0x6eb0f800 + WORD $0x6e30c800 + WORD $0x6eb0c800 + RET +` + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfloatminmaxacross": {Name: "rawfloatminmaxacross", Ret: Void}}, + }); err != nil { + t.Fatal(err) + } +} diff --git a/arm64_lower_float_narrow.go b/arm64_lower_float_narrow.go new file mode 100644 index 00000000..62a8a049 --- /dev/null +++ b/arm64_lower_float_narrow.go @@ -0,0 +1,90 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64RawVectorFloatNarrow struct { + sourceBits int + upper bool + source int + destination int +} + +func decodeARM64RawVectorFloatNarrow(word uint32) (arm64RawVectorFloatNarrow, bool) { + if word&0xbfbffc00 != 0x0e216800 { + return arm64RawVectorFloatNarrow{}, false + } + sourceBits := 32 + if word&(1<<22) != 0 { + sourceBits = 64 + } + return arm64RawVectorFloatNarrow{ + sourceBits: sourceBits, + upper: word&(1<<30) != 0, + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawVectorFloatNarrow(form arm64RawVectorFloatNarrow) error { + return c.lowerARM64VectorFloatNarrowForm(form.sourceBits, form.upper, + Reg(fmt.Sprintf("V%d", form.source)), Reg(fmt.Sprintf("V%d", form.destination))) +} + +func (c *arm64Ctx) lowerARM64VectorFloatNarrow(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VFCVTN" && op != "VFCVTN2" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects Vsrc.S4/D2 and the corresponding narrow destination and no suffix: %q", op, ins.Raw) + } + source, sourceOK := parseARM64VectorArrangement(ins.Args[0].Reg) + destination, destinationOK := parseARM64VectorArrangement(ins.Args[1].Reg) + wantDestinationLanes := source.lanes + if op == "VFCVTN2" { + wantDestinationLanes *= 2 + } + validSource := sourceOK && ((source.elementBits == 32 && source.lanes == 4) || (source.elementBits == 64 && source.lanes == 2)) + if !validSource || !destinationOK || destination != (arm64VectorArrangement{elementBits: source.elementBits / 2, lanes: wantDestinationLanes}) { + return true, false, fmt.Errorf("arm64 %s operand arrangements are outside Go 1.27's narrowing optab: %q", op, ins.Raw) + } + return true, false, c.lowerARM64VectorFloatNarrowForm(source.elementBits, op == "VFCVTN2", ins.Args[0].Reg, ins.Args[1].Reg) +} + +func (c *arm64Ctx) lowerARM64VectorFloatNarrowForm(sourceBits int, upper bool, sourceReg, destinationReg Reg) error { + destinationBits := sourceBits / 2 + sourceLanes := 128 / sourceBits + sourceArrangement := arm64VectorArrangement{elementBits: sourceBits, lanes: sourceLanes} + source, err := c.loadARM64VectorFloat(sourceReg, sourceArrangement) + if err != nil { + return err + } + sourceType, destinationType := "float", "half" + if sourceBits == 64 { + sourceType, destinationType = "double", "float" + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fptrunc <%d x %s> %s to <%d x %s>\n", + converted, sourceLanes, sourceType, source, sourceLanes, destinationType) + if !upper { + return c.storeARM64VectorFloat(destinationReg, + arm64VectorArrangement{elementBits: destinationBits, lanes: sourceLanes}, "%"+converted) + } + + destinationArrangement := arm64VectorArrangement{elementBits: destinationBits, lanes: sourceLanes * 2} + result, err := c.loadARM64VectorFloat(destinationReg, destinationArrangement) + if err != nil { + return err + } + for lane := 0; lane < sourceLanes; lane++ { + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %%%s, i32 %d\n", element, sourceLanes, destinationType, converted, lane) + updated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x %s> %s, %s %%%s, i32 %d\n", + updated, sourceLanes*2, destinationType, result, destinationType, element, sourceLanes+lane) + result = "%" + updated + } + return c.storeARM64VectorFloat(destinationReg, destinationArrangement, result) +} diff --git a/arm64_lower_float_narrow_test.go b/arm64_lower_float_narrow_test.go new file mode 100644 index 00000000..d3b29b60 --- /dev/null +++ b/arm64_lower_float_narrow_test.go @@ -0,0 +1,183 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64VectorFloatNarrowCompleteGoAssemblerForms(t *testing.T) { + const source = ` +TEXT vectorfloatnarrowforms(SB),$0-0 + VFCVTN V2.S4, V3.H4 + VFCVTN2 V4.S4, V5.H8 + VFCVTN V0.D2, V31.S2 + VFCVTN2 V30.D2, V1.S4 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"vectorfloatnarrowforms": {Name: "vectorfloatnarrowforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"fptrunc <4 x float>", "fptrunc <2 x double>"} { + if !strings.Contains(ir, want) { + t.Fatalf("ARM64 VFCVTN family omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-float-narrow.ll", "arm64-vector-float-narrow.o", ir) + }) + } +} + +func TestTranslateARM64RawVectorFloatNarrowCompleteBaseFormats(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawvectorfloatnarrowforms(SB),$0-0\n") + for _, size := range []uint32{0, 1 << 22} { // 4S -> 4H and 2D -> 2S. + for _, upper := range []uint32{0, 1 << 30} { // FCVTN and FCVTN2. + fmt.Fprintf(&source, "\tWORD $%#08x\n", uint32(0x0e216800)|size|upper|30<<5|29) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawvectorfloatnarrowforms": {Name: "rawvectorfloatnarrowforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"fptrunc <4 x float>", "fptrunc <2 x double>"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw floating narrow omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-vector-float-narrow.ll", "arm64-raw-vector-float-narrow.o", ir) + }) + } +} + +func TestARM64RawVectorFloatNarrowDecoderRejectsAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x2e216800, // FCVTXN, not FCVTN. + 0x0ea16800, // Unallocated size. + 0x0e217800, // FCVTL, not FCVTN. + 0x0e216c00, // Adjacent opcode. + } { + if _, ok := decodeARM64RawVectorFloatNarrow(word); ok { + t.Fatalf("floating narrow decoder accepted adjacent encoding %#08x", word) + } + } +} + +func TestTranslateARM64VectorFloatNarrowRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "VFCVTN V0.D2", + "VFCVTN V0.D2, V1.S4", + "VFCVTN2 V0.D2, V1.S2", + "VFCVTN V0.S2, V1.H4", + "VFCVTN2 V0.S4, V1.S4", + "VFCVTN.P V0.D2, V1.S2", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT badvectorfloatnarrow(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", + Sigs: map[string]FuncSig{"badvectorfloatnarrow": {Name: "badvectorfloatnarrow", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VFCVTN/VFCVTN2 optab", instruction) + } + }) + } +} + +func TestARM64RawVectorFloatNarrowRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawvectorfloatnarrow(SB),$0-16 + MOVD input+0(FP), R0 + MOVD output+8(FP), R1 + ADD $16, R1, R2 + VLD1 (R0), [V1.S4] + VLD1 (R2), [V2.H8] + WORD $0x0e216820 // FCVTN V0.4H, V1.4S + VST1 [V0.H8], (R1) + WORD $0x4e216822 // FCVTN2 V2.8H, V1.4S + VST1 [V2.H8], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawvectorfloatnarrow": { + Name: "rawvectorfloatnarrow", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawvectorfloatnarrow(const float *, uint16_t *); +int main(void) { + const float input[4] = {1.0f, -2.0f, 0.5f, 65504.0f}; + const uint16_t want[16] = { + 0x3c00,0xc000,0x3800,0x7bff, 0,0,0,0, + 1,2,3,4, 0x3c00,0xc000,0x3800,0x7bff, + }; + uint16_t got[16] = {0,0,0,0,0,0,0,0, 1,2,3,4,5,6,7,8}; + rawvectorfloatnarrow(input, got); + for (int i = 0; i < 16; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_vector_float_narrow", triple, ir, mainC, nil) +} diff --git a/arm64_lower_float_pair.go b/arm64_lower_float_pair.go new file mode 100644 index 00000000..265095dd --- /dev/null +++ b/arm64_lower_float_pair.go @@ -0,0 +1,173 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +// lowerARM64FloatPair implements the single floating-point register-pair +// family described by Go 1.27's arm64 optab: FLDPS/FLDPD/FLDPQ and +// FSTPS/FSTPD/FSTPQ, including ordinary, pre-indexed, and post-indexed memory. +func (c *arm64Ctx) lowerARM64FloatPair(op Op, ins Instr) (ok bool, terminated bool, err error) { + elementBytes := map[Op]int{ + "FLDPS": 4, "FSTPS": 4, + "FLDPD": 8, "FSTPD": 8, + "FLDPQ": 16, "FSTPQ": 16, + }[op] + if elementBytes == 0 { + return false, false, nil + } + + rawOp := strings.ToUpper(string(ins.Op)) + preIndex, postIndex := false, false + switch rawOp { + case string(op): + case string(op) + ".W": + preIndex = true + case string(op) + ".P": + postIndex = true + default: + return true, false, fmt.Errorf("arm64 %s accepts only .P or .W memory suffixes: %q", op, ins.Raw) + } + + load := strings.HasPrefix(string(op), "FLDP") + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects exactly 2 operands: %q", op, ins.Raw) + } + memory, pair := ins.Args[0], ins.Args[1] + if !load { + pair, memory = ins.Args[0], ins.Args[1] + } + if pair.Kind != OpRegList || len(pair.RegList) != 2 { + return true, false, fmt.Errorf("arm64 %s expects a pair of floating-point registers: %q", op, ins.Raw) + } + for _, reg := range pair.RegList { + if _, valid := arm64ParseFReg(reg); !valid { + return true, false, fmt.Errorf("arm64 %s expects a pair of floating-point registers: %q", op, ins.Raw) + } + } + if load && pair.RegList[0] == pair.RegList[1] { + return true, false, fmt.Errorf("arm64 %s destination pair has constrained unpredictable behavior: %q", op, ins.Raw) + } + + ptr, base, increment, update, err := c.arm64FloatPairMemoryPointer(memory, elementBytes, preIndex, postIndex) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + for index, reg := range pair.RegList { + elementPtr := ptr + if index != 0 { + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = getelementptr i8, ptr %s, i64 %d\n", next, ptr, elementBytes) + elementPtr = "%" + next + } + if load { + if err := c.loadARM64FloatPairElement(reg, elementPtr, elementBytes); err != nil { + return true, false, err + } + } else if err := c.storeARM64FloatPairElement(reg, elementPtr, elementBytes); err != nil { + return true, false, err + } + } + if update { + if err := c.updatePostInc(base, increment); err != nil { + return true, false, err + } + } + return true, false, nil +} + +func (c *arm64Ctx) arm64FloatPairMemoryPointer(op Operand, elementBytes int, preIndex, postIndex bool) (ptr string, base Reg, increment int64, update bool, err error) { + if preIndex && postIndex { + return "", "", 0, false, fmt.Errorf("memory operand cannot be both pre- and post-indexed") + } + if op.Kind == OpSym { + if preIndex || postIndex { + return "", "", 0, false, fmt.Errorf("symbol operand cannot be pre- or post-indexed") + } + ptr, err := c.ptrFromSB(op.Sym) + return ptr, "", 0, false, err + } + if op.Kind != OpMem { + return "", "", 0, false, fmt.Errorf("expected a memory operand") + } + if op.Mem.Index != "" { + return "", "", 0, false, fmt.Errorf("register-indexed memory is absent from the Go 1.27 floating pair optab") + } + if !isARM64FloatPairMemoryBase(op.Mem.Base) { + return "", "", 0, false, fmt.Errorf("memory base must be R0-R30, RSP, SP, or ZR") + } + if preIndex || postIndex { + limit := int64(64*elementBytes - elementBytes) + if op.Mem.Off < -int64(64*elementBytes) || op.Mem.Off > limit || op.Mem.Off%int64(elementBytes) != 0 { + return "", "", 0, false, fmt.Errorf("pre/post-index offset %d must be aligned to %d and in [%d,%d]", op.Mem.Off, elementBytes, -64*elementBytes, limit) + } + } + addr, base, increment, err := c.addrI64(op.Mem, postIndex) + if err != nil { + return "", "", 0, false, err + } + if preIndex { + if err := c.storeReg(base, addr); err != nil { + return "", "", 0, false, err + } + } + name := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", name, addr) + return "%" + name, base, increment, postIndex, nil +} + +func isARM64FloatPairMemoryBase(reg Reg) bool { + if reg == SP || reg == Reg("RSP") || reg == ZR { + return true + } + s := strings.ToUpper(strings.TrimSpace(string(reg))) + if !strings.HasPrefix(s, "R") { + return false + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "R")) + return err == nil && n >= 0 && n <= 30 +} + +func (c *arm64Ctx) loadARM64FloatPairElement(reg Reg, ptr string, elementBytes int) error { + if elementBytes == 16 { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load <16 x i8>, ptr %s, align 1\n", value, ptr) + return c.storeVReg(reg, "%"+value) + } + bits := elementBytes * 8 + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i%d, ptr %s, align 1\n", value, bits, ptr) + value64 := "%" + value + if bits != 64 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i%d %%%s to i64\n", wide, bits, value) + value64 = "%" + wide + } + return c.storeReg(reg, value64) +} + +func (c *arm64Ctx) storeARM64FloatPairElement(reg Reg, ptr string, elementBytes int) error { + if elementBytes == 16 { + value, err := c.loadVReg(reg) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store <16 x i8> %s, ptr %s, align 1\n", value, ptr) + return nil + } + value, err := c.loadReg(reg) + if err != nil { + return err + } + bits := elementBytes * 8 + if bits == 64 { + fmt.Fprintf(c.b, " store i64 %s, ptr %s, align 1\n", value, ptr) + return nil + } + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrow, value, bits) + fmt.Fprintf(c.b, " store i%d %%%s, ptr %s, align 1\n", bits, narrow, ptr) + return nil +} diff --git a/arm64_lower_float_pair_test.go b/arm64_lower_float_pair_test.go new file mode 100644 index 00000000..d209906d --- /dev/null +++ b/arm64_lower_float_pair_test.go @@ -0,0 +1,178 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64FloatPairLoadStoreCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 defines one six-op family: FLDPS/FLDPD/FLDPQ and + // FSTPS/FSTPD/FSTPQ. Each precision accepts register- or SP-relative + // memory, pre/post indexing, and SB symbols. Cover every shape here rather + // than teaching the translator only the FSTPQ form first seen in Wago. + const source = ` +TEXT floatPairForms(SB),$0-0 + FLDPS (R0), (F0, F1) + FSTPS (F0, F1), 4(R0) + FLDPS.P 8(R1), (F2, F3) + FSTPS.W (F2, F3), -8(R1) + FLDPS pairData(SB), (F4, F5) + FSTPS (F4, F5), pairData+8(SB) + FLDPD -16(R2), (F6, F7) + FSTPD (F6, F7), (R2) + FLDPD.P 16(R3), (F8, F9) + FSTPD.W (F8, F9), -16(R3) + FLDPD pairData(SB), (F10, F11) + FSTPD (F10, F11), pairData+16(SB) + FLDPQ -32(R4), (F12, F13) + FSTPQ (F12, F13), (R4) + FLDPQ.P 32(R5), (F14, F15) + FSTPQ.W (F14, F15), -32(R5) + FLDPQ pairData(SB), (F16, F17) + FSTPQ (F16, F17), pairData+32(SB) + FLDPQ (RSP), (F30, F31) + FSTPQ (F30, F31), 64(RSP) + RET +` + requireARM64GoAssemblerResult(t, source, true) + + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-arm64", triple: "arm64-apple-darwin"}, + {name: "linux-arm64", triple: "aarch64-unknown-linux-gnu"}, + {name: "windows-arm64", triple: "aarch64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "floatPairForms": {Name: "floatPairForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load i32", "store i32", "load i64", "store i64", "load <16 x i8>", "store <16 x i8>"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s did not lower %q:\n%s", target.name, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "arm64-float-pair-"+target.name+".ll", "arm64-float-pair-"+target.name+".o", ll) + }) + } +} + +func TestTranslateARM64FloatPairLoadStoreRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "FLDPQ (R0), (R1, R2)", + "FSTPQ (R1, R2), (R0)", + "FLDPD (R0), (F2, F2)", + "FLDPS (R0)(R1), (F0, F1)", + "FSTPS (F0, F1), (R0)(R1)", + "FLDPQ.P pairData(SB), (F0, F1)", + "FSTPQ.W (F0, F1), pairData(SB)", + "FLDPQ.X (R0), (F0, F1)", + "FSTPD (F0), (R0)", + "FLDPS (R0)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badFloatPair(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badFloatPair": {Name: "badFloatPair", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 floating pair table", instruction) + } + }) + } +} + +func TestARM64FloatPairLoadStoreRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT floatPairRoundTrip(SB),$0-0 + FLDPS.P 8(R0), (F0, F1) + FSTPS.P (F0, F1), 8(R1) + FLDPD.W -16(R2), (F2, F3) + FSTPD.W (F2, F3), 16(R3) + FLDPQ (R4), (F4, F5) + FSTPQ (F4, F5), (R5) + MOVD R0, 0(R6) + MOVD R1, 8(R6) + MOVD R2, 16(R6) + MOVD R3, 24(R6) + RET +` + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + {Offset: 40, Type: Ptr, Index: 5, Field: -1}, + {Offset: 48, Type: Ptr, Index: 6, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "floatPairRoundTrip": {Name: "floatPairRoundTrip", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr, Ptr, Ptr}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +#include +extern void floatPairRoundTrip(const uint32_t *, uint32_t *, const uint64_t *, uint64_t *, const unsigned char *, unsigned char *, uintptr_t *); +int main(void) { + const uint32_t s[2] = {0x11223344u, 0xaabbccddu}; uint32_t so[2] = {0}; + const uint64_t dbuf[4] = {0, 0, 0x0102030405060708ull, 0x8877665544332211ull}; uint64_t doutbuf[4] = {0}; + const unsigned char q[32] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32}; unsigned char qout[32] = {0}; + uintptr_t advanced[4] = {0}; + floatPairRoundTrip(s, so, dbuf + 4, doutbuf, q, qout, advanced); + if (memcmp(s, so, sizeof(s)) != 0) return 1; + if (memcmp(dbuf + 2, doutbuf + 2, 2 * sizeof(uint64_t)) != 0) return 2; + if (memcmp(q, qout, sizeof(q)) != 0) return 3; + if (advanced[0] != (uintptr_t)(s + 2) || advanced[1] != (uintptr_t)(so + 2)) return 4; + if (advanced[2] != (uintptr_t)(dbuf + 2) || advanced[3] != (uintptr_t)(doutbuf + 2)) return 5; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_float_pair", triple, ll, mainC, nil) +} diff --git a/arm64_lower_float_scalar_compare.go b/arm64_lower_float_scalar_compare.go new file mode 100644 index 00000000..024d077c --- /dev/null +++ b/arm64_lower_float_scalar_compare.go @@ -0,0 +1,70 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64ScalarFloatCompare(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "FCMPS", "FCMPD", "FCMPES", "FCMPED": + default: + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || + ins.Args[1].Kind != OpReg || !isARM64FReg(ins.Args[1].Reg) || + !arm64ScalarFloatCompareSource(ins.Args[0]) { + return true, false, fmt.Errorf("arm64 %s expects Fsrc or $(0.0), Fdst and no suffix: %q", op, ins.Raw) + } + + bits := 64 + typeName := "double" + if op == "FCMPS" || op == "FCMPES" { + bits = 32 + typeName = "float" + } + right := formatLLVMFloat64Literal(0) + if ins.Args[0].Kind == OpReg { + right, err = c.loadARM64ScalarFloatReg(ins.Args[0].Reg, bits) + if err != nil { + return true, false, err + } + } + left, err := c.loadARM64ScalarFloatReg(ins.Args[1].Reg, bits) + if err != nil { + return true, false, err + } + c.setARM64FloatCompareFlags(typeName, left, right) + return true, false, nil +} + +func arm64ScalarFloatCompareSource(operand Operand) bool { + if operand.Kind == OpReg { + return isARM64FReg(operand.Reg) + } + // Go's C_FCON optab class accepts any floating constant here even though + // AArch64's FCMP-immediate encoding always compares against zero. Preserve + // that assembler behavior instead of treating the source spelling as the + // value encoded by the instruction. + return operand.Kind == OpImm && operand.ImmRaw == "" && operand.ImmIsFloat +} + +func (c *arm64Ctx) setARM64FloatCompareFlags(typeName, left, right string) { + equal := c.newTmp() + less := c.newTmp() + greater := c.newTmp() + unordered := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp oeq %s %s, %s\n", equal, typeName, left, right) + fmt.Fprintf(c.b, " %%%s = fcmp olt %s %s, %s\n", less, typeName, left, right) + fmt.Fprintf(c.b, " %%%s = fcmp ogt %s %s, %s\n", greater, typeName, left, right) + fmt.Fprintf(c.b, " %%%s = fcmp uno %s %s, %s\n", unordered, typeName, left, right) + greaterOrEqual := c.newTmp() + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", greaterOrEqual, greater, equal) + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", carry, greaterOrEqual, unordered) + c.flagsWritten = true + c.storeFlag(c.flagsNSlot, "%"+less) + c.storeFlag(c.flagsZSlot, "%"+equal) + c.storeFlag(c.flagsCSlot, "%"+carry) + c.storeFlag(c.flagsVSlot, "%"+unordered) +} diff --git a/arm64_lower_float_scalar_compare_test.go b/arm64_lower_float_scalar_compare_test.go new file mode 100644 index 00000000..24347ab7 --- /dev/null +++ b/arm64_lower_float_scalar_compare_test.go @@ -0,0 +1,167 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64ScalarFloatCompareForms = ` +TEXT scalarfloatcompareforms(SB),$0-0 + FCMPS F3, F17 + FCMPS $(1.0), F8 + FCMPD F11, F27 + FCMPD $(0.0), F25 + FCMPES F16, F30 + FCMPES $(0.0), F29 + FCMPED F13, F10 + FCMPED $(0.0), F25 + RET +` + +func TestTranslateARM64ScalarFloatCompareCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64ScalarFloatCompareForms, true) + file, err := Parse(ArchARM64, arm64ScalarFloatCompareForms) + if err != nil { + t.Fatal(err) + } + foundFloatImmediate := false + for _, ins := range file.Funcs[0].Instrs { + if ins.Op == "FCMPS" && len(ins.Args) == 2 && ins.Args[0].Kind == OpImm { + foundFloatImmediate = ins.Args[0].ImmIsFloat + } + } + if !foundFloatImmediate { + t.Fatal("FCMP floating immediate was not preserved as C_FCON") + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "scalarfloatcompareforms": {Name: "scalarfloatcompareforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"fcmp oeq float", "fcmp uno float", "fcmp oeq double", "fcmp uno double"} { + if !strings.Contains(ir, want) { + t.Fatalf("scalar floating compare lowering omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-scalar-float-compare.ll", "arm64-scalar-float-compare.o", ir) + }) + } +} + +func TestTranslateARM64ScalarFloatCompareRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "FCMPS F0", + "FCMPS R0, F1", + "FCMPS F0, R1", + "FCMPS $1, F1", + "FCMPS $(1), F1", + "FCMPD F0, F1, F2", + "FCMPED.P F0, F1", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badscalarfloatcompare(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badscalarfloatcompare": {Name: "badscalarfloatcompare", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's FCMP forms", instruction) + } + }) + } +} + +func TestARM64ScalarFloatCompareRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT scalarfloatcompare(SB),$0-16 + FMOVS a+0(FP), F0 + FMOVS b+4(FP), F1 + MOVD out+8(FP), R2 + FCMPS F0, F1 + CSET MI, R3 + MOVD R3, 0(R2) + CSET EQ, R3 + MOVD R3, 8(R2) + CSET CS, R3 + MOVD R3, 16(R2) + CSET VS, R3 + MOVD R3, 24(R2) + FCMPES $(0.0), F1 + CSET MI, R3 + MOVD R3, 32(R2) + CSET EQ, R3 + MOVD R3, 40(R2) + CSET CS, R3 + MOVD R3, 48(R2) + CSET VS, R3 + MOVD R3, 56(R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "scalarfloatcompare": { + Name: "scalarfloatcompare", Args: []LLVMType{"float", "float", Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: "float", Index: 0, Field: -1}, + {Offset: 4, Type: "float", Index: 1, Field: -1}, + {Offset: 8, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void scalarfloatcompare(float, float, uint64_t *); +int main(void) { + uint64_t got[8] = {0}; + scalarfloatcompare(2.0f, 1.0f, got); + const uint64_t want[8] = {1,0,0,0, 0,0,1,0}; + for (int i = 0; i < 8; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_scalar_float_compare", triple, ir, mainC, nil) +} diff --git a/arm64_lower_float_scalar_unary_test.go b/arm64_lower_float_scalar_unary_test.go new file mode 100644 index 00000000..f877786a --- /dev/null +++ b/arm64_lower_float_scalar_unary_test.go @@ -0,0 +1,77 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64ScalarFloatUnaryCompleteGoAssemblerForms(t *testing.T) { + ops := []string{ + "FABSS", "FABSD", "FNEGS", "FNEGD", "FSQRTS", "FSQRTD", + "FRINTNS", "FRINTND", "FRINTPS", "FRINTPD", "FRINTMS", "FRINTMD", + "FRINTZS", "FRINTZD", "FRINTAS", "FRINTAD", "FRINTXS", "FRINTXD", + "FRINTIS", "FRINTID", + } + var source strings.Builder + source.WriteString("TEXT ·scalarfloatunaryforms(SB), $0-0\n") + for _, op := range ops { + source.WriteString("\t" + op + " F0, F31\n") + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "scalarfloatunaryforms": {Name: "scalarfloatunaryforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-scalar-float-unary.ll", "arm64-scalar-float-unary.o", ll) + }) + } +} + +func TestTranslateARM64ScalarFloatUnaryRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "FNEGD F0", + "FNEGS F0, F1, F2", + "FABSS R0, F1", + "FRINTND F0, R1", + "FRINTAS.P F0, F1", + } { + source := "TEXT ·bad(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scalar floating unary table", instruction) + } + } +} diff --git a/arm64_lower_float_select_test.go b/arm64_lower_float_select_test.go new file mode 100644 index 00000000..208637cb --- /dev/null +++ b/arm64_lower_float_select_test.go @@ -0,0 +1,134 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64FloatConditionalSelectCompleteGoAssemblerForms(t *testing.T) { + conditions := []string{"EQ", "NE", "HS", "LO", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV"} + var source strings.Builder + source.WriteString("TEXT floatconditionalselectforms(SB),$0-0\n\tCMP R0, R1\n") + for _, op := range []string{"FCSELS", "FCSELD"} { + for _, condition := range conditions { + source.WriteString("\t" + op + " " + condition + ", F0, F1, F31\n") + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"floatconditionalselectforms": {Name: "floatconditionalselectforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"select i1", "float", "double"} { + if !strings.Contains(ir, want) { + t.Fatalf("floating conditional-select family for %s omitted %q:\n%s", triple, want, ir) + } + } + compileLLVMToObject(t, llc, triple, "arm64-float-conditional-select.ll", "arm64-float-conditional-select.o", ir) + }) + } +} + +func TestTranslateARM64FloatConditionalSelectRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "FCSELS EQ, F0, F1", + "FCSELD EQ, F0, F1, F2, F3", + "FCSELS BAD, F0, F1, F2", + "FCSELS EQ, R0, F1, F2", + "FCSELD EQ, F0, (R1), F2", + "FCSELS.P EQ, F0, F1, F2", + } { + source := "TEXT badfloatconditionalselect(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", + Sigs: map[string]FuncSig{"badfloatconditionalselect": {Name: "badfloatconditionalselect", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's FCSEL optab", instruction) + } + } +} + +func TestARM64FloatConditionalSelectRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT floatconditionalselect(SB),$0-24 + MOVD input+0(FP), R0 + MOVD output+8(FP), R1 + MOVD flag+16(FP), R2 + FMOVS 0(R0), F0 + FMOVS 4(R0), F1 + FMOVD 8(R0), F2 + FMOVD 16(R0), F3 + CMP $0, R2 + FCSELS GT, F0, F1, F4 + FCSELD LE, F2, F3, F5 + FMOVS F4, 0(R1) + FMOVD F5, 8(R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"floatconditionalselect": { + Name: "floatconditionalselect", Args: []LLVMType{Ptr, Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +struct input { float a, b; double c, d; }; +struct output { float s; uint32_t pad; double d; }; +extern void floatconditionalselect(const struct input *, struct output *, uint64_t); +int main(void) { + const struct input input = {1.25f, -2.5f, 3.75, -4.5}; + struct output positive = {0}, zero = {0}; + floatconditionalselect(&input, &positive, 1); + floatconditionalselect(&input, &zero, 0); + if (positive.s != input.a || positive.d != input.d) return 1; + if (zero.s != input.b || zero.d != input.c) return 2; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_float_conditional_select", triple, ir, mainC, nil) +} diff --git a/arm64_lower_float_vector.go b/arm64_lower_float_vector.go new file mode 100644 index 00000000..32b54fc3 --- /dev/null +++ b/arm64_lower_float_vector.go @@ -0,0 +1,866 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +type arm64VectorArrangement struct { + elementBits int + lanes int +} + +func parseARM64VectorArrangement(reg Reg) (arm64VectorArrangement, bool) { + s := strings.ToUpper(strings.TrimSpace(string(reg))) + dot := strings.IndexByte(s, '.') + if dot < 2 || dot+2 >= len(s) { + return arm64VectorArrangement{}, false + } + if _, ok := arm64ParseVReg(reg); !ok { + return arm64VectorArrangement{}, false + } + kind := s[dot+1] + lanes, err := strconv.Atoi(s[dot+2:]) + if err != nil { + return arm64VectorArrangement{}, false + } + elementBits := 0 + switch kind { + case 'B': + elementBits = 8 + case 'H': + elementBits = 16 + case 'S': + elementBits = 32 + case 'D': + elementBits = 64 + default: + return arm64VectorArrangement{}, false + } + if lanes*elementBits != 64 && lanes*elementBits != 128 { + return arm64VectorArrangement{}, false + } + return arm64VectorArrangement{elementBits: elementBits, lanes: lanes}, true +} + +func (c *arm64Ctx) loadARM64VectorFloat(reg Reg, arrangement arm64VectorArrangement) (string, error) { + bytesValue, err := c.loadVReg(reg) + if err != nil { + return "", err + } + physicalLanes := 128 / arrangement.elementBits + floatType := "float" + if arrangement.elementBits == 16 { + floatType = "half" + } else if arrangement.elementBits == 64 { + floatType = "double" + } + all := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x %s>\n", all, bytesValue, physicalLanes, floatType) + if arrangement.lanes == physicalLanes { + return "%" + all, nil + } + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x %s> %%%s, <%d x %s> poison, <%d x i32> <", low, physicalLanes, floatType, all, physicalLanes, floatType, arrangement.lanes) + for i := 0; i < arrangement.lanes; i++ { + if i != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", i) + } + c.b.WriteString(">\n") + return "%" + low, nil +} + +func (c *arm64Ctx) storeARM64VectorFloat(reg Reg, arrangement arm64VectorArrangement, value string) error { + floatType := "float" + if arrangement.elementBits == 16 { + floatType = "half" + } else if arrangement.elementBits == 64 { + floatType = "double" + } + activeBytes := arrangement.lanes * arrangement.elementBits / 8 + if activeBytes == 16 { + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x %s> %s to <16 x i8>\n", out, arrangement.lanes, floatType, value) + return c.storeVReg(reg, "%"+out) + } + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x %s> %s to i64\n", low, arrangement.lanes, floatType, value) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> zeroinitializer, i64 %%%s, i32 0\n", wide, low) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", out, wide) + return c.storeVReg(reg, "%"+out) +} + +func (c *arm64Ctx) loadARM64VectorInteger(reg Reg, arrangement arm64VectorArrangement) (string, error) { + bytesValue, err := c.loadVReg(reg) + if err != nil { + return "", err + } + physicalLanes := 128 / arrangement.elementBits + all := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x i%d>\n", all, bytesValue, physicalLanes, arrangement.elementBits) + if arrangement.lanes == physicalLanes { + return "%" + all, nil + } + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %%%s, <%d x i%d> poison, <%d x i32> <", low, physicalLanes, arrangement.elementBits, all, physicalLanes, arrangement.elementBits, arrangement.lanes) + for i := 0; i < arrangement.lanes; i++ { + if i != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", i) + } + c.b.WriteString(">\n") + return "%" + low, nil +} + +func (c *arm64Ctx) storeARM64VectorInteger(reg Reg, arrangement arm64VectorArrangement, value string) error { + activeBytes := arrangement.lanes * arrangement.elementBits / 8 + if activeBytes == 16 { + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to <16 x i8>\n", out, arrangement.lanes, arrangement.elementBits, value) + return c.storeVReg(reg, "%"+out) + } + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %s to i64\n", low, arrangement.lanes, arrangement.elementBits, value) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> zeroinitializer, i64 %%%s, i32 0\n", wide, low) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", out, wide) + return c.storeVReg(reg, "%"+out) +} + +func (c *arm64Ctx) lowerARM64VectorIntegerAddSub(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VADD" && op != "VSUB" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || (len(ins.Args) != 2 && len(ins.Args) != 3) { + return true, false, fmt.Errorf("arm64 %s expects two bare V registers or three same-arrangement vector registers: %q", op, ins.Raw) + } + + arranged := strings.Contains(string(ins.Args[0].Reg), ".") + if arranged { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s arranged form requires three operands: %q", op, ins.Raw) + } + allowed := func(a arm64VectorArrangement) bool { + return (a.elementBits == 8 && (a.lanes == 8 || a.lanes == 16)) || + (a.elementBits == 16 && (a.lanes == 4 || a.lanes == 8)) || + (a.elementBits == 32 && (a.lanes == 2 || a.lanes == 4)) || + (a.elementBits == 64 && a.lanes == 2) + } + var arrangement arm64VectorArrangement + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || !allowed(parsed) { + return true, false, fmt.Errorf("arm64 %s has an invalid vector arrangement: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + source, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + base, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + result := c.newTmp() + operation := "add" + if op == "VSUB" { + operation = "sub" + } + fmt.Fprintf(c.b, " %%%s = %s <%d x i%d> %s, %s\n", result, operation, arrangement.lanes, arrangement.elementBits, base, source) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, "%"+result) + } + + for _, arg := range ins.Args { + if arg.Kind != OpReg || strings.Contains(string(arg.Reg), ".") { + return true, false, fmt.Errorf("arm64 %s scalar SIMD form requires bare V registers: %q", op, ins.Raw) + } + if _, valid := arm64ParseVReg(arg.Reg); !valid { + return true, false, fmt.Errorf("arm64 %s scalar SIMD form requires bare V registers: %q", op, ins.Raw) + } + } + sourceBytes, err := c.loadVReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + baseIndex := 1 + destinationIndex := 1 + if len(ins.Args) == 3 { + destinationIndex = 2 + } + baseBytes, err := c.loadVReg(ins.Args[baseIndex].Reg) + if err != nil { + return true, false, err + } + sourceWords := c.newTmp() + baseWords := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", sourceWords, sourceBytes) + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", baseWords, baseBytes) + sourceLow := c.newTmp() + baseLow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 0\n", sourceLow, sourceWords) + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 0\n", baseLow, baseWords) + resultLow := c.newTmp() + operation := "add" + if op == "VSUB" { + operation = "sub" + } + fmt.Fprintf(c.b, " %%%s = %s i64 %%%s, %%%s\n", resultLow, operation, baseLow, sourceLow) + resultWords := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> zeroinitializer, i64 %%%s, i32 0\n", resultWords, resultLow) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <2 x i64> %%%s to <16 x i8>\n", out, resultWords) + return true, false, c.storeVReg(ins.Args[destinationIndex].Reg, "%"+out) +} + +func (c *arm64Ctx) lowerARM64AddAcross(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "VADDV": + // handled below + default: + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 VADDV expects arranged vector source and bare V destination: %q", ins.Raw) + } + arrangement, valid := parseARM64VectorArrangement(ins.Args[0].Reg) + if !valid || !((arrangement.elementBits == 8 && (arrangement.lanes == 8 || arrangement.lanes == 16)) || + (arrangement.elementBits == 16 && (arrangement.lanes == 4 || arrangement.lanes == 8)) || + (arrangement.elementBits == 32 && arrangement.lanes == 4)) { + return true, false, fmt.Errorf("arm64 VADDV accepts only B8, B16, H4, H8, or S4 source: %q", ins.Raw) + } + if strings.Contains(string(ins.Args[1].Reg), ".") { + return true, false, fmt.Errorf("arm64 VADDV destination must be a bare V register: %q", ins.Raw) + } + if _, ok := arm64ParseVReg(ins.Args[1].Reg); !ok { + return true, false, fmt.Errorf("arm64 VADDV destination must be a bare V register: %q", ins.Raw) + } + + lanes, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + sum := "0" + for lane := 0; lane < arrangement.lanes; lane++ { + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", element, arrangement.lanes, arrangement.elementBits, lanes, lane) + added := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i%d %s, %%%s\n", added, arrangement.elementBits, sum, element) + sum = "%" + added + } + physicalLanes := 128 / arrangement.elementBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> zeroinitializer, i%d %s, i32 0\n", result, physicalLanes, arrangement.elementBits, arrangement.elementBits, sum) + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", out, physicalLanes, arrangement.elementBits, result) + return true, false, c.storeVReg(ins.Args[1].Reg, "%"+out) +} + +func (c *arm64Ctx) lowerARM64VectorFloatArithmetic(op Op, ins Instr) (ok bool, terminated bool, err error) { + type operationSpec struct { + operation string + pairwise bool + } + specs := map[Op]operationSpec{ + "VFADD": {operation: "add"}, + "VFSUB": {operation: "sub"}, + "VFMUL": {operation: "mul"}, + "VFDIV": {operation: "div"}, + "VFMAX": {operation: "maximum"}, + "VFMAXNM": {operation: "maxnum"}, + "VFMIN": {operation: "minimum"}, + "VFMINNM": {operation: "minnum"}, + "VFADDP": {operation: "add", pairwise: true}, + "VFMAXP": {operation: "maximum", pairwise: true}, + "VFMAXNMP": {operation: "maxnum", pairwise: true}, + "VFMINP": {operation: "minimum", pairwise: true}, + "VFMINNMP": {operation: "minnum", pairwise: true}, + } + spec, handled := specs[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects three same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + var arrangement arm64VectorArrangement + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || !((parsed.elementBits == 32 && (parsed.lanes == 2 || parsed.lanes == 4)) || (parsed.elementBits == 64 && parsed.lanes == 2)) { + return true, false, fmt.Errorf("arm64 %s accepts only S2, S4, or D2 arrangements: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + + first, err := c.loadARM64VectorFloat(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + second, err := c.loadARM64VectorFloat(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + floatType := "float" + intrinsicSuffix := "f32" + if arrangement.elementBits == 64 { + floatType, intrinsicSuffix = "double", "f64" + } + result := "" + if !spec.pairwise { + computed := c.newTmp() + switch spec.operation { + case "add", "sub", "mul", "div": + fmt.Fprintf(c.b, " %%%s = f%s <%d x %s> %s, %s\n", computed, spec.operation, arrangement.lanes, floatType, second, first) + default: + fmt.Fprintf(c.b, " %%%s = call <%d x %s> @llvm.%s.v%d%s(<%d x %s> %s, <%d x %s> %s)\n", + computed, arrangement.lanes, floatType, spec.operation, arrangement.lanes, intrinsicSuffix, + arrangement.lanes, floatType, second, arrangement.lanes, floatType, first) + } + result = "%" + computed + } else { + result = "poison" + half := arrangement.lanes / 2 + for lane := 0; lane < arrangement.lanes; lane++ { + source := second + if lane >= half { + source = first + } + pair := (lane % half) * 2 + left := c.newTmp() + right := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %s, i32 %d\n", left, arrangement.lanes, floatType, source, pair) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %s, i32 %d\n", right, arrangement.lanes, floatType, source, pair+1) + combined := c.newTmp() + if spec.operation == "add" { + fmt.Fprintf(c.b, " %%%s = fadd %s %%%s, %%%s\n", combined, floatType, left, right) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.%s(%s %%%s, %s %%%s)\n", combined, floatType, spec.operation, intrinsicSuffix, floatType, left, floatType, right) + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x %s> %s, %s %%%s, i32 %d\n", inserted, arrangement.lanes, floatType, result, floatType, combined, lane) + result = "%" + inserted + } + } + return true, false, c.storeARM64VectorFloat(ins.Args[2].Reg, arrangement, result) +} + +func (c *arm64Ctx) lowerARM64VectorFloatUnary(op Op, ins Instr) (ok bool, terminated bool, err error) { + operations := map[Op]string{ + "VFABS": "fabs", + "VFNEG": "neg", + "VFSQRT": "sqrt", + "VFRINTN": "roundeven", + "VFRINTP": "ceil", + "VFRINTM": "floor", + "VFRINTZ": "trunc", + "VFCVTZS": "fptosi.sat", + "VFCVTZU": "fptoui.sat", + "VFCVTNS": "fptosi.roundeven.sat", + "VFCVTNU": "fptoui.roundeven.sat", + "VFCVTMS": "fptosi.floor.sat", + "VFCVTMU": "fptoui.floor.sat", + "VFCVTAS": "fptosi.round.sat", + "VFCVTAU": "fptoui.round.sat", + "VFCVTPS": "fptosi.ceil.sat", + "VFCVTPU": "fptoui.ceil.sat", + "VSCVTF": "sitofp", + "VUCVTF": "uitofp", + } + operation, handled := operations[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects two same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + sourceArrangement, sourceValid := parseARM64VectorArrangement(ins.Args[0].Reg) + destinationArrangement, destinationValid := parseARM64VectorArrangement(ins.Args[1].Reg) + if !sourceValid || !destinationValid || sourceArrangement != destinationArrangement || + !((sourceArrangement.elementBits == 32 && (sourceArrangement.lanes == 2 || sourceArrangement.lanes == 4)) || + (sourceArrangement.elementBits == 64 && sourceArrangement.lanes == 2)) { + return true, false, fmt.Errorf("arm64 %s requires matching S2, S4, or D2 arrangements: %q", op, ins.Raw) + } + arrangement := sourceArrangement + floatType := "float" + floatSuffix := "f32" + if arrangement.elementBits == 64 { + floatType, floatSuffix = "double", "f64" + } + vectorFloatSuffix := fmt.Sprintf("v%d%s", arrangement.lanes, floatSuffix) + vectorIntegerSuffix := fmt.Sprintf("v%di%d", arrangement.lanes, arrangement.elementBits) + + switch operation { + case "sitofp", "uitofp": + source, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s <%d x i%d> %s to <%d x %s>\n", converted, operation, arrangement.lanes, arrangement.elementBits, source, arrangement.lanes, floatType) + return true, false, c.storeARM64VectorFloat(ins.Args[1].Reg, arrangement, "%"+converted) + case "fptosi.sat", "fptoui.sat", + "fptosi.roundeven.sat", "fptoui.roundeven.sat", + "fptosi.floor.sat", "fptoui.floor.sat", + "fptosi.round.sat", "fptoui.round.sat", + "fptosi.ceil.sat", "fptoui.ceil.sat": + source, err := c.loadARM64VectorFloat(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + roundingIntrinsic := "" + switch { + case strings.Contains(operation, ".roundeven."): + roundingIntrinsic = "roundeven" + case strings.Contains(operation, ".floor."): + roundingIntrinsic = "floor" + case strings.Contains(operation, ".round."): + roundingIntrinsic = "round" + case strings.Contains(operation, ".ceil."): + roundingIntrinsic = "ceil" + } + if roundingIntrinsic != "" { + rounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <%d x %s> @llvm.%s.%s(<%d x %s> %s)\n", + rounded, arrangement.lanes, floatType, roundingIntrinsic, vectorFloatSuffix, + arrangement.lanes, floatType, source) + source = "%" + rounded + } + conversionIntrinsic := "fptosi.sat" + if strings.HasPrefix(operation, "fptoui") { + conversionIntrinsic = "fptoui.sat" + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <%d x i%d> @llvm.%s.%s.%s(<%d x %s> %s)\n", + converted, arrangement.lanes, arrangement.elementBits, conversionIntrinsic, vectorIntegerSuffix, vectorFloatSuffix, + arrangement.lanes, floatType, source) + return true, false, c.storeARM64VectorInteger(ins.Args[1].Reg, arrangement, "%"+converted) + default: + source, err := c.loadARM64VectorFloat(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + result := c.newTmp() + if operation == "neg" { + fmt.Fprintf(c.b, " %%%s = fneg <%d x %s> %s\n", result, arrangement.lanes, floatType, source) + } else { + fmt.Fprintf(c.b, " %%%s = call <%d x %s> @llvm.%s.%s(<%d x %s> %s)\n", result, arrangement.lanes, floatType, operation, vectorFloatSuffix, arrangement.lanes, floatType, source) + } + return true, false, c.storeARM64VectorFloat(ins.Args[1].Reg, arrangement, "%"+result) + } +} + +func (c *arm64Ctx) lowerARM64VectorShiftRight(op Op, ins Instr) (ok bool, terminated bool, err error) { + type shiftRightSpec struct { + signed bool + rounding bool + accumulate bool + } + spec, handled := map[Op]shiftRightSpec{ + "VSSHR": {signed: true}, + "VSSRA": {signed: true, accumulate: true}, + "VSRSHR": {signed: true, rounding: true}, + "VSRSRA": {signed: true, rounding: true, accumulate: true}, + "VUSHR": {}, + "VUSRA": {accumulate: true}, + "VURSHR": {rounding: true}, + "VURSRA": {rounding: true, accumulate: true}, + }[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects $shift, Vsrc., Vdst. and no suffix: %q", op, ins.Raw) + } + scalar := !strings.Contains(string(ins.Args[1].Reg), ".") && !strings.Contains(string(ins.Args[2].Reg), ".") + sourceArrangement, sourceValid := parseARM64VectorArrangement(ins.Args[1].Reg) + destinationArrangement, destinationValid := parseARM64VectorArrangement(ins.Args[2].Reg) + if scalar { + _, sourceValid = arm64ParseVReg(ins.Args[1].Reg) + _, destinationValid = arm64ParseVReg(ins.Args[2].Reg) + sourceArrangement = arm64VectorArrangement{elementBits: 64, lanes: 1} + destinationArrangement = sourceArrangement + } + allowed := func(a arm64VectorArrangement) bool { + return (a.elementBits == 8 && (a.lanes == 8 || a.lanes == 16)) || + (a.elementBits == 16 && (a.lanes == 4 || a.lanes == 8)) || + (a.elementBits == 32 && (a.lanes == 2 || a.lanes == 4)) || + (a.elementBits == 64 && a.lanes == 2) + } + if !sourceValid || !destinationValid || sourceArrangement != destinationArrangement || !scalar && !allowed(sourceArrangement) { + return true, false, fmt.Errorf("arm64 %s requires a matching bare scalar D form or B8/B16/H4/H8/S2/S4/D2 vector arrangements: %q", op, ins.Raw) + } + if ins.Args[0].Imm < 1 || ins.Args[0].Imm > int64(sourceArrangement.elementBits) { + return true, false, fmt.Errorf("arm64 %s shift must be in [1,%d]: %q", op, sourceArrangement.elementBits, ins.Raw) + } + source, err := c.loadARM64VectorInteger(ins.Args[1].Reg, sourceArrangement) + if err != nil { + return true, false, err + } + vectorType := fmt.Sprintf("<%d x i%d>", sourceArrangement.lanes, sourceArrangement.elementBits) + if scalar { + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i64> %s, i32 0\n", extracted, source) + source = "%" + extracted + vectorType = "i64" + } + shiftValue := func(amount int64) string { + if scalar { + return fmt.Sprintf("%d", amount) + } + return arm64VectorIntegerSplat(sourceArrangement, amount) + } + zero := "zeroinitializer" + if scalar { + zero = "0" + } + emitShift := func(value string, amount int64, signed bool) string { + if amount >= int64(sourceArrangement.elementBits) && !signed { + return zero + } + if amount >= int64(sourceArrangement.elementBits) { + amount = int64(sourceArrangement.elementBits - 1) // ASR by the element width is the replicated sign bit. + } + result := c.newTmp() + operation := "lshr" + if signed { + operation = "ashr" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", result, operation, vectorType, value, shiftValue(amount)) + return "%" + result + } + result := emitShift(source, ins.Args[0].Imm, spec.signed) + if spec.rounding { + roundingBit := emitShift(source, ins.Args[0].Imm-1, false) + maskedBit := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", maskedBit, vectorType, roundingBit, shiftValue(1)) + rounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %%%s\n", rounded, vectorType, result, maskedBit) + result = "%" + rounded + } + if spec.accumulate { + destination, err := c.loadARM64VectorInteger(ins.Args[2].Reg, destinationArrangement) + if err != nil { + return true, false, err + } + if scalar { + extracted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i64> %s, i32 0\n", extracted, destination) + destination = "%" + extracted + } + accumulated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", accumulated, vectorType, destination, result) + result = "%" + accumulated + } + if scalar { + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i64> zeroinitializer, i64 %s, i32 0\n", inserted, result) + result = "%" + inserted + } + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, sourceArrangement, result) +} + +func (c *arm64Ctx) lowerARM64VectorIntegerCompare(op Op, ins Instr) (ok bool, terminated bool, err error) { + predicates := map[Op]string{ + "VCMEQ": "eq", + "VCMGE": "sge", + "VCMGT": "sgt", + "VCMLE": "sle", + "VCMLT": "slt", + "VCMHI": "ugt", + "VCMHS": "uge", + } + predicate, handled := predicates[op] + testBits := op == "VCMTST" + if !handled && !testBits { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects register compare or $0 compare form and no suffix: %q", op, ins.Raw) + } + zeroForm := ins.Args[0].Kind == OpImm + if testBits && (zeroForm || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg) { + return true, false, fmt.Errorf("arm64 VCMTST requires three vector registers: %q", ins.Raw) + } + if zeroForm { + if op == "VCMHI" || op == "VCMHS" || ins.Args[0].Imm != 0 || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s immediate compare requires exactly $0, Vsrc., Vdst.: %q", op, ins.Raw) + } + } else { + if op == "VCMLE" || op == "VCMLT" || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s register compare form is absent from Go 1.27's optab: %q", op, ins.Raw) + } + } + + sourceIndex := 1 + if !zeroForm { + sourceIndex = 0 + } + arrangement, valid := parseARM64VectorArrangement(ins.Args[sourceIndex].Reg) + allowed := func(a arm64VectorArrangement) bool { + return (a.elementBits == 8 && (a.lanes == 8 || a.lanes == 16)) || + (a.elementBits == 16 && (a.lanes == 4 || a.lanes == 8)) || + (a.elementBits == 32 && (a.lanes == 2 || a.lanes == 4)) || + (a.elementBits == 64 && a.lanes == 2) + } + if !valid || !allowed(arrangement) { + return true, false, fmt.Errorf("arm64 %s has invalid vector arrangement: %q", op, ins.Raw) + } + start := 1 + if !zeroForm { + start = 0 + } + for i := start; i < len(ins.Args); i++ { + parsed, ok := parseARM64VectorArrangement(ins.Args[i].Reg) + if !ok || parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + + left, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + right := "zeroinitializer" + if !zeroForm { + right, err = c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + } + compared := c.newTmp() + if testBits { + vectorType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, arrangement.elementBits) + masked := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", masked, vectorType, left, right) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %%%s, zeroinitializer\n", compared, vectorType, masked) + } else { + fmt.Fprintf(c.b, " %%%s = icmp %s <%d x i%d> %s, %s\n", compared, predicate, arrangement.lanes, arrangement.elementBits, left, right) + } + allBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext <%d x i1> %%%s to <%d x i%d>\n", allBits, arrangement.lanes, compared, arrangement.lanes, arrangement.elementBits) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, "%"+allBits) +} + +func (c *arm64Ctx) lowerARM64VectorLogical(op Op, ins Instr) (ok bool, terminated bool, err error) { + handled := false + for _, candidate := range []Op{"VAND", "VORR", "VEOR", "VBIC", "VORN", "VBSL", "VBIT", "VBIF", "VNOT"} { + if op == candidate { + handled = true + break + } + } + if !handled { + return false, false, nil + } + if op == "VNOT" { + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 VNOT expects source and destination B8/B16 vector registers and no suffix: %q", ins.Raw) + } + source, sourceValid := parseARM64VectorArrangement(ins.Args[0].Reg) + destination, destinationValid := parseARM64VectorArrangement(ins.Args[1].Reg) + if !sourceValid || !destinationValid || source != destination || source.elementBits != 8 || (source.lanes != 8 && source.lanes != 16) { + return true, false, fmt.Errorf("arm64 VNOT accepts matching B8 or B16 arrangements: %q", ins.Raw) + } + value, err := c.loadARM64VectorInteger(ins.Args[0].Reg, source) + if err != nil { + return true, false, err + } + vectorType := fmt.Sprintf("<%d x i8>", source.lanes) + ones := "<" + strings.TrimSuffix(strings.Repeat("i8 -1, ", source.lanes), ", ") + ">" + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, %s\n", result, vectorType, value, ones) + return true, false, c.storeARM64VectorInteger(ins.Args[1].Reg, destination, "%"+result) + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects three matching B8/B16 vector registers and no suffix: %q", op, ins.Raw) + } + var arrangement arm64VectorArrangement + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || parsed.elementBits != 8 || (parsed.lanes != 8 && parsed.lanes != 16) { + return true, false, fmt.Errorf("arm64 %s accepts only B8 or B16 arrangements: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + first, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + second, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + vectorType := fmt.Sprintf("<%d x i8>", arrangement.lanes) + result := "" + emitBinary := func(operation, left, right string) string { + name := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", name, operation, vectorType, left, right) + return "%" + name + } + emitNot := func(value string) string { + return emitBinary("xor", value, "<"+strings.TrimSuffix(strings.Repeat("i8 -1, ", arrangement.lanes), ", ")+">") + } + switch op { + case "VAND": + result = emitBinary("and", second, first) + case "VORR": + result = emitBinary("or", second, first) + case "VEOR": + result = emitBinary("xor", second, first) + case "VBIC": + result = emitBinary("and", second, emitNot(first)) + case "VORN": + result = emitBinary("or", second, emitNot(first)) + case "VBSL", "VBIT", "VBIF": + old, err := c.loadARM64VectorInteger(ins.Args[2].Reg, arrangement) + if err != nil { + return true, false, err + } + var mask, whenTrue, whenFalse string + switch op { + case "VBSL": + mask, whenTrue, whenFalse = old, second, first + case "VBIT": + mask, whenTrue, whenFalse = first, second, old + case "VBIF": + mask, whenTrue, whenFalse = first, old, second + } + selected := emitBinary("and", mask, whenTrue) + unselected := emitBinary("and", emitNot(mask), whenFalse) + result = emitBinary("or", selected, unselected) + } + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, result) +} + +func (c *arm64Ctx) lowerARM64VectorFloatWiden(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VFCVTL" && op != "VFCVTL2" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects Vsrc.S%d, Vdst.D2 and no suffix: %q", op, map[bool]int{false: 2, true: 4}[op == "VFCVTL2"], ins.Raw) + } + sourceArrangement, sourceValid := parseARM64VectorArrangement(ins.Args[0].Reg) + destinationArrangement, destinationValid := parseARM64VectorArrangement(ins.Args[1].Reg) + wantSourceLanes := 2 + if op == "VFCVTL2" { + wantSourceLanes = 4 + } + if !sourceValid || sourceArrangement.elementBits != 32 || sourceArrangement.lanes != wantSourceLanes || + !destinationValid || destinationArrangement.elementBits != 64 || destinationArrangement.lanes != 2 { + return true, false, fmt.Errorf("arm64 %s operand arrangements are outside Go 1.27's widening optab: %q", op, ins.Raw) + } + return true, false, c.lowerARM64VectorFloatWidenForm(32, op == "VFCVTL2", ins.Args[0].Reg, ins.Args[1].Reg) +} + +func (c *arm64Ctx) lowerARM64VectorFloatWidenForm(sourceBits int, upper bool, sourceReg, destinationReg Reg) error { + sourceBytes, err := c.loadVReg(sourceReg) + if err != nil { + return err + } + physicalLanes := 128 / sourceBits + selectedLanes := physicalLanes / 2 + sourceType, destinationType := "half", "float" + if sourceBits == 32 { + sourceType, destinationType = "float", "double" + } + all := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x %s>\n", all, sourceBytes, physicalLanes, sourceType) + firstLane := 0 + if upper { + firstLane = selectedLanes + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x %s> %%%s, <%d x %s> poison, <%d x i32> <", + selected, physicalLanes, sourceType, all, physicalLanes, sourceType, selectedLanes) + for lane := 0; lane < selectedLanes; lane++ { + if lane != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", firstLane+lane) + } + c.b.WriteString(">\n") + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fpext <%d x %s> %%%s to <%d x %s>\n", + converted, selectedLanes, sourceType, selected, selectedLanes, destinationType) + return c.storeARM64VectorFloat(destinationReg, + arm64VectorArrangement{elementBits: sourceBits * 2, lanes: selectedLanes}, "%"+converted) +} + +func (c *arm64Ctx) lowerARM64VectorFMA(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VFMLA" && op != "VFMLS" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects three same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + var arrangement arm64VectorArrangement + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + parsed, ok := parseARM64VectorArrangement(arg.Reg) + if !ok || !((parsed.elementBits == 32 && (parsed.lanes == 2 || parsed.lanes == 4)) || (parsed.elementBits == 64 && parsed.lanes == 2)) { + return true, false, fmt.Errorf("arm64 %s accepts only S2, S4, or D2 arrangements: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + + first, err := c.loadARM64VectorFloat(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + second, err := c.loadARM64VectorFloat(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + addend, err := c.loadARM64VectorFloat(ins.Args[2].Reg, arrangement) + if err != nil { + return true, false, err + } + floatType := "float" + if arrangement.elementBits == 64 { + floatType = "double" + } + if op == "VFMLS" { + negated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg <%d x %s> %s\n", negated, arrangement.lanes, floatType, first) + first = "%" + negated + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <%d x %s> @llvm.fma.v%d%s(<%d x %s> %s, <%d x %s> %s, <%d x %s> %s)\n", + result, arrangement.lanes, floatType, arrangement.lanes, map[int]string{32: "f32", 64: "f64"}[arrangement.elementBits], + arrangement.lanes, floatType, first, arrangement.lanes, floatType, second, arrangement.lanes, floatType, addend) + return true, false, c.storeARM64VectorFloat(ins.Args[2].Reg, arrangement, "%"+result) +} diff --git a/arm64_lower_float_vector_test.go b/arm64_lower_float_vector_test.go new file mode 100644 index 00000000..57416c55 --- /dev/null +++ b/arm64_lower_float_vector_test.go @@ -0,0 +1,703 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64VectorFMACompleteGoAssemblerForms(t *testing.T) { + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, ` +TEXT vectorfmaforms(SB),NOSPLIT,$0-0 + VFMLA V0.S2, V1.S2, V2.S2 + VFMLA V3.S4, V4.S4, V5.S4 + VFMLA V6.D2, V7.D2, V8.D2 + VFMLS V9.S2, V10.S2, V11.S2 + VFMLS V12.S4, V13.S4, V14.S4 + VFMLS V15.D2, V16.D2, V31.D2 + RET +`) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorfmaforms": {Name: "vectorfmaforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"@llvm.fma.v2f32", "@llvm.fma.v4f32", "@llvm.fma.v2f64"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 vector FMA for %s omitted %s:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-fma.ll", "arm64-vector-fma.o", ll) + } +} + +func TestTranslateARM64VectorFMARejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "VFMLA V0.S2, V1.S2", + "VFMLS V0.S2, V1.S2, V2.S2, V3.S2", + "VFMLA V0.D2, V1.D2, V2.S2", + "VFMLA V0.S2, V1.S4, V2.S2", + "VFMLS V0.B16, V1.B16, V2.B16", + "VFMLS V0.H8, V1.H8, V2.H8", + "VFMLA V0.S[0], V1.S2, V2.S2", + "VFMLA.P V0.S4, V1.S4, V2.S4", + } { + file, err := Parse(ArchARM64, "TEXT badvectorfma(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorfma": {Name: "badvectorfma", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VFMLA/VFMLS optab", instruction) + } + } +} + +func TestTranslateARM64VectorIntegerAddSubCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT vectorintegeraddsubforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VADD", "VSUB"} { + for i, arrangement := range []string{"B8", "B16", "H4", "H8", "S2", "S4", "D2"} { + src.WriteString("\t" + op + " V0." + arrangement + ", V1." + arrangement + ", V" + string(rune('2'+i)) + "." + arrangement + "\n") + } + src.WriteString("\t" + op + " V12, V30\n") + src.WriteString("\t" + op + " V12, V20, V31\n") + } + src.WriteString("\tRET\n") + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorintegeraddsubforms": {Name: "vectorintegeraddsubforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-integer-add-sub.ll", "arm64-vector-integer-add-sub.o", ll) + } +} + +func TestTranslateARM64VectorIntegerAddSubRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "VADD V0.B8, V1.B8", + "VSUB V0.B8, V1.B8, V2.B8, V3.B8", + "VADD V0.B8, V1.B16, V2.B8", + "VSUB V0.D1, V1.D1, V2.D1", + "VADD V0.F4, V1.F4, V2.F4", + "VSUB V0.S[0], V1.S2, V2.S2", + "VADD V0, V1, V2, V3", + "VSUB V0.S4, V1, V2.S4", + "VADD.P V0.S4, V1.S4, V2.S4", + } { + file, err := Parse(ArchARM64, "TEXT badvectorintegeraddsub(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorintegeraddsub": {Name: "badvectorintegeraddsub", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VADD/VSUB optab", instruction) + } + } +} + +func TestTranslateARM64AddAcrossCompleteGoAssemblerForms(t *testing.T) { + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, ` +TEXT addacrossforms(SB),NOSPLIT,$0-0 + VADDV V0.B8, V1 + VADDV V2.B16, V3 + VADDV V4.H4, V5 + VADDV V6.H8, V7 + VADDV V30.S4, V31 + RET +`) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "addacrossforms": {Name: "addacrossforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-add-across.ll", "arm64-add-across.o", ll) + } +} + +func TestTranslateARM64AddAcrossRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "VADDV V0.B8", + "VADDV V0.B8, V1, V2", + "VADDV V0.S2, V1", + "VADDV V0.D2, V1", + "VADDV V0.B16, V1.B16", + "VADDV V0, V1", + "VADDV.P V0.S4, V1", + } { + file, err := Parse(ArchARM64, "TEXT badaddacross(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badaddacross": {Name: "badaddacross", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VADDV optab", instruction) + } + } +} + +func TestTranslateARM64VectorFloatArithmeticCompleteGoAssemblerForms(t *testing.T) { + ops := []string{ + "VFADD", "VFSUB", "VFMUL", "VFDIV", + "VFMAX", "VFMAXNM", "VFMIN", "VFMINNM", + "VFADDP", "VFMAXP", "VFMAXNMP", "VFMINP", "VFMINNMP", + } + var src strings.Builder + src.WriteString("TEXT vectorfloatarithmeticforms(SB),NOSPLIT,$0-0\n") + for _, op := range ops { + for _, arrangement := range []string{"S2", "S4", "D2"} { + src.WriteString("\t" + op + " V0." + arrangement + ", V1." + arrangement + ", V31." + arrangement + "\n") + } + } + src.WriteString("\tRET\n") + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorfloatarithmeticforms": {Name: "vectorfloatarithmeticforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-float-arithmetic.ll", "arm64-vector-float-arithmetic.o", ll) + } +} + +func TestTranslateARM64VectorFloatArithmeticRejectsFormsOutsideGoOptab(t *testing.T) { + for _, op := range []string{ + "VFADD", "VFSUB", "VFMUL", "VFDIV", + "VFMAX", "VFMAXNM", "VFMIN", "VFMINNM", + "VFADDP", "VFMAXP", "VFMAXNMP", "VFMINP", "VFMINNMP", + } { + for _, operands := range []string{ + "V0.S4, V1.S4", + "V0.H4, V1.H4, V2.H4", + "V0.S2, V1.S4, V2.S2", + "V0.S[0], V1.S2, V2.S2", + } { + instruction := op + " " + operands + file, err := Parse(ArchARM64, "TEXT badvectorfloatarithmetic(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorfloatarithmetic": {Name: "badvectorfloatarithmetic", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector floating arithmetic optab", instruction) + } + } + } +} + +func TestTranslateARM64VectorFloatUnaryCompleteGoAssemblerForms(t *testing.T) { + ops := []string{ + "VFABS", "VFNEG", "VFSQRT", + "VFRINTN", "VFRINTP", "VFRINTM", "VFRINTZ", + "VFCVTZS", "VFCVTZU", "VSCVTF", "VUCVTF", + } + var src strings.Builder + src.WriteString("TEXT vectorfloatunaryforms(SB),NOSPLIT,$0-0\n") + for _, op := range ops { + for _, arrangement := range []string{"S2", "S4", "D2"} { + src.WriteString("\t" + op + " V0." + arrangement + ", V31." + arrangement + "\n") + } + } + src.WriteString("\tRET\n") + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorfloatunaryforms": {Name: "vectorfloatunaryforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-float-unary.ll", "arm64-vector-float-unary.o", ll) + } +} + +func TestTranslateARM64VectorFloatUnaryRejectsFormsOutsideGoOptab(t *testing.T) { + for _, op := range []string{ + "VFABS", "VFNEG", "VFSQRT", + "VFRINTN", "VFRINTP", "VFRINTM", "VFRINTZ", + "VFCVTZS", "VFCVTZU", "VSCVTF", "VUCVTF", + } { + for _, operands := range []string{ + "V0.S4", + "V0.H4, V1.H4", + "V0.S2, V1.S4", + "V0.S[0], V1.S2", + } { + instruction := op + " " + operands + file, err := Parse(ArchARM64, "TEXT badvectorfloatunary(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorfloatunary": {Name: "badvectorfloatunary", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector floating unary optab", instruction) + } + } + } +} + +func TestTranslateARM64VectorShiftRightCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT vectorshiftrightforms(SB),$0-0\n") + for _, form := range []struct { + arrangement string + width string + }{ + {arrangement: "B8", width: "8"}, + {arrangement: "B16", width: "8"}, + {arrangement: "H4", width: "16"}, + {arrangement: "H8", width: "16"}, + {arrangement: "S2", width: "32"}, + {arrangement: "S4", width: "32"}, + {arrangement: "D2", width: "64"}, + } { + for _, op := range []string{"VUSHR", "VSSHR", "VSRSHR", "VUSRA"} { + src.WriteString("\t" + op + " $1, V0." + form.arrangement + ", V1." + form.arrangement + "\n") + src.WriteString("\t" + op + " $" + form.width + ", V30." + form.arrangement + ", V31." + form.arrangement + "\n") + } + } + src.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, src.String(), true) + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorshiftrightforms": {Name: "vectorshiftrightforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-signed-shift-right.ll", "arm64-vector-signed-shift-right.o", ll) + } +} + +func TestTranslateARM64VectorShiftRightRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "VSSHR V0.S4, V1.S4", + "VSSHR $0, V0.S4, V1.S4", + "VSSHR $33, V0.S4, V1.S4", + "VUSHR $0, V0.B8, V1.B8", + "VSRSHR $65, V0.D2, V1.D2", + "VUSRA $17, V0.H8, V1.H8", + "VSSHR $9, V0.B16, V1.B16", + "VSSHR $1, V0.S2, V1.S4", + "VSSHR $1, V0.D1, V1.D1", + "VSSHR.P $1, V0.S4, V1.S4", + } { + source := "TEXT badvectorshiftright(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorshiftright": {Name: "badvectorshiftright", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector shift-right optab", instruction) + } + } +} + +func TestTranslateARM64VectorIntegerCompareCompleteGoAssemblerForms(t *testing.T) { + arrangements := []string{"B8", "B16", "H4", "H8", "S2", "S4", "D2"} + var src strings.Builder + src.WriteString("TEXT vectorintegercompareforms(SB),$0-0\n") + for _, op := range []string{"VCMEQ", "VCMGE", "VCMGT", "VCMHI", "VCMHS"} { + for _, arrangement := range arrangements { + src.WriteString("\t" + op + " V0." + arrangement + ", V1." + arrangement + ", V31." + arrangement + "\n") + } + } + for _, arrangement := range arrangements { + src.WriteString("\tVCMTST V0." + arrangement + ", V1." + arrangement + ", V31." + arrangement + "\n") + } + for _, op := range []string{"VCMEQ", "VCMGE", "VCMGT", "VCMLE", "VCMLT"} { + for _, arrangement := range arrangements { + src.WriteString("\t" + op + " $0, V30." + arrangement + ", V31." + arrangement + "\n") + } + } + src.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, src.String(), true) + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorintegercompareforms": {Name: "vectorintegercompareforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-integer-compare.ll", "arm64-vector-integer-compare.o", ll) + } +} + +func TestTranslateARM64VectorIntegerCompareRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "VCMEQ V0, V1, V2", + "VCMEQ V0.S4, V1.S4", + "VCMGE V0.S2, V1.S4, V2.S2", + "VCMGT V0.D1, V1.D1, V2.D1", + "VCMLE V0.S4, V1.S4, V2.S4", + "VCMLT V0.S4, V1.S4, V2.S4", + "VCMEQ $1, V0.S4, V1.S4", + "VCMGT $-1, V0.S4, V1.S4", + "VCMHI $0, V0.S4, V1.S4", + "VCMHS V0.S4, V1.S4", + "VCMLE $0, V0.S2, V1.S4", + "VCMLT.P $0, V0.S4, V1.S4", + "VCMTST V0.S4, V1.S4", + "VCMTST V0.S2, V1.S4, V2.S2", + "VCMTST $0, V0.S4, V1.S4", + } { + source := "TEXT badvectorintegercompare(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorintegercompare": {Name: "badvectorintegercompare", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector integer compare optab", instruction) + } + } +} + +func TestARM64VectorTestBitsRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectortestbits(SB),$0-24 + MOVD first+0(FP), R0 + MOVD second+8(FP), R1 + MOVD output+16(FP), R2 + VLD1 (R0), [V0.B16] + VLD1 (R1), [V1.B16] + VCMTST V0.B16, V1.B16, V2.B16 + VCMTST V0.H8, V1.H8, V3.H8 + VCMTST V0.S4, V1.S4, V4.S4 + VCMTST V0.D2, V1.D2, V5.D2 + VST1 [V2.B16, V3.B16, V4.B16, V5.B16], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"vectortestbits": { + Name: "vectortestbits", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void vectortestbits(const uint8_t *, const uint8_t *, uint8_t *); +int main(void) { + const uint8_t first[16] = {1,2,4,8, 1,2,4,8, 1,2,4,8, 1,2,4,8}; + const uint8_t second[16] = {1,1,1,1, 2,2,2,2, 4,4,4,4, 8,8,8,8}; + uint8_t got[64] = {0}; + uint8_t want[64] = {0}; + vectortestbits(first, second, got); + for (int lane = 0; lane < 16; lane++) want[lane] = (first[lane] & second[lane]) ? 255 : 0; + for (int width = 2; width <= 8; width *= 2) { + int block = width == 2 ? 16 : width == 4 ? 32 : 48; + for (int lane = 0; lane < 16 / width; lane++) { + int nonzero = 0; + for (int byte = 0; byte < width; byte++) nonzero |= first[lane * width + byte] & second[lane * width + byte]; + memset(want + block + lane * width, nonzero ? 255 : 0, width); + } + } + for (int i = 0; i < 64; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_test_bits", triple, ir, mainC, nil) +} + +func TestTranslateARM64VectorLogicalCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT vectorlogicalforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"VAND", "VORR", "VEOR", "VBIC", "VORN", "VBSL", "VBIT", "VBIF"} { + for _, arrangement := range []string{"B8", "B16"} { + src.WriteString("\t" + op + " V0." + arrangement + ", V1." + arrangement + ", V31." + arrangement + "\n") + } + } + src.WriteString("\tRET\n") + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorlogicalforms": {Name: "vectorlogicalforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-logical.ll", "arm64-vector-logical.o", ll) + } +} + +func TestTranslateARM64VectorLogicalRejectsFormsOutsideGoOptab(t *testing.T) { + for _, op := range []string{"VAND", "VORR", "VEOR", "VBIC", "VORN", "VBSL", "VBIT", "VBIF"} { + for _, operands := range []string{ + "V0.B16, V1.B16", + "V0.H8, V1.H8, V2.H8", + "V0.B8, V1.B16, V2.B8", + "V0, V1, V2", + } { + instruction := op + " " + operands + file, err := Parse(ArchARM64, "TEXT badvectorlogical(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorlogical": {Name: "badvectorlogical", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector logical optab", instruction) + } + } + } +} + +func TestTranslateARM64VectorFloatWidenCompleteGoAssemblerForms(t *testing.T) { + const source = ` +TEXT vectorfloatwidenforms(SB),$0-0 + VFCVTL V0.S2, V31.D2 + VFCVTL2 V30.S4, V1.D2 + RET +` + requireARM64GoAssemblerResult(t, source, true) + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorfloatwidenforms": {Name: "vectorfloatwidenforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, "fpext <2 x float>") { + t.Fatalf("ARM64 VFCVTL family omitted vector fpext:\n%s", ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-float-widen.ll", "arm64-vector-float-widen.o", ll) + } +} + +func TestTranslateARM64VectorFloatWidenRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "VFCVTL V0.S2", + "VFCVTL V0.S4, V1.D2", + "VFCVTL2 V0.S2, V1.D2", + "VFCVTL V0.H4, V1.S4", + "VFCVTL2 V0.S4, V1.S4", + "VFCVTL.P V0.S2, V1.D2", + } { + file, err := Parse(ArchARM64, "TEXT badvectorfloatwiden(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorfloatwiden": {Name: "badvectorfloatwiden", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VFCVTL/VFCVTL2 optab", instruction) + } + } +} diff --git a/arm64_lower_float_widen_raw.go b/arm64_lower_float_widen_raw.go new file mode 100644 index 00000000..c2443d31 --- /dev/null +++ b/arm64_lower_float_widen_raw.go @@ -0,0 +1,31 @@ +package plan9asm + +import "fmt" + +type arm64RawVectorFloatWiden struct { + sourceBits int + upper bool + source int + destination int +} + +func decodeARM64RawVectorFloatWiden(word uint32) (arm64RawVectorFloatWiden, bool) { + if word&0xbfbffc00 != 0x0e217800 { + return arm64RawVectorFloatWiden{}, false + } + sourceBits := 16 + if word&(1<<22) != 0 { + sourceBits = 32 + } + return arm64RawVectorFloatWiden{ + sourceBits: sourceBits, + upper: word&(1<<30) != 0, + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawVectorFloatWiden(form arm64RawVectorFloatWiden) error { + return c.lowerARM64VectorFloatWidenForm(form.sourceBits, form.upper, + Reg(fmt.Sprintf("V%d", form.source)), Reg(fmt.Sprintf("V%d", form.destination))) +} diff --git a/arm64_lower_float_widen_raw_test.go b/arm64_lower_float_widen_raw_test.go new file mode 100644 index 00000000..4604ca19 --- /dev/null +++ b/arm64_lower_float_widen_raw_test.go @@ -0,0 +1,116 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64RawVectorFloatWidenCompleteBaseFormats(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawvectorfloatwidenforms(SB),$0-0\n") + for _, size := range []uint32{0, 1 << 22} { // 4H -> 4S and 2S -> 2D. + for _, upper := range []uint32{0, 1 << 30} { // FCVTL and FCVTL2. + fmt.Fprintf(&source, "\tWORD $%#08x\n", uint32(0x0e217800)|size|upper|30<<5|29) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawvectorfloatwidenforms": {Name: "rawvectorfloatwidenforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"fpext <4 x half>", "fpext <2 x float>"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw floating widen omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-vector-float-widen.ll", "arm64-raw-vector-float-widen.o", ir) + }) + } +} + +func TestARM64RawVectorFloatWidenDecoderRejectsAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x2e217800, // U bit is unallocated for FCVTL. + 0x0ea17800, // Unallocated size. + 0x0e216800, // FCVTN, not FCVTL. + 0x0e217c00, // Adjacent opcode. + } { + if _, ok := decodeARM64RawVectorFloatWiden(word); ok { + t.Fatalf("floating widen decoder accepted adjacent encoding %#08x", word) + } + } +} + +func TestARM64RawVectorFloatWidenRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawvectorfloatwiden(SB),$0-16 + MOVD input+0(FP), R0 + MOVD output+8(FP), R1 + ADD $16, R1, R2 + VLD1 (R0), [V1.H8] + WORD $0x0e217822 // FCVTL V1.4H, V2.4S + VST1 [V2.S4], (R1) + WORD $0x4e217823 // FCVTL2 V1.8H, V3.4S + VST1 [V3.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawvectorfloatwiden": { + Name: "rawvectorfloatwiden", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawvectorfloatwiden(const uint16_t *, uint32_t *); +int main(void) { + const uint16_t input[8] = {0x3c00,0xc000,0x3800,0x7bff, 0x8000,0x7c00,0xfc00,0x3400}; + const uint32_t want[8] = {0x3f800000,0xc0000000,0x3f000000,0x477fe000, 0x80000000,0x7f800000,0xff800000,0x3e800000}; + uint32_t got[8] = {0}; + rawvectorfloatwiden(input, got); + for (int i = 0; i < 8; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_vector_float_widen", triple, ir, mainC, nil) +} diff --git a/arm64_lower_fma_test.go b/arm64_lower_fma_test.go new file mode 100644 index 00000000..1916f813 --- /dev/null +++ b/arm64_lower_fma_test.go @@ -0,0 +1,77 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64FusedMultiplyAddCompleteGoAssemblerForms(t *testing.T) { + const source = `TEXT fusedmultiplyaddforms(SB),NOSPLIT,$0-0 + FMADDS F0, F1, F2, F3 + FMADDD F4, F5, F6, F7 + FMSUBS F8, F9, F10, F11 + FMSUBD F12, F13, F14, F15 + FNMADDS F16, F17, F18, F19 + FNMADDD F20, F21, F22, F23 + FNMSUBS F24, F25, F26, F27 + FNMSUBD F28, F29, F30, F31 + RET +` + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-arm64", triple: "arm64-apple-darwin"}, + {name: "linux-arm64", triple: "aarch64-unknown-linux-gnu"}, + {name: "windows-arm64", triple: "aarch64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "fusedmultiplyaddforms": {Name: "fusedmultiplyaddforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "arm64-fused-multiply-add-"+target.name+".ll", "arm64-fused-multiply-add-"+target.name+".o", ll) + }) + } +} + +func TestTranslateARM64FusedMultiplyAddRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "FMADDS F0, F1, F2", + "FMADDD F0, F1, F2, F3, F4", + "FMSUBS 8(R0), F1, F2, F3", + "FMSUBD F0, R1, F2, F3", + "FNMADDS F0, F1, V2, F3", + "FNMADDD F0, F1, F2, R3", + "FNMSUBS.P F0, F1, F2, F3", + "FNMSUBD F32, F1, F2, F3", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchARM64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 fused multiply-add table", instruction) + } + }) + } +} diff --git a/arm64_lower_fmov.go b/arm64_lower_fmov.go new file mode 100644 index 00000000..7c720ed4 --- /dev/null +++ b/arm64_lower_fmov.go @@ -0,0 +1,209 @@ +package plan9asm + +import ( + "fmt" + "math" + "strconv" + "strings" +) + +// lowerScalarFloatMove implements the full Go 1.27 FMOVS/FMOVD shape family: +// floating constants, F<->F, general/zero-register<->F, and F<->memory for +// stack, symbol, immediate-offset, register-offset, post-index, and pre-index +// addresses. +func (c *arm64Ctx) lowerScalarFloatMove(op Op, ins Instr) (ok bool, terminated bool, err error) { + bits := 64 + switch op { + case "FMOVB": + bits = 8 + case "FMOVH": + bits = 16 + case "FMOVS": + bits = 32 + } + rawOp := strings.ToUpper(string(ins.Op)) + postIndex := false + preIndex := false + switch rawOp { + case string(op): + case string(op) + ".P": + postIndex = true + case string(op) + ".W": + preIndex = true + default: + return true, false, fmt.Errorf("arm64 %s accepts only .P or .W memory suffixes: %q", op, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects exactly 2 operands: %q", op, ins.Raw) + } + src, dst := ins.Args[0], ins.Args[1] + srcF := src.Kind == OpReg && isARM64FReg(src.Reg) + dstF := dst.Kind == OpReg && isARM64FReg(dst.Reg) + srcGP := src.Kind == OpReg && isARM64GeneralOrZeroReg(src.Reg) + dstGP := dst.Kind == OpReg && isARM64GeneralOrZeroReg(dst.Reg) + srcMem := isARM64ScalarFloatMemory(src) + dstMem := isARM64ScalarFloatMemory(dst) + + valid := false + switch { + case src.Kind == OpImm: + valid = dstF + case srcF: + valid = dstF || dstGP || dstMem + case srcGP: + valid = dstF + case srcMem: + valid = dstF + } + if !valid { + return true, false, fmt.Errorf("arm64 %s operands are absent from the Go 1.27 optab: %q", op, ins.Raw) + } + + indexedMemory := Operand{} + if src.Kind == OpMem { + indexedMemory = src + } else if dst.Kind == OpMem { + indexedMemory = dst + } + if postIndex || preIndex { + if indexedMemory.Kind != OpMem || indexedMemory.Mem.Index != "" { + return true, false, fmt.Errorf("arm64 %s .P/.W requires one immediate-offset register memory operand: %q", op, ins.Raw) + } + } + + var value string + switch { + case src.Kind == OpImm: + value, err = arm64FloatImmediateBits(src, bits) + case srcF || srcGP: + value, err = c.loadReg(src.Reg) + case srcMem: + value, err = c.loadScalarFloatMemory(src, bits, postIndex, preIndex) + } + if err != nil { + return true, false, err + } + value = c.normalizeScalarFloatBits(value, bits) + + switch { + case dstF || dstGP: + err = c.storeReg(dst.Reg, value) + case dstMem: + err = c.storeScalarFloatMemory(dst, bits, postIndex, preIndex, value) + } + return true, false, err +} + +func isARM64FReg(r Reg) bool { + _, ok := arm64ParseFReg(r) + return ok +} + +func isARM64GeneralOrZeroReg(r Reg) bool { + if r == ZR { + return true + } + s := strings.ToUpper(strings.TrimSpace(string(r))) + if !strings.HasPrefix(s, "R") { + return false + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "R")) + return err == nil && n >= 0 && n <= 30 +} + +func isARM64ScalarFloatMemory(op Operand) bool { + switch op.Kind { + case OpFP, OpMem, OpSym: + return op.Kind != OpSym || !strings.HasPrefix(strings.TrimSpace(op.Sym), "$") + default: + return false + } +} + +func arm64FloatImmediateBits(op Operand, bits int) (string, error) { + if op.ImmRaw != "" { + return "", fmt.Errorf("arm64: unresolved floating immediate %s", op.String()) + } + if op.Imm == 0 { + return "0", nil + } + value := math.Float64frombits(uint64(op.Imm)) + if bits == 32 { + return strconv.FormatUint(uint64(math.Float32bits(float32(value))), 10), nil + } + return strconv.FormatUint(uint64(op.Imm), 10), nil +} + +func (c *arm64Ctx) normalizeScalarFloatBits(value string, bits int) string { + if bits == 64 { + return value + } + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrow, value, bits) + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i%d %%%s to i64\n", wide, bits, narrow) + return "%" + wide +} + +func (c *arm64Ctx) loadScalarFloatMemory(op Operand, bits int, postIndex, preIndex bool) (string, error) { + switch op.Kind { + case OpFP: + return c.evalFPValue64(op) + case OpSym: + ptr, err := c.ptrFromSB(op.Sym) + if err != nil { + return "", err + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i%d, ptr %s, align 1\n", loaded, bits, ptr) + if bits == 64 { + return "%" + loaded, nil + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i%d %%%s to i64\n", wide, bits, loaded) + return "%" + wide, nil + case OpMem: + value, err := c.loadMem(op.Mem, bits, postIndex) + if err != nil { + return "", err + } + if preIndex { + if err := c.updatePostInc(op.Mem.Base, op.Mem.Off); err != nil { + return "", err + } + } + return value, nil + default: + return "", fmt.Errorf("arm64: unsupported scalar floating load %s", op.String()) + } +} + +func (c *arm64Ctx) storeScalarFloatMemory(op Operand, bits int, postIndex, preIndex bool, value string) error { + switch op.Kind { + case OpFP: + return c.storeFPResult64(op.FPOffset, value) + case OpSym: + ptr, err := c.ptrFromSB(op.Sym) + if err != nil { + return err + } + if bits == 64 { + fmt.Fprintf(c.b, " store i64 %s, ptr %s, align 1\n", value, ptr) + return nil + } + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrow, value, bits) + fmt.Fprintf(c.b, " store i%d %%%s, ptr %s, align 1\n", bits, narrow, ptr) + return nil + case OpMem: + if err := c.storeMem(op.Mem, bits, postIndex, value); err != nil { + return err + } + if preIndex { + return c.updatePostInc(op.Mem.Base, op.Mem.Off) + } + return nil + default: + return fmt.Errorf("arm64: unsupported scalar floating store %s", op.String()) + } +} diff --git a/arm64_lower_fmovq.go b/arm64_lower_fmovq.go new file mode 100644 index 00000000..5a5f7394 --- /dev/null +++ b/arm64_lower_fmovq.go @@ -0,0 +1,68 @@ +package plan9asm + +import "fmt" + +// loadFMOVQFrame reconstructs the 16 contiguous bytes addressed by off(FP) +// from the scalar LLVM fields used to model Go aggregate parameters. +func (c *arm64Ctx) loadFMOVQFrame(off int64) (string, error) { + packed := "0" + for cursor := off; cursor < off+16; { + slot, ok := c.fpParams[cursor] + if !ok { + return "", fmt.Errorf("arm64: FMOVQ input frame range +%d(FP)..+%d(FP) has no slot at +%d(FP)", off, off+16, cursor) + } + size := frameTypeSize(slot.Type, 8) + if size <= 0 || size > 8 || cursor+size > off+16 { + return "", fmt.Errorf("arm64: FMOVQ input frame slot +%d(FP) has unsupported type %q", cursor, slot.Type) + } + value, err := c.evalFPValue64(Operand{Kind: OpFP, FPOffset: cursor}) + if err != nil { + return "", err + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i64 %s to i128\n", wide, value) + part := "%" + wide + if shift := (cursor - off) * 8; shift != 0 { + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i128 %s, %d\n", shifted, part, shift) + part = "%" + shifted + } + merged := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i128 %s, %s\n", merged, packed, part) + packed = "%" + merged + cursor += size + } + vector := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i128 %s to <16 x i8>\n", vector, packed) + return "%" + vector, nil +} + +// storeFMOVQFrame splits a vector into the scalar LLVM result slots that cover +// the 16 contiguous bytes addressed by off(FP). +func (c *arm64Ctx) storeFMOVQFrame(off int64, value string) error { + packed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to i128\n", packed, value) + for cursor := off; cursor < off+16; { + slot, ok := c.fpResultSlotByOffset(cursor) + if !ok { + return fmt.Errorf("arm64: FMOVQ output frame range +%d(FP)..+%d(FP) has no slot at +%d(FP)", off, off+16, cursor) + } + size := frameTypeSize(slot.Type, 8) + if size <= 0 || size > 8 || cursor+size > off+16 { + return fmt.Errorf("arm64: FMOVQ output frame slot +%d(FP) has unsupported type %q", cursor, slot.Type) + } + part := "%" + packed + if shift := (cursor - off) * 8; shift != 0 { + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i128 %s, %d\n", shifted, part, shift) + part = "%" + shifted + } + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i128 %s to i64\n", narrow, part) + if err := c.storeFPResult64(cursor, "%"+narrow); err != nil { + return err + } + cursor += size + } + return nil +} diff --git a/arm64_lower_fmovq_frame_test.go b/arm64_lower_fmovq_frame_test.go new file mode 100644 index 00000000..1baa028d --- /dev/null +++ b/arm64_lower_fmovq_frame_test.go @@ -0,0 +1,93 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64FMOVQCompleteFPFrameForms(t *testing.T) { + tests := []struct { + name string + source string + sig FuncSig + loads int + stores int + }{ + { + name: "two uint64 lanes", + source: `TEXT fmovqwords(SB),$0-32 + FMOVQ value+0(FP), F0 + FMOVQ F0, ret+16(FP) + RET +`, + sig: FuncSig{ + Name: "fmovqwords", Args: []LLVMType{"[2 x i64]"}, Ret: LLVMType("{ i64, i64 }"), + Frame: FrameLayout{ + Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: 0, Fields: []int{0}}, + {Offset: 8, Type: I64, Index: 0, Field: 1, Fields: []int{1}}, + }, + Results: []FrameSlot{ + {Offset: 16, Type: I64, Index: 0, Field: -1}, + {Offset: 24, Type: I64, Index: 1, Field: -1}, + }, + }, + }, + loads: 2, stores: 2, + }, + { + name: "four float32 lanes", + source: `TEXT fmovqfloats(SB),$0-32 + FMOVQ value+0(FP), F1 + FMOVQ F1, ret+16(FP) + RET +`, + sig: FuncSig{ + Name: "fmovqfloats", Args: []LLVMType{"[4 x float]"}, Ret: LLVMType("{ float, float, float, float }"), + Frame: FrameLayout{ + Params: []FrameSlot{ + {Offset: 0, Type: LLVMType("float"), Index: 0, Field: 0, Fields: []int{0}}, + {Offset: 4, Type: LLVMType("float"), Index: 0, Field: 1, Fields: []int{1}}, + {Offset: 8, Type: LLVMType("float"), Index: 0, Field: 2, Fields: []int{2}}, + {Offset: 12, Type: LLVMType("float"), Index: 0, Field: 3, Fields: []int{3}}, + }, + Results: []FrameSlot{ + {Offset: 16, Type: LLVMType("float"), Index: 0, Field: -1}, + {Offset: 20, Type: LLVMType("float"), Index: 1, Field: -1}, + {Offset: 24, Type: LLVMType("float"), Index: 2, Field: -1}, + {Offset: 28, Type: LLVMType("float"), Index: 3, Field: -1}, + }, + }, + }, + loads: 4, stores: 4, + }, + } + + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + requireARM64GoAssemblerResult(t, test.source, true) + file, err := Parse(ArchARM64, test.source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "arm64", TargetTriple: "aarch64-unknown-linux-gnu", + Sigs: map[string]FuncSig{test.sig.Name: test.sig}, + }) + if err != nil { + t.Fatal(err) + } + if got := strings.Count(ir, "extractvalue"); got < test.loads { + t.Fatalf("FMOVQ frame load emitted %d extractvalue operations, want at least %d:\n%s", got, test.loads, ir) + } + if got := strings.Count(ir, "store "); got < test.stores { + t.Fatalf("FMOVQ frame store emitted %d stores, want at least %d:\n%s", got, test.stores, ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "aarch64-unknown-linux-gnu", "arm64-fmovq-frame.ll", "arm64-fmovq-frame.o", ir) + }) + } +} diff --git a/arm64_lower_fpops.go b/arm64_lower_fpops.go index 485d41a8..05f42488 100644 --- a/arm64_lower_fpops.go +++ b/arm64_lower_fpops.go @@ -7,252 +7,291 @@ import ( "strings" ) +func (c *arm64Ctx) lowerARM64ScalarFloatUnary(op Op, ins Instr) (ok bool, terminated bool, err error) { + operations := map[Op]string{ + "FABSS": "fabs", "FABSD": "fabs", + "FNEGS": "neg", "FNEGD": "neg", + "FSQRTS": "sqrt", "FSQRTD": "sqrt", + "FRINTNS": "roundeven", "FRINTND": "roundeven", + "FRINTPS": "ceil", "FRINTPD": "ceil", + "FRINTMS": "floor", "FRINTMD": "floor", + "FRINTZS": "trunc", "FRINTZD": "trunc", + "FRINTAS": "round", "FRINTAD": "round", + "FRINTXS": "rint", "FRINTXD": "rint", + "FRINTIS": "nearbyint", "FRINTID": "nearbyint", + } + operation, handled := operations[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || + ins.Args[0].Kind != OpReg || !isARM64FReg(ins.Args[0].Reg) || + ins.Args[1].Kind != OpReg || !isARM64FReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm64 %s expects Fsrc, Fdst and no suffix: %q", op, ins.Raw) + } + bits := 64 + floatType := "double" + intrinsicSuffix := "f64" + if strings.HasSuffix(string(op), "S") { + bits = 32 + floatType = "float" + intrinsicSuffix = "f32" + } + source, err := c.loadARM64ScalarFloatReg(ins.Args[0].Reg, bits) + if err != nil { + return true, false, err + } + result := c.newTmp() + if operation == "neg" { + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", result, floatType, source) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.%s(%s %s)\n", result, floatType, operation, intrinsicSuffix, floatType, source) + } + return true, false, c.storeARM64ScalarFloatReg(ins.Args[1].Reg, bits, "%"+result) +} + func (c *arm64Ctx) lowerFP(op Op, ins Instr) (ok bool, terminated bool, err error) { + if ok, terminated, err := c.lowerARM64ScalarFloatCompare(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64FloatConditionalCompare(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64ScalarFloatBinary(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64ScalarFloatUnary(op, ins); ok { + return ok, terminated, err + } switch op { - case "FMOVD": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("arm64 FMOVD expects 2 operands: %q", ins.Raw) - } - bits, err := c.evalFMOVDBits(ins.Args[0]) - if err != nil { - return true, false, err - } - switch ins.Args[1].Kind { - case OpReg: - return true, false, c.storeReg(ins.Args[1].Reg, bits) - case OpFP: - return true, false, c.storeFPResult64(ins.Args[1].FPOffset, bits) - default: - return true, false, fmt.Errorf("arm64 FMOVD unsupported dst: %q", ins.Raw) - } + case "FMOVB", "FMOVH", "FMOVS", "FMOVD": + return c.lowerScalarFloatMove(op, ins) - case "FCMPD": - // FCMPD src, dst => compare dst ? src (same operand order convention as CMP/SUB). - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("arm64 FCMPD expects 2 operands: %q", ins.Raw) - } - src, err := c.evalF64(ins.Args[0]) - if err != nil { - return true, false, err - } - dst, err := c.evalF64(ins.Args[1]) + case "FCVTSD", "FCVTDS", "FCVTSH", "FCVTHS", "FCVTDH", "FCVTHD": + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || + ins.Args[0].Kind != OpReg || !isARM64FReg(ins.Args[0].Reg) || + ins.Args[1].Kind != OpReg || !isARM64FReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm64 %s expects Fsrc, Fdst and no suffix: %q", op, ins.Raw) + } + conversionWidths := map[Op][2]int{ + "FCVTSD": {32, 64}, + "FCVTDS": {64, 32}, + "FCVTSH": {32, 16}, + "FCVTHS": {16, 32}, + "FCVTDH": {64, 16}, + "FCVTHD": {16, 64}, + } + sourceBits := conversionWidths[op][0] + destinationBits := conversionWidths[op][1] + source, err := c.loadARM64ScalarFloatReg(ins.Args[0].Reg, sourceBits) if err != nil { return true, false, err } - eq := c.newTmp() - lt := c.newTmp() - gt := c.newTmp() - uno := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fcmp oeq double %s, %s\n", eq, dst, src) - fmt.Fprintf(c.b, " %%%s = fcmp olt double %s, %s\n", lt, dst, src) - fmt.Fprintf(c.b, " %%%s = fcmp ogt double %s, %s\n", gt, dst, src) - fmt.Fprintf(c.b, " %%%s = fcmp uno double %s, %s\n", uno, dst, src) - // AArch64 FCMP flags model: - // - unordered: N=0 Z=0 C=1 V=1 - // - lt: N=1 Z=0 C=0 V=0 - // - eq: N=0 Z=1 C=1 V=0 - // - gt: N=0 Z=0 C=1 V=0 - c01 := c.newTmp() - cf := c.newTmp() - fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", c01, gt, eq) - fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %%%s\n", cf, c01, uno) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", lt, c.flagsNSlot) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", eq, c.flagsZSlot) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", cf, c.flagsCSlot) - fmt.Fprintf(c.b, " store i1 %%%s, ptr %s\n", uno, c.flagsVSlot) - c.flagsWritten = true - return true, false, nil - - case "FCSELD": - // FCSELD cond, a, b, dst - if len(ins.Args) != 4 || ins.Args[0].Kind != OpIdent { - return true, false, fmt.Errorf("arm64 FCSELD expects cond, a, b, dst: %q", ins.Raw) + converted := c.newTmp() + llvmFloatType := func(bits int) string { + switch bits { + case 16: + return "half" + case 32: + return "float" + default: + return "double" + } } - a, err := c.evalF64(ins.Args[1]) - if err != nil { - return true, false, err + sourceType := llvmFloatType(sourceBits) + destinationType := llvmFloatType(destinationBits) + if sourceBits < destinationBits { + fmt.Fprintf(c.b, " %%%s = fpext %s %s to %s\n", converted, sourceType, source, destinationType) + } else { + fmt.Fprintf(c.b, " %%%s = fptrunc %s %s to %s\n", converted, sourceType, source, destinationType) } - bv, err := c.evalF64(ins.Args[2]) - if err != nil { - return true, false, err + return true, false, c.storeARM64ScalarFloatReg(ins.Args[1].Reg, destinationBits, "%"+converted) + + case "FCSELS", "FCSELD": + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects condition, Fsrc, Fsrc, Fdst and no suffix: %q", op, ins.Raw) } - cv, err := c.condValue(ins.Args[0].Ident) - if err != nil { - return true, false, err + condition, conditionOK := arm64ConditionOperand(ins.Args[0]) + if !conditionOK { + return true, false, fmt.Errorf("arm64 %s expects a condition operand: %q", op, ins.Raw) } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %s, double %s, double %s\n", t, cv, a, bv) - return true, false, c.storeF64(ins.Args[3], "%"+t) - - case "FADDD", "FSUBD", "FMULD", "FDIVD", "FMAXD", "FMIND": - var src, dst string - var dstOp Operand - switch len(ins.Args) { - case 2: - src, err = c.evalF64(ins.Args[0]) - if err != nil { - return true, false, err + for _, operand := range ins.Args[1:] { + if operand.Kind != OpReg || !isARM64FReg(operand.Reg) { + return true, false, fmt.Errorf("arm64 %s accepts only scalar floating registers: %q", op, ins.Raw) } - dst, err = c.evalF64(ins.Args[1]) - if err != nil { - return true, false, err - } - dstOp = ins.Args[1] - case 3: - src, err = c.evalF64(ins.Args[0]) - if err != nil { - return true, false, err - } - dst, err = c.evalF64(ins.Args[1]) - if err != nil { - return true, false, err - } - dstOp = ins.Args[2] - default: - return true, false, fmt.Errorf("arm64 %s expects 2 or 3 operands: %q", op, ins.Raw) } - t := c.newTmp() - switch op { - case "FADDD": - fmt.Fprintf(c.b, " %%%s = fadd double %s, %s\n", t, dst, src) - case "FSUBD": - fmt.Fprintf(c.b, " %%%s = fsub double %s, %s\n", t, dst, src) - case "FMULD": - fmt.Fprintf(c.b, " %%%s = fmul double %s, %s\n", t, dst, src) - case "FDIVD": - fmt.Fprintf(c.b, " %%%s = fdiv double %s, %s\n", t, dst, src) - case "FMAXD": - fmt.Fprintf(c.b, " %%%s = call double @llvm.maxnum.f64(double %s, double %s)\n", t, dst, src) - case "FMIND": - fmt.Fprintf(c.b, " %%%s = call double @llvm.minnum.f64(double %s, double %s)\n", t, dst, src) - } - return true, false, c.storeF64(dstOp, "%"+t) - - case "FMADDD", "FMSUBD", "FNMSUBD": - // {FMA,FMSUB,FNMSUB}D a, b, c, dst - if len(ins.Args) != 4 { - return true, false, fmt.Errorf("arm64 %s expects 4 operands: %q", op, ins.Raw) + bits := 32 + typeName := "float" + if op == "FCSELD" { + bits = 64 + typeName = "double" } - a, err := c.evalF64(ins.Args[0]) + first, err := c.loadARM64ScalarFloatReg(ins.Args[1].Reg, bits) if err != nil { return true, false, err } - b, err := c.evalF64(ins.Args[1]) + second, err := c.loadARM64ScalarFloatReg(ins.Args[2].Reg, bits) if err != nil { return true, false, err } - cv, err := c.evalF64(ins.Args[2]) + predicate, err := c.condValue(condition) if err != nil { return true, false, err } - m := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fmul double %s, %s\n", m, a, cv) - t := c.newTmp() - switch op { - case "FMADDD": - // b + a*c - fmt.Fprintf(c.b, " %%%s = fadd double %s, %%%s\n", t, b, m) - case "FMSUBD": - // b - a*c - fmt.Fprintf(c.b, " %%%s = fsub double %s, %%%s\n", t, b, m) - case "FNMSUBD": - // a*c - b - fmt.Fprintf(c.b, " %%%s = fsub double %%%s, %s\n", t, m, b) - } - return true, false, c.storeF64(ins.Args[3], "%"+t) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, %s %s, %s %s\n", selected, predicate, typeName, first, typeName, second) + return true, false, c.storeARM64ScalarFloatReg(ins.Args[3].Reg, bits, "%"+selected) - case "FNMULD": - // FNMULD src, dst (or src1, src2, dst): dst = -(dst*src) or -(src2*src1). - var src, dst string - var dstOp Operand - switch len(ins.Args) { - case 2: - src, err = c.evalF64(ins.Args[0]) - if err != nil { - return true, false, err - } - dst, err = c.evalF64(ins.Args[1]) - if err != nil { - return true, false, err - } - dstOp = ins.Args[1] - case 3: - src, err = c.evalF64(ins.Args[0]) - if err != nil { - return true, false, err - } - dst, err = c.evalF64(ins.Args[1]) - if err != nil { - return true, false, err - } - dstOp = ins.Args[2] - default: - return true, false, fmt.Errorf("arm64 FNMULD expects 2 or 3 operands: %q", ins.Raw) - } - m := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fmul double %s, %s\n", m, dst, src) - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fneg double %%%s\n", t, m) - return true, false, c.storeF64(dstOp, "%"+t) + case "FMADDS", "FMADDD", "FMSUBS", "FMSUBD", + "FNMADDS", "FNMADDD", "FNMSUBS", "FNMSUBD": + return c.lowerFusedMultiplyAdd(op, ins) - case "FABSD": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("arm64 FABSD expects 2 operands: %q", ins.Raw) - } - src, err := c.evalF64(ins.Args[0]) + case "FCVTZSD", "FCVTZSDW", "FCVTZSS", "FCVTZSSW", + "FCVTZUD", "FCVTZUDW", "FCVTZUS", "FCVTZUSW": + // Go 1.27 exposes the complete scalar FCVT-to-integer family through + // AFCVTZSD's single C_FREG -> C_ZREG optab row. The final W selects a + // 32-bit integer result; S/D before it selects the floating input width. + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || + ins.Args[0].Kind != OpReg || !isARM64FReg(ins.Args[0].Reg) || + ins.Args[1].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm64 %s expects Fsrc, Rdst/ZR and no suffix: %q", op, ins.Raw) + } + sourceBits := 64 + floatType := "double" + floatSuffix := "f64" + sourceMnemonic := strings.TrimSuffix(string(op), "W") + if strings.HasSuffix(sourceMnemonic, "S") { + sourceBits = 32 + floatType = "float" + floatSuffix = "f32" + } + src, err := c.loadARM64ScalarFloatReg(ins.Args[0].Reg, sourceBits) if err != nil { return true, false, err } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = call double @llvm.fabs.f64(double %s)\n", t, src) - return true, false, c.storeF64(ins.Args[1], "%"+t) - - case "FRINTZD", "FRINTMD", "FRINTPD": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("arm64 %s expects 2 operands: %q", op, ins.Raw) + destinationBits := 64 + if strings.HasSuffix(string(op), "W") { + destinationBits = 32 } - src, err := c.evalF64(ins.Args[0]) - if err != nil { - return true, false, err + intrinsic := "fptosi.sat" + if strings.HasPrefix(string(op), "FCVTZU") { + intrinsic = "fptoui.sat" } + integerType := fmt.Sprintf("i%d", destinationBits) t := c.newTmp() - switch op { - case "FRINTZD": - fmt.Fprintf(c.b, " %%%s = call double @llvm.trunc.f64(double %s)\n", t, src) - case "FRINTMD": - fmt.Fprintf(c.b, " %%%s = call double @llvm.floor.f64(double %s)\n", t, src) - case "FRINTPD": - fmt.Fprintf(c.b, " %%%s = call double @llvm.ceil.f64(double %s)\n", t, src) - } - return true, false, c.storeF64(ins.Args[1], "%"+t) + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.%s.%s(%s %s)\n", t, integerType, intrinsic, integerType, floatSuffix, floatType, src) + value := "%" + t + if destinationBits == 32 { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, value) + value = "%" + wide + } + return true, false, c.storeReg(ins.Args[1].Reg, value) - case "FCVTZSD": - // FCVTZSD src, dstReg - if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("arm64 FCVTZSD expects src, dstReg: %q", ins.Raw) + case "SCVTFD", "SCVTFS", "SCVTFWD", "SCVTFWS", + "UCVTFD", "UCVTFS", "UCVTFWD", "UCVTFWS": + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || + ins.Args[0].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[0].Reg) || + ins.Args[1].Kind != OpReg || !isARM64FReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm64 %s expects one R/ZR source, one F destination, and no suffix: %q", op, ins.Raw) } - src, err := c.evalF64(ins.Args[0]) + src, err := c.loadReg(ins.Args[0].Reg) if err != nil { return true, false, err } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = fptosi double %s to i64\n", t, src) - return true, false, c.storeReg(ins.Args[1].Reg, "%"+t) + integerType := "i64" + if strings.Contains(string(op), "W") { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", narrow, src) + src = "%" + narrow + integerType = "i32" + } + floatType := "double" + bits := 64 + if strings.HasSuffix(string(op), "S") { + floatType = "float" + bits = 32 + } + conversion := "sitofp" + if strings.HasPrefix(string(op), "U") { + conversion = "uitofp" + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", converted, conversion, integerType, src, floatType) + if bits == 64 { + encoded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %%%s to i64\n", encoded, converted) + return true, false, c.storeReg(ins.Args[1].Reg, "%"+encoded) + } + encoded := c.newTmp() + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %%%s to i32\n", encoded, converted) + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, encoded) + return true, false, c.storeReg(ins.Args[1].Reg, "%"+wide) + } + return false, false, nil +} - case "SCVTFD": - // SCVTFD srcReg, dst - if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg { - return true, false, fmt.Errorf("arm64 SCVTFD expects srcReg, dst: %q", ins.Raw) +func (c *arm64Ctx) lowerFusedMultiplyAdd(op Op, ins Instr) (ok bool, terminated bool, err error) { + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects four F-register operands and no suffixes: %q", op, ins.Raw) + } + for _, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects four F-register operands: %q", op, ins.Raw) } - src, err := c.loadReg(ins.Args[0].Reg) - if err != nil { - return true, false, err + if _, ok := arm64ParseFReg(arg.Reg); !ok { + return true, false, fmt.Errorf("arm64 %s expects four F-register operands: %q", op, ins.Raw) } - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sitofp i64 %s to double\n", t, src) - return true, false, c.storeF64(ins.Args[1], "%"+t) } - return false, false, nil + + floatType := "double" + intrinsic := "@llvm.fma.f64" + eval := c.evalF64 + store := c.storeF64 + if strings.HasSuffix(string(op), "S") { + floatType = "float" + intrinsic = "@llvm.fma.f32" + eval = c.evalF32 + store = c.storeF32 + } + + // Go's Plan 9 order is Fm, Fa, Fn, Fd. The architectural operations are: + // FMADD: Fn*Fm + Fa FMSUB: Fa - Fn*Fm + // FNMADD: -(Fn*Fm + Fa) FNMSUB: Fn*Fm - Fa + fm, err := eval(ins.Args[0]) + if err != nil { + return true, false, err + } + fa, err := eval(ins.Args[1]) + if err != nil { + return true, false, err + } + fn, err := eval(ins.Args[2]) + if err != nil { + return true, false, err + } + + if strings.HasPrefix(string(op), "FMSUB") { + negFM := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", negFM, floatType, fm) + fm = "%" + negFM + } else if strings.HasPrefix(string(op), "FNMSUB") { + negFA := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", negFA, floatType, fa) + fa = "%" + negFA + } + + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s %s(%s %s, %s %s, %s %s)\n", + result, floatType, intrinsic, floatType, fm, floatType, fn, floatType, fa) + value := "%" + result + if strings.HasPrefix(string(op), "FNMADD") { + negResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", negResult, floatType, value) + value = "%" + negResult + } + return true, false, store(ins.Args[3], value) } func (c *arm64Ctx) evalFMOVDBits(op Operand) (string, error) { @@ -295,16 +334,9 @@ func (c *arm64Ctx) evalF64(op Operand) (string, error) { if !ok { return "", fmt.Errorf("arm64: unsupported FP param slot: %s", op.String()) } - idx := slot.Index - if idx < 0 || idx >= len(c.sig.Args) { - return "", fmt.Errorf("arm64: FP slot %s invalid arg index %d", op.String(), idx) - } - arg := fmt.Sprintf("%%arg%d", idx) - if slot.Field >= 0 { - aggTy := c.sig.Args[idx] - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", t, aggTy, arg, slot.Field) - arg = "%" + t + arg, err := c.loadFPParameter(slot) + if err != nil { + return "", err } switch slot.Type { case LLVMType("double"): @@ -337,6 +369,21 @@ func (c *arm64Ctx) evalF64(op Operand) (string, error) { } } +func (c *arm64Ctx) evalF32(op Operand) (string, error) { + if op.Kind != OpReg { + return "", fmt.Errorf("arm64: unsupported f32 operand %s", op.String()) + } + v64, err := c.loadReg(op.Reg) + if err != nil { + return "", err + } + v32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", v32, v64) + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", value, v32) + return "%" + value, nil +} + func (c *arm64Ctx) storeF64(dst Operand, v string) error { switch dst.Kind { case OpReg: @@ -352,6 +399,17 @@ func (c *arm64Ctx) storeF64(dst Operand, v string) error { } } +func (c *arm64Ctx) storeF32(dst Operand, v string) error { + if dst.Kind != OpReg { + return fmt.Errorf("arm64: unsupported f32 dst operand %s", dst.String()) + } + bits32 := c.newTmp() + bits64 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %s to i32\n", bits32, v) + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", bits64, bits32) + return c.storeReg(dst.Reg, "%"+bits64) +} + func arm64ParseDollarFloat(sym string) (float64, bool) { if !strings.HasPrefix(sym, "$") { return 0, false diff --git a/arm64_lower_halving_add.go b/arm64_lower_halving_add.go new file mode 100644 index 00000000..d7b559eb --- /dev/null +++ b/arm64_lower_halving_add.go @@ -0,0 +1,74 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorHalvingAdd(op Op, ins Instr) (ok bool, terminated bool, err error) { + type operationSpec struct { + signed bool + rounding bool + } + spec, handled := map[Op]operationSpec{ + "VSHADD": {signed: true}, + "VSRHADD": {signed: true, rounding: true}, + "VUHADD": {}, + "VURHADD": {rounding: true}, + }[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects three same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + var arrangement arm64VectorArrangement + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || parsed.elementBits == 64 && parsed.lanes != 2 { + return true, false, fmt.Errorf("arm64 %s accepts only B8/B16/H4/H8/S2/S4/D2 arrangements: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + first, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + second, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + narrowType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, arrangement.elementBits) + wideArrangement := arm64VectorArrangement{elementBits: arrangement.elementBits * 2, lanes: arrangement.lanes} + wideType := fmt.Sprintf("<%d x i%d>", wideArrangement.lanes, wideArrangement.elementBits) + extension := "zext" + shift := "lshr" + if spec.signed { + extension = "sext" + shift = "ashr" + } + wideFirst := c.newTmp() + wideSecond := c.newTmp() + sum := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", wideFirst, extension, narrowType, first, wideType) + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", wideSecond, extension, narrowType, second, wideType) + fmt.Fprintf(c.b, " %%%s = add %s %%%s, %%%s\n", sum, wideType, wideFirst, wideSecond) + shiftSource := "%" + sum + if spec.rounding { + rounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", rounded, wideType, shiftSource, arm64VectorIntegerSplat(wideArrangement, 1)) + shiftSource = "%" + rounded + } + halved := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", halved, shift, wideType, shiftSource, arm64VectorIntegerSplat(wideArrangement, 1)) + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", result, wideType, halved, narrowType) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, "%"+result) +} diff --git a/arm64_lower_halving_add_test.go b/arm64_lower_halving_add_test.go new file mode 100644 index 00000000..3888a34a --- /dev/null +++ b/arm64_lower_halving_add_test.go @@ -0,0 +1,81 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorHalvingAddCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT ·vectorHalvingAddForms(SB), $0-0\n") + for _, op := range []string{"VSHADD", "VSRHADD", "VUHADD", "VURHADD"} { + for _, arrangement := range []string{"B8", "B16", "H4", "H8", "S2", "S4", "D2"} { + source.WriteString("\t" + op + " V0." + arrangement + ", V1." + arrangement + ", V31." + arrangement + "\n") + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorHalvingAddForms": {Name: "vectorHalvingAddForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{"sext <", "zext <", "ashr <", "lshr <", "trunc <"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s halving-add IR omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-halving-add.ll", "arm64-vector-halving-add.o", ll) + } +} + +func TestTranslateARM64VectorHalvingAddRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VSHADD V0.B8, V1.B8", + "VSRHADD V0.B8, V1.B16, V2.B8", + "VUHADD V0.D1, V1.D1, V2.D1", + "VURHADD V0.S4, V1.S4, V2.S2", + "VURHADD.P V0.H8, V1.H8, V2.H8", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT ·badVectorHalvingAdd(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badVectorHalvingAdd": {Name: "badVectorHalvingAdd", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector halving-add forms", instruction) + } + }) + } +} diff --git a/arm64_lower_hint.go b/arm64_lower_hint.go new file mode 100644 index 00000000..527c4b3d --- /dev/null +++ b/arm64_lower_hint.go @@ -0,0 +1,151 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64Hint(op Op, ins Instr) (ok bool, terminated bool, err error) { + pointerAuthHints := map[Op]uint8{ + "PACIASP": 25, + "PACIBSP": 27, + "AUTIASP": 29, + "AUTIBSP": 31, + "AUTIA1716": 12, + "AUTIB1716": 14, + } + _, pointerAuthHint := pointerAuthHints[op] + if op != "HINT" && op != "YIELD" && op != "WFE" && op != "WFI" && op != "SEV" && op != "SEVL" && op != "NOP" && op != "NOOP" && op != "BTI" && !pointerAuthHint { + return false, false, nil + } + if pointerAuthHint { + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 0 { + return true, false, fmt.Errorf("arm64 %s takes no operands or suffix: %q", op, ins.Raw) + } + c.emitARM64Hint(pointerAuthHints[op]) + return true, false, nil + } + if op == "BTI" { + if strings.ToUpper(string(ins.Op)) != "BTI" || len(ins.Args) != 1 || ins.Args[0].Kind != OpIdent { + return true, false, fmt.Errorf("arm64 BTI expects C, J, or JC and no suffix: %q", ins.Raw) + } + immediate, valid := map[string]uint8{"C": 34, "J": 36, "JC": 38}[strings.ToUpper(ins.Args[0].Ident)] + if !valid { + return true, false, fmt.Errorf("arm64 BTI target type must be C, J, or JC: %q", ins.Raw) + } + c.emitARM64Hint(immediate) + return true, false, nil + } + if op == "NOOP" { + if strings.ToUpper(string(ins.Op)) != "NOOP" || len(ins.Args) != 0 { + return true, false, fmt.Errorf("arm64 NOOP takes no operands or suffix: %q", ins.Raw) + } + c.emitARM64Hint(0) + return true, false, nil + } + if op == "NOP" { + if strings.ToUpper(string(ins.Op)) != "NOP" || len(ins.Args) > 1 { + return true, false, fmt.Errorf("arm64 NOP accepts no operand or one C_LCON/R/ZR/V operand, with no suffix: %q", ins.Raw) + } + if len(ins.Args) == 1 { + operand := ins.Args[0] + valid := operand.Kind == OpImm && operand.ImmRaw == "" && arm64GoLCON(operand.Imm) + if operand.Kind == OpReg { + _, vector := arm64ParseVReg(operand.Reg) + valid = isARM64GeneralOrZeroReg(operand.Reg) || vector + } + if !valid { + return true, false, fmt.Errorf("arm64 NOP operand is outside Go's C_LCON/C_ZREG/C_VREG rows: %q", ins.Raw) + } + } + // Go's NOP pseudo-instruction intentionally emits no machine code. + return true, false, nil + } + rawOp := strings.ToUpper(string(ins.Op)) + if op == "HINT" { + if rawOp != "HINT" || len(ins.Args) != 1 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 HINT takes one resolved integer constant and no suffix: %q", ins.Raw) + } + c.emitARM64Hint(uint8(ins.Args[0].Imm & 0x7f)) + return true, false, nil + } + if rawOp != string(op) || len(ins.Args) != 0 { + return true, false, fmt.Errorf("arm64 %s takes no operands or suffix: %q", op, ins.Raw) + } + mnemonics := map[Op]string{ + "YIELD": "yield", + "WFE": "wfe", + "WFI": "wfi", + "SEV": "sev", + "SEVL": "sevl", + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, \"\"()\n", mnemonics[op]) + return true, false, nil +} + +func decodeARM64RawHint(word uint32) (uint8, bool) { + const immediateMask = uint32(0x7f << 5) + if word&^immediateMask != 0xd503201f { + return 0, false + } + return uint8(word >> 5 & 0x7f), true +} + +func (c *arm64Ctx) emitARM64Hint(immediate uint8) { + fmt.Fprintf(c.b, " call void asm sideeffect \"hint #%d\", \"\"()\n", immediate&0x7f) +} + +// arm64GoLCON reports whether conclass(v, 64) can satisfy Go's C_LCON +// operand row. Only C_VCON falls outside that row; all earlier constant +// classes are compatible with it. +func arm64GoLCON(value int64) bool { + if value == 0 || arm64GoAddConstant(value) || arm64GoMoveConstant(value) || + arm64GoMoveConstant(^value) || arm64GoBitConstant(uint64(value)) || + (value >= 0 && value <= 0xffffff) { + return true + } + return uint64(value) == uint64(uint32(value)) || value == int64(int32(value)) +} + +func arm64GoAddConstant(value int64) bool { + if value < 0 { + return false + } + if value&0xfff == 0 { + value >>= 12 + } + return value <= 0xfff +} + +func arm64GoMoveConstant(value int64) bool { + bits := uint64(value) + for shift := uint(0); shift < 64; shift += 16 { + if bits&^(uint64(0xffff)<>32|value<<32: + case value != value>>16|value<<48: + value = uint64(int64(int32(value))) + case value != value>>8|value<<56: + value = uint64(int64(int16(value))) + case value != value>>4|value<<60: + value = uint64(int64(int8(value))) + default: + return true + } + return arm64SequenceOfOnes(value) || arm64SequenceOfOnes(^value) +} + +func arm64SequenceOfOnes(value uint64) bool { + next := value + (value & -value) + return (next-1)&next == 0 +} diff --git a/arm64_lower_hint_test.go b/arm64_lower_hint_test.go new file mode 100644 index 00000000..67f104f8 --- /dev/null +++ b/arm64_lower_hint_test.go @@ -0,0 +1,179 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64YieldCompleteGoAssemblerForms(t *testing.T) { + source := "TEXT yieldform(SB),$0-0\n\tYIELD\n\tRET\n" + requireARM64GoAssemblerResult(t, source, true) + + for _, triple := range []string{ + "arm64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"yieldform": {Name: "yieldform", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, `asm sideeffect "yield"`) { + t.Fatalf("ARM64 YIELD was silently discarded for %s:\n%s", triple, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-yield.ll", "arm64-yield.o", ll) + }) + } +} + +func TestTranslateARM64HintFamilyCompleteGoAssemblerForms(t *testing.T) { + source := ` +TEXT hintforms(SB),$0-0 + HINT $0 + HINT $6 + HINT $127 + HINT $128 + HINT $-1 + HINT $0x1122334455667788 + YIELD + WFE + WFI + SEV + SEVL + WORD $0xd503203f + WORD $0xd503205f + WORD $0xd503207f + WORD $0xd503209f + WORD $0xd50320bf + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "arm64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"hintforms": {Name: "hintforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"hint #0"`, `"hint #6"`, `"hint #127"`, `"yield"`, `"wfe"`, `"wfi"`, `"sev"`, `"sevl"`} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 hint family omitted %s for %s:\n%s", want, triple, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-hints.ll", "arm64-hints.o", ll) + }) + } +} + +func TestTranslateARM64HintRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{"HINT", "HINT R0", "HINT $1, $2", "HINT.P $1", "WFE $0", "WFI R0", "SEV $1", "SEVL.P"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's hint forms", instruction) + } + } +} + +func TestTranslateARM64YieldRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{"YIELD $0", "YIELD R0", "YIELD.P"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's YIELD forms", instruction) + } + } +} + +func TestTranslateARM64NOPMatchesGoAssemblerForms(t *testing.T) { + source := ` +TEXT nopform(SB),$0-0 + NOP + NOP $0 + NOP $4294967295 + NOP $4294967296 + NOP R0 + NOP ZR + NOP V0 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"nopform": {Name: "nopform", Ret: Void}}, + }); err != nil { + t.Fatal(err) + } + for _, instruction := range []string{ + "NOP $0x1122334455667788", + "NOP F0", + "NOP RSP", + "NOP R0, R1", + "NOP.P", + } { + badSource := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, badSource, false) + badFile, err := Parse(ArchARM64, badSource) + if err != nil { + continue + } + if _, err := Translate(badFile, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's NOP forms", instruction) + } + } +} diff --git a/arm64_lower_immediate_shift_right_test.go b/arm64_lower_immediate_shift_right_test.go new file mode 100644 index 00000000..8a46ddaf --- /dev/null +++ b/arm64_lower_immediate_shift_right_test.go @@ -0,0 +1,245 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func encodeARM64ImmediateShiftRight(base uint32, elementBits, shift int, fullVector bool, source, destination int) uint32 { + encodedImmediate := uint32(2*elementBits - shift) + word := base | encodedImmediate<<16 | uint32(source)<<5 | uint32(destination) + if fullVector { + word |= 1 << 30 + } + return word +} + +func TestTranslateARM64RawImmediateShiftRightCompleteArchitectureFamily(t *testing.T) { + families := []struct { + name string + base uint32 + }{ + {name: "VSSHR", base: 0x0f000400}, + {name: "VSSRA", base: 0x0f001400}, + {name: "VSRSHR", base: 0x0f002400}, + {name: "VSRSRA", base: 0x0f003400}, + {name: "VUSHR", base: 0x2f000400}, + {name: "VUSRA", base: 0x2f001400}, + {name: "VURSHR", base: 0x2f002400}, + {name: "VURSRA", base: 0x2f003400}, + } + type form struct { + elementBits int + fullVector bool + } + forms := []form{ + {elementBits: 8}, {elementBits: 8, fullVector: true}, + {elementBits: 16}, {elementBits: 16, fullVector: true}, + {elementBits: 32}, {elementBits: 32, fullVector: true}, + {elementBits: 64, fullVector: true}, + } + arrangementName := func(form form) string { + lanes := 64 / form.elementBits + if form.fullVector { + lanes *= 2 + } + letter := map[int]string{8: "B", 16: "H", 32: "S", 64: "D"}[form.elementBits] + return fmt.Sprintf("%s%d", letter, lanes) + } + + var source strings.Builder + source.WriteString("TEXT ·immediateShiftRightArchitectureForms(SB), $0-0\n") + for _, family := range families { + for _, form := range forms { + for _, shift := range []int{1, form.elementBits} { + word := encodeARM64ImmediateShiftRight(family.base, form.elementBits, shift, form.fullVector, 29, 28) + decoded, err := decodeARM64RawWordInstruction(Instr{Op: OpWORD, Args: []Operand{{Kind: OpImm, Imm: int64(word)}}}) + if err != nil { + t.Fatalf("decode %s %d-bit Q=%v shift=%d: %v", family.name, form.elementBits, form.fullVector, shift, err) + } + wantSource := Reg("V29." + arrangementName(form)) + wantDestination := Reg("V28." + arrangementName(form)) + if decoded.Op != Op(family.name) || len(decoded.Args) != 3 || decoded.Args[0].Kind != OpImm || decoded.Args[0].Imm != int64(shift) || + decoded.Args[1].Reg != wantSource || decoded.Args[2].Reg != wantDestination { + t.Fatalf("decoded %s %d-bit Q=%v shift=%d %#08x as %#v", family.name, form.elementBits, form.fullVector, shift, word, decoded) + } + fmt.Fprintf(&source, "\tWORD $%#08x // %s %d-bit Q=%v shift=%d\n", word, family.name, form.elementBits, form.fullVector, shift) + } + } + for _, shift := range []int{1, 64} { + scalarBase := family.base | 0x50000000 + word := encodeARM64ImmediateShiftRight(scalarBase, 64, shift, false, 29, 28) + decoded, err := decodeARM64RawWordInstruction(Instr{Op: OpWORD, Args: []Operand{{Kind: OpImm, Imm: int64(word)}}}) + if err != nil { + t.Fatalf("decode scalar %s shift=%d: %v", family.name, shift, err) + } + if decoded.Op != Op(family.name) || len(decoded.Args) != 3 || decoded.Args[0].Kind != OpImm || decoded.Args[0].Imm != int64(shift) || decoded.Args[1].Reg != "V29" || decoded.Args[2].Reg != "V28" { + t.Fatalf("decoded scalar %s shift=%d %#08x as %#v", family.name, shift, word, decoded) + } + fmt.Fprintf(&source, "\tWORD $%#08x // scalar %s D shift=%d\n", word, family.name, shift) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "immediateShiftRightArchitectureForms": {Name: "immediateShiftRightArchitectureForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, line := range strings.Split(ll, "\n") { + if !strings.Contains(line, " = ashr ") && !strings.Contains(line, " = lshr ") { + continue + } + if strings.Contains(line, "ashr i64") || strings.Contains(line, "lshr i64") { + if strings.HasSuffix(line, ", 64") { + t.Fatalf("%s emitted undefined scalar width-sized shift: %s", triple, line) + } + } + for _, bits := range []int{8, 16, 32, 64} { + if strings.Contains(line, fmt.Sprintf("x i%d>", bits)) && strings.Contains(line, fmt.Sprintf("i%d %d", bits, bits)) { + t.Fatalf("%s emitted undefined vector width-sized shift: %s", triple, line) + } + } + } + for _, operation := range []string{"ashr", "lshr", "add"} { + if !strings.Contains(ll, " = "+operation+" ") { + t.Fatalf("%s omitted %s semantics:\n%s", triple, operation, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-immediate-shift-right.ll", "arm64-immediate-shift-right.o", ll) + }) + } +} + +func TestTranslateARM64ImmediateShiftRightRejectsInvalidArchitectureForms(t *testing.T) { + for _, instruction := range []string{ + "VURSHR V0.S4, V1.S4", + "VURSRA $0, V0.S4, V1.S4", + "VSSRA $33, V0.S4, V1.S4", + "VSRSRA $1, V0.S2, V1.S4", + "VURSHR $1, V0.D1, V1.D1", + "VURSRA.P $1, V0.S4, V1.S4", + } { + file, err := Parse(ArchARM64, "TEXT ·badImmediateShift(SB), $0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{"badImmediateShift": {Name: "badImmediateShift", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted invalid ARM64 immediate shift-right form %q", instruction) + } + } +} + +func TestARM64ImmediateShiftRightRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + families := []uint32{ + 0x0f000400, // SSHR + 0x0f001400, // SSRA + 0x0f002400, // SRSHR + 0x0f003400, // SRSRA + 0x2f000400, // USHR + 0x2f001400, // USRA + 0x2f002400, // URSHR + 0x2f003400, // URSRA + } + var source strings.Builder + source.WriteString("TEXT immediateShiftRightSemantics(SB),$0-24\n") + source.WriteString("\tMOVD in+0(FP), R0\n\tMOVD initial+8(FP), R1\n\tMOVD out+16(FP), R2\n") + source.WriteString("\tVLD1 (R0), [V0.B16]\n") + source.WriteString("\tVLD1.P 64(R1), [V8.B16, V9.B16, V10.B16, V11.B16]\n") + source.WriteString("\tVLD1 (R1), [V12.B16, V13.B16, V14.B16, V15.B16]\n") + for i, base := range families { + word := encodeARM64ImmediateShiftRight(base, 8, 4, true, 0, 8+i) + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + source.WriteString("\tVST1.P [V8.B16, V9.B16, V10.B16, V11.B16], 64(R2)\n") + source.WriteString("\tVST1 [V12.B16, V13.B16, V14.B16, V15.B16], (R2)\n\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"immediateShiftRightSemantics": { + Name: "immediateShiftRightSemantics", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void immediateShiftRightSemantics(const uint8_t *, const uint8_t *, uint8_t *); +int main(void) { + uint8_t in[16], initial[128], got[128] = {0}; + for (int i = 0; i < 16; i++) in[i] = (uint8_t)(i * 29u + 3u); + for (int i = 0; i < 128; i++) initial[i] = (uint8_t)(i * 7u + 5u); + immediateShiftRightSemantics(in, initial, got); + for (int i = 0; i < 16; i++) { + const int16_t sx = (int8_t)in[i]; + const uint16_t ux = in[i]; + const int16_t signed_shift = sx >> 4; + const int16_t signed_round = signed_shift + ((sx >> 3) & 1); + const uint16_t unsigned_shift = ux >> 4; + const uint16_t unsigned_round = unsigned_shift + ((ux >> 3) & 1); + const uint8_t want[8] = { + (uint8_t)signed_shift, + (uint8_t)(initial[1*16+i] + signed_shift), + (uint8_t)signed_round, + (uint8_t)(initial[3*16+i] + signed_round), + (uint8_t)unsigned_shift, + (uint8_t)(initial[5*16+i] + unsigned_shift), + (uint8_t)unsigned_round, + (uint8_t)(initial[7*16+i] + unsigned_round), + }; + for (int op = 0; op < 8; op++) if (got[op*16+i] != want[op]) return op*16+i+1; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_immediate_shift_right", triple, ll, mainC, nil) +} diff --git a/arm64_lower_integer_abs_neg.go b/arm64_lower_integer_abs_neg.go new file mode 100644 index 00000000..9b897e2d --- /dev/null +++ b/arm64_lower_integer_abs_neg.go @@ -0,0 +1,70 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorIntegerAbsNeg(op Op, ins Instr) (ok bool, terminated bool, err error) { + saturating, handled := map[Op]bool{ + "VABS": false, "VNEG": false, + "VSQABS": true, "VSQNEG": true, + }[op] + if !handled && op != "VABS" && op != "VNEG" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || + ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects two same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + sourceArrangement, sourceOK := parseARM64VectorArrangement(ins.Args[0].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[1].Reg) + validArrangement := sourceArrangement.elementBits != 64 || sourceArrangement.lanes == 2 + if !sourceOK || !destinationOK || sourceArrangement != destinationArrangement || !validArrangement { + return true, false, fmt.Errorf("arm64 %s requires matching B8, B16, H4, H8, S2, S4, or D2 arrangements: %q", op, ins.Raw) + } + + arrangement := sourceArrangement + vectorType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, arrangement.elementBits) + source, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + negated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s zeroinitializer, %s\n", negated, vectorType, source) + result := "%" + negated + if op == "VABS" || op == "VSQABS" { + negative := c.newTmp() + absolute := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp slt %s %s, zeroinitializer\n", negative, vectorType, source) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %%%s, %s %s\n", + absolute, arrangement.lanes, negative, vectorType, negated, vectorType, source) + result = "%" + absolute + } + if saturating { + // In two's complement, zero and the signed minimum are the only values + // equal to their own negation. Excluding zero identifies saturation; a + // logical shift of the minimum produces the signed maximum. + equalNegation := c.newTmp() + nonzero := c.newTmp() + overflow := c.newTmp() + saturated := c.newTmp() + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, %%%s\n", equalNegation, vectorType, source, negated) + fmt.Fprintf(c.b, " %%%s = icmp ne %s %s, zeroinitializer\n", nonzero, vectorType, source) + fmt.Fprintf(c.b, " %%%s = and <%d x i1> %%%s, %%%s\n", overflow, arrangement.lanes, equalNegation, nonzero) + fmt.Fprintf(c.b, " %%%s = lshr %s %%%s, %s\n", saturated, vectorType, negated, arm64VectorIntegerSplat(arrangement, 1)) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %%%s, %s %s\n", + selected, arrangement.lanes, overflow, vectorType, saturated, vectorType, result) + result = "%" + selected + } + return true, false, c.storeARM64VectorInteger(ins.Args[1].Reg, arrangement, result) +} + +func arm64VectorIntegerSplat(arrangement arm64VectorArrangement, value int64) string { + parts := make([]string, arrangement.lanes) + for i := range parts { + parts[i] = fmt.Sprintf("i%d %d", arrangement.elementBits, value) + } + return "<" + strings.Join(parts, ", ") + ">" +} diff --git a/arm64_lower_integer_abs_neg_test.go b/arm64_lower_integer_abs_neg_test.go new file mode 100644 index 00000000..38f6c3bf --- /dev/null +++ b/arm64_lower_integer_abs_neg_test.go @@ -0,0 +1,82 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorIntegerAbsNegCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT ·vectorIntegerAbsNegForms(SB), $0-0\n") + for _, op := range []string{"VABS", "VNEG", "VSQABS", "VSQNEG"} { + for _, arrangement := range []string{"B8", "B16", "H4", "H8", "S2", "S4", "D2"} { + source.WriteString("\t" + op + " V0." + arrangement + ", V31." + arrangement + "\n") + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorIntegerAbsNegForms": {Name: "vectorIntegerAbsNegForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{"sub <", "icmp slt <", "icmp eq <", "select <"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s integer abs/neg IR omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-integer-abs-neg.ll", "arm64-vector-integer-abs-neg.o", ll) + } +} + +func TestTranslateARM64VectorIntegerAbsNegRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VABS V0.B8", + "VNEG V0.B8, V1.B16", + "VSQABS V0.D1, V1.D1", + "VSQNEG V0.B16, V1.B16, V2.B16", + "VABS.P V0.S4, V1.S4", + "VABS F0, F1", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT ·badVectorIntegerAbsNeg(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badVectorIntegerAbsNeg": {Name: "badVectorIntegerAbsNeg", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector integer abs/neg forms", instruction) + } + }) + } +} diff --git a/arm64_lower_integer_minmax.go b/arm64_lower_integer_minmax.go new file mode 100644 index 00000000..156890f7 --- /dev/null +++ b/arm64_lower_integer_minmax.go @@ -0,0 +1,84 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorIntegerMinMax(op Op, ins Instr) (ok bool, terminated bool, err error) { + type operationSpec struct { + predicate string + pairwise bool + } + specs := map[Op]operationSpec{ + "VSMAX": {predicate: "sgt"}, + "VSMIN": {predicate: "slt"}, + "VUMAX": {predicate: "ugt"}, + "VUMIN": {predicate: "ult"}, + "VSMAXP": {predicate: "sgt", pairwise: true}, + "VSMINP": {predicate: "slt", pairwise: true}, + "VUMAXP": {predicate: "ugt", pairwise: true}, + "VUMINP": {predicate: "ult", pairwise: true}, + } + spec, handled := specs[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects three same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + var arrangement arm64VectorArrangement + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || parsed.elementBits == 64 { + return true, false, fmt.Errorf("arm64 %s accepts only B8, B16, H4, H8, S2, or S4 arrangements: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + first, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + second, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + result := "" + if !spec.pairwise { + condition := c.newTmp() + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %s <%d x i%d> %s, %s\n", condition, spec.predicate, arrangement.lanes, arrangement.elementBits, first, second) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, <%d x i%d> %s, <%d x i%d> %s\n", + selected, arrangement.lanes, condition, arrangement.lanes, arrangement.elementBits, first, arrangement.lanes, arrangement.elementBits, second) + result = "%" + selected + } else { + result = "poison" + half := arrangement.lanes / 2 + for lane := 0; lane < arrangement.lanes; lane++ { + source := second + if lane >= half { + source = first + } + pair := (lane % half) * 2 + left := c.newTmp() + right := c.newTmp() + condition := c.newTmp() + selected := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", left, arrangement.lanes, arrangement.elementBits, source, pair) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", right, arrangement.lanes, arrangement.elementBits, source, pair+1) + fmt.Fprintf(c.b, " %%%s = icmp %s i%d %%%s, %%%s\n", condition, spec.predicate, arrangement.elementBits, left, right) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %%%s, i%d %%%s\n", selected, condition, arrangement.elementBits, left, arrangement.elementBits, right) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", inserted, arrangement.lanes, arrangement.elementBits, result, arrangement.elementBits, selected, lane) + result = "%" + inserted + } + } + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, result) +} diff --git a/arm64_lower_integer_minmax_across.go b/arm64_lower_integer_minmax_across.go new file mode 100644 index 00000000..1b88a783 --- /dev/null +++ b/arm64_lower_integer_minmax_across.go @@ -0,0 +1,58 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorIntegerMinMaxAcross(op Op, ins Instr) (ok bool, terminated bool, err error) { + predicate, handled := map[Op]string{ + "VSMAXV": "sgt", + "VSMINV": "slt", + "VUMAXV": "ugt", + "VUMINV": "ult", + }[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || + ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects an arranged vector source, bare V destination, and no suffix: %q", op, ins.Raw) + } + arrangement, valid := parseARM64VectorArrangement(ins.Args[0].Reg) + if !valid || !((arrangement.elementBits == 8 && (arrangement.lanes == 8 || arrangement.lanes == 16)) || + (arrangement.elementBits == 16 && (arrangement.lanes == 4 || arrangement.lanes == 8)) || + (arrangement.elementBits == 32 && arrangement.lanes == 4)) { + return true, false, fmt.Errorf("arm64 %s accepts only B8, B16, H4, H8, or S4 source: %q", op, ins.Raw) + } + if strings.Contains(string(ins.Args[1].Reg), ".") { + return true, false, fmt.Errorf("arm64 %s destination must be a bare V register: %q", op, ins.Raw) + } + if _, valid := arm64ParseVReg(ins.Args[1].Reg); !valid { + return true, false, fmt.Errorf("arm64 %s destination must be a bare V register: %q", op, ins.Raw) + } + + source, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 0\n", result, arrangement.lanes, arrangement.elementBits, source) + current := "%" + result + for lane := 1; lane < arrangement.lanes; lane++ { + element := c.newTmp() + condition := c.newTmp() + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", element, arrangement.lanes, arrangement.elementBits, source, lane) + fmt.Fprintf(c.b, " %%%s = icmp %s i%d %s, %%%s\n", condition, predicate, arrangement.elementBits, current, element) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i%d %s, i%d %%%s\n", selected, condition, arrangement.elementBits, current, arrangement.elementBits, element) + current = "%" + selected + } + physicalLanes := 128 / arrangement.elementBits + vector := c.newTmp() + out := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> zeroinitializer, i%d %s, i32 0\n", + vector, physicalLanes, arrangement.elementBits, arrangement.elementBits, current) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", out, physicalLanes, arrangement.elementBits, vector) + return true, false, c.storeVReg(ins.Args[1].Reg, "%"+out) +} diff --git a/arm64_lower_integer_minmax_across_test.go b/arm64_lower_integer_minmax_across_test.go new file mode 100644 index 00000000..785a9a04 --- /dev/null +++ b/arm64_lower_integer_minmax_across_test.go @@ -0,0 +1,81 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorIntegerMinMaxAcrossCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT ·vectorIntegerMinMaxAcrossForms(SB), $0-0\n") + for _, op := range []string{"VSMAXV", "VSMINV", "VUMAXV", "VUMINV"} { + for _, arrangement := range []string{"B8", "B16", "H4", "H8", "S4"} { + source.WriteString("\t" + op + " V0." + arrangement + ", V31\n") + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorIntegerMinMaxAcrossForms": {Name: "vectorIntegerMinMaxAcrossForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{"icmp sgt i", "icmp slt i", "icmp ugt i", "icmp ult i", "select i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s integer min/max-across IR omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-integer-minmax-across.ll", "arm64-vector-integer-minmax-across.o", ll) + } +} + +func TestTranslateARM64VectorIntegerMinMaxAcrossRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VSMAXV V0.B8", + "VSMINV V0.S2, V1", + "VUMAXV V0.D2, V1", + "VUMINV V0.H8, V1.H8", + "VUMINV.P V0.S4, V1", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT ·badVectorIntegerMinMaxAcross(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badVectorIntegerMinMaxAcross": {Name: "badVectorIntegerMinMaxAcross", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector integer min/max-across forms", instruction) + } + }) + } +} diff --git a/arm64_lower_integer_minmax_test.go b/arm64_lower_integer_minmax_test.go new file mode 100644 index 00000000..18482f86 --- /dev/null +++ b/arm64_lower_integer_minmax_test.go @@ -0,0 +1,67 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorIntegerMinMaxCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT ·vectorintegerminmaxforms(SB), $0-0\n") + for _, op := range []string{"VSMAX", "VSMIN", "VUMAX", "VUMIN", "VSMAXP", "VSMINP", "VUMAXP", "VUMINP"} { + for _, arrangement := range []string{"B8", "B16", "H4", "H8", "S2", "S4"} { + source.WriteString("\t" + op + " V0." + arrangement + ", V1." + arrangement + ", V31." + arrangement + "\n") + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{"vectorintegerminmaxforms": {Name: "vectorintegerminmaxforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-integer-minmax.ll", "arm64-vector-integer-minmax.o", ll) + }) + } +} + +func TestTranslateARM64VectorIntegerMinMaxRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VUMAX V0.D2, V1.D2, V2.D2", + "VSMIN V0.S2, V1.S4, V2.S2", + "VUMAXP V0.H8, V1.H8", + "VSMAX.P V0.B16, V1.B16, V2.B16", + "VUMIN R0, V1.S4, V2.S4", + } { + source := "TEXT ·bad(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector integer min/max table", instruction) + } + } +} diff --git a/arm64_lower_integer_multiply.go b/arm64_lower_integer_multiply.go new file mode 100644 index 00000000..2a545188 --- /dev/null +++ b/arm64_lower_integer_multiply.go @@ -0,0 +1,57 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorIntegerMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + accumulate, handled := map[Op]string{ + "VMUL": "", + "VMLA": "add", + "VMLS": "sub", + }[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects three same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + var arrangement arm64VectorArrangement + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || parsed.elementBits == 64 { + return true, false, fmt.Errorf("arm64 %s accepts only B8/B16/H4/H8/S2/S4 arrangements: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + first, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + second, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + vectorType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, arrangement.elementBits) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul %s %s, %s\n", product, vectorType, second, first) + result := "%" + product + if accumulate != "" { + accumulator, err := c.loadARM64VectorInteger(ins.Args[2].Reg, arrangement) + if err != nil { + return true, false, err + } + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %%%s\n", combined, accumulate, vectorType, accumulator, product) + result = "%" + combined + } + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, result) +} diff --git a/arm64_lower_integer_multiply_test.go b/arm64_lower_integer_multiply_test.go new file mode 100644 index 00000000..843dbf05 --- /dev/null +++ b/arm64_lower_integer_multiply_test.go @@ -0,0 +1,81 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorIntegerMultiplyCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT ·vectorIntegerMultiplyForms(SB), $0-0\n") + for _, op := range []string{"VMUL", "VMLA", "VMLS"} { + for _, arrangement := range []string{"B8", "B16", "H4", "H8", "S2", "S4"} { + source.WriteString("\t" + op + " V0." + arrangement + ", V1." + arrangement + ", V31." + arrangement + "\n") + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorIntegerMultiplyForms": {Name: "vectorIntegerMultiplyForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{"mul <", "add <", "sub <"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s integer-multiply IR omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-integer-multiply.ll", "arm64-vector-integer-multiply.o", ll) + } +} + +func TestTranslateARM64VectorIntegerMultiplyRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VMUL V0.B8, V1.B8", + "VMLA V0.B8, V1.B16, V2.B8", + "VMLS V0.D2, V1.D2, V2.D2", + "VMUL V0.S4, V1.S4, V2.S2", + "VMUL.P V0.H8, V1.H8, V2.H8", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT ·badVectorIntegerMultiply(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badVectorIntegerMultiply": {Name: "badVectorIntegerMultiply", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector integer multiply forms", instruction) + } + }) + } +} diff --git a/arm64_lower_integer_narrow.go b/arm64_lower_integer_narrow.go new file mode 100644 index 00000000..0b84986a --- /dev/null +++ b/arm64_lower_integer_narrow.go @@ -0,0 +1,99 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorIntegerNarrow(op Op, ins Instr) (ok bool, terminated bool, err error) { + kind, handled := map[Op]string{ + "VXTN": "truncate", "VXTN2": "truncate", + "VSQXTN": "signed", "VSQXTN2": "signed", + "VSQXTUN": "signed-to-unsigned", "VSQXTUN2": "signed-to-unsigned", + "VUQXTN": "unsigned", "VUQXTN2": "unsigned", + }[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || + ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects a wide vector source, narrow vector destination, and no suffix: %q", op, ins.Raw) + } + sourceArrangement, sourceOK := parseARM64VectorArrangement(ins.Args[0].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[1].Reg) + highHalf := strings.HasSuffix(string(op), "2") + wantDestinationLanes := sourceArrangement.lanes + if highHalf { + wantDestinationLanes *= 2 + } + if !sourceOK || !destinationOK || + sourceArrangement.lanes*sourceArrangement.elementBits != 128 || + sourceArrangement.elementBits != destinationArrangement.elementBits*2 || + destinationArrangement.lanes != wantDestinationLanes { + return true, false, fmt.Errorf("arm64 %s requires H8->B8/S4->H4/D2->S2 (or the doubled *2 destination): %q", op, ins.Raw) + } + + source, err := c.loadARM64VectorInteger(ins.Args[0].Reg, sourceArrangement) + if err != nil { + return true, false, err + } + sourceType := fmt.Sprintf("<%d x i%d>", sourceArrangement.lanes, sourceArrangement.elementBits) + destinationType := fmt.Sprintf("<%d x i%d>", sourceArrangement.lanes, destinationArrangement.elementBits) + clamped := source + switch kind { + case "signed": + minimum := -(int64(1) << (destinationArrangement.elementBits - 1)) + maximum := (int64(1) << (destinationArrangement.elementBits - 1)) - 1 + clamped = c.clampARM64VectorInteger(sourceType, sourceArrangement, source, "slt", minimum, "sgt", maximum) + case "signed-to-unsigned": + maximum := (int64(1) << destinationArrangement.elementBits) - 1 + clamped = c.clampARM64VectorInteger(sourceType, sourceArrangement, source, "slt", 0, "sgt", maximum) + case "unsigned": + maximum := (int64(1) << destinationArrangement.elementBits) - 1 + above := c.newTmp() + selected := c.newTmp() + upper := arm64VectorIntegerSplat(sourceArrangement, maximum) + fmt.Fprintf(c.b, " %%%s = icmp ugt %s %s, %s\n", above, sourceType, source, upper) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %s\n", + selected, sourceArrangement.lanes, above, sourceType, upper, sourceType, source) + clamped = "%" + selected + } + narrowed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", narrowed, sourceType, clamped, destinationType) + if !highHalf { + return true, false, c.storeARM64VectorInteger(ins.Args[1].Reg, destinationArrangement, "%"+narrowed) + } + + // The *2 forms preserve the low half of the destination and insert the + // newly narrowed lanes into its high half. + result, err := c.loadARM64VectorInteger(ins.Args[1].Reg, destinationArrangement) + if err != nil { + return true, false, err + } + fullDestinationType := fmt.Sprintf("<%d x i%d>", destinationArrangement.lanes, destinationArrangement.elementBits) + for lane := 0; lane < sourceArrangement.lanes; lane++ { + element := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", element, destinationType, narrowed, lane) + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %%%s, i32 %d\n", + inserted, fullDestinationType, result, destinationArrangement.elementBits, element, sourceArrangement.lanes+lane) + result = "%" + inserted + } + return true, false, c.storeARM64VectorInteger(ins.Args[1].Reg, destinationArrangement, result) +} + +func (c *arm64Ctx) clampARM64VectorInteger(vectorType string, arrangement arm64VectorArrangement, source, lowerPredicate string, lower int64, upperPredicate string, upper int64) string { + lowerValue := arm64VectorIntegerSplat(arrangement, lower) + below := c.newTmp() + lowerClamped := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %s %s %s, %s\n", below, lowerPredicate, vectorType, source, lowerValue) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %s\n", + lowerClamped, arrangement.lanes, below, vectorType, lowerValue, vectorType, source) + upperValue := arm64VectorIntegerSplat(arrangement, upper) + above := c.newTmp() + upperClamped := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %s %s %%%s, %s\n", above, upperPredicate, vectorType, lowerClamped, upperValue) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %%%s\n", + upperClamped, arrangement.lanes, above, vectorType, upperValue, vectorType, lowerClamped) + return "%" + upperClamped +} diff --git a/arm64_lower_integer_narrow_test.go b/arm64_lower_integer_narrow_test.go new file mode 100644 index 00000000..03291fa2 --- /dev/null +++ b/arm64_lower_integer_narrow_test.go @@ -0,0 +1,85 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorIntegerNarrowCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT ·vectorIntegerNarrowForms(SB), $0-0\n") + for _, op := range []string{"VXTN", "VSQXTN", "VSQXTUN", "VUQXTN"} { + source.WriteString("\t" + op + " V0.H8, V1.B8\n") + source.WriteString("\t" + op + " V2.S4, V3.H4\n") + source.WriteString("\t" + op + " V4.D2, V5.S2\n") + source.WriteString("\t" + op + "2 V6.H8, V7.B16\n") + source.WriteString("\t" + op + "2 V8.S4, V9.H8\n") + source.WriteString("\t" + op + "2 V10.D2, V11.S4\n") + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorIntegerNarrowForms": {Name: "vectorIntegerNarrowForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{"trunc <", "icmp slt <", "icmp sgt <", "icmp ugt <", "insertelement <"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s integer narrow IR omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-integer-narrow.ll", "arm64-vector-integer-narrow.o", ll) + } +} + +func TestTranslateARM64VectorIntegerNarrowRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VXTN V0.B8, V1.B8", + "VXTN2 V0.H8, V1.B8", + "VSQXTN V0.H8, V1.B16", + "VSQXTUN2 V0.S4, V1.S4", + "VUQXTN V0.D2, V1.H4", + "VUQXTN.P V0.H8, V1.B8", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT ·badVectorIntegerNarrow(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badVectorIntegerNarrow": {Name: "badVectorIntegerNarrow", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector integer narrowing forms", instruction) + } + }) + } +} diff --git a/arm64_lower_integer_pair.go b/arm64_lower_integer_pair.go new file mode 100644 index 00000000..56f6eb4c --- /dev/null +++ b/arm64_lower_integer_pair.go @@ -0,0 +1,150 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64IntegerPair(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "LDP", "LDPW", "LDPSW", "STP", "STPW": + default: + return false, false, nil + } + rawOp := strings.ToUpper(string(ins.Op)) + preIndex, postIndex := false, false + switch rawOp { + case string(op): + case string(op) + ".W": + preIndex = true + case string(op) + ".P": + postIndex = true + default: + return true, false, fmt.Errorf("arm64 %s accepts only .W or .P memory suffixes: %q", op, ins.Raw) + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects exactly 2 operands: %q", op, ins.Raw) + } + load := strings.HasPrefix(string(op), "LDP") + memory, pair := ins.Args[0], ins.Args[1] + if !load { + pair, memory = ins.Args[0], ins.Args[1] + } + if pair.Kind != OpRegList || len(pair.RegList) != 2 { + return true, false, fmt.Errorf("arm64 %s expects a pair of general registers: %q", op, ins.Raw) + } + for _, reg := range pair.RegList { + if !isARM64GeneralOrZeroReg(reg) { + return true, false, fmt.Errorf("arm64 %s expects a pair of general registers: %q", op, ins.Raw) + } + } + if memory.Kind == OpFP { + if op != "LDP" || preIndex || postIndex { + return true, false, fmt.Errorf("arm64 %s does not support this FP-relative pair form: %q", op, ins.Raw) + } + // Preserve the established ABI-frame behavior: the first register + // receives the modeled frame slot and the unavailable adjacent slot is + // materialized as zero. + value, err := c.eval64(memory, false) + if err != nil { + return true, false, err + } + if err := c.storeReg(pair.RegList[0], value); err != nil { + return true, false, err + } + return true, false, c.storeReg(pair.RegList[1], "0") + } + ptr, base, increment, update, err := c.arm64IntegerPairPointer(memory, preIndex, postIndex) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + elementBytes := 8 + if op == "LDPW" || op == "LDPSW" || op == "STPW" { + elementBytes = 4 + } + for index, reg := range pair.RegList { + elementPtr := ptr + if index != 0 { + next := c.newTmp() + fmt.Fprintf(c.b, " %%%s = getelementptr i8, ptr %s, i64 %d\n", next, ptr, elementBytes) + elementPtr = "%" + next + } + if load { + if err := c.loadARM64IntegerPairElement(reg, elementPtr, elementBytes, op == "LDPSW"); err != nil { + return true, false, err + } + } else if err := c.storeARM64IntegerPairElement(reg, elementPtr, elementBytes); err != nil { + return true, false, err + } + } + if update { + if err := c.updatePostInc(base, increment); err != nil { + return true, false, err + } + } + return true, false, nil +} + +func (c *arm64Ctx) arm64IntegerPairPointer(operand Operand, preIndex, postIndex bool) (ptr string, base Reg, increment int64, update bool, err error) { + if operand.Kind == OpSym { + if preIndex || postIndex { + return "", "", 0, false, fmt.Errorf("symbol operand cannot be pre- or post-indexed") + } + ptr, err := c.ptrFromSB(operand.Sym) + return ptr, "", 0, false, err + } + if operand.Kind != OpMem { + return "", "", 0, false, fmt.Errorf("expected a memory operand") + } + if operand.Mem.Index != "" { + return "", "", 0, false, fmt.Errorf("register-indexed memory is absent from the Go 1.27 integer-pair optab") + } + if !isARM64FloatPairMemoryBase(operand.Mem.Base) { + return "", "", 0, false, fmt.Errorf("memory base must be R0-R30, RSP, SP, or ZR") + } + addr, base, increment, err := c.addrI64(operand.Mem, postIndex) + if err != nil { + return "", "", 0, false, err + } + if preIndex { + if err := c.storeReg(base, addr); err != nil { + return "", "", 0, false, err + } + } + name := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", name, addr) + return "%" + name, base, increment, postIndex, nil +} + +func (c *arm64Ctx) loadARM64IntegerPairElement(reg Reg, ptr string, elementBytes int, signed bool) error { + bits := elementBytes * 8 + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i%d, ptr %s, align 1\n", value, bits, ptr) + result := "%" + value + if bits == 32 { + wide := c.newTmp() + extension := "zext" + if signed { + extension = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s i32 %%%s to i64\n", wide, extension, value) + result = "%" + wide + } + return c.storeReg(reg, result) +} + +func (c *arm64Ctx) storeARM64IntegerPairElement(reg Reg, ptr string, elementBytes int) error { + value, err := c.loadReg(reg) + if err != nil { + return err + } + bits := elementBytes * 8 + if bits == 64 { + fmt.Fprintf(c.b, " store i64 %s, ptr %s, align 1\n", value, ptr) + return nil + } + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", narrow, value) + fmt.Fprintf(c.b, " store i32 %%%s, ptr %s, align 1\n", narrow, ptr) + return nil +} diff --git a/arm64_lower_integer_pair_test.go b/arm64_lower_integer_pair_test.go new file mode 100644 index 00000000..8babe261 --- /dev/null +++ b/arm64_lower_integer_pair_test.go @@ -0,0 +1,87 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64IntegerPairCompleteFormats(t *testing.T) { + const source = `TEXT integerPairComplete(SB),$0-0 + LDP (R0), (R1, R2) + LDP.W 16(R3), (R4, R5) + LDP.P -16(R6), (R7, R8) + LDP pairData(SB), (R9, R10) + LDPW (R11), (R12, R13) + LDPW.W 8(R14), (R15, R16) + LDPW.P -8(R17), (R19, R20) + LDPW pairData+8(SB), (R20, R21) + LDPSW (R22), (R23, R24) + LDPSW.W 8(R25), (R26, R27) + LDPSW.P -8(R20), (R21, R22) + LDPSW pairData+16(SB), (R1, R2) + STP (R3, R4), (R5) + STP.W (R6, R7), 16(R8) + STP.P (R9, R10), -16(R11) + STP (R12, R13), pairData+24(SB) + STPW (R14, R15), (R16) + STPW.W (R17, R19), 8(R20) + STPW.P (R20, R21), -8(R22) + STPW (R23, R24), pairData+40(SB) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"integerPairComplete": {Name: "integerPairComplete", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "load i64", "load i32", "sext i32", "zext i32", + "store i64", "store i32", "getelementptr i8", "pairData", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 integer-pair lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-integer-pair.ll", "arm64-integer-pair.o", ll) +} + +func TestTranslateARM64IntegerPairRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "LDP (R0), R1", + "LDP (R0)(R1), (R2, R3)", + "LDP.W pairData(SB), (R1, R2)", + "LDPSW (R0), (R1, V2)", + "STP (R0), (R1)", + "STPW (R0, R1), (R2)(R3)", + "STPW.P (R0, R1), pairData(SB)", + "STP.X (R0, R1), (R2)", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 integer-pair optab", instruction) + } + } +} diff --git a/arm64_lower_inverted_logical.go b/arm64_lower_inverted_logical.go new file mode 100644 index 00000000..8f48c6d1 --- /dev/null +++ b/arm64_lower_inverted_logical.go @@ -0,0 +1,74 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64InvertedLogical(op Op, ins Instr) (ok bool, terminated bool, err error) { + word := op == "ORNW" || op == "EONW" + exclusive := op == "EON" || op == "EONW" + if !word && !exclusive && op != "ORN" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects 2 or 3 operands: %q", op, ins.Raw) + } + if !arm64BitClearSourceValid(ins.Args[0], word) { + return true, false, fmt.Errorf("arm64 %s invalid first operand: %q", op, ins.Raw) + } + + destination := ins.Args[len(ins.Args)-1] + if destination.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s destination must be a register: %q", op, ins.Raw) + } + destinationGeneral := isARM64GeneralOrZeroReg(destination.Reg) + destinationStack := destination.Reg == SP || destination.Reg == Reg("RSP") + if !destinationGeneral && !(len(ins.Args) == 3 && ins.Args[0].Kind == OpImm && destinationStack) { + return true, false, fmt.Errorf("arm64 %s invalid destination register: %q", op, ins.Raw) + } + + leftOperand := destination + if len(ins.Args) == 3 { + leftOperand = ins.Args[1] + if leftOperand.Kind != OpReg || !isARM64GeneralOrZeroReg(leftOperand.Reg) { + return true, false, fmt.Errorf("arm64 %s second operand must be a general register: %q", op, ins.Raw) + } + } + + typeName := "i64" + right, err := c.eval64(ins.Args[0], false) + if word { + typeName = "i32" + right, err = c.eval32(ins.Args[0]) + } + if err != nil { + return true, false, err + } + left, err := c.eval64(leftOperand, false) + if word { + left, err = c.eval32(leftOperand) + } + if err != nil { + return true, false, err + } + + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, -1\n", inverted, typeName, right) + llvmOp := "or" + if exclusive { + llvmOp = "xor" + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %%%s\n", result, llvmOp, typeName, left, inverted) + value := "%" + result + if word { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, value) + value = "%" + wide + } + return true, false, c.storeReg(destination.Reg, value) +} diff --git a/arm64_lower_inverted_logical_test.go b/arm64_lower_inverted_logical_test.go new file mode 100644 index 00000000..fe007972 --- /dev/null +++ b/arm64_lower_inverted_logical_test.go @@ -0,0 +1,153 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64InvertedLogicalForms = ` +TEXT invertedlogicalforms(SB),$0-0 + ORN R0, R1 + ORN R2, R3, R4 + ORN R5>>7, R6, R7 + ORN $255, R8, R9 + ORN $255, R9, RSP + ORNW R10, R11 + ORNW R12->3, R13, R14 + ORNW $255, R15, R16 + EON R17, R19 + EON R20<<12, R21, R22 + EON $255, R23, R24 + EONW R24, R25 + EONW R26@>15, R27, R29 + EONW $255, R30, R0 + RET +` + +func TestTranslateARM64InvertedLogicalCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64InvertedLogicalForms, true) + file, err := Parse(ArchARM64, arm64InvertedLogicalForms) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"invertedlogicalforms": {Name: "invertedlogicalforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"xor i64", "or i64", "xor i32", "or i32"} { + if !strings.Contains(ir, want) { + t.Fatalf("inverted-logical family for %s omitted %q:\n%s", triple, want, ir) + } + } + compileLLVMToObject(t, llc, triple, "arm64-inverted-logical.ll", "arm64-inverted-logical.o", ir) + }) + } +} + +func TestTranslateARM64InvertedLogicalRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "ORN R0", + "ORN R0, R1, R2, R3", + "ORN (R0), R1", + "ORN R0.UXTB, R1", + "ORN RSP, R1", + "ORNW R0<<32, R1", + "EON R0, RSP", + "EONW.P R0, R1", + } { + source := "TEXT badinvertedlogical(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", + Sigs: map[string]FuncSig{"badinvertedlogical": {Name: "badinvertedlogical", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's inverted-logical optab", instruction) + } + } +} + +func TestARM64InvertedLogicalRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT invertedlogical(SB),$0-24 + MOVD first+0(FP), R0 + MOVD second+8(FP), R1 + MOVD output+16(FP), R2 + ORN R0, R1, R3 + EON R0, R1, R4 + ORNW R0, R1, R5 + EONW R0, R1, R6 + ORN R0>>8, R1, R7 + EONW $255, R1, R8 + MOVD R3, 0(R2) + MOVD R4, 8(R2) + MOVD R5, 16(R2) + MOVD R6, 24(R2) + MOVD R7, 32(R2) + MOVD R8, 40(R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"invertedlogical": { + Name: "invertedlogical", Args: []LLVMType{I64, I64, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void invertedlogical(uint64_t, uint64_t, uint64_t *); +int main(void) { + const uint64_t first = UINT64_C(0x00ff00ff8000000f); + const uint64_t second = UINT64_C(0xf000aaa055aa1234); + uint64_t got[6] = {0}; + invertedlogical(first, second, got); + const uint64_t want[6] = { + second | ~first, + second ^ ~first, + (uint32_t)second | ~(uint32_t)first, + (uint32_t)second ^ ~(uint32_t)first, + second | ~(first >> 8), + (uint32_t)second ^ ~(uint32_t)255 + }; + for (int i = 0; i < 6; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_inverted_logical", triple, ir, mainC, nil) +} diff --git a/arm64_lower_movk_complete_test.go b/arm64_lower_movk_complete_test.go new file mode 100644 index 00000000..7042f4a8 --- /dev/null +++ b/arm64_lower_movk_complete_test.go @@ -0,0 +1,72 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64MOVKCompleteFormats(t *testing.T) { + const source = `TEXT movkComplete(SB),$0-0 + MOVK $1, R1 + MOVK $(1<<12), R0 + MOVK $(2<<16), R2 + MOVK $(3<<32), R3 + MOVK $(4<<48), R4 + MOVK $5, ZR + MOVKW $6, R5 + MOVKW $(7<<16), R6 + MOVKW $8, ZR + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"movkComplete": {Name: "movkComplete", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"and i64", "or i64", "and i32", "or i32", "zext i32"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 MOVK lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-movk-complete.ll", "arm64-movk-complete.o", ll) +} + +func TestTranslateARM64MOVKRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "MOVK $0, R0", + "MOVK $0x10001, R0", + "MOVK $1, RSP", + "MOVK $1, 8(R0)", + "MOVK.P $1, R0", + "MOVKW $(1<<32), R0", + "MOVKW $-1, R0", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 MOVK optab", instruction) + } + } +} diff --git a/arm64_lower_negate.go b/arm64_lower_negate.go new file mode 100644 index 00000000..defa4566 --- /dev/null +++ b/arm64_lower_negate.go @@ -0,0 +1,189 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerNegate implements the complete Go 1.27 NEG and negate-with-carry +// families: NEG/NEGW/NEGS/NEGSW and NGC/NGCW/NGCS/NGCSW. +func (c *arm64Ctx) lowerNegate(op Op, ins Instr) (ok bool, terminated bool, err error) { + rawOp := strings.ToUpper(string(op)) + baseOp := rawOp + if dot := strings.IndexByte(baseOp, '.'); dot >= 0 { + baseOp = baseOp[:dot] + } + word, setFlags, withCarry, recognized := arm64NegateProperties(baseOp) + if !recognized { + return false, false, nil + } + originalOp := rawOp + if ins.Op != "" { + originalOp = strings.ToUpper(string(ins.Op)) + } + if originalOp != baseOp { + return true, false, fmt.Errorf("arm64 %s does not accept instruction suffixes: %q", baseOp, ins.Raw) + } + + if withCarry { + return c.lowerNegateWithCarry(baseOp, word, setFlags, ins) + } + if len(ins.Args) != 1 && len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects source[, destination]: %q", baseOp, ins.Raw) + } + source := ins.Args[0] + destination := source + if len(ins.Args) == 2 { + destination = ins.Args[1] + } + if err := validateARM64NegateSource(source, word); err != nil { + return true, false, fmt.Errorf("arm64 %s source: %w: %q", baseOp, err, ins.Raw) + } + if destination.Kind != OpReg || !isARM64GeneralOrZeroReg(destination.Reg) { + return true, false, fmt.Errorf("arm64 %s destination is outside Go 1.27's C_ZREG class: %q", baseOp, ins.Raw) + } + + if word { + sourceValue, err := c.eval32(source) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 0, %s\n", result, sourceValue) + if setFlags { + c.setFlagsSub32("0", sourceValue, "%"+result) + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, result) + return true, false, c.storeReg(destination.Reg, "%"+wide) + } + sourceValue, err := c.eval64(source, false) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i64 0, %s\n", result, sourceValue) + if setFlags { + c.setFlagsSub("0", sourceValue, "%"+result) + } + return true, false, c.storeReg(destination.Reg, "%"+result) +} + +func arm64NegateProperties(op string) (word, setFlags, withCarry, ok bool) { + switch op { + case "NEG": + return false, false, false, true + case "NEGW": + return true, false, false, true + case "NEGS": + return false, true, false, true + case "NEGSW": + return true, true, false, true + case "NGC": + return false, false, true, true + case "NGCW": + return true, false, true, true + case "NGCS": + return false, true, true, true + case "NGCSW": + return true, true, true, true + default: + return false, false, false, false + } +} + +func validateARM64NegateSource(source Operand, word bool) error { + switch source.Kind { + case OpReg: + if !isARM64GeneralOrZeroReg(source.Reg) { + return fmt.Errorf("operand is outside Go 1.27's C_ZREG class") + } + return nil + case OpRegShift: + if !isARM64GeneralOrZeroReg(source.Reg) || source.ShiftReg != "" { + return fmt.Errorf("operand is outside Go 1.27's C_SHIFT class") + } + if source.ShiftOp != ShiftLeft && source.ShiftOp != ShiftRight && source.ShiftOp != ShiftArith { + return fmt.Errorf("unsupported shift operator %q", source.ShiftOp) + } + maximum := int64(63) + if word { + maximum = 31 + } + if source.ShiftAmount < 0 || source.ShiftAmount > maximum { + return fmt.Errorf("shift amount %d is outside 0..%d", source.ShiftAmount, maximum) + } + return nil + default: + return fmt.Errorf("operand is outside Go 1.27's C_ZREG/C_SHIFT classes") + } +} + +func (c *arm64Ctx) lowerNegateWithCarry(op string, word, setFlags bool, ins Instr) (ok bool, terminated bool, err error) { + if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg || + !isARM64GeneralOrZeroReg(ins.Args[0].Reg) || !isARM64GeneralOrZeroReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm64 %s expects C_ZREG source and destination: %q", op, ins.Raw) + } + typeName := LLVMType(I64) + wideType := LLVMType("i128") + if word { + typeName = I32 + wideType = I64 + } + var source string + if word { + source, err = c.eval32(ins.Args[0]) + } else { + source, err = c.eval64(ins.Args[0], false) + } + if err != nil { + return true, false, err + } + wideSource := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", wideSource, typeName, source, wideType) + carry := c.newTmp() + borrow := c.newTmp() + wideBorrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i1, ptr %s\n", carry, c.flagsCSlot) + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", borrow, carry) + fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to %s\n", wideBorrow, borrow, wideType) + subtrahend := c.newTmp() + wideResult := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %%%s, %%%s\n", subtrahend, wideType, wideSource, wideBorrow) + fmt.Fprintf(c.b, " %%%s = sub %s 0, %%%s\n", wideResult, wideType, subtrahend) + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", result, wideType, wideResult, typeName) + resultValue := "%" + result + if setFlags { + c.setNegateWithCarryFlags(typeName, wideType, source, resultValue, "%"+subtrahend) + } + stored := resultValue + if word { + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, resultValue) + stored = "%" + wide + } + return true, false, c.storeReg(ins.Args[1].Reg, stored) +} + +func (c *arm64Ctx) setNegateWithCarryFlags(typeName, wideType LLVMType, source, result, wideSubtrahend string) { + c.flagsWritten = true + zero := c.newTmp() + negative := c.newTmp() + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, 0\n", zero, typeName, result) + fmt.Fprintf(c.b, " %%%s = icmp slt %s %s, 0\n", negative, typeName, result) + fmt.Fprintf(c.b, " %%%s = icmp uge %s 0, %s\n", carry, wideType, wideSubtrahend) + xorOperands := c.newTmp() + xorResult := c.newTmp() + overflowBits := c.newTmp() + overflow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s 0, %s\n", xorOperands, typeName, source) + fmt.Fprintf(c.b, " %%%s = xor %s 0, %s\n", xorResult, typeName, result) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", overflowBits, typeName, xorOperands, xorResult) + fmt.Fprintf(c.b, " %%%s = icmp slt %s %%%s, 0\n", overflow, typeName, overflowBits) + c.storeFlag(c.flagsNSlot, "%"+negative) + c.storeFlag(c.flagsZSlot, "%"+zero) + c.storeFlag(c.flagsCSlot, "%"+carry) + c.storeFlag(c.flagsVSlot, "%"+overflow) +} diff --git a/arm64_lower_negate_test.go b/arm64_lower_negate_test.go new file mode 100644 index 00000000..204f15c1 --- /dev/null +++ b/arm64_lower_negate_test.go @@ -0,0 +1,169 @@ +//go:build !llgo + +package plan9asm + +import ( + "os" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64NegateCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT negateforms(SB),NOSPLIT,$0-0\n") + for _, op := range []string{"NEG", "NEGW", "NEGS", "NEGSW"} { + source.WriteString("\t" + op + " R1, R2\n") + source.WriteString("\t" + op + " R2\n") + source.WriteString("\t" + op + " R3<<1, R4\n") + source.WriteString("\t" + op + " R5>>1, R6\n") + source.WriteString("\t" + op + " R7->1, R8\n") + } + for _, op := range []string{"NGC", "NGCW", "NGCS", "NGCSW"} { + source.WriteString("\t" + op + " R9, R10\n") + } + source.WriteString("\tRET\n") + + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-arm64", triple: "arm64-apple-darwin"}, + {name: "linux-arm64", triple: "aarch64-unknown-linux-gnu"}, + {name: "windows-arm64", triple: "aarch64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"negateforms": {Name: "negateforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "arm64-negate-"+target.name+".ll", "arm64-negate-"+target.name+".o", ll) + }) + } +} + +func TestTranslateARM64NegateRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "NEG $1, R0", + "NEG 0(R1), R0", + "NEG RSP, R0", + "NEG R0, RSP", + "NEG R0, R1, R2", + "NEG R1<<64, R2", + "NEGW R1<<32, R2", + "NEGS R1@>2, R2", + "NGC R1", + "NGC R1<<1, R2", + "NGCS RSP, R2", + "NGCSW R1, RSP", + "NGC.P R1, R2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchARM64, "TEXT bad(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 NEG/NGC tables", instruction) + } + }) + } +} + +func TestARM64NegateRuntimeSemantics(t *testing.T) { + crossLinux := runtime.GOOS == "linux" && runtime.GOARCH == "amd64" && os.Getenv("PLAN9ASM_CROSS_EXEC") == "1" + if runtime.GOARCH != "arm64" && !crossLinux { + t.Skip("runtime execution test only runs on an arm64 host") + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compiler := []string{} + var runPrefix []string + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + if crossLinux { + compiler = []string{"aarch64-linux-gnu-gcc"} + runPrefix = []string{"qemu-aarch64", "-L", "/usr/aarch64-linux-gnu"} + triple = "aarch64-unknown-linux-gnu" + } else { + _, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("clang not found") + } + compiler = []string{clang} + } + + const source = ` +TEXT negatesemantics(SB),NOSPLIT,$0-8 + MOVD out+0(FP), R20 + MOVD $5, R0 + NEGS R0, R1 + CSET CS, R2 + CSET MI, R3 + NGCS R0, R4 + MOVD R1, 0(R20) + MOVD R2, 8(R20) + MOVD R3, 16(R20) + MOVD R4, 24(R20) + NEGS ZR, R5 + NGC R0, R6 + MOVD R6, 32(R20) + MOVD $0x80000000, R7 + NEGSW R7, R8 + CSET VS, R9 + MOVD R8, 40(R20) + MOVD R9, 48(R20) + NGCW R0, R10 + MOVD R10, 56(R20) + RET +` + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "negatesemantics": { + Name: "negatesemantics", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void negatesemantics(uint64_t *); +int main(void) { + uint64_t got[8] = {0}; + const uint64_t want[8] = { + UINT64_MAX-4, 0, 1, UINT64_MAX-5, + UINT64_MAX-4, 0x80000000ULL, 1, 0xfffffffaULL + }; + negatesemantics(got); + for (int i = 0; i < 8; i++) if (got[i] != want[i]) return i+1; + return 0; +} +` + compileAndRunRuntimeTestWithCompiler(t, llc, compiler, "arm64_negate", triple, ll, mainC, runPrefix) +} diff --git a/arm64_lower_pc_relative.go b/arm64_lower_pc_relative.go new file mode 100644 index 00000000..4aa9eee5 --- /dev/null +++ b/arm64_lower_pc_relative.go @@ -0,0 +1,53 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerPCRelativeAddress(bi int, op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "ADR", "ADRP": + default: + return false, false, nil + } + if strings.Contains(strings.ToUpper(string(ins.Op)), ".") { + return true, false, fmt.Errorf("arm64 %s does not accept a suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 || ins.Args[1].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm64 %s expects label|n(PC), general register: %q", op, ins.Raw) + } + + target, targetOK := c.resolveBranchTarget(bi, ins.Args[0]) + if !targetOK || (ins.Args[0].Kind != OpIdent && ins.Args[0].Kind != OpSym && + (ins.Args[0].Kind != OpMem || ins.Args[0].Mem.Base != PC)) { + return true, false, fmt.Errorf("arm64 %s expects label|n(PC), general register: %q", op, ins.Raw) + } + if ins.Args[0].Kind == OpSym && strings.HasSuffix(ins.Args[0].Sym, "(SB)") { + return true, false, fmt.Errorf("arm64 %s expects a local label or n(PC): %q", op, ins.Raw) + } + knownTarget := false + for _, block := range c.blocks { + if block.name == target { + knownTarget = true + break + } + } + if !knownTarget { + return true, false, fmt.Errorf("arm64 %s undefined local target %q: %q", op, target, ins.Raw) + } + + address := c.newTmp() + if global, ok := c.rawDataGlobals[target]; ok { + fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %s to i64\n", address, llvmGlobal(global)) + } else { + fmt.Fprintf(c.b, " %%%s = ptrtoint ptr blockaddress(%s, %%%s) to i64\n", address, llvmGlobal(c.sig.Name), arm64LLVMBlockName(target)) + } + value := "%" + address + if op == "ADRP" { + page := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, -4096\n", page, value) + value = "%" + page + } + return true, false, c.storeReg(ins.Args[1].Reg, value) +} diff --git a/arm64_lower_pc_relative_test.go b/arm64_lower_pc_relative_test.go new file mode 100644 index 00000000..e43b94c2 --- /dev/null +++ b/arm64_lower_pc_relative_test.go @@ -0,0 +1,90 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64PCRelativeAddressCompleteGoAssemblerForms(t *testing.T) { + const source = ` +TEXT pcRelativeAddressForms(SB),$0-0 + ADR target, R0 + ADRP target, R1 + ADR -2(PC), R2 + ADR 2(PC), R3 + ADRP -2(PC), R29 + ADRP 2(PC), R30 + ADR target, ZR + ADRP target, ZR +target: + RET +` + requireARM64GoAssemblerResult(t, source, true) + + for _, target := range []struct { + name string + triple string + }{ + {name: "darwin-arm64", triple: "arm64-apple-darwin"}, + {name: "linux-arm64", triple: "aarch64-unknown-linux-gnu"}, + {name: "windows-arm64", triple: "aarch64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "pcRelativeAddressForms": {Name: "pcRelativeAddressForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if got := strings.Count(ll, "blockaddress("); got != 8 { + t.Fatalf("emitted %d block addresses, want 8:\n%s", got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, target.triple, "arm64-pc-relative-"+target.name+".ll", "arm64-pc-relative-"+target.name+".o", ll) + }) + } +} + +func TestTranslateARM64PCRelativeAddressRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "ADR R1, R2", + "ADR $1, R2", + "ADR target, RSP", + "ADR target, V0", + "ADR target", + "ADR target, R1, R2", + "ADRP 0(R1), R2", + "ADRP.P target, R2", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badPCRelativeAddress(SB),$0-0\n\t" + instruction + "\ntarget:\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badPCRelativeAddress": {Name: "badPCRelativeAddress", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 ADR/ADRP table", instruction) + } + }) + } +} diff --git a/arm64_lower_permute.go b/arm64_lower_permute.go new file mode 100644 index 00000000..26fcff88 --- /dev/null +++ b/arm64_lower_permute.go @@ -0,0 +1,99 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorPermute(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "VZIP1", "VZIP2", "VUZP1", "VUZP2", "VTRN1", "VTRN2": + default: + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects three same-arrangement vector registers: %q", op, ins.Raw) + } + allowed := func(a arm64VectorArrangement) bool { + return (a.elementBits == 8 && (a.lanes == 8 || a.lanes == 16)) || + (a.elementBits == 16 && (a.lanes == 4 || a.lanes == 8)) || + (a.elementBits == 32 && (a.lanes == 2 || a.lanes == 4)) || + (a.elementBits == 64 && a.lanes == 2) + } + var arrangement arm64VectorArrangement + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || !allowed(parsed) { + return true, false, fmt.Errorf("arm64 %s has an invalid vector arrangement: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + + // Go's Plan 9 order is Vm, Vn, Vd, while the architectural operation is + // written Vd, Vn, Vm. Keep Vn as LLVM's first shuffle input so the masks + // below follow the ARM lane descriptions directly. + m, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + n, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + mask := arm64VectorPermuteMask(string(op), arrangement.lanes) + if len(mask) != arrangement.lanes { + return true, false, fmt.Errorf("arm64 %s could not construct a vector shuffle mask: %q", op, ins.Raw) + } + result := c.newTmp() + fmt.Fprintf(c.b, " ; arm64 vector permute %s\n", op) + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %s, <%d x i%d> %s, <%d x i32> <", result, arrangement.lanes, arrangement.elementBits, n, arrangement.lanes, arrangement.elementBits, m, arrangement.lanes) + for i, lane := range mask { + if i != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", lane) + } + c.b.WriteString(">\n") + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, "%"+result) +} + +func arm64VectorPermuteMask(op string, lanes int) []int { + mask := make([]int, 0, lanes) + switch op { + case "VZIP1", "VZIP2": + start := 0 + if op == "VZIP2" { + start = lanes / 2 + } + for lane := start; lane < start+lanes/2; lane++ { + mask = append(mask, lane, lanes+lane) + } + case "VUZP1", "VUZP2": + start := 0 + if op == "VUZP2" { + start = 1 + } + for lane := start; lane < lanes; lane += 2 { + mask = append(mask, lane) + } + for lane := start; lane < lanes; lane += 2 { + mask = append(mask, lanes+lane) + } + case "VTRN1", "VTRN2": + start := 0 + if op == "VTRN2" { + start = 1 + } + for lane := start; lane < lanes; lane += 2 { + mask = append(mask, lane, lanes+lane) + } + } + return mask +} diff --git a/arm64_lower_permute_test.go b/arm64_lower_permute_test.go new file mode 100644 index 00000000..43ded503 --- /dev/null +++ b/arm64_lower_permute_test.go @@ -0,0 +1,169 @@ +//go:build !llgo + +package plan9asm + +import ( + "os" + "os/exec" + "path/filepath" + "runtime" + "strconv" + "strings" + "testing" +) + +func TestTranslateARM64VectorPermuteCompleteGoAssemblerForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT ·vectorpermuteforms(SB), $0-0\n") + for _, op := range []string{"VZIP1", "VZIP2", "VUZP1", "VUZP2", "VTRN1", "VTRN2"} { + for _, arrangement := range []string{"B8", "B16", "H4", "H8", "S2", "S4", "D2"} { + src.WriteString("\t" + op + " V0." + arrangement + ", V1." + arrangement + ", V2." + arrangement + "\n") + } + } + src.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, src.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorpermuteforms": {Name: "vectorpermuteforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + // The 42 operations each emit one result shuffle. The three 64-bit + // arrangements also narrow both inputs, adding 36 shuffles. + if got := strings.Count(ll, "shufflevector"); got != 78 { + t.Fatalf("%s emitted %d vector shuffles, want 78:\n%s", triple, got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-permute.ll", "arm64-vector-permute.o", ll) + } +} + +func TestTranslateARM64VectorPermuteRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VZIP1 V0.B8, V1.B8", + "VUZP2 V0.B8, V1.B16, V2.B8", + "VTRN1 V0.D1, V1.D1, V2.D1", + "VTRN2 V0.S4, V1.S4, V2.S4, V3.S4", + "VZIP2 V0, V1, V2", + "VUZP1.P V0.B16, V1.B16, V2.B16", + } { + t.Run(strings.Fields(instruction)[0]+"-"+strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT ·badvectorpermute(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, src, false) + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badvectorpermute": {Name: "badvectorpermute", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector permute optab", instruction) + } + }) + } +} + +func requireARM64GoAssemblerResult(t *testing.T, src string, wantSuccess bool) { + requireARM64GoAssemblerResultWithExperiment(t, src, wantSuccess, "") +} + +func requireARM64SVEGoAssemblerResult(t *testing.T, src string, wantSuccess bool) { + requireARM64GoAssemblerResultWithExperiment(t, src, wantSuccess, "simd") +} + +func requireARM64GoAssemblerResultWithExperiment(t *testing.T, src string, wantSuccess bool, experiment string) { + t.Helper() + // These fixtures are derived from the Go 1.27 assembler tables. Older Go + // compatibility lanes must still parse, translate, and compile them through + // LLVM 22, but their own assembler cannot serve as the 1.27 form oracle. + if !goToolchainAtLeast(runtime.Version(), 1, 27) { + return + } + dir := t.TempDir() + asm := filepath.Join(dir, "forms.s") + if err := os.WriteFile(asm, []byte(src), 0o600); err != nil { + t.Fatal(err) + } + cmd := exec.Command("go", "tool", "asm", "-p", "example.com/forms", "-o", filepath.Join(dir, "forms.o"), asm) + cmd.Env = append(os.Environ(), "GOOS=linux", "GOARCH=arm64") + if experiment != "" { + cmd.Env = append(cmd.Env, "GOEXPERIMENT="+experiment) + } + out, err := cmd.CombinedOutput() + if wantSuccess && err != nil { + t.Fatalf("Go 1.27 assembler rejected accepted forms: %v\n%s", err, out) + } + if !wantSuccess && err == nil { + t.Fatalf("Go 1.27 assembler accepted a form expected outside the optab:\n%s", src) + } +} + +func goToolchainAtLeast(version string, wantMajor, wantMinor int) bool { + start := strings.Index(version, "go") + if start < 0 { + return false + } + parts := strings.SplitN(version[start+2:], ".", 3) + if len(parts) < 2 { + return false + } + major, err := strconv.Atoi(parts[0]) + if err != nil { + return false + } + minorText := parts[1] + end := 0 + for end < len(minorText) && minorText[end] >= '0' && minorText[end] <= '9' { + end++ + } + if end == 0 { + return false + } + minor, err := strconv.Atoi(minorText[:end]) + if err != nil { + return false + } + return major > wantMajor || major == wantMajor && minor >= wantMinor +} + +func TestGoToolchainAtLeast(t *testing.T) { + tests := []struct { + version string + want bool + }{ + {version: "go1.26.9", want: false}, + {version: "go1.27", want: true}, + {version: "go1.27rc1", want: true}, + {version: "go1.28.0", want: true}, + {version: "devel go1.28-abcdef", want: true}, + {version: "devel", want: false}, + } + for _, test := range tests { + if got := goToolchainAtLeast(test.version, 1, 27); got != test.want { + t.Errorf("goToolchainAtLeast(%q, 1, 27) = %v, want %v", test.version, got, test.want) + } + } +} diff --git a/arm64_lower_pointer_auth_hint_test.go b/arm64_lower_pointer_auth_hint_test.go new file mode 100644 index 00000000..91b43789 --- /dev/null +++ b/arm64_lower_pointer_auth_hint_test.go @@ -0,0 +1,71 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64PointerAuthHintCompleteForms(t *testing.T) { + const source = `TEXT pointerAuthHints(SB),$0-0 + BTI C + BTI J + BTI JC + PACIASP + PACIBSP + AUTIASP + AUTIBSP + AUTIA1716 + AUTIB1716 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"pointerAuthHints": {Name: "pointerAuthHints", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, immediate := range []string{"hint #34", "hint #36", "hint #38", "hint #25", "hint #27", "hint #29", "hint #31", "hint #12", "hint #14"} { + if !strings.Contains(ll, immediate) { + t.Fatalf("ARM64 pointer-auth hint lowering omitted %q:\n%s", immediate, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-pointer-auth-hints.ll", "arm64-pointer-auth-hints.o", ll) +} + +func TestTranslateARM64PointerAuthHintRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "BTI", + "BTI BAD", + "BTI C, J", + "BTI.P C", + "PACIASP R0", + "AUTIA1716.P", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 pointer-auth hint optab", instruction) + } + } +} diff --git a/arm64_lower_polynomial_multiply.go b/arm64_lower_polynomial_multiply.go new file mode 100644 index 00000000..3fa40eff --- /dev/null +++ b/arm64_lower_polynomial_multiply.go @@ -0,0 +1,96 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerARM64PolynomialMultiply implements the complete AVPMULL optab row. +// Go accepts the low/high halves of B8/B16 -> H8 and D1/D2 -> Q1. LLVM's +// AArch64 intrinsics preserve carry-less (GF(2)) multiplication semantics. +func (c *arm64Ctx) lowerARM64PolynomialMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VPMULL" && op != "VPMULL2" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects two polynomial vector sources and one widened destination, with no suffix: %q", op, ins.Raw) + } + for _, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + } + + firstArrangement, firstOK := parseARM64VectorArrangement(ins.Args[0].Reg) + secondArrangement, secondOK := parseARM64VectorArrangement(ins.Args[1].Reg) + if !firstOK || !secondOK || firstArrangement != secondArrangement { + return true, false, fmt.Errorf("arm64 %s requires matching B8/B16 or D1/D2 source arrangements: %q", op, ins.Raw) + } + highHalf := op == "VPMULL2" + + switch { + case arm64VectorRegHasExactArrangement(ins.Args[2].Reg, "H8"): + wantLanes := 8 + if highHalf { + wantLanes = 16 + } + if firstArrangement.elementBits != 8 || firstArrangement.lanes != wantLanes { + return true, false, fmt.Errorf("arm64 %s H8 result requires B%d sources: %q", op, wantLanes, ins.Raw) + } + first, err := c.loadARM64VectorInteger(ins.Args[0].Reg, firstArrangement) + if err != nil { + return true, false, err + } + second, err := c.loadARM64VectorInteger(ins.Args[1].Reg, secondArrangement) + if err != nil { + return true, false, err + } + if highHalf { + destination := arm64VectorArrangement{elementBits: 16, lanes: 8} + first = c.selectARM64VectorHighHalf(firstArrangement, destination.lanes, first) + second = c.selectARM64VectorHighHalf(secondArrangement, destination.lanes, second) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %s, <8 x i8> %s)\n", result, first, second) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arm64VectorArrangement{elementBits: 16, lanes: 8}, "%"+result) + + case arm64VectorRegHasExactArrangement(ins.Args[2].Reg, "Q1"): + wantLanes := 1 + if highHalf { + wantLanes = 2 + } + if firstArrangement.elementBits != 64 || firstArrangement.lanes != wantLanes { + return true, false, fmt.Errorf("arm64 %s Q1 result requires D%d sources: %q", op, wantLanes, ins.Raw) + } + first, err := c.loadARM64VectorInteger(ins.Args[0].Reg, firstArrangement) + if err != nil { + return true, false, err + } + second, err := c.loadARM64VectorInteger(ins.Args[1].Reg, secondArrangement) + if err != nil { + return true, false, err + } + lane := 0 + if highHalf { + lane = 1 + } + firstScalar := c.newTmp() + secondScalar := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %s, i32 %d\n", firstScalar, firstArrangement.lanes, first, lane) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i64> %s, i32 %d\n", secondScalar, secondArrangement.lanes, second, lane) + fmt.Fprintf(c.b, " %%%s = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %%%s, i64 %%%s)\n", result, firstScalar, secondScalar) + return true, false, c.storeVReg(ins.Args[2].Reg, "%"+result) + + default: + return true, false, fmt.Errorf("arm64 %s destination must be H8 or Q1: %q", op, ins.Raw) + } +} + +func arm64VectorRegHasExactArrangement(reg Reg, arrangement string) bool { + if _, ok := arm64ParseVReg(reg); !ok { + return false + } + s := strings.ToUpper(strings.TrimSpace(string(reg))) + return strings.HasSuffix(s, "."+arrangement) +} diff --git a/arm64_lower_polynomial_multiply_test.go b/arm64_lower_polynomial_multiply_test.go new file mode 100644 index 00000000..cef8dc85 --- /dev/null +++ b/arm64_lower_polynomial_multiply_test.go @@ -0,0 +1,88 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64PolynomialMultiplyCompleteGoAssemblerForms(t *testing.T) { + const source = `TEXT ·polynomialMultiplyForms(SB), $0-0 + VPMULL V0.B8, V1.B8, V2.H8 + VPMULL2 V3.B16, V4.B16, V5.H8 + VPMULL V6.D1, V7.D1, V8.Q1 + VPMULL2 V9.D2, V10.D2, V11.Q1 + RET +` + requireARM64GoAssemblerResult(t, source, true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "polynomialMultiplyForms": {Name: "polynomialMultiplyForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{ + "llvm.aarch64.neon.pmull.v8i16", + "llvm.aarch64.neon.pmull64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s polynomial-multiply IR omitted %q:\n%s", triple, want, ll) + } + } + if !strings.Contains(ll, `"target-features"="+aes"`) { + t.Fatalf("%s polynomial-multiply function omitted +aes:\n%s", triple, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-polynomial-multiply.ll", "arm64-polynomial-multiply.o", ll) + } +} + +func TestTranslateARM64PolynomialMultiplyRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VPMULL V0.B16, V1.B16, V2.H8", + "VPMULL2 V0.B8, V1.B8, V2.H8", + "VPMULL V0.H4, V1.H4, V2.S4", + "VPMULL V0.S2, V1.S2, V2.D2", + "VPMULL V0.D2, V1.D2, V2.Q1", + "VPMULL V0.D1, V1.D1, V2.D2", + "VPMULL.P V0.B8, V1.B8, V2.H8", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT ·badPolynomialMultiply(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badPolynomialMultiply": {Name: "badPolynomialMultiply", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go's VPMULL/VPMULL2 optab", instruction) + } + }) + } +} diff --git a/arm64_lower_prefetch.go b/arm64_lower_prefetch.go new file mode 100644 index 00000000..5088703a --- /dev/null +++ b/arm64_lower_prefetch.go @@ -0,0 +1,149 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64PrefetchOperation string + +// arm64PrefetchOperations mirrors Go's prfopfield table. +var arm64PrefetchOperations = map[arm64PrefetchOperation]uint8{ + "PLDL1KEEP": 0, + "PLDL1STRM": 1, + "PLDL2KEEP": 2, + "PLDL2STRM": 3, + "PLDL3KEEP": 4, + "PLDL3STRM": 5, + "PLIL1KEEP": 8, + "PLIL1STRM": 9, + "PLIL2KEEP": 10, + "PLIL2STRM": 11, + "PLIL3KEEP": 12, + "PLIL3STRM": 13, + "PSTL1KEEP": 16, + "PSTL1STRM": 17, + "PSTL2KEEP": 18, + "PSTL2STRM": 19, + "PSTL3KEEP": 20, + "PSTL3STRM": 21, +} + +func (c *arm64Ctx) lowerARM64Prefetch(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op == "RPRFM" { + return c.lowerARM64RangePrefetch(ins) + } + if op != "PRFM" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != "PRFM" || len(ins.Args) != 2 || ins.Args[0].Kind != OpMem { + return true, false, fmt.Errorf("arm64 PRFM expects unsigned-scaled memory and a prefetch operation, with no suffix: %q", ins.Raw) + } + memory := ins.Args[0].Mem + validBase := isARM64GeneralOrZeroReg(memory.Base) || memory.Base == SP || memory.Base == Reg("RSP") + if !validBase || memory.Sym != "" || memory.Index != "" || memory.OffRaw != "" || !arm64PRFMOffsetAccepted(memory.Off) { + return true, false, fmt.Errorf("arm64 PRFM address is outside Go's C_UOREG32K class: %q", ins.Raw) + } + + var hint uint8 + switch operation := ins.Args[1]; operation.Kind { + case OpIdent: + name := arm64PrefetchOperation(strings.ToUpper(strings.TrimSpace(operation.Ident))) + value, exists := arm64PrefetchOperations[name] + if !exists { + return true, false, fmt.Errorf("arm64 PRFM operation %q is outside Go's prfopfield table: %q", name, ins.Raw) + } + hint = value + case OpImm: + if operation.ImmRaw != "" || operation.Imm < 0 || operation.Imm > 31 { + return true, false, fmt.Errorf("arm64 PRFM numeric operation must be in [0,31]: %q", ins.Raw) + } + hint = uint8(operation.Imm) + default: + return true, false, fmt.Errorf("arm64 PRFM operation must be a Go prfop name or $0..$31: %q", ins.Raw) + } + + baseReg := memory.Base + if baseReg == ZR { + // Register number 31 in an AArch64 memory operand denotes SP. Go's + // parser accepts ZR here and its encoder consequently emits SP. + baseReg = SP + } + base, err := c.loadReg(baseReg) + if err != nil { + return true, false, err + } + // Go's case-91 encoder shifts directly and therefore discards the low + // three offset bits without issuing offsetshift's usual odd-offset error. + encodedOffset := memory.Off &^ 7 + assembly := fmt.Sprintf("prfm #%d, [$0, #%d]", hint, encodedOffset) + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(i64 %s)\n", assembly, "r,~{memory}", base) + return true, false, nil +} + +var arm64RangePrefetchOperations = map[string]uint8{ + "PLDKEEP": 0, + "PSTKEEP": 1, + "PLDSTRM": 4, + "PSTSTRM": 5, +} + +func (c *arm64Ctx) lowerARM64RangePrefetch(ins Instr) (ok bool, terminated bool, err error) { + if strings.ToUpper(string(ins.Op)) != "RPRFM" || len(ins.Args) != 3 || ins.Args[0].Kind != OpMem { + return true, false, fmt.Errorf("arm64 RPRFM expects (Rn), Rm, operation without a suffix: %q", ins.Raw) + } + memory := ins.Args[0].Mem + base, baseOK := arm64SVEAddressReg(Operand{Kind: OpReg, Reg: memory.Base}, true) + rangeRegister, rangeOK := arm64SVEAddressReg(ins.Args[1], false) + if !baseOK || !rangeOK || memory.Sym != "" || memory.Off != 0 || memory.OffRaw != "" || memory.Index != "" { + return true, false, fmt.Errorf("arm64 RPRFM requires an unoffset R0..R30/RSP base and R0..R30 range register: %q", ins.Raw) + } + var hint uint8 + switch operation := ins.Args[2]; operation.Kind { + case OpIdent: + var exists bool + hint, exists = arm64RangePrefetchOperations[strings.ToUpper(strings.TrimSpace(operation.Ident))] + if !exists { + return true, false, fmt.Errorf("arm64 RPRFM operation must be PLDKEEP, PSTKEEP, PLDSTRM, or PSTSTRM: %q", ins.Raw) + } + case OpImm: + if operation.ImmRaw != "" || operation.ImmIsFloat || operation.Imm < 0 || operation.Imm > 63 { + return true, false, fmt.Errorf("arm64 RPRFM numeric operation must be in [0,63]: %q", ins.Raw) + } + hint = uint8(operation.Imm) + default: + return true, false, fmt.Errorf("arm64 RPRFM operation must be a range-prefetch name or $0..$63: %q", ins.Raw) + } + baseValue, err := c.loadReg(base) + if err != nil { + return true, false, err + } + rangeValue, err := c.loadReg(rangeRegister) + if err != nil { + return true, false, err + } + assembly := fmt.Sprintf("rprfm #%d, $1, [$0]", hint) + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(i64 %s, i64 %s)\n", assembly, "r,r,~{memory}", baseValue, rangeValue) + return true, false, nil +} + +// arm64PRFMOffsetAccepted mirrors autoclass/oregclass plus cmp(C_UOREG32K, +// class) in Go's ARM64 backend. Some smaller compatible address classes admit +// offsets that are not multiples of eight; case 91 then truncates their low +// three bits. +func arm64PRFMOffsetAccepted(offset int64) bool { + switch { + case offset < 0: + return false + case offset <= 255: + return true + case offset <= 504: + return offset%8 == 0 + case offset <= 1008: + return offset%16 == 0 + case offset <= 32760: + return offset%8 == 0 + default: + return false + } +} diff --git a/arm64_lower_prefetch_test.go b/arm64_lower_prefetch_test.go new file mode 100644 index 00000000..73502faf --- /dev/null +++ b/arm64_lower_prefetch_test.go @@ -0,0 +1,121 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +const arm64PrefetchForms = ` +TEXT prefetchforms(SB),$0-0 + PRFM (R0), PLDL1KEEP + PRFM 8(R1), PLDL1STRM + PRFM 16(R2), PLDL2KEEP + PRFM 24(R3), PLDL2STRM + PRFM 32(R4), PLDL3KEEP + PRFM 40(R5), PLDL3STRM + PRFM 48(R6), PLIL1KEEP + PRFM 56(R7), PLIL1STRM + PRFM 64(R8), PLIL2KEEP + PRFM 72(R9), PLIL2STRM + PRFM 80(R10), PLIL3KEEP + PRFM 88(R11), PLIL3STRM + PRFM 96(R12), PSTL1KEEP + PRFM 104(R13), PSTL1STRM + PRFM 112(R14), PSTL2KEEP + PRFM 120(R15), PSTL2STRM + PRFM 128(R16), PSTL3KEEP + PRFM 136(R17), PSTL3STRM + PRFM (RSP), $0 + // Go accepts ZR in this address position; encoding register 31 means SP. + PRFM (ZR), $1 + // Go accepts every non-negative C_UOREG32K offset and the PRFM encoder + // discards its low three bits rather than diagnosing offsets admitted by a + // smaller compatible class. + PRFM 1(R20), $31 + PRFM 8(R21), $30 + PRFM 4088(R22), PLDL1KEEP + PRFM 8184(R23), PLDL1KEEP + PRFM 16376(R24), PLDL1KEEP + PRFM 32760(R19), PLDL1KEEP + RET +` + +func TestTranslateARM64PrefetchCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64PrefetchForms, true) + + for _, triple := range []string{ + "arm64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, arm64PrefetchForms) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"prefetchforms": {Name: "prefetchforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if got := strings.Count(ll, `asm sideeffect "prfm #`); got != 26 { + t.Fatalf("ARM64 PRFM lowering emitted %d prefetch operations, want 26:\n%s", got, ll) + } + for _, want := range []string{ + `asm sideeffect "prfm #0, [$0, #0]"`, + `asm sideeffect "prfm #13, [$0, #88]"`, + `asm sideeffect "prfm #21, [$0, #136]"`, + `asm sideeffect "prfm #31, [$0, #0]"`, + `asm sideeffect "prfm #30, [$0, #8]"`, + `asm sideeffect "prfm #0, [$0, #4088]"`, + `asm sideeffect "prfm #0, [$0, #32760]"`, + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 PRFM lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-prefetch.ll", "arm64-prefetch.o", ll) + }) + } +} + +func TestTranslateARM64PrefetchRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "PRFM -8(R0), PLDL1KEEP", + "PRFM 257(R0), PLDL1KEEP", + "PRFM 505(R0), PLDL1KEEP", + "PRFM 4097(R0), PLDL1KEEP", + "PRFM 8191(R0), PLDL1KEEP", + "PRFM 16381(R0), PLDL1KEEP", + "PRFM 32761(R0), PLDL1KEEP", + "PRFM 32768(R0), PLDL1KEEP", + "PRFM (R0), PLDKEEP", + "PRFM (R0), $32", + "PRFM R0, PLDL1KEEP", + "PRFM (R0)", + "PRFM.P (R0), PLDL1KEEP", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's PRFM forms", instruction) + } + } +} diff --git a/arm64_lower_range_prefetch_test.go b/arm64_lower_range_prefetch_test.go new file mode 100644 index 00000000..d4648b26 --- /dev/null +++ b/arm64_lower_range_prefetch_test.go @@ -0,0 +1,72 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64RangePrefetchCompleteGo127Family(t *testing.T) { + source := `TEXT range_prefetch_forms(SB),$0-0 + RPRFM (R0), R30, PLDKEEP + RPRFM (R1), R2, PSTKEEP + RPRFM (R2), R3, PLDSTRM + RPRFM (RSP), R4, PSTSTRM + RPRFM (R5), R6, $0 + RPRFM (R7), R8, $63 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"range_prefetch_forms": {Name: "range_prefetch_forms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `asm sideeffect "rprfm #0, $1, [$0]"`, + `asm sideeffect "rprfm #5, $1, [$0]"`, + `asm sideeffect "rprfm #63, $1, [$0]"`, + `"r,r,~{memory}"`, + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s ARM64 range-prefetch lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-range-prefetch.ll", "arm64-range-prefetch.o", ll) + }) + } +} + +func TestTranslateARM64RangePrefetchRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "RPRFM 8(R1), R2, PLDKEEP", + "RPRFM (R1)(R2), R3, PLDKEEP", + "RPRFM (R1), RZR, PLDKEEP", + "RPRFM (R1), R2, PLDL1KEEP", + "RPRFM (R1), R2, $-1", + "RPRFM (R1), R2, $64", + "RPRFM.Z (R1), R2, PLDKEEP", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badrangeprefetch(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badrangeprefetch": {Name: "badrangeprefetch", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's RPRFM forms", instruction) + } + }) + } +} diff --git a/arm64_lower_rounding_variable_shift_test.go b/arm64_lower_rounding_variable_shift_test.go new file mode 100644 index 00000000..ea98f537 --- /dev/null +++ b/arm64_lower_rounding_variable_shift_test.go @@ -0,0 +1,133 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64VariableShift(base uint32, elementBits int, fullVector bool, shifts, value, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + word := base | size<<22 | uint32(shifts)<<16 | uint32(value)<<5 | uint32(destination) + if fullVector { + word |= 1 << 30 + } + return word +} + +func TestTranslateARM64RawVariableShiftCompleteArchitectureFamily(t *testing.T) { + families := []struct { + name string + base uint32 + }{ + {name: "VSSHL", base: 0x0e204400}, + {name: "VSRSHL", base: 0x0e205400}, + {name: "VUSHL", base: 0x2e204400}, + {name: "VURSHL", base: 0x2e205400}, + } + type form struct { + elementBits int + fullVector bool + } + forms := []form{ + {elementBits: 8}, {elementBits: 8, fullVector: true}, + {elementBits: 16}, {elementBits: 16, fullVector: true}, + {elementBits: 32}, {elementBits: 32, fullVector: true}, + {elementBits: 64, fullVector: true}, + } + + var source strings.Builder + source.WriteString("TEXT ·variableShiftArchitectureForms(SB), $0-0\n") + for _, family := range families { + for _, form := range forms { + word := encodeARM64VariableShift(family.base, form.elementBits, form.fullVector, 30, 29, 28) + decoded, err := decodeARM64RawWordInstruction(Instr{Op: OpWORD, Args: []Operand{{Kind: OpImm, Imm: int64(word)}}}) + if err != nil { + t.Fatalf("decode %s %d-bit Q=%v: %v", family.name, form.elementBits, form.fullVector, err) + } + if decoded.Op != Op(family.name) || len(decoded.Args) != 3 || + !strings.HasPrefix(string(decoded.Args[0].Reg), "V30.") || + !strings.HasPrefix(string(decoded.Args[1].Reg), "V29.") || + !strings.HasPrefix(string(decoded.Args[2].Reg), "V28.") { + t.Fatalf("decoded %s %d-bit Q=%v %#08x as %#v; want reversed Vm=V30, Vn=V29, Vd=V28", family.name, form.elementBits, form.fullVector, word, decoded) + } + fmt.Fprintf(&source, "\tWORD $%#08x // %s %d-bit Q=%v\n", word, family.name, form.elementBits, form.fullVector) + } + // The architecture has one additional scalar D form. It shares the + // size=3 encoding but has Q=0 and decodes to bare V registers. + scalarBase := family.base | 0x50000000 + word := encodeARM64VariableShift(scalarBase, 64, false, 30, 29, 28) + decoded, err := decodeARM64RawWordInstruction(Instr{Op: OpWORD, Args: []Operand{{Kind: OpImm, Imm: int64(word)}}}) + if err != nil { + t.Fatalf("decode scalar %s: %v", family.name, err) + } + if decoded.Op != Op(family.name) || len(decoded.Args) != 3 || decoded.Args[0].Reg != "V30" || decoded.Args[1].Reg != "V29" || decoded.Args[2].Reg != "V28" { + t.Fatalf("decoded scalar %s %#08x as %#v; want V30, V29, V28", family.name, word, decoded) + } + fmt.Fprintf(&source, "\tWORD $%#08x // scalar %s D\n", word, family.name) + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "variableShiftArchitectureForms": {Name: "variableShiftArchitectureForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{"sshl", "srshl", "ushl", "urshl"} { + if got := strings.Count(ll, " = call "); got != 32 { + t.Fatalf("%s emitted %d intrinsic calls, want 32:\n%s", triple, got, ll) + } + if !strings.Contains(ll, "@llvm.aarch64.neon."+intrinsic+".i64") || !strings.Contains(ll, "@llvm.aarch64.neon."+intrinsic+".v16i8") { + t.Fatalf("%s omitted scalar or vector %s intrinsic:\n%s", triple, intrinsic, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-variable-shift.ll", "arm64-variable-shift.o", ll) + }) + } +} + +func TestTranslateARM64VariableShiftRejectsInvalidArchitectureForms(t *testing.T) { + for _, instruction := range []string{ + "VSRSHL V0.B8, V1.B8", + "VURSHL V0.B8, V1.B16, V2.B8", + "VSRSHL V0.D1, V1.D1, V2.D1", + "VURSHL V0, V1.D2, V2.D2", + "VSRSHL.P V0.H8, V1.H8, V2.H8", + } { + file, err := Parse(ArchARM64, "TEXT ·badVariableShift(SB), $0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{"badVariableShift": {Name: "badVariableShift", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted invalid ARM64 variable-shift form %q", instruction) + } + } +} diff --git a/arm64_lower_saturating_arithmetic.go b/arm64_lower_saturating_arithmetic.go new file mode 100644 index 00000000..b503dfa3 --- /dev/null +++ b/arm64_lower_saturating_arithmetic.go @@ -0,0 +1,49 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorSaturatingArithmetic(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, handled := map[Op]string{ + "VSQADD": "sadd.sat", + "VUQADD": "uadd.sat", + "VSQSUB": "ssub.sat", + "VUQSUB": "usub.sat", + }[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects three same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + var arrangement arm64VectorArrangement + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || parsed.elementBits == 64 && parsed.lanes != 2 { + return true, false, fmt.Errorf("arm64 %s accepts only B8/B16/H4/H8/S2/S4/D2 arrangements: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + source, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + base, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + vectorType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, arrangement.elementBits) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.v%di%d(%s %s, %s %s)\n", + result, vectorType, intrinsic, arrangement.lanes, arrangement.elementBits, vectorType, base, vectorType, source) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, "%"+result) +} diff --git a/arm64_lower_saturating_arithmetic_test.go b/arm64_lower_saturating_arithmetic_test.go new file mode 100644 index 00000000..0ef4895d --- /dev/null +++ b/arm64_lower_saturating_arithmetic_test.go @@ -0,0 +1,81 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorSaturatingArithmeticCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT ·vectorSaturatingArithmeticForms(SB), $0-0\n") + for _, op := range []string{"VSQADD", "VUQADD", "VSQSUB", "VUQSUB"} { + for _, arrangement := range []string{"B8", "B16", "H4", "H8", "S2", "S4", "D2"} { + source.WriteString("\t" + op + " V0." + arrangement + ", V1." + arrangement + ", V31." + arrangement + "\n") + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorSaturatingArithmeticForms": {Name: "vectorSaturatingArithmeticForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{"@llvm.sadd.sat.", "@llvm.uadd.sat.", "@llvm.ssub.sat.", "@llvm.usub.sat."} { + if !strings.Contains(ll, want) { + t.Fatalf("%s saturating arithmetic IR omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-saturating-arithmetic.ll", "arm64-vector-saturating-arithmetic.o", ll) + } +} + +func TestTranslateARM64VectorSaturatingArithmeticRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VSQADD V0.B8, V1.B8", + "VUQADD V0.B8, V1.B16, V2.B8", + "VSQSUB V0.D1, V1.D1, V2.D1", + "VUQSUB V0.S4, V1.S4, V2.S2", + "VSQADD.P V0.H8, V1.H8, V2.H8", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT ·badVectorSaturatingArithmetic(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badVectorSaturatingArithmetic": {Name: "badVectorSaturatingArithmetic", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector saturating arithmetic forms", instruction) + } + }) + } +} diff --git a/arm64_lower_saturating_shift.go b/arm64_lower_saturating_shift.go new file mode 100644 index 00000000..c3dfdba2 --- /dev/null +++ b/arm64_lower_saturating_shift.go @@ -0,0 +1,81 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorSaturatingShift(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, handled := map[Op]string{"VSQSHL": "sqshl", "VUQSHL": "uqshl"}[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects $shift|Vshifts.T, Vvalue.T, Vdst.T with no suffix: %q", op, ins.Raw) + } + var arrangement arm64VectorArrangement + for index, operand := range ins.Args[1:] { + if operand.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s value and destination must be vector registers: %q", op, ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(operand.Reg) + if !valid || !arm64SaturatingShiftArrangement(parsed) { + return true, false, fmt.Errorf("arm64 %s accepts only B8/B16/H4/H8/S2/S4/D2 arrangements: %q", op, ins.Raw) + } + if index == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + + vectorType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, arrangement.elementBits) + shifts := "" + switch shiftOperand := ins.Args[0]; shiftOperand.Kind { + case OpImm: + if shiftOperand.ImmRaw != "" || shiftOperand.Imm < 0 || shiftOperand.Imm >= int64(arrangement.elementBits) { + return true, false, fmt.Errorf("arm64 %s immediate shift must be in [0,%d): %q", op, arrangement.elementBits, ins.Raw) + } + var constant strings.Builder + constant.WriteString("<") + for lane := 0; lane < arrangement.lanes; lane++ { + if lane != 0 { + constant.WriteString(", ") + } + fmt.Fprintf(&constant, "i%d %d", arrangement.elementBits, shiftOperand.Imm) + } + constant.WriteString(">") + shifts = constant.String() + case OpReg: + shiftArrangement, valid := parseARM64VectorArrangement(shiftOperand.Reg) + if !valid || shiftArrangement != arrangement { + return true, false, fmt.Errorf("arm64 %s shift-count arrangement must match: %q", op, ins.Raw) + } + shifts, err = c.loadARM64VectorInteger(shiftOperand.Reg, arrangement) + if err != nil { + return true, false, err + } + default: + return true, false, fmt.Errorf("arm64 %s first operand must be an immediate or vector register: %q", op, ins.Raw) + } + value, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.neon.%s.v%di%d(%s %s, %s %s)\n", + result, vectorType, intrinsic, arrangement.lanes, arrangement.elementBits, vectorType, value, vectorType, shifts) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, "%"+result) +} + +func arm64SaturatingShiftArrangement(arrangement arm64VectorArrangement) bool { + switch { + case arrangement.elementBits == 8 && (arrangement.lanes == 8 || arrangement.lanes == 16): + case arrangement.elementBits == 16 && (arrangement.lanes == 4 || arrangement.lanes == 8): + case arrangement.elementBits == 32 && (arrangement.lanes == 2 || arrangement.lanes == 4): + case arrangement.elementBits == 64 && arrangement.lanes == 2: + default: + return false + } + return true +} diff --git a/arm64_lower_saturating_shift_narrow.go b/arm64_lower_saturating_shift_narrow.go new file mode 100644 index 00000000..e1958671 --- /dev/null +++ b/arm64_lower_saturating_shift_narrow.go @@ -0,0 +1,212 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SaturatingShiftNarrowSpec struct { + signedSource bool + unsignedDestination bool + rounding bool +} + +var arm64SaturatingShiftNarrowSpecs = map[Op]arm64SaturatingShiftNarrowSpec{ + "VSQSHRN": {signedSource: true}, + "VSQSHRN2": {signedSource: true}, + "VSQRSHRN": {signedSource: true, rounding: true}, + "VSQRSHRN2": {signedSource: true, rounding: true}, + "VSQSHRUN": {signedSource: true, unsignedDestination: true}, + "VSQSHRUN2": {signedSource: true, unsignedDestination: true}, + "VSQRSHRUN": {signedSource: true, unsignedDestination: true, rounding: true}, + "VSQRSHRUN2": {signedSource: true, unsignedDestination: true, rounding: true}, + "VUQSHRN": {}, + "VUQSHRN2": {}, + "VUQRSHRN": {rounding: true}, + "VUQRSHRN2": {rounding: true}, +} + +type arm64RawSaturatingShiftNarrow struct { + op Op + spec arm64SaturatingShiftNarrowSpec + scalar bool + highHalf bool + sourceArrangement arm64VectorArrangement + destinationArrangement arm64VectorArrangement + shift int + source int + destination int +} + +func decodeARM64RawSaturatingShiftNarrow(word uint32) (arm64RawSaturatingShiftNarrow, bool) { + type encoding struct { + op Op + scalar bool + highHalf bool + } + encodings := map[uint32]encoding{ + 0x0f009400: {op: "VSQSHRN"}, + 0x4f009400: {op: "VSQSHRN2", highHalf: true}, + 0x5f009400: {op: "VSQSHRN", scalar: true}, + 0x0f009c00: {op: "VSQRSHRN"}, + 0x4f009c00: {op: "VSQRSHRN2", highHalf: true}, + 0x5f009c00: {op: "VSQRSHRN", scalar: true}, + 0x2f008400: {op: "VSQSHRUN"}, + 0x6f008400: {op: "VSQSHRUN2", highHalf: true}, + 0x7f008400: {op: "VSQSHRUN", scalar: true}, + 0x2f008c00: {op: "VSQRSHRUN"}, + 0x6f008c00: {op: "VSQRSHRUN2", highHalf: true}, + 0x7f008c00: {op: "VSQRSHRUN", scalar: true}, + 0x2f009400: {op: "VUQSHRN"}, + 0x6f009400: {op: "VUQSHRN2", highHalf: true}, + 0x7f009400: {op: "VUQSHRN", scalar: true}, + 0x2f009c00: {op: "VUQRSHRN"}, + 0x6f009c00: {op: "VUQRSHRN2", highHalf: true}, + 0x7f009c00: {op: "VUQRSHRN", scalar: true}, + } + decoded, ok := encodings[word&0xff80fc00] + if !ok { + return arm64RawSaturatingShiftNarrow{}, false + } + encodedImmediate := int(word>>16) & 0x7f + destinationBits := 0 + switch { + case encodedImmediate >= 32 && encodedImmediate < 64: + destinationBits = 32 + case encodedImmediate >= 16: + destinationBits = 16 + case encodedImmediate >= 8: + destinationBits = 8 + default: + return arm64RawSaturatingShiftNarrow{}, false + } + shift := 2*destinationBits - encodedImmediate + if shift < 1 || shift > destinationBits { + return arm64RawSaturatingShiftNarrow{}, false + } + sourceLanes := 128 / (destinationBits * 2) + destinationLanes := sourceLanes + if decoded.scalar { + sourceLanes = 1 + destinationLanes = 1 + } else if decoded.highHalf { + destinationLanes *= 2 + } + return arm64RawSaturatingShiftNarrow{ + op: decoded.op, + spec: arm64SaturatingShiftNarrowSpecs[decoded.op], + scalar: decoded.scalar, + highHalf: decoded.highHalf, + sourceArrangement: arm64VectorArrangement{elementBits: destinationBits * 2, lanes: sourceLanes}, + destinationArrangement: arm64VectorArrangement{elementBits: destinationBits, lanes: destinationLanes}, + shift: shift, + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawSaturatingShiftNarrow(form arm64RawSaturatingShiftNarrow) error { + return c.lowerARM64SaturatingShiftNarrowForm(form) +} + +func (c *arm64Ctx) lowerARM64VectorSaturatingShiftNarrow(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, handled := arm64SaturatingShiftNarrowSpecs[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || + ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects immediate, wide vector source, narrow vector destination, and no suffix: %q", op, ins.Raw) + } + sourceArrangement, sourceOK := parseARM64VectorArrangement(ins.Args[1].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[2].Reg) + highHalf := strings.HasSuffix(string(op), "2") + wantDestinationLanes := sourceArrangement.lanes + if highHalf { + wantDestinationLanes *= 2 + } + shift := ins.Args[0].Imm + if !sourceOK || !destinationOK || sourceArrangement.lanes*sourceArrangement.elementBits != 128 || + sourceArrangement.elementBits != destinationArrangement.elementBits*2 || + destinationArrangement.lanes != wantDestinationLanes || shift < 1 || shift > int64(destinationArrangement.elementBits) { + return true, false, fmt.Errorf("arm64 %s requires $1..$N with H8->B8/S4->H4/D2->S2 (or the doubled *2 destination): %q", op, ins.Raw) + } + source, _ := arm64ParseVReg(ins.Args[1].Reg) + destination, _ := arm64ParseVReg(ins.Args[2].Reg) + form := arm64RawSaturatingShiftNarrow{ + op: op, spec: spec, highHalf: highHalf, + sourceArrangement: sourceArrangement, destinationArrangement: destinationArrangement, + shift: int(shift), source: source, destination: destination, + } + return true, false, c.lowerARM64SaturatingShiftNarrowForm(form) +} + +func (c *arm64Ctx) lowerARM64SaturatingShiftNarrowForm(form arm64RawSaturatingShiftNarrow) error { + source, err := c.loadRawARM64VectorOperand(form.source, form.sourceArrangement, 0, form.scalar) + if err != nil { + return err + } + sourceType := fmt.Sprintf("<%d x i%d>", form.sourceArrangement.lanes, form.sourceArrangement.elementBits) + shiftValue := arm64VectorIntegerSplat(form.sourceArrangement, int64(form.shift)) + shifted := c.newTmp() + operation := "lshr" + if form.spec.signedSource { + operation = "ashr" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", shifted, operation, sourceType, source, shiftValue) + shiftedValue := "%" + shifted + if form.spec.rounding { + roundingShift := c.newTmp() + roundingBit := c.newTmp() + rounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %s\n", roundingShift, sourceType, source, + arm64VectorIntegerSplat(form.sourceArrangement, int64(form.shift-1))) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %s\n", roundingBit, sourceType, roundingShift, + arm64VectorIntegerSplat(form.sourceArrangement, 1)) + fmt.Fprintf(c.b, " %%%s = add %s %s, %%%s\n", rounded, sourceType, shiftedValue, roundingBit) + shiftedValue = "%" + rounded + } + + clamped := shiftedValue + destinationBits := form.destinationArrangement.elementBits + switch { + case form.spec.signedSource && form.spec.unsignedDestination: + maximum := (int64(1) << destinationBits) - 1 + clamped = c.clampARM64VectorInteger(sourceType, form.sourceArrangement, shiftedValue, "slt", 0, "sgt", maximum) + case form.spec.signedSource: + minimum := -(int64(1) << (destinationBits - 1)) + maximum := (int64(1) << (destinationBits - 1)) - 1 + clamped = c.clampARM64VectorInteger(sourceType, form.sourceArrangement, shiftedValue, "slt", minimum, "sgt", maximum) + default: + maximum := (int64(1) << destinationBits) - 1 + above := c.newTmp() + selected := c.newTmp() + upper := arm64VectorIntegerSplat(form.sourceArrangement, maximum) + fmt.Fprintf(c.b, " %%%s = icmp ugt %s %s, %s\n", above, sourceType, shiftedValue, upper) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %s\n", + selected, form.sourceArrangement.lanes, above, sourceType, upper, sourceType, shiftedValue) + clamped = "%" + selected + } + + narrowType := fmt.Sprintf("<%d x i%d>", form.sourceArrangement.lanes, destinationBits) + narrowed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", narrowed, sourceType, clamped, narrowType) + result := "%" + narrowed + if form.highHalf { + destination, err := c.loadRawARM64VectorOperand(form.destination, form.destinationArrangement, 0, false) + if err != nil { + return err + } + fullDestinationType := fmt.Sprintf("<%d x i%d>", form.destinationArrangement.lanes, destinationBits) + for lane := 0; lane < form.sourceArrangement.lanes; lane++ { + element := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %d\n", element, narrowType, result, lane) + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %%%s, i32 %d\n", + inserted, fullDestinationType, destination, destinationBits, element, form.sourceArrangement.lanes+lane) + destination = "%" + inserted + } + result = destination + } + return c.storeRawARM64VectorResult(form.destination, form.destinationArrangement, result, form.scalar) +} diff --git a/arm64_lower_saturating_shift_narrow_test.go b/arm64_lower_saturating_shift_narrow_test.go new file mode 100644 index 00000000..4c4084f4 --- /dev/null +++ b/arm64_lower_saturating_shift_narrow_test.go @@ -0,0 +1,250 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func encodeARM64SaturatingShiftNarrow(base uint32, destinationBits, shift int, highHalf bool, source, destination int) uint32 { + encodedImmediate := uint32(2*destinationBits - shift) + word := base | encodedImmediate<<16 | uint32(source)<<5 | uint32(destination) + if highHalf { + word |= 1 << 30 + } + return word +} + +func TestTranslateARM64RawSaturatingShiftNarrowCompleteArchitectureFamily(t *testing.T) { + type family struct { + name string + vectorBase uint32 + scalarBase uint32 + } + families := []family{ + {name: "VSQSHRN", vectorBase: 0x0f009400, scalarBase: 0x5f009400}, + {name: "VSQRSHRN", vectorBase: 0x0f009c00, scalarBase: 0x5f009c00}, + {name: "VSQSHRUN", vectorBase: 0x2f008400, scalarBase: 0x7f008400}, + {name: "VSQRSHRUN", vectorBase: 0x2f008c00, scalarBase: 0x7f008c00}, + {name: "VUQSHRN", vectorBase: 0x2f009400, scalarBase: 0x7f009400}, + {name: "VUQRSHRN", vectorBase: 0x2f009c00, scalarBase: 0x7f009c00}, + } + letter := map[int]string{8: "B", 16: "H", 32: "S", 64: "D"} + var source strings.Builder + source.WriteString("TEXT saturatingShiftNarrowArchitectureForms(SB),$0-0\n") + for _, family := range families { + for _, destinationBits := range []int{8, 16, 32} { + for _, highHalf := range []bool{false, true} { + for _, shift := range []int{1, destinationBits} { + word := encodeARM64SaturatingShiftNarrow(family.vectorBase, destinationBits, shift, highHalf, 29, 28) + decoded, err := decodeARM64RawWordInstruction(Instr{Op: OpWORD, Args: []Operand{{Kind: OpImm, Imm: int64(word)}}}) + if err != nil { + t.Fatalf("decode %s destination=%d high=%v shift=%d: %v", family.name, destinationBits, highHalf, shift, err) + } + wantName := family.name + if highHalf { + wantName += "2" + } + wantSource := Reg(fmt.Sprintf("V29.%s%d", letter[destinationBits*2], 128/(destinationBits*2))) + wantDestinationLanes := 64 / destinationBits + if highHalf { + wantDestinationLanes *= 2 + } + wantDestination := Reg(fmt.Sprintf("V28.%s%d", letter[destinationBits], wantDestinationLanes)) + if decoded.Op != Op(wantName) || len(decoded.Args) != 3 || decoded.Args[0].Kind != OpImm || decoded.Args[0].Imm != int64(shift) || + decoded.Args[1].Reg != wantSource || decoded.Args[2].Reg != wantDestination { + t.Fatalf("decoded %s destination=%d high=%v shift=%d %#08x as %#v", family.name, destinationBits, highHalf, shift, word, decoded) + } + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + } + for _, shift := range []int{1, destinationBits} { + word := encodeARM64SaturatingShiftNarrow(family.scalarBase, destinationBits, shift, false, 29, 28) + decoded, err := decodeARM64RawWordInstruction(Instr{Op: OpWORD, Args: []Operand{{Kind: OpImm, Imm: int64(word)}}}) + if err != nil { + t.Fatalf("decode scalar %s destination=%d shift=%d: %v", family.name, destinationBits, shift, err) + } + if decoded.Op != Op(family.name) || len(decoded.Args) != 3 || decoded.Args[0].Kind != OpImm || decoded.Args[0].Imm != int64(shift) || + decoded.Args[1].Reg != "V29" || decoded.Args[2].Reg != "V28" { + t.Fatalf("decoded scalar %s destination=%d shift=%d %#08x as %#v", family.name, destinationBits, shift, word, decoded) + } + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "saturatingShiftNarrowArchitectureForms": {Name: "saturatingShiftNarrowArchitectureForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, operation := range []string{"ashr", "lshr", "icmp", "select", "trunc", "insertelement"} { + if !strings.Contains(ll, " = "+operation+" ") { + t.Fatalf("%s omitted %s semantics:\n%s", triple, operation, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-saturating-shift-narrow.ll", "arm64-saturating-shift-narrow.o", ll) + }) + } +} + +func TestARM64RawSaturatingShiftNarrowDecoderCoversEveryImmediate(t *testing.T) { + families := []struct { + vectorBase uint32 + scalarBase uint32 + }{ + {0x0f009400, 0x5f009400}, + {0x0f009c00, 0x5f009c00}, + {0x2f008400, 0x7f008400}, + {0x2f008c00, 0x7f008c00}, + {0x2f009400, 0x7f009400}, + {0x2f009c00, 0x7f009c00}, + } + for _, family := range families { + for _, destinationBits := range []int{8, 16, 32} { + for shift := 1; shift <= destinationBits; shift++ { + for _, form := range []struct { + base uint32 + highHalf bool + scalar bool + }{ + {base: family.vectorBase}, + {base: family.vectorBase, highHalf: true}, + {base: family.scalarBase, scalar: true}, + } { + word := encodeARM64SaturatingShiftNarrow(form.base, destinationBits, shift, form.highHalf, 31, 30) + decoded, ok := decodeARM64RawSaturatingShiftNarrow(word) + if !ok || decoded.shift != shift || decoded.source != 31 || decoded.destination != 30 || + decoded.scalar != form.scalar || decoded.highHalf != form.highHalf || + decoded.sourceArrangement.elementBits != destinationBits*2 || decoded.destinationArrangement.elementBits != destinationBits { + t.Fatalf("decode base=%#08x destination=%d shift=%d high=%v scalar=%v: form=%#v ok=%v", + form.base, destinationBits, shift, form.highHalf, form.scalar, decoded, ok) + } + } + } + } + } +} + +func TestARM64SaturatingShiftNarrowRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + families := []uint32{0x0f009400, 0x0f009c00, 0x2f008400, 0x2f008c00, 0x2f009400, 0x2f009c00} + var source strings.Builder + source.WriteString("TEXT saturatingShiftNarrowSemantics(SB),$0-24\n") + source.WriteString("\tMOVD in+0(FP), R0\n\tMOVD initial+8(FP), R1\n\tMOVD out+16(FP), R2\n") + for _, base := range families { + for _, highHalf := range []bool{false, true} { + source.WriteString("\tVLD1 (R0), [V0.H8]\n\tVLD1 (R1), [V1.B16]\n") + word := encodeARM64SaturatingShiftNarrow(base, 8, 1, highHalf, 0, 1) + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + source.WriteString("\tVST1.P [V1.B16], 16(R2)\n") + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"saturatingShiftNarrowSemantics": { + Name: "saturatingShiftNarrowSemantics", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void saturatingShiftNarrowSemantics(const int16_t *, const uint8_t *, uint8_t *); +static int16_t signed_clamp(int32_t value) { + if (value < INT8_MIN) return INT8_MIN; + if (value > INT8_MAX) return INT8_MAX; + return value; +} +static uint16_t unsigned_clamp(int32_t value) { + if (value < 0) return 0; + if (value > UINT8_MAX) return UINT8_MAX; + return value; +} +int main(void) { + const int16_t in[8] = {INT16_MIN, -1001, -255, -1, 0, 255, 1001, INT16_MAX}; + uint8_t initial[16], got[12*16] = {0}; + for (int i = 0; i < 16; i++) initial[i] = (uint8_t)(i * 13u + 7u); + saturatingShiftNarrowSemantics(in, initial, got); + for (int family = 0; family < 6; family++) { + for (int high = 0; high < 2; high++) { + const int output = (family * 2 + high) * 16; + for (int lane = 0; lane < 16; lane++) { + uint8_t want; + if (high && lane < 8) { + want = initial[lane]; + } else if (!high && lane >= 8) { + want = 0; + } else { + const int input_lane = high ? lane - 8 : lane; + const int32_t signed_value = in[input_lane]; + const uint32_t unsigned_value = (uint16_t)in[input_lane]; + const int rounding = family == 1 || family == 3 || family == 5; + if (family < 2) { + int32_t shifted = signed_value >> 1; + if (rounding) shifted += signed_value & 1; + want = (uint8_t)(int8_t)signed_clamp(shifted); + } else if (family < 4) { + int32_t shifted = signed_value >> 1; + if (rounding) shifted += signed_value & 1; + want = (uint8_t)unsigned_clamp(shifted); + } else { + uint32_t shifted = unsigned_value >> 1; + if (rounding) shifted += unsigned_value & 1; + want = (uint8_t)(shifted > UINT8_MAX ? UINT8_MAX : shifted); + } + } + if (got[output+lane] != want) return output + lane + 1; + } + } + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_saturating_shift_narrow", triple, ll, mainC, nil) +} diff --git a/arm64_lower_saturating_shift_test.go b/arm64_lower_saturating_shift_test.go new file mode 100644 index 00000000..1d33e45e --- /dev/null +++ b/arm64_lower_saturating_shift_test.go @@ -0,0 +1,78 @@ +//go:build !llgo + +package plan9asm + +import ( + "strconv" + "strings" + "testing" +) + +func arm64SaturatingShiftCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT saturatingShiftComplete(SB),$0-0\n") + for _, op := range []string{"VSQSHL", "VUQSHL"} { + for _, arrangement := range []struct { + name string + maxShift int + }{{"B8", 7}, {"B16", 7}, {"H4", 15}, {"H8", 15}, {"S2", 31}, {"S4", 31}, {"D2", 63}} { + source.WriteString("\t" + op + " $" + strconv.Itoa(arrangement.maxShift) + ", V1." + arrangement.name + ", V2." + arrangement.name + "\n") + source.WriteString("\t" + op + " V3." + arrangement.name + ", V4." + arrangement.name + ", V5." + arrangement.name + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SaturatingShiftCompleteFormats(t *testing.T) { + source := arm64SaturatingShiftCompleteForms() + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "saturatingShiftComplete": {Name: "saturatingShiftComplete", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{"llvm.aarch64.neon.sqshl", "llvm.aarch64.neon.uqshl"} { + if !strings.Contains(ll, intrinsic) { + t.Fatalf("ARM64 saturating shift lowering omitted %q:\n%s", intrinsic, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-saturating-shift.ll", "arm64-saturating-shift.o", ll) +} + +func TestTranslateARM64SaturatingShiftRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "VSQSHL $8, V0.B8, V1.B8", + "VSQSHL V0.B8, V1.B16, V2.B8", + "VUQSHL $1, V0.D1, V1.D1", + "VUQSHL R0, V1.S4, V2.S4", + "VUQSHL.P V0.S4, V1.S4, V2.S4", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 saturating-shift optab", instruction) + } + } +} diff --git a/arm64_lower_scalar_float_integer_test.go b/arm64_lower_scalar_float_integer_test.go new file mode 100644 index 00000000..6ad0b970 --- /dev/null +++ b/arm64_lower_scalar_float_integer_test.go @@ -0,0 +1,154 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64ScalarFloatToIntegerForms = ` +TEXT scalarfloattointegerforms(SB),$0-0 + FCVTZSD F0, R0 + FCVTZSDW F1, R1 + FCVTZSS F2, R2 + FCVTZSSW F3, R3 + FCVTZUD F4, R4 + FCVTZUDW F5, R5 + FCVTZUS F6, R6 + FCVTZUSW F7, ZR + RET +` + +func TestTranslateARM64ScalarFloatToIntegerCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64ScalarFloatToIntegerForms, true) + file, err := Parse(ArchARM64, arm64ScalarFloatToIntegerForms) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "scalarfloattointegerforms": {Name: "scalarfloattointegerforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "@llvm.fptosi.sat.i64.f64", "@llvm.fptosi.sat.i32.f64", + "@llvm.fptosi.sat.i64.f32", "@llvm.fptosi.sat.i32.f32", + "@llvm.fptoui.sat.i64.f64", "@llvm.fptoui.sat.i32.f64", + "@llvm.fptoui.sat.i64.f32", "@llvm.fptoui.sat.i32.f32", + } { + if !strings.Contains(ir, want) { + t.Fatalf("scalar float-to-integer lowering for %s omitted %s:\n%s", triple, want, ir) + } + } + compileLLVMToObject(t, llc, triple, "scalar-float-to-integer.ll", "scalar-float-to-integer.o", ir) + }) + } +} + +func TestTranslateARM64ScalarFloatToIntegerRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "FCVTZSS F0", + "FCVTZSS F0, R1, R2", + "FCVTZSS R0, R1", + "FCVTZSS F0, F1", + "FCVTZSS F0, RSP", + "FCVTZUSW.P F0, R1", + } { + source := "TEXT badscalarfloattointeger(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", + Sigs: map[string]FuncSig{"badscalarfloattointeger": {Name: "badscalarfloattointeger", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scalar float-to-integer family", instruction) + } + } +} + +func TestARM64ScalarFloatToIntegerRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT scalarfloattointeger(SB),$0-24 + MOVD singles+0(FP), R0 + MOVD doubles+8(FP), R1 + MOVD output+16(FP), R2 + FMOVS 0(R0), F0 + FMOVS 4(R0), F1 + FMOVD 0(R1), F2 + FMOVD 8(R1), F3 + FCVTZSS F0, R3 + FCVTZSSW F1, R4 + FCVTZUS F1, R5 + FCVTZUSW F0, R6 + FCVTZSD F2, R7 + FCVTZSDW F3, R8 + FCVTZUD F3, R9 + FCVTZUDW F2, R10 + MOVD R3, 0(R2) + MOVD R4, 8(R2) + MOVD R5, 16(R2) + MOVD R6, 24(R2) + MOVD R7, 32(R2) + MOVD R8, 40(R2) + MOVD R9, 48(R2) + MOVD R10, 56(R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"scalarfloattointeger": { + Name: "scalarfloattointeger", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void scalarfloattointeger(const float *, const double *, uint64_t *); +int main(void) { + const float singles[2] = {7.75f, -3.75f}; + const double doubles[2] = {-9.5, 11.5}; + uint64_t got[8] = {0}; + const uint64_t want[8] = {7, UINT32_MAX - 2, 0, 7, UINT64_MAX - 8, 11, 11, 0}; + scalarfloattointeger(singles, doubles, got); + for (int i = 0; i < 8; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_scalar_float_to_integer", triple, ir, mainC, nil) +} diff --git a/arm64_lower_scalar_multiply.go b/arm64_lower_scalar_multiply.go new file mode 100644 index 00000000..bea0dfbd --- /dev/null +++ b/arm64_lower_scalar_multiply.go @@ -0,0 +1,187 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerARM64ScalarMultiply implements the complete scalar multiply rows shared +// by Go 1.27's AMUL and AMADD optabs. In particular, the two-operand AMUL-row +// form uses the destination as the second multiplicand. +func (c *arm64Ctx) lowerARM64ScalarMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "MNEG", "MNEGW", "SMULL", "UMULL", "SMNEGL", "UMNEGL", "SMULH", "UMULH": + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept instruction suffixes: %q", op, ins.Raw) + } + first, second, destination, err := c.arm64ScalarMultiplyOperands(op, ins) + if err != nil { + return true, false, err + } + switch op { + case "MNEG", "MNEGW": + return true, false, c.lowerARM64MultiplyNegate(op == "MNEGW", first, second, destination) + case "SMULL", "UMULL", "SMNEGL", "UMNEGL": + signed := op == "SMULL" || op == "SMNEGL" + negate := op == "SMNEGL" || op == "UMNEGL" + return true, false, c.lowerARM64MultiplyLong(signed, negate, first, second, destination) + case "SMULH", "UMULH": + return true, false, c.lowerARM64MultiplyHigh(op == "SMULH", first, second, destination) + } + + case "SMADDL", "SMSUBL", "UMADDL", "UMSUBL": + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept instruction suffixes: %q", op, ins.Raw) + } + if len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects four C_ZREG operands: %q", op, ins.Raw) + } + for _, operand := range ins.Args { + if !arm64ScalarMultiplyRegister(operand) { + return true, false, fmt.Errorf("arm64 %s expects four C_ZREG operands: %q", op, ins.Raw) + } + } + signed := op == "SMADDL" || op == "SMSUBL" + subtract := op == "SMSUBL" || op == "UMSUBL" + return true, false, c.lowerARM64MultiplyAddLong(signed, subtract, ins.Args[0], ins.Args[1], ins.Args[2], ins.Args[3].Reg) + } + return false, false, nil +} + +func (c *arm64Ctx) arm64ScalarMultiplyOperands(op Op, ins Instr) (Operand, Operand, Reg, error) { + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return Operand{}, Operand{}, "", fmt.Errorf("arm64 %s expects two or three C_ZREG operands: %q", op, ins.Raw) + } + for _, operand := range ins.Args { + if !arm64ScalarMultiplyRegister(operand) { + return Operand{}, Operand{}, "", fmt.Errorf("arm64 %s expects two or three C_ZREG operands: %q", op, ins.Raw) + } + } + if len(ins.Args) == 2 { + return ins.Args[0], ins.Args[1], ins.Args[1].Reg, nil + } + return ins.Args[0], ins.Args[1], ins.Args[2].Reg, nil +} + +func arm64ScalarMultiplyRegister(operand Operand) bool { + return operand.Kind == OpReg && isARM64GeneralOrZeroReg(operand.Reg) +} + +func (c *arm64Ctx) lowerARM64MultiplyNegate(word bool, first, second Operand, destination Reg) error { + if word { + a, err := c.eval32(first) + if err != nil { + return err + } + b, err := c.eval32(second) + if err != nil { + return err + } + product := c.newTmp() + result := c.newTmp() + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i32 %s, %s\n", product, a, b) + fmt.Fprintf(c.b, " %%%s = sub i32 0, %%%s\n", result, product) + fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", wide, result) + return c.storeReg(destination, "%"+wide) + } + a, err := c.eval64(first, false) + if err != nil { + return err + } + b, err := c.eval64(second, false) + if err != nil { + return err + } + product := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i64 %s, %s\n", product, a, b) + fmt.Fprintf(c.b, " %%%s = sub i64 0, %%%s\n", result, product) + return c.storeReg(destination, "%"+result) +} + +func (c *arm64Ctx) lowerARM64MultiplyLong(signed, negate bool, first, second Operand, destination Reg) error { + a, err := c.eval32(first) + if err != nil { + return err + } + b, err := c.eval32(second) + if err != nil { + return err + } + extension := "zext" + if signed { + extension = "sext" + } + wideA := c.newTmp() + wideB := c.newTmp() + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s i32 %s to i64\n", wideA, extension, a) + fmt.Fprintf(c.b, " %%%s = %s i32 %s to i64\n", wideB, extension, b) + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %%%s\n", product, wideA, wideB) + value := "%" + product + if negate { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i64 0, %s\n", result, value) + value = "%" + result + } + return c.storeReg(destination, value) +} + +func (c *arm64Ctx) lowerARM64MultiplyHigh(signed bool, first, second Operand, destination Reg) error { + a, err := c.eval64(first, false) + if err != nil { + return err + } + b, err := c.eval64(second, false) + if err != nil { + return err + } + extension := "zext" + if signed { + extension = "sext" + } + wideA := c.newTmp() + wideB := c.newTmp() + product := c.newTmp() + high := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s i64 %s to i128\n", wideA, extension, a) + fmt.Fprintf(c.b, " %%%s = %s i64 %s to i128\n", wideB, extension, b) + fmt.Fprintf(c.b, " %%%s = mul i128 %%%s, %%%s\n", product, wideA, wideB) + fmt.Fprintf(c.b, " %%%s = lshr i128 %%%s, 64\n", high, product) + fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", result, high) + return c.storeReg(destination, "%"+result) +} + +func (c *arm64Ctx) lowerARM64MultiplyAddLong(signed, subtract bool, first, second, addend Operand, destination Reg) error { + a, err := c.eval32(first) + if err != nil { + return err + } + b, err := c.eval32(second) + if err != nil { + return err + } + cv, err := c.eval64(addend, false) + if err != nil { + return err + } + extension := "zext" + if signed { + extension = "sext" + } + wideA := c.newTmp() + wideB := c.newTmp() + product := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s i32 %s to i64\n", wideA, extension, a) + fmt.Fprintf(c.b, " %%%s = %s i32 %s to i64\n", wideB, extension, b) + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %%%s\n", product, wideA, wideB) + if subtract { + fmt.Fprintf(c.b, " %%%s = sub i64 %s, %%%s\n", result, cv, product) + } else { + fmt.Fprintf(c.b, " %%%s = add i64 %s, %%%s\n", result, cv, product) + } + return c.storeReg(destination, "%"+result) +} diff --git a/arm64_lower_scalar_multiply_test.go b/arm64_lower_scalar_multiply_test.go new file mode 100644 index 00000000..cdf0fd8f --- /dev/null +++ b/arm64_lower_scalar_multiply_test.go @@ -0,0 +1,185 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64ScalarMultiplyCompleteGo127Forms(t *testing.T) { + const source = `TEXT scalarMultiplyForms(SB), $0-0 + MNEG R0, R1 + MNEG R0, R1, R2 + MNEGW R3, R4 + MNEGW R3, R4, R5 + SMULL R6, R7 + SMULL R6, R7, R8 + UMULL R9, R10 + UMULL R9, R10, R11 + SMNEGL R12, R13 + SMNEGL R12, R13, R14 + UMNEGL R15, R16 + UMNEGL R15, R16, R17 + SMULH R17, R19 + SMULH R17, R19, R20 + UMULH R21, R22 + UMULH R21, R22, R23 + SMADDL R0, R1, R2, R3 + SMSUBL R4, R5, R6, R7 + UMADDL R8, R9, R10, R11 + UMSUBL R12, R13, R14, R15 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "scalarMultiplyForms": {Name: "scalarMultiplyForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sext i32", "zext i32", "sext i64", "zext i64", "mul i128", "lshr i128", "sub i64", "add i64"} { + if !strings.Contains(ll, want) { + t.Fatalf("scalar multiply lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-scalar-multiply.ll", "arm64-scalar-multiply.o", ll) + }) + } +} + +func TestTranslateARM64ScalarMultiplyRejectsFormsOutsideGo127Optab(t *testing.T) { + for _, instruction := range []string{ + "UMULL R0", + "UMULL $1, R0", + "SMULL R0, R1, R2, R3", + "SMULH R0, (R1)", + "UMULH.P R0, R1, R2", + "SMADDL R0, R1, R2", + "UMSUBL R0, R1, R2, (R3)", + "MNEG R0", + "MNEGW $1, R0", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT badScalarMultiply(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badScalarMultiply": {Name: "badScalarMultiply", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scalar multiply optab", instruction) + } + }) + } +} + +func TestARM64ScalarMultiplyRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT scalarMultiplyRuntime(SB), $0-32 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD add+16(FP), R2 + MOVD out+24(FP), R3 + UMULL R0, R1, R4 + MOVD R4, 0(R3) + SMULL R0, R1, R4 + MOVD R4, 8(R3) + UMNEGL R0, R1, R4 + MOVD R4, 16(R3) + SMNEGL R0, R1, R4 + MOVD R4, 24(R3) + UMULH R0, R1, R4 + MOVD R4, 32(R3) + SMULH R0, R1, R4 + MOVD R4, 40(R3) + UMADDL R0, R1, R2, R4 + MOVD R4, 48(R3) + UMSUBL R0, R1, R2, R4 + MOVD R4, 56(R3) + SMADDL R0, R1, R2, R4 + MOVD R4, 64(R3) + SMSUBL R0, R1, R2, R4 + MOVD R4, 72(R3) + MNEG R0, R1, R4 + MOVD R4, 80(R3) + MNEGW R0, R1, R4 + MOVD R4, 88(R3) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "scalarMultiplyRuntime": { + Name: "scalarMultiplyRuntime", Args: []LLVMType{I64, I64, I64, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: I64, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void scalarMultiplyRuntime(uint64_t, uint64_t, uint64_t, uint64_t *); +int main(void) { + const uint64_t a = UINT64_C(0xffffffff80000003); + const uint64_t b = UINT64_C(0x8000000000000005); + const uint64_t add = UINT64_C(0x1020304050607080); + uint64_t got[12] = {0}; + scalarMultiplyRuntime(a, b, add, got); + const uint64_t up = (uint64_t)(uint32_t)a * (uint64_t)(uint32_t)b; + const int64_t sp = (int64_t)(int32_t)a * (int64_t)(int32_t)b; + const unsigned __int128 uw = (unsigned __int128)a * (unsigned __int128)b; + const __int128 sw = (__int128)(int64_t)a * (__int128)(int64_t)b; + const uint64_t want[12] = { + up, (uint64_t)sp, 0-up, 0-(uint64_t)sp, + (uint64_t)(uw >> 64), (uint64_t)((unsigned __int128)sw >> 64), + add+up, add-up, add+(uint64_t)sp, add-(uint64_t)sp, + 0-(a*b), (uint64_t)(uint32_t)(0-((uint32_t)a*(uint32_t)b)), + }; + for (int i = 0; i < 12; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_scalar_multiply", triple, ll, mainC, nil) +} diff --git a/arm64_lower_sha.go b/arm64_lower_sha.go new file mode 100644 index 00000000..de16c96c --- /dev/null +++ b/arm64_lower_sha.go @@ -0,0 +1,180 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var ( + arm64SHA32Arrangement = arm64VectorArrangement{elementBits: 32, lanes: 4} + arm64SHA64Arrangement = arm64VectorArrangement{elementBits: 64, lanes: 2} +) + +func (c *arm64Ctx) lowerARM64SHA(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "SHA1C", "SHA1P", "SHA1M": + if err := validateARM64SHAHashForm(op, ins, arm64SHA32Arrangement); err != nil { + return true, false, err + } + schedule, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arm64SHA32Arrangement) + if err != nil { + return true, false, err + } + hashVector, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arm64SHA32Arrangement) + if err != nil { + return true, false, err + } + hash := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x i32> %s, i32 0\n", hash, hashVector) + destination, err := c.loadARM64VectorInteger(ins.Args[2].Reg, arm64SHA32Arrangement) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <4 x i32> @llvm.aarch64.crypto.%s(<4 x i32> %s, i32 %%%s, <4 x i32> %s)\n", result, strings.ToLower(string(op)), destination, hash, schedule) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arm64SHA32Arrangement, "%"+result) + + case "SHA1H": + if err := validateARM64SHABareRegisters(op, ins, 2); err != nil { + return true, false, err + } + sourceVector, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arm64SHA32Arrangement) + if err != nil { + return true, false, err + } + source := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x i32> %s, i32 0\n", source, sourceVector) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.aarch64.crypto.sha1h(i32 %%%s)\n", result, source) + return true, false, c.storeARM64SHA1Scalar(ins.Args[1].Reg, "%"+result) + + case "SHA1SU0", "SHA256SU1": + if err := validateARM64SHAArrangedRegisters(op, ins, 3, arm64SHA32Arrangement); err != nil { + return true, false, err + } + return true, false, c.lowerARM64SHAVector3(op, ins, arm64SHA32Arrangement) + + case "SHA1SU1", "SHA256SU0": + if err := validateARM64SHAArrangedRegisters(op, ins, 2, arm64SHA32Arrangement); err != nil { + return true, false, err + } + return true, false, c.lowerARM64SHAVector2(op, ins, arm64SHA32Arrangement) + + case "SHA256H", "SHA256H2": + if err := validateARM64SHAHashForm(op, ins, arm64SHA32Arrangement); err != nil { + return true, false, err + } + return true, false, c.lowerARM64SHAVector3(op, ins, arm64SHA32Arrangement) + + case "SHA512H", "SHA512H2": + if err := validateARM64SHAHashForm(op, ins, arm64SHA64Arrangement); err != nil { + return true, false, err + } + return true, false, c.lowerARM64SHAVector3(op, ins, arm64SHA64Arrangement) + + case "SHA512SU0": + if err := validateARM64SHAArrangedRegisters(op, ins, 2, arm64SHA64Arrangement); err != nil { + return true, false, err + } + return true, false, c.lowerARM64SHAVector2(op, ins, arm64SHA64Arrangement) + + case "SHA512SU1": + if err := validateARM64SHAArrangedRegisters(op, ins, 3, arm64SHA64Arrangement); err != nil { + return true, false, err + } + return true, false, c.lowerARM64SHAVector3(op, ins, arm64SHA64Arrangement) + } + return false, false, nil +} + +func validateARM64SHAHashForm(op Op, ins Instr, arrangement arm64VectorArrangement) error { + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return fmt.Errorf("arm64 %s expects an optional-arrangement source and two bare V registers with no suffix: %q", op, ins.Raw) + } + if !arm64SHARegisterMatches(ins.Args[0], arrangement, true) || !arm64SHARegisterMatches(ins.Args[1], arrangement, false) || !arm64SHARegisterMatches(ins.Args[2], arrangement, false) { + return fmt.Errorf("arm64 %s operands do not match Go's assembler table: %q", op, ins.Raw) + } + return nil +} + +func validateARM64SHABareRegisters(op Op, ins Instr, count int) error { + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != count { + return fmt.Errorf("arm64 %s expects %d bare V registers with no suffix: %q", op, count, ins.Raw) + } + for _, arg := range ins.Args { + if !arm64SHARegisterMatches(arg, arm64VectorArrangement{}, false) { + return fmt.Errorf("arm64 %s expects only bare V registers: %q", op, ins.Raw) + } + } + return nil +} + +func validateARM64SHAArrangedRegisters(op Op, ins Instr, count int, arrangement arm64VectorArrangement) error { + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != count { + return fmt.Errorf("arm64 %s expects %d same-arrangement V registers with no suffix: %q", op, count, ins.Raw) + } + for _, arg := range ins.Args { + if !arm64SHARegisterMatches(arg, arrangement, true) || !strings.Contains(string(arg.Reg), ".") { + return fmt.Errorf("arm64 %s operands do not match Go's assembler table: %q", op, ins.Raw) + } + } + return nil +} + +func arm64SHARegisterMatches(arg Operand, arrangement arm64VectorArrangement, allowArrangement bool) bool { + if arg.Kind != OpReg { + return false + } + if _, ok := arm64ParseVReg(arg.Reg); !ok { + return false + } + hasArrangement := strings.Contains(string(arg.Reg), ".") + if !hasArrangement { + return true + } + if !allowArrangement { + return false + } + got, ok := parseARM64VectorArrangement(arg.Reg) + return ok && got == arrangement +} + +func (c *arm64Ctx) lowerARM64SHAVector2(op Op, ins Instr, arrangement arm64VectorArrangement) error { + source, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return err + } + destination, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return err + } + result := c.newTmp() + vectorType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, arrangement.elementBits) + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.crypto.%s(%s %s, %s %s)\n", result, vectorType, strings.ToLower(string(op)), vectorType, destination, vectorType, source) + return c.storeARM64VectorInteger(ins.Args[1].Reg, arrangement, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SHAVector3(op Op, ins Instr, arrangement arm64VectorArrangement) error { + first, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return err + } + second, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return err + } + destination, err := c.loadARM64VectorInteger(ins.Args[2].Reg, arrangement) + if err != nil { + return err + } + result := c.newTmp() + vectorType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, arrangement.elementBits) + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.crypto.%s(%s %s, %s %s, %s %s)\n", result, vectorType, strings.ToLower(string(op)), vectorType, destination, vectorType, second, vectorType, first) + return c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, "%"+result) +} + +func (c *arm64Ctx) storeARM64SHA1Scalar(reg Reg, value string) error { + vector := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <4 x i32> zeroinitializer, i32 %s, i32 0\n", vector, value) + return c.storeARM64VectorInteger(reg, arm64SHA32Arrangement, "%"+vector) +} diff --git a/arm64_lower_sha3.go b/arm64_lower_sha3.go new file mode 100644 index 00000000..19a6045c --- /dev/null +++ b/arm64_lower_sha3.go @@ -0,0 +1,136 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SHA3(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "VEOR3", "VBCAX": + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects four V.B16 operands with no suffix: %q", op, ins.Raw) + } + for _, arg := range ins.Args { + if arg.Kind != OpReg || string(arg.Reg) != strings.Split(string(arg.Reg), ".")[0]+".B16" { + return true, false, fmt.Errorf("arm64 %s expects four V.B16 operands: %q", op, ins.Raw) + } + arrangement, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || arrangement.elementBits != 8 || arrangement.lanes != 16 { + return true, false, fmt.Errorf("arm64 %s expects four V.B16 operands: %q", op, ins.Raw) + } + } + a, err := c.loadVReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + m, err := c.loadVReg(ins.Args[1].Reg) + if err != nil { + return true, false, err + } + n, err := c.loadVReg(ins.Args[2].Reg) + if err != nil { + return true, false, err + } + var result string + if op == "VEOR3" { + first := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor <16 x i8> %s, %s\n", first, a, m) + second := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor <16 x i8> %%%s, %s\n", second, first, n) + result = "%" + second + } else { + // BCAX Vd, Vn, Vm, Va computes Vn XOR (Vm AND NOT Va). + complement := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor <16 x i8> %s, %s\n", complement, a, arm64VectorI8Splat(-1)) + cleared := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and <16 x i8> %s, %%%s\n", cleared, m, complement) + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor <16 x i8> %s, %%%s\n", combined, n, cleared) + result = "%" + combined + } + return true, false, c.storeVReg(ins.Args[3].Reg, result) + + case "VRAX1": + if err := validateARM64SHA3D2Registers(op, ins, 3); err != nil { + return true, false, err + } + m, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arm64VectorArrangement{elementBits: 64, lanes: 2}) + if err != nil { + return true, false, err + } + n, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arm64VectorArrangement{elementBits: 64, lanes: 2}) + if err != nil { + return true, false, err + } + left := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl <2 x i64> %s, \n", left, m) + right := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr <2 x i64> %s, \n", right, m) + rotated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or <2 x i64> %%%s, %%%s\n", rotated, left, right) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor <2 x i64> %s, %%%s\n", result, n, rotated) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arm64VectorArrangement{elementBits: 64, lanes: 2}, "%"+result) + + case "VXAR": + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 || ins.Args[0].Kind != OpImm { + return true, false, fmt.Errorf("arm64 VXAR expects $0..$63 and three V.D2 operands with no suffix: %q", ins.Raw) + } + if ins.Args[0].Imm < 0 || ins.Args[0].Imm > 63 { + return true, false, fmt.Errorf("arm64 VXAR immediate is outside 0..63: %q", ins.Raw) + } + registerInstruction := ins + registerInstruction.Args = ins.Args[1:] + if err := validateARM64SHA3D2Registers(op, registerInstruction, 3); err != nil { + return true, false, err + } + m, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arm64VectorArrangement{elementBits: 64, lanes: 2}) + if err != nil { + return true, false, err + } + n, err := c.loadARM64VectorInteger(ins.Args[2].Reg, arm64VectorArrangement{elementBits: 64, lanes: 2}) + if err != nil { + return true, false, err + } + xored := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor <2 x i64> %s, %s\n", xored, m, n) + result := "%" + xored + if ins.Args[0].Imm != 0 { + shift := ins.Args[0].Imm + right := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr <2 x i64> %%%s, \n", right, xored, shift, shift) + left := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl <2 x i64> %%%s, \n", left, xored, 64-shift, 64-shift) + rotated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or <2 x i64> %%%s, %%%s\n", rotated, right, left) + result = "%" + rotated + } + return true, false, c.storeARM64VectorInteger(ins.Args[3].Reg, arm64VectorArrangement{elementBits: 64, lanes: 2}, result) + } + return false, false, nil +} + +func validateARM64SHA3D2Registers(op Op, ins Instr, count int) error { + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != count { + return fmt.Errorf("arm64 %s expects %d V.D2 operands with no suffix: %q", op, count, ins.Raw) + } + for _, arg := range ins.Args { + if arg.Kind != OpReg { + return fmt.Errorf("arm64 %s expects only V.D2 operands: %q", op, ins.Raw) + } + arrangement, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || arrangement.elementBits != 64 || arrangement.lanes != 2 { + return fmt.Errorf("arm64 %s expects only V.D2 operands: %q", op, ins.Raw) + } + } + return nil +} + +func arm64VectorI8Splat(value int) string { + values := make([]string, 16) + for i := range values { + values[i] = fmt.Sprintf("i8 %d", value) + } + return "<" + strings.Join(values, ", ") + ">" +} diff --git a/arm64_lower_sha3_test.go b/arm64_lower_sha3_test.go new file mode 100644 index 00000000..50409100 --- /dev/null +++ b/arm64_lower_sha3_test.go @@ -0,0 +1,163 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64SHA3Forms = ` +TEXT sha3forms(SB),$0-0 + VEOR3 V0.B16, V1.B16, V2.B16, V3.B16 + VBCAX V4.B16, V5.B16, V6.B16, V7.B16 + VRAX1 V8.D2, V9.D2, V10.D2 + VXAR $0, V11.D2, V12.D2, V13.D2 + VXAR $63, V14.D2, V15.D2, V16.D2 + RET +` + +func TestTranslateARM64SHA3CompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64SHA3Forms, true) + file, err := Parse(ArchARM64, arm64SHA3Forms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "sha3forms": {Name: "sha3forms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"xor <16 x i8>", "and <16 x i8>", "shl <2 x i64>", "lshr <2 x i64>"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 SHA3 lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sha3.ll", "arm64-sha3.o", ll) + }) + } +} + +func TestTranslateARM64SHA3RejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VEOR3 V0.B8, V1.B8, V2.B8, V3.B8", + "VEOR3 V0.B16, V1.B16, V2.B16", + "VBCAX V0.D2, V1.D2, V2.D2, V3.D2", + "VRAX1 V0.B16, V1.B16, V2.B16", + "VXAR $64, V0.D2, V1.D2, V2.D2", + "VXAR $1, V0.S4, V1.S4, V2.S4", + "VXAR.P $1, V0.D2, V1.D2, V2.D2", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsha3(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badsha3": {Name: "badsha3", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SHA3 optab", instruction) + } + }) + } +} + +func TestARM64SHA3RuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT sha3semantics(SB),$0-8 + MOVD out+0(FP), R0 + VMOVQ $0x0123456789abcdef, $0xfedcba9876543210, V1 + VMOVQ $0x1111222233334444, $0xaaaabbbbccccdddd, V2 + VMOVQ $0x0f0f0f0f0f0f0f0f, $0x5555555555555555, V3 + VEOR3 V1.B16, V2.B16, V3.B16, V4.B16 + VBCAX V1.B16, V2.B16, V3.B16, V5.B16 + VRAX1 V1.D2, V2.D2, V6.D2 + VXAR $13, V1.D2, V2.D2, V7.D2 + VMOV V4.D[0], R1 + VMOV V4.D[1], R2 + VMOV V5.D[0], R3 + VMOV V5.D[1], R4 + VMOV V6.D[0], R5 + VMOV V6.D[1], R6 + VMOV V7.D[0], R7 + VMOV V7.D[1], R8 + MOVD R1, 0(R0) + MOVD R2, 8(R0) + MOVD R3, 16(R0) + MOVD R4, 24(R0) + MOVD R5, 32(R0) + MOVD R6, 40(R0) + MOVD R7, 48(R0) + MOVD R8, 56(R0) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "sha3semantics": { + Name: "sha3semantics", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void sha3semantics(uint64_t *); +static uint64_t rotl1(uint64_t x) { return (x << 1) | (x >> 63); } +static uint64_t rotr13(uint64_t x) { return (x >> 13) | (x << 51); } +int main(void) { + uint64_t got[8] = {0}; + const uint64_t a[2] = {UINT64_C(0x0123456789abcdef), UINT64_C(0xfedcba9876543210)}; + const uint64_t m[2] = {UINT64_C(0x1111222233334444), UINT64_C(0xaaaabbbbccccdddd)}; + const uint64_t n[2] = {UINT64_C(0x0f0f0f0f0f0f0f0f), UINT64_C(0x5555555555555555)}; + sha3semantics(got); + for (int i = 0; i < 2; i++) { + if (got[i] != (a[i] ^ m[i] ^ n[i])) return 1; + if (got[2+i] != (n[i] ^ (m[i] & ~a[i]))) return 2; + if (got[4+i] != (m[i] ^ rotl1(a[i]))) return 3; + if (got[6+i] != rotr13(a[i] ^ m[i])) return 4; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_sha3", triple, ll, mainC, nil) +} diff --git a/arm64_lower_sha_test.go b/arm64_lower_sha_test.go new file mode 100644 index 00000000..c44b0e43 --- /dev/null +++ b/arm64_lower_sha_test.go @@ -0,0 +1,253 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64SHAForms = ` +TEXT shaforms(SB),$0-0 + SHA1C V0, V1, V2 + SHA1C V3.S4, V4, V5 + SHA1P V6, V7, V8 + SHA1P V9.S4, V10, V11 + SHA1M V12, V13, V14 + SHA1M V15.S4, V16, V17 + SHA1H V18, V19 + SHA1SU0 V20.S4, V21.S4, V22.S4 + SHA1SU1 V23.S4, V24.S4 + SHA256H V25, V26, V27 + SHA256H V28.S4, V29, V30 + SHA256H2 V0, V1, V2 + SHA256H2 V3.S4, V4, V5 + SHA256SU0 V6.S4, V7.S4 + SHA256SU1 V8.S4, V9.S4, V10.S4 + SHA512H V11, V12, V13 + SHA512H V14.D2, V15, V16 + SHA512H2 V17, V18, V19 + SHA512H2 V20.D2, V21, V22 + SHA512SU0 V23.D2, V24.D2 + SHA512SU1 V25.D2, V26.D2, V27.D2 + RET +` + +func TestTranslateARM64SHACompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64SHAForms, true) + file, err := Parse(ArchARM64, arm64SHAForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "shaforms": {Name: "shaforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "@llvm.aarch64.crypto.sha1c", + "@llvm.aarch64.crypto.sha1p", + "@llvm.aarch64.crypto.sha1m", + "@llvm.aarch64.crypto.sha1h", + "@llvm.aarch64.crypto.sha1su0", + "@llvm.aarch64.crypto.sha1su1", + "@llvm.aarch64.crypto.sha256h", + "@llvm.aarch64.crypto.sha256h2", + "@llvm.aarch64.crypto.sha256su0", + "@llvm.aarch64.crypto.sha256su1", + "@llvm.aarch64.crypto.sha512h", + "@llvm.aarch64.crypto.sha512h2", + "@llvm.aarch64.crypto.sha512su0", + "@llvm.aarch64.crypto.sha512su1", + `"target-features"="+sha2,+sha3"`, + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 SHA lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sha.ll", "arm64-sha.o", ll) + }) + } +} + +func TestTranslateARM64SHARejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "SHA1C V0.B16, V1, V2", + "SHA1C V0.S4, V1.S4, V2", + "SHA1C V0.S4, V1, V2.S4", + "SHA1H V0.S4, V1", + "SHA1SU0 V0.S4, V1.S4, V2.D2", + "SHA1SU1 V0.B16, V1.B16", + "SHA256H V0.D2, V1, V2", + "SHA256SU0 V0.S4, V1", + "SHA256SU1 V0.S4, V1.D2, V2.S4", + "SHA512H V0.S4, V1, V2", + "SHA512SU0 V0.D2, V1.S4", + "SHA512SU1 V0.D2, V1.D2, V2.S4", + "SHA1C.P V0.S4, V1, V2", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsha(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badsha": {Name: "badsha", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SHA optab", instruction) + } + }) + } +} + +func TestARM64SHARuntimeOperandOrderAndResults(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT shasemantics(SB),$0-16 + MOVD out+0(FP), R1 + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA1C V0.S4, V1, V2 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA1P V0.S4, V1, V2 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA1M V0.S4, V1, V2 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16] + SHA1H V0, V2 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA1SU0 V0.S4, V1.S4, V2.S4 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA1SU1 V0.S4, V2.S4 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA256H V0.S4, V1, V2 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA256H2 V0.S4, V1, V2 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA256SU0 V0.S4, V2.S4 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA256SU1 V0.S4, V1.S4, V2.S4 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA512H V0.D2, V1, V2 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA512H2 V0.D2, V1, V2 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA512SU0 V0.D2, V2.D2 + VST1.P [V2.B16], 16(R1) + MOVD in+8(FP), R0 + VLD1 (R0), [V0.B16, V1.B16, V2.B16] + SHA512SU1 V0.D2, V1.D2, V2.D2 + VST1 [V2.B16], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "shasemantics": { + Name: "shasemantics", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void shasemantics(uint8_t *, const uint8_t *); + +static void oracle(uint8_t *out, const uint8_t *in) { + uint8_t *o = out; + __asm__ volatile( + ".arch armv8.4-a+sha3\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha1c q2, s1, v0.4s\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha1p q2, s1, v0.4s\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha1m q2, s1, v0.4s\n\tstr q2, [%0], #16\n\t" + "ldr q0, [%1]\n\tsha1h s2, s0\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha1su0 v2.4s, v1.4s, v0.4s\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha1su1 v2.4s, v0.4s\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha256h q2, q1, v0.4s\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha256h2 q2, q1, v0.4s\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha256su0 v2.4s, v0.4s\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha256su1 v2.4s, v1.4s, v0.4s\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha512h q2, q1, v0.2d\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha512h2 q2, q1, v0.2d\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha512su0 v2.2d, v0.2d\n\tstr q2, [%0], #16\n\t" + "ldp q0, q1, [%1]\n\tldr q2, [%1, #32]\n\tsha512su1 v2.2d, v1.2d, v0.2d\n\tstr q2, [%0]" + : "+r"(o) : "r"(in) : "v0", "v1", "v2", "memory"); +} + +int main(void) { + uint8_t in[48]; + uint8_t got[14 * 16] = {0}; + uint8_t want[14 * 16] = {0}; + for (unsigned i = 0; i < sizeof(in); ++i) in[i] = (uint8_t)(i * 37u + 11u); + shasemantics(got, in); + oracle(want, in); + return memcmp(got, want, sizeof(got)) != 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_sha", triple, ll, mainC, nil) +} diff --git a/arm64_lower_shift_insert.go b/arm64_lower_shift_insert.go new file mode 100644 index 00000000..53bc4880 --- /dev/null +++ b/arm64_lower_shift_insert.go @@ -0,0 +1,70 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorShiftInsert(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VSRI" && op != "VSLI" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects $shift, Vsrc., Vdst. and no suffix: %q", op, ins.Raw) + } + sourceArrangement, sourceOK := parseARM64VectorArrangement(ins.Args[1].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[2].Reg) + allowed := func(a arm64VectorArrangement) bool { + return (a.elementBits == 8 && (a.lanes == 8 || a.lanes == 16)) || + (a.elementBits == 16 && (a.lanes == 4 || a.lanes == 8)) || + (a.elementBits == 32 && (a.lanes == 2 || a.lanes == 4)) || + (a.elementBits == 64 && a.lanes == 2) + } + if !sourceOK || !destinationOK || sourceArrangement != destinationArrangement || !allowed(sourceArrangement) { + return true, false, fmt.Errorf("arm64 %s requires matching B8/B16/H4/H8/S2/S4/D2 arrangements: %q", op, ins.Raw) + } + shift := ins.Args[0].Imm + if op == "VSRI" { + if shift < 1 || shift > int64(sourceArrangement.elementBits) { + return true, false, fmt.Errorf("arm64 VSRI shift must be in [1,%d]: %q", sourceArrangement.elementBits, ins.Raw) + } + } else if shift < 0 || shift >= int64(sourceArrangement.elementBits) { + return true, false, fmt.Errorf("arm64 VSLI shift must be in [0,%d]: %q", sourceArrangement.elementBits-1, ins.Raw) + } + source, err := c.loadARM64VectorInteger(ins.Args[1].Reg, sourceArrangement) + if err != nil { + return true, false, err + } + destination, err := c.loadARM64VectorInteger(ins.Args[2].Reg, destinationArrangement) + if err != nil { + return true, false, err + } + vectorType := fmt.Sprintf("<%d x i%d>", sourceArrangement.lanes, sourceArrangement.elementBits) + result := source + if op == "VSRI" { + if shift == int64(sourceArrangement.elementBits) { + result = destination + } else { + lowBits := int64(sourceArrangement.elementBits) - shift + high := c.newTmp() + preserved := c.newTmp() + inserted := c.newTmp() + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %s\n", high, vectorType, destination, arm64VectorIntegerSplat(sourceArrangement, lowBits)) + fmt.Fprintf(c.b, " %%%s = shl %s %%%s, %s\n", preserved, vectorType, high, arm64VectorIntegerSplat(sourceArrangement, lowBits)) + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %s\n", inserted, vectorType, source, arm64VectorIntegerSplat(sourceArrangement, shift)) + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %%%s\n", combined, vectorType, preserved, inserted) + result = "%" + combined + } + } else if shift > 0 { + preserved := c.newTmp() + inserted := c.newTmp() + combined := c.newTmp() + lowMask := int64((uint64(1) << uint(shift)) - 1) + fmt.Fprintf(c.b, " %%%s = and %s %s, %s\n", preserved, vectorType, destination, arm64VectorIntegerSplat(sourceArrangement, lowMask)) + fmt.Fprintf(c.b, " %%%s = shl %s %s, %s\n", inserted, vectorType, source, arm64VectorIntegerSplat(sourceArrangement, shift)) + fmt.Fprintf(c.b, " %%%s = or %s %%%s, %%%s\n", combined, vectorType, preserved, inserted) + result = "%" + combined + } + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, destinationArrangement, result) +} diff --git a/arm64_lower_shift_insert_test.go b/arm64_lower_shift_insert_test.go new file mode 100644 index 00000000..22da6e2b --- /dev/null +++ b/arm64_lower_shift_insert_test.go @@ -0,0 +1,150 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64VectorShiftInsertCompleteGoAssemblerForms(t *testing.T) { + forms := []struct { + arrangement string + bits int + }{{"B8", 8}, {"B16", 8}, {"H4", 16}, {"H8", 16}, {"S2", 32}, {"S4", 32}, {"D2", 64}} + var source strings.Builder + source.WriteString("TEXT vectorshiftinsertforms(SB),$0-0\n") + for _, form := range forms { + for _, shift := range []int{1, form.bits} { + fmt.Fprintf(&source, "\tVSRI $%d, V0.%s, V1.%s\n", shift, form.arrangement, form.arrangement) + } + for _, shift := range []int{0, form.bits - 1} { + fmt.Fprintf(&source, "\tVSLI $%d, V2.%s, V3.%s\n", shift, form.arrangement, form.arrangement) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"vectorshiftinsertforms": {Name: "vectorshiftinsertforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"lshr <", "shl <", "and <", "or <"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 vector shift-insert lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-shift-insert.ll", "arm64-vector-shift-insert.o", ll) + }) + } +} + +func TestTranslateARM64VectorShiftInsertRejectsInvalidForms(t *testing.T) { + for _, tc := range []struct { + instruction string + goAccepts bool + }{ + {"VSRI $0, V0.S4, V1.S4", false}, + {"VSRI $33, V0.S4, V1.S4", false}, + // Go 1.27 accepts this and encodes it as a different element width. + // Retain the architectural range check instead of copying that bug. + {"VSLI $-1, V0.S4, V1.S4", true}, + {"VSLI $32, V0.S4, V1.S4", false}, + {"VSRI $1, V0.S2, V1.S4", false}, + {"VSLI $1, V0.D1, V1.D1", false}, + {"VSRI.P $1, V0.S4, V1.S4", false}, + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(tc.instruction), func(t *testing.T) { + source := "TEXT badvectorshiftinsert(SB),$0-0\n\t" + tc.instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, tc.goAccepts) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", + Sigs: map[string]FuncSig{"badvectorshiftinsert": {Name: "badvectorshiftinsert", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted invalid vector shift-insert form %q", tc.instruction) + } + }) + } +} + +func TestARM64VectorShiftInsertRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectorshiftinsert(SB),$0-24 + MOVD src+0(FP), R0 + MOVD dst+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V1.S4] + VSRI $20, V0.S4, V1.S4 + VST1.P [V1.S4], 16(R2) + VLD1 (R1), [V1.S4] + VSLI $7, V0.S4, V1.S4 + VST1 [V1.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorshiftinsert": { + Name: "vectorshiftinsert", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void vectorshiftinsert(const uint32_t *, const uint32_t *, uint32_t *); +int main(void) { + const uint32_t src[4] = {0x12345678u, 0xffffffffu, 0x80000000u, 1u}; + const uint32_t dst[4] = {0xabcdef01u, 0x01234567u, 0xffffffffu, 0u}; + uint32_t got[8] = {0}; + vectorshiftinsert(src, dst, got); + for (int i = 0; i < 4; i++) { + uint32_t sri = (dst[i] & 0xfffff000u) | (src[i] >> 20); + uint32_t sli = (dst[i] & 0x0000007fu) | (src[i] << 7); + if (got[i] != sri) return i + 1; + if (got[4+i] != sli) return i + 11; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_shift_insert", triple, ll, mainC, nil) +} diff --git a/arm64_lower_shift_left.go b/arm64_lower_shift_left.go new file mode 100644 index 00000000..c1a563e2 --- /dev/null +++ b/arm64_lower_shift_left.go @@ -0,0 +1,33 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerARM64VectorShiftLeft implements Go's complete AVSHL immediate optab +// row for all seven accepted 64- and 128-bit vector arrangements. +func (c *arm64Ctx) lowerARM64VectorShiftLeft(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VSHL" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != "VSHL" || len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 VSHL expects $shift, Vsrc., Vdst. with no suffix: %q", ins.Raw) + } + sourceArrangement, sourceValid := parseARM64VectorArrangement(ins.Args[1].Reg) + destinationArrangement, destinationValid := parseARM64VectorArrangement(ins.Args[2].Reg) + if !sourceValid || !destinationValid || sourceArrangement != destinationArrangement || !arm64VDUPArrangementAllowed(sourceArrangement) { + return true, false, fmt.Errorf("arm64 VSHL requires matching B8/B16/H4/H8/S2/S4/D2 arrangements: %q", ins.Raw) + } + shift := ins.Args[0].Imm + if shift < 0 || shift >= int64(sourceArrangement.elementBits) { + return true, false, fmt.Errorf("arm64 VSHL shift must be in [0,%d]: %q", sourceArrangement.elementBits-1, ins.Raw) + } + source, err := c.loadARM64VectorInteger(ins.Args[1].Reg, sourceArrangement) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl <%d x i%d> %s, %s\n", result, sourceArrangement.lanes, sourceArrangement.elementBits, source, arm64VectorIntegerSplat(sourceArrangement, shift)) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, sourceArrangement, "%"+result) +} diff --git a/arm64_lower_shift_left_test.go b/arm64_lower_shift_left_test.go new file mode 100644 index 00000000..6cf62f5b --- /dev/null +++ b/arm64_lower_shift_left_test.go @@ -0,0 +1,146 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strconv" + "strings" + "testing" +) + +func TestTranslateARM64VectorShiftLeftCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT vectorshiftleftforms(SB),$0-0\n") + for _, form := range []struct { + arrangement string + maxShift int + }{ + {"B8", 7}, {"B16", 7}, {"H4", 15}, {"H8", 15}, + {"S2", 31}, {"S4", 31}, {"D2", 63}, + } { + source.WriteString("\tVSHL $0, V0." + form.arrangement + ", V1." + form.arrangement + "\n") + source.WriteString("\tVSHL $" + strconv.Itoa(form.maxShift) + ", V2." + form.arrangement + ", V3." + form.arrangement + "\n") + } + source.WriteString("\tRET\n") + forms := source.String() + requireARM64GoAssemblerResult(t, forms, true) + file, err := Parse(ArchARM64, forms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorshiftleftforms": {Name: "vectorshiftleftforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, "shl <") { + t.Fatalf("ARM64 VSHL lowering for %s omitted vector shift:\n%s", triple, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-shift-left.ll", "arm64-vector-shift-left.o", ll) + }) + } +} + +func TestTranslateARM64VectorShiftLeftRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VSHL $8, V0.B16, V1.B16", + "VSHL $16, V0.H8, V1.H8", + "VSHL $32, V0.S4, V1.S4", + "VSHL $64, V0.D2, V1.D2", + "VSHL $1, V0.S2, V1.S4", + "VSHL $1, V0.D1, V1.D1", + "VSHL V0.S4, V1.S4", + "VSHL.P $1, V0.S4, V1.S4", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badvectorshiftleft(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorshiftleft": {Name: "badvectorshiftleft", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VSHL optab", instruction) + } + }) + } +} + +func TestARM64VectorShiftLeftRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectorshiftleft(SB),$0-8 + MOVD out+0(FP), R0 + VMOVQ $0x0000000200000001, $0x8000000040000000, V1 + VSHL $1, V1.S4, V2.S4 + VSHL $31, V1.S4, V3.S4 + VMOV V2.D[0], R1 + VMOV V2.D[1], R2 + VMOV V3.D[0], R3 + VMOV V3.D[1], R4 + MOVD R1, 0(R0) + MOVD R2, 8(R0) + MOVD R3, 16(R0) + MOVD R4, 24(R0) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorshiftleft": { + Name: "vectorshiftleft", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void vectorshiftleft(uint64_t *); +int main(void) { + uint64_t got[4] = {0}; + vectorshiftleft(got); + if (got[0] != UINT64_C(0x0000000400000002) || got[1] != UINT64_C(0x0000000080000000)) return 1; + if (got[2] != UINT64_C(0x0000000080000000) || got[3] != 0) return 2; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_shift_left", triple, ll, mainC, nil) +} diff --git a/arm64_lower_shift_narrow.go b/arm64_lower_shift_narrow.go new file mode 100644 index 00000000..0539aa00 --- /dev/null +++ b/arm64_lower_shift_narrow.go @@ -0,0 +1,75 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorShiftNarrow(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VSHRN" && op != "VSHRN2" && op != "VRSHRN" && op != "VRSHRN2" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || + ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects immediate, wide vector source, narrow vector destination, and no suffix: %q", op, ins.Raw) + } + + sourceArrangement, sourceOK := parseARM64VectorArrangement(ins.Args[1].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[2].Reg) + highHalf := op == "VSHRN2" || op == "VRSHRN2" + rounding := op == "VRSHRN" || op == "VRSHRN2" + wantDestinationLanes := sourceArrangement.lanes + if highHalf { + wantDestinationLanes *= 2 + } + shift := ins.Args[0].Imm + if !sourceOK || !destinationOK || + sourceArrangement.lanes*sourceArrangement.elementBits != 128 || + sourceArrangement.elementBits != destinationArrangement.elementBits*2 || + destinationArrangement.lanes != wantDestinationLanes || + shift < 1 || shift > int64(destinationArrangement.elementBits) { + return true, false, fmt.Errorf("arm64 %s requires $1..$N with H8->B8/S4->H4/D2->S2 (or the doubled *2 destination): %q", op, ins.Raw) + } + + source, err := c.loadARM64VectorInteger(ins.Args[1].Reg, sourceArrangement) + if err != nil { + return true, false, err + } + sourceType := fmt.Sprintf("<%d x i%d>", sourceArrangement.lanes, sourceArrangement.elementBits) + shifted := c.newTmp() + shiftValue := arm64VectorIntegerSplat(sourceArrangement, shift) + if rounding { + // RSHRN rounds the signed source before narrowing. The addition is + // intentionally wrapping at the source width, matching the ARM + // instruction's two's-complement operation for non-saturating forms. + bias := arm64VectorIntegerSplat(sourceArrangement, int64(1)<<(shift-1)) + rounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", rounded, sourceType, source, bias) + fmt.Fprintf(c.b, " %%%s = ashr %s %%%s, %s\n", shifted, sourceType, rounded, shiftValue) + } else { + fmt.Fprintf(c.b, " %%%s = lshr %s %s, %s\n", shifted, sourceType, source, shiftValue) + } + destinationType := fmt.Sprintf("<%d x i%d>", sourceArrangement.lanes, destinationArrangement.elementBits) + narrowed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", narrowed, sourceType, shifted, destinationType) + if !highHalf { + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, destinationArrangement, "%"+narrowed) + } + + // VSHRN2 preserves the existing low half and inserts the narrowed values + // into the high half of the destination vector. + result, err := c.loadARM64VectorInteger(ins.Args[2].Reg, destinationArrangement) + if err != nil { + return true, false, err + } + fullDestinationType := fmt.Sprintf("<%d x i%d>", destinationArrangement.lanes, destinationArrangement.elementBits) + for lane := 0; lane < sourceArrangement.lanes; lane++ { + element := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", element, destinationType, narrowed, lane) + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i%d %%%s, i32 %d\n", + inserted, fullDestinationType, result, destinationArrangement.elementBits, element, sourceArrangement.lanes+lane) + result = "%" + inserted + } + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, destinationArrangement, result) +} diff --git a/arm64_lower_shift_narrow_test.go b/arm64_lower_shift_narrow_test.go new file mode 100644 index 00000000..a30c308f --- /dev/null +++ b/arm64_lower_shift_narrow_test.go @@ -0,0 +1,93 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorShiftNarrowCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 exposes exactly H8->B8, S4->H4, and D2->S2 for VSHRN; + // VSHRN2 writes the same narrowed lanes into the high half. Exercise both + // endpoints of every legal immediate interval: 1..8, 1..16, and 1..32. + const source = `TEXT ·vectorShiftNarrowForms(SB), $0-0 + VSHRN $1, V1.H8, V0.B8 + VSHRN $8, V31.H8, V30.B8 + VSHRN $1, V2.S4, V3.H4 + VSHRN $16, V30.S4, V29.H4 + VSHRN $1, V4.D2, V5.S2 + VSHRN $32, V29.D2, V28.S2 + VSHRN2 $1, V6.H8, V7.B16 + VSHRN2 $8, V28.H8, V27.B16 + VSHRN2 $1, V8.S4, V9.H8 + VSHRN2 $16, V27.S4, V26.H8 + VSHRN2 $1, V10.D2, V11.S4 + VSHRN2 $32, V26.D2, V25.S4 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorShiftNarrowForms": {Name: "vectorShiftNarrowForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{"lshr <", "trunc <", "insertelement <"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s VSHRN IR omitted %q:\n%s", triple, want, ll) + } + } + compileLLVMToObject(t, llc, triple, "arm64-vector-shift-narrow.ll", "arm64-vector-shift-narrow.o", ll) + } +} + +func TestTranslateARM64VectorShiftNarrowRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VSHRN $0, V0.H8, V1.B8", + "VSHRN $9, V0.H8, V1.B8", + "VSHRN $17, V0.S4, V1.H4", + "VSHRN $33, V0.D2, V1.S2", + "VSHRN V0.H8, V1.B8", + "VSHRN $1, V0.B16, V1.B8", + "VSHRN2 $1, V0.H8, V1.B8", + "VSHRN.P $1, V0.H8, V1.B8", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT ·badVectorShiftNarrow(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badVectorShiftNarrow": {Name: "badVectorShiftNarrow", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VSHRN tables", instruction) + } + }) + } +} diff --git a/arm64_lower_structure.go b/arm64_lower_structure.go new file mode 100644 index 00000000..33ee5485 --- /dev/null +++ b/arm64_lower_structure.go @@ -0,0 +1,245 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64StructureLoadStoreCounts = map[Op]int{ + "VLD1": 1, + "VLD2": 2, + "VLD3": 3, + "VLD4": 4, + "VLD1R": 1, + "VLD2R": 2, + "VLD3R": 3, + "VLD4R": 4, + "VST1": 1, + "VST2": 2, + "VST3": 3, + "VST4": 4, +} + +func (c *arm64Ctx) lowerARM64StructureLoadStore(op Op, postInc bool, ins Instr) (ok bool, terminated bool, err error) { + registerCount, handled := arm64StructureLoadStoreCounts[op] + if !handled { + return false, false, nil + } + // VLD1 also has single-lane forms (for example VLD1.P (R0), V1.S[2]). + // Keep those in the lane-specific lowerer below this mechanism. + if op == "VLD1" && len(ins.Args) == 2 && ins.Args[1].Kind == OpReg { + return false, false, nil + } + if op == "VST1" && len(ins.Args) == 2 && ins.Args[0].Kind == OpReg && ins.Args[1].Kind == OpMem { + return false, false, nil + } + rawOp := strings.ToUpper(string(ins.Op)) + load := strings.HasPrefix(string(op), "VLD") + replicate := strings.HasSuffix(string(op), "R") + if rawOp != string(op) && rawOp != string(op)+".P" { + return true, false, fmt.Errorf("arm64 %s accepts only the optional .P suffix: %q", op, ins.Raw) + } + if postInc != strings.HasSuffix(rawOp, ".P") || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects one memory operand and one vector register list: %q", op, ins.Raw) + } + var memory Operand + var listed []Reg + if load { + if ins.Args[0].Kind != OpMem || ins.Args[1].Kind != OpRegList { + return true, false, fmt.Errorf("arm64 %s expects memory, [V...]: %q", op, ins.Raw) + } + memory, listed = ins.Args[0], ins.Args[1].RegList + } else { + if ins.Args[0].Kind != OpRegList || ins.Args[1].Kind != OpMem { + return true, false, fmt.Errorf("arm64 %s expects [V...], memory: %q", op, ins.Raw) + } + listed, memory = ins.Args[0].RegList, ins.Args[1] + } + if len(listed) < 1 || len(listed) > 4 { + return true, false, fmt.Errorf("arm64 %s expects a Go C_LIST containing one through four registers: %q", op, ins.Raw) + } + if replicate && postInc && memory.Mem.Off != 0 && len(listed) != registerCount { + return true, false, fmt.Errorf("arm64 %s explicit-immediate post-indexed form expects exactly %d vector registers: %q", op, registerCount, ins.Raw) + } + arrangement, valid := parseARM64VectorArrangement(listed[0]) + firstIndex, firstValid := arm64ParseVReg(listed[0]) + if !valid || !firstValid { + return true, false, fmt.Errorf("arm64 %s requires an arranged vector list: %q", op, ins.Raw) + } + for i, reg := range listed { + parsed, ok := parseARM64VectorArrangement(reg) + index, indexOK := arm64ParseVReg(reg) + if !ok || parsed != arrangement || !indexOK || index != (firstIndex+i)%32 { + return true, false, fmt.Errorf("arm64 %s requires consecutive same-arrangement vector registers: %q", op, ins.Raw) + } + } + if op == "VLD1" || op == "VST1" { + registerCount = len(listed) + } + registers := make([]Reg, registerCount) + arrangementName := arm64VectorArrangementName(arrangement) + for i := range registers { + registers[i] = Reg(fmt.Sprintf("V%d.%s", (firstIndex+i)%32, arrangementName)) + } + activeBytes := arrangement.lanes * arrangement.elementBits / 8 + incrementBytes := registerCount * activeBytes + immediateBytes := len(listed) * activeBytes + if replicate { + incrementBytes = registerCount * arrangement.elementBits / 8 + immediateBytes = len(listed) * arrangement.elementBits / 8 + } + addr, base, increment, err := c.arm64StructureAddress(memory.Mem, postInc, int64(incrementBytes), int64(immediateBytes)) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w", op, err) + } + if replicate { + for registerIndex, reg := range registers { + elementOffset := int64(registerIndex * arrangement.elementBits / 8) + element, err := c.arm64LoadStructureElement(addr, elementOffset, arrangement.elementBits) + if err != nil { + return true, false, err + } + value := c.arm64VDUPSplat(arrangement, element) + if err := c.storeARM64VectorInteger(reg, arrangement, value); err != nil { + return true, false, err + } + } + } else if load { + for registerIndex, reg := range registers { + value := "poison" + for lane := 0; lane < arrangement.lanes; lane++ { + elementOffset := arm64StructureElementOffset(op, arrangement, registerCount, registerIndex, lane) + element, err := c.arm64LoadStructureElement(addr, elementOffset, arrangement.elementBits) + if err != nil { + return true, false, err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %s, i32 %d\n", + inserted, arrangement.lanes, arrangement.elementBits, value, arrangement.elementBits, element, lane) + value = "%" + inserted + } + if err := c.storeARM64VectorInteger(reg, arrangement, value); err != nil { + return true, false, err + } + } + } else { + values := make([]string, registerCount) + for i, reg := range registers { + values[i], err = c.loadARM64VectorInteger(reg, arrangement) + if err != nil { + return true, false, err + } + } + for lane := 0; lane < arrangement.lanes; lane++ { + for registerIndex := range registers { + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", element, arrangement.lanes, arrangement.elementBits, values[registerIndex], lane) + elementOffset := arm64StructureElementOffset(op, arrangement, registerCount, registerIndex, lane) + if err := c.arm64StoreStructureElement(addr, elementOffset, arrangement.elementBits, "%"+element); err != nil { + return true, false, err + } + } + } + } + if postInc { + if err := c.arm64UpdatePostIncrement(base, increment); err != nil { + return true, false, err + } + } + return true, false, nil +} + +func arm64StructureElementOffset(op Op, arrangement arm64VectorArrangement, registerCount, registerIndex, lane int) int64 { + elementBytes := arrangement.elementBits / 8 + if op == "VLD1" || op == "VST1" { + return int64(registerIndex*arrangement.lanes*elementBytes + lane*elementBytes) + } + return int64((lane*registerCount + registerIndex) * elementBytes) +} + +func arm64VectorArrangementName(arrangement arm64VectorArrangement) string { + kind := "B" + switch arrangement.elementBits { + case 16: + kind = "H" + case 32: + kind = "S" + case 64: + kind = "D" + } + return fmt.Sprintf("%s%d", kind, arrangement.lanes) +} + +func (c *arm64Ctx) arm64StructureAddress(mem MemRef, postInc bool, incrementBytes, immediateBytes int64) (addr string, base Reg, increment string, err error) { + base = mem.Base + if base == ZR || base == Reg("RSP") { + base = SP + } + addr, err = c.loadReg(base) + if err != nil { + return "", "", "", err + } + if !postInc { + if mem.Off != 0 || mem.Index != "" { + return "", "", "", fmt.Errorf("non-post-indexed structure memory must use (Rbase)") + } + return addr, base, "", nil + } + if mem.Index != "" { + if mem.Off != 0 || mem.IndexExt != "" || (mem.Scale != 0 && mem.Scale != 1) { + return "", "", "", fmt.Errorf("register post-increment requires plain (Rbase)(Rindex)") + } + increment, err = c.loadReg(mem.Index) + return addr, base, increment, err + } + // `(Rbase)` is Go's implicit post-increment spelling. The encoded + // instruction advances by the structure width even though its parsed + // displacement is zero. + if mem.Off == 0 { + return addr, base, c.imm64(incrementBytes), nil + } + if mem.Off != immediateBytes { + return "", "", "", fmt.Errorf("immediate post-increment is %d bytes, want %d for the written register list", mem.Off, immediateBytes) + } + return addr, base, c.imm64(incrementBytes), nil +} + +func (c *arm64Ctx) arm64UpdatePostIncrement(base Reg, increment string) error { + if increment == "" { + return nil + } + baseValue, err := c.loadReg(base) + if err != nil { + return err + } + updated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", updated, baseValue, increment) + return c.storeReg(base, "%"+updated) +} + +func (c *arm64Ctx) arm64LoadStructureElement(addr string, offset int64, bits int) (string, error) { + elementAddr := addr + if offset != 0 { + added := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %d\n", added, addr, offset) + elementAddr = "%" + added + } + pointer := c.newTmp() + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, elementAddr) + fmt.Fprintf(c.b, " %%%s = load i%d, ptr %%%s, align 1\n", value, bits, pointer) + return "%" + value, nil +} + +func (c *arm64Ctx) arm64StoreStructureElement(addr string, offset int64, bits int, value string) error { + elementAddr := addr + if offset != 0 { + added := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %d\n", added, addr, offset) + elementAddr = "%" + added + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, elementAddr) + fmt.Fprintf(c.b, " store i%d %s, ptr %%%s, align 1\n", bits, value, pointer) + return nil +} diff --git a/arm64_lower_structure_lane_test.go b/arm64_lower_structure_lane_test.go new file mode 100644 index 00000000..c9be1978 --- /dev/null +++ b/arm64_lower_structure_lane_test.go @@ -0,0 +1,41 @@ +//go:build !llgo + +package plan9asm + +import "testing" + +func TestTranslateARM64StructureStoreLaneForms(t *testing.T) { + const source = `TEXT structurestorelanes(SB),$0-0 + VST1.P V0.B[0], 1(R0) + VST1.P V1.H[3], 2(R0) + VST1.P V2.S[1], 4(R0) + VST1.P V3.D[0], 8(R0) + VST1 V4.B[15], (R0) + VST1 V5.H[7], (R0) + VST1 V6.S[3], (R0) + VST1 V7.D[1], (R0) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"structurestorelanes": {Name: "structurestorelanes", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-structure-store-lanes.ll", "arm64-structure-store-lanes.o", ll) + }) + } +} diff --git a/arm64_lower_structure_replicate_test.go b/arm64_lower_structure_replicate_test.go new file mode 100644 index 00000000..48a334db --- /dev/null +++ b/arm64_lower_structure_replicate_test.go @@ -0,0 +1,152 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64StructureReplicateLoadCompleteGoAssemblerForms(t *testing.T) { + arrangements := []string{"B8", "B16", "H4", "H8", "S2", "S4", "D1", "D2"} + var source strings.Builder + source.WriteString("TEXT structurereplicateloadforms(SB),$0-0\n") + for count := 1; count <= 4; count++ { + op := fmt.Sprintf("VLD%dR", count) + for _, arrangement := range arrangements { + regs := arm64TestVectorList(28, count, arrangement) + elementBytes := map[byte]int{'B': 1, 'H': 2, 'S': 4, 'D': 8}[arrangement[0]] + fmt.Fprintf(&source, "\t%s (R0), %s\n", op, regs) + fmt.Fprintf(&source, "\t%s.P %d(R0), %s\n", op, count*elementBytes, regs) + fmt.Fprintf(&source, "\t%s.P (R0)(R1), %s\n", op, regs) + } + // Go classifies every one-through-four-register list as C_LIST. The + // opcode still determines how many registers hardware writes. Only an + // explicit nonzero post-index immediate triggers an exact-count check. + for writtenCount := 1; writtenCount <= 4; writtenCount++ { + regs := arm64TestVectorList(24, writtenCount, "S4") + fmt.Fprintf(&source, "\t%s (R0), %s\n", op, regs) + fmt.Fprintf(&source, "\t%s.P (R0), %s\n", op, regs) + fmt.Fprintf(&source, "\t%s.P (R0)(R1), %s\n", op, regs) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "structurereplicateloadforms": {Name: "structurereplicateloadforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load i8", "load i16", "load i32", "load i64", "shufflevector"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 VLDnR lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-structure-replicate-load.ll", "arm64-structure-replicate-load.o", ll) + }) + } +} + +func TestTranslateARM64StructureReplicateLoadRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VLD2R (R0), [V0.S4, V2.S4]", + "VLD2R.P 4(R0), [V0.S4]", + "VLD3R (R0), [V0.H8, V1.S4, V2.H8]", + "VLD4R.P 8(R0), [V0.S4, V1.S4, V2.S4, V3.S4]", + "VLD1R.Z (R0), [V0.B16]", + "VLD1R 1(R0), [V0.B16]", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badstructurereplicateload(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badstructurereplicateload": {Name: "badstructurereplicateload", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VLDnR optab", instruction) + } + }) + } +} + +func TestARM64StructureReplicateLoadRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT structurereplicateload(SB),$0-0 + VLD4R.P 16(R0), [V0.S4, V1.S4, V2.S4, V3.S4] + VST1.P [V0.S4, V1.S4, V2.S4, V3.S4], 64(R1) + MOVD R0, 0(R2) + MOVD R1, 8(R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "structurereplicateload": { + Name: "structurereplicateload", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void structurereplicateload(const uint32_t *, uint32_t *, uintptr_t *); +int main(void) { + const uint32_t input[4] = {11, 22, 33, 44}; + uint32_t output[16] = {0}; + uintptr_t advanced[2] = {0}; + structurereplicateload(input, output, advanced); + for (int group = 0; group < 4; group++) + for (int lane = 0; lane < 4; lane++) + if (output[group*4+lane] != input[group]) return 1 + group*4 + lane; + if (advanced[0] != (uintptr_t)(input+4)) return 30; + if (advanced[1] != (uintptr_t)(output+16)) return 31; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_structure_replicate_load", triple, ll, mainC, nil) +} diff --git a/arm64_lower_structure_test.go b/arm64_lower_structure_test.go new file mode 100644 index 00000000..b9be9e0c --- /dev/null +++ b/arm64_lower_structure_test.go @@ -0,0 +1,158 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64StructureLoadStoreCompleteGoAssemblerForms(t *testing.T) { + arrangements := []string{"B8", "B16", "H4", "H8", "S2", "S4", "D2"} + var source strings.Builder + source.WriteString("TEXT ·structureloadstoreforms(SB), $0-0\n") + for count := 1; count <= 4; count++ { + loadOp := fmt.Sprintf("VLD%d", count) + storeOp := fmt.Sprintf("VST%d", count) + for _, arrangement := range arrangements { + regs := arm64TestVectorList(0, count, arrangement) + fmt.Fprintf(&source, "\t%s (R0), %s\n", loadOp, regs) + fmt.Fprintf(&source, "\t%s %s, (R0)\n", storeOp, regs) + } + bytes := count * 16 + regs := arm64TestVectorList(28, count, "D2") + fmt.Fprintf(&source, "\t%s.P %d(R0), %s\n", loadOp, bytes, regs) + fmt.Fprintf(&source, "\t%s.P %s, %d(R0)\n", storeOp, regs, bytes) + regs = arm64TestVectorList(28, count, "B8") + fmt.Fprintf(&source, "\t%s.P (R0)(R1), %s\n", loadOp, regs) + fmt.Fprintf(&source, "\t%s.P %s, (R0)(R1)\n", storeOp, regs) + } + for count := 2; count <= 4; count++ { + regs := arm64TestVectorList(8, count, "S4") + fmt.Fprintf(&source, "\tVLD1 (R0), %s\n", regs) + fmt.Fprintf(&source, "\tVST1 %s, (R0)\n", regs) + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{"structureloadstoreforms": {Name: "structureloadstoreforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-structure-load-store.ll", "arm64-structure-load-store.o", ll) + }) + } +} + +func TestARM64StructureLoadStoreRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + source := ` +TEXT structureroundtrip(SB), $0-0 + VLD3.P 48(R0), [V0.S4, V1.S4, V2.S4] + VST1.P [V0.S4, V1.S4, V2.S4], 48(R1) + VLD1.P 48(R2), [V3.S4, V4.S4, V5.S4] + VST3.P [V3.S4, V4.S4, V5.S4], 48(R3) + MOVD R0, 0(R4) + MOVD R1, 8(R4) + MOVD R2, 16(R4) + MOVD R3, 24(R4) + RET +` + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + frame := FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + {Offset: 32, Type: Ptr, Index: 4, Field: -1}, + }} + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "structureroundtrip": {Name: "structureroundtrip", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr, Ptr}, Ret: Void, Frame: frame}, + }, + }) + if err != nil { + t.Fatal(err) + } + mainC := ` +#include +extern void structureroundtrip(const int32_t *, int32_t *, const int32_t *, int32_t *, uintptr_t *); +int main(void) { + const int32_t interleaved[12] = {10,20,30, 11,21,31, 12,22,32, 13,23,33}; + const int32_t separated[12] = {10,11,12,13, 20,21,22,23, 30,31,32,33}; + int32_t got_separated[12] = {0}, got_interleaved[12] = {0}; + uintptr_t advanced[4] = {0}; + structureroundtrip(interleaved, got_separated, separated, got_interleaved, advanced); + for (int i = 0; i < 12; i++) { + if (got_separated[i] != separated[i]) return 10+i; + if (got_interleaved[i] != interleaved[i]) return 30+i; + } + if (advanced[0] != (uintptr_t)(interleaved+12)) return 51; + if (advanced[1] != (uintptr_t)(got_separated+12)) return 52; + if (advanced[2] != (uintptr_t)(separated+12)) return 53; + if (advanced[3] != (uintptr_t)(got_interleaved+12)) return 54; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_structure_load_store", triple, ll, mainC, nil) +} + +func TestTranslateARM64StructureLoadStoreRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VLD2 (R0), [V0.S4, V2.S4]", + "VST3 [V0.B16, V1.H8, V2.B16], (R0)", + "VLD3.P 32(R0), [V0.S4, V1.S4, V2.S4]", + "VST4.Z [V0.B16, V1.B16, V2.B16, V3.B16], (R0)", + } { + source := "TEXT ·bad(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's structure load/store table", instruction) + } + } +} + +func arm64TestVectorList(start, count int, arrangement string) string { + regs := make([]string, count) + for i := range regs { + regs[i] = fmt.Sprintf("V%d.%s", (start+i)%32, arrangement) + } + return "[" + strings.Join(regs, ", ") + "]" +} diff --git a/arm64_lower_sve_absolute_difference.go b/arm64_lower_sve_absolute_difference.go new file mode 100644 index 00000000..b4fc34cd --- /dev/null +++ b/arm64_lower_sve_absolute_difference.go @@ -0,0 +1,193 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEAbsoluteDifferenceKind uint8 + +const ( + arm64SVEAbsoluteAccumulate arm64SVEAbsoluteDifferenceKind = iota + arm64SVEAbsoluteDifference + arm64SVEAbsoluteLongAccumulate + arm64SVEAbsoluteLongDifference + arm64SVEAbsolutePairAccumulate +) + +type arm64SVEAbsoluteDifferenceSpec struct { + intrinsic string + kind arm64SVEAbsoluteDifferenceKind +} + +var arm64SVEAbsoluteDifferenceSpecs = map[Op]arm64SVEAbsoluteDifferenceSpec{ + "ZSABA": {intrinsic: "saba", kind: arm64SVEAbsoluteAccumulate}, + "ZUABA": {intrinsic: "uaba", kind: arm64SVEAbsoluteAccumulate}, + "ZSABD": {intrinsic: "sabd", kind: arm64SVEAbsoluteDifference}, + "ZUABD": {intrinsic: "uabd", kind: arm64SVEAbsoluteDifference}, + "ZSABALB": {intrinsic: "sabalb", kind: arm64SVEAbsoluteLongAccumulate}, + "ZSABALT": {intrinsic: "sabalt", kind: arm64SVEAbsoluteLongAccumulate}, + "ZUABALB": {intrinsic: "uabalb", kind: arm64SVEAbsoluteLongAccumulate}, + "ZUABALT": {intrinsic: "uabalt", kind: arm64SVEAbsoluteLongAccumulate}, + "ZSABDLB": {intrinsic: "sabdlb", kind: arm64SVEAbsoluteLongDifference}, + "ZSABDLT": {intrinsic: "sabdlt", kind: arm64SVEAbsoluteLongDifference}, + "ZUABDLB": {intrinsic: "uabdlb", kind: arm64SVEAbsoluteLongDifference}, + "ZUABDLT": {intrinsic: "uabdlt", kind: arm64SVEAbsoluteLongDifference}, + "ZSADALP": {intrinsic: "sadalp", kind: arm64SVEAbsolutePairAccumulate}, + "ZUADALP": {intrinsic: "uadalp", kind: arm64SVEAbsolutePairAccumulate}, +} + +type arm64SVEAbsoluteDifferenceForm struct { + elementBits int + sourceBits int + first int + second int + predicate int + destination int +} + +func (c *arm64Ctx) lowerARM64SVEAbsoluteDifference(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEAbsoluteDifferenceSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + form, err := arm64ParseSVEAbsoluteDifferenceForm(op, spec, ins) + if err != nil { + return true, false, err + } + return true, false, c.lowerARM64SVEAbsoluteDifferenceForm(spec, form) +} + +func arm64ParseSVEAbsoluteDifferenceForm(op Op, spec arm64SVEAbsoluteDifferenceSpec, ins Instr) (arm64SVEAbsoluteDifferenceForm, error) { + form := arm64SVEAbsoluteDifferenceForm{} + switch spec.kind { + case arm64SVEAbsoluteDifference: + if len(ins.Args) != 4 { + return form, fmt.Errorf("arm64 %s expects Zm.T, Zdn.T, Pg/M, Zdn.T: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits || first != destination { + return form, fmt.Errorf("arm64 %s requires matching-width destructive data and P0..P7/M: %q", op, ins.Raw) + } + return arm64SVEAbsoluteDifferenceForm{elementBits: firstBits, first: first, second: second, predicate: predicate, destination: destination}, nil + case arm64SVEAbsolutePairAccumulate: + if len(ins.Args) != 3 { + return form, fmt.Errorf("arm64 %s expects Zn.Tb, Pg/M, Zda.T: %q", op, ins.Raw) + } + first, sourceBits, firstOK := arm64ParseSVEZElementReg(ins.Args[0]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !firstOK || !predicateOK || !destinationOK || sourceBits == 64 || destinationBits != 2*sourceBits { + return form, fmt.Errorf("arm64 %s requires a B/H/S source, P0..P7/M, and H/S/D accumulator: %q", op, ins.Raw) + } + return arm64SVEAbsoluteDifferenceForm{elementBits: destinationBits, sourceBits: sourceBits, first: first, predicate: predicate, destination: destination}, nil + default: + if len(ins.Args) != 3 { + return form, fmt.Errorf("arm64 %s expects three scalable vector operands: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != firstBits { + return form, fmt.Errorf("arm64 %s requires matching source widths: %q", op, ins.Raw) + } + if spec.kind == arm64SVEAbsoluteAccumulate { + if firstBits != destinationBits { + return form, fmt.Errorf("arm64 %s requires matching B/H/S/D sources and accumulator: %q", op, ins.Raw) + } + return arm64SVEAbsoluteDifferenceForm{elementBits: firstBits, first: first, second: second, destination: destination}, nil + } + if firstBits == 64 || destinationBits != 2*firstBits { + return form, fmt.Errorf("arm64 %s requires B/H/S sources widened to H/S/D: %q", op, ins.Raw) + } + return arm64SVEAbsoluteDifferenceForm{elementBits: destinationBits, sourceBits: firstBits, first: first, second: second, destination: destination}, nil + } +} + +func (c *arm64Ctx) lowerARM64SVEAbsoluteDifferenceForm(spec arm64SVEAbsoluteDifferenceSpec, form arm64SVEAbsoluteDifferenceForm) error { + if spec.kind == arm64SVEAbsoluteDifference { + first, vectorType, err := c.loadZRegElements(form.first, form.elementBits) + if err != nil { + return err + } + second, _, err := c.loadZRegElements(form.second, form.elementBits) + if err != nil { + return err + } + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + lanes := 128 / form.elementBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, spec.intrinsic, lanes, form.elementBits, predicateType, predicate, vectorType, first, vectorType, second) + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) + } + if spec.kind == arm64SVEAbsoluteAccumulate { + accumulator, vectorType, err := c.loadZRegElements(form.destination, form.elementBits) + if err != nil { + return err + } + first, _, err := c.loadZRegElements(form.first, form.elementBits) + if err != nil { + return err + } + second, _, err := c.loadZRegElements(form.second, form.elementBits) + if err != nil { + return err + } + lanes := 128 / form.elementBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, spec.intrinsic, lanes, form.elementBits, vectorType, accumulator, vectorType, first, vectorType, second) + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) + } + sourceType, _, err := arm64SVEVectorType(form.sourceBits) + if err != nil { + return err + } + destinationType, destinationLanes, err := arm64SVEVectorType(form.elementBits) + if err != nil { + return err + } + first, _, err := c.loadZRegElements(form.first, form.sourceBits) + if err != nil { + return err + } + accumulator := "" + if spec.kind == arm64SVEAbsoluteLongAccumulate || spec.kind == arm64SVEAbsolutePairAccumulate { + accumulator, _, err = c.loadZRegElements(form.destination, form.elementBits) + if err != nil { + return err + } + } + result := c.newTmp() + switch spec.kind { + case arm64SVEAbsoluteLongAccumulate: + second, _, err := c.loadZRegElements(form.second, form.sourceBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, destinationType, spec.intrinsic, destinationLanes, form.elementBits, destinationType, accumulator, sourceType, first, sourceType, second) + case arm64SVEAbsoluteLongDifference: + second, _, err := c.loadZRegElements(form.second, form.sourceBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, destinationType, spec.intrinsic, destinationLanes, form.elementBits, sourceType, first, sourceType, second) + case arm64SVEAbsolutePairAccumulate: + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, destinationType, spec.intrinsic, destinationLanes, form.elementBits, predicateType, predicate, destinationType, accumulator, sourceType, first) + default: + return fmt.Errorf("unknown ARM64 SVE absolute-difference kind %d", spec.kind) + } + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) +} diff --git a/arm64_lower_sve_absolute_difference_test.go b/arm64_lower_sve_absolute_difference_test.go new file mode 100644 index 00000000..f7424713 --- /dev/null +++ b/arm64_lower_sve_absolute_difference_test.go @@ -0,0 +1,103 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEAbsoluteDifferenceCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveabsdiffforms(SB),$0-0\n") + for _, op := range []string{"ZSABA", "ZUABA"} { + for _, width := range []string{"B", "H", "S", "D"} { + source.WriteString("\t" + op + " Z1." + width + ", Z2." + width + ", Z3." + width + "\n") + } + } + for _, op := range []string{"ZSABD", "ZUABD"} { + for predicate, width := range []string{"B", "H", "S", "D"} { + source.WriteString("\t" + op + " Z4." + width + ", Z5." + width + ", P" + string(rune('0'+predicate)) + ".M, Z5." + width + "\n") + } + } + for _, op := range []string{"ZSABALB", "ZSABALT", "ZUABALB", "ZUABALT", "ZSABDLB", "ZSABDLT", "ZUABDLB", "ZUABDLT"} { + for _, narrowWidth := range []string{"B", "H", "S"} { + wideWidth := map[string]string{"B": "H", "H": "S", "S": "D"}[narrowWidth] + source.WriteString("\t" + op + " Z6." + narrowWidth + ", Z7." + narrowWidth + ", Z8." + wideWidth + "\n") + } + } + for _, op := range []string{"ZSADALP", "ZUADALP"} { + for predicate, narrowWidth := range []string{"B", "H", "S"} { + wideWidth := map[string]string{"B": "H", "H": "S", "S": "D"}[narrowWidth] + source.WriteString("\t" + op + " Z9." + narrowWidth + ", P" + string(rune('4'+predicate)) + ".M, Z10." + wideWidth + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEAbsoluteDifferenceCompleteGo127Family(t *testing.T) { + source := arm64SVEAbsoluteDifferenceCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveabsdiffforms": {Name: "sveabsdiffforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.saba.nxv16i8", + "@llvm.aarch64.sve.uaba.nxv2i64", + "@llvm.aarch64.sve.sabd.nxv8i16", + "@llvm.aarch64.sve.uabd.nxv4i32", + "@llvm.aarch64.sve.sabalb.nxv8i16", + "@llvm.aarch64.sve.uabalt.nxv2i64", + "@llvm.aarch64.sve.sabdlt.nxv4i32", + "@llvm.aarch64.sve.uabdlb.nxv8i16", + "@llvm.aarch64.sve.sadalp.nxv8i16", + "@llvm.aarch64.sve.uadalp.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE absolute-difference lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-absolute-difference.ll", "arm64-sve-absolute-difference.o", ll) + }) + } +} + +func TestTranslateARM64SVEAbsoluteDifferenceRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSABA Z1.B, Z2.H, Z3.B", + "ZUABA Z1.S, Z2.S, Z3.D", + "ZSABD Z1.B, Z2.B, P0, Z2.B", + "ZUABD Z1.H, Z2.H, P8.M, Z2.H", + "ZSABD Z1.S, Z2.S, P0.M, Z3.S", + "ZSABALB Z1.B, Z2.H, Z3.H", + "ZUABALT Z1.S, Z2.S, Z3.S", + "ZSABDLB Z1.D, Z2.D, Z3.D", + "ZUABDLT Z1.H, Z2.H, Z3.H", + "ZSADALP Z1.B, P0, Z2.H", + "ZUADALP Z1.H, P0.M, Z2.H", + "ZSABA.Z Z1.B, Z2.B, Z3.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveabsdiff(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveabsdiff": {Name: "badsveabsdiff", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE absolute-difference forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_add.go b/arm64_lower_sve_add.go new file mode 100644 index 00000000..e668de81 --- /dev/null +++ b/arm64_lower_sve_add.go @@ -0,0 +1,146 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +type arm64SVEAddMode uint8 + +const ( + arm64SVEAddUnpredicated arm64SVEAddMode = iota + arm64SVEAddPredicated + arm64SVEAddImmediate +) + +type arm64RawSVEAdd struct { + mode arm64SVEAddMode + elementBits int + first int + second int + predicate int + immediate int + destination int +} + +func decodeARM64RawSVEAdd(word uint32) (arm64RawSVEAdd, bool) { + form := arm64RawSVEAdd{elementBits: 8 << (int(word>>22) & 3)} + switch { + case word&0xff3fe000 == 0x04000000: + form.mode = arm64SVEAddPredicated + form.destination = int(word) & 31 + form.first = form.destination + form.second = int(word>>5) & 31 + form.predicate = int(word>>10) & 7 + case word&0xff20fc00 == 0x04200000: + form.mode = arm64SVEAddUnpredicated + form.destination = int(word) & 31 + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + case word&0xff3fc000 == 0x2520c000: + form.mode = arm64SVEAddImmediate + form.destination = int(word) & 31 + form.first = form.destination + shift := 0 + if word&(1<<13) != 0 { + shift = 8 + } + if form.elementBits == 8 && shift != 0 { + return arm64RawSVEAdd{}, false + } + form.immediate = (int(word>>5) & 255) << shift + default: + return arm64RawSVEAdd{}, false + } + return form, true +} + +func arm64ParseSVEPredicateMerge(operand Operand) (int, bool) { + if operand.Kind != OpReg { + return 0, false + } + parts := strings.Split(strings.ToUpper(strings.TrimSpace(string(operand.Reg))), ".") + if len(parts) != 2 || parts[1] != "M" || !strings.HasPrefix(parts[0], "P") { + return 0, false + } + index, err := strconv.Atoi(strings.TrimPrefix(parts[0], "P")) + return index, err == nil && index >= 0 && index < 8 +} + +func arm64SVEAddImmediateRepresentable(elementBits int, immediate int64) bool { + if immediate >= 0 && immediate <= 255 { + return true + } + if elementBits == 8 || immediate%256 != 0 { + return false + } + unshifted := immediate / 256 + return unshifted >= 0 && unshifted <= 255 +} + +func (c *arm64Ctx) lowerARM64SVEAdd(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZADD" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 ZADD does not accept an instruction suffix: %q", ins.Raw) + } + + form := arm64RawSVEAdd{} + if len(ins.Args) == 3 && ins.Args[0].Kind == OpImm { + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if ins.Args[0].ImmRaw != "" || !firstOK || !destinationOK || first != destination || firstBits != destinationBits || !arm64SVEAddImmediateRepresentable(firstBits, ins.Args[0].Imm) { + return true, false, fmt.Errorf("arm64 ZADD immediate expects $imm, Zdn.T, Zdn.T with identical destructive registers: %q", ins.Raw) + } + form = arm64RawSVEAdd{mode: arm64SVEAddImmediate, elementBits: firstBits, first: first, destination: destination, immediate: int(ins.Args[0].Imm)} + } else if len(ins.Args) == 3 { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZADD vector expects Zm.T, Zn.T, Zd.T with one element width: %q", ins.Raw) + } + form = arm64RawSVEAdd{mode: arm64SVEAddUnpredicated, elementBits: firstBits, first: first, second: second, destination: destination} + } else if len(ins.Args) == 4 { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits || first != destination { + return true, false, fmt.Errorf("arm64 ZADD predicated expects Zm.T, Zdn.T, Pg.M, Zdn.T with identical destructive registers: %q", ins.Raw) + } + form = arm64RawSVEAdd{mode: arm64SVEAddPredicated, elementBits: firstBits, first: first, second: second, predicate: predicate, destination: destination} + } else { + return true, false, fmt.Errorf("arm64 ZADD expects a Go 1.27 SVE vector, predicated, or immediate form: %q", ins.Raw) + } + return true, false, c.lowerRawSVEAdd(form) +} + +func (c *arm64Ctx) lowerRawSVEAdd(form arm64RawSVEAdd) error { + first, vectorType, err := c.loadZRegElements(form.first, form.elementBits) + if err != nil { + return err + } + second := fmt.Sprintf("splat (i%d %d)", form.elementBits, form.immediate) + if form.mode != arm64SVEAddImmediate { + second, _, err = c.loadZRegElements(form.second, form.elementBits) + if err != nil { + return err + } + } + added := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", added, vectorType, first, second) + result := "%" + added + if form.mode == arm64SVEAddPredicated { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", selected, predicateType, predicate, vectorType, result, vectorType, first) + result = "%" + selected + } + return c.storeZRegElements(form.destination, form.elementBits, result) +} diff --git a/arm64_lower_sve_add_reduction.go b/arm64_lower_sve_add_reduction.go new file mode 100644 index 00000000..5387589a --- /dev/null +++ b/arm64_lower_sve_add_reduction.go @@ -0,0 +1,176 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEAddReductionKind uint8 + +const ( + arm64SVEFloatAddAccumulate arm64SVEAddReductionKind = iota + arm64SVEFloatAddReduce + arm64SVEFloatAddQuadReduce + arm64SVESignedAddReduce + arm64SVEUnsignedAddReduce +) + +type arm64SVEAddReductionSpec struct { + kind arm64SVEAddReductionKind + elementBits int +} + +var arm64SVEAddReductionSpecs = map[Op]arm64SVEAddReductionSpec{ + "ZFADDAD": {kind: arm64SVEFloatAddAccumulate, elementBits: 64}, + "ZFADDAH": {kind: arm64SVEFloatAddAccumulate, elementBits: 16}, + "ZFADDAS": {kind: arm64SVEFloatAddAccumulate, elementBits: 32}, + "ZFADDQV": {kind: arm64SVEFloatAddQuadReduce}, + "ZFADDVD": {kind: arm64SVEFloatAddReduce, elementBits: 64}, + "ZFADDVH": {kind: arm64SVEFloatAddReduce, elementBits: 16}, + "ZFADDVS": {kind: arm64SVEFloatAddReduce, elementBits: 32}, + "ZSADDVD": {kind: arm64SVESignedAddReduce}, + "ZUADDVD": {kind: arm64SVEUnsignedAddReduce}, +} + +type arm64SVEAddReductionForm struct { + elementBits int + source int + predicate int + destination int +} + +func (c *arm64Ctx) lowerARM64SVEAddReduction(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEAddReductionSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + form, err := arm64ParseSVEAddReductionForm(op, spec, ins) + if err != nil { + return true, false, err + } + return true, false, c.lowerARM64SVEAddReductionForm(spec, form, ins.Args[len(ins.Args)-1].Reg) +} + +func arm64ParseSVEAddReductionForm(op Op, spec arm64SVEAddReductionSpec, ins Instr) (arm64SVEAddReductionForm, error) { + form := arm64SVEAddReductionForm{} + if spec.kind == arm64SVEFloatAddAccumulate { + if len(ins.Args) != 4 || ins.Args[1].Kind != OpReg || ins.Args[3].Kind != OpReg { + return form, fmt.Errorf("arm64 %s expects Zm.T, Vdn, Pg, Vdn: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64SVEFloatElementReg(ins.Args[0]) + initial, initialOK := arm64ParseVReg(ins.Args[1].Reg) + predicate, predicateOK := arm64ParseSVEPredicate(ins.Args[2]) + destination, destinationOK := arm64ParseVReg(ins.Args[3].Reg) + if !sourceOK || !initialOK || !predicateOK || predicate > 7 || !destinationOK || initial != destination || strings.Contains(string(ins.Args[1].Reg), ".") || strings.Contains(string(ins.Args[3].Reg), ".") { + return form, fmt.Errorf("arm64 %s requires an H/S/D source, bare P0..P7, and one destructive bare V register: %q", op, ins.Raw) + } + return arm64SVEAddReductionForm{elementBits: arm64SVEFloatReductionElementBits(spec.elementBits, sourceBits), source: source, predicate: predicate, destination: destination}, nil + } + if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { + return form, fmt.Errorf("arm64 %s expects Zn.T, Pg, Vd: %q", op, ins.Raw) + } + predicate, predicateOK := arm64ParseSVEPredicate(ins.Args[1]) + destination, destinationOK := arm64ParseVReg(ins.Args[2].Reg) + if !predicateOK || predicate > 7 || !destinationOK { + return form, fmt.Errorf("arm64 %s requires a bare P0..P7 and SIMD destination: %q", op, ins.Raw) + } + switch spec.kind { + case arm64SVEFloatAddReduce, arm64SVEFloatAddQuadReduce: + source, sourceBits, sourceOK := arm64SVEFloatElementReg(ins.Args[0]) + if !sourceOK { + return form, fmt.Errorf("arm64 %s source must use H, S, or D elements: %q", op, ins.Raw) + } + if spec.kind == arm64SVEFloatAddReduce { + if strings.Contains(string(ins.Args[2].Reg), ".") { + return form, fmt.Errorf("arm64 %s destination must be a bare V register: %q", op, ins.Raw) + } + sourceBits = arm64SVEFloatReductionElementBits(spec.elementBits, sourceBits) + } else { + arrangement, arrangementOK := parseARM64VectorArrangement(ins.Args[2].Reg) + if !arrangementOK || arrangement.elementBits != sourceBits || arrangement.lanes*arrangement.elementBits != 128 { + return form, fmt.Errorf("arm64 %s destination must be a full-width SIMD vector matching its source elements: %q", op, ins.Raw) + } + } + return arm64SVEAddReductionForm{elementBits: sourceBits, source: source, predicate: predicate, destination: destination}, nil + case arm64SVESignedAddReduce, arm64SVEUnsignedAddReduce: + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + if !sourceOK || (spec.kind == arm64SVESignedAddReduce && sourceBits == 64) || strings.Contains(string(ins.Args[2].Reg), ".") { + return form, fmt.Errorf("arm64 %s source/destination widths are outside its Go 1.27 form: %q", op, ins.Raw) + } + return arm64SVEAddReductionForm{elementBits: sourceBits, source: source, predicate: predicate, destination: destination}, nil + default: + return form, fmt.Errorf("arm64 %s has an unknown SVE add reduction form", op) + } +} + +func arm64SVEFloatReductionElementBits(opcodeBits, sourceBits int) int { + opcodeSize := map[int]int{16: 1, 32: 2, 64: 3}[opcodeBits] + sourceSize := map[int]int{16: 1, 32: 2, 64: 3}[sourceBits] + return 8 << (opcodeSize | sourceSize) +} + +func (c *arm64Ctx) lowerARM64SVEAddReductionForm(spec arm64SVEAddReductionSpec, form arm64SVEAddReductionForm, destination Reg) error { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + if spec.kind == arm64SVESignedAddReduce || spec.kind == arm64SVEUnsignedAddReduce { + source, vectorType, err := c.loadZRegElements(form.source, form.elementBits) + if err != nil { + return err + } + lanes := 128 / form.elementBits + intrinsic := map[arm64SVEAddReductionKind]string{arm64SVESignedAddReduce: "saddv", arm64SVEUnsignedAddReduce: "uaddv"}[spec.kind] + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, intrinsic, lanes, form.elementBits, predicateType, predicate, vectorType, source) + return c.storeARM64ScalarToVReg(destination, 64, "%"+result) + } + source, vectorType, err := c.loadRawSVEFloatVector(form.source, form.elementBits) + if err != nil { + return err + } + scalarType, _, lanes, err := arm64SVEFloatType(form.elementBits) + if err != nil { + return err + } + mangle := fmt.Sprintf("nxv%d%s", lanes, map[int]string{16: "f16", 32: "f32", 64: "f64"}[form.elementBits]) + result := c.newTmp() + switch spec.kind { + case arm64SVEFloatAddAccumulate: + initialBytes, err := c.loadVReg(destination) + if err != nil { + return err + } + initialVector := c.newTmp() + initial := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x %s>\n", initialVector, initialBytes, lanes, scalarType) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %%%s, i32 0\n", initial, lanes, scalarType, initialVector) + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fadda.%s(%s %s, %s %%%s, %s %s)\n", result, scalarType, mangle, predicateType, predicate, scalarType, initial, vectorType, source) + return c.storeARM64SVEFloatScalarToVReg(destination, form.elementBits, "%"+result) + case arm64SVEFloatAddReduce: + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.faddv.%s(%s %s, %s %s)\n", result, scalarType, mangle, predicateType, predicate, vectorType, source) + return c.storeARM64SVEFloatScalarToVReg(destination, form.elementBits, "%"+result) + case arm64SVEFloatAddQuadReduce: + fmt.Fprintf(c.b, " %%%s = call <%d x %s> @llvm.aarch64.sve.faddqv.v%d%s.%s(%s %s, %s %s)\n", result, lanes, scalarType, lanes, map[int]string{16: "f16", 32: "f32", 64: "f64"}[form.elementBits], mangle, predicateType, predicate, vectorType, source) + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x %s> %%%s to <16 x i8>\n", bytes, lanes, scalarType, result) + return c.storeVReg(destination, "%"+bytes) + default: + return fmt.Errorf("unknown ARM64 SVE add reduction kind %d", spec.kind) + } +} + +func (c *arm64Ctx) storeARM64SVEFloatScalarToVReg(destination Reg, elementBits int, value string) error { + scalarType, _, lanes, err := arm64SVEFloatType(elementBits) + if err != nil { + return err + } + fixed := c.newTmp() + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x %s> zeroinitializer, %s %s, i32 0\n", fixed, lanes, scalarType, scalarType, value) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x %s> %%%s to <16 x i8>\n", bytes, lanes, scalarType, fixed) + return c.storeVReg(destination, "%"+bytes) +} diff --git a/arm64_lower_sve_add_reduction_test.go b/arm64_lower_sve_add_reduction_test.go new file mode 100644 index 00000000..a2942faa --- /dev/null +++ b/arm64_lower_sve_add_reduction_test.go @@ -0,0 +1,97 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEAddReductionCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveaddreduceforms(SB),$0-0\n") + for _, opcodeWidth := range []string{"H", "S", "D"} { + for predicate, sourceWidth := range []string{"H", "S", "D"} { + // The generated FADDA/FADDV encoders use a generic H/S/D source. + // As with the integer reductions, Go ORs its size bits into the + // mnemonic's fixed bits, so every 3x3 combination is legal. + source.WriteString("\tZFADDA" + opcodeWidth + " Z1." + sourceWidth + ", V2, P" + string(rune('0'+predicate)) + ", V2\n") + source.WriteString("\tZFADDV" + opcodeWidth + " Z3." + sourceWidth + ", P" + string(rune('3'+predicate)) + ", V4\n") + } + } + for predicate, width := range []string{"H", "S", "D"} { + arrangement := map[string]string{"H": "H8", "S": "S4", "D": "D2"}[width] + source.WriteString("\tZFADDQV Z5." + width + ", P" + string(rune('0'+predicate)) + ", V6." + arrangement + "\n") + } + for predicate, width := range []string{"B", "H", "S"} { + source.WriteString("\tZSADDVD Z7." + width + ", P" + string(rune('4'+predicate)) + ", V8\n") + } + for predicate, width := range []string{"B", "H", "S", "D"} { + source.WriteString("\tZUADDVD Z9." + width + ", P" + string(rune('0'+predicate)) + ", V10\n") + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEAddReductionCompleteGo127Family(t *testing.T) { + source := arm64SVEAddReductionCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveaddreduceforms": {Name: "sveaddreduceforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2p1"`, + "@llvm.aarch64.sve.fadda.nxv8f16", + "@llvm.aarch64.sve.fadda.nxv4f32", + "@llvm.aarch64.sve.fadda.nxv2f64", + "@llvm.aarch64.sve.faddv.nxv8f16", + "@llvm.aarch64.sve.faddqv.v4f32.nxv4f32", + "@llvm.aarch64.sve.saddv.nxv16i8", + "@llvm.aarch64.sve.uaddv.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE add reduction lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-add-reduction.ll", "arm64-sve-add-reduction.o", ll) + }) + } +} + +func TestTranslateARM64SVEAddReductionRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFADDAH Z1.H, V2, P0, V3", + "ZFADDAS Z1.B, V2, P0, V2", + "ZFADDAD Z1.D, V2, P0.M, V2", + "ZFADDVH Z1.B, P0, V2", + "ZFADDVS Z1.S, P0.M, V2", + "ZFADDVD Z1.D, P0, V2.D2", + "ZFADDQV Z1.S, P0, V2.H8", + "ZFADDQV Z1.D, P0, V2", + "ZSADDVD Z1.D, P0, V2", + "ZSADDVD Z1.S, P0.M, V2", + "ZUADDVD Z1.Q, P0, V2", + "ZUADDVD.Z Z1.D, P0, V2", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveaddreduce(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveaddreduce": {Name: "badsveaddreduce", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE add reduction forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_add_sub.go b/arm64_lower_sve_add_sub.go new file mode 100644 index 00000000..7ccebe4a --- /dev/null +++ b/arm64_lower_sve_add_sub.go @@ -0,0 +1,102 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEAddSubSpec struct { + intrinsic string + reverse bool + unpredicated bool + predicated bool + immediate bool +} + +var arm64SVEAddSubSpecs = map[Op]arm64SVEAddSubSpec{ + "ZSUB": {unpredicated: true, predicated: true, immediate: true}, + "ZSUBR": {reverse: true, predicated: true, immediate: true}, + "ZSQADD": {intrinsic: "aarch64.sve.sqadd.x", unpredicated: true, predicated: true, immediate: true}, + "ZSQSUB": {intrinsic: "aarch64.sve.sqsub.x", unpredicated: true, predicated: true, immediate: true}, + "ZSQSUBR": {intrinsic: "aarch64.sve.sqsub.x", reverse: true, predicated: true}, + "ZUQADD": {intrinsic: "aarch64.sve.uqadd.x", unpredicated: true, predicated: true, immediate: true}, + "ZUQSUB": {intrinsic: "aarch64.sve.uqsub.x", unpredicated: true, predicated: true, immediate: true}, + "ZUQSUBR": {intrinsic: "aarch64.sve.uqsub.x", reverse: true, predicated: true}, +} + +func (c *arm64Ctx) lowerARM64SVEAddSub(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEAddSubSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + + form := arm64RawSVEAdd{} + switch { + case len(ins.Args) == 3 && ins.Args[0].Kind == OpImm: + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !spec.immediate || ins.Args[0].ImmRaw != "" || !firstOK || !destinationOK || first != destination || firstBits != destinationBits || !arm64SVEAddImmediateRepresentable(firstBits, ins.Args[0].Imm) { + return true, false, fmt.Errorf("arm64 %s does not accept this immediate form: %q", op, ins.Raw) + } + form = arm64RawSVEAdd{mode: arm64SVEAddImmediate, elementBits: firstBits, first: first, destination: destination, immediate: int(ins.Args[0].Imm)} + case len(ins.Args) == 3: + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !spec.unpredicated || !secondOK || !firstOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s does not accept this unpredicated vector form: %q", op, ins.Raw) + } + form = arm64RawSVEAdd{mode: arm64SVEAddUnpredicated, elementBits: firstBits, first: first, second: second, destination: destination} + case len(ins.Args) == 4: + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !spec.predicated || !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits || first != destination { + return true, false, fmt.Errorf("arm64 %s does not accept this predicated destructive form: %q", op, ins.Raw) + } + form = arm64RawSVEAdd{mode: arm64SVEAddPredicated, elementBits: firstBits, first: first, second: second, predicate: predicate, destination: destination} + default: + return true, false, fmt.Errorf("arm64 %s expects one of its Go 1.27 SVE forms: %q", op, ins.Raw) + } + return true, false, c.lowerRawSVEAddSub(spec, form) +} + +func (c *arm64Ctx) lowerRawSVEAddSub(spec arm64SVEAddSubSpec, form arm64RawSVEAdd) error { + first, vectorType, err := c.loadZRegElements(form.first, form.elementBits) + if err != nil { + return err + } + second := fmt.Sprintf("splat (i%d %d)", form.elementBits, form.immediate) + if form.mode != arm64SVEAddImmediate { + second, _, err = c.loadZRegElements(form.second, form.elementBits) + if err != nil { + return err + } + } + left, right := first, second + if spec.reverse { + left, right = right, left + } + calculated := c.newTmp() + if spec.intrinsic == "" { + fmt.Fprintf(c.b, " %%%s = sub %s %s, %s\n", calculated, vectorType, left, right) + } else { + lanes := 128 / form.elementBits + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.nxv%di%d(%s %s, %s %s)\n", calculated, vectorType, spec.intrinsic, lanes, form.elementBits, vectorType, left, vectorType, right) + } + result := "%" + calculated + if form.mode == arm64SVEAddPredicated { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", selected, predicateType, predicate, vectorType, result, vectorType, first) + result = "%" + selected + } + return c.storeZRegElements(form.destination, form.elementBits, result) +} diff --git a/arm64_lower_sve_add_sub_test.go b/arm64_lower_sve_add_sub_test.go new file mode 100644 index 00000000..815afe20 --- /dev/null +++ b/arm64_lower_sve_add_sub_test.go @@ -0,0 +1,123 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +type arm64SVEAddSubFormSpec struct { + op string + unpredicated bool + predicated bool + immediate bool +} + +var arm64SVEAddSubCompleteFamily = []arm64SVEAddSubFormSpec{ + {op: "ZSUB", unpredicated: true, predicated: true, immediate: true}, + {op: "ZSUBR", predicated: true, immediate: true}, + {op: "ZSQADD", unpredicated: true, predicated: true, immediate: true}, + {op: "ZSQSUB", unpredicated: true, predicated: true, immediate: true}, + {op: "ZSQSUBR", predicated: true}, + {op: "ZUQADD", unpredicated: true, predicated: true, immediate: true}, + {op: "ZUQSUB", unpredicated: true, predicated: true, immediate: true}, + {op: "ZUQSUBR", predicated: true}, +} + +func arm64SVEAddSubForms(function string, specs []arm64SVEAddSubFormSpec) string { + var source strings.Builder + source.WriteString("TEXT " + function + "(SB),$0-0\n") + for _, spec := range specs { + for widthIndex, width := range []string{"B", "H", "S", "D"} { + if spec.unpredicated { + source.WriteString("\t" + spec.op + " Z1." + width + ", Z2." + width + ", Z3." + width + "\n") + } + if spec.predicated { + source.WriteString("\t" + spec.op + " Z4." + width + ", Z5." + width + ", P" + string(rune('0'+widthIndex)) + ".M, Z5." + width + "\n") + } + if spec.immediate { + immediate := "255" + if width != "B" { + immediate = "65280" + } + source.WriteString("\t" + spec.op + " $" + immediate + ", Z6." + width + ", Z6." + width + "\n") + } + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEAddSubCompleteGo127Family(t *testing.T) { + for _, spec := range arm64SVEAddSubCompleteFamily { + spec := spec + t.Run(spec.op, func(t *testing.T) { + function := "sve" + strings.ToLower(spec.op) + source := arm64SVEAddSubForms(function, []arm64SVEAddSubFormSpec{spec}) + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + wants := []string{} + if spec.op == "ZSUB" || spec.op == "ZSUBR" { + wants = append(wants, " sub >5) & 63 + if immediate&32 != 0 { + immediate -= 64 + } + form.immediate = immediate + form.source = int(word>>16) & 31 + form.destination = int(word) & 31 + if form.op == "RDVL" && form.destination == 31 { + return arm64RawSVEAddress{}, false + } + return form, true +} + +func arm64SVEAddressReg(operand Operand, allowSP bool) (Reg, bool) { + if operand.Kind != OpReg { + return "", false + } + s := strings.ToUpper(string(operand.Reg)) + if operand.Reg == SP || s == "RSP" { + return SP, allowSP + } + if !strings.HasPrefix(s, "R") { + return "", false + } + index, err := strconv.Atoi(s[1:]) + if err != nil || index < 0 || index > 30 { + return "", false + } + return Reg(fmt.Sprintf("R%d", index)), true +} + +func (c *arm64Ctx) lowerARM64SVEAddress(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ADDVL" && op != "ADDPL" && op != "RDVL" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) < 2 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || ins.Args[0].Imm < -32 || ins.Args[0].Imm > 31 { + return true, false, fmt.Errorf("arm64 %s expects a signed 6-bit immediate and no suffix: %q", op, ins.Raw) + } + immediate := ins.Args[0].Imm + var source, destination Reg + if op == "RDVL" { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 RDVL expects $imm, Rdst: %q", ins.Raw) + } + var valid bool + destination, valid = arm64SVEAddressReg(ins.Args[1], false) + if !valid { + return true, false, fmt.Errorf("arm64 RDVL destination must be R0..R30: %q", ins.Raw) + } + } else { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects $imm, Rsrc|RSP, Rdst|RSP: %q", op, ins.Raw) + } + var sourceValid, destinationValid bool + source, sourceValid = arm64SVEAddressReg(ins.Args[1], true) + destination, destinationValid = arm64SVEAddressReg(ins.Args[2], true) + if !sourceValid || !destinationValid { + return true, false, fmt.Errorf("arm64 %s source and destination must be R0..R30 or RSP: %q", op, ins.Raw) + } + } + + vscale := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.vscale.i64()\n", vscale) + bytesPerVScale := int64(16) + if op == "ADDPL" { + bytesPerVScale = 2 + } + scaled := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %d\n", scaled, vscale, immediate*bytesPerVScale) + value := "%" + scaled + if op != "RDVL" { + base, err := c.loadReg(source) + if err != nil { + return true, false, err + } + added := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", added, base, value) + value = "%" + added + } + return true, false, c.storeReg(destination, value) +} + +func (c *arm64Ctx) lowerRawSVEAddress(form arm64RawSVEAddress) error { + reg := func(index int, spAllowed bool) Operand { + if index == 31 && spAllowed { + return Operand{Kind: OpReg, Reg: SP} + } + return Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("R%d", index))} + } + args := []Operand{{Kind: OpImm, Imm: int64(form.immediate)}} + if form.op == "RDVL" { + args = append(args, reg(form.destination, false)) + } else { + args = append(args, reg(form.source, true), reg(form.destination, true)) + } + ins := Instr{Op: form.op, Raw: fmt.Sprintf("decoded ARM64 WORD as %s", form.op), Args: args} + ok, _, err := c.lowerARM64SVEAddress(form.op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", form.op) + } + return err +} diff --git a/arm64_lower_sve_address_generation.go b/arm64_lower_sve_address_generation.go new file mode 100644 index 00000000..7dfe9f28 --- /dev/null +++ b/arm64_lower_sve_address_generation.go @@ -0,0 +1,67 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEAddressGeneration(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZADR" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || ins.Args[0].Kind != OpMem { + return true, false, fmt.Errorf("arm64 ZADR expects one complete Go 1.27 memory-vector form without a suffix: %q", ins.Raw) + } + memory := ins.Args[0].Mem + if memory.Sym != "" || memory.Off != 0 || memory.OffRaw != "" || memory.Base == "" || memory.Index == "" { + return true, false, fmt.Errorf("arm64 ZADR requires scalable-vector base and index registers: %q", ins.Raw) + } + shift, shiftOK := map[int64]int{1: 0, 2: 1, 4: 2, 8: 3}[memory.Scale] + if !shiftOK { + return true, false, fmt.Errorf("arm64 ZADR shift amount must be 0..3: %q", ins.Raw) + } + base, baseBits, baseOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Base}) + index, indexBits, indexOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[1]) + if !baseOK || !indexOK || !destinationOK { + return true, false, fmt.Errorf("arm64 ZADR operands must be scalable-vector element registers: %q", ins.Raw) + } + extended := memory.IndexExt == ExtendSXTW || memory.IndexExt == ExtendUXTW + if memory.IndexExt != "" && !extended { + return true, false, fmt.Errorf("arm64 ZADR only accepts UXTW or SXTW index extension: %q", ins.Raw) + } + if extended { + if baseBits != 64 || indexBits != 64 || destinationBits != 64 { + return true, false, fmt.Errorf("arm64 ZADR extended form requires D elements: %q", ins.Raw) + } + } else if (baseBits != 32 && baseBits != 64) || baseBits != indexBits || indexBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZADR unextended operands must use one S/D width: %q", ins.Raw) + } + baseValue, vectorType, err := c.loadZRegElements(base, baseBits) + if err != nil { + return true, false, err + } + indexValue, _, err := c.loadZRegElements(index, indexBits) + if err != nil { + return true, false, err + } + if extended { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s to \n", truncated, indexValue) + extendedValue := c.newTmp() + extension := "zext" + if memory.IndexExt == ExtendSXTW { + extension = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s %%%s to \n", extendedValue, extension, truncated) + indexValue = "%" + extendedValue + } + if shift != 0 { + scaled := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl %s %s, splat (i%d %d)\n", scaled, vectorType, indexValue, baseBits, shift) + indexValue = "%" + scaled + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", result, vectorType, baseValue, indexValue) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_address_generation_test.go b/arm64_lower_sve_address_generation_test.go new file mode 100644 index 00000000..8a17a2f8 --- /dev/null +++ b/arm64_lower_sve_address_generation_test.go @@ -0,0 +1,79 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEAddressGenerationCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT sveaddressgenerationforms(SB),$0-0\n") + for _, width := range []string{"S", "D"} { + for amount := 0; amount <= 3; amount++ { + fmt.Fprintf(&source, "\tZADR (Z1.%s<<%d)(Z2.%s), Z3.%s\n", width, amount, width, width) + } + } + for _, extension := range []string{"SXTW", "UXTW"} { + for amount := 0; amount <= 3; amount++ { + fmt.Fprintf(&source, "\tZADR (Z4.D.%s<<%d)(Z5.D), Z6.D\n", extension, amount) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveaddressgenerationforms": {Name: "sveaddressgenerationforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + " shl ", + " shl ", + " sext ", + " zext ", + " add = 0 && register <= 31 && lane >= 0 && lane <= 3 +} + +func arm64ParseSVEAESRoundGroup(operand Operand) ([]int, bool) { + if operand.Kind != OpRegList || !operand.RegListRange || len(operand.RegList) != 2 && len(operand.RegList) != 4 { + return nil, false + } + registers := make([]int, len(operand.RegList)) + for i, register := range operand.RegList { + index, bits, ok := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: register}) + if !ok || bits != 8 || i > 0 && index != registers[0]+i { + return nil, false + } + registers[i] = index + } + return registers, registers[0]%len(registers) == 0 +} + +func (c *arm64Ctx) lowerARM64SVEAESRound(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEAESRoundIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects one of the Go 1.27 single- or multi-vector AES forms without a suffix: %q", op, ins.Raw) + } + if source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]); sourceOK { + firstDestination, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + secondDestination, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[2]) + if op != "ZAESD" && op != "ZAESE" || sourceBits != 8 || !firstOK || !secondOK || firstBits != 8 || secondBits != 8 || firstDestination != secondDestination { + return true, false, fmt.Errorf("arm64 %s single-vector form requires Zm.B, Zdn.B, Zdn.B: %q", op, ins.Raw) + } + oldDestination, vectorType, err := c.loadZRegElements(firstDestination, 8) + if err != nil { + return true, false, err + } + sourceValue, _, err := c.loadZRegElements(source, 8) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s(%s %s, %s %s)\n", result, vectorType, intrinsic, vectorType, oldDestination, vectorType, sourceValue) + return true, false, c.storeZRegElements(firstDestination, 8, "%"+result) + } + key, lane, keyOK := arm64ParseSVEAESRoundKey(ins.Args[0]) + firstGroup, firstGroupOK := arm64ParseSVEAESRoundGroup(ins.Args[1]) + secondGroup, secondGroupOK := arm64ParseSVEAESRoundGroup(ins.Args[2]) + if !keyOK || !firstGroupOK || !secondGroupOK || len(firstGroup) != len(secondGroup) { + return true, false, fmt.Errorf("arm64 %s multi-vector form requires a Q[0..3] key and matching aligned B ranges of two or four registers: %q", op, ins.Raw) + } + for i := range firstGroup { + if firstGroup[i] != secondGroup[i] { + return true, false, fmt.Errorf("arm64 %s multi-vector source/destination ranges must match: %q", op, ins.Raw) + } + } + values := make([]string, len(firstGroup)) + vectorType := "" + for i, register := range firstGroup { + values[i], vectorType, err = c.loadZRegElements(register, 8) + if err != nil { + return true, false, err + } + } + keyValue, _, err := c.loadZRegElements(key, 8) + if err != nil { + return true, false, err + } + types := make([]string, len(values)) + arguments := make([]string, 0, len(values)+2) + for i, value := range values { + types[i] = vectorType + arguments = append(arguments, vectorType+" "+value) + } + arguments = append(arguments, vectorType+" "+keyValue, fmt.Sprintf("i32 %d", lane)) + aggregateType := "{ " + strings.Join(types, ", ") + " }" + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.lane.x%d(%s)\n", result, aggregateType, intrinsic, len(values), strings.Join(arguments, ", ")) + for i, register := range firstGroup { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, %d\n", value, aggregateType, result, i) + if err := c.storeZRegElements(register, 8, "%"+value); err != nil { + return true, false, err + } + } + return true, false, nil +} diff --git a/arm64_lower_sve_aes_round_test.go b/arm64_lower_sve_aes_round_test.go new file mode 100644 index 00000000..f464ea3b --- /dev/null +++ b/arm64_lower_sve_aes_round_test.go @@ -0,0 +1,91 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEAESRoundCompleteGo127Family(t *testing.T) { + const source = ` +TEXT sveaessingle(SB),$0-0 + ZAESD Z1.B, Z2.B, Z2.B + ZAESE Z3.B, Z4.B, Z4.B + RET +TEXT sveaesmulti(SB),$0-0 + ZAESD Z5.Q[0], [Z6.B-Z7.B], [Z6.B-Z7.B] + ZAESD Z31.Q[3], [Z28.B-Z31.B], [Z28.B-Z31.B] + ZAESDIMC Z8.Q[1], [Z10.B-Z11.B], [Z10.B-Z11.B] + ZAESDIMC Z9.Q[2], [Z24.B-Z27.B], [Z24.B-Z27.B] + ZAESE Z10.Q[3], [Z12.B-Z13.B], [Z12.B-Z13.B] + ZAESE Z11.Q[0], [Z20.B-Z23.B], [Z20.B-Z23.B] + ZAESEMC Z12.Q[2], [Z14.B-Z15.B], [Z14.B-Z15.B] + ZAESEMC Z13.Q[1], [Z16.B-Z19.B], [Z16.B-Z19.B] + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + sigs := map[string]FuncSig{ + "sveaessingle": {Name: "sveaessingle", Ret: Void}, + "sveaesmulti": {Name: "sveaesmulti", Ret: Void}, + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve2-aes"`, + `"target-features"="+sve,+sve-aes2"`, + "@llvm.aarch64.sve.aesd(", + "@llvm.aarch64.sve.aese(", + "@llvm.aarch64.sve.aesd.lane.x2", + "@llvm.aarch64.sve.aesd.lane.x4", + "@llvm.aarch64.sve.aesdimc.lane.x2", + "@llvm.aarch64.sve.aesdimc.lane.x4", + "@llvm.aarch64.sve.aese.lane.x2", + "@llvm.aarch64.sve.aese.lane.x4", + "@llvm.aarch64.sve.aesemc.lane.x2", + "@llvm.aarch64.sve.aesemc.lane.x4", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE AES round lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-aes-round.ll", "arm64-sve-aes-round.o", ll) + }) + } +} + +func TestTranslateARM64SVEAESRoundRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZAESD Z1.B, Z2.B, Z3.B", + "ZAESE Z1.H, Z2.H, Z2.H", + "ZAESDIMC Z1.B, Z2.B, Z2.B", + "ZAESD Z1.Q[4], [Z2.B-Z3.B], [Z2.B-Z3.B]", + "ZAESE Z1.Q[0], [Z1.B-Z2.B], [Z1.B-Z2.B]", + "ZAESDIMC Z1.Q[0], [Z4.B-Z6.B], [Z4.B-Z6.B]", + "ZAESEMC Z1.Q[0], [Z4.B-Z5.B], [Z6.B-Z7.B]", + "ZAESD Z1.Q[0], [Z4.B, Z5.B], [Z4.B, Z5.B]", + "ZAESE.Z Z1.B, Z2.B, Z2.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_", "[", "", "]", "").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveaesround(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveaesround": {Name: "badsveaesround", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE AES round forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_bfdot.go b/arm64_lower_sve_bfdot.go new file mode 100644 index 00000000..8c4dff42 --- /dev/null +++ b/arm64_lower_sve_bfdot.go @@ -0,0 +1,77 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEBFDOTForm struct { + first int + second int + destination int + lane int + indexed bool +} + +func (c *arm64Ctx) lowerARM64SVEBFDOT(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZBFDOT" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 ZBFDOT expects one complete Go 1.27 form without a suffix: %q", ins.Raw) + } + form := arm64SVEBFDOTForm{} + if first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[0]); firstOK { + if firstBits != 16 { + return true, false, fmt.Errorf("arm64 ZBFDOT vector source must use H elements: %q", ins.Raw) + } + form.first = first + } else { + first, firstBits, lane, firstOK := arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[0]) + if !firstOK || firstBits != 16 || first > 7 || lane > 3 { + return true, false, fmt.Errorf("arm64 ZBFDOT indexed source must use Z0..Z7.H[0..3]: %q", ins.Raw) + } + form.first = first + form.lane = lane + form.indexed = true + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || secondBits != 16 || !destinationOK || destinationBits != 32 { + return true, false, fmt.Errorf("arm64 ZBFDOT operands must use H source elements and an S accumulator: %q", ins.Raw) + } + form.second = second + form.destination = destination + return true, false, c.lowerARM64SVEBFDOTForm(form) +} + +func (c *arm64Ctx) lowerARM64SVEBFDOTForm(form arm64SVEBFDOTForm) error { + accumulator, accumulatorType, err := c.loadRawSVEFloatVector(form.destination, 32) + if err != nil { + return err + } + loadBFloat := func(register int) (string, error) { + integer, integerType, err := c.loadZRegElements(register, 16) + if err != nil { + return "", err + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to \n", converted, integerType, integer) + return "%" + converted, nil + } + second, err := loadBFloat(form.second) + if err != nil { + return err + } + first, err := loadBFloat(form.first) + if err != nil { + return err + } + result := c.newTmp() + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.bfdot.lane.v2( %s, %s, %s, i32 %d)\n", result, accumulator, second, first, form.lane) + } else { + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.bfdot( %s, %s, %s)\n", result, accumulator, second, first) + } + return c.storeRawSVEFloatVector(form.destination, 32, "%"+result, accumulatorType) +} diff --git a/arm64_lower_sve_bfdot_test.go b/arm64_lower_sve_bfdot_test.go new file mode 100644 index 00000000..9039315f --- /dev/null +++ b/arm64_lower_sve_bfdot_test.go @@ -0,0 +1,65 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEBFDOTCompleteGo127Family(t *testing.T) { + source := "TEXT svebfdotforms(SB),$0-0\n" + + "\tZBFDOT Z1.H, Z2.H, Z3.S\n" + + "\tZBFDOT Z0.H[0], Z2.H, Z3.S\n" + + "\tZBFDOT Z7.H[3], Z2.H, Z3.S\n" + + "\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svebfdotforms": {Name: "svebfdotforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+bf16,+sve\"", + "@llvm.aarch64.sve.bfdot(", + "@llvm.aarch64.sve.bfdot.lane.v2(", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE BFDOT lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-bfdot.ll", "arm64-sve-bfdot.o", ll) + }) + } +} + +func TestTranslateARM64SVEBFDOTRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZBFDOT Z1.B, Z2.B, Z3.S", + "ZBFDOT Z1.H, Z2.H, Z3.H", + "ZBFDOT Z1.H[0], Z2.S, Z3.S", + "ZBFDOT Z8.H[0], Z2.H, Z3.S", + "ZBFDOT Z7.H[4], Z2.H, Z3.S", + "ZBFDOT Z1.H, Z2.H", + "ZBFDOT.Z Z1.H, Z2.H, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvebfdot(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvebfdot": {Name: "badsvebfdot", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE BFDOT forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_bfloat_arithmetic.go b/arm64_lower_sve_bfloat_arithmetic.go new file mode 100644 index 00000000..da4521d1 --- /dev/null +++ b/arm64_lower_sve_bfloat_arithmetic.go @@ -0,0 +1,116 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEBFloatArithmeticSpec struct { + intrinsic string + unpredicated bool + indexed bool + scale bool +} + +var arm64SVEBFloatArithmeticSpecs = map[Op]arm64SVEBFloatArithmeticSpec{ + "ZBFADD": {intrinsic: "fadd", unpredicated: true}, + "ZBFSUB": {intrinsic: "fsub", unpredicated: true}, + "ZBFMUL": {intrinsic: "fmul", unpredicated: true, indexed: true}, + "ZBFMAX": {intrinsic: "fmax"}, + "ZBFMAXNM": {intrinsic: "fmaxnm"}, + "ZBFMIN": {intrinsic: "fmin"}, + "ZBFMINNM": {intrinsic: "fminnm"}, + "ZBFSCALE": {intrinsic: "fscale", scale: true}, +} + +func (c *arm64Ctx) lowerARM64SVEBFloatArithmetic(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEBFloatArithmeticSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if len(ins.Args) == 4 { + return c.lowerARM64SVEBFloatArithmeticPredicated(op, spec, ins) + } + if len(ins.Args) == 3 && spec.unpredicated { + return c.lowerARM64SVEBFloatArithmeticUnpredicated(op, spec, ins) + } + return true, false, fmt.Errorf("arm64 %s operands are outside its complete Go 1.27 BF16 arithmetic forms: %q", op, ins.Raw) +} + +func (c *arm64Ctx) lowerARM64SVEBFloatArithmeticPredicated(op Op, spec arm64SVEBFloatArithmeticSpec, ins Instr) (bool, bool, error) { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != 16 || firstBits != 16 || destinationBits != 16 || destination != first { + return true, false, fmt.Errorf("arm64 %s requires destructive H operands and P0..P7/M: %q", op, ins.Raw) + } + firstValue, err := c.loadARM64SVEBFloatVector(first) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, 16) + if err != nil { + return true, false, err + } + result := c.newTmp() + if spec.scale { + secondValue, secondType, err := c.loadZRegElements(second, 16) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.fscale.nxv8bf16(%s %s, %s, %s %s)\n", result, predicateType, predicateValue, firstValue, secondType, secondValue) + } else { + secondValue, err := c.loadARM64SVEBFloatVector(second) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.%s.nxv8bf16(%s %s, %s, %s)\n", result, spec.intrinsic, predicateType, predicateValue, firstValue, secondValue) + } + return true, false, c.storeARM64SVEBFloatVector(destination, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEBFloatArithmeticUnpredicated(op Op, spec arm64SVEBFloatArithmeticSpec, ins Instr) (bool, bool, error) { + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !firstOK || !destinationOK || firstBits != 16 || destinationBits != 16 { + return true, false, fmt.Errorf("arm64 %s requires H vector operands: %q", op, ins.Raw) + } + firstValue, err := c.loadARM64SVEBFloatVector(first) + if err != nil { + return true, false, err + } + result := c.newTmp() + if second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]); secondOK { + if secondBits != 16 { + return true, false, fmt.Errorf("arm64 %s requires H vector operands: %q", op, ins.Raw) + } + secondValue, err := c.loadARM64SVEBFloatVector(second) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " %%%s = %s %s, %s\n", result, spec.intrinsic, firstValue, secondValue) + } else { + second, secondBits, lane, secondOK := arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[0]) + if !spec.indexed || !secondOK || secondBits != 16 || second > 7 || lane > 7 { + return true, false, fmt.Errorf("arm64 %s indexed source must use Z0..Z7.H[0..7]: %q", op, ins.Raw) + } + secondValue, err := c.loadARM64SVEBFloatVector(second) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %s, %s, i32 %d)\n", result, firstValue, secondValue, lane) + } + return true, false, c.storeARM64SVEBFloatVector(destination, "%"+result) +} + +func emitARM64SVEBFloatArithmeticDeclarations(b *strings.Builder) { + for _, intrinsic := range []string{"fadd", "fsub", "fmul", "fmax", "fmaxnm", "fmin", "fminnm"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv8bf16(, , )\n", intrinsic) + } + b.WriteString("declare @llvm.aarch64.sve.fmul.lane.nxv8bf16(, , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.fscale.nxv8bf16(, , )\n") +} diff --git a/arm64_lower_sve_bfloat_arithmetic_test.go b/arm64_lower_sve_bfloat_arithmetic_test.go new file mode 100644 index 00000000..5b12b5ac --- /dev/null +++ b/arm64_lower_sve_bfloat_arithmetic_test.go @@ -0,0 +1,124 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEBFloatArithmeticCompleteGo127Family(t *testing.T) { + const source = `TEXT svebfloatarithmetic(SB),$0-0 + ZBFADD Z0.H, Z1.H, P0.M, Z1.H + ZBFADD Z2.H, Z3.H, Z4.H + ZBFSUB Z5.H, Z6.H, P7.M, Z6.H + ZBFSUB Z7.H, Z8.H, Z9.H + ZBFMUL Z10.H, Z11.H, P1.M, Z11.H + ZBFMUL Z12.H, Z13.H, Z14.H + ZBFMUL Z0.H[0], Z15.H, Z16.H + ZBFMUL Z7.H[7], Z17.H, Z18.H + ZBFMAX Z19.H, Z20.H, P2.M, Z20.H + ZBFMAXNM Z21.H, Z22.H, P3.M, Z22.H + ZBFMIN Z23.H, Z24.H, P4.M, Z24.H + ZBFMINNM Z25.H, Z26.H, P5.M, Z26.H + ZBFSCALE Z27.H, Z28.H, P6.M, Z28.H + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svebfloatarithmetic": {Name: "svebfloatarithmetic", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve-b16b16,+sve-bfscale"`, + "= fadd ", + "= fsub ", + "= fmul ", + "= call @llvm.aarch64.sve.fadd.nxv8bf16", + "= call @llvm.aarch64.sve.fsub.nxv8bf16", + "= call @llvm.aarch64.sve.fmul.nxv8bf16", + "= call @llvm.aarch64.sve.fmul.lane.nxv8bf16", + "= call @llvm.aarch64.sve.fmax.nxv8bf16", + "= call @llvm.aarch64.sve.fmaxnm.nxv8bf16", + "= call @llvm.aarch64.sve.fmin.nxv8bf16", + "= call @llvm.aarch64.sve.fminnm.nxv8bf16", + "= call @llvm.aarch64.sve.fscale.nxv8bf16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s BF16 arithmetic lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-bfloat-arithmetic.ll", "arm64-sve-bfloat-arithmetic.o", ll) + }) + } +} + +func TestTranslateARM64SVEBFloatArithmeticInfersIndependentFeatures(t *testing.T) { + classes := []struct { + name, instruction, features string + }{ + {name: "b16b16", instruction: "ZBFADD Z0.H, Z1.H, Z2.H", features: "+sve,+sve-b16b16"}, + {name: "bfscale", instruction: "ZBFSCALE Z0.H, Z1.H, P0.M, Z1.H", features: "+sve,+sve-bfscale"}, + } + for _, class := range classes { + t.Run(class.name, func(t *testing.T) { + source := "TEXT onebfloatfeature(SB),$0-0\n\t" + class.instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"onebfloatfeature": {Name: "onebfloatfeature", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + want := `"target-features"="` + class.features + `"` + if !strings.Contains(ll, want) { + t.Fatalf("%s feature inference omitted %q for %s:\n%s", triple, want, class.instruction, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-bfloat-feature.ll", "arm64-sve-bfloat-feature.o", ll) + }) + } + }) + } +} + +func TestTranslateARM64SVEBFloatArithmeticRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZBFADD Z0.S, Z1.S, Z2.S", + "ZBFADD Z0.H, Z1.H, P8.M, Z1.H", + "ZBFSUB Z0.H, Z1.H, P0.M, Z2.H", + "ZBFMUL Z0.H, Z1.H, P0.Z, Z1.H", + "ZBFMUL Z8.H[0], Z1.H, Z2.H", + "ZBFMUL Z7.H[8], Z1.H, Z2.H", + "ZBFMAX Z0.H, Z1.H, Z2.H", + "ZBFSCALE Z0.H, Z1.H, Z2.H", + "ZBFMINNM.Z Z0.H, Z1.H, P0.M, Z1.H", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvebfloatarithmetic(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvebfloatarithmetic": {Name: "badsvebfloatarithmetic", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's BF16 arithmetic forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_bfloat_mla.go b/arm64_lower_sve_bfloat_mla.go new file mode 100644 index 00000000..35725e44 --- /dev/null +++ b/arm64_lower_sve_bfloat_mla.go @@ -0,0 +1,130 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEBFloatMLASpec struct { + intrinsic string + laneIntrinsic string + widening bool + subtractLong bool +} + +var arm64SVEBFloatMLASpecs = map[Op]arm64SVEBFloatMLASpec{ + "ZBFMLA": {intrinsic: "fmla", laneIntrinsic: "fmla.lane"}, + "ZBFMLS": {intrinsic: "fmls", laneIntrinsic: "fmls.lane"}, + "ZBFMLALB": {intrinsic: "bfmlalb", laneIntrinsic: "bfmlalb.lane.v2", widening: true}, + "ZBFMLALT": {intrinsic: "bfmlalt", laneIntrinsic: "bfmlalt.lane.v2", widening: true}, + "ZBFMLSLB": {intrinsic: "bfmlslb", laneIntrinsic: "bfmlslb.lane", widening: true, subtractLong: true}, + "ZBFMLSLT": {intrinsic: "bfmlslt", laneIntrinsic: "bfmlslt.lane", widening: true, subtractLong: true}, +} + +type arm64SVEBFloatMLAForm struct { + spec arm64SVEBFloatMLASpec + first, second, destination int + predicate, lane int + predicated, indexed, widening bool +} + +func (c *arm64Ctx) lowerARM64SVEBFloatMLA(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEBFloatMLASpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + form := arm64SVEBFloatMLAForm{spec: spec, widening: spec.widening} + if len(ins.Args) == 4 && !spec.widening { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != 16 || firstBits != 16 || destinationBits != 16 { + return true, false, fmt.Errorf("arm64 %s requires H sources, H accumulator, and P0..P7/M: %q", op, ins.Raw) + } + form.first, form.second, form.destination = first, second, destination + form.predicate, form.predicated = predicate, true + return true, false, c.lowerARM64SVEBFloatMLAForm(form) + } + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s operands are outside its complete Go 1.27 BF16 MLA forms: %q", op, ins.Raw) + } + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + wantDestinationBits := 16 + if spec.widening { + wantDestinationBits = 32 + } + if !firstOK || !destinationOK || firstBits != 16 || destinationBits != wantDestinationBits { + return true, false, fmt.Errorf("arm64 %s source/destination widths are outside its Go 1.27 forms: %q", op, ins.Raw) + } + form.first, form.destination = first, destination + if second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]); secondOK { + if !spec.widening || secondBits != 16 { + return true, false, fmt.Errorf("arm64 %s has no unpredicated non-indexed same-width form: %q", op, ins.Raw) + } + form.second = second + } else { + second, secondBits, lane, secondOK := arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[0]) + if !secondOK || secondBits != 16 || second > 7 || lane > 7 { + return true, false, fmt.Errorf("arm64 %s indexed source must use Z0..Z7.H[0..7]: %q", op, ins.Raw) + } + form.second, form.lane, form.indexed = second, lane, true + } + return true, false, c.lowerARM64SVEBFloatMLAForm(form) +} + +func (c *arm64Ctx) lowerARM64SVEBFloatMLAForm(form arm64SVEBFloatMLAForm) error { + firstValue, err := c.loadARM64SVEBFloatVector(form.first) + if err != nil { + return err + } + secondValue, err := c.loadARM64SVEBFloatVector(form.second) + if err != nil { + return err + } + result := c.newTmp() + if form.widening { + accumulator, accumulatorType, err := c.loadRawSVEFloatVector(form.destination, 32) + if err != nil { + return err + } + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s(%s %s, %s, %s, i32 %d)\n", result, accumulatorType, form.spec.laneIntrinsic, accumulatorType, accumulator, firstValue, secondValue, form.lane) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s(%s %s, %s, %s)\n", result, accumulatorType, form.spec.intrinsic, accumulatorType, accumulator, firstValue, secondValue) + } + return c.storeRawSVEFloatVector(form.destination, 32, "%"+result, accumulatorType) + } + accumulator, err := c.loadARM64SVEBFloatVector(form.destination) + if err != nil { + return err + } + if form.predicated { + predicate, predicateType, err := c.loadPRegElements(form.predicate, 16) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.%s.nxv8bf16(%s %s, %s, %s, %s)\n", result, form.spec.intrinsic, predicateType, predicate, accumulator, firstValue, secondValue) + } else { + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.%s.nxv8bf16( %s, %s, %s, i32 %d)\n", result, form.spec.laneIntrinsic, accumulator, firstValue, secondValue, form.lane) + } + return c.storeARM64SVEBFloatVector(form.destination, "%"+result) +} + +func emitARM64SVEBFloatMLADeclarations(b *strings.Builder) { + for _, intrinsic := range []string{"fmla", "fmls"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv8bf16(, , , )\n", intrinsic) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.lane.nxv8bf16(, , , i32 immarg)\n", intrinsic) + } + for _, spec := range []arm64SVEBFloatMLASpec{ + arm64SVEBFloatMLASpecs["ZBFMLALB"], arm64SVEBFloatMLASpecs["ZBFMLALT"], + arm64SVEBFloatMLASpecs["ZBFMLSLB"], arm64SVEBFloatMLASpecs["ZBFMLSLT"], + } { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s(, , )\n", spec.intrinsic) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s(, , , i32 immarg)\n", spec.laneIntrinsic) + } +} diff --git a/arm64_lower_sve_bfloat_mla_test.go b/arm64_lower_sve_bfloat_mla_test.go new file mode 100644 index 00000000..9b469669 --- /dev/null +++ b/arm64_lower_sve_bfloat_mla_test.go @@ -0,0 +1,125 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEBFloatMLACompleteGo127Family(t *testing.T) { + const source = `TEXT svebfloatmla(SB),$0-0 + ZBFMLA Z0.H, Z1.H, P0.M, Z2.H + ZBFMLA Z0.H[0], Z3.H, Z4.H + ZBFMLS Z5.H, Z6.H, P7.M, Z7.H + ZBFMLS Z7.H[7], Z8.H, Z9.H + ZBFMLALB Z10.H, Z11.H, Z12.S + ZBFMLALB Z0.H[0], Z13.H, Z14.S + ZBFMLALT Z15.H, Z16.H, Z17.S + ZBFMLALT Z7.H[7], Z18.H, Z19.S + ZBFMLSLB Z20.H, Z21.H, Z22.S + ZBFMLSLB Z0.H[0], Z23.H, Z24.S + ZBFMLSLT Z25.H, Z26.H, Z27.S + ZBFMLSLT Z7.H[7], Z28.H, Z29.S + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svebfloatmla": {Name: "svebfloatmla", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+bf16,+sve,+sve-b16b16,+sve2p1"`, + "= call @llvm.aarch64.sve.fmla.nxv8bf16", + "= call @llvm.aarch64.sve.fmla.lane.nxv8bf16", + "= call @llvm.aarch64.sve.fmls.nxv8bf16", + "= call @llvm.aarch64.sve.fmls.lane.nxv8bf16", + "= call @llvm.aarch64.sve.bfmlalb(", + "= call @llvm.aarch64.sve.bfmlalb.lane.v2(", + "= call @llvm.aarch64.sve.bfmlalt(", + "= call @llvm.aarch64.sve.bfmlalt.lane.v2(", + "= call @llvm.aarch64.sve.bfmlslb(", + "= call @llvm.aarch64.sve.bfmlslb.lane(", + "= call @llvm.aarch64.sve.bfmlslt(", + "= call @llvm.aarch64.sve.bfmlslt.lane(", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s BF16 MLA lowering omitted actual call %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-bfloat-mla.ll", "arm64-sve-bfloat-mla.o", ll) + }) + } +} + +func TestTranslateARM64SVEBFloatMLAInfersIndependentFeatures(t *testing.T) { + classes := []struct { + name, instruction, features string + }{ + {name: "non-widening", instruction: "ZBFMLA Z0.H, Z1.H, P0.M, Z2.H", features: "+sve,+sve-b16b16"}, + {name: "widening-add", instruction: "ZBFMLALB Z0.H, Z1.H, Z2.S", features: "+bf16,+sve"}, + {name: "widening-subtract", instruction: "ZBFMLSLB Z0.H, Z1.H, Z2.S", features: "+bf16,+sve,+sve2p1"}, + } + for _, class := range classes { + t.Run(class.name, func(t *testing.T) { + source := "TEXT onebfloatmlafeature(SB),$0-0\n\t" + class.instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"onebfloatmlafeature": {Name: "onebfloatmlafeature", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + want := `"target-features"="` + class.features + `"` + if !strings.Contains(ll, want) { + t.Fatalf("%s feature inference omitted %q for %s:\n%s", triple, want, class.instruction, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-bfloat-mla-feature.ll", "arm64-sve-bfloat-mla-feature.o", ll) + }) + } + }) + } +} + +func TestTranslateARM64SVEBFloatMLARejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZBFMLA Z0.S, Z1.S, P0.M, Z2.S", + "ZBFMLA Z0.H, Z1.H, P8.M, Z2.H", + "ZBFMLS Z0.H, Z1.H, P0.Z, Z2.H", + "ZBFMLA Z0.H, Z1.H, Z2.H", + "ZBFMLA Z8.H[0], Z1.H, Z2.H", + "ZBFMLS Z7.H[8], Z1.H, Z2.H", + "ZBFMLALB Z0.H, Z1.H, Z2.H", + "ZBFMLALT Z0.S, Z1.S, Z2.S", + "ZBFMLSLB Z0.H, Z1.H, P0.M, Z2.S", + "ZBFMLSLT.Z Z0.H, Z1.H, Z2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvebfloatmla(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvebfloatmla": {Name: "badsvebfloatmla", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's BF16 MLA forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_bit_permute.go b/arm64_lower_sve_bit_permute.go new file mode 100644 index 00000000..4bce26d0 --- /dev/null +++ b/arm64_lower_sve_bit_permute.go @@ -0,0 +1,40 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEBitPermuteIntrinsics = map[Op]string{ + "ZBDEP": "bdep.x", + "ZBEXT": "bext.x", + "ZBGRP": "bgrp.x", +} + +func (c *arm64Ctx) lowerARM64SVEBitPermute(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEBitPermuteIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zm.T, Zn.T, Zd.T without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || firstBits != secondBits || destinationBits != firstBits { + return true, false, fmt.Errorf("arm64 %s requires matching B/H/S/D operands: %q", op, ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, firstBits) + if err != nil { + return true, false, err + } + lanes := 128 / firstBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, vectorType, intrinsic, lanes, firstBits, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeZRegElements(destination, firstBits, "%"+result) +} diff --git a/arm64_lower_sve_bit_permute_test.go b/arm64_lower_sve_bit_permute_test.go new file mode 100644 index 00000000..5cc3978b --- /dev/null +++ b/arm64_lower_sve_bit_permute_test.go @@ -0,0 +1,73 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEBitPermuteCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svebitpermuteforms(SB),$0-0\n") + for _, op := range []string{"ZBDEP", "ZBEXT", "ZBGRP"} { + for _, width := range []string{"B", "H", "S", "D"} { + source.WriteString("\t" + op + " Z1." + width + ", Z2." + width + ", Z3." + width + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEBitPermuteCompleteGo127Family(t *testing.T) { + source := arm64SVEBitPermuteCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svebitpermuteforms": {Name: "svebitpermuteforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve-bitperm,+sve2"`, + "@llvm.aarch64.sve.bdep.x.nxv16i8", + "@llvm.aarch64.sve.bext.x.nxv8i16", + "@llvm.aarch64.sve.bgrp.x.nxv4i32", + "@llvm.aarch64.sve.bdep.x.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE bit-permute lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-bit-permute.ll", "arm64-sve-bit-permute.o", ll) + }) + } +} + +func TestTranslateARM64SVEBitPermuteRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZBDEP Z1.B, Z2.H, Z3.B", + "ZBEXT Z1.S, Z2.S, Z3.D", + "ZBGRP Z1.Q, Z2.Q, Z3.Q", + "ZBDEP Z1.D, Z2.D", + "ZBEXT.Z Z1.D, Z2.D, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvebitpermute(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvebitpermute": {Name: "badsvebitpermute", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE bit-permute forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_carry_long.go b/arm64_lower_sve_carry_long.go new file mode 100644 index 00000000..44401d83 --- /dev/null +++ b/arm64_lower_sve_carry_long.go @@ -0,0 +1,45 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVECarryLongIntrinsics = map[Op]string{ + "ZADCLB": "adclb", + "ZADCLT": "adclt", + "ZSBCLB": "sbclb", + "ZSBCLT": "sbclt", +} + +func (c *arm64Ctx) lowerARM64SVECarryLong(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVECarryLongIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zm.S|D, Zn.S|D, Zda.S|D without a suffix: %q", op, ins.Raw) + } + third, thirdBits, thirdOK := arm64ParseSVEZElementReg(ins.Args[0]) + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[1]) + accumulator, accumulatorBits, accumulatorOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !thirdOK || !secondOK || !accumulatorOK || (accumulatorBits != 32 && accumulatorBits != 64) || secondBits != accumulatorBits || thirdBits != accumulatorBits { + return true, false, fmt.Errorf("arm64 %s requires matching S/D operands: %q", op, ins.Raw) + } + accumulatorValue, vectorType, err := c.loadZRegElements(accumulator, accumulatorBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, accumulatorBits) + if err != nil { + return true, false, err + } + thirdValue, _, err := c.loadZRegElements(third, accumulatorBits) + if err != nil { + return true, false, err + } + lanes := 128 / accumulatorBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, intrinsic, lanes, accumulatorBits, vectorType, accumulatorValue, vectorType, secondValue, vectorType, thirdValue) + return true, false, c.storeZRegElements(accumulator, accumulatorBits, "%"+result) +} diff --git a/arm64_lower_sve_carry_long_test.go b/arm64_lower_sve_carry_long_test.go new file mode 100644 index 00000000..8c1fadc3 --- /dev/null +++ b/arm64_lower_sve_carry_long_test.go @@ -0,0 +1,73 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVECarryLongCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svecarrylongforms(SB),$0-0\n") + for _, op := range []string{"ZADCLB", "ZADCLT", "ZSBCLB", "ZSBCLT"} { + for _, width := range []string{"S", "D"} { + source.WriteString("\t" + op + " Z1." + width + ", Z2." + width + ", Z3." + width + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVECarryLongCompleteGo127Family(t *testing.T) { + source := arm64SVECarryLongCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svecarrylongforms": {Name: "svecarrylongforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.adclb.nxv4i32", + "@llvm.aarch64.sve.adclt.nxv2i64", + "@llvm.aarch64.sve.sbclb.nxv4i32", + "@llvm.aarch64.sve.sbclt.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE carry-long lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-carry-long.ll", "arm64-sve-carry-long.o", ll) + }) + } +} + +func TestTranslateARM64SVECarryLongRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZADCLB Z1.B, Z2.B, Z3.B", + "ZADCLT Z1.H, Z2.H, Z3.H", + "ZSBCLB Z1.S, Z2.D, Z3.S", + "ZSBCLT Z1.D, Z2.D", + "ZADCLB.Z Z1.D, Z2.D, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvecarrylong(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvecarrylong": {Name: "badsvecarrylong", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE carry-long forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_cdot.go b/arm64_lower_sve_cdot.go new file mode 100644 index 00000000..88ca8427 --- /dev/null +++ b/arm64_lower_sve_cdot.go @@ -0,0 +1,77 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVECDOTForm struct { + first, second, destination int + sourceBits, destinationBits int + rotation int + lane int + indexed bool +} + +func (c *arm64Ctx) lowerARM64SVECDOT(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZCDOT" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || ins.Args[0].ImmIsFloat { + return true, false, fmt.Errorf("arm64 ZCDOT expects $0|$90|$180|$270 and one complete Go 1.27 vector or indexed form: %q", ins.Raw) + } + rotation := int(ins.Args[0].Imm) + if rotation != 0 && rotation != 90 && rotation != 180 && rotation != 270 { + return true, false, fmt.Errorf("arm64 ZCDOT rotation must be $0, $90, $180, or $270: %q", ins.Raw) + } + form := arm64SVECDOTForm{rotation: rotation} + if first, sourceBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]); firstOK { + form.first, form.sourceBits = first, sourceBits + } else { + first, sourceBits, lane, firstOK := arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[1]) + if !firstOK { + return true, false, fmt.Errorf("arm64 ZCDOT requires a B/H vector or indexed source: %q", ins.Raw) + } + form.first, form.sourceBits, form.lane, form.indexed = first, sourceBits, lane, true + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + validWidths := (form.sourceBits == 8 && destinationBits == 32) || (form.sourceBits == 16 && destinationBits == 64) + if !secondOK || !destinationOK || secondBits != form.sourceBits || !validWidths { + return true, false, fmt.Errorf("arm64 ZCDOT requires B sources with an S accumulator or H sources with a D accumulator: %q", ins.Raw) + } + if form.indexed { + maxRegister, maxLane := 7, 3 + if form.sourceBits == 16 { + maxRegister, maxLane = 15, 1 + } + if form.first > maxRegister || form.lane > maxLane { + return true, false, fmt.Errorf("arm64 ZCDOT indexed source exceeds its register or lane range: %q", ins.Raw) + } + } + form.second, form.destination, form.destinationBits = second, destination, destinationBits + return true, false, c.lowerARM64SVECDOTForm(form) +} + +func (c *arm64Ctx) lowerARM64SVECDOTForm(form arm64SVECDOTForm) error { + accumulator, accumulatorType, err := c.loadZRegElements(form.destination, form.destinationBits) + if err != nil { + return err + } + first, sourceType, err := c.loadZRegElements(form.first, form.sourceBits) + if err != nil { + return err + } + second, _, err := c.loadZRegElements(form.second, form.sourceBits) + if err != nil { + return err + } + lanes := 128 / form.destinationBits + result := c.newTmp() + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.cdot.lane.nxv%di%d(%s %s, %s %s, %s %s, i32 %d, i32 %d)\n", result, accumulatorType, lanes, form.destinationBits, accumulatorType, accumulator, sourceType, second, sourceType, first, form.lane, form.rotation) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.cdot.nxv%di%d(%s %s, %s %s, %s %s, i32 %d)\n", result, accumulatorType, lanes, form.destinationBits, accumulatorType, accumulator, sourceType, second, sourceType, first, form.rotation) + } + return c.storeZRegElements(form.destination, form.destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_cdot_test.go b/arm64_lower_sve_cdot_test.go new file mode 100644 index 00000000..3f02a589 --- /dev/null +++ b/arm64_lower_sve_cdot_test.go @@ -0,0 +1,74 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVECDOTCompleteGo127Family(t *testing.T) { + const source = `TEXT svecdot(SB),$0-0 + ZCDOT $0, Z8.B, Z9.B, Z10.S + ZCDOT $90, Z11.H, Z12.H, Z13.D + ZCDOT $180, Z14.B, Z15.B, Z16.S + ZCDOT $270, Z17.H, Z18.H, Z19.D + ZCDOT $0, Z0.B[0], Z20.B, Z21.S + ZCDOT $270, Z7.B[3], Z22.B, Z23.S + ZCDOT $90, Z0.H[0], Z24.H, Z25.D + ZCDOT $180, Z15.H[1], Z26.H, Z27.D + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svecdot": {Name: "svecdot", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.cdot.nxv4i32", + "@llvm.aarch64.sve.cdot.nxv2i64", + "@llvm.aarch64.sve.cdot.lane.nxv4i32", + "@llvm.aarch64.sve.cdot.lane.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s ZCDOT lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-cdot.ll", "arm64-sve-cdot.o", ll) + }) + } +} + +func TestTranslateARM64SVECDOTRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZCDOT $1, Z1.B, Z2.B, Z3.S", + "ZCDOT $90, Z1.B, Z2.H, Z3.S", + "ZCDOT $90, Z1.H, Z2.H, Z3.S", + "ZCDOT $90, Z8.B[0], Z2.B, Z3.S", + "ZCDOT $90, Z7.B[4], Z2.B, Z3.S", + "ZCDOT $90, Z16.H[0], Z2.H, Z3.D", + "ZCDOT $90, Z15.H[2], Z2.H, Z3.D", + "ZCDOT.Z $270, Z1.H, Z2.H, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvecdot(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvecdot": {Name: "badsvecdot", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ZCDOT forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_character_match.go b/arm64_lower_sve_character_match.go new file mode 100644 index 00000000..ea19769b --- /dev/null +++ b/arm64_lower_sve_character_match.go @@ -0,0 +1,44 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVECharacterMatchIntrinsics = map[Op]string{ + "ZMATCH": "match", + "ZNMATCH": "nmatch", +} + +func (c *arm64Ctx) lowerARM64SVECharacterMatch(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVECharacterMatchIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects Zm.B|H, Zn.B|H, Pg/Z, Pd.B|H without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + governing, governingOK := arm64ParseSVEPredicateMode(ins.Args[2], "Z", 7) + destination, destinationBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[3]) + if !secondOK || !firstOK || !governingOK || !destinationOK || (firstBits != 8 && firstBits != 16) || secondBits != firstBits || destinationBits != firstBits { + return true, false, fmt.Errorf("arm64 %s requires matching B/H vectors and result predicate under P0..P7/Z: %q", op, ins.Raw) + } + governingValue, predicateType, err := c.loadPRegElements(governing, firstBits) + if err != nil { + return true, false, err + } + firstValue, vectorType, err := c.loadZRegElements(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, secondBits) + if err != nil { + return true, false, err + } + lanes := 128 / firstBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, predicateType, intrinsic, lanes, firstBits, predicateType, governingValue, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storePRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_character_match_test.go b/arm64_lower_sve_character_match_test.go new file mode 100644 index 00000000..d19c13c1 --- /dev/null +++ b/arm64_lower_sve_character_match_test.go @@ -0,0 +1,71 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVECharacterMatchCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svecharactermatch(SB),$0-0\n") + for opIndex, op := range []string{"ZMATCH", "ZNMATCH"} { + for widthIndex, width := range []string{"B", "H"} { + fmt.Fprintf(&source, "\t%s Z%d.%s, Z%d.%s, P%d.Z, P%d.%s\n", op, opIndex*2+widthIndex, width, opIndex*2+widthIndex+1, width, opIndex+widthIndex, opIndex*2+widthIndex+8, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svecharactermatch": {Name: "svecharactermatch", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.match.nxv16i8", + "@llvm.aarch64.sve.match.nxv8i16", + "@llvm.aarch64.sve.nmatch.nxv16i8", + "@llvm.aarch64.sve.nmatch.nxv8i16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE character-match lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-character-match.ll", "arm64-sve-character-match.o", ll) + }) + } +} + +func TestTranslateARM64SVECharacterMatchRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZMATCH Z1.S, Z2.S, P0.Z, P1.S", + "ZNMATCH Z1.D, Z2.D, P0.Z, P1.D", + "ZMATCH Z1.B, Z2.H, P0.Z, P1.B", + "ZNMATCH Z1.H, Z2.H, P8.Z, P1.H", + "ZMATCH Z1.B, Z2.B, P0.M, P1.B", + "ZNMATCH Z1.H, Z2.H, P0.Z, P1.B", + "ZMATCH.Z Z1.B, Z2.B, P0.Z, P1.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvecharactermatch(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvecharactermatch": {Name: "badsvecharactermatch", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's character-match forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_clamp.go b/arm64_lower_sve_clamp.go new file mode 100644 index 00000000..21463796 --- /dev/null +++ b/arm64_lower_sve_clamp.go @@ -0,0 +1,125 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEClampKind uint8 + +const ( + arm64SVEClampInteger arm64SVEClampKind = iota + arm64SVEClampFloat + arm64SVEClampBFloat +) + +type arm64SVEClampSpec struct { + intrinsic string + kind arm64SVEClampKind +} + +var arm64SVEClampSpecs = map[Op]arm64SVEClampSpec{ + "ZSCLAMP": {intrinsic: "sclamp", kind: arm64SVEClampInteger}, + "ZUCLAMP": {intrinsic: "uclamp", kind: arm64SVEClampInteger}, + "ZFCLAMP": {intrinsic: "fclamp", kind: arm64SVEClampFloat}, + "ZBFCLAMP": {intrinsic: "fclamp", kind: arm64SVEClampBFloat}, +} + +func (c *arm64Ctx) lowerARM64SVEClamp(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEClampSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zm.T, Zn.T, Zd.T without a suffix: %q", op, ins.Raw) + } + maximum, maximumBits, maximumOK := arm64ParseSVEZElementReg(ins.Args[0]) + minimum, minimumBits, minimumOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !maximumOK || !minimumOK || !destinationOK || maximumBits != destinationBits || minimumBits != destinationBits || !arm64SVEClampWidthOK(spec.kind, destinationBits) { + return true, false, fmt.Errorf("arm64 %s has invalid or mismatched element widths: %q", op, ins.Raw) + } + + switch spec.kind { + case arm64SVEClampInteger: + return true, false, c.lowerARM64SVEIntegerClamp(spec, destinationBits, destination, minimum, maximum) + case arm64SVEClampFloat: + return true, false, c.lowerARM64SVEFloatClamp(spec, destinationBits, destination, minimum, maximum) + case arm64SVEClampBFloat: + return true, false, c.lowerARM64SVEBFloatClamp(spec, destination, minimum, maximum) + default: + return true, false, fmt.Errorf("arm64 %s has an unknown clamp kind", op) + } +} + +func arm64SVEClampWidthOK(kind arm64SVEClampKind, bits int) bool { + switch kind { + case arm64SVEClampInteger: + return bits == 8 || bits == 16 || bits == 32 || bits == 64 + case arm64SVEClampFloat: + return bits == 16 || bits == 32 || bits == 64 + case arm64SVEClampBFloat: + return bits == 16 + default: + return false + } +} + +func (c *arm64Ctx) lowerARM64SVEIntegerClamp(spec arm64SVEClampSpec, bits, destination, minimum, maximum int) error { + value, vectorType, err := c.loadZRegElements(destination, bits) + if err != nil { + return err + } + minimumValue, _, err := c.loadZRegElements(minimum, bits) + if err != nil { + return err + } + maximumValue, _, err := c.loadZRegElements(maximum, bits) + if err != nil { + return err + } + lanes := 128 / bits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, spec.intrinsic, lanes, bits, vectorType, value, vectorType, minimumValue, vectorType, maximumValue) + return c.storeZRegElements(destination, bits, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEFloatClamp(spec arm64SVEClampSpec, bits, destination, minimum, maximum int) error { + value, vectorType, err := c.loadRawSVEFloatVector(destination, bits) + if err != nil { + return err + } + minimumValue, _, err := c.loadRawSVEFloatVector(minimum, bits) + if err != nil { + return err + } + maximumValue, _, err := c.loadRawSVEFloatVector(maximum, bits) + if err != nil { + return err + } + lanes := 128 / bits + suffix := map[int]string{16: "f16", 32: "f32", 64: "f64"}[bits] + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%d%s(%s %s, %s %s, %s %s)\n", result, vectorType, spec.intrinsic, lanes, suffix, vectorType, value, vectorType, minimumValue, vectorType, maximumValue) + return c.storeRawSVEFloatVector(destination, bits, "%"+result, vectorType) +} + +func (c *arm64Ctx) lowerARM64SVEBFloatClamp(spec arm64SVEClampSpec, destination, minimum, maximum int) error { + integerType := "" + vectorType := "" + values := make([]string, 3) + for i, reg := range []int{destination, minimum, maximum} { + integerValue, _, err := c.loadZRegElements(reg, 16) + if err != nil { + return err + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", converted, integerType, integerValue, vectorType) + values[i] = "%" + converted + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv8bf16(%s %s, %s %s, %s %s)\n", result, vectorType, spec.intrinsic, vectorType, values[0], vectorType, values[1], vectorType, values[2]) + integerResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to %s\n", integerResult, vectorType, result, integerType) + return c.storeZRegElements(destination, 16, "%"+integerResult) +} diff --git a/arm64_lower_sve_clamp_test.go b/arm64_lower_sve_clamp_test.go new file mode 100644 index 00000000..45880d9d --- /dev/null +++ b/arm64_lower_sve_clamp_test.go @@ -0,0 +1,80 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEClampCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveclampforms(SB),$0-0\n") + for _, op := range []string{"ZSCLAMP", "ZUCLAMP"} { + for _, width := range []string{"B", "H", "S", "D"} { + source.WriteString("\t" + op + " Z1." + width + ", Z2." + width + ", Z3." + width + "\n") + } + } + for _, width := range []string{"H", "S", "D"} { + source.WriteString("\tZFCLAMP Z1." + width + ", Z2." + width + ", Z3." + width + "\n") + } + source.WriteString("\tZBFCLAMP Z1.H, Z2.H, Z3.H\n") + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEClampCompleteGo127Family(t *testing.T) { + source := arm64SVEClampCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveclampforms": {Name: "sveclampforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve-b16b16,+sve2p1"`, + "@llvm.aarch64.sve.sclamp.nxv16i8", + "@llvm.aarch64.sve.uclamp.nxv2i64", + "@llvm.aarch64.sve.fclamp.nxv8f16", + "@llvm.aarch64.sve.fclamp.nxv4f32", + "@llvm.aarch64.sve.fclamp.nxv2f64", + "@llvm.aarch64.sve.fclamp.nxv8bf16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE clamp lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-clamp.ll", "arm64-sve-clamp.o", ll) + }) + } +} + +func TestTranslateARM64SVEClampRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSCLAMP Z1.B, Z2.H, Z3.B", + "ZUCLAMP Z1.Q, Z2.Q, Z3.Q", + "ZFCLAMP Z1.B, Z2.B, Z3.B", + "ZBFCLAMP Z1.S, Z2.S, Z3.S", + "ZFCLAMP Z1.S, Z2.S", + "ZSCLAMP.Z Z1.D, Z2.D, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveclamp(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveclamp": {Name: "badsveclamp", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE clamp forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_clast.go b/arm64_lower_sve_clast.go new file mode 100644 index 00000000..3e9ef7a7 --- /dev/null +++ b/arm64_lower_sve_clast.go @@ -0,0 +1,146 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVECLastDestination uint8 + +const ( + arm64SVECLastGeneric arm64SVECLastDestination = iota + arm64SVECLastGPR + arm64SVECLastVReg +) + +type arm64SVECLastSpec struct { + intrinsic string + baseSize int + destination arm64SVECLastDestination +} + +var arm64SVECLastSpecs = map[Op]arm64SVECLastSpec{ + "ZCLASTA": {intrinsic: "clasta", destination: arm64SVECLastGeneric}, + "ZCLASTAW": {intrinsic: "clasta", destination: arm64SVECLastGPR}, + "ZCLASTAB": {intrinsic: "clasta", destination: arm64SVECLastVReg}, + "ZCLASTAH": {intrinsic: "clasta", baseSize: 1, destination: arm64SVECLastVReg}, + "ZCLASTAS": {intrinsic: "clasta", baseSize: 2, destination: arm64SVECLastVReg}, + "ZCLASTAD": {intrinsic: "clasta", baseSize: 3, destination: arm64SVECLastVReg}, + "ZCLASTB": {intrinsic: "clastb", destination: arm64SVECLastGeneric}, + "ZCLASTBW": {intrinsic: "clastb", destination: arm64SVECLastGPR}, + "ZCLASTBB": {intrinsic: "clastb", destination: arm64SVECLastVReg}, + "ZCLASTBH": {intrinsic: "clastb", baseSize: 1, destination: arm64SVECLastVReg}, + "ZCLASTBS": {intrinsic: "clastb", baseSize: 2, destination: arm64SVECLastVReg}, + "ZCLASTBD": {intrinsic: "clastb", baseSize: 3, destination: arm64SVECLastVReg}, +} + +func (c *arm64Ctx) lowerARM64SVECLast(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVECLastSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects source, old destination, Pg, destination without a suffix: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + predicate, predicateOK := arm64ParseSVEPredicateBare(ins.Args[2], 7) + if !sourceOK || !predicateOK { + return true, false, fmt.Errorf("arm64 %s requires a Z source and P0..P7: %q", op, ins.Raw) + } + sourceSize := map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[sourceBits] + + destinationKind := spec.destination + oldVector, oldBits, oldVectorOK := arm64ParseSVEZElementReg(ins.Args[1]) + newVector, newBits, newVectorOK := arm64ParseSVEZElementReg(ins.Args[3]) + if destinationKind == arm64SVECLastGeneric && oldVectorOK && newVectorOK { + if oldVector != newVector { + return true, false, fmt.Errorf("arm64 %s vector destination must be destructive: %q", op, ins.Raw) + } + elementBits := 8 << (sourceSize | + map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[oldBits] | + map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[newBits]) + return true, false, c.lowerARM64SVECLastVector(spec.intrinsic, source, predicate, oldVector, elementBits) + } + if destinationKind == arm64SVECLastGeneric { + destinationKind = arm64SVECLastGPR + spec.baseSize = 3 + } + elementBits := 8 << (spec.baseSize | sourceSize) + if destinationKind == arm64SVECLastGPR { + if !arm64SVEIndexScalarRegister(ins.Args[1]) || !arm64SVEIndexScalarRegister(ins.Args[3]) || ins.Args[1].Reg != ins.Args[3].Reg { + return true, false, fmt.Errorf("arm64 %s GP destination must be the same R0..R30 or ZR operand twice: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVECLastScalar(spec.intrinsic, source, predicate, ins.Args[1].Reg, elementBits, false) + } + oldDestination, oldOK := arm64SVEInsertVRegister(ins.Args[1]) + newDestination, newOK := arm64SVEInsertVRegister(ins.Args[3]) + if !oldOK || !newOK || oldDestination != newDestination { + return true, false, fmt.Errorf("arm64 %s SIMD destination must be the same V0..V31 operand twice: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVECLastScalar(spec.intrinsic, source, predicate, oldDestination, elementBits, true) +} + +func (c *arm64Ctx) lowerARM64SVECLastVector(intrinsic string, source, predicate, destination, elementBits int) error { + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return err + } + oldValue, vectorType, err := c.loadZRegElements(destination, elementBits) + if err != nil { + return err + } + sourceValue, _, err := c.loadZRegElements(source, elementBits) + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", + result, vectorType, intrinsic, lanes, elementBits, predicateType, predicateValue, vectorType, oldValue, vectorType, sourceValue) + return c.storeZRegElements(destination, elementBits, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVECLastScalar(intrinsic string, source, predicate int, destination Reg, elementBits int, vectorDestination bool) error { + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return err + } + sourceValue, vectorType, err := c.loadZRegElements(source, elementBits) + if err != nil { + return err + } + var oldValue string + if vectorDestination { + oldValue, err = c.arm64SVEInsertVectorScalar(destination, elementBits) + } else { + oldValue, err = c.loadReg(destination) + if err == nil && elementBits != 64 && oldValue != "0" { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", truncated, oldValue, elementBits) + oldValue = "%" + truncated + } + } + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i%d @llvm.aarch64.sve.%s.n.nxv%di%d(%s %s, i%d %s, %s %s)\n", + result, elementBits, intrinsic, lanes, elementBits, predicateType, predicateValue, elementBits, oldValue, vectorType, sourceValue) + if vectorDestination { + return c.storeARM64ScalarToVReg(destination, elementBits, "%"+result) + } + value := "%" + result + if elementBits != 64 { + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i%d %s to i64\n", extended, elementBits, value) + value = "%" + extended + } + return c.storeReg(destination, value) +} diff --git a/arm64_lower_sve_clast_test.go b/arm64_lower_sve_clast_test.go new file mode 100644 index 00000000..9fc5a5f5 --- /dev/null +++ b/arm64_lower_sve_clast_test.go @@ -0,0 +1,86 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVECLastCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveclastforms(SB),$0-0\n") + for _, selector := range []string{"A", "B"} { + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\tZCLAST%s Z1.%s, Z2.%s, P0, Z2.%s\n", selector, width, width, width) + fmt.Fprintf(&source, "\tZCLAST%s Z3.%s, R4, P1, R4\n", selector, width) + fmt.Fprintf(&source, "\tZCLAST%sW Z5.%s, R6, P2, R6\n", selector, width) + fmt.Fprintf(&source, "\tZCLAST%sB Z7.%s, V8, P3, V8\n", selector, width) + fmt.Fprintf(&source, "\tZCLAST%sH Z9.%s, V10, P4, V10\n", selector, width) + fmt.Fprintf(&source, "\tZCLAST%sS Z11.%s, V12, P5, V12\n", selector, width) + fmt.Fprintf(&source, "\tZCLAST%sD Z13.%s, V14, P7, V14\n", selector, width) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVECLastCompleteGo127Family(t *testing.T) { + source := arm64SVECLastCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveclastforms": {Name: "sveclastforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.clasta.nxv16i8", + "@llvm.aarch64.sve.clasta.n.nxv8i16", + "@llvm.aarch64.sve.clastb.nxv4i32", + "@llvm.aarch64.sve.clastb.n.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE CLAST lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-clast.ll", "arm64-sve-clast.o", ll) + }) + } +} + +func TestTranslateARM64SVECLastRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZCLASTA Z0.D, Z1.D, P0, Z2.D", + "ZCLASTB Z0.D, R1, P0, R2", + "ZCLASTAW Z0.S, V1, P0, V1", + "ZCLASTBW Z0.S, RSP, P0, RSP", + "ZCLASTAB Z0.B, R1, P0, R1", + "ZCLASTBH Z0.H, V1, P8, V1", + "ZCLASTAS Z0.S, V1, P0.M, V1", + "ZCLASTBD Z0.Q, V1, P0, V1", + "ZCLASTA.Z Z0.D, R1, P0, R1", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveclast(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveclast": {Name: "badsveclast", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE CLAST forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_compact.go b/arm64_lower_sve_compact.go new file mode 100644 index 00000000..f3fe346f --- /dev/null +++ b/arm64_lower_sve_compact.go @@ -0,0 +1,45 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func arm64SVECompactNeedsSVE2P2(ins Instr) bool { + if len(ins.Args) != 3 { + return false + } + _, bits, ok := arm64ParseSVEZElementReg(ins.Args[0]) + return ok && bits <= 16 +} + +func (c *arm64Ctx) lowerARM64SVECompact(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZCOMPACT" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 ZCOMPACT expects Zn.T, Pg, Zd.T without a suffix: %q", ins.Raw) + } + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + predicate, predicateOK := arm64ParseSVEPredicateBare(ins.Args[1], 7) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !sourceOK || !predicateOK || !destinationOK || sourceBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZCOMPACT requires matching B/H/S/D vectors and P0..P7: %q", ins.Raw) + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, sourceBits) + if err != nil { + return true, false, err + } + sourceValue, vectorType, err := c.loadZRegElements(source, sourceBits) + if err != nil { + return true, false, err + } + _, lanes, err := arm64SVEVectorType(sourceBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.compact.nxv%di%d(%s %s, %s %s)\n", + result, vectorType, lanes, sourceBits, predicateType, predicateValue, vectorType, sourceValue) + return true, false, c.storeZRegElements(destination, sourceBits, "%"+result) +} diff --git a/arm64_lower_sve_compact_test.go b/arm64_lower_sve_compact_test.go new file mode 100644 index 00000000..3bf396e9 --- /dev/null +++ b/arm64_lower_sve_compact_test.go @@ -0,0 +1,69 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVECompactCompleteGo127Family(t *testing.T) { + source := "TEXT svecompactforms(SB),$0-0\n" + + "\tZCOMPACT Z0.B, P0, Z4.B\n" + + "\tZCOMPACT Z1.H, P1, Z5.H\n" + + "\tZCOMPACT Z2.S, P2, Z6.S\n" + + "\tZCOMPACT Z3.D, P7, Z7.D\n" + + "\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svecompactforms": {Name: "svecompactforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve,+sve2p2\"", + "@llvm.aarch64.sve.compact.nxv16i8", + "@llvm.aarch64.sve.compact.nxv8i16", + "@llvm.aarch64.sve.compact.nxv4i32", + "@llvm.aarch64.sve.compact.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE COMPACT lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-compact.ll", "arm64-sve-compact.o", ll) + }) + } +} + +func TestTranslateARM64SVECompactRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZCOMPACT Z0.B, P0, Z1.H", + "ZCOMPACT Z0.H, P0, Z1.B", + "ZCOMPACT Z0.S, P8, Z1.S", + "ZCOMPACT Z0.D, P0.M, Z1.D", + "ZCOMPACT Z0.Q, P0, Z1.Q", + "ZCOMPACT.Z Z0.D, P0, Z1.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvecompact(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvecompact": {Name: "badsvecompact", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE COMPACT forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_compare.go b/arm64_lower_sve_compare.go new file mode 100644 index 00000000..e92d4772 --- /dev/null +++ b/arm64_lower_sve_compare.go @@ -0,0 +1,227 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVECompareSpec struct { + predicate string + floating bool + absolute bool + allowReg bool + allowImm bool + unsignedImm bool +} + +var arm64SVECompareSpecs = map[Op]arm64SVECompareSpec{ + "ZCMPEQ": {predicate: "eq", allowReg: true, allowImm: true}, + "ZCMPGE": {predicate: "sge", allowReg: true, allowImm: true}, + "ZCMPGT": {predicate: "sgt", allowReg: true, allowImm: true}, + "ZCMPHI": {predicate: "ugt", allowReg: true, allowImm: true, unsignedImm: true}, + "ZCMPHS": {predicate: "uge", allowReg: true, allowImm: true, unsignedImm: true}, + "ZCMPNE": {predicate: "ne", allowReg: true, allowImm: true}, + "ZFACGE": {predicate: "oge", floating: true, absolute: true, allowReg: true}, + "ZFACGT": {predicate: "ogt", floating: true, absolute: true, allowReg: true}, + "ZFCMEQ": {predicate: "oeq", floating: true, allowReg: true, allowImm: true}, + "ZFCMGE": {predicate: "oge", floating: true, allowReg: true, allowImm: true}, + "ZFCMGT": {predicate: "ogt", floating: true, allowReg: true, allowImm: true}, + "ZFCMLE": {predicate: "ole", floating: true, allowImm: true}, + "ZFCMLT": {predicate: "olt", floating: true, allowImm: true}, + "ZFCMNE": {predicate: "une", floating: true, allowReg: true, allowImm: true}, + "ZFCMUO": {predicate: "uno", floating: true, allowReg: true}, +} + +func arm64ParseSVEPredicateMode(operand Operand, mode string, maximum int) (int, bool) { + if operand.Kind != OpReg { + return 0, false + } + parts := strings.Split(strings.ToUpper(strings.TrimSpace(string(operand.Reg))), ".") + if len(parts) != 2 || parts[1] != mode || !strings.HasPrefix(parts[0], "P") { + return 0, false + } + var index int + if _, err := fmt.Sscanf(parts[0], "P%d", &index); err != nil || index < 0 || index > maximum { + return 0, false + } + return index, true +} + +func arm64ParseSVEPredicateBare(operand Operand, maximum int) (int, bool) { + if operand.Kind != OpReg { + return 0, false + } + text := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + if strings.Contains(text, ".") || !strings.HasPrefix(text, "P") { + return 0, false + } + var index int + if _, err := fmt.Sscanf(text, "P%d", &index); err != nil || index < 0 || index > maximum { + return 0, false + } + return index, true +} + +func arm64ParseSVEPredicateElement(operand Operand) (index, elementBits int, ok bool) { + if operand.Kind != OpReg { + return 0, 0, false + } + parts := strings.Split(strings.ToUpper(strings.TrimSpace(string(operand.Reg))), ".") + if len(parts) != 2 || !strings.HasPrefix(parts[0], "P") { + return 0, 0, false + } + if _, err := fmt.Sscanf(parts[0], "P%d", &index); err != nil || index < 0 || index > 15 { + return 0, 0, false + } + elementBits, ok = map[string]int{"B": 8, "H": 16, "S": 32, "D": 64}[parts[1]] + return index, elementBits, ok +} + +type arm64SVECompareForm struct { + op Op + elementBits int + first int + second int + predicate int + destination int + immediate int64 + hasImmediate bool + wide bool +} + +func (c *arm64Ctx) lowerARM64SVECompare(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVECompareSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects one of its four-operand Go 1.27 SVE compare forms: %q", op, ins.Raw) + } + parseElement := arm64ParseSVEZElementReg + if spec.floating { + parseElement = arm64SVEFloatElementReg + } + first, firstBits, firstOK := parseElement(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "Z", 7) + destination, destinationBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[3]) + if !firstOK || !predicateOK || !destinationOK || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s compare data, governing predicate, and result widths do not match: %q", op, ins.Raw) + } + form := arm64SVECompareForm{op: op, elementBits: firstBits, first: first, predicate: predicate, destination: destination} + if ins.Args[0].Kind == OpImm { + if !spec.allowImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 %s does not accept this immediate compare form: %q", op, ins.Raw) + } + if spec.floating { + if !ins.Args[0].ImmIsFloat || uint64(ins.Args[0].Imm) != 0 { + return true, false, fmt.Errorf("arm64 %s floating immediate must be $(0.0): %q", op, ins.Raw) + } + } else if ins.Args[0].ImmIsFloat || (!spec.unsignedImm && (ins.Args[0].Imm < -16 || ins.Args[0].Imm > 15)) || (spec.unsignedImm && (ins.Args[0].Imm < 0 || ins.Args[0].Imm > 127)) { + return true, false, fmt.Errorf("arm64 %s integer immediate is outside its Go 1.27 range: %q", op, ins.Raw) + } + form.hasImmediate = true + form.immediate = ins.Args[0].Imm + } else { + if !spec.allowReg { + return true, false, fmt.Errorf("arm64 %s does not accept a vector compare source: %q", op, ins.Raw) + } + second, secondBits, secondOK := parseElement(ins.Args[0]) + if !secondOK { + return true, false, fmt.Errorf("arm64 %s compare source is not a valid scalable vector: %q", op, ins.Raw) + } + if secondBits == firstBits { + form.second = second + } else if !spec.floating && secondBits == 64 && firstBits < 64 { + form.second = second + form.wide = true + } else { + return true, false, fmt.Errorf("arm64 %s compare vector widths do not match a regular or wide form: %q", op, ins.Raw) + } + } + return true, false, c.lowerARM64SVECompareForm(spec, form) +} + +func (c *arm64Ctx) lowerARM64SVECompareForm(spec arm64SVECompareSpec, form arm64SVECompareForm) error { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + if form.wide { + first, vectorType, err := c.loadZRegElements(form.first, form.elementBits) + if err != nil { + return err + } + second, wideType, err := c.loadZRegElements(form.second, 64) + if err != nil { + return err + } + intrinsic := strings.ToLower(strings.TrimPrefix(string(form.op), "Z")) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.wide.nxv%di%d(%s %s, %s %s, %s %s)\n", result, predicateType, intrinsic, 128/form.elementBits, form.elementBits, predicateType, predicate, vectorType, first, wideType, second) + return c.storePRegElements(form.destination, form.elementBits, "%"+result) + } + + var first, second, vectorType string + if spec.floating { + first, vectorType, err = c.loadRawSVEFloatVector(form.first, form.elementBits) + if err != nil { + return err + } + if form.hasImmediate { + second = "zeroinitializer" + } else { + second, _, err = c.loadRawSVEFloatVector(form.second, form.elementBits) + if err != nil { + return err + } + } + if spec.absolute { + first, err = c.arm64SVEFloatAbsolute(first, form.elementBits) + if err != nil { + return err + } + second, err = c.arm64SVEFloatAbsolute(second, form.elementBits) + if err != nil { + return err + } + } + } else { + first, vectorType, err = c.loadZRegElements(form.first, form.elementBits) + if err != nil { + return err + } + if form.hasImmediate { + second = fmt.Sprintf("splat (i%d %d)", form.elementBits, form.immediate) + } else { + second, _, err = c.loadZRegElements(form.second, form.elementBits) + if err != nil { + return err + } + } + } + compared := c.newTmp() + operation := "icmp" + if spec.floating { + operation = "fcmp" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s %s, %s\n", compared, operation, spec.predicate, vectorType, first, second) + active := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %s\n", active, predicateType, compared, predicate) + return c.storePRegElements(form.destination, form.elementBits, "%"+active) +} + +func (c *arm64Ctx) arm64SVEFloatAbsolute(value string, elementBits int) (string, error) { + integerType, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return "", err + } + floatingType := fmt.Sprintf("", lanes, map[int]string{16: "half", 32: "float", 64: "double"}[elementBits]) + bits := c.newTmp() + cleared := c.newTmp() + result := c.newTmp() + mask := uint64(1)<<(elementBits-1) - 1 + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", bits, floatingType, value, integerType) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, splat (i%d %d)\n", cleared, integerType, bits, elementBits, mask) + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to %s\n", result, integerType, cleared, floatingType) + return "%" + result, nil +} diff --git a/arm64_lower_sve_compare_test.go b/arm64_lower_sve_compare_test.go new file mode 100644 index 00000000..a03367e3 --- /dev/null +++ b/arm64_lower_sve_compare_test.go @@ -0,0 +1,96 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVECompareCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svecompareforms(SB),$0-0\n") + for _, op := range []string{"ZCMPEQ", "ZCMPGE", "ZCMPGT", "ZCMPHI", "ZCMPHS", "ZCMPNE"} { + for index, width := range []string{"B", "H", "S", "D"} { + predicate := string(rune('0' + index)) + source.WriteString("\t" + op + " Z1." + width + ", Z2." + width + ", P" + predicate + ".Z, P12." + width + "\n") + } + for index, width := range []string{"B", "H", "S"} { + predicate := string(rune('4' + index)) + source.WriteString("\t" + op + " Z3.D, Z4." + width + ", P" + predicate + ".Z, P13." + width + "\n") + } + for index, width := range []string{"B", "H", "S", "D"} { + predicate := string(rune('0' + index)) + immediate := "-16" + if op == "ZCMPHI" || op == "ZCMPHS" { + immediate = "127" + } + source.WriteString("\t" + op + " $" + immediate + ", Z5." + width + ", P" + predicate + ".Z, P14." + width + "\n") + } + } + for _, op := range []string{"ZFACGE", "ZFACGT", "ZFCMEQ", "ZFCMGE", "ZFCMGT", "ZFCMNE", "ZFCMUO"} { + for index, width := range []string{"H", "S", "D"} { + predicate := string(rune('0' + index)) + source.WriteString("\t" + op + " Z6." + width + ", Z7." + width + ", P" + predicate + ".Z, P15." + width + "\n") + } + } + for _, op := range []string{"ZFCMEQ", "ZFCMGE", "ZFCMGT", "ZFCMLE", "ZFCMLT", "ZFCMNE"} { + for index, width := range []string{"H", "S", "D"} { + predicate := string(rune('4' + index)) + source.WriteString("\t" + op + " $(0.0), Z8." + width + ", P" + predicate + ".Z, P11." + width + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVECompareCompleteGo127Family(t *testing.T) { + source := arm64SVECompareCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svecompareforms": {Name: "svecompareforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve"`, " icmp ", " fcmp ", "@llvm.aarch64.sve.cmpeq.wide.nxv", "@llvm.aarch64.sve.convert.to.svbool"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE compare lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-compare.ll", "arm64-sve-compare.o", ll) + }) + } +} + +func TestTranslateARM64SVECompareRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZCMPEQ Z1.B, Z2.H, P0.Z, P1.H", + "ZCMPGE $16, Z2.S, P0.Z, P1.S", + "ZCMPHI $-1, Z2.S, P0.Z, P1.S", + "ZCMPNE Z1.S, Z2.S, P8.Z, P1.S", + "ZFCMEQ Z1.B, Z2.B, P0.Z, P1.B", + "ZFCMGT $(1.0), Z2.D, P0.Z, P1.D", + "ZFACGE Z1.S, Z2.S, P0.M, P1.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvecompare(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvecompare": {Name: "badsvecompare", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE compare forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_complex_add.go b/arm64_lower_sve_complex_add.go new file mode 100644 index 00000000..a6266952 --- /dev/null +++ b/arm64_lower_sve_complex_add.go @@ -0,0 +1,40 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEComplexAddIntrinsics = map[Op]string{ + "ZCADD": "cadd.x", + "ZSQCADD": "sqcadd.x", +} + +func (c *arm64Ctx) lowerARM64SVEComplexAdd(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEComplexAddIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 %s expects $90|$270, Zm.T, Zdn.T, Zdn.T without a suffix: %q", op, ins.Raw) + } + rotation := ins.Args[0].Imm + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + repeatedDestination, repeatedBits, repeatedOK := arm64ParseSVEZElementReg(ins.Args[3]) + if (rotation != 90 && rotation != 270) || !secondOK || !destinationOK || !repeatedOK || secondBits != destinationBits || repeatedBits != destinationBits || repeatedDestination != destination { + return true, false, fmt.Errorf("arm64 %s requires rotation $90/$270 and matching destructive B/H/S/D operands: %q", op, ins.Raw) + } + destinationValue, vectorType, err := c.loadZRegElements(destination, destinationBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, secondBits) + if err != nil { + return true, false, err + } + lanes := 128 / destinationBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, i32 %d)\n", result, vectorType, intrinsic, lanes, destinationBits, vectorType, destinationValue, vectorType, secondValue, rotation) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_complex_add_test.go b/arm64_lower_sve_complex_add_test.go new file mode 100644 index 00000000..51793303 --- /dev/null +++ b/arm64_lower_sve_complex_add_test.go @@ -0,0 +1,73 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEComplexAddCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svecomplexadd(SB),$0-0\n") + for opIndex, op := range []string{"ZCADD", "ZSQCADD"} { + for widthIndex, width := range []string{"B", "H", "S", "D"} { + for rotationIndex, rotation := range []int{90, 270} { + destination := opIndex*8 + widthIndex*2 + rotationIndex + fmt.Fprintf(&source, "\t%s $%d, Z%d.%s, Z%d.%s, Z%d.%s\n", op, rotation, (destination+1)%32, width, destination, width, destination, width) + } + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svecomplexadd": {Name: "svecomplexadd", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.cadd.x.nxv16i8", + "@llvm.aarch64.sve.cadd.x.nxv2i64", + "@llvm.aarch64.sve.sqcadd.x.nxv8i16", + "@llvm.aarch64.sve.sqcadd.x.nxv4i32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE complex-add lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-complex-add.ll", "arm64-sve-complex-add.o", ll) + }) + } +} + +func TestTranslateARM64SVEComplexAddRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZCADD $0, Z1.B, Z2.B, Z2.B", + "ZCADD $180, Z1.H, Z2.H, Z2.H", + "ZSQCADD $91, Z1.S, Z2.S, Z2.S", + "ZSQCADD $270, Z1.D, Z2.S, Z2.S", + "ZCADD $90, Z1.S, Z2.S, Z3.S", + "ZSQCADD.Z $270, Z1.D, Z2.D, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvecomplexadd(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvecomplexadd": {Name: "badsvecomplexadd", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's complex-add forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_complex_multiply_accumulate.go b/arm64_lower_sve_complex_multiply_accumulate.go new file mode 100644 index 00000000..05b91d7a --- /dev/null +++ b/arm64_lower_sve_complex_multiply_accumulate.go @@ -0,0 +1,95 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEComplexMultiplyAccumulateIntrinsics = map[Op]string{ + "ZCMLA": "cmla", + "ZSQRDCMLAH": "sqrdcmlah", +} + +type arm64SVEComplexMultiplyAccumulateForm struct { + intrinsic string + elementBits int + multiplier int + multiplicand int + lane int + rotation int + destination int + indexed bool +} + +func (c *arm64Ctx) lowerARM64SVEComplexMultiplyAccumulate(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEComplexMultiplyAccumulateIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 form without a suffix: %q", op, ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || ins.Args[0].ImmIsFloat { + return true, false, fmt.Errorf("arm64 %s rotation must be 0, 90, 180, or 270: %q", op, ins.Raw) + } + rotation := int(ins.Args[0].Imm) + if rotation != 0 && rotation != 90 && rotation != 180 && rotation != 270 { + return true, false, fmt.Errorf("arm64 %s rotation must be 0, 90, 180, or 270: %q", op, ins.Raw) + } + form := arm64SVEComplexMultiplyAccumulateForm{intrinsic: intrinsic, rotation: rotation} + if multiplier, multiplierBits, lane, indexed := arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[1]); indexed { + multiplicand, multiplicandBits, multiplicandOK := arm64ParseSVEZElementReg(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + maximumVector, vectorOK := map[int]int{16: 7, 32: 15}[multiplierBits] + maximumLane, laneOK := map[int]int{16: 3, 32: 1}[multiplierBits] + if !multiplicandOK || !destinationOK || !vectorOK || !laneOK || multiplier > maximumVector || lane > maximumLane || multiplierBits != multiplicandBits || multiplicandBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s indexed operands must use an encodable H/S complex lane: %q", op, ins.Raw) + } + form.elementBits = multiplierBits + form.multiplier = multiplier + form.multiplicand = multiplicand + form.lane = lane + form.destination = destination + form.indexed = true + } else { + multiplier, multiplierBits, multiplierOK := arm64ParseSVEZElementReg(ins.Args[1]) + multiplicand, multiplicandBits, multiplicandOK := arm64ParseSVEZElementReg(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !multiplierOK || !multiplicandOK || !destinationOK || multiplierBits != multiplicandBits || multiplicandBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s vector operands must use one B/H/S/D width: %q", op, ins.Raw) + } + form.elementBits = multiplierBits + form.multiplier = multiplier + form.multiplicand = multiplicand + form.destination = destination + } + return true, false, c.lowerARM64SVEComplexMultiplyAccumulateForm(form) +} + +func (c *arm64Ctx) lowerARM64SVEComplexMultiplyAccumulateForm(form arm64SVEComplexMultiplyAccumulateForm) error { + accumulator, vectorType, err := c.loadZRegElements(form.destination, form.elementBits) + if err != nil { + return err + } + multiplicand, _, err := c.loadZRegElements(form.multiplicand, form.elementBits) + if err != nil { + return err + } + multiplier, _, err := c.loadZRegElements(form.multiplier, form.elementBits) + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(form.elementBits) + if err != nil { + return err + } + result := c.newTmp() + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.lane.x.nxv%di%d(%s %s, %s %s, %s %s, i32 %d, i32 %d)\n", + result, vectorType, form.intrinsic, lanes, form.elementBits, vectorType, accumulator, vectorType, multiplicand, vectorType, multiplier, form.lane, form.rotation) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.x.nxv%di%d(%s %s, %s %s, %s %s, i32 %d)\n", + result, vectorType, form.intrinsic, lanes, form.elementBits, vectorType, accumulator, vectorType, multiplicand, vectorType, multiplier, form.rotation) + } + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) +} diff --git a/arm64_lower_sve_complex_multiply_accumulate_test.go b/arm64_lower_sve_complex_multiply_accumulate_test.go new file mode 100644 index 00000000..cb90ddec --- /dev/null +++ b/arm64_lower_sve_complex_multiply_accumulate_test.go @@ -0,0 +1,80 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEComplexMultiplyAccumulateCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svecomplexmultiplyaccumulateforms(SB),$0-0\n") + for _, op := range []string{"ZCMLA", "ZSQRDCMLAH"} { + for _, rotation := range []int{0, 90, 180, 270} { + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\t%s $%d, Z31.%s, Z2.%s, Z3.%s\n", op, rotation, width, width, width) + } + fmt.Fprintf(&source, "\t%s $%d, Z7.H[3], Z4.H, Z5.H\n", op, rotation) + fmt.Fprintf(&source, "\t%s $%d, Z15.S[1], Z6.S, Z7.S\n", op, rotation) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svecomplexmultiplyaccumulateforms": {Name: "svecomplexmultiplyaccumulateforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve,+sve2\"", + "@llvm.aarch64.sve.cmla.x.nxv16i8", + "@llvm.aarch64.sve.cmla.lane.x.nxv8i16", + "@llvm.aarch64.sve.sqrdcmlah.x.nxv2i64", + "@llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32", + "i32 0", + "i32 270", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE complex multiply-accumulate lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-complex-multiply-accumulate.ll", "arm64-sve-complex-multiply-accumulate.o", ll) + }) + } +} + +func TestTranslateARM64SVEComplexMultiplyAccumulateRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZCMLA $45, Z1.S, Z2.S, Z3.S", + "ZSQRDCMLAH $0, Z1.H, Z2.S, Z3.S", + "ZCMLA $0, Z8.H[0], Z2.H, Z3.H", + "ZSQRDCMLAH $0, Z7.H[4], Z2.H, Z3.H", + "ZCMLA $0, Z16.S[0], Z2.S, Z3.S", + "ZSQRDCMLAH $0, Z15.S[2], Z2.S, Z3.S", + "ZCMLA $0, Z1.D[0], Z2.D, Z3.D", + "ZSQRDCMLAH.Z $0, Z1.S, Z2.S, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvecomplexmultiplyaccumulate(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvecomplexmultiplyaccumulate": {Name: "badsvecomplexmultiplyaccumulate", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE complex multiply-accumulate forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_convert.go b/arm64_lower_sve_convert.go new file mode 100644 index 00000000..95a2ebee --- /dev/null +++ b/arm64_lower_sve_convert.go @@ -0,0 +1,187 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEConvertKind uint8 + +const ( + arm64SVEConvertFloat arm64SVEConvertKind = iota + arm64SVEConvertFloatToSigned + arm64SVEConvertFloatToUnsigned + arm64SVEConvertSignedToFloat + arm64SVEConvertUnsignedToFloat +) + +type arm64SVEConvertSpec struct { + kind arm64SVEConvertKind + intrinsic string + zeroIntrinsic string + zeroKeepsDestination bool + allowed map[[2]int]bool +} + +var ( + arm64SVEConvertDifferentFloatWidths = arm64SVEWidthPairs( + [2]int{16, 32}, [2]int{16, 64}, [2]int{32, 16}, [2]int{32, 64}, [2]int{64, 16}, [2]int{64, 32}, + ) + arm64SVEConvertFloatToIntWidths = arm64SVEWidthPairs( + [2]int{16, 16}, [2]int{16, 32}, [2]int{16, 64}, [2]int{32, 32}, [2]int{32, 64}, [2]int{64, 32}, [2]int{64, 64}, + ) + arm64SVEConvertIntToFloatWidths = arm64SVEWidthPairs( + [2]int{16, 16}, [2]int{32, 16}, [2]int{32, 32}, [2]int{32, 64}, [2]int{64, 16}, [2]int{64, 32}, [2]int{64, 64}, + ) + arm64SVEConvertSpecs = map[Op]arm64SVEConvertSpec{ + "ZFCVT": {kind: arm64SVEConvertFloat, allowed: arm64SVEConvertDifferentFloatWidths}, + "ZFCVTZS": {kind: arm64SVEConvertFloatToSigned, allowed: arm64SVEConvertFloatToIntWidths}, + "ZFCVTZU": {kind: arm64SVEConvertFloatToUnsigned, allowed: arm64SVEConvertFloatToIntWidths}, + "ZSCVTF": {kind: arm64SVEConvertSignedToFloat, allowed: arm64SVEConvertIntToFloatWidths}, + "ZUCVTF": {kind: arm64SVEConvertUnsignedToFloat, allowed: arm64SVEConvertIntToFloatWidths}, + "ZFCVTLT": {kind: arm64SVEConvertFloat, intrinsic: "fcvtlt", allowed: arm64SVEWidthPairs( + [2]int{16, 32}, [2]int{32, 64}, + )}, + "ZFCVTX": {kind: arm64SVEConvertFloat, intrinsic: "fcvtx", allowed: arm64SVEWidthPairs( + [2]int{64, 32}, + )}, + "ZFCVTXNT": {kind: arm64SVEConvertFloat, intrinsic: "fcvtxnt", zeroIntrinsic: "fcvtxnt.z", zeroKeepsDestination: true, allowed: arm64SVEWidthPairs( + [2]int{64, 32}, + )}, + } +) + +func arm64SVEWidthPairs(pairs ...[2]int) map[[2]int]bool { + result := make(map[[2]int]bool, len(pairs)) + for _, pair := range pairs { + result[pair] = true + } + return result +} + +func (c *arm64Ctx) lowerARM64SVEConvert(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEConvertSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zn.T, P0..P7/M|Z, Zd.T without a suffix: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !sourceOK || !destinationOK || !spec.allowed[[2]int{sourceBits, destinationBits}] { + return true, false, fmt.Errorf("arm64 %s does not accept the requested source/destination widths: %q", op, ins.Raw) + } + predicate, mergeOK := arm64ParseSVEPredicateMode(ins.Args[1], "M", 7) + zeroing := false + if !mergeOK { + predicate, zeroing = arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + if !zeroing { + return true, false, fmt.Errorf("arm64 %s requires P0..P7/M or P0..P7/Z: %q", op, ins.Raw) + } + } + + sourceValue, sourceType, err := c.loadARM64SVEConvertVector(source, sourceBits, spec.kind == arm64SVEConvertFloat || spec.kind == arm64SVEConvertFloatToSigned || spec.kind == arm64SVEConvertFloatToUnsigned) + if err != nil { + return true, false, err + } + destinationFloat := spec.kind == arm64SVEConvertFloat || spec.kind == arm64SVEConvertSignedToFloat || spec.kind == arm64SVEConvertUnsignedToFloat + merge := "zeroinitializer" + destinationType, err := arm64SVEConvertVectorType(destinationBits, destinationFloat) + if err != nil { + return true, false, err + } + if !zeroing || spec.zeroKeepsDestination { + merge, _, err = c.loadARM64SVEConvertVector(destination, destinationBits, destinationFloat) + if err != nil { + return true, false, err + } + } + predicateBits := sourceBits + if destinationBits > predicateBits { + predicateBits = destinationBits + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, predicateBits) + if err != nil { + return true, false, err + } + name := arm64SVEConvertIntrinsicName(spec, sourceBits, destinationBits, zeroing) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s(%s %s, %s %s, %s %s)\n", + result, destinationType, name, destinationType, merge, predicateType, predicateValue, sourceType, sourceValue) + if destinationFloat { + return true, false, c.storeRawSVEFloatVector(destination, destinationBits, "%"+result, destinationType) + } + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} + +func arm64SVEConvertVectorType(elementBits int, floating bool) (string, error) { + if floating { + _, vectorType, _, err := arm64SVEFloatType(elementBits) + return vectorType, err + } + vectorType, _, err := arm64SVEVectorType(elementBits) + return vectorType, err +} + +func (c *arm64Ctx) loadARM64SVEConvertVector(register, elementBits int, floating bool) (string, string, error) { + if floating { + return c.loadRawSVEFloatVector(register, elementBits) + } + return c.loadZRegElements(register, elementBits) +} + +func arm64SVEConvertIntrinsicName(spec arm64SVEConvertSpec, sourceBits, destinationBits int, zeroing bool) string { + floatCode := map[int]string{16: "f16", 32: "f32", 64: "f64"} + intCode := map[int]string{16: "i16", 32: "i32", 64: "i64"} + if spec.intrinsic != "" { + intrinsic := spec.intrinsic + if zeroing && spec.zeroIntrinsic != "" { + intrinsic = spec.zeroIntrinsic + } + return intrinsic + "." + floatCode[destinationBits] + floatCode[sourceBits] + } + switch spec.kind { + case arm64SVEConvertFloat: + return "fcvt." + floatCode[destinationBits] + floatCode[sourceBits] + case arm64SVEConvertFloatToSigned: + return "fcvtzs." + intCode[destinationBits] + floatCode[sourceBits] + case arm64SVEConvertFloatToUnsigned: + return "fcvtzu." + intCode[destinationBits] + floatCode[sourceBits] + case arm64SVEConvertSignedToFloat: + return "scvtf." + floatCode[destinationBits] + intCode[sourceBits] + default: + return "ucvtf." + floatCode[destinationBits] + intCode[sourceBits] + } +} + +func emitARM64SVEConvertDeclarations(b *strings.Builder) { + for _, op := range []Op{"ZFCVT", "ZFCVTZS", "ZFCVTZU", "ZSCVTF", "ZUCVTF", "ZFCVTLT", "ZFCVTX", "ZFCVTXNT"} { + spec := arm64SVEConvertSpecs[op] + for _, sourceBits := range []int{16, 32, 64} { + for _, destinationBits := range []int{16, 32, 64} { + if !spec.allowed[[2]int{sourceBits, destinationBits}] { + continue + } + sourceFloat := spec.kind == arm64SVEConvertFloat || spec.kind == arm64SVEConvertFloatToSigned || spec.kind == arm64SVEConvertFloatToUnsigned + destinationFloat := spec.kind == arm64SVEConvertFloat || spec.kind == arm64SVEConvertSignedToFloat || spec.kind == arm64SVEConvertUnsignedToFloat + sourceType, _ := arm64SVEConvertVectorType(sourceBits, sourceFloat) + destinationType, _ := arm64SVEConvertVectorType(destinationBits, destinationFloat) + predicateBits := sourceBits + if destinationBits > predicateBits { + predicateBits = destinationBits + } + _, predicateLanes, _ := arm64SVEVectorType(predicateBits) + predicateType := fmt.Sprintf("", predicateLanes) + names := []string{arm64SVEConvertIntrinsicName(spec, sourceBits, destinationBits, false)} + if spec.zeroIntrinsic != "" { + names = append(names, arm64SVEConvertIntrinsicName(spec, sourceBits, destinationBits, true)) + } + for _, name := range names { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s(%s, %s, %s)\n", + destinationType, name, destinationType, predicateType, sourceType) + } + } + } + } +} diff --git a/arm64_lower_sve_convert_test.go b/arm64_lower_sve_convert_test.go new file mode 100644 index 00000000..20bce9ce --- /dev/null +++ b/arm64_lower_sve_convert_test.go @@ -0,0 +1,114 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEConvertCompleteForms() string { + forms := map[string][][2]string{ + "ZFCVT": { + {"H", "S"}, {"H", "D"}, {"S", "H"}, {"S", "D"}, {"D", "H"}, {"D", "S"}, + }, + "ZFCVTZS": { + {"H", "H"}, {"H", "S"}, {"H", "D"}, {"S", "S"}, {"S", "D"}, {"D", "S"}, {"D", "D"}, + }, + "ZFCVTZU": { + {"H", "H"}, {"H", "S"}, {"H", "D"}, {"S", "S"}, {"S", "D"}, {"D", "S"}, {"D", "D"}, + }, + "ZSCVTF": { + {"H", "H"}, {"S", "H"}, {"S", "S"}, {"S", "D"}, {"D", "H"}, {"D", "S"}, {"D", "D"}, + }, + "ZUCVTF": { + {"H", "H"}, {"S", "H"}, {"S", "S"}, {"S", "D"}, {"D", "H"}, {"D", "S"}, {"D", "D"}, + }, + "ZFCVTLT": {{"H", "S"}, {"S", "D"}}, + "ZFCVTX": {{"D", "S"}}, + "ZFCVTXNT": {{"D", "S"}}, + } + var source strings.Builder + source.WriteString("TEXT sveconvertforms(SB),$0-0\n") + register := 0 + for _, op := range []string{"ZFCVT", "ZFCVTZS", "ZFCVTZU", "ZSCVTF", "ZUCVTF", "ZFCVTLT", "ZFCVTX", "ZFCVTXNT"} { + for _, widths := range forms[op] { + for _, mode := range []string{"M", "Z"} { + fmt.Fprintf(&source, "\t%s Z%d.%s, P7.%s, Z%d.%s\n", op, register%32, widths[0], mode, (register+1)%32, widths[1]) + register += 2 + } + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEConvertCompleteGo127Family(t *testing.T) { + source := arm64SVEConvertCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveconvertforms": {Name: "sveconvertforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve,+sve2p2\"", + "@llvm.aarch64.sve.fcvt.f16f32", + "@llvm.aarch64.sve.fcvt.f64f16", + "@llvm.aarch64.sve.fcvtzs.i32f64", + "@llvm.aarch64.sve.fcvtzu.i64f16", + "@llvm.aarch64.sve.scvtf.f16i64", + "@llvm.aarch64.sve.ucvtf.f64i32", + "@llvm.aarch64.sve.fcvtlt.f32f16", + "@llvm.aarch64.sve.fcvtx.f32f64", + "@llvm.aarch64.sve.fcvtxnt.f32f64", + "@llvm.aarch64.sve.fcvtxnt.z.f32f64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE conversion lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-convert.ll", "arm64-sve-convert.o", ll) + }) + } +} + +func TestTranslateARM64SVEConvertRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFCVT Z0.H, P0.M, Z1.H", + "ZFCVT Z0.S, P0.M, Z1.S", + "ZFCVT Z0.D, P0.M, Z1.D", + "ZFCVTZS Z0.D, P0.M, Z1.H", + "ZFCVTZU Z0.S, P0.M, Z1.H", + "ZSCVTF Z0.H, P0.M, Z1.S", + "ZUCVTF Z0.H, P0.M, Z1.D", + "ZFCVTLT Z0.D, P0.M, Z1.S", + "ZFCVTX Z0.S, P0.M, Z1.H", + "ZFCVTXNT Z0.S, P0.M, Z1.D", + "ZFCVT Z0.H, P8.M, Z1.S", + "ZFCVT Z0.H, P0, Z1.S", + "ZFCVT.Z Z0.H, P0.M, Z1.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveconvert(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveconvert": {Name: "badsveconvert", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE conversion forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_copy.go b/arm64_lower_sve_copy.go new file mode 100644 index 00000000..8c17eef6 --- /dev/null +++ b/arm64_lower_sve_copy.go @@ -0,0 +1,130 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVECopyVectorBaseSize = map[Op]int{ + "ZCPYB": 0, + "ZCPYH": 1, + "ZCPYS": 2, + "ZCPYD": 3, +} + +func (c *arm64Ctx) lowerARM64SVECopy(op Op, ins Instr) (ok bool, terminated bool, err error) { + vectorBaseSize, vectorForm := arm64SVECopyVectorBaseSize[op] + if op != "ZCPY" && op != "ZCPYW" && !vectorForm { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects scalar, predicate mode, Z.B/H/S/D without a suffix: %q", op, ins.Raw) + } + + destination, writtenBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !destinationOK { + return true, false, fmt.Errorf("arm64 %s destination must be Z0..Z31.B/H/S/D: %q", op, ins.Raw) + } + writtenSize := map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[writtenBits] + elementBits := writtenBits + predicateLimit := 7 + mode := "M" + var scalar string + + switch { + case op == "ZCPY" && ins.Args[0].Kind == OpImm: + if !arm64SVECopyImmediate(ins.Args[0]) { + return true, false, fmt.Errorf("arm64 ZCPY immediate must be signed 8-bit, optionally shifted left 8: %q", ins.Raw) + } + predicateLimit = 15 + if _, ok := arm64ParseSVEPredicateMode(ins.Args[1], "M", predicateLimit); !ok { + mode = "Z" + } + scalar = arm64SVECopyImmediateValue(ins.Args[0].Imm, elementBits) + case op == "ZCPY" || op == "ZCPYW": + if !arm64SVECopyGeneralRegister(ins.Args[0]) { + return true, false, fmt.Errorf("arm64 %s source must be R0..R30 or RSP: %q", op, ins.Raw) + } + baseSize := 3 + if op == "ZCPYW" { + baseSize = 0 + } + elementBits = 8 << (baseSize | writtenSize) + scalar, err = c.loadReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + scalar = c.arm64SVECopyTruncate(scalar, elementBits) + case vectorForm: + register, registerOK := arm64SVEInsertVRegister(ins.Args[0]) + if !registerOK { + return true, false, fmt.Errorf("arm64 %s source must be a bare V0..V31 register: %q", op, ins.Raw) + } + elementBits = 8 << (vectorBaseSize | writtenSize) + scalar, err = c.arm64SVEInsertVectorScalar(register, elementBits) + if err != nil { + return true, false, err + } + } + + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[1], mode, predicateLimit) + if !predicateOK { + return true, false, fmt.Errorf("arm64 %s predicate must be P0..P%d.%s: %q", op, predicateLimit, mode, ins.Raw) + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + vectorType, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + inserted := c.newTmp() + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s poison, i%d %s, i64 0\n", inserted, vectorType, elementBits, scalar) + fmt.Fprintf(c.b, " %%%s = shufflevector %s %%%s, %s poison, zeroinitializer\n", splat, vectorType, inserted, vectorType, lanes) + merge := "zeroinitializer" + if mode == "M" { + merge, _, err = c.loadZRegElements(destination, elementBits) + if err != nil { + return true, false, err + } + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %%%s, %s %s\n", + result, predicateType, predicateValue, vectorType, splat, vectorType, merge) + return true, false, c.storeZRegElements(destination, elementBits, "%"+result) +} + +func arm64SVECopyImmediate(operand Operand) bool { + if operand.Kind != OpImm || operand.ImmRaw != "" { + return false + } + value := operand.Imm + if value >= -128 && value <= 127 { + return true + } + return value%256 == 0 && value/256 >= -128 && value/256 <= 127 +} + +func arm64SVECopyImmediateValue(value int64, elementBits int) string { + mask := uint64(1)<", + "insertelement ", + "insertelement ", + "insertelement ", + "select ", + "select ", + "select ", + "select ", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE CPY lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-copy.ll", "arm64-sve-copy.o", ll) + }) + } +} + +func TestTranslateARM64SVECopyRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZCPY $-33024, P0.M, Z0.B", + "ZCPY $-129, P0.M, Z0.B", + "ZCPY $128, P0.M, Z0.B", + "ZCPY $32768, P0.M, Z0.B", + "ZCPY $1, P0, Z0.B", + "ZCPY $1, P16.M, Z0.B", + "ZCPY $1, P0.M, Z0.Q", + "ZCPY R0, P8.M, Z0.D", + "ZCPY ZR, P0.M, Z0.D", + "ZCPYW ZR, P0.M, Z0.S", + "ZCPYB V0, P8.M, Z0.B", + "ZCPYB R0, P0.M, Z0.B", + "ZCPYD V0, P0.Z, Z0.D", + "ZCPY.Z $1, P0.M, Z0.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvecopy(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvecopy": {Name: "badsvecopy", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE CPY forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_count.go b/arm64_lower_sve_count.go new file mode 100644 index 00000000..9cbcddef --- /dev/null +++ b/arm64_lower_sve_count.go @@ -0,0 +1,54 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64RawSVECnt struct { + op Op + elementBits int + destination int +} + +func decodeARM64RawSVECnt(word uint32) (arm64RawSVECnt, bool) { + base := word & 0xffe0ffe0 + forms := map[uint32]struct { + op Op + bits int + }{ + 0x0420e3e0: {"CNTB", 8}, + 0x0460e3e0: {"CNTH", 16}, + 0x04a0e3e0: {"CNTW", 32}, + 0x04e0e3e0: {"CNTD", 64}, + } + form, ok := forms[base] + if !ok { + return arm64RawSVECnt{}, false + } + return arm64RawSVECnt{op: form.op, elementBits: form.bits, destination: int(word & 31)}, true +} + +func (c *arm64Ctx) lowerRawSVECnt(form arm64RawSVECnt) error { + ins := Instr{Op: form.op, Raw: fmt.Sprintf("decoded ARM64 WORD as %s", form.op), Args: []Operand{{Kind: OpReg, Reg: Reg(fmt.Sprintf("R%d", form.destination))}}} + ok, _, err := c.lowerARM64SVECnt(form.op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", form.op) + } + return err +} + +func (c *arm64Ctx) lowerARM64SVECnt(op Op, ins Instr) (ok bool, terminated bool, err error) { + multiplier, handled := map[Op]int{"CNTB": 16, "CNTH": 8, "CNTW": 4, "CNTD": 2}[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 1 || ins.Args[0].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[0].Reg) || ins.Args[0].Reg == ZR { + return true, false, fmt.Errorf("arm64 %s expects one general destination register: %q", op, ins.Raw) + } + vscale := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.vscale.i64()\n", vscale) + count := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %d\n", count, vscale, multiplier) + return true, false, c.storeReg(ins.Args[0].Reg, "%"+count) +} diff --git a/arm64_lower_sve_divide.go b/arm64_lower_sve_divide.go new file mode 100644 index 00000000..17afefc0 --- /dev/null +++ b/arm64_lower_sve_divide.go @@ -0,0 +1,46 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEDivideIntrinsics = map[Op]string{ + "ZSDIV": "sdiv", + "ZSDIVR": "sdivr", + "ZUDIV": "udiv", + "ZUDIVR": "udivr", +} + +func (c *arm64Ctx) lowerARM64SVEDivide(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEDivideIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects Zm.S|D, Zdn.S|D, P0..P7/M, Zdn.S|D without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || (firstBits != 32 && firstBits != 64) || secondBits != firstBits || destinationBits != firstBits || destination != first { + return true, false, fmt.Errorf("arm64 %s requires matching-width destructive S/D operands and P0..P7/M: %q", op, ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, firstBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, firstBits) + if err != nil { + return true, false, err + } + lanes := 128 / firstBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, intrinsic, lanes, firstBits, predicateType, predicateValue, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeZRegElements(destination, firstBits, "%"+result) +} diff --git a/arm64_lower_sve_divide_test.go b/arm64_lower_sve_divide_test.go new file mode 100644 index 00000000..42f56e76 --- /dev/null +++ b/arm64_lower_sve_divide_test.go @@ -0,0 +1,75 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEDivideCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svedivideforms(SB),$0-0\n") + for _, op := range []string{"ZSDIV", "ZSDIVR", "ZUDIV", "ZUDIVR"} { + for predicate, width := range []string{"S", "D"} { + source.WriteString("\t" + op + " Z1." + width + ", Z2." + width + ", P" + string(rune('0'+predicate)) + ".M, Z2." + width + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEDivideCompleteGo127Family(t *testing.T) { + source := arm64SVEDivideCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svedivideforms": {Name: "svedivideforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.sdiv.nxv4i32", + "@llvm.aarch64.sve.sdivr.nxv2i64", + "@llvm.aarch64.sve.udiv.nxv4i32", + "@llvm.aarch64.sve.udivr.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE divide lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-divide.ll", "arm64-sve-divide.o", ll) + }) + } +} + +func TestTranslateARM64SVEDivideRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSDIV Z1.B, Z2.B, P0.M, Z2.B", + "ZUDIV Z1.H, Z2.H, P0.M, Z2.H", + "ZSDIVR Z1.S, Z2.D, P0.M, Z2.D", + "ZUDIVR Z1.D, Z2.D, P0, Z2.D", + "ZSDIV Z1.S, Z2.S, P8.M, Z2.S", + "ZUDIV Z1.S, Z2.S, P0.M, Z3.S", + "ZSDIV.Z Z1.S, Z2.S, P0.M, Z2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvedivide(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvedivide": {Name: "badsvedivide", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE divide forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_dup_general.go b/arm64_lower_sve_dup_general.go new file mode 100644 index 00000000..8382e3b1 --- /dev/null +++ b/arm64_lower_sve_dup_general.go @@ -0,0 +1,47 @@ +package plan9asm + +import "fmt" + +type arm64RawSVEDupGeneral struct { + elementBits int + source int + destination int +} + +// decodeARM64RawSVEDupGeneral covers the complete SVE DUP (general) encoding: +// DUP Zd.T, Rn, where T is B/H/S/D and R31 denotes SP (not ZR). +func decodeARM64RawSVEDupGeneral(word uint32) (arm64RawSVEDupGeneral, bool) { + if word&0xff3ffc00 != 0x05203800 { + return arm64RawSVEDupGeneral{}, false + } + return arm64RawSVEDupGeneral{ + elementBits: 8 << (int(word>>22) & 3), + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawSVEDupGeneral(form arm64RawSVEDupGeneral) error { + reg := Reg(fmt.Sprintf("R%d", form.source)) + if form.source == 31 { + reg = SP + } + source, err := c.loadReg(reg) + if err != nil { + return err + } + if form.elementBits != 64 { + narrowed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrowed, source, form.elementBits) + source = "%" + narrowed + } + lanes := 128 / form.elementBits + vectorType := fmt.Sprintf("", lanes, form.elementBits) + inserted := c.newTmp() + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s poison, i%d %s, i64 0\n", inserted, vectorType, form.elementBits, source) + fmt.Fprintf(c.b, " %%%s = shufflevector %s %%%s, %s poison, zeroinitializer\n", splat, vectorType, inserted, vectorType, lanes) + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to \n", bytes, vectorType, splat) + return c.storeZReg(form.destination, "%"+bytes) +} diff --git a/arm64_lower_sve_dup_general_test.go b/arm64_lower_sve_dup_general_test.go new file mode 100644 index 00000000..7f2a399c --- /dev/null +++ b/arm64_lower_sve_dup_general_test.go @@ -0,0 +1,73 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64RawSVEDupGeneral(elementBits, source, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + return 0x05203800 | size<<22 | uint32(source)<<5 | uint32(destination) +} + +func TestTranslateARM64RawSVEDupGeneralCompleteArchitecturalForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT sveDupGeneralRaw(SB), $0-0\n") + for _, elementBits := range []int{8, 16, 32, 64} { + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawSVEDupGeneral(elementBits, 15, elementBits/8)) + } + source.WriteString("\tRET\n") + + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveDupGeneralRaw": {Name: "sveDupGeneralRaw", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve"`, "", "insertelement >16) & 31 + if imm5 == 0 { + return arm64RawSVEDupElement{}, false + } + size := 0 + for imm5&(1< 4 { + return arm64RawSVEDupElement{}, false + } + form := arm64RawSVEDupElement{ + elementBits: 8 << size, + source: int(word>>5) & 31, + destination: int(word) & 31, + } + if size == 4 { + if imm5 != 16 { + return arm64RawSVEDupElement{}, false + } + form.lane = int(word>>22) & 1 + } else { + if word&(1<<22) != 0 { + return arm64RawSVEDupElement{}, false + } + form.lane = imm5 >> (size + 1) + } + return form, true +} + +func decodeARM64RawSVEDupImmediate(word uint32) (arm64RawSVEDupImmediate, bool) { + if word&0xff3fc000 != 0x2538c000 { + return arm64RawSVEDupImmediate{}, false + } + elementBits := 8 << (int(word>>22) & 3) + shift := 0 + if word&(1<<13) != 0 { + shift = 8 + } + // The byte element has no room for an LSL #8 immediate. LLVM and the Arm + // architecture reject this encoding even though Go 1.27's generated + // encoder does not correlate the shift bit with the element size. + if elementBits == 8 && shift != 0 { + return arm64RawSVEDupImmediate{}, false + } + immediate := int(int8(word >> 5)) + immediate <<= shift + return arm64RawSVEDupImmediate{ + elementBits: elementBits, + immediate: immediate, + destination: int(word) & 31, + }, true +} + +func arm64ParseSVEZElementReg(operand Operand) (index, elementBits int, ok bool) { + if operand.Kind != OpReg { + return 0, 0, false + } + parts := strings.Split(strings.ToUpper(strings.TrimSpace(string(operand.Reg))), ".") + if len(parts) != 2 || !strings.HasPrefix(parts[0], "Z") { + return 0, 0, false + } + index, err := strconv.Atoi(strings.TrimPrefix(parts[0], "Z")) + if err != nil || index < 0 || index > 31 { + return 0, 0, false + } + elementBits, ok = map[string]int{"B": 8, "H": 16, "S": 32, "D": 64}[parts[1]] + return index, elementBits, ok +} + +func arm64SVEDupImmediateRepresentable(elementBits int, immediate int64) bool { + if immediate >= -128 && immediate <= 127 { + return true + } + if elementBits == 8 || immediate%256 != 0 { + return false + } + unshifted := immediate / 256 + return unshifted >= -128 && unshifted <= 127 +} + +func arm64ParseSVEDupElementReg(operand Operand) (index, elementBits, lane int, ok bool) { + if operand.Kind != OpReg { + return 0, 0, 0, false + } + name := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + dot := strings.IndexByte(name, '.') + open := strings.IndexByte(name, '[') + if dot <= 1 || open <= dot+1 || !strings.HasSuffix(name, "]") || !strings.HasPrefix(name, "Z") { + return 0, 0, 0, false + } + index, err := strconv.Atoi(name[1:dot]) + if err != nil || index < 0 || index > 31 { + return 0, 0, 0, false + } + elementBits, ok = map[string]int{"B": 8, "H": 16, "S": 32, "D": 64, "Q": 128}[name[dot+1:open]] + lane, err = strconv.Atoi(name[open+1 : len(name)-1]) + if err != nil || !ok || lane < 0 || lane >= 256/elementBits { + return 0, 0, 0, false + } + return index, elementBits, lane, true +} + +func arm64ParseSVEDupDestination(operand Operand, allowQ bool) (index, elementBits int, ok bool) { + if index, elementBits, ok = arm64ParseSVEZElementReg(operand); ok { + return index, elementBits, true + } + if !allowQ || operand.Kind != OpReg { + return 0, 0, false + } + name := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + if !strings.HasPrefix(name, "Z") || !strings.HasSuffix(name, ".Q") { + return 0, 0, false + } + index, err := strconv.Atoi(strings.TrimSuffix(strings.TrimPrefix(name, "Z"), ".Q")) + return index, 128, err == nil && index >= 0 && index <= 31 +} + +func arm64ParseSVEDupGeneralSource(operand Operand) (int, bool) { + if operand.Kind != OpReg { + return 0, false + } + name := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + if name == "SP" || name == "RSP" { + return 31, true + } + if !strings.HasPrefix(name, "R") { + return 0, false + } + index, err := strconv.Atoi(strings.TrimPrefix(name, "R")) + return index, err == nil && index >= 0 && index <= 30 +} + +func (c *arm64Ctx) lowerARM64SVEDupImmediate(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZDUP" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 ZDUP expects one of Go 1.27's general, indexed-element, or immediate forms: %q", ins.Raw) + } + if source, validSource := arm64ParseSVEDupGeneralSource(ins.Args[0]); validSource { + destination, elementBits, validDestination := arm64ParseSVEDupDestination(ins.Args[1], false) + if !validDestination { + return true, false, fmt.Errorf("arm64 ZDUP general expects Rn|RSP, Zd.B|H|S|D: %q", ins.Raw) + } + return true, false, c.lowerRawSVEDupGeneral(arm64RawSVEDupGeneral{elementBits: elementBits, source: source, destination: destination}) + } + if source, elementBits, lane, validSource := arm64ParseSVEDupElementReg(ins.Args[0]); validSource { + destination, destinationBits, validDestination := arm64ParseSVEDupDestination(ins.Args[1], true) + if !validDestination || elementBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZDUP element expects Zn.T[index], Zd.T with matching B/H/S/D/Q: %q", ins.Raw) + } + return true, false, c.lowerRawSVEDupElement(arm64RawSVEDupElement{elementBits: elementBits, lane: lane, source: source, destination: destination}) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 ZDUP expects one of Go 1.27's general, indexed-element, or immediate forms: %q", ins.Raw) + } + destination, elementBits, valid := arm64ParseSVEZElementReg(ins.Args[1]) + if !valid || !arm64SVEDupImmediateRepresentable(elementBits, ins.Args[0].Imm) { + return true, false, fmt.Errorf("arm64 ZDUP immediate is outside Go 1.27's SVE form: %q", ins.Raw) + } + return true, false, c.lowerRawSVEDupImmediate(arm64RawSVEDupImmediate{ + elementBits: elementBits, + immediate: int(ins.Args[0].Imm), + destination: destination, + }) +} + +func (c *arm64Ctx) lowerRawSVEDupElement(form arm64RawSVEDupElement) error { + source, err := c.loadZReg(form.source) + if err != nil { + return err + } + if form.elementBits == 128 { + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.dupq.lane.nxv16i8( %s, i64 %d)\n", result, source, form.lane) + return c.storeZReg(form.destination, "%"+result) + } + lanes := 128 / form.elementBits + vectorType := fmt.Sprintf("", lanes, form.elementBits) + typedSource := source + if form.elementBits != 8 { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s to %s\n", converted, source, vectorType) + typedSource = "%" + converted + } + element := c.newTmp() + inserted := c.newTmp() + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i64 %d\n", element, vectorType, typedSource, form.lane) + fmt.Fprintf(c.b, " %%%s = insertelement %s poison, i%d %%%s, i64 0\n", inserted, vectorType, form.elementBits, element) + fmt.Fprintf(c.b, " %%%s = shufflevector %s %%%s, %s poison, zeroinitializer\n", splat, vectorType, inserted, vectorType, lanes) + result := "%" + splat + if form.elementBits != 8 { + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to \n", bytes, vectorType, result) + result = "%" + bytes + } + return c.storeZReg(form.destination, result) +} + +func (c *arm64Ctx) lowerRawSVEDupImmediate(form arm64RawSVEDupImmediate) error { + lanes := 128 / form.elementBits + vectorType := fmt.Sprintf("", lanes, form.elementBits) + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s splat (i%d %d) to \n", + bytes, vectorType, form.elementBits, form.immediate) + return c.storeZReg(form.destination, "%"+bytes) +} diff --git a/arm64_lower_sve_dupm.go b/arm64_lower_sve_dupm.go new file mode 100644 index 00000000..a2f6a239 --- /dev/null +++ b/arm64_lower_sve_dupm.go @@ -0,0 +1,23 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEDupM(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZDUPM" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || ins.Args[0].ImmIsFloat { + return true, false, fmt.Errorf("arm64 ZDUPM expects a resolved logical bitmask immediate and Zd.B|H|S|D without a suffix: %q", ins.Raw) + } + destination, elementBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[1]) + immediate := uint64(ins.Args[0].Imm) + if !destinationOK || !arm64SVELogicalImmediateRepresentable(elementBits, immediate) { + return true, false, fmt.Errorf("arm64 ZDUPM immediate is not a Go logical bitmask for the destination width: %q", ins.Raw) + } + immediate &= arm64SVEMaskForBits(elementBits) + value := fmt.Sprintf("splat (i%d %d)", elementBits, immediate) + return true, false, c.storeZRegElements(destination, elementBits, value) +} diff --git a/arm64_lower_sve_dupm_test.go b/arm64_lower_sve_dupm_test.go new file mode 100644 index 00000000..be39604b --- /dev/null +++ b/arm64_lower_sve_dupm_test.go @@ -0,0 +1,72 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEDupMCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svedupm(SB),$0-0\n") + for index, form := range []struct { + width string + immediate string + }{{"B", "0x55"}, {"H", "0xff00"}, {"S", "0xffff0000"}, {"D", "-4294967296"}} { + fmt.Fprintf(&source, "\tZDUPM $%s, Z%d.%s\n", form.immediate, index+16, form.width) + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svedupm": {Name: "svedupm", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "", + "", + "", + "", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s ZDUPM lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-dupm.ll", "arm64-sve-dupm.o", ll) + }) + } +} + +func TestTranslateARM64SVEDupMRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZDUPM $0, Z1.B", + "ZDUPM $255, Z1.B", + "ZDUPM $5, Z1.B", + "ZDUPM $65535, Z1.H", + "ZDUPM $1, Z1.Q", + "ZDUPM Z1.D, Z2.D", + "ZDUPM.Z $7, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvedupm(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvedupm": {Name: "badsvedupm", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ZDUPM forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_dupq.go b/arm64_lower_sve_dupq.go new file mode 100644 index 00000000..a0f68e4a --- /dev/null +++ b/arm64_lower_sve_dupq.go @@ -0,0 +1,28 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEDupQ(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZDUPQ" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 ZDUPQ expects Zn.B|H|S|D[index], Zd.B|H|S|D without a suffix: %q", ins.Raw) + } + source, elementBits, lane, sourceOK := arm64ParseSVEDupElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEDupDestination(ins.Args[1], false) + if !sourceOK || !destinationOK || elementBits == 128 || elementBits != destinationBits || lane >= 128/elementBits { + return true, false, fmt.Errorf("arm64 ZDUPQ requires matching B/H/S/D widths and an index within one 128-bit segment: %q", ins.Raw) + } + sourceValue, vectorType, err := c.loadZRegElements(source, elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.dupq.lane.nxv%di%d(%s %s, i64 %d)\n", result, vectorType, lanes, elementBits, vectorType, sourceValue, lane) + return true, false, c.storeZRegElements(destination, elementBits, "%"+result) +} diff --git a/arm64_lower_sve_dupq_test.go b/arm64_lower_sve_dupq_test.go new file mode 100644 index 00000000..d7ca8e04 --- /dev/null +++ b/arm64_lower_sve_dupq_test.go @@ -0,0 +1,75 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEDupQCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svedupq(SB),$0-0\n") + for widthIndex, form := range []struct { + width string + max int + }{{"B", 15}, {"H", 7}, {"S", 3}, {"D", 1}} { + for laneIndex, lane := range []int{0, form.max} { + destination := widthIndex*2 + laneIndex + fmt.Fprintf(&source, "\tZDUPQ Z%d.%s[%d], Z%d.%s\n", destination+16, form.width, lane, destination, form.width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svedupq": {Name: "svedupq", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2p1"`, + "@llvm.aarch64.sve.dupq.lane.nxv16i8", + "@llvm.aarch64.sve.dupq.lane.nxv8i16", + "@llvm.aarch64.sve.dupq.lane.nxv4i32", + "@llvm.aarch64.sve.dupq.lane.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s ZDUPQ lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-dupq.ll", "arm64-sve-dupq.o", ll) + }) + } +} + +func TestTranslateARM64SVEDupQRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZDUPQ Z1.B[16], Z2.B", + "ZDUPQ Z1.H[8], Z2.H", + "ZDUPQ Z1.S[4], Z2.S", + "ZDUPQ Z1.D[2], Z2.D", + "ZDUPQ Z1.H[2], Z2.S", + "ZDUPQ Z1.Q[0], Z2.Q", + "ZDUPQ.Z Z1.D[1], Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvedupq(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvedupq": {Name: "badsvedupq", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ZDUPQ forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_dupw.go b/arm64_lower_sve_dupw.go new file mode 100644 index 00000000..c3d3ad36 --- /dev/null +++ b/arm64_lower_sve_dupw.go @@ -0,0 +1,21 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEDupW(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZDUPW" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 ZDUPW expects Rn|RSP, Zd.B|H|S|D without a suffix: %q", ins.Raw) + } + source, sourceOK := arm64ParseSVEDupGeneralSource(ins.Args[0]) + destination, elementBits, destinationOK := arm64ParseSVEDupDestination(ins.Args[1], false) + if !sourceOK || !destinationOK { + return true, false, fmt.Errorf("arm64 ZDUPW requires R0..R30 or RSP and a B/H/S/D destination: %q", ins.Raw) + } + return true, false, c.lowerRawSVEDupGeneral(arm64RawSVEDupGeneral{elementBits: elementBits, source: source, destination: destination}) +} diff --git a/arm64_lower_sve_dupw_test.go b/arm64_lower_sve_dupw_test.go new file mode 100644 index 00000000..8f842344 --- /dev/null +++ b/arm64_lower_sve_dupw_test.go @@ -0,0 +1,72 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEDupWCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svedupw(SB),$0-0\n") + for index, width := range []string{"B", "H", "S", "D"} { + sourceReg := fmt.Sprintf("R%d", index+4) + if width == "D" { + sourceReg = "RSP" + } + fmt.Fprintf(&source, "\tZDUPW %s, Z%d.%s\n", sourceReg, index+16, width) + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svedupw": {Name: "svedupw", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "shufflevector ", + "shufflevector ", + "shufflevector ", + "shufflevector ", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s ZDUPW lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-dupw.ll", "arm64-sve-dupw.o", ll) + }) + } +} + +func TestTranslateARM64SVEDupWRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZDUPW ZR, Z1.B", + "ZDUPW R31, Z1.H", + "ZDUPW R1, Z32.S", + "ZDUPW R1, Z2.Q", + "ZDUPW Z1.S, Z2.S", + "ZDUPW.Z R1, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvedupw(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvedupw": {Name: "badsvedupw", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ZDUPW forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_eor.go b/arm64_lower_sve_eor.go new file mode 100644 index 00000000..8e06c6e1 --- /dev/null +++ b/arm64_lower_sve_eor.go @@ -0,0 +1,269 @@ +package plan9asm + +import ( + "fmt" + "math/bits" + "strings" +) + +type arm64SVEEORMode uint8 + +const ( + arm64SVEEORUnpredicated arm64SVEEORMode = iota + arm64SVEEORPredicated + arm64SVEEORImmediate +) + +type arm64RawSVEEOR struct { + op Op + mode arm64SVEEORMode + elementBits int + first int + second int + predicate int + immediate uint64 + destination int +} + +func decodeARM64SVELogicalImmediate(imm13 int) (elementBits int, immediate uint64, ok bool) { + n := (imm13 >> 12) & 1 + immr := (imm13 >> 6) & 63 + imms := imm13 & 63 + lengthSource := n<<6 | (^imms & 63) + length := bits.Len(uint(lengthSource)) - 1 + if length < 1 { + return 0, 0, false + } + esize := 1 << length + levels := esize - 1 + s := imms & levels + if s == levels { + return 0, 0, false + } + r := immr & levels + ones := s + 1 + pattern := (uint64(1) << ones) - 1 + mask := ^uint64(0) + if esize < 64 { + mask = (uint64(1) << esize) - 1 + } + pattern = ((pattern >> r) | (pattern << (esize - r))) & mask + elementBits = esize + if elementBits < 8 { + elementBits = 8 + } + for offset := esize; offset < elementBits; offset += esize { + immediate |= pattern << offset + } + immediate |= pattern + return elementBits, immediate, true +} + +func decodeARM64RawSVEEOR(word uint32) (arm64RawSVEEOR, bool) { + form := arm64RawSVEEOR{} + switch { + case word&0xffe0fc00 == 0x04203000: + form.op = "ZAND" + form.mode = arm64SVEEORUnpredicated + form.elementBits = 64 + form.second = int(word>>16) & 31 + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + case word&0xffe0fc00 == 0x04603000: + form.op = "ZORR" + form.mode = arm64SVEEORUnpredicated + form.elementBits = 64 + form.second = int(word>>16) & 31 + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + case word&0xffe0fc00 == 0x04a03000: + form.op = "ZEOR" + form.mode = arm64SVEEORUnpredicated + form.elementBits = 64 + form.second = int(word>>16) & 31 + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + case word&0xffe0fc00 == 0x04e03000: + form.op = "ZBIC" + form.mode = arm64SVEEORUnpredicated + form.elementBits = 64 + form.second = int(word>>16) & 31 + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + case word&0xff3fe000 == 0x04180000: + form.op = "ZORR" + form.mode = arm64SVEEORPredicated + form.elementBits = 8 << (int(word>>22) & 3) + form.destination = int(word) & 31 + form.first = form.destination + form.second = int(word>>5) & 31 + form.predicate = int(word>>10) & 7 + case word&0xff3fe000 == 0x04190000: + form.op = "ZEOR" + form.mode = arm64SVEEORPredicated + form.elementBits = 8 << (int(word>>22) & 3) + form.destination = int(word) & 31 + form.first = form.destination + form.second = int(word>>5) & 31 + form.predicate = int(word>>10) & 7 + case word&0xff3fe000 == 0x041a0000: + form.op = "ZAND" + form.mode = arm64SVEEORPredicated + form.elementBits = 8 << (int(word>>22) & 3) + form.destination = int(word) & 31 + form.first = form.destination + form.second = int(word>>5) & 31 + form.predicate = int(word>>10) & 7 + case word&0xff3fe000 == 0x041b0000: + form.op = "ZBIC" + form.mode = arm64SVEEORPredicated + form.elementBits = 8 << (int(word>>22) & 3) + form.destination = int(word) & 31 + form.first = form.destination + form.second = int(word>>5) & 31 + form.predicate = int(word>>10) & 7 + case word&0xfffc0000 == 0x05000000: + form.op = "ZORR" + form.mode = arm64SVEEORImmediate + var ok bool + form.elementBits, form.immediate, ok = decodeARM64SVELogicalImmediate(int(word>>5) & 0x1fff) + if !ok { + return arm64RawSVEEOR{}, false + } + form.destination = int(word) & 31 + form.first = form.destination + case word&0xfffc0000 == 0x05400000: + form.op = "ZEOR" + form.mode = arm64SVEEORImmediate + var ok bool + form.elementBits, form.immediate, ok = decodeARM64SVELogicalImmediate(int(word>>5) & 0x1fff) + if !ok { + return arm64RawSVEEOR{}, false + } + form.destination = int(word) & 31 + form.first = form.destination + case word&0xfffc0000 == 0x05800000: + form.op = "ZAND" + form.mode = arm64SVEEORImmediate + var ok bool + form.elementBits, form.immediate, ok = decodeARM64SVELogicalImmediate(int(word>>5) & 0x1fff) + if !ok { + return arm64RawSVEEOR{}, false + } + form.destination = int(word) & 31 + form.first = form.destination + default: + return arm64RawSVEEOR{}, false + } + return form, true +} + +func arm64SVEMaskForBits(elementBits int) uint64 { + if elementBits == 64 { + return ^uint64(0) + } + return (uint64(1) << elementBits) - 1 +} + +func arm64SVEReplicateImmediate(value uint64, fromBits, toBits int) uint64 { + value &= arm64SVEMaskForBits(fromBits) + result := uint64(0) + for offset := 0; offset < toBits; offset += fromBits { + result |= value << offset + } + return result & arm64SVEMaskForBits(toBits) +} + +func arm64SVELogicalImmediateRepresentable(elementBits int, value uint64) bool { + value &= arm64SVEMaskForBits(elementBits) + if value == 0 || value == arm64SVEMaskForBits(elementBits) { + return false + } + for imm13 := 0; imm13 < 1<<13; imm13++ { + encodedBits, encodedValue, ok := decodeARM64SVELogicalImmediate(imm13) + if ok && encodedBits <= elementBits && arm64SVEReplicateImmediate(encodedValue, encodedBits, elementBits) == value { + return true + } + } + return false +} + +func (c *arm64Ctx) lowerARM64SVEEOR(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZAND" && op != "ZBIC" && op != "ZEOR" && op != "ZORR" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + form := arm64RawSVEEOR{} + if len(ins.Args) == 3 && ins.Args[0].Kind == OpImm { + if op == "ZBIC" { + return true, false, fmt.Errorf("arm64 ZBIC has no immediate form in Go 1.27: %q", ins.Raw) + } + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + immediate := uint64(ins.Args[0].Imm) + if ins.Args[0].ImmRaw != "" || !firstOK || !destinationOK || first != destination || firstBits != destinationBits || !arm64SVELogicalImmediateRepresentable(firstBits, immediate) { + return true, false, fmt.Errorf("arm64 %s immediate expects a Go logical bitmask and identical Zdn.T operands: %q", op, ins.Raw) + } + form = arm64RawSVEEOR{op: op, mode: arm64SVEEORImmediate, elementBits: firstBits, first: first, immediate: immediate & arm64SVEMaskForBits(firstBits), destination: destination} + } else if len(ins.Args) == 3 { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != 64 || firstBits != 64 || destinationBits != 64 { + return true, false, fmt.Errorf("arm64 %s unpredicated form requires three .D vectors: %q", op, ins.Raw) + } + form = arm64RawSVEEOR{op: op, mode: arm64SVEEORUnpredicated, elementBits: 64, first: first, second: second, destination: destination} + } else if len(ins.Args) == 4 { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits || first != destination { + return true, false, fmt.Errorf("arm64 %s predicated form requires one width and identical destructive operands: %q", op, ins.Raw) + } + form = arm64RawSVEEOR{op: op, mode: arm64SVEEORPredicated, elementBits: firstBits, first: first, second: second, predicate: predicate, destination: destination} + } else { + return true, false, fmt.Errorf("arm64 %s expects a Go 1.27 SVE logical form: %q", op, ins.Raw) + } + return true, false, c.lowerRawSVEEOR(form) +} + +func (c *arm64Ctx) lowerRawSVEEOR(form arm64RawSVEEOR) error { + first, vectorType, err := c.loadZRegElements(form.first, form.elementBits) + if err != nil { + return err + } + second := fmt.Sprintf("splat (i%d %d)", form.elementBits, form.immediate) + if form.mode != arm64SVEEORImmediate { + second, _, err = c.loadZRegElements(form.second, form.elementBits) + if err != nil { + return err + } + } + llvmOp := "xor" + if form.op == "ZAND" || form.op == "ZBIC" { + llvmOp = "and" + } else if form.op == "ZORR" { + llvmOp = "or" + } + if form.op == "ZBIC" { + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, splat (i%d -1)\n", inverted, vectorType, second, form.elementBits) + second = "%" + inverted + } + calculated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", calculated, llvmOp, vectorType, first, second) + result := "%" + calculated + if form.mode == arm64SVEEORPredicated { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", selected, predicateType, predicate, vectorType, result, vectorType, first) + result = "%" + selected + } + return c.storeZRegElements(form.destination, form.elementBits, result) +} diff --git a/arm64_lower_sve_eor_interleave.go b/arm64_lower_sve_eor_interleave.go new file mode 100644 index 00000000..45317ff5 --- /dev/null +++ b/arm64_lower_sve_eor_interleave.go @@ -0,0 +1,43 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEEORInterleaveIntrinsics = map[Op]string{ + "ZEORBT": "eorbt", + "ZEORTB": "eortb", +} + +func (c *arm64Ctx) lowerARM64SVEEORInterleave(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEEORInterleaveIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zm.T, Zn.T, Zd.T without a suffix: %q", op, ins.Raw) + } + third, thirdBits, thirdOK := arm64ParseSVEZElementReg(ins.Args[0]) + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !thirdOK || !secondOK || !destinationOK || thirdBits != secondBits || secondBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s operands must use one matching B/H/S/D width: %q", op, ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(destination, destinationBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, destinationBits) + if err != nil { + return true, false, err + } + thirdValue, _, err := c.loadZRegElements(third, destinationBits) + if err != nil { + return true, false, err + } + lanes := 128 / destinationBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, intrinsic, lanes, destinationBits, vectorType, firstValue, vectorType, secondValue, vectorType, thirdValue) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_eor_interleave_test.go b/arm64_lower_sve_eor_interleave_test.go new file mode 100644 index 00000000..4d5c5c8f --- /dev/null +++ b/arm64_lower_sve_eor_interleave_test.go @@ -0,0 +1,62 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEEORInterleaveCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT sveeorinterleaveforms(SB),$0-0\n") + for _, op := range []string{"ZEORBT", "ZEORTB"} { + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, Z3.%s\n", op, width, width, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveeorinterleaveforms": {Name: "sveeorinterleaveforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2"`, "@llvm.aarch64.sve.eorbt.nxv16i8", "@llvm.aarch64.sve.eortb.nxv2i64"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE EORBT/EORTB lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-eor-interleave.ll", "arm64-sve-eor-interleave.o", ll) + }) + } +} + +func TestTranslateARM64SVEEORInterleaveRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZEORBT Z1.B, Z2.H, Z3.B", + "ZEORTB Z1.Q, Z2.Q, Z3.Q", + "ZEORBT Z1.S, Z2.S", + "ZEORTB.Z Z1.D, Z2.D, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveeorinterleave(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveeorinterleave": {Name: "badsveeorinterleave", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE EORBT/EORTB forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_eor_test.go b/arm64_lower_sve_eor_test.go new file mode 100644 index 00000000..b337fd94 --- /dev/null +++ b/arm64_lower_sve_eor_test.go @@ -0,0 +1,159 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64RawSVEEORUnpredicated(second, first, destination int) uint32 { + return 0x04a03000 | uint32(second)<<16 | uint32(first)<<5 | uint32(destination) +} + +func encodeARM64RawSVEEORPredicated(elementBits, second, predicate, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + return 0x04190000 | size<<22 | uint32(second)<<5 | uint32(predicate)<<10 | uint32(destination) +} + +func encodeARM64RawSVEEORImmediateBits(imm13, destination int) uint32 { + return 0x05400000 | uint32(imm13)<<5 | uint32(destination) +} + +func TestTranslateARM64SVEEORCompleteGo127Forms(t *testing.T) { + const named = ` +TEXT sveeornamed(SB),$0-0 + ZEOR Z31.D, Z30.D, Z29.D + ZEOR Z28.B, Z0.B, P0.M, Z0.B + ZEOR Z27.H, Z1.H, P1.M, Z1.H + ZEOR Z26.S, Z2.S, P2.M, Z2.S + ZEOR Z25.D, Z3.D, P7.M, Z3.D + ZEOR $0x55, Z4.B, Z4.B + ZEOR $0xff00, Z5.H, Z5.H + ZEOR $0xffff0000, Z6.S, Z6.S + ZEOR $0xffffffff00000000, Z7.D, Z7.D + RET +` + requireARM64SVEGoAssemblerResult(t, named, true) + + var raw strings.Builder + raw.WriteString("TEXT sveeorraw(SB),$0-0\n") + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEEORUnpredicated(1, 2, 3)) + for _, elementBits := range []int{8, 16, 32, 64} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEEORPredicated(elementBits, 4, 5, 6)) + } + for _, imm13 := range []int{0x03c, 0x227, 0x40f, 0x181f} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEEORImmediateBits(imm13, 7)) + } + raw.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, raw.String(), true) + + for name, source := range map[string]string{"named": named, "raw": raw.String()} { + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "sveeor" + name + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve"`, " xor 4 || + ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 255 { + return true, false, fmt.Errorf("arm64 ZEXT expects an unsigned 8-bit immediate and one Go 1.27 vector form: %q", ins.Raw) + } + immediate := ins.Args[0].Imm + var first, second, destination int + if len(ins.Args) == 4 { + var firstOK, secondOK, destinationOK bool + second, secondOK = arm64ParseSVEByteReg(ins.Args[1]) + first, firstOK = arm64ParseSVEByteReg(ins.Args[2]) + destination, destinationOK = arm64ParseSVEByteReg(ins.Args[3]) + if !firstOK || !secondOK || !destinationOK || first != destination { + return true, false, fmt.Errorf("arm64 ZEXT destructive form requires $imm, Zm.B, Zdn.B, Zdn.B: %q", ins.Raw) + } + } else { + if ins.Args[1].Kind != OpRegList || len(ins.Args[1].RegList) != 2 { + return true, false, fmt.Errorf("arm64 ZEXT list form requires exactly two consecutive byte vectors: %q", ins.Raw) + } + var firstOK, secondOK, destinationOK bool + first, firstOK = arm64ParseSVEByteReg(Operand{Kind: OpReg, Reg: ins.Args[1].RegList[0]}) + second, secondOK = arm64ParseSVEByteReg(Operand{Kind: OpReg, Reg: ins.Args[1].RegList[1]}) + destination, destinationOK = arm64ParseSVEByteReg(ins.Args[2]) + if !firstOK || !secondOK || !destinationOK || first == 31 || second != first+1 { + return true, false, fmt.Errorf("arm64 ZEXT list form requires [Zn.B, Z(n+1).B], Zd.B: %q", ins.Raw) + } + } + firstValue, err := c.loadZReg(first) + if err != nil { + return true, false, err + } + secondValue, err := c.loadZReg(second) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.ext.nxv16i8( %s, %s, i32 %d)\n", + result, firstValue, secondValue, immediate) + return true, false, c.storeZReg(destination, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEEXTQ(ins Instr) (ok bool, terminated bool, err error) { + if strings.ToUpper(string(ins.Op)) != "ZEXTQ" || len(ins.Args) != 4 || + ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 15 { + return true, false, fmt.Errorf("arm64 ZEXTQ expects $imm4, Zm.B, Zdn.B, Zdn.B without a suffix: %q", ins.Raw) + } + second, secondOK := arm64ParseSVEByteReg(ins.Args[1]) + first, firstOK := arm64ParseSVEByteReg(ins.Args[2]) + destination, destinationOK := arm64ParseSVEByteReg(ins.Args[3]) + if !firstOK || !secondOK || !destinationOK || first != destination { + return true, false, fmt.Errorf("arm64 ZEXTQ requires matching destructive byte-vector operands: %q", ins.Raw) + } + firstValue, err := c.loadZReg(first) + if err != nil { + return true, false, err + } + secondValue, err := c.loadZReg(second) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.extq.nxv16i8( %s, %s, i32 %d)\n", + result, firstValue, secondValue, ins.Args[0].Imm) + return true, false, c.storeZReg(destination, "%"+result) +} + +func arm64ParseSVEByteReg(operand Operand) (int, bool) { + index, bits, ok := arm64ParseSVEZElementReg(operand) + return index, ok && bits == 8 +} diff --git a/arm64_lower_sve_ext_test.go b/arm64_lower_sve_ext_test.go new file mode 100644 index 00000000..ed251de4 --- /dev/null +++ b/arm64_lower_sve_ext_test.go @@ -0,0 +1,128 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEEXTCompleteGo127Family(t *testing.T) { + source := "TEXT sveextforms(SB),$0-0\n" + + "\tZEXT $0, Z2.B, Z1.B, Z1.B\n" + + "\tZEXT $255, Z4.B, Z3.B, Z3.B\n" + + "\tZEXT $6, [Z5.B, Z6.B], Z7.B\n" + + "\tZEXT $255, [Z30.B, Z31.B], Z8.B\n" + + "\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveextforms": {Name: "sveextforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.ext.nxv16i8", + "i32 0)", + "i32 255)", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE EXT lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-ext.ll", "arm64-sve-ext.o", ll) + }) + } +} + +func TestTranslateARM64SVEEXTRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZEXT $-1, Z1.B, Z0.B, Z0.B", + "ZEXT $256, Z1.B, Z0.B, Z0.B", + "ZEXT $1, Z1.B, Z0.B, Z2.B", + "ZEXT $1, Z1.H, Z0.H, Z0.H", + "ZEXT $1, [Z1.B], Z0.B", + "ZEXT $1, [Z1.B, Z3.B], Z0.B", + "ZEXT $1, [Z31.B, Z0.B], Z0.B", + "ZEXT.Z $1, Z1.B, Z0.B, Z0.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveext(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveext": {Name: "badsveext", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE EXT forms", instruction) + } + }) + } +} + +func TestTranslateARM64SVEEXTQCompleteGo127Family(t *testing.T) { + source := "TEXT sveextqforms(SB),$0-0\n" + + "\tZEXTQ $0, Z2.B, Z1.B, Z1.B\n" + + "\tZEXTQ $15, Z4.B, Z3.B, Z3.B\n" + + "\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveextqforms": {Name: "sveextqforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve,+sve2p1\"", + "@llvm.aarch64.sve.extq.nxv16i8", + "i32 0)", + "i32 15)", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE EXTQ lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-extq.ll", "arm64-sve-extq.o", ll) + }) + } +} + +func TestTranslateARM64SVEEXTQRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZEXTQ $-1, Z1.B, Z0.B, Z0.B", + "ZEXTQ $16, Z1.B, Z0.B, Z0.B", + "ZEXTQ $1, Z1.B, Z0.B, Z2.B", + "ZEXTQ $1, Z1.H, Z0.H, Z0.H", + "ZEXTQ $1, [Z1.B, Z2.B], Z0.B", + "ZEXTQ.Z $1, Z1.B, Z0.B, Z0.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveextq(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveextq": {Name: "badsveextq", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE EXTQ forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_fdot.go b/arm64_lower_sve_fdot.go new file mode 100644 index 00000000..9574fabb --- /dev/null +++ b/arm64_lower_sve_fdot.go @@ -0,0 +1,101 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEFDOTForm struct { + first, second, destination int + sourceBits, destinationBits int + lane int + indexed bool +} + +func (c *arm64Ctx) lowerARM64SVEFDOT(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZFDOT" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 ZFDOT expects one complete Go 1.27 vector or indexed form without a suffix: %q", ins.Raw) + } + form := arm64SVEFDOTForm{} + if first, sourceBits, firstOK := arm64ParseSVEZElementReg(ins.Args[0]); firstOK { + form.first, form.sourceBits = first, sourceBits + } else { + first, sourceBits, lane, firstOK := arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[0]) + if !firstOK || first > 7 { + return true, false, fmt.Errorf("arm64 ZFDOT indexed source must use Z0..Z7: %q", ins.Raw) + } + form.first, form.sourceBits, form.lane, form.indexed = first, sourceBits, lane, true + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + validWidths := (form.sourceBits == 8 && (destinationBits == 16 || destinationBits == 32)) || (form.sourceBits == 16 && destinationBits == 32) + if !secondOK || !destinationOK || secondBits != form.sourceBits || !validWidths { + return true, false, fmt.Errorf("arm64 ZFDOT requires B sources with an H/S accumulator or H sources with an S accumulator: %q", ins.Raw) + } + if form.indexed { + maxLane := 3 + if form.sourceBits == 8 && destinationBits == 16 { + maxLane = 7 + } + if form.lane > maxLane { + return true, false, fmt.Errorf("arm64 ZFDOT lane is outside the selected dot-product group range: %q", ins.Raw) + } + } + form.second, form.destination, form.destinationBits = second, destination, destinationBits + return true, false, c.lowerARM64SVEFDOTForm(form) +} + +func (c *arm64Ctx) lowerARM64SVEFDOTForm(form arm64SVEFDOTForm) error { + accumulator, accumulatorType, err := c.loadRawSVEFloatVector(form.destination, form.destinationBits) + if err != nil { + return err + } + result := c.newTmp() + if form.sourceBits == 8 { + first, err := c.loadZReg(form.first) + if err != nil { + return err + } + second, err := c.loadZReg(form.second) + if err != nil { + return err + } + lanes := 128 / form.destinationBits + mangle := map[int]string{16: "f16", 32: "f32"}[form.destinationBits] + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fp8.fdot.lane.nxv%d%s(%s %s, %s, %s, i32 %d)\n", result, accumulatorType, lanes, mangle, accumulatorType, accumulator, second, first, form.lane) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fp8.fdot.nxv%d%s(%s %s, %s, %s)\n", result, accumulatorType, lanes, mangle, accumulatorType, accumulator, second, first) + } + } else { + first, _, err := c.loadRawSVEFloatVector(form.first, 16) + if err != nil { + return err + } + second, _, err := c.loadRawSVEFloatVector(form.second, 16) + if err != nil { + return err + } + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.fdot.lane.x2.nxv4f32( %s, %s, %s, i32 %d)\n", result, accumulator, second, first, form.lane) + } else { + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.fdot.x2.nxv4f32( %s, %s, %s)\n", result, accumulator, second, first) + } + } + return c.storeRawSVEFloatVector(form.destination, form.destinationBits, "%"+result, accumulatorType) +} + +func arm64SVEFDOTFeatureClass(ins Instr) (sourceBits, destinationBits int, ok bool) { + if len(ins.Args) != 3 { + return 0, 0, false + } + _, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + if !sourceOK { + _, sourceBits, _, sourceOK = arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[0]) + } + _, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + return sourceBits, destinationBits, sourceOK && destinationOK +} diff --git a/arm64_lower_sve_fdot_test.go b/arm64_lower_sve_fdot_test.go new file mode 100644 index 00000000..9f80b4b2 --- /dev/null +++ b/arm64_lower_sve_fdot_test.go @@ -0,0 +1,77 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEFDOTCompleteGo127Family(t *testing.T) { + const source = `TEXT svefdot(SB),$0-0 + ZFDOT Z8.B, Z9.B, Z10.H + ZFDOT Z11.B, Z12.B, Z13.S + ZFDOT Z14.H, Z15.H, Z16.S + ZFDOT Z0.B[0], Z17.B, Z18.H + ZFDOT Z7.B[7], Z19.B, Z20.H + ZFDOT Z0.B[0], Z21.B, Z22.S + ZFDOT Z7.B[3], Z23.B, Z24.S + ZFDOT Z0.H[0], Z25.H, Z26.S + ZFDOT Z7.H[3], Z27.H, Z28.S + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefdot": {Name: "svefdot", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+f16f32dot,+fp8,+ssve-fp8dot2,+ssve-fp8dot4,+sve,+sve2,+sve2p1,+sve2p2"`, + "@llvm.aarch64.sve.fp8.fdot.nxv8f16", + "@llvm.aarch64.sve.fp8.fdot.nxv4f32", + "@llvm.aarch64.sve.fp8.fdot.lane.nxv8f16", + "@llvm.aarch64.sve.fp8.fdot.lane.nxv4f32", + "@llvm.aarch64.sve.fdot.x2.nxv4f32", + "@llvm.aarch64.sve.fdot.lane.x2.nxv4f32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s ZFDOT lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-fdot.ll", "arm64-sve-fdot.o", ll) + }) + } +} + +func TestTranslateARM64SVEFDOTRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFDOT Z1.S, Z2.S, Z3.D", + "ZFDOT Z1.B, Z2.H, Z3.S", + "ZFDOT Z8.B[0], Z2.B, Z3.H", + "ZFDOT Z7.B[8], Z2.B, Z3.H", + "ZFDOT Z7.B[4], Z2.B, Z3.S", + "ZFDOT Z7.H[4], Z2.H, Z3.S", + "ZFDOT Z7.H[3], Z2.H, Z3.H", + "ZFDOT.Z Z1.B, Z2.B, Z3.H", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefdot(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefdot": {Name: "badsvefdot", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ZFDOT forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_first_fault_memory.go b/arm64_lower_sve_first_fault_memory.go new file mode 100644 index 00000000..67592391 --- /dev/null +++ b/arm64_lower_sve_first_fault_memory.go @@ -0,0 +1,177 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEFirstFaultMemorySpec struct { + memoryBits int + signed bool +} + +// arm64SVEFirstFaultMemorySpecs covers every Go 1.27 LDFF1 spelling, +// including its widening unsigned and sign-extending variants. +var arm64SVEFirstFaultMemorySpecs = map[Op]arm64SVEFirstFaultMemorySpec{ + "ZLDFF1B": {memoryBits: 8}, + "ZLDFF1H": {memoryBits: 16}, + "ZLDFF1W": {memoryBits: 32}, + "ZLDFF1D": {memoryBits: 64}, + "ZLDFF1SB": {memoryBits: 8, signed: true}, + "ZLDFF1SH": {memoryBits: 16, signed: true}, + "ZLDFF1SW": {memoryBits: 32, signed: true}, +} + +func (c *arm64Ctx) lowerARM64SVEFirstFaultMemory(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEFirstFaultMemorySpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[0].Kind != OpMem || ins.Args[2].Kind != OpRegList { + return true, false, fmt.Errorf("arm64 %s expects memory, predicate, vector-list operands: %q", op, ins.Raw) + } + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + vectors, elementBits, vectorsOK := arm64ParseSVEConsecutiveVectorList(ins.Args[2]) + if !predicateOK || !vectorsOK || len(vectors) != 1 || elementBits < spec.memoryBits || spec.signed && elementBits == spec.memoryBits { + return true, false, fmt.Errorf("arm64 %s has predicate or destination widths outside its Go 1.27 table: %q", op, ins.Raw) + } + + memory := ins.Args[0].Mem + if _, _, vectorOffset := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}); vectorOffset { + return c.lowerARM64SVEFirstFaultVectorOffset(op, spec, memory, predicate, vectors[0], elementBits, ins) + } + if _, _, vectorBase := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Base}); vectorBase { + return c.lowerARM64SVEFirstFaultVectorBase(op, spec, memory, predicate, vectors[0], elementBits, ins) + } + return c.lowerARM64SVEFirstFaultContiguous(op, spec, memory, predicate, vectors[0], elementBits, ins) +} + +func (c *arm64Ctx) lowerARM64SVEFirstFaultContiguous(op Op, spec arm64SVEFirstFaultMemorySpec, memory MemRef, predicate, destination, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + address, err := c.arm64SVERegisterOffsetAddress(memory, int64(spec.memoryBits/8)) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + loadedType := fmt.Sprintf("", lanes, spec.memoryBits) + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ldff1.nxv%di%d(%s %s, ptr %%%s)\n", + loaded, loadedType, lanes, spec.memoryBits, predicateType, predicateValue, pointer) + return c.finishARM64SVEFirstFaultLoad(spec, destination, elementBits, loadedType, "%"+loaded) +} + +func (c *arm64Ctx) lowerARM64SVEFirstFaultVectorOffset(op Op, spec arm64SVEFirstFaultMemorySpec, memory MemRef, predicate, destination, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + if memory.Sym != "" || memory.Segment != "" || memory.Off != 0 || memory.OffRaw != "" { + return true, false, fmt.Errorf("arm64 %s vector-offset form does not accept a displacement: %q", op, ins.Raw) + } + baseReg, baseOK := arm64SVEPhysicalMemoryBase(memory.Base) + index, indexBits, indexOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}) + byteScale := int64(spec.memoryBits / 8) + if !baseOK || !indexOK || indexBits != elementBits || (elementBits != 32 && elementBits != 64) || (memory.Scale != 1 && memory.Scale != byteScale) { + return true, false, fmt.Errorf("arm64 %s vector offset has widths or scale outside its Go 1.27 table: %q", op, ins.Raw) + } + + extension := "" + switch memory.IndexExt { + case "": + if indexBits != 64 { + return true, false, fmt.Errorf("arm64 %s unextended vector offset requires Zm.D: %q", op, ins.Raw) + } + case ExtendUXTW: + extension = "uxtw" + case ExtendSXTW: + extension = "sxtw" + default: + return true, false, fmt.Errorf("arm64 %s vector offset only accepts UXTW or SXTW: %q", op, ins.Raw) + } + + base, err := c.loadReg(baseReg) + if err != nil { + return true, false, err + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, base) + indexValue, indexType, err := c.loadZRegElements(index, indexBits) + if err != nil { + return true, false, err + } + // Go accepts Zm.D.UXTW/SXTW. LLVM models the UXTW/SXTW gather intrinsics + // with 32-bit lanes, so explicitly extend the low word of each D lane and + // use the equivalent D-offset intrinsic. + if extension != "" && indexBits == 64 { + narrowType := "" + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", narrow, indexType, indexValue, narrowType) + extended := c.newTmp() + opcode := "zext" + if extension == "sxtw" { + opcode = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s %s %%%s to %s\n", extended, opcode, narrowType, narrow, indexType) + indexValue = "%" + extended + extension = "" + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + loadedType := fmt.Sprintf("", lanes, spec.memoryBits) + suffix := "" + if extension != "" { + suffix = "." + extension + } + if byteScale > 1 && memory.Scale == byteScale { + suffix += ".index" + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ldff1.gather%s.nxv%di%d(%s %s, ptr %%%s, %s %s)\n", + loaded, loadedType, suffix, lanes, spec.memoryBits, predicateType, predicateValue, pointer, indexType, indexValue) + return c.finishARM64SVEFirstFaultLoad(spec, destination, elementBits, loadedType, "%"+loaded) +} + +func (c *arm64Ctx) lowerARM64SVEFirstFaultVectorBase(op Op, spec arm64SVEFirstFaultMemorySpec, memory MemRef, predicate, destination, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + base, baseBits, baseOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Base}) + alignment := int64(spec.memoryBits / 8) + maximum := int64(31) * alignment + if !baseOK || baseBits != elementBits || (elementBits != 32 && elementBits != 64) || memory.Index != "" || memory.IndexExt != "" || memory.Sym != "" || memory.Segment != "" || memory.OffRaw != "" || memory.Off < 0 || memory.Off > maximum || memory.Off%alignment != 0 { + return true, false, fmt.Errorf("arm64 %s vector-base offset must match the destination width, be aligned to %d, and be in [0,%d]: %q", op, alignment, maximum, ins.Raw) + } + baseValue, baseType, err := c.loadZRegElements(base, baseBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + loadedType := fmt.Sprintf("", lanes, spec.memoryBits) + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv%di%d.nxv%di%d(%s %s, %s %s, i64 %d)\n", + loaded, loadedType, lanes, spec.memoryBits, lanes, elementBits, predicateType, predicateValue, baseType, baseValue, memory.Off) + return c.finishARM64SVEFirstFaultLoad(spec, destination, elementBits, loadedType, "%"+loaded) +} + +func (c *arm64Ctx) finishARM64SVEFirstFaultLoad(spec arm64SVEFirstFaultMemorySpec, destination, elementBits int, loadedType, loaded string) (ok bool, terminated bool, err error) { + value := loaded + if spec.memoryBits < elementBits { + vectorType, _, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + extended := c.newTmp() + extension := "zext" + if spec.signed { + extension = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", extended, extension, loadedType, value, vectorType) + value = "%" + extended + } + return true, false, c.storeZRegElements(destination, elementBits, value) +} diff --git a/arm64_lower_sve_first_fault_memory_test.go b/arm64_lower_sve_first_fault_memory_test.go new file mode 100644 index 00000000..a760ec25 --- /dev/null +++ b/arm64_lower_sve_first_fault_memory_test.go @@ -0,0 +1,162 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEFirstFaultMemoryCompleteGo127Forms() string { + return `TEXT svefirstfaultmemoryforms(SB),$0-0 + ZLDFF1B (R7)(RSP), P4.Z, [Z13.B] + ZLDFF1B (R6)(R14), P4.Z, [Z13.H] + ZLDFF1B (R5)(R27), P3.Z, [Z6.S] + ZLDFF1B (R2)(R3), P2.Z, [Z24.D] + ZLDFF1B (Z10.D)(R19), P3.Z, [Z15.D] + ZLDFF1B (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLDFF1B (Z5.D.SXTW)(R12), P2.Z, [Z11.D] + ZLDFF1B (Z4.S.UXTW)(R3), P3.Z, [Z4.S] + ZLDFF1B (Z9.S.SXTW)(R8), P5.Z, [Z10.S] + ZLDFF1B (Z7.S), P4.Z, [Z13.S] + ZLDFF1B 31(Z7.D), P4.Z, [Z13.D] + + ZLDFF1H (R7<<1)(R14), P4.Z, [Z13.H] + ZLDFF1H (R6<<1)(R14), P4.Z, [Z13.S] + ZLDFF1H (R5<<1)(R27), P3.Z, [Z6.D] + ZLDFF1H (Z10.D)(RSP), P3.Z, [Z15.D] + ZLDFF1H (Z23.D<<1)(R24), P1.Z, [Z22.D] + ZLDFF1H (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLDFF1H (Z5.D.SXTW<<1)(R12), P2.Z, [Z11.D] + ZLDFF1H (Z4.S.UXTW)(R3), P3.Z, [Z4.S] + ZLDFF1H (Z9.S.SXTW<<1)(R8), P5.Z, [Z10.S] + ZLDFF1H (Z7.S), P4.Z, [Z13.S] + ZLDFF1H 62(Z7.D), P4.Z, [Z13.D] + + ZLDFF1W (R7<<2)(R14), P4.Z, [Z13.S] + ZLDFF1W (R6<<2)(R14), P4.Z, [Z13.D] + ZLDFF1W (Z10.D)(R19), P3.Z, [Z15.D] + ZLDFF1W (Z23.D<<2)(R24), P1.Z, [Z22.D] + ZLDFF1W (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLDFF1W (Z5.D.SXTW<<2)(R12), P2.Z, [Z11.D] + ZLDFF1W (Z4.S.UXTW)(R3), P3.Z, [Z4.S] + ZLDFF1W (Z9.S.SXTW<<2)(R8), P5.Z, [Z10.S] + ZLDFF1W (Z7.S), P4.Z, [Z13.S] + ZLDFF1W 124(Z7.D), P4.Z, [Z13.D] + + ZLDFF1D (R7<<3)(R14), P4.Z, [Z13.D] + ZLDFF1D (R6<<3)(R14), P4.Z, [Z13.D] + ZLDFF1D (Z10.D)(R19), P3.Z, [Z15.D] + ZLDFF1D (Z23.D<<3)(R24), P1.Z, [Z22.D] + ZLDFF1D (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLDFF1D (Z5.D.SXTW<<3)(R12), P2.Z, [Z11.D] + ZLDFF1D (Z7.D), P4.Z, [Z13.D] + ZLDFF1D 248(Z7.D), P4.Z, [Z13.D] + + ZLDFF1SB (R7)(R14), P4.Z, [Z13.H] + ZLDFF1SB (R6)(R14), P4.Z, [Z13.S] + ZLDFF1SB (R5)(R27), P3.Z, [Z6.D] + ZLDFF1SB (Z10.D)(R19), P3.Z, [Z15.D] + ZLDFF1SB (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLDFF1SB (Z5.D.SXTW)(R12), P2.Z, [Z11.D] + ZLDFF1SB (Z4.S.UXTW)(R3), P3.Z, [Z4.S] + ZLDFF1SB (Z9.S.SXTW)(R8), P5.Z, [Z10.S] + ZLDFF1SB (Z7.S), P4.Z, [Z13.S] + ZLDFF1SB 31(Z7.D), P4.Z, [Z13.D] + + ZLDFF1SH (R7<<1)(R14), P4.Z, [Z13.S] + ZLDFF1SH (R6<<1)(R14), P4.Z, [Z13.D] + ZLDFF1SH (Z10.D)(R19), P3.Z, [Z15.D] + ZLDFF1SH (Z23.D<<1)(R24), P1.Z, [Z22.D] + ZLDFF1SH (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLDFF1SH (Z5.D.SXTW<<1)(R12), P2.Z, [Z11.D] + ZLDFF1SH (Z4.S.UXTW)(R3), P3.Z, [Z4.S] + ZLDFF1SH (Z9.S.SXTW<<1)(R8), P5.Z, [Z10.S] + ZLDFF1SH (Z7.S), P4.Z, [Z13.S] + ZLDFF1SH 62(Z7.D), P4.Z, [Z13.D] + + ZLDFF1SW (R7<<2)(R14), P4.Z, [Z13.D] + ZLDFF1SW (R6<<2)(R14), P4.Z, [Z13.D] + ZLDFF1SW (Z10.D)(R19), P3.Z, [Z15.D] + ZLDFF1SW (Z23.D<<2)(R24), P1.Z, [Z22.D] + ZLDFF1SW (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLDFF1SW (Z5.D.SXTW<<2)(R12), P2.Z, [Z11.D] + ZLDFF1SW (Z7.D), P4.Z, [Z13.D] + ZLDFF1SW 124(Z7.D), P4.Z, [Z13.D] + RET +` +} + +func TestTranslateARM64SVEFirstFaultMemoryCompleteGo127Family(t *testing.T) { + source := arm64SVEFirstFaultMemoryCompleteGo127Forms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefirstfaultmemoryforms": {Name: "svefirstfaultmemoryforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.ldff1.nxv", + "@llvm.aarch64.sve.ldff1.gather.nxv", + "@llvm.aarch64.sve.ldff1.gather.index.nxv", + "@llvm.aarch64.sve.ldff1.gather.uxtw.nxv", + "@llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv", + "@llvm.aarch64.sve.ldff1.gather.sxtw.nxv", + "@llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv", + "@llvm.aarch64.sve.ldff1.gather.scalar.offset.", + " sext = 16 +} + +func (c *arm64Ctx) lowerARM64SVEFloatAddSub(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEFloatAddSubSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + + form := arm64SVEFloatAddSubForm{} + if len(ins.Args) == 3 { + second, secondBits, secondOK := arm64SVEFloatElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64SVEFloatElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + if !spec.unpredicated || !secondOK || !firstOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s does not accept this unpredicated floating vector form: %q", op, ins.Raw) + } + form = arm64SVEFloatAddSubForm{elementBits: firstBits, first: first, second: second, destination: destination} + } else if len(ins.Args) == 4 { + first, firstBits, firstOK := arm64SVEFloatElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[3]) + if !firstOK || !predicateOK || !destinationOK || first != destination || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s requires identical predicated destructive floating registers: %q", op, ins.Raw) + } + form = arm64SVEFloatAddSubForm{elementBits: firstBits, first: first, predicate: predicate, destination: destination, predicated: true} + if ins.Args[0].Kind == OpImm { + if ins.Args[0].ImmRaw != "" || !ins.Args[0].ImmIsFloat { + return true, false, fmt.Errorf("arm64 %s immediate requires $(0.5) or $(1.0): %q", op, ins.Raw) + } + form.immediate = math.Float64frombits(uint64(ins.Args[0].Imm)) + if form.immediate != 0.5 && form.immediate != 1.0 { + return true, false, fmt.Errorf("arm64 %s immediate requires $(0.5) or $(1.0): %q", op, ins.Raw) + } + form.hasImmediate = true + } else { + second, secondBits, secondOK := arm64SVEFloatElementReg(ins.Args[0]) + if !secondOK || secondBits != firstBits { + return true, false, fmt.Errorf("arm64 %s predicated source must match the destination element width: %q", op, ins.Raw) + } + form.second = second + } + } else { + return true, false, fmt.Errorf("arm64 %s expects one of its Go 1.27 SVE floating forms: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVEFloatAddSubForm(spec, form) +} + +func (c *arm64Ctx) lowerARM64SVEFloatAddSubForm(spec arm64SVEFloatAddSubSpec, form arm64SVEFloatAddSubForm) error { + first, vectorType, err := c.loadRawSVEFloatVector(form.first, form.elementBits) + if err != nil { + return err + } + second := "" + if form.hasImmediate { + integerType, lanes, err := arm64SVEVectorType(form.elementBits) + if err != nil { + return err + } + var bits uint64 + switch form.elementBits { + case 16: + bits = uint64(arm64Float16Bits(form.immediate)) + case 32: + bits = uint64(math.Float32bits(float32(form.immediate))) + case 64: + bits = math.Float64bits(form.immediate) + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s splat (i%d %d) to \n", converted, integerType, form.elementBits, bits, lanes, map[int]string{16: "half", 32: "float", 64: "double"}[form.elementBits]) + second = "%" + converted + } else { + second, _, err = c.loadRawSVEFloatVector(form.second, form.elementBits) + if err != nil { + return err + } + } + left, right := first, second + if spec.reverse { + left, right = right, left + } + calculated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", calculated, spec.operation, vectorType, left, right) + result := "%" + calculated + if form.predicated { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", selected, predicateType, predicate, vectorType, result, vectorType, first) + result = "%" + selected + } + return c.storeRawSVEFloatVector(form.destination, form.elementBits, result, vectorType) +} diff --git a/arm64_lower_sve_float_add_sub_test.go b/arm64_lower_sve_float_add_sub_test.go new file mode 100644 index 00000000..6246e463 --- /dev/null +++ b/arm64_lower_sve_float_add_sub_test.go @@ -0,0 +1,84 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEFloatAddSubForms(op string) string { + var source strings.Builder + function := "sve" + strings.ToLower(op) + "forms" + source.WriteString("TEXT " + function + "(SB),$0-0\n") + for index, width := range []string{"H", "S", "D"} { + predicate := string(rune('0' + index)) + if op != "ZFSUBR" { + source.WriteString("\t" + op + " Z1." + width + ", Z2." + width + ", Z3." + width + "\n") + } + source.WriteString("\t" + op + " Z4." + width + ", Z5." + width + ", P" + predicate + ".M, Z5." + width + "\n") + for _, immediate := range []string{"0.5", "1.0"} { + source.WriteString("\t" + op + " $(" + immediate + "), Z6." + width + ", P" + predicate + ".M, Z6." + width + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEFloatAddSubCompleteGo127Family(t *testing.T) { + for _, op := range []string{"ZFADD", "ZFSUB", "ZFSUBR"} { + t.Run(op, func(t *testing.T) { + source := arm64SVEFloatAddSubForms(op) + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "sve" + strings.ToLower(op) + "forms" + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + operation := "fadd" + if op != "ZFADD" { + operation = "fsub" + } + for _, want := range []string{`"target-features"="+sve"`, " " + operation + " maximumVector || lane > maximumLane || multiplierBits != multiplicandBits || multiplicandBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZFCMLA indexed operands must use an encodable H/S complex lane: %q", ins.Raw) + } + form.elementBits = multiplierBits + form.multiplier = multiplier + form.multiplicand = multiplicand + form.lane = lane + form.destination = destination + form.indexed = true + } + return true, false, c.lowerARM64SVEFloatComplexMultiplyAccumulateForm(form) +} + +func (c *arm64Ctx) lowerARM64SVEFloatComplexMultiplyAccumulateForm(form arm64SVEFloatComplexMultiplyAccumulateForm) error { + accumulator, vectorType, err := c.loadRawSVEFloatVector(form.destination, form.elementBits) + if err != nil { + return err + } + multiplicand, _, err := c.loadRawSVEFloatVector(form.multiplicand, form.elementBits) + if err != nil { + return err + } + multiplier, _, err := c.loadRawSVEFloatVector(form.multiplier, form.elementBits) + if err != nil { + return err + } + _, _, lanes, _ := arm64SVEFloatType(form.elementBits) + code := map[int]string{16: "f16", 32: "f32", 64: "f64"}[form.elementBits] + result := c.newTmp() + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fcmla.lane.nxv%d%s(%s %s, %s %s, %s %s, i32 %d, i32 %d)\n", + result, vectorType, lanes, code, vectorType, accumulator, vectorType, multiplicand, vectorType, multiplier, form.lane, form.rotation) + } else { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fcmla.nxv%d%s(%s %s, %s %s, %s %s, %s %s, i32 %d)\n", + result, vectorType, lanes, code, predicateType, predicate, vectorType, accumulator, vectorType, multiplicand, vectorType, multiplier, form.rotation) + } + return c.storeRawSVEFloatVector(form.destination, form.elementBits, "%"+result, vectorType) +} diff --git a/arm64_lower_sve_float_complex_multiply_accumulate_test.go b/arm64_lower_sve_float_complex_multiply_accumulate_test.go new file mode 100644 index 00000000..ef0f4995 --- /dev/null +++ b/arm64_lower_sve_float_complex_multiply_accumulate_test.go @@ -0,0 +1,80 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatComplexMultiplyAccumulateCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatcomplexmultiplyaccumulateforms(SB),$0-0\n") + for _, rotation := range []int{0, 90, 180, 270} { + for _, width := range []string{"H", "S", "D"} { + fmt.Fprintf(&source, "\tZFCMLA $%d, Z31.%s, Z2.%s, P7.M, Z3.%s\n", rotation, width, width, width) + } + fmt.Fprintf(&source, "\tZFCMLA $%d, Z7.H[3], Z4.H, Z5.H\n", rotation) + fmt.Fprintf(&source, "\tZFCMLA $%d, Z15.S[1], Z6.S, Z7.S\n", rotation) + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatcomplexmultiplyaccumulateforms": {Name: "svefloatcomplexmultiplyaccumulateforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.fcmla.nxv8f16", + "@llvm.aarch64.sve.fcmla.nxv2f64", + "@llvm.aarch64.sve.fcmla.lane.nxv8f16", + "@llvm.aarch64.sve.fcmla.lane.nxv4f32", + "i32 0", + "i32 270", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating complex multiply-accumulate lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-complex-multiply-accumulate.ll", "arm64-sve-float-complex-multiply-accumulate.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatComplexMultiplyAccumulateRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFCMLA $45, Z1.S, Z2.S, P0.M, Z3.S", + "ZFCMLA $0, Z1.B, Z2.B, P0.M, Z3.B", + "ZFCMLA $0, Z1.H, Z2.S, P0.M, Z3.S", + "ZFCMLA $0, Z1.S, Z2.S, P8.M, Z3.S", + "ZFCMLA $0, Z8.H[0], Z2.H, Z3.H", + "ZFCMLA $0, Z7.H[4], Z2.H, Z3.H", + "ZFCMLA $0, Z16.S[0], Z2.S, Z3.S", + "ZFCMLA $0, Z15.S[2], Z2.S, Z3.S", + "ZFCMLA $0, Z1.D[0], Z2.D, Z3.D", + "ZFCMLA.Z $0, Z1.S, Z2.S, P0.M, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatcomplexmultiplyaccumulate(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatcomplexmultiplyaccumulate": {Name: "badsvefloatcomplexmultiplyaccumulate", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ZFCMLA forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_divide_scale.go b/arm64_lower_sve_float_divide_scale.go new file mode 100644 index 00000000..07d5cf7b --- /dev/null +++ b/arm64_lower_sve_float_divide_scale.go @@ -0,0 +1,56 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEFloatDivideScale(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZFDIV" && op != "ZFDIVR" && op != "ZFSCALE" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects Zm.H|S|D, Zdn.H|S|D, P0..P7/M, Zdn.H|S|D without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64SVEFloatElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64SVEFloatElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || destinationBits != firstBits || destination != first { + return true, false, fmt.Errorf("arm64 %s requires matching-width destructive H/S/D operands and P0..P7/M: %q", op, ins.Raw) + } + firstValue, vectorType, err := c.loadRawSVEFloatVector(first, firstBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, firstBits) + if err != nil { + return true, false, err + } + _, _, lanes, err := arm64SVEFloatType(firstBits) + if err != nil { + return true, false, err + } + mangle := map[int]string{16: "f16", 32: "f32", 64: "f64"}[firstBits] + result := c.newTmp() + if op == "ZFSCALE" { + secondValue, integerType, err := c.loadZRegElements(second, secondBits) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fscale.nxv%d%s(%s %s, %s %s, %s %s)\n", result, vectorType, lanes, mangle, predicateType, predicateValue, vectorType, firstValue, integerType, secondValue) + } else { + secondValue, _, err := c.loadRawSVEFloatVector(second, secondBits) + if err != nil { + return true, false, err + } + intrinsic := "fdiv" + if op == "ZFDIVR" { + intrinsic = "fdivr" + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%d%s(%s %s, %s %s, %s %s)\n", result, vectorType, intrinsic, lanes, mangle, predicateType, predicateValue, vectorType, firstValue, vectorType, secondValue) + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %%%s, %s %s\n", selected, predicateType, predicateValue, vectorType, result, vectorType, firstValue) + return true, false, c.storeRawSVEFloatVector(destination, firstBits, "%"+selected, vectorType) +} diff --git a/arm64_lower_sve_float_divide_scale_test.go b/arm64_lower_sve_float_divide_scale_test.go new file mode 100644 index 00000000..bd0caa82 --- /dev/null +++ b/arm64_lower_sve_float_divide_scale_test.go @@ -0,0 +1,75 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatDivideScaleCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatdividescale(SB),$0-0\n") + for index, width := range []string{"H", "S", "D"} { + for opIndex, op := range []string{"ZFDIV", "ZFDIVR", "ZFSCALE"} { + destination := index*3 + opIndex + predicate := []int{0, 4, 7}[opIndex] + fmt.Fprintf(&source, "\t%s Z%d.%s, Z%d.%s, P%d.M, Z%d.%s\n", op, destination+16, width, destination, width, predicate, destination, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatdividescale": {Name: "svefloatdividescale", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.fdiv.nxv8f16", + "@llvm.aarch64.sve.fdiv.nxv4f32", + "@llvm.aarch64.sve.fdiv.nxv2f64", + "@llvm.aarch64.sve.fdivr.nxv8f16", + "@llvm.aarch64.sve.fscale.nxv8f16", + "@llvm.aarch64.sve.fscale.nxv2f64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating divide/scale lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-divide-scale.ll", "arm64-sve-float-divide-scale.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatDivideScaleRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFDIV Z1.B, Z2.B, P0.M, Z2.B", + "ZFDIV Z1.S, Z2.S, P8.M, Z2.S", + "ZFDIV Z1.S, Z2.S, P0.Z, Z2.S", + "ZFDIV Z1.S, Z2.S, P0.M, Z3.S", + "ZFDIVR Z1.H, Z2.S, P0.M, Z2.S", + "ZFSCALE Z1.D, Z2.D, P0, Z2.D", + "ZFSCALE.Z Z1.D, Z2.D, P0.M, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatdividescale(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatdividescale": {Name: "badsvefloatdividescale", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's floating divide/scale forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_exponent.go b/arm64_lower_sve_float_exponent.go new file mode 100644 index 00000000..0dfaf389 --- /dev/null +++ b/arm64_lower_sve_float_exponent.go @@ -0,0 +1,74 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEFloatExponent(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZFEXPA" && op != "ZFLOGB" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept a mnemonic suffix: %q", op, ins.Raw) + } + if op == "ZFEXPA" { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 ZFEXPA expects Zn.H|S|D, Zd.H|S|D: %q", ins.Raw) + } + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[1]) + if !sourceOK || !destinationOK || sourceBits == 8 || sourceBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZFEXPA requires matching H/S/D source and destination widths: %q", ins.Raw) + } + sourceValue, integerType, err := c.loadZRegElements(source, sourceBits) + if err != nil { + return true, false, err + } + _, floatingType, lanes, err := arm64SVEFloatType(sourceBits) + if err != nil { + return true, false, err + } + mangle := map[int]string{16: "f16", 32: "f32", 64: "f64"}[sourceBits] + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fexpa.x.nxv%d%s(%s %s)\n", result, floatingType, lanes, mangle, integerType, sourceValue) + return true, false, c.storeRawSVEFloatVector(destination, destinationBits, "%"+result, floatingType) + } + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 ZFLOGB expects Zn.H|S|D, Pg/M|Z, Zd.H|S|D: %q", ins.Raw) + } + source, sourceBits, sourceOK := arm64SVEFloatElementReg(ins.Args[0]) + mergePredicate, mergeOK := arm64ParseSVEPredicateMode(ins.Args[1], "M", 7) + zeroPredicate, zeroOK := arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !sourceOK || (!mergeOK && !zeroOK) || !destinationOK || sourceBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZFLOGB requires matching H/S/D operands and P0..P7/M|Z: %q", ins.Raw) + } + predicate := mergePredicate + if zeroOK { + predicate = zeroPredicate + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, sourceBits) + if err != nil { + return true, false, err + } + sourceValue, floatingType, err := c.loadRawSVEFloatVector(source, sourceBits) + if err != nil { + return true, false, err + } + passthrough := "zeroinitializer" + integerType, lanes, err := arm64SVEVectorType(destinationBits) + if err != nil { + return true, false, err + } + if mergeOK { + passthrough, _, err = c.loadZRegElements(destination, destinationBits) + if err != nil { + return true, false, err + } + } + mangle := map[int]string{16: "f16", 32: "f32", 64: "f64"}[sourceBits] + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.flogb.nxv%d%s(%s %s, %s %s, %s %s)\n", result, integerType, lanes, mangle, integerType, passthrough, predicateType, predicateValue, floatingType, sourceValue) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_float_exponent_test.go b/arm64_lower_sve_float_exponent_test.go new file mode 100644 index 00000000..3e14bf65 --- /dev/null +++ b/arm64_lower_sve_float_exponent_test.go @@ -0,0 +1,72 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatExponentCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatexponent(SB),$0-0\n") + for index, width := range []string{"H", "S", "D"} { + fmt.Fprintf(&source, "\tZFEXPA Z%d.%s, Z%d.%s\n", index, width, index+4, width) + fmt.Fprintf(&source, "\tZFLOGB Z%d.%s, P%d.M, Z%d.%s\n", index+8, width, index, index+12, width) + fmt.Fprintf(&source, "\tZFLOGB Z%d.%s, P%d.Z, Z%d.%s\n", index+16, width, index+3, index+20, width) + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatexponent": {Name: "svefloatexponent", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.fexpa.x.nxv8f16", + "@llvm.aarch64.sve.fexpa.x.nxv4f32", + "@llvm.aarch64.sve.fexpa.x.nxv2f64", + "@llvm.aarch64.sve.flogb.nxv8f16", + "@llvm.aarch64.sve.flogb.nxv2f64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating exponent lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-exponent.ll", "arm64-sve-float-exponent.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatExponentRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFEXPA Z1.B, Z2.B", + "ZFEXPA Z1.S, Z2.D", + "ZFLOGB Z1.B, P0.M, Z2.B", + "ZFLOGB Z1.S, P8.M, Z2.S", + "ZFLOGB Z1.S, P0, Z2.S", + "ZFLOGB Z1.S, P0.Z, Z2.D", + "ZFEXPA.Z Z1.D, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatexponent(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatexponent": {Name: "badsvefloatexponent", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's floating exponent forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_immediate.go b/arm64_lower_sve_float_immediate.go new file mode 100644 index 00000000..7ea3c55a --- /dev/null +++ b/arm64_lower_sve_float_immediate.go @@ -0,0 +1,73 @@ +package plan9asm + +import ( + "fmt" + "math" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEFloatImmediate(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZFCPY" && op != "ZFDUP" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept a mnemonic suffix: %q", op, ins.Raw) + } + wantArgs := 2 + if op == "ZFCPY" { + wantArgs = 3 + } + if len(ins.Args) != wantArgs || !arm64SVEFloatImmediateRepresentable(ins.Args[0]) { + return true, false, fmt.Errorf("arm64 %s requires an encodable floating immediate and its complete Go 1.27 operand form: %q", op, ins.Raw) + } + destinationOperand := ins.Args[wantArgs-1] + destination, elementBits, destinationOK := arm64SVEFloatElementReg(destinationOperand) + if !destinationOK { + return true, false, fmt.Errorf("arm64 %s destination must use H, S, or D elements: %q", op, ins.Raw) + } + value := math.Float64frombits(uint64(ins.Args[0].Imm)) + splat, err := c.arm64SVEFloatSplat(value, elementBits) + if err != nil { + return true, false, err + } + _, vectorType, _, err := arm64SVEFloatType(elementBits) + if err != nil { + return true, false, err + } + if op == "ZFDUP" { + return true, false, c.storeRawSVEFloatVector(destination, elementBits, splat, vectorType) + } + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[1], "M", 15) + if !predicateOK { + return true, false, fmt.Errorf("arm64 ZFCPY requires P0..P15/M: %q", ins.Raw) + } + oldDestination, _, err := c.loadRawSVEFloatVector(destination, elementBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", selected, predicateType, predicateValue, vectorType, splat, vectorType, oldDestination) + return true, false, c.storeRawSVEFloatVector(destination, elementBits, "%"+selected, vectorType) +} + +// arm64SVEFloatImmediateRepresentable mirrors Go's chipfloat7 acceptance +// check: one sign bit, a 3-bit exponent, and four fractional bits expanded to +// an exact binary64 value. That is the full 256-value immediate domain shared +// by ZFCPY and ZFDUP. +func arm64SVEFloatImmediateRepresentable(operand Operand) bool { + if operand.Kind != OpImm || operand.ImmRaw != "" || !operand.ImmIsFloat { + return false + } + bits := math.Float64bits(math.Float64frombits(uint64(operand.Imm))) + low := uint32(bits) + high := uint32(bits >> 32) + if low != 0 || high&0xffff != 0 { + return false + } + exponent := high & 0x7fc00000 + return exponent == 0x40000000 || exponent == 0x3fc00000 +} diff --git a/arm64_lower_sve_float_immediate_test.go b/arm64_lower_sve_float_immediate_test.go new file mode 100644 index 00000000..f330e387 --- /dev/null +++ b/arm64_lower_sve_float_immediate_test.go @@ -0,0 +1,107 @@ +package plan9asm + +import ( + "fmt" + "math" + "strconv" + "strings" + "testing" +) + +func TestARM64SVEFloatImmediateCompleteEncodingDomain(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatimmediatedomain(SB),$0-0\n") + count := 0 + for _, sign := range []float64{1, -1} { + for exponent := -3; exponent <= 4; exponent++ { + for numerator := 16; numerator <= 31; numerator++ { + value := math.Ldexp(sign*float64(numerator)/16, exponent) + operand := Operand{Kind: OpImm, Imm: int64(math.Float64bits(value)), ImmIsFloat: true} + if !arm64SVEFloatImmediateRepresentable(operand) { + t.Fatalf("representable ARM floating immediate rejected: %g", value) + } + literal := strconv.FormatFloat(value, 'g', -1, 64) + if !strings.ContainsAny(literal, ".eE") { + literal += ".0" + } + fmt.Fprintf(&source, "\tZFDUP $(%s), Z0.%s\n", literal, []string{"H", "S", "D"}[count%3]) + count++ + } + } + } + if count != 256 { + t.Fatalf("floating immediate domain has %d values, want 256", count) + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + for _, value := range []float64{0, 0.1, math.Inf(1), math.Inf(-1), math.NaN()} { + operand := Operand{Kind: OpImm, Imm: int64(math.Float64bits(value)), ImmIsFloat: true} + if arm64SVEFloatImmediateRepresentable(operand) { + t.Fatalf("non-encodable ARM floating immediate accepted: %g", value) + } + } +} + +func TestTranslateARM64SVEFloatImmediateCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatimmediate(SB),$0-0\n") + values := []string{"1.0", "-1.0", "0.5"} + for index, width := range []string{"H", "S", "D"} { + predicate := []int{0, 8, 15}[index] + fmt.Fprintf(&source, "\tZFCPY $(%s), P%d.M, Z%d.%s\n", values[index], predicate, index+4, width) + fmt.Fprintf(&source, "\tZFDUP $(%s), Z%d.%s\n", values[index], index+8, width) + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatimmediate": {Name: "svefloatimmediate", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "", + "", + "", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating immediate lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-immediate.ll", "arm64-sve-float-immediate.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatImmediateRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFCPY $(1.0), P0.M, Z1.B", + "ZFCPY $(1.0), P16.M, Z1.S", + "ZFCPY $(1.0), P0.Z, Z1.S", + "ZFCPY $(0.0), P0.M, Z1.S", + "ZFDUP $(1.0), Z1.B", + "ZFDUP $(0.0), Z1.S", + "ZFDUP.Z $(1.0), Z1.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatimmediate(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatimmediate": {Name: "badsvefloatimmediate", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's floating immediate forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_minmax.go b/arm64_lower_sve_float_minmax.go new file mode 100644 index 00000000..87dd5961 --- /dev/null +++ b/arm64_lower_sve_float_minmax.go @@ -0,0 +1,234 @@ +package plan9asm + +import ( + "fmt" + "math" + "strings" +) + +type arm64SVEFloatMinMaxKind uint8 + +const ( + arm64SVEFloatMinMaxDirect arm64SVEFloatMinMaxKind = iota + arm64SVEFloatMinMaxPairwise + arm64SVEFloatMinMaxReduce + arm64SVEFloatMinMaxQuadReduce +) + +type arm64SVEFloatMinMaxSpec struct { + intrinsic string + kind arm64SVEFloatMinMaxKind + elementBits int +} + +var arm64SVEFloatMinMaxSpecs = map[Op]arm64SVEFloatMinMaxSpec{ + "ZFMAX": {intrinsic: "fmax", kind: arm64SVEFloatMinMaxDirect}, + "ZFMAXP": {intrinsic: "fmaxp", kind: arm64SVEFloatMinMaxPairwise}, + "ZFMAXQV": {intrinsic: "fmaxqv", kind: arm64SVEFloatMinMaxQuadReduce}, + "ZFMAXVH": {intrinsic: "fmaxv", kind: arm64SVEFloatMinMaxReduce, elementBits: 16}, + "ZFMAXVS": {intrinsic: "fmaxv", kind: arm64SVEFloatMinMaxReduce, elementBits: 32}, + "ZFMAXVD": {intrinsic: "fmaxv", kind: arm64SVEFloatMinMaxReduce, elementBits: 64}, + "ZFMIN": {intrinsic: "fmin", kind: arm64SVEFloatMinMaxDirect}, + "ZFMINP": {intrinsic: "fminp", kind: arm64SVEFloatMinMaxPairwise}, + "ZFMINQV": {intrinsic: "fminqv", kind: arm64SVEFloatMinMaxQuadReduce}, + "ZFMINVH": {intrinsic: "fminv", kind: arm64SVEFloatMinMaxReduce, elementBits: 16}, + "ZFMINVS": {intrinsic: "fminv", kind: arm64SVEFloatMinMaxReduce, elementBits: 32}, + "ZFMINVD": {intrinsic: "fminv", kind: arm64SVEFloatMinMaxReduce, elementBits: 64}, + "ZFMAXNM": {intrinsic: "fmaxnm", kind: arm64SVEFloatMinMaxDirect}, + "ZFMAXNMP": {intrinsic: "fmaxnmp", kind: arm64SVEFloatMinMaxPairwise}, + "ZFMAXNMQV": {intrinsic: "fmaxnmqv", kind: arm64SVEFloatMinMaxQuadReduce}, + "ZFMAXNMVH": {intrinsic: "fmaxnmv", kind: arm64SVEFloatMinMaxReduce, elementBits: 16}, + "ZFMAXNMVS": {intrinsic: "fmaxnmv", kind: arm64SVEFloatMinMaxReduce, elementBits: 32}, + "ZFMAXNMVD": {intrinsic: "fmaxnmv", kind: arm64SVEFloatMinMaxReduce, elementBits: 64}, + "ZFMINNM": {intrinsic: "fminnm", kind: arm64SVEFloatMinMaxDirect}, + "ZFMINNMP": {intrinsic: "fminnmp", kind: arm64SVEFloatMinMaxPairwise}, + "ZFMINNMQV": {intrinsic: "fminnmqv", kind: arm64SVEFloatMinMaxQuadReduce}, + "ZFMINNMVH": {intrinsic: "fminnmv", kind: arm64SVEFloatMinMaxReduce, elementBits: 16}, + "ZFMINNMVS": {intrinsic: "fminnmv", kind: arm64SVEFloatMinMaxReduce, elementBits: 32}, + "ZFMINNMVD": {intrinsic: "fminnmv", kind: arm64SVEFloatMinMaxReduce, elementBits: 64}, +} + +type arm64SVEFloatMinMaxForm struct { + elementBits int + first int + second int + predicate int + destination int + immediate float64 + hasImmediate bool +} + +func (c *arm64Ctx) lowerARM64SVEFloatMinMax(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEFloatMinMaxSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + + switch spec.kind { + case arm64SVEFloatMinMaxDirect, arm64SVEFloatMinMaxPairwise: + form, err := arm64ParseSVEFloatMinMaxDirectForm(op, spec, ins) + if err != nil { + return true, false, err + } + return true, false, c.lowerARM64SVEFloatMinMaxDirectForm(spec, form) + case arm64SVEFloatMinMaxReduce, arm64SVEFloatMinMaxQuadReduce: + form, err := arm64ParseSVEFloatMinMaxReductionForm(op, spec, ins) + if err != nil { + return true, false, err + } + return true, false, c.lowerARM64SVEFloatMinMaxReductionForm(spec, form, ins.Args[2].Reg) + default: + return true, false, fmt.Errorf("arm64 %s has an unknown SVE floating min/max form", op) + } +} + +func arm64ParseSVEFloatMinMaxDirectForm(op Op, spec arm64SVEFloatMinMaxSpec, ins Instr) (arm64SVEFloatMinMaxForm, error) { + form := arm64SVEFloatMinMaxForm{} + if len(ins.Args) != 4 { + return form, fmt.Errorf("arm64 %s expects its four-operand predicated Go 1.27 form: %q", op, ins.Raw) + } + first, firstBits, firstOK := arm64SVEFloatElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[3]) + if !firstOK || !predicateOK || !destinationOK || first != destination || firstBits != destinationBits { + return form, fmt.Errorf("arm64 %s requires matching-width destructive registers and P0..P7/M: %q", op, ins.Raw) + } + form = arm64SVEFloatMinMaxForm{elementBits: firstBits, first: first, predicate: predicate, destination: destination} + if ins.Args[0].Kind == OpImm { + if spec.kind != arm64SVEFloatMinMaxDirect || ins.Args[0].ImmRaw != "" || !ins.Args[0].ImmIsFloat { + return form, fmt.Errorf("arm64 %s does not accept this floating immediate: %q", op, ins.Raw) + } + form.immediate = math.Float64frombits(uint64(ins.Args[0].Imm)) + if form.immediate != 0 && form.immediate != 1 { + return form, fmt.Errorf("arm64 %s immediate must be $(0.0) or $(1.0): %q", op, ins.Raw) + } + form.hasImmediate = true + return form, nil + } + second, secondBits, secondOK := arm64SVEFloatElementReg(ins.Args[0]) + if !secondOK || secondBits != firstBits { + return form, fmt.Errorf("arm64 %s vector operands must have identical H, S, or D widths: %q", op, ins.Raw) + } + form.second = second + return form, nil +} + +func arm64ParseSVEFloatMinMaxReductionForm(op Op, spec arm64SVEFloatMinMaxSpec, ins Instr) (arm64SVEFloatMinMaxForm, error) { + form := arm64SVEFloatMinMaxForm{} + if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { + return form, fmt.Errorf("arm64 %s expects Zn.T, Pg, Vd%s: %q", op, map[bool]string{true: ".T", false: ""}[spec.kind == arm64SVEFloatMinMaxQuadReduce], ins.Raw) + } + first, elementBits, firstOK := arm64SVEFloatElementReg(ins.Args[0]) + predicate, predicateOK := arm64ParseSVEPredicate(ins.Args[1]) + destination, destinationOK := arm64ParseVReg(ins.Args[2].Reg) + if !firstOK || !predicateOK || predicate > 7 || !destinationOK { + return form, fmt.Errorf("arm64 %s requires an H/S/D scalable source, bare P0..P7, and SIMD destination: %q", op, ins.Raw) + } + if spec.kind == arm64SVEFloatMinMaxReduce { + if strings.Contains(string(ins.Args[2].Reg), ".") { + return form, fmt.Errorf("arm64 %s destination must be a bare V register: %q", op, ins.Raw) + } + opcodeSize := map[int]int{16: 1, 32: 2, 64: 3}[spec.elementBits] + sourceSize := map[int]int{16: 1, 32: 2, 64: 3}[elementBits] + elementBits = 8 << (opcodeSize | sourceSize) + } else { + arrangement, arrangementOK := parseARM64VectorArrangement(ins.Args[2].Reg) + if !arrangementOK || arrangement.elementBits != elementBits || arrangement.lanes*arrangement.elementBits != 128 { + return form, fmt.Errorf("arm64 %s destination must be a full-width SIMD vector matching its source elements: %q", op, ins.Raw) + } + } + form = arm64SVEFloatMinMaxForm{elementBits: elementBits, first: first, predicate: predicate, destination: destination} + return form, nil +} + +func arm64SVEFloatType(elementBits int) (scalar, vector string, lanes int, err error) { + lanes = 128 / elementBits + scalar, ok := map[int]string{16: "half", 32: "float", 64: "double"}[elementBits] + if !ok { + return "", "", 0, fmt.Errorf("unsupported ARM64 SVE floating element width %d", elementBits) + } + return scalar, fmt.Sprintf("", lanes, scalar), lanes, nil +} + +func (c *arm64Ctx) arm64SVEFloatSplat(value float64, elementBits int) (string, error) { + integerType, _, err := arm64SVEVectorType(elementBits) + if err != nil { + return "", err + } + _, vectorType, _, err := arm64SVEFloatType(elementBits) + if err != nil { + return "", err + } + var bits uint64 + switch elementBits { + case 16: + bits = uint64(arm64Float16Bits(value)) + case 32: + bits = uint64(math.Float32bits(float32(value))) + case 64: + bits = math.Float64bits(value) + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s splat (i%d %d) to %s\n", converted, integerType, elementBits, bits, vectorType) + return "%" + converted, nil +} + +func (c *arm64Ctx) lowerARM64SVEFloatMinMaxDirectForm(spec arm64SVEFloatMinMaxSpec, form arm64SVEFloatMinMaxForm) error { + first, vectorType, err := c.loadRawSVEFloatVector(form.first, form.elementBits) + if err != nil { + return err + } + second := "" + if form.hasImmediate { + second, err = c.arm64SVEFloatSplat(form.immediate, form.elementBits) + } else { + second, _, err = c.loadRawSVEFloatVector(form.second, form.elementBits) + } + if err != nil { + return err + } + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + _, _, lanes, err := arm64SVEFloatType(form.elementBits) + if err != nil { + return err + } + calculated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%d%s(%s %s, %s %s, %s %s)\n", calculated, vectorType, spec.intrinsic, lanes, map[int]string{16: "f16", 32: "f32", 64: "f64"}[form.elementBits], predicateType, predicate, vectorType, first, vectorType, second) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %%%s, %s %s\n", selected, predicateType, predicate, vectorType, calculated, vectorType, first) + return c.storeRawSVEFloatVector(form.destination, form.elementBits, "%"+selected, vectorType) +} + +func (c *arm64Ctx) lowerARM64SVEFloatMinMaxReductionForm(spec arm64SVEFloatMinMaxSpec, form arm64SVEFloatMinMaxForm, destination Reg) error { + source, vectorType, err := c.loadRawSVEFloatVector(form.first, form.elementBits) + if err != nil { + return err + } + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + scalarType, _, lanes, err := arm64SVEFloatType(form.elementBits) + if err != nil { + return err + } + mangle := fmt.Sprintf("nxv%d%s", lanes, map[int]string{16: "f16", 32: "f32", 64: "f64"}[form.elementBits]) + result := c.newTmp() + if spec.kind == arm64SVEFloatMinMaxReduce { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.%s(%s %s, %s %s)\n", result, scalarType, spec.intrinsic, mangle, predicateType, predicate, vectorType, source) + fixed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x %s> zeroinitializer, %s %%%s, i32 0\n", fixed, lanes, scalarType, scalarType, result) + result = fixed + } else { + fmt.Fprintf(c.b, " %%%s = call <%d x %s> @llvm.aarch64.sve.%s.v%d%s.%s(%s %s, %s %s)\n", result, lanes, scalarType, spec.intrinsic, lanes, map[int]string{16: "f16", 32: "f32", 64: "f64"}[form.elementBits], mangle, predicateType, predicate, vectorType, source) + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x %s> %%%s to <16 x i8>\n", bytes, lanes, scalarType, result) + return c.storeVReg(destination, "%"+bytes) +} diff --git a/arm64_lower_sve_float_minmax_test.go b/arm64_lower_sve_float_minmax_test.go new file mode 100644 index 00000000..fc9b201b --- /dev/null +++ b/arm64_lower_sve_float_minmax_test.go @@ -0,0 +1,82 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEFloatMinMaxCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svefloatminmaxforms(SB),$0-0\n") + for _, base := range []string{"ZFMAX", "ZFMIN", "ZFMAXNM", "ZFMINNM"} { + for index, width := range []string{"H", "S", "D"} { + predicate := string(rune('0' + index)) + source.WriteString("\t" + base + " Z1." + width + ", Z2." + width + ", P" + predicate + ".M, Z2." + width + "\n") + for _, immediate := range []string{"0.0", "1.0"} { + source.WriteString("\t" + base + " $(" + immediate + "), Z3." + width + ", P" + predicate + ".M, Z3." + width + "\n") + } + source.WriteString("\t" + base + "P Z4." + width + ", Z5." + width + ", P" + predicate + ".M, Z5." + width + "\n") + for _, opcodeWidth := range []string{"H", "S", "D"} { + source.WriteString("\t" + base + "V" + opcodeWidth + " Z6." + width + ", P" + predicate + ", V7\n") + } + arrangement := map[string]string{"H": "H8", "S": "S4", "D": "D2"}[width] + source.WriteString("\t" + base + "QV Z8." + width + ", P" + predicate + ", V9." + arrangement + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEFloatMinMaxCompleteGo127Family(t *testing.T) { + source := arm64SVEFloatMinMaxCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatminmaxforms": {Name: "svefloatminmaxforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2,+sve2p1"`, "@llvm.aarch64.sve.fmax.nxv", "@llvm.aarch64.sve.fminnmp.nxv", "@llvm.aarch64.sve.fmaxnmv.nxv", "@llvm.aarch64.sve.fminqv."} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating min/max lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-minmax.ll", "arm64-sve-float-minmax.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatMinMaxRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFMAX $(0.5), Z1.S, P0.M, Z1.S", + "ZFMIN Z1.B, Z2.B, P0.M, Z2.B", + "ZFMAXNM Z1.S, Z2.D, P0.M, Z2.D", + "ZFMINNM Z1.S, Z2.S, P0.M, Z3.S", + "ZFMAXP Z1.S, Z2.S, P0.Z, Z2.S", + "ZFMINVH Z1.S, P8, V2", + "ZFMAXNMVS Z1.S, P0, V2.S4", + "ZFMINNMQV Z1.S, P0, V2.H8", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatminmax(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatminmax": {Name: "badsvefloatminmax", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE floating min/max forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_multiply.go b/arm64_lower_sve_float_multiply.go new file mode 100644 index 00000000..b49d3122 --- /dev/null +++ b/arm64_lower_sve_float_multiply.go @@ -0,0 +1,116 @@ +package plan9asm + +import ( + "fmt" + "math" + "strings" +) + +type arm64SVEFloatMultiplyForm struct { + elementBits int + first int + second int + predicate int + laneVector int + lane int + destination int + immediate float64 + hasImmediate bool + hasLane bool + predicated bool +} + +func (c *arm64Ctx) lowerARM64SVEFloatMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZFMUL" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || (len(ins.Args) != 3 && len(ins.Args) != 4) { + return true, false, fmt.Errorf("arm64 ZFMUL expects one complete Go 1.27 floating form without a suffix: %q", ins.Raw) + } + form := arm64SVEFloatMultiplyForm{} + if len(ins.Args) == 4 { + first, elementBits, firstOK := arm64SVEFloatElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[3]) + if !firstOK || !predicateOK || !destinationOK || first != destination || elementBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZFMUL predicated form requires matching destructive H/S/D operands and P0..P7.M: %q", ins.Raw) + } + form = arm64SVEFloatMultiplyForm{elementBits: elementBits, first: first, predicate: predicate, destination: destination, predicated: true} + if ins.Args[0].Kind == OpImm { + if ins.Args[0].ImmRaw != "" || !ins.Args[0].ImmIsFloat { + return true, false, fmt.Errorf("arm64 ZFMUL immediate requires $(0.5) or $(2.0): %q", ins.Raw) + } + form.immediate = math.Float64frombits(uint64(ins.Args[0].Imm)) + if form.immediate != 0.5 && form.immediate != 2.0 { + return true, false, fmt.Errorf("arm64 ZFMUL immediate requires $(0.5) or $(2.0): %q", ins.Raw) + } + form.hasImmediate = true + } else { + second, secondBits, secondOK := arm64SVEFloatElementReg(ins.Args[0]) + if !secondOK || secondBits != elementBits { + return true, false, fmt.Errorf("arm64 ZFMUL predicated source must match the destination width: %q", ins.Raw) + } + form.second = second + } + } else { + first, elementBits, firstOK := arm64SVEFloatElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + if !firstOK || !destinationOK || elementBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZFMUL unpredicated operands must use one H/S/D width: %q", ins.Raw) + } + form = arm64SVEFloatMultiplyForm{elementBits: elementBits, first: first, destination: destination} + if laneVector, laneBits, lane, laneOK := arm64ParseSVEZIndexedElementReg(ins.Args[0]); laneOK { + if laneBits != elementBits { + return true, false, fmt.Errorf("arm64 ZFMUL lane width must match the other operands: %q", ins.Raw) + } + form.laneVector, form.lane, form.hasLane = laneVector, lane, true + } else { + second, secondBits, secondOK := arm64SVEFloatElementReg(ins.Args[0]) + if !secondOK || secondBits != elementBits { + return true, false, fmt.Errorf("arm64 ZFMUL vector sources must use one H/S/D width: %q", ins.Raw) + } + form.second = second + } + } + return true, false, c.lowerARM64SVEFloatMultiplyForm(form) +} + +func (c *arm64Ctx) lowerARM64SVEFloatMultiplyForm(form arm64SVEFloatMultiplyForm) error { + first, vectorType, err := c.loadRawSVEFloatVector(form.first, form.elementBits) + if err != nil { + return err + } + result := c.newTmp() + if form.hasLane { + laneVector, _, err := c.loadRawSVEFloatVector(form.laneVector, form.elementBits) + if err != nil { + return err + } + _, _, lanes, _ := arm64SVEFloatType(form.elementBits) + code := map[int]string{16: "f16", 32: "f32", 64: "f64"}[form.elementBits] + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fmul.lane.nxv%d%s(%s %s, %s %s, i32 %d)\n", + result, vectorType, lanes, code, vectorType, first, vectorType, laneVector, form.lane) + } else { + second := "" + if form.hasImmediate { + second, err = c.arm64SVEFloatSplat(form.immediate, form.elementBits) + } else { + second, _, err = c.loadRawSVEFloatVector(form.second, form.elementBits) + } + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = fmul %s %s, %s\n", result, vectorType, first, second) + } + value := "%" + result + if form.predicated { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", selected, predicateType, predicate, vectorType, value, vectorType, first) + value = "%" + selected + } + return c.storeRawSVEFloatVector(form.destination, form.elementBits, value, vectorType) +} diff --git a/arm64_lower_sve_float_multiply_accumulate.go b/arm64_lower_sve_float_multiply_accumulate.go new file mode 100644 index 00000000..9dac4404 --- /dev/null +++ b/arm64_lower_sve_float_multiply_accumulate.go @@ -0,0 +1,102 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEFloatMultiplyAccumulateSpec struct { + intrinsic string + indexed bool +} + +var arm64SVEFloatMultiplyAccumulateSpecs = map[Op]arm64SVEFloatMultiplyAccumulateSpec{ + "ZFMLA": {intrinsic: "fmla", indexed: true}, + "ZFMLS": {intrinsic: "fmls", indexed: true}, + "ZFMAD": {intrinsic: "fmad"}, + "ZFMSB": {intrinsic: "fmsb"}, + "ZFNMLA": {intrinsic: "fnmla"}, + "ZFNMLS": {intrinsic: "fnmls"}, + "ZFNMAD": {intrinsic: "fnmad"}, + "ZFNMSB": {intrinsic: "fnmsb"}, +} + +type arm64SVEFloatMultiplyAccumulateForm struct { + intrinsic string + elementBits int + multiplier int + multiplicand int + predicate int + lane int + destination int + indexed bool +} + +func (c *arm64Ctx) lowerARM64SVEFloatMultiplyAccumulate(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEFloatMultiplyAccumulateSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 && (len(ins.Args) != 3 || !spec.indexed) { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 floating multiply-accumulate form without a suffix: %q", op, ins.Raw) + } + form := arm64SVEFloatMultiplyAccumulateForm{intrinsic: spec.intrinsic} + if len(ins.Args) == 4 { + multiplier, multiplierBits, multiplierOK := arm64SVEFloatElementReg(ins.Args[0]) + multiplicand, multiplicandBits, multiplicandOK := arm64SVEFloatElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[3]) + if !multiplierOK || !multiplicandOK || !predicateOK || !destinationOK || multiplierBits != multiplicandBits || multiplicandBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s predicated operands must use one H/S/D width and P0..P7.M: %q", op, ins.Raw) + } + form.elementBits = multiplierBits + form.multiplier = multiplier + form.multiplicand = multiplicand + form.predicate = predicate + form.destination = destination + } else { + multiplier, multiplierBits, lane, multiplierOK := arm64ParseSVEZIndexedElementReg(ins.Args[0]) + multiplicand, multiplicandBits, multiplicandOK := arm64SVEFloatElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + if !multiplierOK || !multiplicandOK || !destinationOK || multiplierBits != multiplicandBits || multiplicandBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s indexed operands must use one H/S/D width and an encodable lane: %q", op, ins.Raw) + } + form.elementBits = multiplierBits + form.multiplier = multiplier + form.multiplicand = multiplicand + form.lane = lane + form.destination = destination + form.indexed = true + } + return true, false, c.lowerARM64SVEFloatMultiplyAccumulateForm(form) +} + +func (c *arm64Ctx) lowerARM64SVEFloatMultiplyAccumulateForm(form arm64SVEFloatMultiplyAccumulateForm) error { + accumulator, vectorType, err := c.loadRawSVEFloatVector(form.destination, form.elementBits) + if err != nil { + return err + } + multiplicand, _, err := c.loadRawSVEFloatVector(form.multiplicand, form.elementBits) + if err != nil { + return err + } + multiplier, _, err := c.loadRawSVEFloatVector(form.multiplier, form.elementBits) + if err != nil { + return err + } + _, _, lanes, _ := arm64SVEFloatType(form.elementBits) + code := map[int]string{16: "f16", 32: "f32", 64: "f64"}[form.elementBits] + result := c.newTmp() + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.lane.nxv%d%s(%s %s, %s %s, %s %s, i32 %d)\n", + result, vectorType, form.intrinsic, lanes, code, vectorType, accumulator, vectorType, multiplicand, vectorType, multiplier, form.lane) + } else { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%d%s(%s %s, %s %s, %s %s, %s %s)\n", + result, vectorType, form.intrinsic, lanes, code, predicateType, predicate, vectorType, accumulator, vectorType, multiplicand, vectorType, multiplier) + } + return c.storeRawSVEFloatVector(form.destination, form.elementBits, "%"+result, vectorType) +} diff --git a/arm64_lower_sve_float_multiply_accumulate_test.go b/arm64_lower_sve_float_multiply_accumulate_test.go new file mode 100644 index 00000000..2855c740 --- /dev/null +++ b/arm64_lower_sve_float_multiply_accumulate_test.go @@ -0,0 +1,77 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatMultiplyAccumulateCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatmultiplyaccumulateforms(SB),$0-0\n") + for _, op := range []string{"ZFMLA", "ZFMLS"} { + for index, width := range []string{"H", "S", "D"} { + maximumVector := []int{7, 7, 15}[index] + maximumLane := []int{7, 3, 1}[index] + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, P%d.M, Z3.%s\n", op, width, width, index, width) + fmt.Fprintf(&source, "\t%s Z%d.%s[%d], Z4.%s, Z5.%s\n", op, maximumVector, width, maximumLane, width, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatmultiplyaccumulateforms": {Name: "svefloatmultiplyaccumulateforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.fmla.nxv8f16", + "@llvm.aarch64.sve.fmla.lane.nxv4f32", + "@llvm.aarch64.sve.fmls.nxv2f64", + "@llvm.aarch64.sve.fmls.lane.nxv8f16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating multiply-accumulate lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-multiply-accumulate.ll", "arm64-sve-float-multiply-accumulate.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatMultiplyAccumulateRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFMLA Z1.B, Z2.B, P0.M, Z3.B", + "ZFMLS Z1.H, Z2.S, P0.M, Z3.S", + "ZFMLA Z1.H, Z2.H, P0, Z3.H", + "ZFMLS Z1.S, Z2.S, P8.M, Z3.S", + "ZFMLA Z8.H[0], Z2.H, Z3.H", + "ZFMLS Z7.H[8], Z2.H, Z3.H", + "ZFMLA Z7.S[3], Z2.D, Z3.D", + "ZFMLS.Z Z1.S, Z2.S, P0.M, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatmultiplyaccumulate(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatmultiplyaccumulate": {Name: "badsvefloatmultiplyaccumulate", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE floating multiply-accumulate forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_multiply_addend_test.go b/arm64_lower_sve_float_multiply_addend_test.go new file mode 100644 index 00000000..d67ce72d --- /dev/null +++ b/arm64_lower_sve_float_multiply_addend_test.go @@ -0,0 +1,72 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatMultiplyAddendCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatmultiplyaddendforms(SB),$0-0\n") + for _, op := range []string{"ZFMAD", "ZFMSB", "ZFNMAD", "ZFNMSB"} { + for index, width := range []string{"H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, P%d.M, Z3.%s\n", op, width, width, index, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatmultiplyaddendforms": {Name: "svefloatmultiplyaddendforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.fmad.nxv8f16", + "@llvm.aarch64.sve.fmsb.nxv4f32", + "@llvm.aarch64.sve.fnmad.nxv2f64", + "@llvm.aarch64.sve.fnmsb.nxv8f16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating multiply-addend lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-multiply-addend.ll", "arm64-sve-float-multiply-addend.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatMultiplyAddendRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFMAD Z1.B, Z2.B, P0.M, Z3.B", + "ZFMSB Z1.H, Z2.S, P0.M, Z3.S", + "ZFNMAD Z1.H, Z2.H, P0, Z3.H", + "ZFNMSB Z1.S, Z2.S, P8.M, Z3.S", + "ZFMAD Z7.H[0], Z2.H, Z3.H", + "ZFMSB.Z Z1.S, Z2.S, P0.M, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatmultiplyaddend(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatmultiplyaddend": {Name: "badsvefloatmultiplyaddend", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE floating multiply-addend forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_multiply_extended.go b/arm64_lower_sve_float_multiply_extended.go new file mode 100644 index 00000000..251b39dd --- /dev/null +++ b/arm64_lower_sve_float_multiply_extended.go @@ -0,0 +1,40 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEFloatMultiplyExtended(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZFMULX" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 ZFMULX expects one complete Go 1.27 predicated form without a suffix: %q", ins.Raw) + } + second, secondBits, secondOK := arm64SVEFloatElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64SVEFloatElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits || first != destination { + return true, false, fmt.Errorf("arm64 ZFMULX requires matching destructive H/S/D operands and P0..P7.M: %q", ins.Raw) + } + firstValue, vectorType, err := c.loadRawSVEFloatVector(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadRawSVEFloatVector(second, firstBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, firstBits) + if err != nil { + return true, false, err + } + _, _, lanes, _ := arm64SVEFloatType(firstBits) + code := map[int]string{16: "f16", 32: "f32", 64: "f64"}[firstBits] + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fmulx.nxv%d%s(%s %s, %s %s, %s %s)\n", + result, vectorType, lanes, code, predicateType, predicateValue, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeRawSVEFloatVector(destination, firstBits, "%"+result, vectorType) +} diff --git a/arm64_lower_sve_float_multiply_extended_test.go b/arm64_lower_sve_float_multiply_extended_test.go new file mode 100644 index 00000000..b9913db4 --- /dev/null +++ b/arm64_lower_sve_float_multiply_extended_test.go @@ -0,0 +1,70 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatMultiplyExtendedCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatmultiplyextendedforms(SB),$0-0\n") + for index, width := range []string{"H", "S", "D"} { + fmt.Fprintf(&source, "\tZFMULX Z1.%s, Z2.%s, P%d.M, Z2.%s\n", width, width, index, width) + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatmultiplyextendedforms": {Name: "svefloatmultiplyextendedforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.fmulx.nxv8f16", + "@llvm.aarch64.sve.fmulx.nxv4f32", + "@llvm.aarch64.sve.fmulx.nxv2f64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating multiply-extended lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-multiply-extended.ll", "arm64-sve-float-multiply-extended.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatMultiplyExtendedRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFMULX Z1.B, Z2.B, P0.M, Z2.B", + "ZFMULX Z1.H, Z2.S, P0.M, Z2.S", + "ZFMULX Z1.S, Z2.S, P0, Z2.S", + "ZFMULX Z1.S, Z2.S, P8.M, Z2.S", + "ZFMULX Z1.S, Z2.S, P0.M, Z3.S", + "ZFMULX Z1.S, Z2.S, Z3.S", + "ZFMULX.Z Z1.S, Z2.S, P0.M, Z2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatmultiplyextended(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatmultiplyextended": {Name: "badsvefloatmultiplyextended", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ZFMULX forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_multiply_test.go b/arm64_lower_sve_float_multiply_test.go new file mode 100644 index 00000000..012c7867 --- /dev/null +++ b/arm64_lower_sve_float_multiply_test.go @@ -0,0 +1,81 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatMultiplyCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatmultiplyforms(SB),$0-0\n") + for index, width := range []string{"H", "S", "D"} { + maximumVector := []int{7, 7, 15}[index] + maximumLane := []int{7, 3, 1}[index] + fmt.Fprintf(&source, "\tZFMUL Z1.%s, Z2.%s, P%d.M, Z2.%s\n", width, width, index, width) + fmt.Fprintf(&source, "\tZFMUL Z3.%s, Z4.%s, Z5.%s\n", width, width, width) + fmt.Fprintf(&source, "\tZFMUL Z%d.%s[%d], Z6.%s, Z7.%s\n", maximumVector, width, maximumLane, width, width) + for _, immediate := range []string{"0.5", "2.0"} { + fmt.Fprintf(&source, "\tZFMUL $(%s), Z8.%s, P%d.M, Z8.%s\n", immediate, width, index, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatmultiplyforms": {Name: "svefloatmultiplyforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + " fmul %s)\n", result, destinationType, spec.intrinsic, suffix, sourceValue) + if spec.bfloat { + return true, false, c.storeARM64SVEBFloatVector(destination, "%"+result) + } + return true, false, c.storeRawSVEFloatVector(destination, 16, "%"+result, destinationType) +} + +func (c *arm64Ctx) lowerARM64SVEFloatNarrowPredicated(op Op, ins Instr) (bool, bool, error) { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zn.S|D, P0..P7/M|Z, Zd.H|S: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64SVEFloatElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + predicate, mergeOK := arm64ParseSVEPredicateMode(ins.Args[1], "M", 7) + zeroing := false + if !mergeOK { + predicate, zeroing = arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + } + validWidths := sourceBits == 32 && destinationBits == 16 + if op == "ZFCVTNT" { + validWidths = validWidths || sourceBits == 64 && destinationBits == 32 + } + if !sourceOK || !destinationOK || (!mergeOK && !zeroing) || !validWidths || (op != "ZBFCVT" && op != "ZBFCVTNT" && op != "ZFCVTNT") { + return true, false, fmt.Errorf("arm64 %s operands are outside its complete Go 1.27 predicated narrowing forms: %q", op, ins.Raw) + } + sourceValue, sourceType, err := c.loadRawSVEFloatVector(source, sourceBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, sourceBits) + if err != nil { + return true, false, err + } + destinationType := map[int]string{16: "", 32: ""}[destinationBits] + mergeValue := "zeroinitializer" + intrinsic := "fcvt.f16f32" + bfloat := op == "ZBFCVT" || op == "ZBFCVTNT" + if bfloat { + destinationType = "" + intrinsic = "fcvt.bf16f32.v2" + } + keepDestination := mergeOK || op == "ZBFCVTNT" || op == "ZFCVTNT" + if keepDestination { + if bfloat { + mergeValue, err = c.loadARM64SVEBFloatVector(destination) + } else { + mergeValue, _, err = c.loadRawSVEFloatVector(destination, destinationBits) + } + if err != nil { + return true, false, err + } + } + if op == "ZBFCVTNT" { + intrinsic = "fcvtnt.bf16f32.v2" + if zeroing { + intrinsic = "fcvtnt.z.bf16f32" + } + } else if op == "ZFCVTNT" { + intrinsic = map[[2]int]string{{32, 16}: "fcvtnt.f16f32", {64, 32}: "fcvtnt.f32f64"}[[2]int{sourceBits, destinationBits}] + if zeroing { + intrinsic = strings.Replace(intrinsic, "fcvtnt.", "fcvtnt.z.", 1) + } + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s(%s %s, %s %s, %s %s)\n", result, destinationType, intrinsic, destinationType, mergeValue, predicateType, predicateValue, sourceType, sourceValue) + if bfloat { + return true, false, c.storeARM64SVEBFloatVector(destination, "%"+result) + } + return true, false, c.storeRawSVEFloatVector(destination, destinationBits, "%"+result, destinationType) +} + +func (c *arm64Ctx) lowerARM64SVEFP8NarrowPair(op Op, ins Instr) (bool, bool, error) { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects one x2 range and one B destination: %q", op, ins.Raw) + } + first, second, sourceBits, sourceOK := arm64ParseSVEEvenVectorPair(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[1]) + wantBits := 16 + if op == "ZFCVTNB" || op == "ZFCVTNT" { + wantBits = 32 + } + if !sourceOK || !destinationOK || sourceBits != wantBits || destinationBits != 8 || (op != "ZBFCVTN" && op != "ZFCVTN" && op != "ZFCVTNB" && op != "ZFCVTNT") { + return true, false, fmt.Errorf("arm64 %s requires its exact even/odd x2 floating range and B destination: %q", op, ins.Raw) + } + var firstValue, secondValue, sourceType string + var err error + if op == "ZBFCVTN" { + firstValue, err = c.loadARM64SVEBFloatVector(first) + if err == nil { + secondValue, err = c.loadARM64SVEBFloatVector(second) + } + sourceType = "" + } else { + firstValue, sourceType, err = c.loadRawSVEFloatVector(first, sourceBits) + if err == nil { + secondValue, _, err = c.loadRawSVEFloatVector(second, sourceBits) + } + } + if err != nil { + return true, false, err + } + intrinsic := map[Op]string{ + "ZBFCVTN": "cvtn.nxv8bf16", + "ZFCVTN": "cvtn.nxv8f16", + "ZFCVTNB": "cvtnb.nxv4f32", + "ZFCVTNT": "cvtnt.nxv4f32", + }[op] + result := c.newTmp() + if op == "ZFCVTNT" { + oldDestination, err := c.loadZReg(destination) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.fp8.%s( %s, %s %s, %s %s)\n", result, intrinsic, oldDestination, sourceType, firstValue, sourceType, secondValue) + } else { + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.fp8.%s(%s %s, %s %s)\n", result, intrinsic, sourceType, firstValue, sourceType, secondValue) + } + return true, false, c.storeZReg(destination, "%"+result) +} + +func (c *arm64Ctx) loadARM64SVEBFloatVector(register int) (string, error) { + integer, integerType, err := c.loadZRegElements(register, 16) + if err != nil { + return "", err + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to \n", converted, integerType, integer) + return "%" + converted, nil +} + +func (c *arm64Ctx) storeARM64SVEBFloatVector(register int, value string) error { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s to \n", converted, value) + return c.storeZRegElements(register, 16, "%"+converted) +} + +func emitARM64SVEFloatNarrowConversionDeclarations(b *strings.Builder) { + for _, intrinsic := range []string{"cvt1", "cvtlt1", "cvt2", "cvtlt2"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.fp8.%s.nxv8f16()\n", intrinsic) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.fp8.%s.nxv8bf16()\n", intrinsic) + } + b.WriteString("declare @llvm.aarch64.sve.fcvt.bf16f32.v2(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fcvtnt.bf16f32.v2(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fcvtnt.z.bf16f32(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fcvtnt.f16f32(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fcvtnt.z.f16f32(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fcvtnt.f32f64(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fcvtnt.z.f32f64(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(, )\n") + b.WriteString("declare @llvm.aarch64.sve.fp8.cvtn.nxv8f16(, )\n") + b.WriteString("declare @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(, )\n") + b.WriteString("declare @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(, , )\n") +} diff --git a/arm64_lower_sve_float_narrow_conversion_test.go b/arm64_lower_sve_float_narrow_conversion_test.go new file mode 100644 index 00000000..95cfa328 --- /dev/null +++ b/arm64_lower_sve_float_narrow_conversion_test.go @@ -0,0 +1,145 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatNarrowConversionCompleteGo127Family(t *testing.T) { + const source = `TEXT svefloatnarrowcvt(SB),$0-0 + ZBF1CVT Z0.B, Z1.H + ZBF1CVTLT Z2.B, Z3.H + ZBF2CVT Z4.B, Z5.H + ZBF2CVTLT Z6.B, Z7.H + ZF1CVT Z8.B, Z9.H + ZF1CVTLT Z10.B, Z11.H + ZF2CVT Z12.B, Z13.H + ZF2CVTLT Z14.B, Z15.H + ZBFCVT Z16.S, P0.M, Z17.H + ZBFCVT Z18.S, P7.Z, Z19.H + ZBFCVTNT Z20.S, P1.M, Z21.H + ZBFCVTNT Z22.S, P6.Z, Z23.H + ZBFCVTN [Z0.H-Z1.H], Z24.B + ZFCVTNT Z2.S, P2.M, Z3.H + ZFCVTNT Z4.S, P5.Z, Z5.H + ZFCVTNT Z6.D, P3.M, Z7.S + ZFCVTNT Z8.D, P4.Z, Z9.S + ZFCVTN [Z10.H-Z11.H], Z25.B + ZFCVTNB [Z12.S-Z13.S], Z26.B + ZFCVTNT [Z30.S-Z31.S], Z27.B + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatnarrowcvt": {Name: "svefloatnarrowcvt", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+bf16,+fp8,+sve,+sve2,+sve2p2"`, + "= call @llvm.aarch64.sve.fp8.cvt1.nxv8bf16", + "= call @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16", + "= call @llvm.aarch64.sve.fp8.cvt2.nxv8bf16", + "= call @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16", + "= call @llvm.aarch64.sve.fp8.cvt1.nxv8f16", + "= call @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16", + "= call @llvm.aarch64.sve.fp8.cvt2.nxv8f16", + "= call @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16", + "= call @llvm.aarch64.sve.fcvt.bf16f32.v2", + "= call @llvm.aarch64.sve.fcvtnt.bf16f32.v2", + "= call @llvm.aarch64.sve.fcvtnt.z.bf16f32", + "= call @llvm.aarch64.sve.fcvtnt.f16f32", + "= call @llvm.aarch64.sve.fcvtnt.z.f16f32", + "= call @llvm.aarch64.sve.fcvtnt.f32f64", + "= call @llvm.aarch64.sve.fcvtnt.z.f32f64", + "= call @llvm.aarch64.sve.fp8.cvtn.nxv8bf16", + "= call @llvm.aarch64.sve.fp8.cvtn.nxv8f16", + "= call @llvm.aarch64.sve.fp8.cvtnb.nxv4f32", + "= call @llvm.aarch64.sve.fp8.cvtnt.nxv4f32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s floating narrowing conversion lowering omitted actual call %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-narrow-conversion.ll", "arm64-sve-float-narrow-conversion.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatNarrowConversionRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZBF1CVT Z0.H, Z1.H", + "ZBF1CVTLT Z0.B, Z1.S", + "ZF2CVT Z0.B, Z1.D", + "ZBFCVT Z0.S, P8.M, Z1.H", + "ZBFCVTNT Z0.D, P0.M, Z1.S", + "ZFCVTNT Z0.H, P0.Z, Z1.B", + "ZBFCVTN [Z1.H-Z2.H], Z3.B", + "ZFCVTN [Z2.H, Z3.H], Z4.B", + "ZFCVTNB [Z2.H-Z3.H], Z4.B", + "ZFCVTNT [Z2.S-Z3.S], Z4.H", + "ZF1CVT.Z Z0.B, Z1.H", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatnarrowcvt(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatnarrowcvt": {Name: "badsvefloatnarrowcvt", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's floating narrowing conversion forms", instruction) + } + }) + } +} + +func TestTranslateARM64SVEFloatNarrowConversionInfersEachFeatureClass(t *testing.T) { + classes := []struct { + name string + source string + features string + }{ + {name: "fp8-to-bf16", source: "ZBF1CVT Z0.B, Z1.H", features: "+fp8,+sve,+sve2,+sve2p2"}, + {name: "bf16-predicated", source: "ZBFCVTNT Z0.S, P0.M, Z1.H", features: "+bf16,+sve"}, + {name: "sve2-merging-top-narrow", source: "ZFCVTNT Z0.D, P0.M, Z1.S", features: "+sve,+sve2"}, + {name: "sve2p2-zeroing-top-narrow", source: "ZFCVTNT Z0.D, P0.Z, Z1.S", features: "+sve,+sve2,+sve2p2"}, + {name: "bf16-to-fp8", source: "ZBFCVTN [Z0.H-Z1.H], Z2.B", features: "+fp8,+sve,+sve2,+sve2p2"}, + } + for _, class := range classes { + t.Run(class.name, func(t *testing.T) { + source := "TEXT onefeatureclass(SB),$0-0\n\t" + class.source + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"onefeatureclass": {Name: "onefeatureclass", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + want := `"target-features"="` + class.features + `"` + if !strings.Contains(ll, want) { + t.Fatalf("%s feature inference omitted %q for %s:\n%s", triple, want, class.source, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-narrow-feature.ll", "arm64-sve-float-narrow-feature.o", ll) + }) + } + }) + } +} diff --git a/arm64_lower_sve_float_negative_multiply_accumulate_test.go b/arm64_lower_sve_float_negative_multiply_accumulate_test.go new file mode 100644 index 00000000..7149acad --- /dev/null +++ b/arm64_lower_sve_float_negative_multiply_accumulate_test.go @@ -0,0 +1,71 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatNegativeMultiplyAccumulateCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatnegativemultiplyaccumulateforms(SB),$0-0\n") + for _, op := range []string{"ZFNMLA", "ZFNMLS"} { + for index, width := range []string{"H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, P%d.M, Z3.%s\n", op, width, width, index, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatnegativemultiplyaccumulateforms": {Name: "svefloatnegativemultiplyaccumulateforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.fnmla.nxv8f16", + "@llvm.aarch64.sve.fnmla.nxv4f32", + "@llvm.aarch64.sve.fnmls.nxv2f64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating negative multiply-accumulate lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-negative-multiply-accumulate.ll", "arm64-sve-float-negative-multiply-accumulate.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatNegativeMultiplyAccumulateRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFNMLA Z1.B, Z2.B, P0.M, Z3.B", + "ZFNMLS Z1.H, Z2.S, P0.M, Z3.S", + "ZFNMLA Z1.H, Z2.H, P0, Z3.H", + "ZFNMLS Z1.S, Z2.S, P8.M, Z3.S", + "ZFNMLA Z7.H[0], Z2.H, Z3.H", + "ZFNMLS.Z Z1.S, Z2.S, P0.M, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatnegativemultiplyaccumulate(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatnegativemultiplyaccumulate": {Name: "badsvefloatnegativemultiplyaccumulate", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE floating negative multiply-accumulate forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_predicated_pairwise.go b/arm64_lower_sve_float_predicated_pairwise.go new file mode 100644 index 00000000..c40950fa --- /dev/null +++ b/arm64_lower_sve_float_predicated_pairwise.go @@ -0,0 +1,56 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEFloatPredicatedPairwiseSpec struct { + intrinsic string + sve2 bool + faminmax bool +} + +var arm64SVEFloatPredicatedPairwiseSpecs = map[Op]arm64SVEFloatPredicatedPairwiseSpec{ + "ZFABD": {intrinsic: "fabd"}, + "ZFADDP": {intrinsic: "faddp", sve2: true}, + "ZFAMAX": {intrinsic: "famax", sve2: true, faminmax: true}, + "ZFAMIN": {intrinsic: "famin", sve2: true, faminmax: true}, +} + +func (c *arm64Ctx) lowerARM64SVEFloatPredicatedPairwise(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEFloatPredicatedPairwiseSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects Zm.H|S|D, Zdn.H|S|D, Pg/M, Zdn.H|S|D without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64SVEFloatElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + repeatedDestination, repeatedBits, repeatedOK := arm64SVEFloatElementReg(ins.Args[3]) + if !secondOK || !destinationOK || !predicateOK || !repeatedOK || secondBits != destinationBits || repeatedBits != destinationBits || repeatedDestination != destination { + return true, false, fmt.Errorf("arm64 %s requires matching destructive H/S/D operands and P0..P7/M: %q", op, ins.Raw) + } + destinationValue, vectorType, err := c.loadRawSVEFloatVector(destination, destinationBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadRawSVEFloatVector(second, secondBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, destinationBits) + if err != nil { + return true, false, err + } + _, _, lanes, err := arm64SVEFloatType(destinationBits) + if err != nil { + return true, false, err + } + mangle := map[int]string{16: "f16", 32: "f32", 64: "f64"}[destinationBits] + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%d%s(%s %s, %s %s, %s %s)\n", result, vectorType, spec.intrinsic, lanes, mangle, predicateType, predicateValue, vectorType, destinationValue, vectorType, secondValue) + return true, false, c.storeRawSVEFloatVector(destination, destinationBits, "%"+result, vectorType) +} diff --git a/arm64_lower_sve_float_predicated_pairwise_test.go b/arm64_lower_sve_float_predicated_pairwise_test.go new file mode 100644 index 00000000..f64bea6d --- /dev/null +++ b/arm64_lower_sve_float_predicated_pairwise_test.go @@ -0,0 +1,71 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatPredicatedPairwiseCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatpredicatedpairwise(SB),$0-0\n") + for opIndex, op := range []string{"ZFABD", "ZFADDP", "ZFAMAX", "ZFAMIN"} { + for widthIndex, width := range []string{"H", "S", "D"} { + destination := opIndex*3 + widthIndex + fmt.Fprintf(&source, "\t%s Z%d.%s, Z%d.%s, P%d.M, Z%d.%s\n", op, (destination+1)%32, width, destination, width, (opIndex+widthIndex)%8, destination, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatpredicatedpairwise": {Name: "svefloatpredicatedpairwise", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+faminmax,+sve,+sve2"`, + "@llvm.aarch64.sve.fabd.nxv8f16", + "@llvm.aarch64.sve.faddp.nxv4f32", + "@llvm.aarch64.sve.famax.nxv2f64", + "@llvm.aarch64.sve.famin.nxv8f16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicated floating pairwise lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-predicated-pairwise.ll", "arm64-sve-float-predicated-pairwise.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatPredicatedPairwiseRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFABD Z1.B, Z2.B, P0.M, Z2.B", + "ZFADDP Z1.H, Z2.S, P0.M, Z2.S", + "ZFAMAX Z1.S, Z2.S, P8.M, Z2.S", + "ZFAMIN Z1.D, Z2.D, P0.Z, Z2.D", + "ZFABD Z1.S, Z2.S, P0.M, Z3.S", + "ZFADDP.Z Z1.D, Z2.D, P0.M, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatpredicatedpairwise(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatpredicatedpairwise": {Name: "badsvefloatpredicatedpairwise", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's predicated floating pairwise forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_reciprocal_step.go b/arm64_lower_sve_float_reciprocal_step.go new file mode 100644 index 00000000..0f98db87 --- /dev/null +++ b/arm64_lower_sve_float_reciprocal_step.go @@ -0,0 +1,43 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEFloatReciprocalStepIntrinsics = map[Op]string{ + "ZFRECPS": "frecps.x", + "ZFRSQRTS": "frsqrts.x", +} + +func (c *arm64Ctx) lowerARM64SVEFloatReciprocalStep(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEFloatReciprocalStepIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zm.H|S|D, Zn.H|S|D, Zd.H|S|D without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64SVEFloatElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64SVEFloatElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s requires three matching H/S/D scalable floating-vector operands: %q", op, ins.Raw) + } + firstValue, vectorType, err := c.loadRawSVEFloatVector(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadRawSVEFloatVector(second, secondBits) + if err != nil { + return true, false, err + } + _, _, lanes, err := arm64SVEFloatType(firstBits) + if err != nil { + return true, false, err + } + mangle := map[int]string{16: "f16", 32: "f32", 64: "f64"}[firstBits] + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%d%s(%s %s, %s %s)\n", result, vectorType, intrinsic, lanes, mangle, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeRawSVEFloatVector(destination, destinationBits, "%"+result, vectorType) +} diff --git a/arm64_lower_sve_float_reciprocal_step_test.go b/arm64_lower_sve_float_reciprocal_step_test.go new file mode 100644 index 00000000..1799e21e --- /dev/null +++ b/arm64_lower_sve_float_reciprocal_step_test.go @@ -0,0 +1,70 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatReciprocalStepCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloatreciprocalstep(SB),$0-0\n") + for opIndex, op := range []string{"ZFRECPS", "ZFRSQRTS"} { + for widthIndex, width := range []string{"H", "S", "D"} { + reg := opIndex*3 + widthIndex + fmt.Fprintf(&source, "\t%s Z%d.%s, Z%d.%s, Z%d.%s\n", op, reg, width, reg+1, width, reg+2, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatreciprocalstep": {Name: "svefloatreciprocalstep", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.frecps.x.nxv8f16", + "@llvm.aarch64.sve.frecps.x.nxv4f32", + "@llvm.aarch64.sve.frsqrts.x.nxv2f64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating reciprocal-step lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-reciprocal-step.ll", "arm64-sve-float-reciprocal-step.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatReciprocalStepRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFRECPS Z1.B, Z2.B, Z3.B", + "ZFRECPS Z1.H, Z2.S, Z3.S", + "ZFRSQRTS Z1.S, Z2.S, Z3.D", + "ZFRSQRTS Z1.Q, Z2.Q, Z3.Q", + "ZFRECPS Z1.S, Z2.S", + "ZFRSQRTS.Z Z1.D, Z2.D, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatreciprocalstep(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatreciprocalstep": {Name: "badsvefloatreciprocalstep", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's floating reciprocal-step forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_trig_multiply.go b/arm64_lower_sve_float_trig_multiply.go new file mode 100644 index 00000000..3119e729 --- /dev/null +++ b/arm64_lower_sve_float_trig_multiply.go @@ -0,0 +1,41 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEFloatTrigIntrinsics = map[Op]string{ + "ZFTSMUL": "ftsmul", + "ZFTSSEL": "ftssel", +} + +func (c *arm64Ctx) lowerARM64SVEFloatTrigMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEFloatTrigIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 vector form without a suffix: %q", op, ins.Raw) + } + control, controlBits, controlOK := arm64SVEFloatElementReg(ins.Args[0]) + source, sourceBits, sourceOK := arm64SVEFloatElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + if !controlOK || !sourceOK || !destinationOK || controlBits != sourceBits || sourceBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s operands must use one H/S/D width: %q", op, ins.Raw) + } + sourceValue, floatVectorType, err := c.loadRawSVEFloatVector(source, sourceBits) + if err != nil { + return true, false, err + } + controlValue, integerVectorType, err := c.loadZRegElements(control, controlBits) + if err != nil { + return true, false, err + } + _, _, lanes, _ := arm64SVEFloatType(sourceBits) + code := map[int]string{16: "f16", 32: "f32", 64: "f64"}[sourceBits] + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.x.nxv%d%s(%s %s, %s %s)\n", + result, floatVectorType, intrinsic, lanes, code, floatVectorType, sourceValue, integerVectorType, controlValue) + return true, false, c.storeRawSVEFloatVector(destination, sourceBits, "%"+result, floatVectorType) +} diff --git a/arm64_lower_sve_float_trig_multiply_add.go b/arm64_lower_sve_float_trig_multiply_add.go new file mode 100644 index 00000000..23bb60c1 --- /dev/null +++ b/arm64_lower_sve_float_trig_multiply_add.go @@ -0,0 +1,38 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEFloatTrigMultiplyAdd(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZFTMAD" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 ZFTMAD expects one complete Go 1.27 vector form without a suffix: %q", ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || ins.Args[0].ImmIsFloat || ins.Args[0].Imm < 0 || ins.Args[0].Imm > 7 { + return true, false, fmt.Errorf("arm64 ZFTMAD immediate must be an unsigned 3-bit integer: %q", ins.Raw) + } + multiplier, multiplierBits, multiplierOK := arm64SVEFloatElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + repeated, repeatedBits, repeatedOK := arm64SVEFloatElementReg(ins.Args[3]) + if !multiplierOK || !destinationOK || !repeatedOK || multiplierBits != destinationBits || destinationBits != repeatedBits || destination != repeated { + return true, false, fmt.Errorf("arm64 ZFTMAD requires matching destructive H/S/D operands: %q", ins.Raw) + } + destinationValue, vectorType, err := c.loadRawSVEFloatVector(destination, destinationBits) + if err != nil { + return true, false, err + } + multiplierValue, _, err := c.loadRawSVEFloatVector(multiplier, multiplierBits) + if err != nil { + return true, false, err + } + _, _, lanes, _ := arm64SVEFloatType(destinationBits) + code := map[int]string{16: "f16", 32: "f32", 64: "f64"}[destinationBits] + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ftmad.x.nxv%d%s(%s %s, %s %s, i32 %d)\n", + result, vectorType, lanes, code, vectorType, destinationValue, vectorType, multiplierValue, ins.Args[0].Imm) + return true, false, c.storeRawSVEFloatVector(destination, destinationBits, "%"+result, vectorType) +} diff --git a/arm64_lower_sve_float_trig_multiply_add_test.go b/arm64_lower_sve_float_trig_multiply_add_test.go new file mode 100644 index 00000000..151dc642 --- /dev/null +++ b/arm64_lower_sve_float_trig_multiply_add_test.go @@ -0,0 +1,73 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatTrigMultiplyAddCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloattrigmultiplyaddforms(SB),$0-0\n") + for _, width := range []string{"H", "S", "D"} { + for _, immediate := range []int{0, 7} { + fmt.Fprintf(&source, "\tZFTMAD $%d, Z1.%s, Z2.%s, Z2.%s\n", immediate, width, width, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloattrigmultiplyaddforms": {Name: "svefloattrigmultiplyaddforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.ftmad.x.nxv8f16", + "@llvm.aarch64.sve.ftmad.x.nxv4f32", + "@llvm.aarch64.sve.ftmad.x.nxv2f64", + "i32 0", + "i32 7", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating trigonometric multiply-add lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-trig-multiply-add.ll", "arm64-sve-float-trig-multiply-add.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatTrigMultiplyAddRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFTMAD $-1, Z1.S, Z2.S, Z2.S", + "ZFTMAD $8, Z1.S, Z2.S, Z2.S", + "ZFTMAD $0, Z1.B, Z2.B, Z2.B", + "ZFTMAD $0, Z1.H, Z2.S, Z2.S", + "ZFTMAD $0, Z1.S, Z2.S, Z3.S", + "ZFTMAD.Z $0, Z1.S, Z2.S, Z2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloattrigmultiplyadd(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloattrigmultiplyadd": {Name: "badsvefloattrigmultiplyadd", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ZFTMAD forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_trig_multiply_test.go b/arm64_lower_sve_float_trig_multiply_test.go new file mode 100644 index 00000000..814506c8 --- /dev/null +++ b/arm64_lower_sve_float_trig_multiply_test.go @@ -0,0 +1,75 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEFloatTrigMultiplyCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svefloattrigmultiplyforms(SB),$0-0\n") + for _, op := range []string{"ZFTSMUL", "ZFTSSEL"} { + for _, width := range []string{"H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, Z3.%s\n", op, width, width, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloattrigmultiplyforms": {Name: "svefloattrigmultiplyforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.ftsmul.x.nxv8f16", + "@llvm.aarch64.sve.ftsmul.x.nxv4f32", + "@llvm.aarch64.sve.ftsmul.x.nxv2f64", + "@llvm.aarch64.sve.ftssel.x.nxv8f16", + "@llvm.aarch64.sve.ftssel.x.nxv2f64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating trigonometric multiply lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-trig-multiply.ll", "arm64-sve-float-trig-multiply.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatTrigMultiplyRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFTSMUL Z1.B, Z2.B, Z3.B", + "ZFTSMUL Z1.H, Z2.S, Z3.S", + "ZFTSMUL Z1.S, Z2.S, Z3.D", + "ZFTSMUL Z1.S, Z2.S, P0.M, Z3.S", + "ZFTSMUL.Z Z1.S, Z2.S, Z3.S", + "ZFTSSEL Z1.B, Z2.B, Z3.B", + "ZFTSSEL Z1.H, Z2.S, Z3.S", + "ZFTSSEL.Z Z1.S, Z2.S, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloattrigmultiply(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloattrigmultiply": {Name: "badsvefloattrigmultiply", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ZFTSMUL forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_float_unary.go b/arm64_lower_sve_float_unary.go new file mode 100644 index 00000000..a5510f00 --- /dev/null +++ b/arm64_lower_sve_float_unary.go @@ -0,0 +1,183 @@ +package plan9asm + +import ( + "fmt" + "math" + "strings" +) + +type arm64SVEFloatUnarySpec struct { + intrinsic string + unpred bool + sdOnly bool + integerBits int + fptoint bool +} + +var arm64SVEFloatUnarySpecs = map[Op]arm64SVEFloatUnarySpec{ + "ZFABS": {intrinsic: "fabs"}, + "ZFNEG": {intrinsic: "fneg"}, + "ZFRECPE": {intrinsic: "frecpe.x", unpred: true}, + "ZFRECPX": {intrinsic: "frecpx"}, + "ZFRINT32X": {intrinsic: "rint", sdOnly: true, integerBits: 32, fptoint: true}, + "ZFRINT32Z": {intrinsic: "trunc", sdOnly: true, integerBits: 32, fptoint: true}, + "ZFRINT64X": {intrinsic: "rint", sdOnly: true, integerBits: 64, fptoint: true}, + "ZFRINT64Z": {intrinsic: "trunc", sdOnly: true, integerBits: 64, fptoint: true}, + "ZFRINTA": {intrinsic: "frinta"}, + "ZFRINTI": {intrinsic: "frinti"}, + "ZFRINTM": {intrinsic: "frintm"}, + "ZFRINTN": {intrinsic: "frintn"}, + "ZFRINTP": {intrinsic: "frintp"}, + "ZFRINTX": {intrinsic: "frintx"}, + "ZFRINTZ": {intrinsic: "frintz"}, + "ZFRSQRTE": {intrinsic: "frsqrte.x", unpred: true}, + "ZFSQRT": {intrinsic: "fsqrt"}, +} + +type arm64SVEFloatUnaryForm struct { + elementBits int + source int + predicate int + destination int + zeroing bool +} + +func (c *arm64Ctx) lowerARM64SVEFloatUnary(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEFloatUnarySpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + form := arm64SVEFloatUnaryForm{} + if spec.unpred { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects Zn.T, Zd.T: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64SVEFloatElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[1]) + if !sourceOK || !destinationOK || sourceBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s requires matching H, S, or D vector widths: %q", op, ins.Raw) + } + form = arm64SVEFloatUnaryForm{elementBits: sourceBits, source: source, destination: destination} + } else { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zn.T, Pg/M|Z, Zd.T: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64SVEFloatElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + predicate, mergeOK := arm64ParseSVEPredicateMode(ins.Args[1], "M", 7) + if !mergeOK { + predicate, form.zeroing = 0, true + var zeroOK bool + predicate, zeroOK = arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + if !zeroOK { + return true, false, fmt.Errorf("arm64 %s requires P0..P7/M or P0..P7/Z: %q", op, ins.Raw) + } + } + if !sourceOK || !destinationOK || sourceBits != destinationBits || (spec.sdOnly && sourceBits == 16) { + return true, false, fmt.Errorf("arm64 %s vector widths do not match its Go 1.27 form: %q", op, ins.Raw) + } + form.elementBits = sourceBits + form.source = source + form.predicate = predicate + form.destination = destination + } + return true, false, c.lowerARM64SVEFloatUnaryForm(spec, form) +} + +func (c *arm64Ctx) lowerARM64SVEFloatUnaryForm(spec arm64SVEFloatUnarySpec, form arm64SVEFloatUnaryForm) error { + source, vectorType, err := c.loadRawSVEFloatVector(form.source, form.elementBits) + if err != nil { + return err + } + _, _, lanes, err := arm64SVEFloatType(form.elementBits) + if err != nil { + return err + } + mangle := fmt.Sprintf("nxv%d%s", lanes, map[int]string{16: "f16", 32: "f32", 64: "f64"}[form.elementBits]) + if spec.integerBits != 0 { + calculated, err := c.lowerARM64SVEFRIntSized(spec, source, vectorType, mangle, lanes, form.elementBits) + if err != nil { + return err + } + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + inactive := "zeroinitializer" + if !form.zeroing { + inactive, _, err = c.loadRawSVEFloatVector(form.destination, form.elementBits) + if err != nil { + return err + } + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", selected, predicateType, predicate, vectorType, calculated, vectorType, inactive) + return c.storeRawSVEFloatVector(form.destination, form.elementBits, "%"+selected, vectorType) + } + result := c.newTmp() + if spec.unpred { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.%s(%s %s)\n", result, vectorType, spec.intrinsic, mangle, vectorType, source) + } else { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + merge := source + if !form.zeroing { + merge, _, err = c.loadRawSVEFloatVector(form.destination, form.elementBits) + if err != nil { + return err + } + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.%s(%s %s, %s %s, %s %s)\n", result, vectorType, spec.intrinsic, mangle, vectorType, merge, predicateType, predicate, vectorType, source) + if form.zeroing { + integerType, _, err := arm64SVEVectorType(form.elementBits) + if err != nil { + return err + } + bits := c.newTmp() + mask := c.newTmp() + zeroed := c.newTmp() + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to %s\n", bits, vectorType, result, integerType) + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", mask, predicateType, predicate, integerType) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", zeroed, integerType, bits, mask) + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to %s\n", converted, integerType, zeroed, vectorType) + result = converted + } + } + return c.storeRawSVEFloatVector(form.destination, form.elementBits, "%"+result, vectorType) +} + +func (c *arm64Ctx) lowerARM64SVEFRIntSized(spec arm64SVEFloatUnarySpec, source, vectorType, mangle string, lanes, elementBits int) (string, error) { + rounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.%s(%s %s)\n", rounded, vectorType, spec.intrinsic, mangle, vectorType, source) + integerType := fmt.Sprintf("", lanes, spec.integerBits) + integers := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.fptosi.sat.nxv%di%d.%s(%s %%%s)\n", integers, integerType, lanes, spec.integerBits, mangle, vectorType, rounded) + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sitofp %s %%%s to %s\n", converted, integerType, integers, vectorType) + minimum := -math.Ldexp(1, spec.integerBits-1) + upper := math.Ldexp(1, spec.integerBits-1) + minimumVector, err := c.arm64SVEFloatSplat(minimum, elementBits) + if err != nil { + return "", err + } + upperVector, err := c.arm64SVEFloatSplat(upper, elementBits) + if err != nil { + return "", err + } + geMinimum := c.newTmp() + belowUpper := c.newTmp() + valid := c.newTmp() + fixed := c.newTmp() + predicateType := fmt.Sprintf("", lanes) + fmt.Fprintf(c.b, " %%%s = fcmp oge %s %%%s, %s\n", geMinimum, vectorType, rounded, minimumVector) + fmt.Fprintf(c.b, " %%%s = fcmp olt %s %%%s, %s\n", belowUpper, vectorType, rounded, upperVector) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", valid, predicateType, geMinimum, belowUpper) + fmt.Fprintf(c.b, " %%%s = select %s %%%s, %s %%%s, %s %s\n", fixed, predicateType, valid, vectorType, converted, vectorType, minimumVector) + return "%" + fixed, nil +} diff --git a/arm64_lower_sve_float_unary_test.go b/arm64_lower_sve_float_unary_test.go new file mode 100644 index 00000000..391bdc0b --- /dev/null +++ b/arm64_lower_sve_float_unary_test.go @@ -0,0 +1,88 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEFloatUnaryCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svefloatunaryforms(SB),$0-0\n") + for _, op := range []string{"ZFABS", "ZFNEG", "ZFRECPX", "ZFRINTA", "ZFRINTI", "ZFRINTM", "ZFRINTN", "ZFRINTP", "ZFRINTX", "ZFRINTZ", "ZFSQRT"} { + for index, width := range []string{"H", "S", "D"} { + predicate := string(rune('0' + index)) + for _, mode := range []string{"M", "Z"} { + source.WriteString("\t" + op + " Z1." + width + ", P" + predicate + "." + mode + ", Z2." + width + "\n") + } + } + } + for _, op := range []string{"ZFRINT32X", "ZFRINT32Z", "ZFRINT64X", "ZFRINT64Z"} { + for index, width := range []string{"S", "D"} { + predicate := string(rune('0' + index)) + for _, mode := range []string{"M", "Z"} { + source.WriteString("\t" + op + " Z3." + width + ", P" + predicate + "." + mode + ", Z4." + width + "\n") + } + } + } + for _, op := range []string{"ZFRECPE", "ZFRSQRTE"} { + for _, width := range []string{"H", "S", "D"} { + source.WriteString("\t" + op + " Z5." + width + ", Z6." + width + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEFloatUnaryCompleteGo127Family(t *testing.T) { + source := arm64SVEFloatUnaryCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svefloatunaryforms": {Name: "svefloatunaryforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+fptoint,+sve"`, "@llvm.aarch64.sve.fabs.nxv", "@llvm.fptosi.sat.nxv2i64.nxv2f64", "@llvm.aarch64.sve.frecpe.x.nxv", "@llvm.aarch64.sve.frsqrte.x.nxv", "@llvm.aarch64.sve.fsqrt.nxv"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE floating unary lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float-unary.ll", "arm64-sve-float-unary.o", ll) + }) + } +} + +func TestTranslateARM64SVEFloatUnaryRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFABS Z1.B, P0.M, Z2.B", + "ZFNEG Z1.S, P0, Z2.S", + "ZFSQRT Z1.S, P8.M, Z2.S", + "ZFRECPX Z1.S, P0.M, Z2.D", + "ZFRINT32X Z1.H, P0.M, Z2.H", + "ZFRINT64Z Z1.S, P0.M, Z2.D", + "ZFRECPE Z1.S, P0.M, Z2.S", + "ZFRSQRTE Z1.S, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefloatunary(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefloatunary": {Name: "badsvefloatunary", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE floating unary forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_halving_add_sub.go b/arm64_lower_sve_halving_add_sub.go new file mode 100644 index 00000000..65b235c5 --- /dev/null +++ b/arm64_lower_sve_halving_add_sub.go @@ -0,0 +1,50 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEHalvingAddSubIntrinsics = map[Op]string{ + "ZSHADD": "shadd", + "ZSRHADD": "srhadd", + "ZUHADD": "uhadd", + "ZURHADD": "urhadd", + "ZSHSUB": "shsub", + "ZSHSUBR": "shsubr", + "ZUHSUB": "uhsub", + "ZUHSUBR": "uhsubr", +} + +func (c *arm64Ctx) lowerARM64SVEHalvingAddSub(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEHalvingAddSubIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects Zm.T, Zdn.T, P0..P7/M, Zdn.T without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits || first != destination { + return true, false, fmt.Errorf("arm64 %s requires matching-width destructive data operands and P0..P7/M: %q", op, ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, firstBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, firstBits) + if err != nil { + return true, false, err + } + lanes := 128 / firstBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, intrinsic, lanes, firstBits, predicateType, predicateValue, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeZRegElements(destination, firstBits, "%"+result) +} diff --git a/arm64_lower_sve_halving_add_sub_test.go b/arm64_lower_sve_halving_add_sub_test.go new file mode 100644 index 00000000..ea0ab16e --- /dev/null +++ b/arm64_lower_sve_halving_add_sub_test.go @@ -0,0 +1,80 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEHalvingAddSubCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svehalvingaddsubforms(SB),$0-0\n") + for _, op := range []string{"ZSHADD", "ZSRHADD", "ZUHADD", "ZURHADD", "ZSHSUB", "ZSHSUBR", "ZUHSUB", "ZUHSUBR"} { + for predicate, width := range []string{"B", "H", "S", "D"} { + source.WriteString("\t" + op + " Z1." + width + ", Z2." + width + ", P" + string(rune('0'+predicate)) + ".M, Z2." + width + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEHalvingAddSubCompleteGo127Family(t *testing.T) { + source := arm64SVEHalvingAddSubCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svehalvingaddsubforms": {Name: "svehalvingaddsubforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.shadd.nxv16i8", + "@llvm.aarch64.sve.srhadd.nxv8i16", + "@llvm.aarch64.sve.uhadd.nxv4i32", + "@llvm.aarch64.sve.urhadd.nxv2i64", + "@llvm.aarch64.sve.shsub.nxv16i8", + "@llvm.aarch64.sve.shsubr.nxv8i16", + "@llvm.aarch64.sve.uhsub.nxv4i32", + "@llvm.aarch64.sve.uhsubr.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE halving add/sub lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-halving-add-sub.ll", "arm64-sve-halving-add-sub.o", ll) + }) + } +} + +func TestTranslateARM64SVEHalvingAddSubRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSHADD Z1.B, Z2.H, P0.M, Z2.H", + "ZSRHADD Z1.S, Z2.S, P0, Z2.S", + "ZUHADD Z1.D, Z2.D, P8.M, Z2.D", + "ZURHADD Z1.H, Z2.H, P0.M, Z3.H", + "ZSHSUB Z1.Q, Z2.Q, P0.M, Z2.Q", + "ZSHSUBR Z1.S, Z2.H, P0.M, Z2.H", + "ZUHSUB Z1.S, Z2.S, P0.Z, Z2.S", + "ZUHSUBR.Z Z1.D, Z2.D, P0.M, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvehalvingaddsub(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvehalvingaddsub": {Name: "badsvehalvingaddsub", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE halving add/sub forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_histogram.go b/arm64_lower_sve_histogram.go new file mode 100644 index 00000000..4806c1a0 --- /dev/null +++ b/arm64_lower_sve_histogram.go @@ -0,0 +1,68 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEHistogramOps = map[Op]struct{}{ + "ZHISTCNT": {}, + "ZHISTSEG": {}, +} + +func (c *arm64Ctx) lowerARM64SVEHistogram(op Op, ins Instr) (ok bool, terminated bool, err error) { + if _, ok := arm64SVEHistogramOps[op]; !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept a mnemonic suffix: %q", op, ins.Raw) + } + if op == "ZHISTSEG" { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 ZHISTSEG expects Zm.B, Zn.B, Zd.B: %q", ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != 8 || firstBits != 8 || destinationBits != 8 { + return true, false, fmt.Errorf("arm64 ZHISTSEG requires three B scalable-vector operands: %q", ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(first, 8) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, 8) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.histseg.nxv16i8(%s %s, %s %s)\n", result, vectorType, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeZRegElements(destination, 8, "%"+result) + } + if len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 ZHISTCNT expects Zm.S|D, Zn.S|D, Pg/Z, Zd.S|D: %q", ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "Z", 7) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || (firstBits != 32 && firstBits != 64) || secondBits != firstBits || destinationBits != firstBits { + return true, false, fmt.Errorf("arm64 ZHISTCNT requires matching S/D vectors under P0..P7/Z: %q", ins.Raw) + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, firstBits) + if err != nil { + return true, false, err + } + firstValue, vectorType, err := c.loadZRegElements(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, secondBits) + if err != nil { + return true, false, err + } + lanes := 128 / firstBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.histcnt.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, lanes, firstBits, predicateType, predicateValue, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_histogram_test.go b/arm64_lower_sve_histogram_test.go new file mode 100644 index 00000000..683d3671 --- /dev/null +++ b/arm64_lower_sve_histogram_test.go @@ -0,0 +1,69 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEHistogramCompleteGo127Family(t *testing.T) { + source := ` +TEXT svehistogram(SB),$0-0 + ZHISTCNT Z1.S, Z2.S, P0.Z, Z3.S + ZHISTCNT Z4.D, Z5.D, P7.Z, Z6.D + ZHISTSEG Z7.B, Z8.B, Z9.B + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svehistogram": {Name: "svehistogram", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.histcnt.nxv4i32", + "@llvm.aarch64.sve.histcnt.nxv2i64", + "@llvm.aarch64.sve.histseg.nxv16i8", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE histogram lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-histogram.ll", "arm64-sve-histogram.o", ll) + }) + } +} + +func TestTranslateARM64SVEHistogramRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZHISTCNT Z1.B, Z2.B, P0.Z, Z3.B", + "ZHISTCNT Z1.H, Z2.H, P0.Z, Z3.H", + "ZHISTCNT Z1.S, Z2.D, P0.Z, Z3.S", + "ZHISTCNT Z1.S, Z2.S, P8.Z, Z3.S", + "ZHISTCNT Z1.S, Z2.S, P0.M, Z3.S", + "ZHISTSEG Z1.H, Z2.H, Z3.H", + "ZHISTSEG Z1.B, Z2.B, Z3.H", + "ZHISTSEG.Z Z1.B, Z2.B, Z3.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvehistogram(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvehistogram": {Name: "badsvehistogram", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's histogram forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_index.go b/arm64_lower_sve_index.go new file mode 100644 index 00000000..cd314560 --- /dev/null +++ b/arm64_lower_sve_index.go @@ -0,0 +1,77 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEIndex(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZINDEX" && op != "ZINDEXW" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects step, start, Zd.B/H/S/D without a suffix: %q", op, ins.Raw) + } + destination, writtenBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !destinationOK { + return true, false, fmt.Errorf("arm64 %s destination must be Z0..Z31.B/H/S/D: %q", op, ins.Raw) + } + stepIsReg := arm64SVEIndexScalarRegister(ins.Args[0]) + startIsReg := arm64SVEIndexScalarRegister(ins.Args[1]) + stepIsImm := arm64SVEIndexImmediate(ins.Args[0]) + startIsImm := arm64SVEIndexImmediate(ins.Args[1]) + if !stepIsReg && !stepIsImm || !startIsReg && !startIsImm || op == "ZINDEXW" && stepIsImm && startIsImm { + return true, false, fmt.Errorf("arm64 %s operands do not match its Go 1.27 scalar/immediate forms: %q", op, ins.Raw) + } + + // Go's ZINDEX register encodings carry fixed D size bits. The generated + // assembler accepts B/H/S spellings too, but ORs their size field with D; + // preserve the resulting machine semantics rather than the written suffix. + elementBits := writtenBits + if op == "ZINDEX" && (stepIsReg || startIsReg) { + elementBits = 64 + } + step, err := c.arm64SVEIndexScalar(ins.Args[0], elementBits) + if err != nil { + return true, false, err + } + start, err := c.arm64SVEIndexScalar(ins.Args[1], elementBits) + if err != nil { + return true, false, err + } + vectorType, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.index.nxv%di%d(i%d %s, i%d %s)\n", + result, vectorType, lanes, elementBits, elementBits, start, elementBits, step) + return true, false, c.storeZRegElements(destination, elementBits, "%"+result) +} + +func arm64SVEIndexScalarRegister(operand Operand) bool { + return operand.Kind == OpReg && isARM64GeneralOrZeroReg(operand.Reg) +} + +func arm64SVEIndexImmediate(operand Operand) bool { + return operand.Kind == OpImm && operand.ImmRaw == "" && operand.Imm >= -16 && operand.Imm <= 15 +} + +func (c *arm64Ctx) arm64SVEIndexScalar(operand Operand, elementBits int) (string, error) { + if arm64SVEIndexImmediate(operand) { + return fmt.Sprintf("%d", operand.Imm), nil + } + if !arm64SVEIndexScalarRegister(operand) { + return "", fmt.Errorf("arm64 SVE INDEX scalar must be R0..R30, ZR, or a signed 5-bit immediate") + } + value, err := c.loadReg(operand.Reg) + if err != nil { + return "", err + } + if elementBits == 64 || value == "0" { + return value, nil + } + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", truncated, value, elementBits) + return "%" + truncated, nil +} diff --git a/arm64_lower_sve_index_test.go b/arm64_lower_sve_index_test.go new file mode 100644 index 00000000..cddd95df --- /dev/null +++ b/arm64_lower_sve_index_test.go @@ -0,0 +1,90 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEIndexCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveindexforms(SB),$0-0\n") + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\tZINDEX R1, R2, Z3.%s\n", width) + fmt.Fprintf(&source, "\tZINDEX ZR, $15, Z4.%s\n", width) + fmt.Fprintf(&source, "\tZINDEX $-16, R5, Z6.%s\n", width) + fmt.Fprintf(&source, "\tZINDEX $1, $11, Z7.%s\n", width) + fmt.Fprintf(&source, "\tZINDEXW R8, R9, Z10.%s\n", width) + fmt.Fprintf(&source, "\tZINDEXW ZR, $-16, Z11.%s\n", width) + fmt.Fprintf(&source, "\tZINDEXW $15, R12, Z13.%s\n", width) + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEIndexCompleteGo127Family(t *testing.T) { + source := arm64SVEIndexCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveindexforms": {Name: "sveindexforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.index.nxv16i8", + "@llvm.aarch64.sve.index.nxv8i16", + "@llvm.aarch64.sve.index.nxv4i32", + "@llvm.aarch64.sve.index.nxv2i64", + "@llvm.aarch64.sve.index.nxv4i32(i32 11, i32 1)", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE INDEX lowering omitted %q:\n%s", triple, want, ll) + } + } + // Go's ZINDEX scalar forms always set the D size bits, even when + // their accepted destination spelling carries B/H/S. + if got := strings.Count(ll, "@llvm.aarch64.sve.index.nxv2i64"); got < 13 { + t.Fatalf("%s ZINDEX scalar forms did not preserve Go's forced-D encoding: got %d i64 references\n%s", triple, got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-index.ll", "arm64-sve-index.o", ll) + }) + } +} + +func TestTranslateARM64SVEIndexRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZINDEXW $1, $2, Z0.S", + "ZINDEX $-17, R0, Z0.D", + "ZINDEX $16, R0, Z0.D", + "ZINDEX RSP, R0, Z0.D", + "ZINDEX R0, RSP, Z0.D", + "ZINDEX R0, R1, Z0", + "ZINDEX R0, R1, Z0.Q", + "ZINDEX R0, R1, V0.D", + "ZINDEX.Z R0, R1, Z0.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveindex(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveindex": {Name: "badsveindex", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE INDEX forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_insert.go b/arm64_lower_sve_insert.go new file mode 100644 index 00000000..f340b787 --- /dev/null +++ b/arm64_lower_sve_insert.go @@ -0,0 +1,99 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +var arm64SVEInsertBaseSize = map[Op]int{ + "ZINSR": 3, + "ZINSRW": 0, + "ZINSRB": 0, + "ZINSRH": 1, + "ZINSRS": 2, + "ZINSRD": 3, +} + +func (c *arm64Ctx) lowerARM64SVEInsert(op Op, ins Instr) (ok bool, terminated bool, err error) { + baseSize, ok := arm64SVEInsertBaseSize[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects scalar, Zdn.B/H/S/D without a suffix: %q", op, ins.Raw) + } + destination, writtenBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[1]) + if !destinationOK { + return true, false, fmt.Errorf("arm64 %s destination must be Z0..Z31.B/H/S/D: %q", op, ins.Raw) + } + writtenSize := map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[writtenBits] + elementBits := 8 << (baseSize | writtenSize) + + var scalar string + if op == "ZINSR" || op == "ZINSRW" { + if !arm64SVEIndexScalarRegister(ins.Args[0]) { + return true, false, fmt.Errorf("arm64 %s source must be R0..R30 or ZR: %q", op, ins.Raw) + } + scalar, err = c.loadReg(ins.Args[0].Reg) + if err != nil { + return true, false, err + } + if elementBits != 64 && scalar != "0" { + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", truncated, scalar, elementBits) + scalar = "%" + truncated + } + } else { + vectorRegister, vectorOK := arm64SVEInsertVRegister(ins.Args[0]) + if !vectorOK { + return true, false, fmt.Errorf("arm64 %s source must be a bare V0..V31 register: %q", op, ins.Raw) + } + scalar, err = c.arm64SVEInsertVectorScalar(vectorRegister, elementBits) + if err != nil { + return true, false, err + } + } + + oldVector, vectorType, err := c.loadZRegElements(destination, elementBits) + if err != nil { + return true, false, err + } + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.insr.nxv%di%d(%s %s, i%d %s)\n", + result, vectorType, lanes, elementBits, vectorType, oldVector, elementBits, scalar) + return true, false, c.storeZRegElements(destination, elementBits, "%"+result) +} + +func arm64SVEInsertVRegister(operand Operand) (Reg, bool) { + if operand.Kind != OpReg { + return "", false + } + text := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + if !strings.HasPrefix(text, "V") || strings.ContainsAny(text, ".[") { + return "", false + } + index, err := strconv.Atoi(text[1:]) + return Reg(text), err == nil && index >= 0 && index <= 31 +} + +func (c *arm64Ctx) arm64SVEInsertVectorScalar(register Reg, elementBits int) (string, error) { + bytes, err := c.loadVReg(register) + if err != nil { + return "", err + } + vectorType := fmt.Sprintf("<%d x i%d>", 128/elementBits, elementBits) + vector := bytes + if elementBits != 8 { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to %s\n", converted, bytes, vectorType) + vector = "%" + converted + } + scalar := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i64 0\n", scalar, vectorType, vector) + return "%" + scalar, nil +} diff --git a/arm64_lower_sve_insert_test.go b/arm64_lower_sve_insert_test.go new file mode 100644 index 00000000..564601ce --- /dev/null +++ b/arm64_lower_sve_insert_test.go @@ -0,0 +1,91 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEInsertCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveinsertforms(SB),$0-0\n") + for _, spec := range []struct { + op string + source string + }{ + {op: "ZINSR", source: "ZR"}, + {op: "ZINSRW", source: "R25"}, + {op: "ZINSRB", source: "V25"}, + {op: "ZINSRH", source: "V7"}, + {op: "ZINSRS", source: "V14"}, + {op: "ZINSRD", source: "V2"}, + } { + for vector, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\t%s %s, Z%d.%s\n", spec.op, spec.source, vector+1, width) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEInsertCompleteGo127Family(t *testing.T) { + source := arm64SVEInsertCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveinsertforms": {Name: "sveinsertforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.insr.nxv16i8", + "@llvm.aarch64.sve.insr.nxv8i16", + "@llvm.aarch64.sve.insr.nxv4i32", + "@llvm.aarch64.sve.insr.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE INSR lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-insert.ll", "arm64-sve-insert.o", ll) + }) + } +} + +func TestTranslateARM64SVEInsertRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZINSR V0, Z0.D", + "ZINSRW V0, Z0.S", + "ZINSRB R0, Z0.B", + "ZINSRH R0, Z0.H", + "ZINSRS R0, Z0.S", + "ZINSRD R0, Z0.D", + "ZINSR RSP, Z0.D", + "ZINSR R0, Z0", + "ZINSRB V0, Z0.Q", + "ZINSR.Z R0, Z0.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveinsert(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveinsert": {Name: "badsveinsert", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE INSR forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_integer_dot.go b/arm64_lower_sve_integer_dot.go new file mode 100644 index 00000000..a2ae3ea1 --- /dev/null +++ b/arm64_lower_sve_integer_dot.go @@ -0,0 +1,152 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEIntegerDotSpec struct { + intrinsic string + mixed bool + indexedOnly bool +} + +var arm64SVEIntegerDotSpecs = map[Op]arm64SVEIntegerDotSpec{ + "ZSDOT": {intrinsic: "sdot"}, + "ZUDOT": {intrinsic: "udot"}, + "ZSUDOT": {intrinsic: "sudot", mixed: true, indexedOnly: true}, + "ZUSDOT": {intrinsic: "usdot", mixed: true}, +} + +type arm64SVEIntegerDotForm struct { + intrinsic string + sourceBits int + destinationBits int + first int + second int + destination int + lane int + indexed bool +} + +func arm64SVEIntegerDotFeature(ins Instr) string { + if len(ins.Args) != 3 { + return "" + } + _, sourceBits, ok := arm64ParseSVEZElementReg(ins.Args[0]) + if !ok { + _, sourceBits, _, ok = arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[0]) + } + _, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !ok || !destinationOK { + return "" + } + if sourceBits == 8 && destinationBits == 16 { + return "+sve2p3" + } + if sourceBits == 16 && destinationBits == 32 { + return "+sve2p1" + } + return "" +} + +func (c *arm64Ctx) lowerARM64SVEIntegerDot(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEIntegerDotSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 integer-dot form without a suffix: %q", op, ins.Raw) + } + form := arm64SVEIntegerDotForm{intrinsic: spec.intrinsic} + if first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[0]); firstOK { + form.first = first + form.sourceBits = firstBits + } else { + first, firstBits, lane, firstOK := arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[0]) + if !firstOK { + return true, false, fmt.Errorf("arm64 %s first source must be a B/H vector or indexed vector: %q", op, ins.Raw) + } + form.first = first + form.sourceBits = firstBits + form.lane = lane + form.indexed = true + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || secondBits != form.sourceBits || !destinationOK || !arm64SVEIntegerDotWidthOK(spec, form.sourceBits, destinationBits) || spec.indexedOnly && !form.indexed { + return true, false, fmt.Errorf("arm64 %s has an invalid source/destination width or indexing mode: %q", op, ins.Raw) + } + if form.indexed { + maximumVector, maximumLane := arm64SVEIntegerDotIndexedLimits(form.sourceBits, destinationBits) + if maximumVector < 0 || form.first > maximumVector || form.lane > maximumLane { + return true, false, fmt.Errorf("arm64 %s indexed source is outside the Go 1.27 register/lane range: %q", op, ins.Raw) + } + } + form.second = second + form.destination = destination + form.destinationBits = destinationBits + return true, false, c.lowerARM64SVEIntegerDotForm(form) +} + +func arm64SVEIntegerDotWidthOK(spec arm64SVEIntegerDotSpec, sourceBits, destinationBits int) bool { + if spec.mixed { + return sourceBits == 8 && destinationBits == 32 + } + return sourceBits == 8 && (destinationBits == 16 || destinationBits == 32) || + sourceBits == 16 && (destinationBits == 32 || destinationBits == 64) +} + +func arm64SVEIntegerDotIndexedLimits(sourceBits, destinationBits int) (maximumVector, maximumLane int) { + switch { + case sourceBits == 8 && destinationBits == 16: + return 7, 7 + case sourceBits == 8 && destinationBits == 32: + return 7, 3 + case sourceBits == 16 && destinationBits == 32: + return 7, 3 + case sourceBits == 16 && destinationBits == 64: + return 15, 1 + default: + return -1, -1 + } +} + +func (c *arm64Ctx) lowerARM64SVEIntegerDotForm(form arm64SVEIntegerDotForm) error { + accumulator, destinationType, err := c.loadZRegElements(form.destination, form.destinationBits) + if err != nil { + return err + } + second, sourceType, err := c.loadZRegElements(form.second, form.sourceBits) + if err != nil { + return err + } + first, _, err := c.loadZRegElements(form.first, form.sourceBits) + if err != nil { + return err + } + if form.destinationBits == 16 { + result := c.newTmp() + assembly := form.intrinsic + " $0.h, $2.b, $3.b" + if form.indexed { + assembly += fmt.Sprintf("[%d]", form.lane) + } + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(%s %s, %s %s, %s %s)\n", result, destinationType, assembly, "=&w,0,w,w", destinationType, accumulator, sourceType, second, sourceType, first) + return c.storeZRegElements(form.destination, form.destinationBits, "%"+result) + } + lanes := 128 / form.destinationBits + intrinsic := form.intrinsic + if form.indexed { + intrinsic += ".lane" + } + if form.destinationBits == form.sourceBits*2 { + intrinsic += ".x2" + } + result := c.newTmp() + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s, i32 %d)\n", result, destinationType, intrinsic, lanes, form.destinationBits, destinationType, accumulator, sourceType, second, sourceType, first, form.lane) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, destinationType, intrinsic, lanes, form.destinationBits, destinationType, accumulator, sourceType, second, sourceType, first) + } + return c.storeZRegElements(form.destination, form.destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_integer_dot_test.go b/arm64_lower_sve_integer_dot_test.go new file mode 100644 index 00000000..ec9770af --- /dev/null +++ b/arm64_lower_sve_integer_dot_test.go @@ -0,0 +1,84 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEIntegerDotCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT sveintegerdotforms(SB),$0-0\n") + for _, op := range []string{"ZSDOT", "ZUDOT"} { + for _, widths := range [][2]string{{"B", "H"}, {"H", "S"}, {"B", "S"}, {"H", "D"}} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, Z3.%s\n", op, widths[0], widths[0], widths[1]) + } + for _, form := range []struct { + source, destination string + vector, lane int + }{{"B", "H", 7, 7}, {"H", "S", 7, 3}, {"B", "S", 7, 3}, {"H", "D", 15, 1}} { + fmt.Fprintf(&source, "\t%s Z%d.%s[%d], Z2.%s, Z3.%s\n", op, form.vector, form.source, form.lane, form.source, form.destination) + } + } + source.WriteString("\tZUSDOT Z1.B, Z2.B, Z3.S\n") + source.WriteString("\tZUSDOT Z7.B[3], Z2.B, Z3.S\n") + source.WriteString("\tZSUDOT Z7.B[3], Z2.B, Z3.S\n") + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveintegerdotforms": {Name: "sveintegerdotforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+i8mm,+sve,+sve2,+sve2p1,+sve2p3"`, + `asm sideeffect "sdot $0.h, $2.b, $3.b"`, + `asm sideeffect "udot $0.h, $2.b, $3.b[7]"`, + "@llvm.aarch64.sve.sdot.nxv2i64", + "@llvm.aarch64.sve.udot.lane.x2.nxv4i32", + "@llvm.aarch64.sve.usdot.nxv4i32", + "@llvm.aarch64.sve.sudot.lane.nxv4i32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE integer dot lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-integer-dot.ll", "arm64-sve-integer-dot.o", ll) + }) + } +} + +func TestTranslateARM64SVEIntegerDotRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSDOT Z1.B, Z2.H, Z3.S", + "ZUDOT Z1.B, Z2.B, Z3.D", + "ZSDOT Z8.B[0], Z2.B, Z3.S", + "ZUDOT Z7.B[4], Z2.B, Z3.S", + "ZSDOT Z16.H[0], Z2.H, Z3.D", + "ZUDOT Z15.H[2], Z2.H, Z3.D", + "ZSUDOT Z1.B, Z2.B, Z3.S", + "ZUSDOT Z1.H, Z2.H, Z3.S", + "ZSDOT.Z Z1.B, Z2.B, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveintegerdot(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveintegerdot": {Name: "badsveintegerdot", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE integer dot forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_integer_reduction.go b/arm64_lower_sve_integer_reduction.go new file mode 100644 index 00000000..f2ee3f0c --- /dev/null +++ b/arm64_lower_sve_integer_reduction.go @@ -0,0 +1,103 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEIntegerReductionSpec struct { + intrinsic string + elementBits int + quad bool +} + +var arm64SVEIntegerReductionSpecs = map[Op]arm64SVEIntegerReductionSpec{ + "ZADDQV": {intrinsic: "addqv", quad: true}, + "ZANDQV": {intrinsic: "andqv", quad: true}, + "ZANDVB": {intrinsic: "andv", elementBits: 8}, + "ZANDVH": {intrinsic: "andv", elementBits: 16}, + "ZANDVS": {intrinsic: "andv", elementBits: 32}, + "ZANDVD": {intrinsic: "andv", elementBits: 64}, + "ZEORQV": {intrinsic: "eorqv", quad: true}, + "ZEORVB": {intrinsic: "eorv", elementBits: 8}, + "ZEORVH": {intrinsic: "eorv", elementBits: 16}, + "ZEORVS": {intrinsic: "eorv", elementBits: 32}, + "ZEORVD": {intrinsic: "eorv", elementBits: 64}, + "ZORQV": {intrinsic: "orqv", quad: true}, + "ZORVB": {intrinsic: "orv", elementBits: 8}, + "ZORVH": {intrinsic: "orv", elementBits: 16}, + "ZORVS": {intrinsic: "orv", elementBits: 32}, + "ZORVD": {intrinsic: "orv", elementBits: 64}, +} + +type arm64SVEIntegerReductionForm struct { + elementBits int + source int + predicate int + destination int +} + +func (c *arm64Ctx) lowerARM64SVEIntegerReduction(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEIntegerReductionSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + form, err := arm64ParseSVEIntegerReductionForm(op, spec, ins) + if err != nil { + return true, false, err + } + return true, false, c.lowerARM64SVEIntegerReductionForm(spec, form, ins.Args[2].Reg) +} + +func arm64ParseSVEIntegerReductionForm(op Op, spec arm64SVEIntegerReductionSpec, ins Instr) (arm64SVEIntegerReductionForm, error) { + form := arm64SVEIntegerReductionForm{} + if len(ins.Args) != 3 { + return form, fmt.Errorf("arm64 %s expects Zn.T, Pg, Vd%s: %q", op, map[bool]string{true: ".T", false: ""}[spec.quad], ins.Raw) + } + source, elementBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + predicate, predicateOK := arm64ParseSVEPredicate(ins.Args[1]) + destination, destinationOK := arm64ParseVReg(ins.Args[2].Reg) + if !sourceOK || !predicateOK || predicate > 7 || !destinationOK || ins.Args[2].Kind != OpReg { + return form, fmt.Errorf("arm64 %s requires a scalable source, bare predicate, and SIMD destination: %q", op, ins.Raw) + } + if !spec.quad { + if strings.Contains(string(ins.Args[2].Reg), ".") { + return form, fmt.Errorf("arm64 %s destination must be a bare V register: %q", op, ins.Raw) + } + // Go's generic Zn.T encoder ORs the operand size bits into the + // mnemonic's fixed size bits, rather than requiring them to match. + opcodeSize := map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[spec.elementBits] + sourceSize := map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + elementBits = 8 << (opcodeSize | sourceSize) + } else { + arrangement, arrangementOK := parseARM64VectorArrangement(ins.Args[2].Reg) + if !arrangementOK || arrangement.elementBits != elementBits || arrangement.lanes*arrangement.elementBits != 128 { + return form, fmt.Errorf("arm64 %s destination must be a full-width SIMD vector matching its source elements: %q", op, ins.Raw) + } + } + return arm64SVEIntegerReductionForm{elementBits: elementBits, source: source, predicate: predicate, destination: destination}, nil +} + +func (c *arm64Ctx) lowerARM64SVEIntegerReductionForm(spec arm64SVEIntegerReductionSpec, form arm64SVEIntegerReductionForm, destination Reg) error { + source, vectorType, err := c.loadZRegElements(form.source, form.elementBits) + if err != nil { + return err + } + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + lanes := 128 / form.elementBits + result := c.newTmp() + if !spec.quad { + fmt.Fprintf(c.b, " %%%s = call i%d @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, form.elementBits, spec.intrinsic, lanes, form.elementBits, predicateType, predicate, vectorType, source) + return c.storeARM64ScalarToVReg(destination, form.elementBits, "%"+result) + } + fmt.Fprintf(c.b, " %%%s = call <%d x i%d> @llvm.aarch64.sve.%s.v%di%d.nxv%di%d(%s %s, %s %s)\n", result, lanes, form.elementBits, spec.intrinsic, lanes, form.elementBits, lanes, form.elementBits, predicateType, predicate, vectorType, source) + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", bytes, lanes, form.elementBits, result) + return c.storeVReg(destination, "%"+bytes) +} diff --git a/arm64_lower_sve_integer_reduction_test.go b/arm64_lower_sve_integer_reduction_test.go new file mode 100644 index 00000000..bb472d0d --- /dev/null +++ b/arm64_lower_sve_integer_reduction_test.go @@ -0,0 +1,91 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEIntegerReductionCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveintreduceforms(SB),$0-0\n") + for _, base := range []string{"ZANDV", "ZEORV", "ZORV"} { + for predicate, sourceWidth := range []string{"B", "H", "S", "D"} { + // Go's generated reduction rows use a generic Zn.T operand for each + // VB/VH/VS/VD spelling. Cover the full 4x4 encoder matrix; the + // effective hardware width is the bitwise union of both size fields. + for _, opcodeWidth := range []string{"B", "H", "S", "D"} { + source.WriteString("\t" + base + opcodeWidth + " Z1." + sourceWidth + ", P" + string(rune('0'+predicate)) + ", V2\n") + } + } + } + for _, op := range []string{"ZADDQV", "ZANDQV", "ZEORQV", "ZORQV"} { + for predicate, width := range []string{"B", "H", "S", "D"} { + arrangement := map[string]string{"B": "B16", "H": "H8", "S": "S4", "D": "D2"}[width] + source.WriteString("\t" + op + " Z3." + width + ", P" + string(rune('4'+predicate)) + ", V5." + arrangement + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEIntegerReductionCompleteGo127Family(t *testing.T) { + source := arm64SVEIntegerReductionCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveintreduceforms": {Name: "sveintreduceforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2p1"`, + "@llvm.aarch64.sve.andv.nxv16i8", + "@llvm.aarch64.sve.eorv.nxv8i16", + "@llvm.aarch64.sve.orv.nxv4i32", + "@llvm.aarch64.sve.addqv.v2i64.nxv2i64", + "@llvm.aarch64.sve.andqv.v16i8.nxv16i8", + "@llvm.aarch64.sve.eorqv.v8i16.nxv8i16", + "@llvm.aarch64.sve.orqv.v4i32.nxv4i32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE integer reduction lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-integer-reduction.ll", "arm64-sve-integer-reduction.o", ll) + }) + } +} + +func TestTranslateARM64SVEIntegerReductionRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZANDVB Z1.H, P0.M, V2", + "ZEORVH Z1.H, P8, V2", + "ZORVS Z1.S, P0, V2.S4", + "ZADDQV Z1.S, P0, V2.H8", + "ZANDQV Z1.H, P0, V2", + "ZEORQV Z1.D, P0.M, V2.D2", + "ZORQV Z1.Q, P0, V2.B16", + "ZADDQV.Z Z1.B, P0, V2.B16", + "ZANDVB Z1.B, P0", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveintreduce(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveintreduce": {Name: "badsveintreduce", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE integer reduction forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_integer_unary.go b/arm64_lower_sve_integer_unary.go new file mode 100644 index 00000000..09329950 --- /dev/null +++ b/arm64_lower_sve_integer_unary.go @@ -0,0 +1,125 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEIntegerUnarySpec struct { + intrinsic string + unpred bool + minBits int + maxBits int + sve2 bool +} + +var arm64SVEIntegerUnarySpecs = map[Op]arm64SVEIntegerUnarySpec{ + "ZABS": {intrinsic: "abs", minBits: 8}, + "ZCLS": {intrinsic: "cls", minBits: 8}, + "ZCLZ": {intrinsic: "clz", minBits: 8}, + "ZCNOT": {intrinsic: "cnot", minBits: 8, sve2: true}, + "ZCNT": {intrinsic: "cnt", minBits: 8}, + "ZNEG": {intrinsic: "neg", minBits: 8}, + "ZNOT": {intrinsic: "not", minBits: 8}, + "ZRBIT": {intrinsic: "rbit", minBits: 8, sve2: true}, + "ZREV": {intrinsic: "vector.reverse", unpred: true, minBits: 8}, + "ZREVB": {intrinsic: "revb", minBits: 16, sve2: true}, + "ZREVH": {intrinsic: "revh", minBits: 32, sve2: true}, + "ZREVW": {intrinsic: "revw", minBits: 64, sve2: true}, + "ZSQABS": {intrinsic: "sqabs", minBits: 8}, + "ZSQNEG": {intrinsic: "sqneg", minBits: 8}, + "ZSXTB": {intrinsic: "sxtb", minBits: 16}, + "ZSXTH": {intrinsic: "sxth", minBits: 32}, + "ZSXTW": {intrinsic: "sxtw", minBits: 64}, + "ZUXTB": {intrinsic: "uxtb", minBits: 16}, + "ZUXTH": {intrinsic: "uxth", minBits: 32}, + "ZUXTW": {intrinsic: "uxtw", minBits: 64}, + "ZURECPE": {intrinsic: "urecpe", minBits: 32, maxBits: 32}, + "ZURSQRTE": {intrinsic: "ursqrte", minBits: 32, maxBits: 32}, +} + +type arm64SVEIntegerUnaryForm struct { + elementBits int + source int + predicate int + destination int + zeroing bool +} + +func (c *arm64Ctx) lowerARM64SVEIntegerUnary(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEIntegerUnarySpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + form := arm64SVEIntegerUnaryForm{} + if spec.unpred { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects Zn.T, Zd.T: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[1]) + if !sourceOK || !destinationOK || sourceBits != destinationBits || sourceBits < spec.minBits || (spec.maxBits != 0 && sourceBits > spec.maxBits) { + return true, false, fmt.Errorf("arm64 %s vector widths do not match its Go 1.27 form: %q", op, ins.Raw) + } + form = arm64SVEIntegerUnaryForm{elementBits: sourceBits, source: source, destination: destination} + } else { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zn.T, Pg/M|Z, Zd.T: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + predicate, mergeOK := arm64ParseSVEPredicateMode(ins.Args[1], "M", 7) + if !mergeOK { + form.zeroing = true + var zeroOK bool + predicate, zeroOK = arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + if !zeroOK { + return true, false, fmt.Errorf("arm64 %s requires P0..P7/M or P0..P7/Z: %q", op, ins.Raw) + } + } + if !sourceOK || !destinationOK || sourceBits != destinationBits || sourceBits < spec.minBits || (spec.maxBits != 0 && sourceBits > spec.maxBits) { + return true, false, fmt.Errorf("arm64 %s vector widths do not match its Go 1.27 form: %q", op, ins.Raw) + } + form.elementBits = sourceBits + form.source = source + form.predicate = predicate + form.destination = destination + } + return true, false, c.lowerARM64SVEIntegerUnaryForm(spec, form) +} + +func (c *arm64Ctx) lowerARM64SVEIntegerUnaryForm(spec arm64SVEIntegerUnarySpec, form arm64SVEIntegerUnaryForm) error { + source, vectorType, err := c.loadZRegElements(form.source, form.elementBits) + if err != nil { + return err + } + lanes := 128 / form.elementBits + result := c.newTmp() + if spec.unpred { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.nxv%di%d(%s %s)\n", result, vectorType, spec.intrinsic, lanes, form.elementBits, vectorType, source) + } else { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + merge := source + if !form.zeroing { + merge, _, err = c.loadZRegElements(form.destination, form.elementBits) + if err != nil { + return err + } + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, spec.intrinsic, lanes, form.elementBits, vectorType, merge, predicateType, predicate, vectorType, source) + if form.zeroing { + mask := c.newTmp() + zeroed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", mask, predicateType, predicate, vectorType) + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %%%s\n", zeroed, vectorType, result, mask) + result = zeroed + } + } + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) +} diff --git a/arm64_lower_sve_integer_unary_test.go b/arm64_lower_sve_integer_unary_test.go new file mode 100644 index 00000000..7bedc32e --- /dev/null +++ b/arm64_lower_sve_integer_unary_test.go @@ -0,0 +1,106 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEIntegerUnaryCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveintegerunaryforms(SB),$0-0\n") + for _, op := range []string{"ZABS", "ZCLS", "ZCLZ", "ZCNOT", "ZCNT", "ZNEG", "ZNOT", "ZRBIT", "ZSQABS", "ZSQNEG"} { + for index, width := range []string{"B", "H", "S", "D"} { + predicate := string(rune('0' + index)) + for _, mode := range []string{"M", "Z"} { + source.WriteString("\t" + op + " Z1." + width + ", P" + predicate + "." + mode + ", Z2." + width + "\n") + } + } + } + for _, spec := range []struct { + op string + widths []string + }{ + {"ZREVB", []string{"H", "S", "D"}}, + {"ZREVH", []string{"S", "D"}}, + {"ZREVW", []string{"D"}}, + {"ZSXTB", []string{"H", "S", "D"}}, + {"ZUXTB", []string{"H", "S", "D"}}, + {"ZSXTH", []string{"S", "D"}}, + {"ZUXTH", []string{"S", "D"}}, + {"ZSXTW", []string{"D"}}, + {"ZUXTW", []string{"D"}}, + {"ZURECPE", []string{"S"}}, + {"ZURSQRTE", []string{"S"}}, + } { + for index, width := range spec.widths { + predicate := string(rune('0' + index)) + for _, mode := range []string{"M", "Z"} { + source.WriteString("\t" + spec.op + " Z3." + width + ", P" + predicate + "." + mode + ", Z4." + width + "\n") + } + } + } + for _, width := range []string{"B", "H", "S", "D"} { + source.WriteString("\tZREV Z5." + width + ", Z6." + width + "\n") + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEIntegerUnaryCompleteGo127Family(t *testing.T) { + source := arm64SVEIntegerUnaryCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveintegerunaryforms": {Name: "sveintegerunaryforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2"`, "@llvm.aarch64.sve.abs.nxv", "@llvm.aarch64.sve.cnt.nxv", "@llvm.aarch64.sve.rbit.nxv", "@llvm.aarch64.sve.sqabs.nxv", "@llvm.aarch64.sve.sxtb.nxv", "@llvm.aarch64.sve.urecpe.nxv", "@llvm.vector.reverse.nxv"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE integer unary lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-integer-unary.ll", "arm64-sve-integer-unary.o", ll) + }) + } +} + +func TestTranslateARM64SVEIntegerUnaryRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZABS Z1.S, P0, Z2.S", + "ZCNT Z1.S, P8.M, Z2.S", + "ZNEG Z1.S, P0.M, Z2.D", + "ZREVB Z1.B, P0.M, Z2.B", + "ZREVH Z1.H, P0.M, Z2.H", + "ZREVW Z1.S, P0.M, Z2.S", + "ZSXTB Z1.B, P0.M, Z2.B", + "ZUXTH Z1.H, P0.M, Z2.H", + "ZSXTW Z1.S, P0.M, Z2.S", + "ZURECPE Z1.H, P0.M, Z2.H", + "ZURSQRTE Z1.D, P0.M, Z2.D", + "ZREV Z1.S, P0.M, Z2.S", + "ZREV Z1.S, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveintegerunary(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveintegerunary": {Name: "badsveintegerunary", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE integer unary forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_last.go b/arm64_lower_sve_last.go new file mode 100644 index 00000000..463bfc1e --- /dev/null +++ b/arm64_lower_sve_last.go @@ -0,0 +1,97 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVELastSpec struct { + intrinsic string + baseSize int + vectorDst bool +} + +var arm64SVELastSpecs = map[Op]arm64SVELastSpec{ + "ZLASTA": {intrinsic: "lasta", baseSize: 3}, + "ZLASTAW": {intrinsic: "lasta"}, + "ZLASTAB": {intrinsic: "lasta", vectorDst: true}, + "ZLASTAH": {intrinsic: "lasta", baseSize: 1, vectorDst: true}, + "ZLASTAS": {intrinsic: "lasta", baseSize: 2, vectorDst: true}, + "ZLASTAD": {intrinsic: "lasta", baseSize: 3, vectorDst: true}, + "ZLASTB": {intrinsic: "lastb", baseSize: 3}, + "ZLASTBW": {intrinsic: "lastb"}, + "ZLASTBB": {intrinsic: "lastb", vectorDst: true}, + "ZLASTBH": {intrinsic: "lastb", baseSize: 1, vectorDst: true}, + "ZLASTBS": {intrinsic: "lastb", baseSize: 2, vectorDst: true}, + "ZLASTBD": {intrinsic: "lastb", baseSize: 3, vectorDst: true}, +} + +func (c *arm64Ctx) lowerARM64SVELast(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVELastSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zn.B/H/S/D, Pg, scalar destination without a suffix: %q", op, ins.Raw) + } + source, writtenBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + predicate, predicateOK := arm64ParseSVEPredicateBare(ins.Args[1], 7) + if !sourceOK || !predicateOK { + return true, false, fmt.Errorf("arm64 %s requires a Z source and P0..P7: %q", op, ins.Raw) + } + writtenSize := map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[writtenBits] + elementBits := 8 << (spec.baseSize | writtenSize) + + var destination Reg + if spec.vectorDst { + var destinationOK bool + destination, destinationOK = arm64SVEInsertVRegister(ins.Args[2]) + if !destinationOK { + return true, false, fmt.Errorf("arm64 %s destination must be a bare V0..V31 register: %q", op, ins.Raw) + } + } else { + if !arm64SVEIndexScalarRegister(ins.Args[2]) { + return true, false, fmt.Errorf("arm64 %s destination must be R0..R30 or ZR: %q", op, ins.Raw) + } + destination = ins.Args[2].Reg + } + + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + vectorValue, vectorType, err := c.loadZRegElements(source, elementBits) + if err != nil { + return true, false, err + } + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i%d @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", + result, elementBits, spec.intrinsic, lanes, elementBits, predicateType, predicateValue, vectorType, vectorValue) + if spec.vectorDst { + return true, false, c.storeARM64ScalarToVReg(destination, elementBits, "%"+result) + } + value := "%" + result + if elementBits != 64 { + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i%d %s to i64\n", extended, elementBits, value) + value = "%" + extended + } + return true, false, c.storeReg(destination, value) +} + +func (c *arm64Ctx) storeARM64ScalarToVReg(register Reg, elementBits int, value string) error { + vectorType := fmt.Sprintf("<%d x i%d>", 128/elementBits, elementBits) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s zeroinitializer, i%d %s, i64 0\n", inserted, vectorType, elementBits, value) + bytes := "%" + inserted + if elementBits != 8 { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", converted, vectorType, inserted) + bytes = "%" + converted + } + return c.storeVReg(register, bytes) +} diff --git a/arm64_lower_sve_last_test.go b/arm64_lower_sve_last_test.go new file mode 100644 index 00000000..8684b327 --- /dev/null +++ b/arm64_lower_sve_last_test.go @@ -0,0 +1,86 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVELastCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svelastforms(SB),$0-0\n") + for _, selector := range []string{"A", "B"} { + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\tZLAST%s Z1.%s, P0, R2\n", selector, width) + fmt.Fprintf(&source, "\tZLAST%sW Z3.%s, P1, R4\n", selector, width) + fmt.Fprintf(&source, "\tZLAST%sB Z5.%s, P2, V6\n", selector, width) + fmt.Fprintf(&source, "\tZLAST%sH Z7.%s, P3, V8\n", selector, width) + fmt.Fprintf(&source, "\tZLAST%sS Z9.%s, P4, V10\n", selector, width) + fmt.Fprintf(&source, "\tZLAST%sD Z11.%s, P7, V12\n", selector, width) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVELastCompleteGo127Family(t *testing.T) { + source := arm64SVELastCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svelastforms": {Name: "svelastforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.lasta.nxv16i8", + "@llvm.aarch64.sve.lasta.nxv8i16", + "@llvm.aarch64.sve.lastb.nxv4i32", + "@llvm.aarch64.sve.lastb.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE LAST lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-last.ll", "arm64-sve-last.o", ll) + }) + } +} + +func TestTranslateARM64SVELastRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZLASTA Z0.D, P8, R0", + "ZLASTB Z0.D, P0.M, R0", + "ZLASTAW Z0.S, P0, V0", + "ZLASTBW Z0.S, P0, RSP", + "ZLASTAB Z0.B, P0, R0", + "ZLASTBH Z0.H, P0, R0", + "ZLASTAS Z0.S, P0, R0", + "ZLASTBD Z0.D, P0, R0", + "ZLASTA Z0.Q, P0, R0", + "ZLASTA.Z Z0.D, P0, R0", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvelast(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvelast": {Name: "badsvelast", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE LAST forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_logical_family_test.go b/arm64_lower_sve_logical_family_test.go new file mode 100644 index 00000000..47d2e3b0 --- /dev/null +++ b/arm64_lower_sve_logical_family_test.go @@ -0,0 +1,71 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVELogicalCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT sveLogicalFamily(SB), $0-0\n") + for _, op := range []string{"ZAND", "ZBIC", "ZEOR", "ZORR"} { + source.WriteString("\t" + op + " Z1.D, Z2.D, Z3.D\n") + for i, arrangement := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z4.%s, Z5.%s, P%d.M, Z5.%s\n", op, arrangement, arrangement, i, arrangement) + } + if op != "ZBIC" { + source.WriteString("\t" + op + " $0x55, Z6.B, Z6.B\n") + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + ir, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveLogicalFamily": {Name: "sveLogicalFamily", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{" and >5)&7 | (int(word>>8)&3)<<3 | (int(word>>22)&3)<<5 + } else { + encoded = int(word>>16)&7 | (int(word>>19)&3)<<3 | (int(word>>22)&3)<<5 + } + switch { + case encoded >= 64: + elementBits = 64 + case encoded >= 32: + elementBits = 32 + case encoded >= 16: + elementBits = 16 + case encoded >= 8: + elementBits = 8 + default: + return 0, 0, false + } + shift = 2*elementBits - encoded + return elementBits, shift, shift >= 1 && shift <= elementBits +} + +func decodeARM64RawSVELSR(word uint32) (arm64RawSVELSR, bool) { + form := arm64RawSVELSR{op: "ZLSR"} + switch { + case word&0xff3fe000 == 0x04198000: + form.mode = arm64SVELSRWidePredicated + form.elementBits = 8 << (int(word>>22) & 3) + if form.elementBits == 64 { + return arm64RawSVELSR{}, false + } + form.shifts = int(word>>5) & 31 + form.predicate = int(word>>10) & 7 + form.destination = int(word) & 31 + form.source = form.destination + case word&0xff20fc00 == 0x04208400: + form.mode = arm64SVELSRWideUnpredicated + form.elementBits = 8 << (int(word>>22) & 3) + if form.elementBits == 64 { + return arm64RawSVELSR{}, false + } + form.shifts = int(word>>16) & 31 + form.source = int(word>>5) & 31 + form.destination = int(word) & 31 + case word&0xff3fe000 == 0x04118000: + form.mode = arm64SVELSRVectorPredicated + form.elementBits = 8 << (int(word>>22) & 3) + form.shifts = int(word>>5) & 31 + form.predicate = int(word>>10) & 7 + form.destination = int(word) & 31 + form.source = form.destination + case word&0xff3fe000 == 0x04018000: + form.mode = arm64SVELSRImmediatePredicated + var ok bool + form.elementBits, form.shift, ok = decodeARM64SVEShiftImmediate(word, 5) + if !ok { + return arm64RawSVELSR{}, false + } + form.predicate = int(word>>10) & 7 + form.destination = int(word) & 31 + form.source = form.destination + case word&0xff20fc00 == 0x04209400: + form.mode = arm64SVELSRImmediateUnpredicated + var ok bool + form.elementBits, form.shift, ok = decodeARM64SVEShiftImmediate(word, 16) + if !ok { + return arm64RawSVELSR{}, false + } + form.source = int(word>>5) & 31 + form.destination = int(word) & 31 + default: + return arm64RawSVELSR{}, false + } + return form, true +} + +func (c *arm64Ctx) lowerARM64SVELSR(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEShiftSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + + form := arm64RawSVELSR{op: op} + if len(ins.Args) == 3 && ins.Args[0].Kind == OpImm { + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + shift := ins.Args[0].Imm + minimum := int64(0) + if spec.right { + minimum = 1 + } + if ins.Args[0].ImmRaw != "" || !sourceOK || !destinationOK || sourceBits != destinationBits || shift < minimum || shift >= int64(sourceBits) { + return true, false, fmt.Errorf("arm64 %s immediate is outside Go 1.27's element-width range: %q", op, ins.Raw) + } + form = arm64RawSVELSR{op: op, mode: arm64SVELSRImmediateUnpredicated, elementBits: sourceBits, source: source, shift: int(shift), destination: destination} + } else if len(ins.Args) == 4 && ins.Args[0].Kind == OpImm { + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + shift := ins.Args[0].Imm + minimum := int64(0) + if spec.right { + minimum = 1 + } + if ins.Args[0].ImmRaw != "" || !sourceOK || !predicateOK || !destinationOK || source != destination || sourceBits != destinationBits || shift < minimum || shift >= int64(sourceBits) { + return true, false, fmt.Errorf("arm64 %s predicated immediate is outside Go 1.27's destructive element-width form: %q", op, ins.Raw) + } + form = arm64RawSVELSR{op: op, mode: arm64SVELSRImmediatePredicated, elementBits: sourceBits, source: source, predicate: predicate, shift: int(shift), destination: destination} + } else if len(ins.Args) == 3 { + shifts, shiftBits, shiftsOK := arm64ParseSVEZElementReg(ins.Args[0]) + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !shiftsOK || !sourceOK || !destinationOK || shiftBits != 64 || sourceBits == 64 || sourceBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s unpredicated wide form expects Zm.D, Zn.B|H|S, Zd.B|H|S: %q", op, ins.Raw) + } + form = arm64RawSVELSR{op: op, mode: arm64SVELSRWideUnpredicated, elementBits: sourceBits, shifts: shifts, source: source, destination: destination} + } else if len(ins.Args) == 4 { + shifts, shiftBits, shiftsOK := arm64ParseSVEZElementReg(ins.Args[0]) + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !shiftsOK || !sourceOK || !predicateOK || !destinationOK || source != destination || sourceBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s predicated form requires identical destructive source and destination: %q", op, ins.Raw) + } + mode := arm64SVELSRVectorPredicated + if shiftBits == 64 && sourceBits != 64 { + mode = arm64SVELSRWidePredicated + } else if shiftBits != sourceBits { + return true, false, fmt.Errorf("arm64 %s shift register width is incompatible with data elements: %q", op, ins.Raw) + } + form = arm64RawSVELSR{op: op, mode: mode, elementBits: sourceBits, shifts: shifts, source: source, predicate: predicate, destination: destination} + } else { + return true, false, fmt.Errorf("arm64 %s expects one of its five Go 1.27 SVE forms: %q", op, ins.Raw) + } + return true, false, c.lowerRawSVELSR(form) +} + +func (c *arm64Ctx) lowerRawSVELSR(form arm64RawSVELSR) error { + spec, ok := arm64SVEShiftSpecs[form.op] + if !ok { + return fmt.Errorf("unsupported ARM64 SVE shift operation %s", form.op) + } + source, vectorType, err := c.loadZRegElements(form.source, form.elementBits) + if err != nil { + return err + } + var predicate, predicateType string + if form.mode == arm64SVELSRWidePredicated || form.mode == arm64SVELSRVectorPredicated || form.mode == arm64SVELSRImmediatePredicated { + predicate, predicateType, err = c.loadPRegElements(form.predicate, form.elementBits) + } else { + predicate, predicateType, err = c.allTruePRegElements(form.elementBits) + } + if err != nil { + return err + } + + intrinsic := "llvm.aarch64.sve." + spec.intrinsic + shiftType := vectorType + shiftValue := fmt.Sprintf("splat (i%d %d)", form.elementBits, form.shift) + if form.mode == arm64SVELSRWidePredicated || form.mode == arm64SVELSRWideUnpredicated { + intrinsic += ".wide" + shiftType = "" + shiftValue, _, err = c.loadZRegElements(form.shifts, 64) + } else if form.mode == arm64SVELSRVectorPredicated { + shiftValue, _, err = c.loadZRegElements(form.shifts, form.elementBits) + } + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(form.elementBits) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @%s.nxv%di%d(%s %s, %s %s, %s %s)\n", + result, vectorType, intrinsic, lanes, form.elementBits, predicateType, predicate, vectorType, source, shiftType, shiftValue) + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) +} diff --git a/arm64_lower_sve_lsr_test.go b/arm64_lower_sve_lsr_test.go new file mode 100644 index 00000000..b293af94 --- /dev/null +++ b/arm64_lower_sve_lsr_test.go @@ -0,0 +1,209 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64SVEShiftImmediateBits(elementBits, shift, lowBit int) uint32 { + encoded := 2*elementBits - shift + if lowBit == 5 { + return uint32(encoded&7)<<5 | uint32((encoded>>3)&3)<<8 | uint32((encoded>>5)&3)<<22 + } + return uint32(encoded&7)<<16 | uint32((encoded>>3)&3)<<19 | uint32((encoded>>5)&3)<<22 +} + +func encodeARM64RawSVELSRWidePredicated(elementBits, shifts, predicate, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2}[elementBits] + return 0x04198000 | size<<22 | uint32(shifts)<<5 | uint32(predicate)<<10 | uint32(destination) +} + +func encodeARM64RawSVELSRWideUnpredicated(elementBits, shifts, source, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2}[elementBits] + return 0x04208400 | size<<22 | uint32(shifts)<<16 | uint32(source)<<5 | uint32(destination) +} + +func encodeARM64RawSVELSRVectorPredicated(elementBits, shifts, predicate, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + return 0x04118000 | size<<22 | uint32(shifts)<<5 | uint32(predicate)<<10 | uint32(destination) +} + +func encodeARM64RawSVELSRImmediatePredicated(elementBits, shift, predicate, destination int) uint32 { + return 0x04018000 | encodeARM64SVEShiftImmediateBits(elementBits, shift, 5) | uint32(predicate)<<10 | uint32(destination) +} + +func encodeARM64RawSVELSRImmediateUnpredicated(elementBits, shift, source, destination int) uint32 { + return 0x04209400 | encodeARM64SVEShiftImmediateBits(elementBits, shift, 16) | uint32(source)<<5 | uint32(destination) +} + +func TestTranslateARM64SVELSRCompleteGo127Forms(t *testing.T) { + const named = ` +TEXT svelsrnamed(SB),$0-0 + ZLSR Z1.D, Z2.B, P0.M, Z2.B + ZLSR Z3.D, Z4.H, P1.M, Z4.H + ZLSR Z5.D, Z6.S, P2.M, Z6.S + ZLSR Z7.D, Z8.B, Z9.B + ZLSR Z10.D, Z11.H, Z12.H + ZLSR Z13.D, Z14.S, Z15.S + ZLSR Z16.B, Z17.B, P3.M, Z17.B + ZLSR Z18.H, Z19.H, P4.M, Z19.H + ZLSR Z20.S, Z21.S, P5.M, Z21.S + ZLSR Z22.D, Z23.D, P6.M, Z23.D + ZLSR $7, Z24.B, P7.M, Z24.B + ZLSR $15, Z25.H, P0.M, Z25.H + ZLSR $31, Z26.S, P1.M, Z26.S + ZLSR $63, Z27.D, P2.M, Z27.D + ZLSR $1, Z28.B, Z29.B + ZLSR $15, Z28.H, Z29.H + ZLSR $31, Z28.S, Z29.S + ZLSR $63, Z28.D, Z29.D + RET +` + requireARM64SVEGoAssemblerResult(t, named, true) + + var raw strings.Builder + raw.WriteString("TEXT svelsrraw(SB),$0-0\n") + for _, elementBits := range []int{8, 16, 32} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVELSRWidePredicated(elementBits, 1, 2, 3)) + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVELSRWideUnpredicated(elementBits, 4, 5, 6)) + } + for _, elementBits := range []int{8, 16, 32, 64} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVELSRVectorPredicated(elementBits, 7, 3, 8)) + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVELSRImmediatePredicated(elementBits, elementBits, 4, 9)) + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVELSRImmediateUnpredicated(elementBits, elementBits/2, 10, 11)) + } + raw.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, raw.String(), true) + + for name, source := range map[string]string{"named": named, "raw": raw.String()} { + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "svelsr" + name + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve"`, "@llvm.aarch64.sve.lsr.nxv", "@llvm.aarch64.sve.lsr.wide.nxv", "@llvm.aarch64.sve.ptrue"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 SVE LSR lowering for %s/%s omitted %q:\n%s", name, triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-lsr.ll", "arm64-sve-lsr.o", ll) + }) + } + }) + } +} + +func TestARM64RawSVELSRDecoderCoversEveryGo127EncodingField(t *testing.T) { + for _, elementBits := range []int{8, 16, 32} { + for shifts := 0; shifts < 32; shifts++ { + for predicate := 0; predicate < 8; predicate++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVELSRWidePredicated(elementBits, shifts, predicate, destination) + got, ok := decodeARM64RawSVELSR(word) + if !ok || got.mode != arm64SVELSRWidePredicated || got.elementBits != elementBits || got.shifts != shifts || got.predicate != predicate || got.source != destination || got.destination != destination { + t.Fatalf("decoded wide predicated SVE LSR %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + for shifts := 0; shifts < 32; shifts++ { + for source := 0; source < 32; source++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVELSRWideUnpredicated(elementBits, shifts, source, destination) + got, ok := decodeARM64RawSVELSR(word) + if !ok || got.mode != arm64SVELSRWideUnpredicated || got.elementBits != elementBits || got.shifts != shifts || got.source != source || got.destination != destination { + t.Fatalf("decoded wide unpredicated SVE LSR %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } + for _, elementBits := range []int{8, 16, 32, 64} { + for shifts := 0; shifts < 32; shifts++ { + for predicate := 0; predicate < 8; predicate++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVELSRVectorPredicated(elementBits, shifts, predicate, destination) + got, ok := decodeARM64RawSVELSR(word) + if !ok || got.mode != arm64SVELSRVectorPredicated || got.elementBits != elementBits || got.shifts != shifts || got.predicate != predicate || got.source != destination || got.destination != destination { + t.Fatalf("decoded vector predicated SVE LSR %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + for shift := 1; shift <= elementBits; shift++ { + for predicate := 0; predicate < 8; predicate++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVELSRImmediatePredicated(elementBits, shift, predicate, destination) + got, ok := decodeARM64RawSVELSR(word) + if !ok || got.mode != arm64SVELSRImmediatePredicated || got.elementBits != elementBits || got.shift != shift || got.predicate != predicate || got.source != destination || got.destination != destination { + t.Fatalf("decoded immediate predicated SVE LSR %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + for shift := 1; shift <= elementBits; shift++ { + for source := 0; source < 32; source++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVELSRImmediateUnpredicated(elementBits, shift, source, destination) + got, ok := decodeARM64RawSVELSR(word) + if !ok || got.mode != arm64SVELSRImmediateUnpredicated || got.elementBits != elementBits || got.shift != shift || got.source != source || got.destination != destination { + t.Fatalf("decoded immediate unpredicated SVE LSR %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } +} + +func TestARM64SVELSRRejectsReservedAdjacentAndMismatchedDestructiveForms(t *testing.T) { + for _, word := range []uint32{0x04d98400, 0x04208000, 0x04108000, 0x04008000, 0x04209000} { + if _, ok := decodeARM64RawSVELSR(word); ok { + t.Fatalf("SVE LSR decoder accepted reserved/adjacent encoding %#08x", word) + } + } + const invalid = ` +TEXT badsvelsr(SB),$0-0 + ZLSR $7, Z1.S, P0.M, Z2.S + RET +` + requireARM64SVEGoAssemblerResult(t, invalid, false) + file, err := Parse(ArchARM64, invalid) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvelsr": {Name: "badsvelsr", Ret: Void}}}); err == nil { + t.Fatal("translator accepted mismatched destructive SVE LSR operands") + } + + // The Arm encoding permits shifting by the complete element width, and the + // raw decoder above covers it. Go 1.27's encodeShiftTriple currently rejects + // that named boundary with v >= elemBits, so the named translator must match + // the Go oracle instead of claiming a source form Go cannot assemble. + const goRejectedBoundary = ` +TEXT badsvelsrboundary(SB),$0-0 + ZLSR $32, Z1.S, Z2.S + RET +` + requireARM64SVEGoAssemblerResult(t, goRejectedBoundary, false) + file, err = Parse(ArchARM64, goRejectedBoundary) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvelsrboundary": {Name: "badsvelsrboundary", Ret: Void}}}); err == nil { + t.Fatal("translator accepted named SVE LSR element-width boundary rejected by Go 1.27") + } +} diff --git a/arm64_lower_sve_luti.go b/arm64_lower_sve_luti.go new file mode 100644 index 00000000..971183b5 --- /dev/null +++ b/arm64_lower_sve_luti.go @@ -0,0 +1,101 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +type arm64SVELUTIForm struct { + op Op + index, lane, destination int + tables []int + elementBits int +} + +func arm64ParseSVERawIndexedReg(operand Operand) (register, lane int, ok bool) { + if operand.Kind != OpReg { + return 0, 0, false + } + name := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + open := strings.IndexByte(name, '[') + if !strings.HasPrefix(name, "Z") || open <= 1 || !strings.HasSuffix(name, "]") || strings.Contains(name[:open], ".") { + return 0, 0, false + } + register, registerErr := strconv.Atoi(name[1:open]) + lane, laneErr := strconv.Atoi(name[open+1 : len(name)-1]) + return register, lane, registerErr == nil && laneErr == nil && register >= 0 && register <= 31 && lane >= 0 +} + +func (c *arm64Ctx) lowerARM64SVELUTI(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZLUTI2" && op != "ZLUTI4" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[1].Kind != OpRegList { + return true, false, fmt.Errorf("arm64 %s expects Zm[index], [Zn.B|H] or [Zn1.H, Zn2.H], Zd.B|H without a suffix: %q", op, ins.Raw) + } + index, lane, indexOK := arm64ParseSVERawIndexedReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !indexOK || !destinationOK || destinationBits != 8 && destinationBits != 16 { + return true, false, fmt.Errorf("arm64 %s requires a raw indexed Z register and a B/H destination: %q", op, ins.Raw) + } + tableOperands := ins.Args[1].RegList + if len(tableOperands) != 1 && len(tableOperands) != 2 { + return true, false, fmt.Errorf("arm64 %s requires exactly one table, or two H tables for ZLUTI4: %q", op, ins.Raw) + } + tables := make([]int, len(tableOperands)) + for tableIndex, tableOperand := range tableOperands { + table, tableBits, tableOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: tableOperand}) + if !tableOK || tableBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s table and destination widths must match: %q", op, ins.Raw) + } + tables[tableIndex] = table + } + if len(tables) == 2 && tables[1] != (tables[0]+1)%32 { + return true, false, fmt.Errorf("arm64 ZLUTI4 table pair must be consecutive, including Z31-to-Z0 wrapping, as required by Go 1.27: %q", ins.Raw) + } + maxLane := -1 + switch { + case op == "ZLUTI2" && len(tables) == 1 && destinationBits == 8: + maxLane = 3 + case op == "ZLUTI2" && len(tables) == 1 && destinationBits == 16: + maxLane = 7 + case op == "ZLUTI4" && len(tables) == 1 && destinationBits == 8: + maxLane = 1 + case op == "ZLUTI4" && len(tables) == 1 && destinationBits == 16: + maxLane = 3 + case op == "ZLUTI4" && len(tables) == 2 && destinationBits == 16: + maxLane = 3 + } + if maxLane < 0 || lane > maxLane { + return true, false, fmt.Errorf("arm64 %s table count, width, or lane is outside the complete Go 1.27 forms: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVELUTIForm(arm64SVELUTIForm{ + op: op, index: index, lane: lane, tables: tables, destination: destination, elementBits: destinationBits, + }) +} + +func (c *arm64Ctx) lowerARM64SVELUTIForm(form arm64SVELUTIForm) error { + index, indexType, err := c.loadZRegElements(form.index, 8) + if err != nil { + return err + } + tableValues := make([]string, len(form.tables)) + vectorType := "" + for tableIndex, table := range form.tables { + tableValue, tableType, err := c.loadZRegElements(table, form.elementBits) + if err != nil { + return err + } + tableValues[tableIndex], vectorType = tableValue, tableType + } + lanes := 128 / form.elementBits + intrinsic := strings.ToLower(strings.TrimPrefix(string(form.op), "Z")) + ".lane" + result := c.newTmp() + if len(tableValues) == 1 { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, i32 %d)\n", result, vectorType, intrinsic, lanes, form.elementBits, vectorType, tableValues[0], indexType, index, form.lane) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.x2.nxv%di%d(%s %s, %s %s, %s %s, i32 %d)\n", result, vectorType, intrinsic, lanes, form.elementBits, vectorType, tableValues[0], vectorType, tableValues[1], indexType, index, form.lane) + } + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) +} diff --git a/arm64_lower_sve_luti_test.go b/arm64_lower_sve_luti_test.go new file mode 100644 index 00000000..e3d43acb --- /dev/null +++ b/arm64_lower_sve_luti_test.go @@ -0,0 +1,75 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVELUTICompleteGo127Family(t *testing.T) { + const source = `TEXT sveluti(SB),$0-0 + ZLUTI2 Z31[0], [Z0.B], Z1.B + ZLUTI2 Z6[3], [Z23.B], Z13.B + ZLUTI2 Z0[7], [Z31.H], Z30.H + ZLUTI4 Z31[1], [Z2.B], Z10.B + ZLUTI4 Z6[3], [Z23.H], Z13.H + ZLUTI4 Z30[3], [Z31.H, Z0.H], Z13.H + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveluti": {Name: "sveluti", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+lut,+sve,+sve2"`, + "@llvm.aarch64.sve.luti2.lane.nxv16i8", + "@llvm.aarch64.sve.luti2.lane.nxv8i16", + "@llvm.aarch64.sve.luti4.lane.nxv16i8", + "@llvm.aarch64.sve.luti4.lane.nxv8i16", + "@llvm.aarch64.sve.luti4.lane.x2.nxv8i16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s ZLUTI lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-luti.ll", "arm64-sve-luti.o", ll) + }) + } +} + +func TestTranslateARM64SVELUTIRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZLUTI2 Z1[4], [Z2.B], Z3.B", + "ZLUTI2 Z1[8], [Z2.H], Z3.H", + "ZLUTI2 Z1[1], [Z2.S], Z3.S", + "ZLUTI2 Z1[1], [Z2.B], Z3.H", + "ZLUTI4 Z1[2], [Z2.B], Z3.B", + "ZLUTI4 Z1[4], [Z2.H], Z3.H", + "ZLUTI4 Z1[4], [Z2.H, Z3.H], Z4.H", + "ZLUTI4 Z1[1], [Z2.B, Z3.B], Z4.B", + "ZLUTI4 Z1[1], [Z2.H, Z4.H], Z5.H", + "ZLUTI4 Z1[1], [Z2.H, Z3.H, Z4.H], Z5.H", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveluti(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveluti": {Name: "badsveluti", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ZLUTI2/ZLUTI4 forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_mad_msb.go b/arm64_lower_sve_mad_msb.go new file mode 100644 index 00000000..e7b85618 --- /dev/null +++ b/arm64_lower_sve_mad_msb.go @@ -0,0 +1,73 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEMADMSBIntrinsics = map[Op]string{ + "ZMAD": "mad", + "ZMSB": "msb", +} + +type arm64SVEMADMSBForm struct { + intrinsic string + elementBits int + addend int + multiplier int + predicate int + destination int +} + +func (c *arm64Ctx) lowerARM64SVEMADMSB(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEMADMSBIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 SVE MAD/MSB form without a suffix: %q", op, ins.Raw) + } + addend, addendBits, addendOK := arm64ParseSVEZElementReg(ins.Args[0]) + multiplier, multiplierBits, multiplierOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !addendOK || !multiplierOK || !predicateOK || !destinationOK || addendBits != multiplierBits || multiplierBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s operands must use one B/H/S/D width and P0..P7.M: %q", op, ins.Raw) + } + form := arm64SVEMADMSBForm{ + intrinsic: intrinsic, + elementBits: addendBits, + addend: addend, + multiplier: multiplier, + predicate: predicate, + destination: destination, + } + return true, false, c.lowerARM64SVEMADMSBForm(form) +} + +func (c *arm64Ctx) lowerARM64SVEMADMSBForm(form arm64SVEMADMSBForm) error { + destination, vectorType, err := c.loadZRegElements(form.destination, form.elementBits) + if err != nil { + return err + } + multiplier, _, err := c.loadZRegElements(form.multiplier, form.elementBits) + if err != nil { + return err + } + addend, _, err := c.loadZRegElements(form.addend, form.elementBits) + if err != nil { + return err + } + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(form.elementBits) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s, %s %s)\n", + result, vectorType, form.intrinsic, lanes, form.elementBits, predicateType, predicate, vectorType, destination, vectorType, multiplier, vectorType, addend) + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) +} diff --git a/arm64_lower_sve_mad_msb_test.go b/arm64_lower_sve_mad_msb_test.go new file mode 100644 index 00000000..93668ee2 --- /dev/null +++ b/arm64_lower_sve_mad_msb_test.go @@ -0,0 +1,70 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEMADMSBCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svemadmsbforms(SB),$0-0\n") + for _, op := range []string{"ZMAD", "ZMSB"} { + for index, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, P%d.M, Z3.%s\n", op, width, width, index, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svemadmsbforms": {Name: "svemadmsbforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.mad.nxv16i8", + "@llvm.aarch64.sve.mad.nxv2i64", + "@llvm.aarch64.sve.msb.nxv16i8", + "@llvm.aarch64.sve.msb.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE MAD/MSB lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-mad-msb.ll", "arm64-sve-mad-msb.o", ll) + }) + } +} + +func TestTranslateARM64SVEMADMSBRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZMAD Z1.B, Z2.H, P0.M, Z3.H", + "ZMSB Z1.S, Z2.S, P0, Z3.S", + "ZMAD Z1.D, Z2.D, P8.M, Z3.D", + "ZMSB Z1.S, Z2.S, P0.Z, Z3.S", + "ZMAD Z1.S, Z2.S, P0.M", + "ZMSB.Z Z1.S, Z2.S, P0.M, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvemadmsb(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvemadmsb": {Name: "badsvemadmsb", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE MAD/MSB forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_matrix_multiply.go b/arm64_lower_sve_matrix_multiply.go new file mode 100644 index 00000000..99a06848 --- /dev/null +++ b/arm64_lower_sve_matrix_multiply.go @@ -0,0 +1,174 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEIntegerMatrixMultiplyIntrinsics = map[Op]string{ + "ZSMMLA": "smmla", + "ZUMMLA": "ummla", + "ZUSMMLA": "usmmla", +} + +func (c *arm64Ctx) lowerARM64SVEMatrixMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + if _, integer := arm64SVEIntegerMatrixMultiplyIntrinsics[op]; !integer && op != "ZBFMMLA" && op != "ZFMMLA" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects its complete Go 1.27 three-vector form without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != firstBits || !arm64SVEMatrixMultiplyWidthOK(op, firstBits, destinationBits) { + return true, false, fmt.Errorf("arm64 %s has invalid or mismatched Go 1.27 matrix element widths: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVEMatrixMultiplyForm(op, firstBits, destinationBits, first, second, destination) +} + +func arm64SVEMatrixMultiplyWidthOK(op Op, sourceBits, destinationBits int) bool { + switch op { + case "ZSMMLA", "ZUMMLA", "ZUSMMLA": + return sourceBits == 8 && destinationBits == 32 + case "ZBFMMLA": + return sourceBits == 16 && (destinationBits == 16 || destinationBits == 32) + case "ZFMMLA": + return (sourceBits == 8 && (destinationBits == 16 || destinationBits == 32)) || + (sourceBits == 16 && (destinationBits == 16 || destinationBits == 32)) || + (sourceBits == 32 && destinationBits == 32) || + (sourceBits == 64 && destinationBits == 64) + default: + return false + } +} + +func (c *arm64Ctx) lowerARM64SVEMatrixMultiplyForm(op Op, sourceBits, destinationBits, firstReg, secondReg, destinationReg int) error { + if intrinsic, integer := arm64SVEIntegerMatrixMultiplyIntrinsics[op]; integer { + accumulator, destinationType, err := c.loadZRegElements(destinationReg, 32) + if err != nil { + return err + } + first, sourceType, err := c.loadZRegElements(firstReg, 8) + if err != nil { + return err + } + second, _, err := c.loadZRegElements(secondReg, 8) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv4i32(%s %s, %s %s, %s %s)\n", result, destinationType, intrinsic, destinationType, accumulator, sourceType, first, sourceType, second) + return c.storeZRegElements(destinationReg, 32, "%"+result) + } + + destinationScalar := map[int]string{16: "half", 32: "float", 64: "double"}[destinationBits] + sourceScalar := map[int]string{16: "half", 32: "float", 64: "double"}[sourceBits] + if op == "ZBFMMLA" { + sourceScalar = "bfloat" + if destinationBits == 16 { + destinationScalar = "bfloat" + } + } + accumulator, destinationType, err := c.loadARM64SVEMatrixFloatVector(destinationReg, destinationBits, destinationScalar) + if err != nil { + return err + } + first, sourceType, err := c.loadARM64SVEMatrixFloatVector(firstReg, sourceBits, sourceScalar) + if err != nil { + return err + } + second, _, err := c.loadARM64SVEMatrixFloatVector(secondReg, sourceBits, sourceScalar) + if err != nil { + return err + } + result := c.newTmp() + if op == "ZBFMMLA" && destinationBits == 16 { + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(%s %s, %s %s, %s %s)\n", result, destinationType, "bfmmla $0.h, $2.h, $3.h", "=&w,0,w,w", destinationType, accumulator, sourceType, first, sourceType, second) + return c.storeARM64SVEMatrixFloatVector(destinationReg, destinationBits, destinationType, "%"+result) + } + if op == "ZFMMLA" && (sourceBits == 8 || sourceBits == 16 && destinationBits == 16) { + sourceSuffix := map[int]string{8: "b", 16: "h"}[sourceBits] + destinationSuffix := map[int]string{16: "h", 32: "s"}[destinationBits] + assembly := fmt.Sprintf("fmmla $0.%s, $2.%s, $3.%s", destinationSuffix, sourceSuffix, sourceSuffix) + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(%s %s, %s %s, %s %s)\n", result, destinationType, assembly, "=&w,0,w,w", destinationType, accumulator, sourceType, first, sourceType, second) + return c.storeARM64SVEMatrixFloatVector(destinationReg, destinationBits, destinationType, "%"+result) + } + intrinsic := arm64SVEMatrixFloatIntrinsic(op, sourceBits, destinationBits) + fmt.Fprintf(c.b, " %%%s = call %s @%s(%s %s, %s %s, %s %s)\n", result, destinationType, intrinsic, destinationType, accumulator, sourceType, first, sourceType, second) + return c.storeARM64SVEMatrixFloatVector(destinationReg, destinationBits, destinationType, "%"+result) +} + +func arm64SVEMatrixFloatIntrinsic(op Op, sourceBits, destinationBits int) string { + if op == "ZBFMMLA" { + return "llvm.aarch64.sve.bfmmla" + } + suffix := map[int]string{16: "f16", 32: "f32", 64: "f64"}[destinationBits] + lanes := 128 / destinationBits + name := fmt.Sprintf("llvm.aarch64.sve.fmmla.nxv%d%s", lanes, suffix) + if sourceBits != destinationBits { + name += ".nxv8f16" + } + return name +} + +func (c *arm64Ctx) loadARM64SVEMatrixFloatVector(reg, bits int, scalar string) (value, vectorType string, err error) { + integer, integerType, err := c.loadZRegElements(reg, bits) + if err != nil { + return "", "", err + } + lanes := 128 / bits + if bits == 8 { + return integer, integerType, nil + } + vectorType = fmt.Sprintf("", lanes, scalar) + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", converted, integerType, integer, vectorType) + return "%" + converted, vectorType, nil +} + +func (c *arm64Ctx) storeARM64SVEMatrixFloatVector(reg, bits int, vectorType, value string) error { + integerType, _, err := arm64SVEVectorType(bits) + if err != nil { + return err + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", converted, vectorType, value, integerType) + return c.storeZRegElements(reg, bits, "%"+converted) +} + +func arm64SVEMatrixMultiplyFeatures(op Op, ins Instr) []string { + if len(ins.Args) != 3 { + return nil + } + _, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + _, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !sourceOK || !destinationOK || !arm64SVEMatrixMultiplyWidthOK(op, sourceBits, destinationBits) { + return nil + } + switch op { + case "ZSMMLA", "ZUMMLA", "ZUSMMLA": + return []string{"+sve", "+i8mm"} + case "ZBFMMLA": + if destinationBits == 16 { + return []string{"+sve", "+sve-b16mm"} + } + return []string{"+sve", "+bf16"} + case "ZFMMLA": + switch { + case sourceBits == 8 && destinationBits == 16: + return []string{"+sve", "+sve2", "+fp8", "+f8f16mm"} + case sourceBits == 8 && destinationBits == 32: + return []string{"+sve", "+sve2", "+fp8", "+f8f32mm"} + case sourceBits == 16 && destinationBits == 16: + return []string{"+sve", "+sve2p2", "+f16mm"} + case sourceBits == 16 && destinationBits == 32: + return []string{"+sve", "+sve-f16f32mm"} + case sourceBits == 32: + return []string{"+sve", "+f32mm"} + case sourceBits == 64: + return []string{"+sve", "+f64mm"} + } + } + return nil +} diff --git a/arm64_lower_sve_matrix_multiply_test.go b/arm64_lower_sve_matrix_multiply_test.go new file mode 100644 index 00000000..ce2aec83 --- /dev/null +++ b/arm64_lower_sve_matrix_multiply_test.go @@ -0,0 +1,93 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEMatrixMultiplyCompleteGo127Family(t *testing.T) { + const source = ` +TEXT svematrixint(SB),$0-0 + ZSMMLA Z1.B, Z2.B, Z3.S + ZUMMLA Z4.B, Z5.B, Z6.S + ZUSMMLA Z7.B, Z8.B, Z9.S + RET +TEXT svematrixbfloat(SB),$0-0 + ZBFMMLA Z10.H, Z11.H, Z12.H + ZBFMMLA Z13.H, Z14.H, Z15.S + RET +TEXT svematrixfloat(SB),$0-0 + ZFMMLA Z16.B, Z17.B, Z18.H + ZFMMLA Z19.B, Z20.B, Z21.S + ZFMMLA Z22.H, Z23.H, Z24.H + ZFMMLA Z25.H, Z26.H, Z27.S + ZFMMLA Z28.S, Z29.S, Z30.S + ZFMMLA Z31.D, Z0.D, Z1.D + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + sigs := map[string]FuncSig{ + "svematrixint": {Name: "svematrixint", Ret: Void}, + "svematrixbfloat": {Name: "svematrixbfloat", Ret: Void}, + "svematrixfloat": {Name: "svematrixfloat", Ret: Void}, + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+i8mm,+sve"`, + `"target-features"="+bf16,+sve,+sve-b16mm"`, + `"target-features"="+f16mm,+f32mm,+f64mm,+f8f16mm,+f8f32mm,+fp8,+sve,+sve-f16f32mm,+sve2,+sve2p2"`, + "@llvm.aarch64.sve.smmla.", + "@llvm.aarch64.sve.bfmmla", + `asm sideeffect "bfmmla $0.h, $2.h, $3.h"`, + `asm sideeffect "fmmla $0.h, $2.b, $3.b"`, + `asm sideeffect "fmmla $0.s, $2.b, $3.b"`, + `asm sideeffect "fmmla $0.h, $2.h, $3.h"`, + "@llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16", + "@llvm.aarch64.sve.fmmla.nxv2f64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE matrix-multiply lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-matrix-multiply.ll", "arm64-sve-matrix-multiply.o", ll) + }) + } +} + +func TestTranslateARM64SVEMatrixMultiplyRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSMMLA Z1.H, Z2.H, Z3.S", + "ZUMMLA Z1.B, Z2.B, Z3.H", + "ZUSMMLA Z1.B, Z2.S, Z3.S", + "ZBFMMLA Z1.S, Z2.S, Z3.S", + "ZBFMMLA Z1.H, Z2.H, Z3.D", + "ZFMMLA Z1.B, Z2.B, Z3.D", + "ZFMMLA Z1.S, Z2.S, Z3.D", + "ZFMMLA.Z Z1.S, Z2.S, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvematrixmultiply(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvematrixmultiply": {Name: "badsvematrixmultiply", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE matrix-multiply forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_minmax.go b/arm64_lower_sve_minmax.go new file mode 100644 index 00000000..cfc1ff8b --- /dev/null +++ b/arm64_lower_sve_minmax.go @@ -0,0 +1,211 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEMinMaxKind uint8 + +const ( + arm64SVEMinMaxDirect arm64SVEMinMaxKind = iota + arm64SVEMinMaxPairwise + arm64SVEMinMaxReduce + arm64SVEMinMaxQuadReduce +) + +type arm64SVEMinMaxSpec struct { + intrinsic string + kind arm64SVEMinMaxKind + elementBits int + unsignedImm bool +} + +var arm64SVEMinMaxSpecs = map[Op]arm64SVEMinMaxSpec{ + "ZSMAX": {intrinsic: "smax", kind: arm64SVEMinMaxDirect}, + "ZSMAXP": {intrinsic: "smaxp", kind: arm64SVEMinMaxPairwise}, + "ZSMAXQV": {intrinsic: "smaxqv", kind: arm64SVEMinMaxQuadReduce}, + "ZSMAXVB": {intrinsic: "smaxv", kind: arm64SVEMinMaxReduce, elementBits: 8}, + "ZSMAXVH": {intrinsic: "smaxv", kind: arm64SVEMinMaxReduce, elementBits: 16}, + "ZSMAXVS": {intrinsic: "smaxv", kind: arm64SVEMinMaxReduce, elementBits: 32}, + "ZSMAXVD": {intrinsic: "smaxv", kind: arm64SVEMinMaxReduce, elementBits: 64}, + "ZSMIN": {intrinsic: "smin", kind: arm64SVEMinMaxDirect}, + "ZSMINP": {intrinsic: "sminp", kind: arm64SVEMinMaxPairwise}, + "ZSMINQV": {intrinsic: "sminqv", kind: arm64SVEMinMaxQuadReduce}, + "ZSMINVB": {intrinsic: "sminv", kind: arm64SVEMinMaxReduce, elementBits: 8}, + "ZSMINVH": {intrinsic: "sminv", kind: arm64SVEMinMaxReduce, elementBits: 16}, + "ZSMINVS": {intrinsic: "sminv", kind: arm64SVEMinMaxReduce, elementBits: 32}, + "ZSMINVD": {intrinsic: "sminv", kind: arm64SVEMinMaxReduce, elementBits: 64}, + "ZUMAX": {intrinsic: "umax", kind: arm64SVEMinMaxDirect, unsignedImm: true}, + "ZUMAXP": {intrinsic: "umaxp", kind: arm64SVEMinMaxPairwise}, + "ZUMAXQV": {intrinsic: "umaxqv", kind: arm64SVEMinMaxQuadReduce}, + "ZUMAXVB": {intrinsic: "umaxv", kind: arm64SVEMinMaxReduce, elementBits: 8}, + "ZUMAXVH": {intrinsic: "umaxv", kind: arm64SVEMinMaxReduce, elementBits: 16}, + "ZUMAXVS": {intrinsic: "umaxv", kind: arm64SVEMinMaxReduce, elementBits: 32}, + "ZUMAXVD": {intrinsic: "umaxv", kind: arm64SVEMinMaxReduce, elementBits: 64}, + "ZUMIN": {intrinsic: "umin", kind: arm64SVEMinMaxDirect, unsignedImm: true}, + "ZUMINP": {intrinsic: "uminp", kind: arm64SVEMinMaxPairwise}, + "ZUMINQV": {intrinsic: "uminqv", kind: arm64SVEMinMaxQuadReduce}, + "ZUMINVB": {intrinsic: "uminv", kind: arm64SVEMinMaxReduce, elementBits: 8}, + "ZUMINVH": {intrinsic: "uminv", kind: arm64SVEMinMaxReduce, elementBits: 16}, + "ZUMINVS": {intrinsic: "uminv", kind: arm64SVEMinMaxReduce, elementBits: 32}, + "ZUMINVD": {intrinsic: "uminv", kind: arm64SVEMinMaxReduce, elementBits: 64}, +} + +type arm64SVEMinMaxForm struct { + elementBits int + first int + second int + predicate int + destination int + immediate int64 + hasImmediate bool +} + +func (c *arm64Ctx) lowerARM64SVEMinMax(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEMinMaxSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + + switch spec.kind { + case arm64SVEMinMaxDirect, arm64SVEMinMaxPairwise: + form, err := arm64ParseSVEMinMaxDirectForm(op, spec, ins) + if err != nil { + return true, false, err + } + return true, false, c.lowerARM64SVEMinMaxDirectForm(spec, form) + case arm64SVEMinMaxReduce, arm64SVEMinMaxQuadReduce: + form, err := arm64ParseSVEMinMaxReductionForm(op, spec, ins) + if err != nil { + return true, false, err + } + return true, false, c.lowerARM64SVEMinMaxReductionForm(spec, form, ins.Args[2].Reg) + default: + return true, false, fmt.Errorf("arm64 %s has an unknown SVE min/max form", op) + } +} + +func arm64ParseSVEMinMaxDirectForm(op Op, spec arm64SVEMinMaxSpec, ins Instr) (arm64SVEMinMaxForm, error) { + form := arm64SVEMinMaxForm{} + if len(ins.Args) == 3 && ins.Args[0].Kind == OpImm { + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + immediate := ins.Args[0].Imm + validImmediate := spec.kind == arm64SVEMinMaxDirect && ins.Args[0].ImmRaw == "" && !ins.Args[0].ImmIsFloat + if spec.unsignedImm { + validImmediate = validImmediate && immediate >= 0 && immediate <= 255 + } else { + validImmediate = validImmediate && immediate >= -128 && immediate <= 127 + } + if !validImmediate || !firstOK || !destinationOK || first != destination || firstBits != destinationBits { + return form, fmt.Errorf("arm64 %s does not accept this destructive immediate form: %q", op, ins.Raw) + } + form = arm64SVEMinMaxForm{elementBits: firstBits, first: first, destination: destination, immediate: immediate, hasImmediate: true} + return form, nil + } + if len(ins.Args) != 4 { + return form, fmt.Errorf("arm64 %s expects its Go 1.27 predicated%s form: %q", op, map[bool]string{true: " pairwise", false: ""}[spec.kind == arm64SVEMinMaxPairwise], ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits || first != destination { + return form, fmt.Errorf("arm64 %s requires matching-width destructive registers and P0..P7/M: %q", op, ins.Raw) + } + form = arm64SVEMinMaxForm{elementBits: firstBits, first: first, second: second, predicate: predicate, destination: destination} + return form, nil +} + +func arm64ParseSVEMinMaxReductionForm(op Op, spec arm64SVEMinMaxSpec, ins Instr) (arm64SVEMinMaxForm, error) { + form := arm64SVEMinMaxForm{} + if len(ins.Args) != 3 { + return form, fmt.Errorf("arm64 %s expects Zn.T, Pg, Vd%s: %q", op, map[bool]string{true: ".T", false: ""}[spec.kind == arm64SVEMinMaxQuadReduce], ins.Raw) + } + first, elementBits, firstOK := arm64ParseSVEZElementReg(ins.Args[0]) + predicate, predicateOK := arm64ParseSVEPredicate(ins.Args[1]) + destination, destinationOK := arm64ParseVReg(ins.Args[2].Reg) + if !firstOK || !predicateOK || predicate > 7 || !destinationOK || ins.Args[2].Kind != OpReg { + return form, fmt.Errorf("arm64 %s requires a scalable source, bare predicate, and SIMD destination: %q", op, ins.Raw) + } + if spec.kind == arm64SVEMinMaxReduce { + if strings.Contains(string(ins.Args[2].Reg), ".") { + return form, fmt.Errorf("arm64 %s destination must be a bare V register: %q", op, ins.Raw) + } + // The Go table gives every VB/VH/VS/VD spelling a generic Zn.T + // operand. Its encoder ORs the operand size bits into the mnemonic's + // fixed size bits, so the effective hardware width is their bitwise + // union rather than requiring the two suffixes to match. + opcodeSize := map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[spec.elementBits] + sourceSize := map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + elementBits = 8 << (opcodeSize | sourceSize) + } else { + arrangement, arrangementOK := parseARM64VectorArrangement(ins.Args[2].Reg) + if !arrangementOK || arrangement.elementBits != elementBits || arrangement.lanes*arrangement.elementBits != 128 { + return form, fmt.Errorf("arm64 %s destination must be a full-width SIMD vector matching its source elements: %q", op, ins.Raw) + } + } + form = arm64SVEMinMaxForm{elementBits: elementBits, first: first, predicate: predicate, destination: destination} + return form, nil +} + +func (c *arm64Ctx) lowerARM64SVEMinMaxDirectForm(spec arm64SVEMinMaxSpec, form arm64SVEMinMaxForm) error { + first, vectorType, err := c.loadZRegElements(form.first, form.elementBits) + if err != nil { + return err + } + var predicate, predicateType string + if form.hasImmediate { + predicate, predicateType, err = c.allTruePRegElements(form.elementBits) + } else { + predicate, predicateType, err = c.loadPRegElements(form.predicate, form.elementBits) + } + if err != nil { + return err + } + second := fmt.Sprintf("splat (i%d %d)", form.elementBits, form.immediate) + if !form.hasImmediate { + second, _, err = c.loadZRegElements(form.second, form.elementBits) + if err != nil { + return err + } + } + lanes := 128 / form.elementBits + calculated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", calculated, vectorType, spec.intrinsic, lanes, form.elementBits, predicateType, predicate, vectorType, first, vectorType, second) + result := "%" + calculated + if !form.hasImmediate { + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", selected, predicateType, predicate, vectorType, result, vectorType, first) + result = "%" + selected + } + return c.storeZRegElements(form.destination, form.elementBits, result) +} + +func (c *arm64Ctx) lowerARM64SVEMinMaxReductionForm(spec arm64SVEMinMaxSpec, form arm64SVEMinMaxForm, destination Reg) error { + source, vectorType, err := c.loadZRegElements(form.first, form.elementBits) + if err != nil { + return err + } + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + lanes := 128 / form.elementBits + result := c.newTmp() + if spec.kind == arm64SVEMinMaxReduce { + fmt.Fprintf(c.b, " %%%s = call i%d @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, form.elementBits, spec.intrinsic, lanes, form.elementBits, predicateType, predicate, vectorType, source) + fixed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> zeroinitializer, i%d %%%s, i32 0\n", fixed, lanes, form.elementBits, form.elementBits, result) + result = fixed + } else { + fmt.Fprintf(c.b, " %%%s = call <%d x i%d> @llvm.aarch64.sve.%s.v%di%d.nxv%di%d(%s %s, %s %s)\n", result, lanes, form.elementBits, spec.intrinsic, lanes, form.elementBits, lanes, form.elementBits, predicateType, predicate, vectorType, source) + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", bytes, lanes, form.elementBits, result) + return c.storeVReg(destination, "%"+bytes) +} diff --git a/arm64_lower_sve_minmax_test.go b/arm64_lower_sve_minmax_test.go new file mode 100644 index 00000000..38e4311e --- /dev/null +++ b/arm64_lower_sve_minmax_test.go @@ -0,0 +1,88 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEMinMaxCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveminmaxforms(SB),$0-0\n") + for _, base := range []string{"ZSMAX", "ZSMIN", "ZUMAX", "ZUMIN"} { + for index, width := range []string{"B", "H", "S", "D"} { + predicate := string(rune('0' + index)) + source.WriteString("\t" + base + " Z1." + width + ", Z2." + width + ", P" + predicate + ".M, Z2." + width + "\n") + immediate := "-128" + if strings.HasPrefix(base, "ZU") { + immediate = "255" + } + source.WriteString("\t" + base + " $" + immediate + ", Z3." + width + ", Z3." + width + "\n") + source.WriteString("\t" + base + "P Z4." + width + ", Z5." + width + ", P" + predicate + ".M, Z5." + width + "\n") + // Go's generated reduction rows use a generic Zn.T operand for each + // VB/VH/VS/VD spelling. All 4x4 spelling/source-width combinations + // are therefore accepted; the encoded width is the bitwise union of + // the mnemonic's fixed size and the operand size. + for _, opcodeWidth := range []string{"B", "H", "S", "D"} { + source.WriteString("\t" + base + "V" + opcodeWidth + " Z6." + width + ", P" + predicate + ", V7\n") + } + arrangement := map[string]string{"B": "B16", "H": "H8", "S": "S4", "D": "D2"}[width] + source.WriteString("\t" + base + "QV Z8." + width + ", P" + predicate + ", V9." + arrangement + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEMinMaxCompleteGo127Family(t *testing.T) { + source := arm64SVEMinMaxCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveminmaxforms": {Name: "sveminmaxforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2,+sve2p1"`, "@llvm.aarch64.sve.smax.nxv", "@llvm.aarch64.sve.sminp.nxv", "@llvm.aarch64.sve.umaxv.nxv", "@llvm.aarch64.sve.uminqv."} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE min/max lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-minmax.ll", "arm64-sve-minmax.o", ll) + }) + } +} + +func TestTranslateARM64SVEMinMaxRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSMAX $128, Z1.S, Z1.S", + "ZUMAX $-1, Z1.S, Z1.S", + "ZSMIN Z1.S, Z2.S, P0.M, Z3.S", + "ZUMIN $1, Z1.S, Z2.S", + "ZSMAXVB Z1.H, P0.M, V2", + "ZSMAXVB Z1.H, P8, V2", + "ZSMAXVB Z1.H, P0, V2.H8", + "ZUMAXQV Z1.S, P0, V2.H8", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveminmax(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveminmax": {Name: "badsveminmax", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE min/max forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_mixed_saturating_add.go b/arm64_lower_sve_mixed_saturating_add.go new file mode 100644 index 00000000..4515a222 --- /dev/null +++ b/arm64_lower_sve_mixed_saturating_add.go @@ -0,0 +1,46 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEMixedSaturatingAdd(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic := "" + switch op { + case "ZSUQADD": + intrinsic = "suqadd" + case "ZUSQADD": + intrinsic = "usqadd" + default: + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects Zm.B|H|S|D, Zdn.B|H|S|D, P0..P7/M, Zdn.B|H|S|D without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || destinationBits != firstBits || destination != first { + return true, false, fmt.Errorf("arm64 %s requires matching-width destructive B/H/S/D operands and P0..P7/M: %q", op, ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, secondBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, firstBits) + if err != nil { + return true, false, err + } + lanes := 128 / firstBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, intrinsic, lanes, firstBits, predicateType, predicateValue, vectorType, firstValue, vectorType, secondValue) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %%%s, %s %s\n", selected, predicateType, predicateValue, vectorType, result, vectorType, firstValue) + return true, false, c.storeZRegElements(destination, firstBits, "%"+selected) +} diff --git a/arm64_lower_sve_mixed_saturating_add_test.go b/arm64_lower_sve_mixed_saturating_add_test.go new file mode 100644 index 00000000..61f3a1e7 --- /dev/null +++ b/arm64_lower_sve_mixed_saturating_add_test.go @@ -0,0 +1,71 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEMixedSaturatingAddCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svemixedsatadd(SB),$0-0\n") + for opIndex, op := range []string{"ZSUQADD", "ZUSQADD"} { + for widthIndex, width := range []string{"B", "H", "S", "D"} { + destination := opIndex*4 + widthIndex + fmt.Fprintf(&source, "\t%s Z%d.%s, Z%d.%s, P%d.M, Z%d.%s\n", op, destination+16, width, destination, width, widthIndex*2, destination, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svemixedsatadd": {Name: "svemixedsatadd", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.suqadd.nxv16i8", + "@llvm.aarch64.sve.suqadd.nxv2i64", + "@llvm.aarch64.sve.usqadd.nxv16i8", + "@llvm.aarch64.sve.usqadd.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE mixed saturating add lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-mixed-saturating-add.ll", "arm64-sve-mixed-saturating-add.o", ll) + }) + } +} + +func TestTranslateARM64SVEMixedSaturatingAddRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSUQADD Z1.B, Z2.H, P0.M, Z2.H", + "ZSUQADD Z1.S, Z2.S, P8.M, Z2.S", + "ZSUQADD Z1.S, Z2.S, P0.Z, Z2.S", + "ZUSQADD Z1.D, Z2.D, P0.M, Z3.D", + "ZUSQADD Z1.S, Z2.S, Z3.S", + "ZUSQADD.Z Z1.D, Z2.D, P0.M, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvemixedsatadd(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvemixedsatadd": {Name: "badsvemixedsatadd", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's mixed saturating add forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_movprfx.go b/arm64_lower_sve_movprfx.go new file mode 100644 index 00000000..1c5e2582 --- /dev/null +++ b/arm64_lower_sve_movprfx.go @@ -0,0 +1,59 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEMOVPRFX(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZMOVPRFX" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 ZMOVPRFX does not accept an instruction suffix: %q", ins.Raw) + } + if len(ins.Args) == 2 { + source, sourceOK := arm64ParseSVEBareZReg(ins.Args[0]) + destination, destinationOK := arm64ParseSVEBareZReg(ins.Args[1]) + if !sourceOK || !destinationOK { + return true, false, fmt.Errorf("arm64 ZMOVPRFX two-operand form requires bare Z registers: %q", ins.Raw) + } + value, err := c.loadZReg(source) + if err != nil { + return true, false, err + } + return true, false, c.storeZReg(destination, value) + } + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 ZMOVPRFX expects Zn, Zd or Zn.T, Pg.M/Z, Zd.T: %q", ins.Raw) + } + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + predicate, merge := arm64ParseSVEPredicateMode(ins.Args[1], "M", 7) + if !merge { + predicate, _ = arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + } + _, zero := arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + if !sourceOK || !destinationOK || sourceBits != destinationBits || !merge && !zero { + return true, false, fmt.Errorf("arm64 ZMOVPRFX predicated form requires matching vectors and P0..P7.M/Z: %q", ins.Raw) + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, sourceBits) + if err != nil { + return true, false, err + } + sourceValue, vectorType, err := c.loadZRegElements(source, sourceBits) + if err != nil { + return true, false, err + } + fallback := "zeroinitializer" + if merge { + fallback, _, err = c.loadZRegElements(destination, sourceBits) + if err != nil { + return true, false, err + } + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", + result, predicateType, predicateValue, vectorType, sourceValue, vectorType, fallback) + return true, false, c.storeZRegElements(destination, sourceBits, "%"+result) +} diff --git a/arm64_lower_sve_movprfx_test.go b/arm64_lower_sve_movprfx_test.go new file mode 100644 index 00000000..59904e3c --- /dev/null +++ b/arm64_lower_sve_movprfx_test.go @@ -0,0 +1,72 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEMOVPRFXCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svemovprfxforms(SB),$0-0\n\tZMOVPRFX Z0, Z1\n") + for index, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\tZMOVPRFX Z%d.%s, P%d.M, Z%d.%s\n", index+2, width, index, index+6, width) + fmt.Fprintf(&source, "\tZMOVPRFX Z%d.%s, P%d.Z, Z%d.%s\n", index+10, width, index+4, index+14, width) + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svemovprfxforms": {Name: "svemovprfxforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "select ", + "select ", + "select ", + "select ", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE MOVPRFX lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-movprfx.ll", "arm64-sve-movprfx.o", ll) + }) + } +} + +func TestTranslateARM64SVEMOVPRFXRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZMOVPRFX Z0.B, P0.M, Z1.H", + "ZMOVPRFX Z0.H, P0.Z, Z1.S", + "ZMOVPRFX Z0.D, P8.M, Z1.D", + "ZMOVPRFX Z0.D, P0, Z1.D", + "ZMOVPRFX Z0.B, Z1.B", + "ZMOVPRFX Z0, P0.M, Z1", + "ZMOVPRFX.Z Z0, Z1", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvemovprfx(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvemovprfx": {Name: "badsvemovprfx", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE MOVPRFX forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_mul_high.go b/arm64_lower_sve_mul_high.go new file mode 100644 index 00000000..ee72a421 --- /dev/null +++ b/arm64_lower_sve_mul_high.go @@ -0,0 +1,71 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEMultiplyHighIntrinsics = map[Op]string{ + "ZSMULH": "smulh", + "ZUMULH": "umulh", +} + +func arm64SVEMultiplyHighNeedsSVE2(ins Instr) bool { + return len(ins.Args) == 3 +} + +func (c *arm64Ctx) lowerARM64SVEMultiplyHigh(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEMultiplyHighIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || (len(ins.Args) != 3 && len(ins.Args) != 4) { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 vector form without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + if !secondOK || !firstOK || secondBits != firstBits { + return true, false, fmt.Errorf("arm64 %s sources must use one B/H/S/D width: %q", op, ins.Raw) + } + destinationIndex := 2 + predicate := 0 + predicated := len(ins.Args) == 4 + if predicated { + var predicateOK bool + predicate, predicateOK = arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + if !predicateOK { + return true, false, fmt.Errorf("arm64 %s predicated form requires P0..P7.M: %q", op, ins.Raw) + } + destinationIndex = 3 + } + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[destinationIndex]) + if !destinationOK || destinationBits != firstBits || (predicated && destination != first) { + return true, false, fmt.Errorf("arm64 %s destination width and destructive operands do not match: %q", op, ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, firstBits) + if err != nil { + return true, false, err + } + var predicateValue, predicateType string + if predicated { + predicateValue, predicateType, err = c.loadPRegElements(predicate, firstBits) + } else { + predicateValue, predicateType, err = c.allTruePRegElements(firstBits) + intrinsic += ".u" + } + if err != nil { + return true, false, err + } + _, lanes, err := arm64SVEVectorType(firstBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", + result, vectorType, intrinsic, lanes, firstBits, predicateType, predicateValue, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeZRegElements(destination, firstBits, "%"+result) +} diff --git a/arm64_lower_sve_mul_high_test.go b/arm64_lower_sve_mul_high_test.go new file mode 100644 index 00000000..5065500e --- /dev/null +++ b/arm64_lower_sve_mul_high_test.go @@ -0,0 +1,73 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEMultiplyHighCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svemulhighforms(SB),$0-0\n") + for _, op := range []string{"ZSMULH", "ZUMULH"} { + for index, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, P%d.M, Z2.%s\n", op, width, width, index, width) + fmt.Fprintf(&source, "\t%s Z3.%s, Z4.%s, Z5.%s\n", op, width, width, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svemulhighforms": {Name: "svemulhighforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve,+sve2\"", + "@llvm.aarch64.sve.smulh.nxv", + "@llvm.aarch64.sve.smulh.u.nxv", + "@llvm.aarch64.sve.umulh.nxv", + "@llvm.aarch64.sve.umulh.u.nxv", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE multiply-high lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-mul-high.ll", "arm64-sve-mul-high.o", ll) + }) + } +} + +func TestTranslateARM64SVEMultiplyHighRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSMULH Z1.S, Z2.S, P0, Z2.S", + "ZUMULH Z1.S, Z2.S, P8.M, Z2.S", + "ZSMULH Z1.S, Z2.S, P0.M, Z3.S", + "ZUMULH Z1.H, Z2.S, Z3.S", + "ZSMULH Z1.S, Z2.S", + "ZUMULH.Z Z1.S, Z2.S, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvemulhigh(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvemulhigh": {Name: "badsvemulhigh", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE multiply-high forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_multi_narrow.go b/arm64_lower_sve_multi_narrow.go new file mode 100644 index 00000000..6de6fa28 --- /dev/null +++ b/arm64_lower_sve_multi_narrow.go @@ -0,0 +1,128 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEMultiNarrowSpec struct { + intrinsic string + shifted bool + signedInput bool + unsignedOutput bool +} + +var arm64SVEMultiNarrowSpecs = map[Op]arm64SVEMultiNarrowSpec{ + "ZSQCVTN": {intrinsic: "sqcvtn"}, + "ZSQCVTUN": {intrinsic: "sqcvtun"}, + "ZUQCVTN": {intrinsic: "uqcvtn"}, + "ZSQRSHRN": {intrinsic: "sqrshrn", shifted: true, signedInput: true}, + "ZSQRSHRUN": {intrinsic: "sqrshrun", shifted: true, signedInput: true, unsignedOutput: true}, + "ZUQRSHRN": {intrinsic: "uqrshrn", shifted: true, unsignedOutput: true}, +} + +func arm64ParseSVEEvenVectorPair(operand Operand) (first, second, elementBits int, ok bool) { + if operand.Kind != OpRegList || !operand.RegListRange || len(operand.RegList) != 2 { + return 0, 0, 0, false + } + first, elementBits, firstOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: operand.RegList[0]}) + second, secondBits, secondOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: operand.RegList[1]}) + return first, second, elementBits, firstOK && secondOK && secondBits == elementBits && first%2 == 0 && second == first+1 +} + +func (c *arm64Ctx) lowerARM64SVEMultiNarrow(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEMultiNarrowSpecs[op] + if !ok { + return false, false, nil + } + wantArgs := 2 + if spec.shifted { + wantArgs = 3 + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != wantArgs { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 even/odd x2 range narrowing form without a suffix: %q", op, ins.Raw) + } + sourceOperand := 0 + shift := int64(0) + if spec.shifted { + if ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || ins.Args[0].ImmIsFloat { + return true, false, fmt.Errorf("arm64 %s requires a concrete shift immediate: %q", op, ins.Raw) + } + shift, sourceOperand = ins.Args[0].Imm, 1 + } + first, second, sourceBits, sourceOK := arm64ParseSVEEvenVectorPair(ins.Args[sourceOperand]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[sourceOperand+1]) + validWidths := sourceBits == 32 && destinationBits == 16 + if spec.shifted { + validWidths = sourceBits == 16 && destinationBits == 8 || sourceBits == 32 && destinationBits == 16 + if shift < 1 || shift > int64(destinationBits) { + validWidths = false + } + } + if !sourceOK || !destinationOK || !validWidths { + return true, false, fmt.Errorf("arm64 %s requires an even/odd S-to-H pair, or a legal H-to-B shift pair: %q", op, ins.Raw) + } + firstValue, sourceType, err := c.loadZRegElements(first, sourceBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, sourceBits) + if err != nil { + return true, false, err + } + destinationType, _, err := arm64SVEVectorType(destinationBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + if spec.shifted && destinationBits == 8 { + result = c.lowerARM64SVEMultiShiftNarrowBytes(spec, firstValue, secondValue, shift) + } else if spec.shifted { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.x2.nxv%di%d(%s %s, %s %s, i32 %d)\n", result, destinationType, spec.intrinsic, 128/sourceBits, sourceBits, sourceType, firstValue, sourceType, secondValue, shift) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.x2.nxv4i32(%s %s, %s %s)\n", result, destinationType, spec.intrinsic, sourceType, firstValue, sourceType, secondValue) + } + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEMultiShiftNarrowBytes(spec arm64SVEMultiNarrowSpec, first, second string, shift int64) string { + narrowed := make([]string, 2) + for index, source := range []string{first, second} { + wide := c.newTmp() + extension := "zext" + shiftOp := "lshr" + if spec.signedInput { + extension, shiftOp = "sext", "ashr" + } + fmt.Fprintf(c.b, " %%%s = %s %s to \n", wide, extension, source) + rounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %%%s, splat (i32 %d)\n", rounded, wide, int64(1)<<(shift-1)) + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %%%s, splat (i32 %d)\n", shifted, shiftOp, rounded, shift) + + minimum, maximum := int64(-128), int64(127) + comparisonPrefix := "s" + if spec.unsignedOutput { + minimum, maximum = 0, 255 + if !spec.signedInput { + comparisonPrefix = "u" + } + } + clampedLow := shifted + if minimum != 0 || spec.signedInput { + below := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %slt %%%s, splat (i32 %d)\n", below, comparisonPrefix, shifted, minimum) + clampedLow = c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %%%s, splat (i32 %d), %%%s\n", clampedLow, below, minimum, shifted) + } + above := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %sgt %%%s, splat (i32 %d)\n", above, comparisonPrefix, clampedLow, maximum) + clamped := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %%%s, splat (i32 %d), %%%s\n", clamped, above, maximum, clampedLow) + narrowed[index] = c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %%%s to \n", narrowed[index], clamped) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.vector.interleave2.nxv16i8( %%%s, %%%s)\n", result, narrowed[0], narrowed[1]) + return result +} diff --git a/arm64_lower_sve_multi_narrow_test.go b/arm64_lower_sve_multi_narrow_test.go new file mode 100644 index 00000000..b1be471c --- /dev/null +++ b/arm64_lower_sve_multi_narrow_test.go @@ -0,0 +1,89 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEMultiNarrowCompleteGo127Family(t *testing.T) { + const source = `TEXT svemultinarrow(SB),$0-0 + ZSQCVTN [Z0.S-Z1.S], Z2.H + ZSQCVTUN [Z14.S-Z15.S], Z16.H + ZUQCVTN [Z30.S-Z31.S], Z0.H + ZSQRSHRN $1, [Z0.H-Z1.H], Z2.B + ZSQRSHRN $8, [Z30.H-Z31.H], Z3.B + ZSQRSHRN $1, [Z2.S-Z3.S], Z4.H + ZSQRSHRN $16, [Z28.S-Z29.S], Z5.H + ZSQRSHRUN $1, [Z4.H-Z5.H], Z6.B + ZSQRSHRUN $8, [Z26.H-Z27.H], Z7.B + ZSQRSHRUN $1, [Z6.S-Z7.S], Z8.H + ZSQRSHRUN $16, [Z24.S-Z25.S], Z9.H + ZUQRSHRN $1, [Z8.H-Z9.H], Z10.B + ZUQRSHRN $8, [Z22.H-Z23.H], Z11.B + ZUQRSHRN $1, [Z10.S-Z11.S], Z12.H + ZUQRSHRN $16, [Z20.S-Z21.S], Z13.H + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svemultinarrow": {Name: "svemultinarrow", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2p1"`, + "@llvm.aarch64.sve.sqcvtn.x2.nxv4i32", + "@llvm.aarch64.sve.sqcvtun.x2.nxv4i32", + "@llvm.aarch64.sve.uqcvtn.x2.nxv4i32", + "@llvm.aarch64.sve.sqrshrn.x2.nxv4i32", + "@llvm.aarch64.sve.sqrshrun.x2.nxv4i32", + "@llvm.aarch64.sve.uqrshrn.x2.nxv4i32", + "sext ", + "zext ", + "icmp slt ", + "icmp ugt ", + "@llvm.vector.interleave2.nxv16i8", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s multi-vector narrow lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-multi-narrow.ll", "arm64-sve-multi-narrow.o", ll) + }) + } +} + +func TestTranslateARM64SVEMultiNarrowRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSQCVTN [Z1.S-Z2.S], Z3.H", + "ZSQCVTUN [Z2.S, Z3.S], Z4.H", + "ZUQCVTN [Z2.H-Z3.H], Z4.B", + "ZSQRSHRN $0, [Z2.H-Z3.H], Z4.B", + "ZSQRSHRN $9, [Z2.H-Z3.H], Z4.B", + "ZSQRSHRUN $17, [Z2.S-Z3.S], Z4.H", + "ZUQRSHRN $1, [Z2.D-Z3.D], Z4.S", + "ZUQRSHRN $1, [Z2.H-Z5.H], Z6.B", + "ZUQRSHRN.Z $1, [Z2.H-Z3.H], Z4.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvemultinarrow(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvemultinarrow": {Name: "badsvemultinarrow", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's multi-vector narrowing forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_multiply.go b/arm64_lower_sve_multiply.go new file mode 100644 index 00000000..706c6e7b --- /dev/null +++ b/arm64_lower_sve_multiply.go @@ -0,0 +1,203 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +type arm64SVEMultiplyMode uint8 + +const ( + arm64SVEMultiplyPredicated arm64SVEMultiplyMode = iota + arm64SVEMultiplyUnpredicated + arm64SVEMultiplyLane + arm64SVEMultiplyImmediate +) + +type arm64RawSVEMultiply struct { + mode arm64SVEMultiplyMode + elementBits int + first int + second int + predicate int + laneVector int + lane int + immediate int + destination int +} + +func decodeARM64RawSVEMultiply(word uint32) (arm64RawSVEMultiply, bool) { + form := arm64RawSVEMultiply{} + switch { + case word&0xff3fe000 == 0x04100000: + form.mode = arm64SVEMultiplyPredicated + form.elementBits = 8 << (int(word>>22) & 3) + form.destination = int(word) & 31 + form.first = form.destination + form.second = int(word>>5) & 31 + form.predicate = int(word>>10) & 7 + case word&0xff20fc00 == 0x04206000: + form.mode = arm64SVEMultiplyUnpredicated + form.elementBits = 8 << (int(word>>22) & 3) + form.destination = int(word) & 31 + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + case word&0xffa0fc00 == 0x4420f800: + form.mode = arm64SVEMultiplyLane + form.elementBits = 16 + form.laneVector = int(word>>16) & 7 + form.lane = int(word>>19)&3 | (int(word>>22)&1)<<2 + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + case word&0xffe0fc00 == 0x44a0f800: + form.mode = arm64SVEMultiplyLane + form.elementBits = 32 + form.laneVector = int(word>>16) & 7 + form.lane = int(word>>19) & 3 + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + case word&0xffe0fc00 == 0x44e0f800: + form.mode = arm64SVEMultiplyLane + form.elementBits = 64 + form.laneVector = int(word>>16) & 15 + form.lane = int(word>>20) & 1 + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + case word&0xff3fe000 == 0x2530c000: + form.mode = arm64SVEMultiplyImmediate + form.elementBits = 8 << (int(word>>22) & 3) + form.destination = int(word) & 31 + form.first = form.destination + form.immediate = int(int8(word >> 5)) + default: + return arm64RawSVEMultiply{}, false + } + return form, true +} + +func arm64ParseSVEZIndexedElementReg(operand Operand) (index, elementBits, lane int, ok bool) { + index, elementBits, lane, ok = arm64ParseSVEZIndexedElementRegUnbounded(operand) + if !ok { + return 0, 0, 0, false + } + maxVector, vectorOK := map[int]int{16: 7, 32: 7, 64: 15}[elementBits] + maxLane, laneOK := map[int]int{16: 7, 32: 3, 64: 1}[elementBits] + return index, elementBits, lane, vectorOK && laneOK && index <= maxVector && lane <= maxLane +} + +func arm64ParseSVEZIndexedElementRegUnbounded(operand Operand) (index, elementBits, lane int, ok bool) { + if operand.Kind != OpReg { + return 0, 0, 0, false + } + name := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + dot := strings.IndexByte(name, '.') + open := strings.IndexByte(name, '[') + if dot <= 1 || open <= dot+1 || !strings.HasSuffix(name, "]") || !strings.HasPrefix(name, "Z") { + return 0, 0, 0, false + } + index, err := strconv.Atoi(name[1:dot]) + if err != nil { + return 0, 0, 0, false + } + elementBits, bitsOK := map[string]int{"B": 8, "H": 16, "S": 32, "D": 64}[name[dot+1:open]] + lane, err = strconv.Atoi(name[open+1 : len(name)-1]) + if err != nil || !bitsOK { + return 0, 0, 0, false + } + return index, elementBits, lane, index >= 0 && index <= 31 && lane >= 0 +} + +func arm64SVEMultiplyNeedsSVE2(ins Instr) bool { + return len(ins.Args) == 3 && len(ins.Args) > 0 && ins.Args[0].Kind != OpImm +} + +func (c *arm64Ctx) lowerARM64SVEMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZMUL" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 ZMUL does not accept an instruction suffix: %q", ins.Raw) + } + + form := arm64RawSVEMultiply{} + if len(ins.Args) == 4 { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits || first != destination { + return true, false, fmt.Errorf("arm64 ZMUL predicated expects Zm.T, Zdn.T, Pg.M, Zdn.T with identical destructive operands: %q", ins.Raw) + } + form = arm64RawSVEMultiply{mode: arm64SVEMultiplyPredicated, elementBits: firstBits, first: first, second: second, predicate: predicate, destination: destination} + } else if len(ins.Args) == 3 && ins.Args[0].Kind == OpImm { + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + immediate := ins.Args[0].Imm + if ins.Args[0].ImmRaw != "" || !firstOK || !destinationOK || first != destination || firstBits != destinationBits || immediate < -128 || immediate > 127 { + return true, false, fmt.Errorf("arm64 ZMUL immediate expects a signed 8-bit value and identical Zdn.T operands: %q", ins.Raw) + } + form = arm64RawSVEMultiply{mode: arm64SVEMultiplyImmediate, elementBits: firstBits, first: first, immediate: int(immediate), destination: destination} + } else if len(ins.Args) == 3 { + if laneVector, laneBits, lane, laneOK := arm64ParseSVEZIndexedElementReg(ins.Args[0]); laneOK { + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !firstOK || !destinationOK || laneBits != firstBits || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZMUL lane operands must share H, S, or D width: %q", ins.Raw) + } + form = arm64RawSVEMultiply{mode: arm64SVEMultiplyLane, elementBits: firstBits, first: first, laneVector: laneVector, lane: lane, destination: destination} + } else { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZMUL vector operands must share one element width: %q", ins.Raw) + } + form = arm64RawSVEMultiply{mode: arm64SVEMultiplyUnpredicated, elementBits: firstBits, first: first, second: second, destination: destination} + } + } else { + return true, false, fmt.Errorf("arm64 ZMUL expects one of the six Go 1.27 SVE forms: %q", ins.Raw) + } + return true, false, c.lowerRawSVEMultiply(form) +} + +func (c *arm64Ctx) lowerRawSVEMultiply(form arm64RawSVEMultiply) error { + first, vectorType, err := c.loadZRegElements(form.first, form.elementBits) + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(form.elementBits) + if err != nil { + return err + } + result := c.newTmp() + switch form.mode { + case arm64SVEMultiplyPredicated: + second, _, err := c.loadZRegElements(form.second, form.elementBits) + if err != nil { + return err + } + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.mul.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, lanes, form.elementBits, predicateType, predicate, vectorType, first, vectorType, second) + case arm64SVEMultiplyUnpredicated: + second, _, err := c.loadZRegElements(form.second, form.elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = mul %s %s, %s\n", result, vectorType, first, second) + case arm64SVEMultiplyLane: + laneVector, _, err := c.loadZRegElements(form.laneVector, form.elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.mul.lane.nxv%di%d(%s %s, %s %s, i32 %d)\n", result, vectorType, lanes, form.elementBits, vectorType, first, vectorType, laneVector, form.lane) + case arm64SVEMultiplyImmediate: + fmt.Fprintf(c.b, " %%%s = mul %s %s, splat (i%d %d)\n", result, vectorType, first, form.elementBits, form.immediate) + default: + return fmt.Errorf("unknown ARM64 SVE MUL mode %d", form.mode) + } + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) +} diff --git a/arm64_lower_sve_multiply_accumulate.go b/arm64_lower_sve_multiply_accumulate.go new file mode 100644 index 00000000..e7470f11 --- /dev/null +++ b/arm64_lower_sve_multiply_accumulate.go @@ -0,0 +1,97 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEMultiplyAccumulateIntrinsics = map[Op]string{ + "ZMLA": "mla", + "ZMLS": "mls", +} + +type arm64SVEMultiplyAccumulateForm struct { + intrinsic string + elementBits int + multiplier int + multiplicand int + predicate int + lane int + destination int + indexed bool +} + +func arm64SVEMultiplyAccumulateNeedsSVE2(ins Instr) bool { + return len(ins.Args) == 3 +} + +func (c *arm64Ctx) lowerARM64SVEMultiplyAccumulate(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEMultiplyAccumulateIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || (len(ins.Args) != 3 && len(ins.Args) != 4) { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 multiply-accumulate form without a suffix: %q", op, ins.Raw) + } + form := arm64SVEMultiplyAccumulateForm{intrinsic: intrinsic} + if len(ins.Args) == 4 { + multiplier, multiplierBits, multiplierOK := arm64ParseSVEZElementReg(ins.Args[0]) + multiplicand, multiplicandBits, multiplicandOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !multiplierOK || !multiplicandOK || !predicateOK || !destinationOK || multiplierBits != multiplicandBits || multiplicandBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s predicated operands must use one B/H/S/D width and P0..P7.M: %q", op, ins.Raw) + } + form.elementBits = multiplierBits + form.multiplier = multiplier + form.multiplicand = multiplicand + form.predicate = predicate + form.destination = destination + } else { + multiplier, multiplierBits, lane, multiplierOK := arm64ParseSVEZIndexedElementReg(ins.Args[0]) + multiplicand, multiplicandBits, multiplicandOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !multiplierOK || !multiplicandOK || !destinationOK || multiplierBits != multiplicandBits || multiplicandBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s indexed operands must use one H/S/D width and an encodable lane: %q", op, ins.Raw) + } + form.elementBits = multiplierBits + form.multiplier = multiplier + form.multiplicand = multiplicand + form.lane = lane + form.destination = destination + form.indexed = true + } + return true, false, c.lowerARM64SVEMultiplyAccumulateForm(form) +} + +func (c *arm64Ctx) lowerARM64SVEMultiplyAccumulateForm(form arm64SVEMultiplyAccumulateForm) error { + accumulator, vectorType, err := c.loadZRegElements(form.destination, form.elementBits) + if err != nil { + return err + } + multiplicand, _, err := c.loadZRegElements(form.multiplicand, form.elementBits) + if err != nil { + return err + } + multiplier, _, err := c.loadZRegElements(form.multiplier, form.elementBits) + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(form.elementBits) + if err != nil { + return err + } + result := c.newTmp() + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.lane.nxv%di%d(%s %s, %s %s, %s %s, i32 %d)\n", + result, vectorType, form.intrinsic, lanes, form.elementBits, vectorType, accumulator, vectorType, multiplicand, vectorType, multiplier, form.lane) + } else { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s, %s %s)\n", + result, vectorType, form.intrinsic, lanes, form.elementBits, predicateType, predicate, vectorType, accumulator, vectorType, multiplicand, vectorType, multiplier) + } + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) +} diff --git a/arm64_lower_sve_multiply_accumulate_long.go b/arm64_lower_sve_multiply_accumulate_long.go new file mode 100644 index 00000000..e18d1579 --- /dev/null +++ b/arm64_lower_sve_multiply_accumulate_long.go @@ -0,0 +1,141 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64RawSVEMultiplyAccumulateLong struct { + op Op + mode arm64SVEUMULLBMode + sourceBits int + first int + second int + laneVector int + lane int + destination int +} + +var arm64SVEMultiplyAccumulateLongIntrinsics = map[Op]string{ + "ZSMLALB": "smlalb", + "ZSMLALT": "smlalt", + "ZUMLALB": "umlalb", + "ZUMLALT": "umlalt", + "ZSMLSLB": "smlslb", + "ZSMLSLT": "smlslt", + "ZUMLSLB": "umlslb", + "ZUMLSLT": "umlslt", +} + +var arm64SVEMultiplyAccumulateLongOpsBySelector = [...]Op{ + "ZSMLALB", "ZSMLALT", "ZUMLALB", "ZUMLALT", + "ZSMLSLB", "ZSMLSLT", "ZUMLSLB", "ZUMLSLT", +} + +// decodeARM64RawSVEMultiplyAccumulateLong covers all SVE2 signed/unsigned +// multiply-add/subtract-long bottom/top vector and indexed forms emitted by the +// Go 1.27 ARM64 assembler. +func decodeARM64RawSVEMultiplyAccumulateLong(word uint32) (arm64RawSVEMultiplyAccumulateLong, bool) { + form := arm64RawSVEMultiplyAccumulateLong{} + switch { + case word&0xff20e000 == 0x44004000: + size := int(word>>22) & 3 + if size == 0 { + return arm64RawSVEMultiplyAccumulateLong{}, false + } + form.mode = arm64SVEUMULLBVector + form.sourceBits = 4 << size + form.second = int(word>>16) & 31 + form.op = arm64SVEMultiplyAccumulateLongOpsBySelector[int(word>>10)&7] + case word&0xffe0c000 == 0x44a08000: + form.mode = arm64SVEUMULLBLane + form.sourceBits = 16 + form.laneVector = int(word>>16) & 7 + form.lane = int(word>>11)&1 | (int(word>>19)&3)<<1 + selector := int(word>>10)&1 | (int(word>>12)&3)<<1 + form.op = arm64SVEMultiplyAccumulateLongOpsBySelector[selector] + case word&0xffe0c000 == 0x44e08000: + form.mode = arm64SVEUMULLBLane + form.sourceBits = 32 + form.laneVector = int(word>>16) & 15 + form.lane = int(word>>11)&1 | (int(word>>20)&1)<<1 + selector := int(word>>10)&1 | (int(word>>12)&3)<<1 + form.op = arm64SVEMultiplyAccumulateLongOpsBySelector[selector] + default: + return arm64RawSVEMultiplyAccumulateLong{}, false + } + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + return form, true +} + +func (c *arm64Ctx) lowerARM64SVEMultiplyAccumulateLong(op Op, ins Instr) (ok bool, terminated bool, err error) { + if _, ok := arm64SVEMultiplyAccumulateLongIntrinsics[op]; !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects one of the five Go 1.27 SVE2 forms: %q", op, ins.Raw) + } + form := arm64RawSVEMultiplyAccumulateLong{op: op} + if laneVector, laneBits, lane, laneOK := arm64ParseSVEUMULLBIndexedReg(ins.Args[0]); laneOK { + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !firstOK || !destinationOK || firstBits != laneBits || destinationBits != 2*laneBits { + return true, false, fmt.Errorf("arm64 %s indexed operands must widen H to S or S to D: %q", op, ins.Raw) + } + form.mode = arm64SVEUMULLBLane + form.sourceBits = firstBits + form.first = first + form.laneVector = laneVector + form.lane = lane + form.destination = destination + } else { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != firstBits || firstBits == 64 || destinationBits != 2*firstBits { + return true, false, fmt.Errorf("arm64 %s vector operands must widen B/H/S to H/S/D: %q", op, ins.Raw) + } + form.mode = arm64SVEUMULLBVector + form.sourceBits = firstBits + form.first = first + form.second = second + form.destination = destination + } + return true, false, c.lowerRawSVEMultiplyAccumulateLong(form) +} + +func (c *arm64Ctx) lowerRawSVEMultiplyAccumulateLong(form arm64RawSVEMultiplyAccumulateLong) error { + intrinsic, ok := arm64SVEMultiplyAccumulateLongIntrinsics[form.op] + if !ok { + return fmt.Errorf("unsupported ARM64 SVE2 multiply-accumulate-long operation %s", form.op) + } + destinationBits := form.sourceBits * 2 + accumulator, destinationType, err := c.loadZRegElements(form.destination, destinationBits) + if err != nil { + return err + } + first, sourceType, err := c.loadZRegElements(form.first, form.sourceBits) + if err != nil { + return err + } + secondIndex := form.second + if form.mode == arm64SVEUMULLBLane { + secondIndex = form.laneVector + } + second, _, err := c.loadZRegElements(secondIndex, form.sourceBits) + if err != nil { + return err + } + _, destinationLanes, err := arm64SVEVectorType(destinationBits) + if err != nil { + return err + } + result := c.newTmp() + if form.mode == arm64SVEUMULLBVector { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, destinationType, intrinsic, destinationLanes, destinationBits, destinationType, accumulator, sourceType, first, sourceType, second) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.lane.nxv%di%d(%s %s, %s %s, %s %s, i32 %d)\n", result, destinationType, intrinsic, destinationLanes, destinationBits, destinationType, accumulator, sourceType, first, sourceType, second, form.lane) + } + return c.storeZRegElements(form.destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_multiply_accumulate_long_test.go b/arm64_lower_sve_multiply_accumulate_long_test.go new file mode 100644 index 00000000..f62a0d9f --- /dev/null +++ b/arm64_lower_sve_multiply_accumulate_long_test.go @@ -0,0 +1,146 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +var arm64SVEMultiplyAccumulateLongOps = []Op{ + "ZSMLALB", "ZSMLALT", "ZUMLALB", "ZUMLALT", + "ZSMLSLB", "ZSMLSLT", "ZUMLSLB", "ZUMLSLT", +} + +func encodeARM64RawSVEMultiplyAccumulateLongVector(op Op, sourceBits, second, first, destination int) uint32 { + selector := arm64SVEMultiplyAccumulateLongSelector(op) + size := map[int]uint32{8: 1, 16: 2, 32: 3}[sourceBits] + return 0x44004000 | size<<22 | uint32(second)<<16 | uint32(selector)<<10 | uint32(first)<<5 | uint32(destination) +} + +func encodeARM64RawSVEMultiplyAccumulateLongLane(op Op, sourceBits, laneVector, lane, first, destination int) uint32 { + selector := arm64SVEMultiplyAccumulateLongSelector(op) + opBits := uint32(selector&1)<<10 | uint32(selector&6)<<11 + if sourceBits == 16 { + return 0x44a08000 | uint32(laneVector)<<16 | uint32(lane&1)<<11 | uint32(lane>>1)<<19 | opBits | uint32(first)<<5 | uint32(destination) + } + return 0x44e08000 | uint32(laneVector)<<16 | uint32(lane&1)<<11 | uint32(lane>>1)<<20 | opBits | uint32(first)<<5 | uint32(destination) +} + +func arm64SVEMultiplyAccumulateLongSelector(op Op) int { + for selector, candidate := range arm64SVEMultiplyAccumulateLongOps { + if op == candidate { + return selector + } + } + panic("unknown SVE multiply-accumulate-long op " + op) +} + +func TestTranslateARM64RawSVEUMLALBReportedEncoding(t *testing.T) { + const source = "TEXT sveumlalbreported(SB),$0-0\n\tWORD $0x44d24a20\n\tRET\n" + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"sveumlalbreported": {Name: "sveumlalbreported", Ret: Void}}}); err != nil { + t.Fatal(err) + } +} + +func TestTranslateARM64SVEMultiplyAccumulateLongCompleteGo127Forms(t *testing.T) { + var named strings.Builder + named.WriteString("TEXT svemlalnamed(SB),$0-0\n") + for _, op := range arm64SVEMultiplyAccumulateLongOps { + fmt.Fprintf(&named, "\t%s Z2.B, Z1.B, Z0.H\n", op) + fmt.Fprintf(&named, "\t%s Z4.H, Z3.H, Z0.S\n", op) + fmt.Fprintf(&named, "\t%s Z6.S, Z5.S, Z0.D\n", op) + fmt.Fprintf(&named, "\t%s Z7.H[7], Z8.H, Z0.S\n", op) + fmt.Fprintf(&named, "\t%s Z15.S[3], Z9.S, Z0.D\n", op) + } + named.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, named.String(), true) + + var raw strings.Builder + raw.WriteString("TEXT svemlalraw(SB),$0-0\n") + for _, op := range arm64SVEMultiplyAccumulateLongOps { + for _, sourceBits := range []int{8, 16, 32} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEMultiplyAccumulateLongVector(op, sourceBits, 2, 1, 0)) + } + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEMultiplyAccumulateLongLane(op, 16, 7, 7, 8, 0)) + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEMultiplyAccumulateLongLane(op, 32, 15, 3, 9, 0)) + } + raw.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, raw.String(), true) + + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for name, source := range map[string]string{"named": named.String(), "raw": raw.String()} { + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "svemlal" + name + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2"`, "@llvm.aarch64.sve.smlalb", "@llvm.aarch64.sve.umlalt", "@llvm.aarch64.sve.smlslt", "@llvm.aarch64.sve.umlslb.lane"} { + if !strings.Contains(ir, want) { + t.Fatalf("SVE2 multiply-accumulate-long lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, triple, "arm64-sve-mlal.ll", "arm64-sve-mlal.o", ir) + }) + } + }) + } +} + +func TestARM64RawSVEMultiplyAccumulateLongDecoderCoversEveryEncodingField(t *testing.T) { + for _, op := range arm64SVEMultiplyAccumulateLongOps { + for _, sourceBits := range []int{8, 16, 32} { + for second := 0; second < 32; second++ { + for first := 0; first < 32; first++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVEMultiplyAccumulateLongVector(op, sourceBits, second, first, destination) + got, ok := decodeARM64RawSVEMultiplyAccumulateLong(word) + if !ok || got.op != op || got.mode != arm64SVEUMULLBVector || got.sourceBits != sourceBits || got.second != second || got.first != first || got.destination != destination { + t.Fatalf("decoded vector %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } + for _, domain := range []struct{ bits, vectors, lanes int }{{16, 8, 8}, {32, 16, 4}} { + for laneVector := 0; laneVector < domain.vectors; laneVector++ { + for lane := 0; lane < domain.lanes; lane++ { + for first := 0; first < 32; first++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVEMultiplyAccumulateLongLane(op, domain.bits, laneVector, lane, first, destination) + got, ok := decodeARM64RawSVEMultiplyAccumulateLong(word) + if !ok || got.op != op || got.mode != arm64SVEUMULLBLane || got.sourceBits != domain.bits || got.laneVector != laneVector || got.lane != lane || got.first != first || got.destination != destination { + t.Fatalf("decoded lane %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } + } + } +} + +func TestARM64SVEMultiplyAccumulateLongRejectsReservedAndInvalidForms(t *testing.T) { + for _, word := range []uint32{0x44004000, 0x44006000, 0x44a0c000, 0x44e0c000} { + if _, ok := decodeARM64RawSVEMultiplyAccumulateLong(word); ok { + t.Fatalf("decoder accepted reserved/adjacent encoding %#08x", word) + } + } + const invalid = "TEXT badsvemlal(SB),$0-0\n\tZUMLALB Z1.B[0], Z2.B, Z3.H\n\tZUMLALB Z1.S, Z2.S, Z3.S\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, invalid, false) +} diff --git a/arm64_lower_sve_multiply_accumulate_test.go b/arm64_lower_sve_multiply_accumulate_test.go new file mode 100644 index 00000000..f0169caf --- /dev/null +++ b/arm64_lower_sve_multiply_accumulate_test.go @@ -0,0 +1,79 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEMultiplyAccumulateCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svemultiplyaccumulateforms(SB),$0-0\n") + for _, op := range []string{"ZMLA", "ZMLS"} { + for index, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, P%d.M, Z3.%s\n", op, width, width, index, width) + } + for index, width := range []string{"H", "S", "D"} { + maximumVector := []int{7, 7, 15}[index] + maximumLane := []int{7, 3, 1}[index] + fmt.Fprintf(&source, "\t%s Z%d.%s[%d], Z4.%s, Z5.%s\n", op, maximumVector, width, maximumLane, width, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svemultiplyaccumulateforms": {Name: "svemultiplyaccumulateforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve,+sve2\"", + "@llvm.aarch64.sve.mla.nxv16i8", + "@llvm.aarch64.sve.mla.lane.nxv8i16", + "@llvm.aarch64.sve.mls.nxv2i64", + "@llvm.aarch64.sve.mls.lane.nxv4i32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE multiply-accumulate lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-multiply-accumulate.ll", "arm64-sve-multiply-accumulate.o", ll) + }) + } +} + +func TestTranslateARM64SVEMultiplyAccumulateRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZMLA Z1.B, Z2.H, P0.M, Z3.H", + "ZMLS Z1.S, Z2.S, P0, Z3.S", + "ZMLA Z1.D, Z2.D, P8.M, Z3.D", + "ZMLS Z1.B[0], Z2.B, Z3.B", + "ZMLA Z8.H[0], Z2.H, Z3.H", + "ZMLS Z7.H[8], Z2.H, Z3.H", + "ZMLA Z7.S[3], Z2.D, Z3.D", + "ZMLS.Z Z1.S, Z2.S, P0.M, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvemultiplyaccumulate(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvemultiplyaccumulate": {Name: "badsvemultiplyaccumulate", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE multiply-accumulate forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_multiply_add_tail.go b/arm64_lower_sve_multiply_add_tail.go new file mode 100644 index 00000000..73ec82ac --- /dev/null +++ b/arm64_lower_sve_multiply_add_tail.go @@ -0,0 +1,43 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEMultiplyAddTailOps = map[Op]string{ + "ZMADPT": "madpt", + "ZMLAPT": "mlapt", +} + +func (c *arm64Ctx) lowerARM64SVEMultiplyAddTail(op Op, ins Instr) (ok bool, terminated bool, err error) { + mnemonic, ok := arm64SVEMultiplyAddTailOps[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects three D-width vector operands without a suffix: %q", op, ins.Raw) + } + firstSource, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[0]) + secondSource, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !firstOK || !secondOK || !destinationOK || firstBits != 64 || secondBits != 64 || destinationBits != 64 { + return true, false, fmt.Errorf("arm64 %s requires three D-width scalable-vector operands: %q", op, ins.Raw) + } + destinationValue, vectorType, err := c.loadZRegElements(destination, 64) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(secondSource, 64) + if err != nil { + return true, false, err + } + firstValue, _, err := c.loadZRegElements(firstSource, 64) + if err != nil { + return true, false, err + } + result := c.newTmp() + assembly := mnemonic + " $0.d, $2.d, $3.d" + fmt.Fprintf(c.b, " %%%s = call %s asm sideeffect %q, %q(%s %s, %s %s, %s %s)\n", result, vectorType, assembly, "=&w,0,w,w", vectorType, destinationValue, vectorType, secondValue, vectorType, firstValue) + return true, false, c.storeZRegElements(destination, 64, "%"+result) +} diff --git a/arm64_lower_sve_multiply_add_tail_test.go b/arm64_lower_sve_multiply_add_tail_test.go new file mode 100644 index 00000000..b345809e --- /dev/null +++ b/arm64_lower_sve_multiply_add_tail_test.go @@ -0,0 +1,64 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEMultiplyAddTailCompleteGo127Family(t *testing.T) { + source := ` +TEXT svemultiplyaddtail(SB),$0-0 + ZMADPT Z7.D, Z6.D, Z23.D + ZMLAPT Z8.D, Z9.D, Z24.D + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svemultiplyaddtail": {Name: "svemultiplyaddtail", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+cpa,+sve"`, + `asm sideeffect "madpt $0.d, $2.d, $3.d", "=&w,0,w,w"`, + `asm sideeffect "mlapt $0.d, $2.d, $3.d", "=&w,0,w,w"`, + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE multiply-add-tail lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-multiply-add-tail.ll", "arm64-sve-multiply-add-tail.o", ll) + }) + } +} + +func TestTranslateARM64SVEMultiplyAddTailRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZMADPT Z1.S, Z2.S, Z3.S", + "ZMADPT Z1.D, Z2.S, Z3.D", + "ZMLAPT Z1.H, Z2.H, Z3.H", + "ZMLAPT Z1.D, Z2.D", + "ZMADPT.Z Z1.D, Z2.D, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvemultiplyaddtail(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvemultiplyaddtail": {Name: "badsvemultiplyaddtail", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's multiply-add-tail forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_multiply_long_extra_test.go b/arm64_lower_sve_multiply_long_extra_test.go new file mode 100644 index 00000000..cbc281f4 --- /dev/null +++ b/arm64_lower_sve_multiply_long_extra_test.go @@ -0,0 +1,153 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64RawSVEMultiplyLongVector(op Op, sourceBits, second, first, destination int) uint32 { + spec := arm64SVEMultiplyLongSpecs[op] + size := map[int]uint32{8: 1, 16: 2, 32: 3}[sourceBits] + return spec.vectorBase | size<<22 | uint32(second)<<16 | uint32(first)<<5 | uint32(destination) +} + +func encodeARM64RawSVEMultiplyLongLane(op Op, sourceBits, laneVector, lane, first, destination int) uint32 { + spec := arm64SVEMultiplyLongSpecs[op] + if sourceBits == 16 { + return spec.laneHBase | uint32(laneVector)<<16 | uint32(lane&1)<<11 | uint32(lane>>1)<<19 | uint32(first)<<5 | uint32(destination) + } + return spec.laneSBase | uint32(laneVector)<<16 | uint32(lane&1)<<11 | uint32(lane>>1)<<20 | uint32(first)<<5 | uint32(destination) +} + +func TestTranslateARM64SVEMultiplyLongExtraCompleteGo127Family(t *testing.T) { + regular := []string{ + "ZSMULLB", "ZSMULLT", "ZUMULLT", + "ZSQDMULLB", "ZSQDMULLT", + "ZSQDMLALB", "ZSQDMLALT", + "ZSQDMLSLB", "ZSQDMLSLT", + } + bottomTop := []string{"ZSQDMLALBT", "ZSQDMLSLBT"} + widths := []struct { + source, destination string + }{{"B", "H"}, {"H", "S"}, {"S", "D"}} + + var source strings.Builder + source.WriteString("TEXT svemultiplylongextra(SB),$0-0\n") + for _, op := range regular { + for _, width := range widths { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, Z3.%s\n", op, width.source, width.source, width.destination) + } + fmt.Fprintf(&source, "\t%s Z7.H[7], Z4.H, Z5.S\n", op) + fmt.Fprintf(&source, "\t%s Z15.S[3], Z6.S, Z7.D\n", op) + } + for _, op := range bottomTop { + for _, width := range widths { + fmt.Fprintf(&source, "\t%s Z8.%s, Z9.%s, Z10.%s\n", op, width.source, width.source, width.destination) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svemultiplylongextra": {Name: "svemultiplylongextra", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.smullb.", + "@llvm.aarch64.sve.umullt.lane.", + "@llvm.aarch64.sve.sqdmullt.", + "@llvm.aarch64.sve.sqdmlalb.lane.", + "@llvm.aarch64.sve.sqdmlslbt.", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE multiply-long lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-multiply-long-extra.ll", "arm64-sve-multiply-long-extra.o", ll) + }) + } +} + +func TestTranslateARM64SVEMultiplyLongExtraRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSMULLB Z1.D, Z2.D, Z3.Q", + "ZSMULLT Z8.H[0], Z1.H, Z2.S", + "ZUMULLT Z1.H, Z2.H, Z3.D", + "ZSQDMULLB Z1.B[0], Z2.B, Z3.H", + "ZSQDMLALBT Z1.H[0], Z2.H, Z3.S", + "ZSQDMLSLBT Z1.B, Z2.B, Z3.S", + "ZSQDMLALT.Z Z1.B, Z2.B, Z3.H", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvemultiplylongextra(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvemultiplylongextra": {Name: "badsvemultiplylongextra", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE multiply-long forms", instruction) + } + }) + } +} + +func TestTranslateARM64SVEMultiplyLongRawEncodings(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svemultiplylongraw(SB),$0-0\n") + for _, op := range arm64SVEMultiplyLongOps { + spec := arm64SVEMultiplyLongSpecs[op] + for _, sourceBits := range []int{8, 16, 32} { + word := encodeARM64RawSVEMultiplyLongVector(op, sourceBits, 1, 2, 3) + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + got, ok := decodeARM64RawSVEUMULLB(word) + if !ok || got.op != op || got.mode != arm64SVEUMULLBVector || got.sourceBits != sourceBits || got.second != 1 || got.first != 2 || got.destination != 3 { + t.Fatalf("decoded vector %s %#08x as %+v, ok=%v", op, word, got, ok) + } + } + if spec.laneHBase == 0 { + continue + } + for _, domain := range []struct { + bits, vector, lane int + }{{16, 7, 7}, {32, 15, 3}} { + word := encodeARM64RawSVEMultiplyLongLane(op, domain.bits, domain.vector, domain.lane, 4, 5) + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + got, ok := decodeARM64RawSVEUMULLB(word) + if !ok || got.op != op || got.mode != arm64SVEUMULLBLane || got.sourceBits != domain.bits || got.laneVector != domain.vector || got.lane != domain.lane || got.first != 4 || got.destination != 5 { + t.Fatalf("decoded indexed %s %#08x as %+v, ok=%v", op, word, got, ok) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svemultiplylongraw": {Name: "svemultiplylongraw", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-multiply-long-raw.ll", "arm64-sve-multiply-long-raw.o", ll) + }) + } +} diff --git a/arm64_lower_sve_multiply_test.go b/arm64_lower_sve_multiply_test.go new file mode 100644 index 00000000..173c0082 --- /dev/null +++ b/arm64_lower_sve_multiply_test.go @@ -0,0 +1,174 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64RawSVEMultiplyPredicated(elementBits, second, predicate, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + return 0x04100000 | size<<22 | uint32(second)<<5 | uint32(predicate)<<10 | uint32(destination) +} + +func encodeARM64RawSVEMultiplyUnpredicated(elementBits, second, first, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + return 0x04206000 | size<<22 | uint32(second)<<16 | uint32(first)<<5 | uint32(destination) +} + +func encodeARM64RawSVEMultiplyLane(elementBits, laneVector, lane, first, destination int) uint32 { + word := uint32(0x44e0f800) + switch elementBits { + case 16: + word = 0x4420f800 | uint32(laneVector)<<16 | uint32(lane&3)<<19 | uint32(lane>>2)<<22 + case 32: + word = 0x44a0f800 | uint32(laneVector)<<16 | uint32(lane)<<19 + case 64: + word |= uint32(laneVector)<<16 | uint32(lane)<<20 + } + return word | uint32(first)<<5 | uint32(destination) +} + +func encodeARM64RawSVEMultiplyImmediate(elementBits, immediate, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + return 0x2530c000 | size<<22 | uint32(uint8(int8(immediate)))<<5 | uint32(destination) +} + +func TestTranslateARM64SVEMultiplyCompleteGo127Forms(t *testing.T) { + const named = ` +TEXT svemulnamed(SB),$0-0 + ZMUL Z31.B, Z0.B, P0.M, Z0.B + ZMUL Z30.H, Z1.H, P1.M, Z1.H + ZMUL Z29.S, Z2.S, P2.M, Z2.S + ZMUL Z28.D, Z3.D, P7.M, Z3.D + ZMUL Z27.B, Z4.B, Z5.B + ZMUL Z26.H, Z6.H, Z7.H + ZMUL Z25.S, Z8.S, Z9.S + ZMUL Z24.D, Z10.D, Z11.D + ZMUL Z7.H[7], Z12.H, Z13.H + ZMUL Z6.S[3], Z14.S, Z15.S + ZMUL Z15.D[1], Z16.D, Z17.D + ZMUL $-128, Z18.B, Z18.B + ZMUL $127, Z19.H, Z19.H + ZMUL $-1, Z20.S, Z20.S + ZMUL $0, Z21.D, Z21.D + RET +` + requireARM64SVEGoAssemblerResult(t, named, true) + + var raw strings.Builder + raw.WriteString("TEXT svemulraw(SB),$0-0\n") + for _, elementBits := range []int{8, 16, 32, 64} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEMultiplyPredicated(elementBits, 1, 2, 3)) + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEMultiplyUnpredicated(elementBits, 4, 5, 6)) + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEMultiplyImmediate(elementBits, -128+elementBits, 7)) + } + for _, form := range []struct{ bits, vector, lane int }{{16, 7, 7}, {32, 7, 3}, {64, 15, 1}} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEMultiplyLane(form.bits, form.vector, form.lane, 8, 9)) + } + raw.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, raw.String(), true) + + for name, source := range map[string]string{"named": named, "raw": raw.String()} { + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "svemul" + name + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2"`, "@llvm.aarch64.sve.mul.nxv", "@llvm.aarch64.sve.mul.lane.nxv", " mul ", lanes, spec.memoryBits) + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ldnf1.nxv%di%d(%s %s, ptr %%%s)\n", + loaded, loadedType, lanes, spec.memoryBits, predicateType, predicateValue, pointer) + value := "%" + loaded + if spec.memoryBits < elementBits { + vectorType, _, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + extended := c.newTmp() + extension := "zext" + if spec.signed { + extension = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", extended, extension, loadedType, value, vectorType) + value = "%" + extended + } + return true, false, c.storeZRegElements(vectors[0], elementBits, value) +} diff --git a/arm64_lower_sve_non_faulting_memory_test.go b/arm64_lower_sve_non_faulting_memory_test.go new file mode 100644 index 00000000..38a94bec --- /dev/null +++ b/arm64_lower_sve_non_faulting_memory_test.go @@ -0,0 +1,96 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVENonFaultingMemoryCompleteGo127Forms() string { + return `TEXT svenonfaultingmemoryforms(SB),$0-0 + ZLDNF1B (-VL*8)(R14), P4.Z, [Z13.B] + ZLDNF1B (VL*7)(RSP), P3.Z, [Z12.H] + ZLDNF1B (VL*0)(R4), P2.Z, [Z11.S] + ZLDNF1B (-VL*2)(R5), P1.Z, [Z10.D] + ZLDNF1H (VL*7)(R14), P4.Z, [Z13.H] + ZLDNF1H (-VL*8)(RSP), P3.Z, [Z12.S] + ZLDNF1H (VL*0)(R4), P2.Z, [Z11.D] + ZLDNF1W (-VL*8)(R14), P4.Z, [Z13.S] + ZLDNF1W (VL*7)(RSP), P3.Z, [Z12.D] + ZLDNF1D (-VL*8)(R14), P4.Z, [Z13.D] + ZLDNF1SB (VL*7)(RSP), P3.Z, [Z12.H] + ZLDNF1SB (VL*0)(R4), P2.Z, [Z11.S] + ZLDNF1SB (-VL*2)(R5), P1.Z, [Z10.D] + ZLDNF1SH (VL*7)(R14), P4.Z, [Z13.S] + ZLDNF1SH (-VL*8)(RSP), P3.Z, [Z12.D] + ZLDNF1SW (VL*0)(R4), P2.Z, [Z11.D] + RET +` +} + +func TestTranslateARM64SVENonFaultingMemoryCompleteGo127Family(t *testing.T) { + source := arm64SVENonFaultingMemoryCompleteGo127Forms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svenonfaultingmemoryforms": {Name: "svenonfaultingmemoryforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.ldnf1.nxv16i8", + "@llvm.aarch64.sve.ldnf1.nxv8i16", + "@llvm.aarch64.sve.ldnf1.nxv4i32", + "@llvm.aarch64.sve.ldnf1.nxv2i64", + " sext ", lanes, spec.memoryBits) + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv%di%d.nxv%di%d(%s %s, %s %s, i64 %s)\n", + loaded, loadedType, lanes, spec.memoryBits, lanes, elementBits, predicateType, predicateValue, baseType, bases, offset) + value := "%" + loaded + if spec.memoryBits < elementBits { + extended := c.newTmp() + extension := "zext" + if spec.signed { + extension = "sext" + } + vectorType, _, _ := arm64SVEVectorType(elementBits) + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", extended, extension, loadedType, value, vectorType) + value = "%" + extended + } + return true, false, c.storeZRegElements(destination, elementBits, value) + } + if spec.signed || elementBits != spec.memoryBits { + return true, false, fmt.Errorf("arm64 %s contiguous form requires its natural %d-bit arrangement: %q", op, spec.memoryBits, ins.Raw) + } + address, err := c.arm64SVENonTemporalContiguousAddress(memory, spec.memoryBits, 1) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + vectorType, _, _ := arm64SVEVectorType(elementBits) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ldnt1.nxv%di%d(%s %s, ptr %%%s)\n", + result, vectorType, lanes, elementBits, predicateType, predicateValue, pointer) + return true, false, c.storeZRegElements(destination, elementBits, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVENonTemporalStore(op Op, spec arm64SVENonTemporalMemorySpec, ins Instr) (ok bool, terminated bool, err error) { + if ins.Args[0].Kind != OpRegList || ins.Args[2].Kind != OpMem { + return true, false, fmt.Errorf("arm64 %s requires vector-list, predicate, memory operands: %q", op, ins.Raw) + } + vectors, elementBits, vectorsOK := arm64ParseSVEConsecutiveVectorList(ins.Args[0]) + if !vectorsOK { + return true, false, fmt.Errorf("arm64 %s requires a consecutive, uniformly arranged Z register list: %q", op, ins.Raw) + } + if predicate, predicateOK := arm64ParseSVEPredicateBare(ins.Args[1], 7); predicateOK { + if len(vectors) != 1 { + return true, false, fmt.Errorf("arm64 %s ordinary predicate form requires one source vector: %q", op, ins.Raw) + } + return c.lowerARM64SVENonTemporalSingleStore(op, spec, ins.Args[2].Mem, predicate, vectors[0], elementBits, ins) + } + predicate, predicateOK := arm64ParseSVENonTemporalPN(ins.Args[1], false) + if !predicateOK || (len(vectors) != 2 && len(vectors) != 4) || elementBits != spec.memoryBits { + return true, false, fmt.Errorf("arm64 %s PN form requires PN8..PN15 and two or four same-width source vectors: %q", op, ins.Raw) + } + address, err := c.arm64SVENonTemporalContiguousAddress(ins.Args[2].Mem, spec.memoryBits, len(vectors)) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + counter, err := c.loadPNReg(predicate) + if err != nil { + return true, false, err + } + vectorType, _, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + values := make([]string, 0, len(vectors)) + for _, vector := range vectors { + value, _, err := c.loadZRegElements(vector, elementBits) + if err != nil { + return true, false, err + } + values = append(values, fmt.Sprintf("%s %s", vectorType, value)) + } + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.stnt1.pn.x%d.nxv%di%d(%s, target(\"aarch64.svcount\") %s, ptr %%%s)\n", + len(vectors), 128/elementBits, elementBits, strings.Join(values, ", "), counter, pointer) + return true, false, nil +} + +func (c *arm64Ctx) lowerARM64SVENonTemporalSingleStore(op Op, spec arm64SVENonTemporalMemorySpec, memory MemRef, predicate, source, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + if elementBits < spec.memoryBits { + return true, false, fmt.Errorf("arm64 %s source arrangement is narrower than its memory element: %q", op, ins.Raw) + } + value, vectorType, err := c.loadZRegElements(source, elementBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + if vectorBase, vectorBaseBits, vectorBaseOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}); vectorBaseOK { + if vectorBaseBits != elementBits || (elementBits != 32 && elementBits != 64) || !arm64SVENonTemporalVectorBaseAddressOK(memory) { + return true, false, fmt.Errorf("arm64 %s vector-base form has widths or address operands outside its Go 1.27 table: %q", op, ins.Raw) + } + bases, baseType, err := c.loadZRegElements(vectorBase, vectorBaseBits) + if err != nil { + return true, false, err + } + offset, err := c.loadReg(memory.Base) + if err != nil { + return true, false, err + } + storedType := vectorType + stored := value + if spec.memoryBits < elementBits { + storedType = fmt.Sprintf("", lanes, spec.memoryBits) + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", truncated, vectorType, value, storedType) + stored = "%" + truncated + } + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv%di%d.nxv%di%d(%s %s, %s %s, %s %s, i64 %s)\n", + lanes, spec.memoryBits, lanes, elementBits, storedType, stored, predicateType, predicateValue, baseType, bases, offset) + return true, false, nil + } + if elementBits != spec.memoryBits { + return true, false, fmt.Errorf("arm64 %s contiguous form requires its natural %d-bit arrangement: %q", op, spec.memoryBits, ins.Raw) + } + address, err := c.arm64SVENonTemporalContiguousAddress(memory, spec.memoryBits, 1) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.stnt1.nxv%di%d(%s %s, %s %s, ptr %%%s)\n", + lanes, elementBits, vectorType, value, predicateType, predicateValue, pointer) + return true, false, nil +} + +func arm64ParseSVEConsecutiveVectorList(operand Operand) (vectors []int, elementBits int, ok bool) { + if operand.Kind != OpRegList || len(operand.RegList) == 0 { + return nil, 0, false + } + vectors = make([]int, len(operand.RegList)) + for i, register := range operand.RegList { + vector, bits, valid := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: register}) + if !valid || i > 0 && (bits != elementBits || vector != vectors[i-1]+1) { + return nil, 0, false + } + vectors[i] = vector + elementBits = bits + } + return vectors, elementBits, true +} + +func arm64ParseSVENonTemporalPN(operand Operand, zeroing bool) (int, bool) { + if operand.Kind != OpReg { + return 0, false + } + text := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + wantSuffix := "" + if zeroing { + wantSuffix = ".Z" + } + if !strings.HasSuffix(text, wantSuffix) { + return 0, false + } + name := strings.TrimSuffix(text, wantSuffix) + if strings.Contains(name, ".") || !strings.HasPrefix(name, "PN") { + return 0, false + } + var index int + if _, err := fmt.Sscanf(name, "PN%d", &index); err != nil || index < 8 || index > 15 { + return 0, false + } + return index, true +} + +func arm64SVENonTemporalVectorBaseAddressOK(memory MemRef) bool { + return memory.Sym == "" && memory.Segment == "" && memory.Off == 0 && memory.OffRaw == "" && memory.IndexExt == "" && memory.Scale == 1 && + isARM64GeneralOrZeroReg(memory.Base) && memory.Base != SP && memory.Base != Reg("RSP") +} + +func (c *arm64Ctx) arm64SVENonTemporalContiguousAddress(memory MemRef, elementBits, vectorCount int) (string, error) { + if memory.Index != "" { + if _, _, vectorIndex := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}); vectorIndex { + return "", fmt.Errorf("contiguous form does not accept a scalable-vector base") + } + return c.arm64SVERegisterOffsetAddress(memory, int64(elementBits/8)) + } + minimum, maximum := int64(-8), int64(7) + if vectorCount == 2 { + minimum, maximum = -16, 14 + } else if vectorCount == 3 { + minimum, maximum = -24, 21 + } else if vectorCount == 4 { + minimum, maximum = -32, 28 + } else if vectorCount != 1 { + return "", fmt.Errorf("contiguous form requires one, two, three, or four vectors") + } + if memory.OffRaw != "" { + multiplier, parsed := parseVectorLengthScaleExpr(memory.OffRaw) + if !parsed || multiplier%int64(vectorCount) != 0 { + return "", fmt.Errorf("MUL VL immediate must be a multiple of %d", vectorCount) + } + } + return c.arm64SVEVLAddress(memory, minimum, maximum, 16) +} + +func arm64SVEAggregateType(vectorType string, count int) string { + values := make([]string, count) + for i := range values { + values[i] = vectorType + } + return "{ " + strings.Join(values, ", ") + " }" +} diff --git a/arm64_lower_sve_non_temporal_memory_test.go b/arm64_lower_sve_non_temporal_memory_test.go new file mode 100644 index 00000000..a5e1e468 --- /dev/null +++ b/arm64_lower_sve_non_temporal_memory_test.go @@ -0,0 +1,164 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVENonTemporalMemoryCompleteGo127Forms() string { + return `TEXT svenontemporalmemoryforms(SB),$0-0 + ZLDNT1B (R6)(R14), P4.Z, [Z13.B] + ZLDNT1B (R6)(Z7.S), P4.Z, [Z13.S] + ZLDNT1B (R6)(Z7.D), P4.Z, [Z13.D] + ZLDNT1B (-VL*2)(R14), P4.Z, [Z13.B] + ZLDNT1B (R5)(R27), PN12.Z, [Z6.B-Z7.B] + ZLDNT1B (R2)(R3), PN10.Z, [Z24.B-Z27.B] + ZLDNT1B (-VL*6)(R3), PN10.Z, [Z24.B-Z25.B] + ZLDNT1B (VL*4)(RSP), PN10.Z, [Z16.B-Z19.B] + ZLDNT1H (R6<<1)(R14), P4.Z, [Z13.H] + ZLDNT1H (R6)(Z7.S), P4.Z, [Z13.S] + ZLDNT1H (R6)(Z7.D), P4.Z, [Z13.D] + ZLDNT1H (-VL*2)(R14), P4.Z, [Z13.H] + ZLDNT1H (R5<<1)(R27), PN12.Z, [Z6.H-Z7.H] + ZLDNT1H (R2<<1)(R3), PN10.Z, [Z24.H-Z27.H] + ZLDNT1H (-VL*6)(R3), PN10.Z, [Z24.H-Z25.H] + ZLDNT1H (VL*4)(RSP), PN10.Z, [Z16.H-Z19.H] + ZLDNT1W (R6<<2)(R14), P4.Z, [Z13.S] + ZLDNT1W (R6)(Z7.S), P4.Z, [Z13.S] + ZLDNT1W (R6)(Z7.D), P4.Z, [Z13.D] + ZLDNT1W (-VL*2)(R14), P4.Z, [Z13.S] + ZLDNT1W (R5<<2)(R27), PN12.Z, [Z6.S-Z7.S] + ZLDNT1W (R2<<2)(R3), PN10.Z, [Z24.S-Z27.S] + ZLDNT1W (-VL*6)(R3), PN10.Z, [Z24.S-Z25.S] + ZLDNT1W (VL*4)(RSP), PN10.Z, [Z16.S-Z19.S] + ZLDNT1D (R6<<3)(R14), P4.Z, [Z13.D] + ZLDNT1D (R6)(Z7.D), P4.Z, [Z13.D] + ZLDNT1D (-VL*2)(R14), P4.Z, [Z13.D] + ZLDNT1D (-VL*8)(R14), P4.Z, [Z12.D] + ZLDNT1D (VL*7)(R14), P4.Z, [Z11.D] + ZLDNT1D (R5<<3)(R27), PN12.Z, [Z6.D-Z7.D] + ZLDNT1D (R2<<3)(R3), PN10.Z, [Z24.D-Z27.D] + ZLDNT1D (-VL*6)(R3), PN10.Z, [Z24.D-Z25.D] + ZLDNT1D (-VL*16)(R3), PN10.Z, [Z20.D-Z21.D] + ZLDNT1D (VL*14)(R3), PN10.Z, [Z18.D-Z19.D] + ZLDNT1D (VL*4)(RSP), PN10.Z, [Z16.D-Z19.D] + ZLDNT1D (-VL*32)(RSP), PN10.Z, [Z8.D-Z11.D] + ZLDNT1D (VL*28)(RSP), PN10.Z, [Z12.D-Z15.D] + ZLDNT1SB (R6)(Z7.S), P4.Z, [Z13.S] + ZLDNT1SB (R6)(Z7.D), P4.Z, [Z13.D] + ZLDNT1SH (R6)(Z7.S), P4.Z, [Z13.S] + ZLDNT1SH (R6)(Z7.D), P4.Z, [Z13.D] + ZLDNT1SW (R6)(Z7.D), P4.Z, [Z13.D] + ZSTNT1B [Z8.B], P3, (R6)(RSP) + ZSTNT1B [Z8.S], P3, (R6)(Z15.S) + ZSTNT1B [Z8.D], P3, (R6)(Z15.D) + ZSTNT1B [Z8.B], P3, (-VL*2)(RSP) + ZSTNT1B [Z14.B-Z15.B], PN12, (R20)(R17) + ZSTNT1B [Z4.B-Z7.B], PN12, (R12)(RSP) + ZSTNT1B [Z14.B-Z15.B], PN12, (-VL*4)(R17) + ZSTNT1B [Z4.B-Z7.B], PN12, (VL*4)(RSP) + ZSTNT1H [Z8.H], P3, (R6<<1)(RSP) + ZSTNT1H [Z8.S], P3, (R6)(Z15.S) + ZSTNT1H [Z8.D], P3, (R6)(Z15.D) + ZSTNT1H [Z8.H], P3, (-VL*2)(RSP) + ZSTNT1H [Z14.H-Z15.H], PN12, (R20<<1)(R17) + ZSTNT1H [Z4.H-Z7.H], PN12, (R12<<1)(RSP) + ZSTNT1H [Z14.H-Z15.H], PN12, (-VL*4)(R17) + ZSTNT1H [Z4.H-Z7.H], PN12, (VL*4)(RSP) + ZSTNT1W [Z8.S], P3, (R6<<2)(RSP) + ZSTNT1W [Z8.S], P3, (R6)(Z15.S) + ZSTNT1W [Z8.D], P3, (R6)(Z15.D) + ZSTNT1W [Z8.S], P3, (-VL*2)(RSP) + ZSTNT1W [Z14.S-Z15.S], PN12, (R20<<2)(R17) + ZSTNT1W [Z4.S-Z7.S], PN12, (R12<<2)(RSP) + ZSTNT1W [Z14.S-Z15.S], PN12, (-VL*4)(R17) + ZSTNT1W [Z4.S-Z7.S], PN12, (VL*4)(RSP) + ZSTNT1D [Z8.D], P3, (R6<<3)(RSP) + ZSTNT1D [Z8.D], P3, (R6)(Z15.D) + ZSTNT1D [Z8.D], P3, (-VL*2)(RSP) + ZSTNT1D [Z8.D], P3, (-VL*8)(RSP) + ZSTNT1D [Z8.D], P3, (VL*7)(RSP) + ZSTNT1D [Z14.D-Z15.D], PN12, (R20<<3)(R17) + ZSTNT1D [Z4.D-Z7.D], PN12, (R12<<3)(RSP) + ZSTNT1D [Z14.D-Z15.D], PN12, (-VL*4)(R17) + ZSTNT1D [Z14.D-Z15.D], PN12, (-VL*16)(R17) + ZSTNT1D [Z14.D-Z15.D], PN12, (VL*14)(R17) + ZSTNT1D [Z4.D-Z7.D], PN12, (VL*4)(RSP) + ZSTNT1D [Z4.D-Z7.D], PN12, (-VL*32)(RSP) + ZSTNT1D [Z4.D-Z7.D], PN12, (VL*28)(RSP) + RET +` +} + +func TestTranslateARM64SVENonTemporalMemoryCompleteGo127Family(t *testing.T) { + source := arm64SVENonTemporalMemoryCompleteGo127Forms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svenontemporalmemoryforms": {Name: "svenontemporalmemoryforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2p1"`, + "@llvm.aarch64.sve.ldnt1.nxv", + "@llvm.aarch64.sve.ldnt1.gather.scalar.offset.", + "@llvm.aarch64.sve.ldnt1.pn.x2.", + "@llvm.aarch64.sve.ldnt1.pn.x4.", + "@llvm.aarch64.sve.stnt1.nxv", + "@llvm.aarch64.sve.stnt1.scatter.scalar.offset.", + "@llvm.aarch64.sve.stnt1.pn.x2.", + "@llvm.aarch64.sve.stnt1.pn.x4.", + " sext ", lanes, spec.memoryBits) + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ld1.nxv%di%d(%s %s, ptr %%%s)\n", + loaded, loadedType, lanes, spec.memoryBits, predicateType, predicateValue, pointer) + return c.finishARM64SVEOrdinaryLoad(spec, destination, elementBits, loadedType, "%"+loaded) +} + +func (c *arm64Ctx) lowerARM64SVEOrdinaryVectorOffsetLoad(op Op, spec arm64SVEOrdinaryMemorySpec, memory MemRef, predicate, destination, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + pointer, indexValue, indexType, suffix, err := c.arm64SVEOrdinaryVectorOffset(op, memory, elementBits, spec.memoryBits, ins) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + loadedType := fmt.Sprintf("", lanes, spec.memoryBits) + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ld1.gather%s.nxv%di%d(%s %s, ptr %s, %s %s)\n", + loaded, loadedType, suffix, lanes, spec.memoryBits, predicateType, predicateValue, pointer, indexType, indexValue) + return c.finishARM64SVEOrdinaryLoad(spec, destination, elementBits, loadedType, "%"+loaded) +} + +func (c *arm64Ctx) lowerARM64SVEOrdinaryVectorBaseLoad(op Op, spec arm64SVEOrdinaryMemorySpec, memory MemRef, predicate, destination, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + baseValue, baseType, err := c.arm64SVEOrdinaryVectorBase(op, memory, elementBits, spec.memoryBits, ins) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + loadedType := fmt.Sprintf("", lanes, spec.memoryBits) + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv%di%d.nxv%di%d(%s %s, %s %s, i64 %d)\n", + loaded, loadedType, lanes, spec.memoryBits, lanes, elementBits, predicateType, predicateValue, baseType, baseValue, memory.Off) + return c.finishARM64SVEOrdinaryLoad(spec, destination, elementBits, loadedType, "%"+loaded) +} + +func (c *arm64Ctx) finishARM64SVEOrdinaryLoad(spec arm64SVEOrdinaryMemorySpec, destination, elementBits int, loadedType, loaded string) (ok bool, terminated bool, err error) { + value := loaded + if spec.memoryBits < elementBits { + vectorType, _, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + extended := c.newTmp() + extension := "zext" + if spec.signed { + extension = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", extended, extension, loadedType, value, vectorType) + value = "%" + extended + } + return true, false, c.storeZRegElements(destination, elementBits, value) +} + +func (c *arm64Ctx) lowerARM64SVEOrdinaryStore(op Op, spec arm64SVEOrdinaryMemorySpec, ins Instr) (ok bool, terminated bool, err error) { + if ins.Args[0].Kind != OpRegList || ins.Args[2].Kind != OpMem { + return true, false, fmt.Errorf("arm64 %s requires vector-list, predicate, memory operands: %q", op, ins.Raw) + } + vectors, elementBits, vectorsOK := arm64ParseSVEOrdinaryVectorList(ins.Args[0]) + if !vectorsOK { + return true, false, fmt.Errorf("arm64 %s requires a consecutive, uniformly arranged Z register list: %q", op, ins.Raw) + } + if predicate, predicateOK := arm64ParseSVEPredicateBare(ins.Args[1], 7); predicateOK { + if len(vectors) != 1 { + return true, false, fmt.Errorf("arm64 %s ordinary predicate form requires one source vector: %q", op, ins.Raw) + } + return c.lowerARM64SVEOrdinarySingleStore(op, spec, ins.Args[2].Mem, predicate, vectors[0], elementBits, ins) + } + predicate, predicateOK := arm64ParseSVENonTemporalPN(ins.Args[1], false) + if !predicateOK || spec.qOnly || (len(vectors) != 2 && len(vectors) != 4) || elementBits != spec.memoryBits { + return true, false, fmt.Errorf("arm64 %s PN form requires PN8..PN15 and two or four natural-width source vectors: %q", op, ins.Raw) + } + address, err := c.arm64SVENonTemporalContiguousAddress(ins.Args[2].Mem, spec.memoryBits, len(vectors)) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + counter, err := c.loadPNReg(predicate) + if err != nil { + return true, false, err + } + vectorType, _, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + values := make([]string, 0, len(vectors)) + for _, vector := range vectors { + value, _, err := c.loadZRegElements(vector, elementBits) + if err != nil { + return true, false, err + } + values = append(values, fmt.Sprintf("%s %s", vectorType, value)) + } + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.st1.pn.x%d.nxv%di%d(%s, target(\"aarch64.svcount\") %s, ptr %%%s)\n", + len(vectors), 128/elementBits, elementBits, strings.Join(values, ", "), counter, pointer) + return true, false, nil +} + +func (c *arm64Ctx) lowerARM64SVEOrdinarySingleStore(op Op, spec arm64SVEOrdinaryMemorySpec, memory MemRef, predicate, source, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + if spec.qOnly { + return c.lowerARM64SVEOrdinaryQScatterStore(op, memory, predicate, source, elementBits, ins) + } + if elementBits == 128 { + if spec.memoryBits != 32 && spec.memoryBits != 64 { + return true, false, fmt.Errorf("arm64 %s Q arrangement is outside its Go 1.27 table: %q", op, ins.Raw) + } + return c.lowerARM64SVEOrdinaryQContiguousStore(op, spec, memory, predicate, source, ins) + } + if elementBits < spec.memoryBits { + return true, false, fmt.Errorf("arm64 %s source arrangement is narrower than its memory element: %q", op, ins.Raw) + } + value, vectorType, err := c.loadZRegElements(source, elementBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + storedType, stored := arm64SVETruncateStoreValue(c, value, vectorType, lanes, spec.memoryBits, elementBits) + if _, _, vectorOffset := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}); vectorOffset { + pointer, indexValue, indexType, suffix, err := c.arm64SVEOrdinaryVectorOffset(op, memory, elementBits, spec.memoryBits, ins) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.st1.scatter%s.nxv%di%d(%s %s, %s %s, ptr %s, %s %s)\n", + suffix, lanes, spec.memoryBits, storedType, stored, predicateType, predicateValue, pointer, indexType, indexValue) + return true, false, nil + } + if _, _, vectorBase := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Base}); vectorBase { + baseValue, baseType, err := c.arm64SVEOrdinaryVectorBase(op, memory, elementBits, spec.memoryBits, ins) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv%di%d.nxv%di%d(%s %s, %s %s, %s %s, i64 %d)\n", + lanes, spec.memoryBits, lanes, elementBits, storedType, stored, predicateType, predicateValue, baseType, baseValue, memory.Off) + return true, false, nil + } + address, err := c.arm64SVEOrdinaryContiguousAddress(memory, spec.memoryBits, 1) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.st1.nxv%di%d(%s %s, %s %s, ptr %%%s)\n", + lanes, spec.memoryBits, storedType, stored, predicateType, predicateValue, pointer) + return true, false, nil +} + +func arm64SVETruncateStoreValue(c *arm64Ctx, value, vectorType string, lanes, memoryBits, elementBits int) (storedType, stored string) { + storedType, stored = vectorType, value + if memoryBits < elementBits { + storedType = fmt.Sprintf("", lanes, memoryBits) + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", truncated, vectorType, value, storedType) + stored = "%" + truncated + } + return storedType, stored +} + +func (c *arm64Ctx) lowerARM64SVEOrdinaryQContiguousLoad(op Op, spec arm64SVEOrdinaryMemorySpec, memory MemRef, predicate, destination int, ins Instr) (ok bool, terminated bool, err error) { + address, err := c.arm64SVEOrdinaryContiguousAddress(memory, spec.memoryBits, 1) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + predicateValue, err := c.loadARM64SVEQPredicate(predicate) + if err != nil { + return true, false, err + } + vectorType, lanes, _ := arm64SVEVectorType(spec.memoryBits) + intrinsic := map[int]string{32: "ld1uwq", 64: "ld1udq"}[spec.memoryBits] + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d( %s, ptr %%%s)\n", + loaded, vectorType, intrinsic, lanes, spec.memoryBits, predicateValue, pointer) + return true, false, c.storeZRegElements(destination, spec.memoryBits, "%"+loaded) +} + +func (c *arm64Ctx) lowerARM64SVEOrdinaryQContiguousStore(op Op, spec arm64SVEOrdinaryMemorySpec, memory MemRef, predicate, source int, ins Instr) (ok bool, terminated bool, err error) { + address, err := c.arm64SVEOrdinaryContiguousAddress(memory, spec.memoryBits, 1) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + value, vectorType, err := c.loadZRegElements(source, spec.memoryBits) + if err != nil { + return true, false, err + } + predicateValue, err := c.loadARM64SVEQPredicate(predicate) + if err != nil { + return true, false, err + } + lanes := 128 / spec.memoryBits + intrinsic := map[int]string{32: "st1wq", 64: "st1dq"}[spec.memoryBits] + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s, ptr %%%s)\n", + intrinsic, lanes, spec.memoryBits, vectorType, value, predicateValue, pointer) + return true, false, nil +} + +func (c *arm64Ctx) lowerARM64SVEOrdinaryQGatherLoad(op Op, memory MemRef, predicate, destination, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + if elementBits != 128 || memory.Sym != "" || memory.Segment != "" || memory.Off != 0 || memory.OffRaw != "" || memory.IndexExt != "" || memory.Scale != 1 { + return true, false, fmt.Errorf("arm64 %s requires vector D bases, a scalar register offset, and a Q destination: %q", op, ins.Raw) + } + bases, baseBits, baseOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}) + if !baseOK || baseBits != 64 || !isARM64GeneralOrZeroReg(memory.Base) || memory.Base == ZR || memory.Base == SP || memory.Base == Reg("RSP") { + return true, false, fmt.Errorf("arm64 %s requires Zn.D bases and R0..R30 offset: %q", op, ins.Raw) + } + baseValue, baseType, err := c.loadZRegElements(bases, 64) + if err != nil { + return true, false, err + } + offset, err := c.loadReg(memory.Base) + if err != nil { + return true, false, err + } + predicateValue, err := c.loadARM64SVEQPredicate(predicate) + if err != nil { + return true, false, err + } + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64( %s, %s %s, i64 %s)\n", + loaded, baseType, predicateValue, baseType, baseValue, offset) + return true, false, c.storeZRegElements(destination, 64, "%"+loaded) +} + +func (c *arm64Ctx) lowerARM64SVEOrdinaryQScatterStore(op Op, memory MemRef, predicate, source, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + if elementBits != 128 || memory.Sym != "" || memory.Segment != "" || memory.Off != 0 || memory.OffRaw != "" || memory.IndexExt != "" || memory.Scale != 1 { + return true, false, fmt.Errorf("arm64 %s requires a Q source, vector D bases, and a scalar register offset: %q", op, ins.Raw) + } + bases, baseBits, baseOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}) + if !baseOK || baseBits != 64 || !isARM64GeneralOrZeroReg(memory.Base) || memory.Base == ZR || memory.Base == SP || memory.Base == Reg("RSP") { + return true, false, fmt.Errorf("arm64 %s requires Zn.D bases and R0..R30 offset: %q", op, ins.Raw) + } + baseValue, baseType, err := c.loadZRegElements(bases, 64) + if err != nil { + return true, false, err + } + offset, err := c.loadReg(memory.Base) + if err != nil { + return true, false, err + } + value, vectorType, err := c.loadZRegElements(source, 64) + if err != nil { + return true, false, err + } + predicateValue, err := c.loadARM64SVEQPredicate(predicate) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(%s %s, %s, %s %s, i64 %s)\n", + vectorType, value, predicateValue, baseType, baseValue, offset) + return true, false, nil +} + +func (c *arm64Ctx) loadARM64SVEQPredicate(predicate int) (string, error) { + value, err := c.loadPReg(predicate) + if err != nil { + return "", err + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %s)\n", converted, value) + return "%" + converted, nil +} + +func (c *arm64Ctx) arm64SVEOrdinaryContiguousAddress(memory MemRef, memoryBits, vectorCount int) (string, error) { + if memory.Index != "" { + if _, _, vectorIndex := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}); vectorIndex { + return "", fmt.Errorf("contiguous form does not accept a scalable-vector index") + } + return c.arm64SVERegisterOffsetAddress(memory, int64(memoryBits/8)) + } + return c.arm64SVENonTemporalContiguousAddress(memory, memoryBits, vectorCount) +} + +func (c *arm64Ctx) arm64SVEOrdinaryVectorOffset(op Op, memory MemRef, elementBits, memoryBits int, ins Instr) (pointer, indexValue, indexType, suffix string, err error) { + if memory.Sym != "" || memory.Segment != "" || memory.Off != 0 || memory.OffRaw != "" { + return "", "", "", "", fmt.Errorf("arm64 %s vector-offset form does not accept a displacement: %q", op, ins.Raw) + } + baseReg, baseOK := arm64SVEPhysicalMemoryBase(memory.Base) + index, indexBits, indexOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}) + byteScale := int64(memoryBits / 8) + if !baseOK || !indexOK || indexBits != elementBits || (elementBits != 32 && elementBits != 64) || (memory.Scale != 1 && memory.Scale != byteScale) { + return "", "", "", "", fmt.Errorf("arm64 %s vector offset has widths or scale outside its Go 1.27 table: %q", op, ins.Raw) + } + extension := "" + switch memory.IndexExt { + case "": + if indexBits != 64 { + return "", "", "", "", fmt.Errorf("arm64 %s unextended vector offset requires Zm.D: %q", op, ins.Raw) + } + case ExtendUXTW: + extension = "uxtw" + case ExtendSXTW: + extension = "sxtw" + default: + return "", "", "", "", fmt.Errorf("arm64 %s vector offset only accepts UXTW or SXTW: %q", op, ins.Raw) + } + base, err := c.loadReg(baseReg) + if err != nil { + return "", "", "", "", err + } + pointerName := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointerName, base) + indexValue, indexType, err = c.loadZRegElements(index, indexBits) + if err != nil { + return "", "", "", "", err + } + if extension != "" && indexBits == 64 { + narrowType := "" + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %s to %s\n", narrow, indexType, indexValue, narrowType) + extended := c.newTmp() + opcode := "zext" + if extension == "sxtw" { + opcode = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s %s %%%s to %s\n", extended, opcode, narrowType, narrow, indexType) + indexValue = "%" + extended + extension = "" + } + if extension != "" { + suffix = "." + extension + } + if byteScale > 1 && memory.Scale == byteScale { + suffix += ".index" + } + return "%" + pointerName, indexValue, indexType, suffix, nil +} + +func (c *arm64Ctx) arm64SVEOrdinaryVectorBase(op Op, memory MemRef, elementBits, memoryBits int, ins Instr) (baseValue, baseType string, err error) { + base, baseBits, baseOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Base}) + alignment := int64(memoryBits / 8) + maximum := int64(31) * alignment + if !baseOK || baseBits != elementBits || (elementBits != 32 && elementBits != 64) || memory.Index != "" || memory.IndexExt != "" || memory.Sym != "" || memory.Segment != "" || memory.OffRaw != "" || memory.Off < 0 || memory.Off > maximum || memory.Off%alignment != 0 { + return "", "", fmt.Errorf("arm64 %s vector-base offset must match the data width, be aligned to %d, and be in [0,%d]: %q", op, alignment, maximum, ins.Raw) + } + return c.loadZRegElements(base, baseBits) +} + +func arm64ParseSVEOrdinaryVectorList(operand Operand) (vectors []int, elementBits int, ok bool) { + if operand.Kind != OpRegList || len(operand.RegList) == 0 { + return nil, 0, false + } + vectors = make([]int, len(operand.RegList)) + for i, register := range operand.RegList { + vector, bits, valid := arm64ParseSVEOrdinaryZReg(register) + if !valid || i > 0 && (bits != elementBits || vector != vectors[i-1]+1) { + return nil, 0, false + } + vectors[i] = vector + elementBits = bits + } + return vectors, elementBits, true +} + +func arm64ParseSVEOrdinaryZReg(register Reg) (index, elementBits int, ok bool) { + if index, elementBits, ok = arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: register}); ok { + return index, elementBits, true + } + parts := strings.Split(strings.ToUpper(strings.TrimSpace(string(register))), ".") + if len(parts) != 2 || parts[1] != "Q" || !strings.HasPrefix(parts[0], "Z") { + return 0, 0, false + } + index, err := strconv.Atoi(strings.TrimPrefix(parts[0], "Z")) + if err != nil || index < 0 || index > 31 { + return 0, 0, false + } + return index, 128, true +} diff --git a/arm64_lower_sve_ordinary_memory_test.go b/arm64_lower_sve_ordinary_memory_test.go new file mode 100644 index 00000000..863c1981 --- /dev/null +++ b/arm64_lower_sve_ordinary_memory_test.go @@ -0,0 +1,286 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEOrdinaryMemoryCompleteGo127Forms() string { + return `TEXT sveordinarymemoryforms(SB),$0-0 + ZLD1B (R6)(R14), P4.Z, [Z13.B] + ZLD1B (R7)(RSP), P3.Z, [Z12.H] + ZLD1B (R5)(R27), P2.Z, [Z6.S] + ZLD1B (R2)(R3), P1.Z, [Z24.D] + ZLD1B (-VL*8)(R14), P4.Z, [Z13.B] + ZLD1B (VL*7)(R14), P4.Z, [Z13.H] + ZLD1B (-VL*2)(R14), P4.Z, [Z13.S] + ZLD1B (VL*3)(R14), P4.Z, [Z13.D] + ZLD1B (Z10.D)(R19), P3.Z, [Z15.D] + ZLD1B (Z6.D.SXTW)(R14), P4.Z, [Z13.D] + ZLD1B (Z4.S.UXTW)(R3), P3.Z, [Z4.S] + ZLD1B (Z7.S), P4.Z, [Z13.S] + ZLD1B 31(Z7.D), P4.Z, [Z13.D] + ZLD1B (R5)(R27), PN12.Z, [Z6.B-Z7.B] + ZLD1B (R2)(R3), PN10.Z, [Z24.B-Z27.B] + ZLD1B (-VL*16)(R3), PN10.Z, [Z24.B-Z25.B] + ZLD1B (VL*28)(RSP), PN10.Z, [Z16.B-Z19.B] + + ZLD1H (R6<<1)(R14), P4.Z, [Z13.H] + ZLD1H (R7<<1)(RSP), P3.Z, [Z12.S] + ZLD1H (R5<<1)(R27), P2.Z, [Z6.D] + ZLD1H (-VL*8)(R14), P4.Z, [Z13.H] + ZLD1H (VL*7)(R14), P4.Z, [Z13.S] + ZLD1H (-VL*2)(R14), P4.Z, [Z13.D] + ZLD1H (Z10.D)(R19), P3.Z, [Z15.D] + ZLD1H (Z23.D<<1)(R24), P1.Z, [Z22.D] + ZLD1H (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLD1H (Z5.D.SXTW<<1)(R12), P2.Z, [Z11.D] + ZLD1H (Z4.S.UXTW)(R3), P3.Z, [Z4.S] + ZLD1H (Z9.S.SXTW<<1)(R8), P5.Z, [Z10.S] + ZLD1H (Z7.S), P4.Z, [Z13.S] + ZLD1H 62(Z7.D), P4.Z, [Z13.D] + ZLD1H (R5<<1)(R27), PN12.Z, [Z6.H-Z7.H] + ZLD1H (R2<<1)(R3), PN10.Z, [Z24.H-Z27.H] + ZLD1H (-VL*16)(R3), PN10.Z, [Z24.H-Z25.H] + ZLD1H (VL*28)(RSP), PN10.Z, [Z16.H-Z19.H] + + ZLD1W (R6<<2)(R14), P4.Z, [Z13.S] + ZLD1W (R7<<2)(RSP), P3.Z, [Z12.D] + ZLD1W (R5<<2)(R27), P2.Z, [Z6.Q] + ZLD1W (-VL*8)(R14), P4.Z, [Z13.S] + ZLD1W (VL*7)(R14), P4.Z, [Z13.D] + ZLD1W (-VL*2)(R14), P4.Z, [Z13.Q] + ZLD1W (Z10.D)(R19), P3.Z, [Z15.D] + ZLD1W (Z23.D<<2)(R24), P1.Z, [Z22.D] + ZLD1W (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLD1W (Z5.D.SXTW<<2)(R12), P2.Z, [Z11.D] + ZLD1W (Z4.S.UXTW)(R3), P3.Z, [Z4.S] + ZLD1W (Z9.S.SXTW<<2)(R8), P5.Z, [Z10.S] + ZLD1W (Z7.S), P4.Z, [Z13.S] + ZLD1W 124(Z7.D), P4.Z, [Z13.D] + ZLD1W (R5<<2)(R27), PN12.Z, [Z6.S-Z7.S] + ZLD1W (R2<<2)(R3), PN10.Z, [Z24.S-Z27.S] + ZLD1W (-VL*16)(R3), PN10.Z, [Z24.S-Z25.S] + ZLD1W (VL*28)(RSP), PN10.Z, [Z16.S-Z19.S] + + ZLD1D (R6<<3)(R14), P4.Z, [Z13.D] + ZLD1D (R7<<3)(RSP), P3.Z, [Z12.Q] + ZLD1D (-VL*8)(R14), P4.Z, [Z13.D] + ZLD1D (VL*7)(R14), P4.Z, [Z13.Q] + ZLD1D (Z10.D)(R19), P3.Z, [Z15.D] + ZLD1D (Z23.D<<3)(R24), P1.Z, [Z22.D] + ZLD1D (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLD1D (Z5.D.SXTW<<3)(R12), P2.Z, [Z11.D] + ZLD1D 248(Z7.D), P4.Z, [Z13.D] + ZLD1D (R5<<3)(R27), PN12.Z, [Z6.D-Z7.D] + ZLD1D (R2<<3)(R3), PN10.Z, [Z24.D-Z27.D] + ZLD1D (-VL*16)(R3), PN10.Z, [Z24.D-Z25.D] + ZLD1D (VL*28)(RSP), PN10.Z, [Z16.D-Z19.D] + + ZLD1SB (R6)(R14), P4.Z, [Z13.H] + ZLD1SB (R7)(RSP), P3.Z, [Z12.S] + ZLD1SB (R5)(R27), P2.Z, [Z6.D] + ZLD1SB (-VL*8)(R14), P4.Z, [Z13.H] + ZLD1SB (VL*7)(R14), P4.Z, [Z13.S] + ZLD1SB (-VL*2)(R14), P4.Z, [Z13.D] + ZLD1SB (Z10.D)(R19), P3.Z, [Z15.D] + ZLD1SB (Z6.D.SXTW)(R14), P4.Z, [Z13.D] + ZLD1SB (Z4.S.UXTW)(R3), P3.Z, [Z4.S] + ZLD1SB (Z7.S), P4.Z, [Z13.S] + ZLD1SB 31(Z7.D), P4.Z, [Z13.D] + + ZLD1SH (R6<<1)(R14), P4.Z, [Z13.S] + ZLD1SH (R7<<1)(RSP), P3.Z, [Z12.D] + ZLD1SH (-VL*8)(R14), P4.Z, [Z13.S] + ZLD1SH (VL*7)(R14), P4.Z, [Z13.D] + ZLD1SH (Z10.D)(R19), P3.Z, [Z15.D] + ZLD1SH (Z23.D<<1)(R24), P1.Z, [Z22.D] + ZLD1SH (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLD1SH (Z5.D.SXTW<<1)(R12), P2.Z, [Z11.D] + ZLD1SH (Z4.S.UXTW)(R3), P3.Z, [Z4.S] + ZLD1SH (Z9.S.SXTW<<1)(R8), P5.Z, [Z10.S] + ZLD1SH (Z7.S), P4.Z, [Z13.S] + ZLD1SH 62(Z7.D), P4.Z, [Z13.D] + + ZLD1SW (R6<<2)(R14), P4.Z, [Z13.D] + ZLD1SW (-VL*8)(R14), P4.Z, [Z13.D] + ZLD1SW (Z10.D)(R19), P3.Z, [Z15.D] + ZLD1SW (Z23.D<<2)(R24), P1.Z, [Z22.D] + ZLD1SW (Z6.D.UXTW)(R14), P4.Z, [Z13.D] + ZLD1SW (Z5.D.SXTW<<2)(R12), P2.Z, [Z11.D] + ZLD1SW 124(Z7.D), P4.Z, [Z13.D] + + ZLD1Q (R6)(Z7.D), P4.Z, [Z13.Q] + + ZST1B [Z7.B], P4, (R21)(R7) + ZST1B [Z8.H], P3, (R6)(RSP) + ZST1B [Z9.S], P2, (R5)(R4) + ZST1B [Z10.D], P1, (R3)(R2) + ZST1B [Z6.D], P4, (Z21.D.UXTW)(R7) + ZST1B [Z5.D], P3, (Z20.D.SXTW)(R8) + ZST1B [Z4.S], P2, (Z19.S.UXTW)(R9) + ZST1B [Z8.S], P3, (Z15.S) + ZST1B [Z8.D], P3, 31(Z15.D) + ZST1B [Z7.B], P4, (-VL*8)(R7) + ZST1B [Z8.H], P3, (VL*7)(RSP) + ZST1B [Z9.S], P2, (-VL*3)(R7) + ZST1B [Z10.D], P1, (VL*4)(R7) + ZST1B [Z14.B-Z15.B], PN12, (R20)(R17) + ZST1B [Z4.B-Z7.B], PN12, (R12)(RSP) + ZST1B [Z14.B-Z15.B], PN12, (-VL*16)(R17) + ZST1B [Z4.B-Z7.B], PN12, (VL*28)(RSP) + + ZST1H [Z7.H], P4, (R21<<1)(R7) + ZST1H [Z8.S], P3, (R6<<1)(RSP) + ZST1H [Z9.D], P2, (R5<<1)(R4) + ZST1H [Z6.D], P4, (Z21.D)(R7) + ZST1H [Z5.D], P3, (Z20.D<<1)(R8) + ZST1H [Z4.D], P2, (Z19.D.UXTW)(R9) + ZST1H [Z3.D], P1, (Z18.D.SXTW<<1)(R10) + ZST1H [Z2.S], P0, (Z17.S.UXTW)(R11) + ZST1H [Z1.S], P7, (Z16.S.SXTW<<1)(R12) + ZST1H [Z8.S], P3, (Z15.S) + ZST1H [Z8.D], P3, 62(Z15.D) + ZST1H [Z7.H], P4, (-VL*8)(R7) + ZST1H [Z8.S], P3, (VL*7)(RSP) + ZST1H [Z9.D], P2, (-VL*3)(R7) + ZST1H [Z14.H-Z15.H], PN12, (R20<<1)(R17) + ZST1H [Z4.H-Z7.H], PN12, (R12<<1)(RSP) + ZST1H [Z14.H-Z15.H], PN12, (-VL*16)(R17) + ZST1H [Z4.H-Z7.H], PN12, (VL*28)(RSP) + + ZST1W [Z7.S], P4, (R21<<2)(R7) + ZST1W [Z8.D], P3, (R6<<2)(RSP) + ZST1W [Z9.Q], P2, (R5<<2)(R4) + ZST1W [Z6.D], P4, (Z21.D)(R7) + ZST1W [Z5.D], P3, (Z20.D<<2)(R8) + ZST1W [Z4.D], P2, (Z19.D.UXTW)(R9) + ZST1W [Z3.D], P1, (Z18.D.SXTW<<2)(R10) + ZST1W [Z2.S], P0, (Z17.S.UXTW)(R11) + ZST1W [Z1.S], P7, (Z16.S.SXTW<<2)(R12) + ZST1W [Z8.S], P3, (Z15.S) + ZST1W [Z8.D], P3, 124(Z15.D) + ZST1W [Z7.S], P4, (-VL*8)(R7) + ZST1W [Z8.D], P3, (VL*7)(RSP) + ZST1W [Z9.Q], P2, (-VL*3)(R7) + ZST1W [Z14.S-Z15.S], PN12, (R20<<2)(R17) + ZST1W [Z4.S-Z7.S], PN12, (R12<<2)(RSP) + ZST1W [Z14.S-Z15.S], PN12, (-VL*16)(R17) + ZST1W [Z4.S-Z7.S], PN12, (VL*28)(RSP) + + ZST1D [Z7.D], P4, (R21<<3)(R7) + ZST1D [Z8.Q], P3, (R6<<3)(RSP) + ZST1D [Z6.D], P4, (Z21.D)(R7) + ZST1D [Z5.D], P3, (Z20.D<<3)(R8) + ZST1D [Z4.D], P2, (Z19.D.UXTW)(R9) + ZST1D [Z3.D], P1, (Z18.D.SXTW<<3)(R10) + ZST1D [Z8.D], P3, (Z15.D) + ZST1D [Z7.D], P4, (-VL*8)(R7) + ZST1D [Z8.Q], P3, (VL*7)(RSP) + ZST1D [Z14.D-Z15.D], PN12, (R20<<3)(R17) + ZST1D [Z4.D-Z7.D], PN12, (R12<<3)(RSP) + ZST1D [Z14.D-Z15.D], PN12, (-VL*16)(R17) + ZST1D [Z4.D-Z7.D], PN12, (VL*28)(RSP) + + ZST1Q [Z8.Q], P3, (R6)(Z15.D) + RET +` +} + +func TestTranslateARM64SVEOrdinaryMemoryCompleteGo127Family(t *testing.T) { + source := arm64SVEOrdinaryMemoryCompleteGo127Forms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveordinarymemoryforms": {Name: "sveordinarymemoryforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2p1"`, + "@llvm.aarch64.sve.ld1.nxv", + "@llvm.aarch64.sve.ld1.gather.nxv", + "@llvm.aarch64.sve.ld1.gather.index.nxv", + "@llvm.aarch64.sve.ld1.gather.uxtw.nxv", + "@llvm.aarch64.sve.ld1.gather.sxtw.index.nxv", + "@llvm.aarch64.sve.ld1.gather.scalar.offset.", + "@llvm.aarch64.sve.ld1.pn.x2.", + "@llvm.aarch64.sve.ld1.pn.x4.", + "@llvm.aarch64.sve.ld1udq.", + "@llvm.aarch64.sve.ld1uwq.", + "@llvm.aarch64.sve.ld1q.gather.scalar.offset.", + "@llvm.aarch64.sve.st1.nxv", + "@llvm.aarch64.sve.st1.scatter.nxv", + "@llvm.aarch64.sve.st1.scatter.index.nxv", + "@llvm.aarch64.sve.st1.scatter.uxtw.nxv", + "@llvm.aarch64.sve.st1.scatter.sxtw.index.nxv", + "@llvm.aarch64.sve.st1.scatter.scalar.offset.", + "@llvm.aarch64.sve.st1.pn.x2.", + "@llvm.aarch64.sve.st1.pn.x4.", + "@llvm.aarch64.sve.st1dq.", + "@llvm.aarch64.sve.st1wq.", + "@llvm.aarch64.sve.st1q.scatter.scalar.offset.", + " sext %s)\n", result, vectorType, assembly, "=&w,0,w,@3Upl", vectorType, firstValue, vectorType, secondValue, predicateValue) + return true, false, c.storeZRegElements(destination, 64, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEAddPairwise(ins Instr) (ok bool, terminated bool, err error) { + if strings.ToUpper(string(ins.Op)) != "ZADDP" || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 ZADDP expects Zm.T, Zdn.T, Pg/M, Zdn.T without a suffix: %q", ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !firstOK || !predicateOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits || first != destination { + return true, false, fmt.Errorf("arm64 ZADDP requires matching element widths and a repeated destructive destination: %q", ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, firstBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, firstBits) + if err != nil { + return true, false, err + } + lanes := 128 / firstBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.addp.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, lanes, firstBits, predicateType, predicateValue, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeZRegElements(destination, firstBits, "%"+result) +} diff --git a/arm64_lower_sve_pairwise_tail_test.go b/arm64_lower_sve_pairwise_tail_test.go new file mode 100644 index 00000000..226252b6 --- /dev/null +++ b/arm64_lower_sve_pairwise_tail_test.go @@ -0,0 +1,82 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEPairwiseTailCompleteGo127Family(t *testing.T) { + const source = ` +TEXT svepairwise(SB),$0-0 + ZADDP Z1.B, Z2.B, P0.M, Z2.B + ZADDP Z3.H, Z4.H, P1.M, Z4.H + ZADDP Z5.S, Z6.S, P2.M, Z6.S + ZADDP Z7.D, Z8.D, P3.M, Z8.D + RET +TEXT svetail(SB),$0-0 + ZADDPT Z9.D, Z10.D, P4.M, Z10.D + ZADDPT Z11.D, Z12.D, Z13.D + ZSUBPT Z14.D, Z15.D, P5.M, Z15.D + ZSUBPT Z16.D, Z17.D, Z18.D + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + sigs := map[string]FuncSig{ + "svepairwise": {Name: "svepairwise", Ret: Void}, + "svetail": {Name: "svetail", Ret: Void}, + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + `"target-features"="+cpa,+sve"`, + "@llvm.aarch64.sve.addp.nxv16i8", + `asm sideeffect "addpt $0.d, $3/m, $0.d, $2.d"`, + `asm sideeffect "addpt $0.d, $1.d, $2.d"`, + `asm sideeffect "subpt $0.d, $3/m, $0.d, $2.d"`, + `asm sideeffect "subpt $0.d, $1.d, $2.d"`, + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE pairwise/tail lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-pairwise-tail.ll", "arm64-sve-pairwise-tail.o", ll) + }) + } +} + +func TestTranslateARM64SVEPairwiseTailRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZADDP Z1.B, Z2.B, P0.M, Z3.B", + "ZADDP Z1.B, Z2.H, P0.M, Z2.H", + "ZADDP Z1.B, Z2.B, P0.Z, Z2.B", + "ZADDPT Z1.S, Z2.S, Z3.S", + "ZADDPT Z1.D, Z2.D, P0.M, Z3.D", + "ZSUBPT Z1.D, Z2.D, P0.Z, Z2.D", + "ZSUBPT.Z Z1.D, Z2.D, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepairwisetail(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepairwisetail": {Name: "badsvepairwisetail", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE pairwise/tail forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_permute.go b/arm64_lower_sve_permute.go new file mode 100644 index 00000000..a5316798 --- /dev/null +++ b/arm64_lower_sve_permute.go @@ -0,0 +1,149 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +type arm64RawSVEPermute struct { + op Op + elementBits int + quad bool + first int + second int + destination int +} + +var arm64SVEPermuteIntrinsics = map[Op]string{ + "ZZIP1": "zip1", + "ZZIP2": "zip2", + "ZUZP1": "uzp1", + "ZUZP2": "uzp2", + "ZTRN1": "trn1", + "ZTRN2": "trn2", + "ZZIPQ1": "zipq1", + "ZZIPQ2": "zipq2", + "ZUZPQ1": "uzpq1", + "ZUZPQ2": "uzpq2", +} + +var arm64SVEPermuteOpsByIndex = [...]Op{"ZZIP1", "ZZIP2", "ZUZP1", "ZUZP2", "ZTRN1", "ZTRN2"} +var arm64SVEQPermuteOpsByIndex = [...]Op{"ZZIPQ1", "ZZIPQ2", "ZUZPQ1", "ZUZPQ2"} + +func arm64SVEIsQPermuteOp(op Op) bool { + for _, candidate := range arm64SVEQPermuteOpsByIndex { + if op == candidate { + return true + } + } + return false +} + +// decodeARM64RawSVEPermute covers the complete ZIP1/2, UZP1/2 and TRN1/2 +// family, including the F64MM 128-bit element forms exposed by Go 1.27. +func decodeARM64RawSVEPermute(word uint32) (arm64RawSVEPermute, bool) { + form := arm64RawSVEPermute{ + first: int(word>>5) & 31, + second: int(word>>16) & 31, + destination: int(word) & 31, + } + selector := int(word>>10) & 7 + switch { + case word&0xff20e000 == 0x05206000: + if selector > 5 { + return arm64RawSVEPermute{}, false + } + form.op = arm64SVEPermuteOpsByIndex[selector] + form.elementBits = 8 << (int(word>>22) & 3) + case word&0xffe0e000 == 0x05a00000: + if selector == 4 || selector == 5 { + return arm64RawSVEPermute{}, false + } + if selector >= 6 { + selector -= 2 + } + form.op = arm64SVEPermuteOpsByIndex[selector] + form.elementBits = 128 + form.quad = true + default: + return arm64RawSVEPermute{}, false + } + return form, true +} + +func arm64ParseSVEPermuteReg(operand Operand) (index, elementBits int, ok bool) { + if index, elementBits, ok := arm64ParseSVEZElementReg(operand); ok { + return index, elementBits, true + } + if operand.Kind != OpReg { + return 0, 0, false + } + parts := strings.Split(strings.ToUpper(strings.TrimSpace(string(operand.Reg))), ".") + if len(parts) != 2 || parts[1] != "Q" || !strings.HasPrefix(parts[0], "Z") { + return 0, 0, false + } + index, err := strconv.Atoi(strings.TrimPrefix(parts[0], "Z")) + return index, 128, err == nil && index >= 0 && index < 32 +} + +func arm64SVEPermuteNeedsF64MM(ins Instr) bool { + if len(ins.Args) != 3 { + return false + } + _, bits, ok := arm64ParseSVEPermuteReg(ins.Args[2]) + return ok && bits == 128 +} + +func (c *arm64Ctx) lowerARM64SVEPermute(op Op, ins Instr) (ok bool, terminated bool, err error) { + if _, ok := arm64SVEPermuteIntrinsics[op]; !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zm.T, Zn.T, Zd.T for T=B/H/S/D/Q: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEPermuteReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEPermuteReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEPermuteReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != firstBits || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s operands must use one matching B/H/S/D/Q element width: %q", op, ins.Raw) + } + if arm64SVEIsQPermuteOp(op) && destinationBits == 128 { + return true, false, fmt.Errorf("arm64 %s only accepts B/H/S/D element widths: %q", op, ins.Raw) + } + return true, false, c.lowerRawSVEPermute(arm64RawSVEPermute{ + op: op, + elementBits: firstBits, + quad: firstBits == 128, + first: first, + second: second, + destination: destination, + }) +} + +func (c *arm64Ctx) lowerRawSVEPermute(form arm64RawSVEPermute) error { + intrinsic, ok := arm64SVEPermuteIntrinsics[form.op] + if !ok { + return fmt.Errorf("unsupported ARM64 SVE permute operation %s", form.op) + } + representationBits := form.elementBits + if form.quad { + representationBits = 64 + intrinsic += "q" + } + first, vectorType, err := c.loadZRegElements(form.first, representationBits) + if err != nil { + return err + } + second, _, err := c.loadZRegElements(form.second, representationBits) + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(representationBits) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, vectorType, intrinsic, lanes, representationBits, vectorType, first, vectorType, second) + return c.storeZRegElements(form.destination, representationBits, "%"+result) +} diff --git a/arm64_lower_sve_permute_test.go b/arm64_lower_sve_permute_test.go new file mode 100644 index 00000000..28480a72 --- /dev/null +++ b/arm64_lower_sve_permute_test.go @@ -0,0 +1,145 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +var arm64SVEPermuteOps = []Op{"ZZIP1", "ZZIP2", "ZUZP1", "ZUZP2", "ZTRN1", "ZTRN2"} + +func encodeARM64RawSVEPermute(op Op, elementBits, second, first, destination int) uint32 { + selector := 0 + for index, candidate := range arm64SVEPermuteOps { + if op == candidate { + selector = index + break + } + } + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + return 0x05206000 | size<<22 | uint32(selector)<<10 | uint32(second)<<16 | uint32(first)<<5 | uint32(destination) +} + +func encodeARM64RawSVEPermuteQ(op Op, second, first, destination int) uint32 { + selector := 0 + for index, candidate := range arm64SVEPermuteOps { + if op == candidate { + selector = index + if selector >= 4 { + selector += 2 + } + break + } + } + return 0x05a00000 | uint32(selector)<<10 | uint32(second)<<16 | uint32(first)<<5 | uint32(destination) +} + +func TestTranslateARM64RawSVEPermuteReportedEncoding(t *testing.T) { + const source = "TEXT svetrn2reported(SB),$0-0\n\tWORD $0x05e47490\n\tRET\n" + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"svetrn2reported": {Name: "svetrn2reported", Ret: Void}}}); err != nil { + t.Fatal(err) + } +} + +func TestTranslateARM64SVEPermuteCompleteGo127Forms(t *testing.T) { + var named strings.Builder + named.WriteString("TEXT svepermutednamed(SB),$0-0\n") + for _, op := range arm64SVEPermuteOps { + fmt.Fprintf(&named, "\t%s Z2.B, Z1.B, Z0.B\n", op) + fmt.Fprintf(&named, "\t%s Z4.H, Z3.H, Z0.H\n", op) + fmt.Fprintf(&named, "\t%s Z6.S, Z5.S, Z0.S\n", op) + fmt.Fprintf(&named, "\t%s Z8.D, Z7.D, Z0.D\n", op) + fmt.Fprintf(&named, "\t%s Z10.Q, Z9.Q, Z0.Q\n", op) + } + named.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, named.String(), true) + + var raw strings.Builder + raw.WriteString("TEXT svepermutedraw(SB),$0-0\n") + for _, op := range arm64SVEPermuteOps { + for _, elementBits := range []int{8, 16, 32, 64} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEPermute(op, elementBits, 2, 1, 0)) + } + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEPermuteQ(op, 10, 9, 0)) + } + raw.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, raw.String(), true) + + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for name, source := range map[string]string{"named": named.String(), "raw": raw.String()} { + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "svepermuted" + name + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+f64mm,+sve"`, "@llvm.aarch64.sve.zip1.nxv", "@llvm.aarch64.sve.uzp2.nxv", "@llvm.aarch64.sve.trn2.nxv", "@llvm.aarch64.sve.trn1q.nxv2i64"} { + if !strings.Contains(ir, want) { + t.Fatalf("SVE permute lowering omitted %q:\n%s", want, ir) + } + } + compileLLVMToObject(t, llc, triple, "arm64-sve-permute.ll", "arm64-sve-permute.o", ir) + }) + } + }) + } +} + +func TestARM64RawSVEPermuteDecoderCoversEveryEncodingField(t *testing.T) { + for _, op := range arm64SVEPermuteOps { + for _, elementBits := range []int{8, 16, 32, 64} { + for second := 0; second < 32; second++ { + for first := 0; first < 32; first++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVEPermute(op, elementBits, second, first, destination) + got, ok := decodeARM64RawSVEPermute(word) + if !ok || got.op != op || got.elementBits != elementBits || got.quad || got.second != second || got.first != first || got.destination != destination { + t.Fatalf("decoded SVE permute %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } + for second := 0; second < 32; second++ { + for first := 0; first < 32; first++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVEPermuteQ(op, second, first, destination) + got, ok := decodeARM64RawSVEPermute(word) + if !ok || got.op != op || !got.quad || got.elementBits != 128 || got.second != second || got.first != first || got.destination != destination { + t.Fatalf("decoded SVE Q permute %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } +} + +func TestARM64SVEPermuteRejectsAdjacentAndInvalidForms(t *testing.T) { + for _, word := range []uint32{ + 0x05206000 | 6<<10, + 0x05206000 | 7<<10, + 0x05a00000 | 4<<10, + 0x05a00000 | 5<<10, + } { + if _, ok := decodeARM64RawSVEPermute(word); ok { + t.Fatalf("SVE permute decoder accepted adjacent encoding %#08x", word) + } + } + const invalid = "TEXT badsvepermute(SB),$0-0\n\tZTRN2 Z1.B, Z2.H, Z3.B\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, invalid, false) +} diff --git a/arm64_lower_sve_pmov.go b/arm64_lower_sve_pmov.go new file mode 100644 index 00000000..9847e125 --- /dev/null +++ b/arm64_lower_sve_pmov.go @@ -0,0 +1,108 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +func arm64ParseSVEPMOVIndexedZReg(operand Operand, elementBits int) (index, lane int, ok bool) { + if operand.Kind != OpReg { + return 0, 0, false + } + text := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + open := strings.IndexByte(text, '[') + if open <= 1 || !strings.HasPrefix(text, "Z") || !strings.HasSuffix(text, "]") || strings.Contains(text[:open], ".") { + return 0, 0, false + } + index, indexErr := strconv.Atoi(text[1:open]) + lane, laneErr := strconv.Atoi(text[open+1 : len(text)-1]) + maximumLane, widthOK := map[int]int{16: 1, 32: 3, 64: 7}[elementBits] + return index, lane, indexErr == nil && laneErr == nil && widthOK && index >= 0 && index <= 31 && lane >= 0 && lane <= maximumLane +} + +func (c *arm64Ctx) lowerARM64SVEPMOV(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZPMOV" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 ZPMOV expects its two-operand Go 1.27 form without a suffix: %q", ins.Raw) + } + + if predicate, elementBits, predicateOK := arm64ParseSVEPredicateElement(ins.Args[0]); predicateOK { + if elementBits == 8 { + vector, vectorOK := arm64ParseSVEBareZReg(ins.Args[1]) + if !vectorOK { + return true, false, fmt.Errorf("arm64 ZPMOV Pn.B source requires a bare Z destination: %q", ins.Raw) + } + return true, false, c.lowerARM64SVEPMOVToVector(predicate, vector, elementBits, 0) + } + vector, lane, vectorOK := arm64ParseSVEPMOVIndexedZReg(ins.Args[1], elementBits) + if !vectorOK { + return true, false, fmt.Errorf("arm64 ZPMOV Pn.%s source requires a valid indexed Z destination: %q", arm64SVEElementLetter(elementBits), ins.Raw) + } + return true, false, c.lowerARM64SVEPMOVToVector(predicate, vector, elementBits, lane) + } + + if predicate, elementBits, predicateOK := arm64ParseSVEPredicateElement(ins.Args[1]); predicateOK { + if elementBits == 8 { + vector, vectorOK := arm64ParseSVEBareZReg(ins.Args[0]) + if !vectorOK { + return true, false, fmt.Errorf("arm64 ZPMOV Pn.B destination requires a bare Z source: %q", ins.Raw) + } + return true, false, c.lowerARM64SVEPMOVToPredicate(vector, predicate, elementBits, 0) + } + vector, lane, vectorOK := arm64ParseSVEPMOVIndexedZReg(ins.Args[0], elementBits) + if !vectorOK { + return true, false, fmt.Errorf("arm64 ZPMOV Pn.%s destination requires a valid indexed Z source: %q", arm64SVEElementLetter(elementBits), ins.Raw) + } + return true, false, c.lowerARM64SVEPMOVToPredicate(vector, predicate, elementBits, lane) + } + + return true, false, fmt.Errorf("arm64 ZPMOV requires one P0..P15.B/H/S/D operand and one matching Go Z operand: %q", ins.Raw) +} + +func (c *arm64Ctx) lowerARM64SVEPMOVToVector(predicate, vector, elementBits, lane int) error { + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return err + } + vectorType, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return err + } + result := c.newTmp() + if lane == 0 { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv%di%d(%s %s)\n", result, vectorType, lanes, elementBits, predicateType, predicateValue) + } else { + oldVector, _, err := c.loadZRegElements(vector, elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv%di%d(%s %s, %s %s, i32 %d)\n", result, vectorType, lanes, elementBits, vectorType, oldVector, predicateType, predicateValue, lane) + } + return c.storeZRegElements(vector, elementBits, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEPMOVToPredicate(vector, predicate, elementBits, lane int) error { + vectorValue, vectorType, err := c.loadZRegElements(vector, elementBits) + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return err + } + predicateType := fmt.Sprintf("", lanes) + result := c.newTmp() + if lane == 0 { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv%di%d(%s %s)\n", result, predicateType, lanes, elementBits, vectorType, vectorValue) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.pmov.to.pred.lane.nxv%di%d(%s %s, i32 %d)\n", result, predicateType, lanes, elementBits, vectorType, vectorValue, lane) + } + return c.storePRegElements(predicate, elementBits, "%"+result) +} + +func arm64SVEElementLetter(elementBits int) string { + return map[int]string{8: "B", 16: "H", 32: "S", 64: "D"}[elementBits] +} diff --git a/arm64_lower_sve_pmov_test.go b/arm64_lower_sve_pmov_test.go new file mode 100644 index 00000000..5ea68a30 --- /dev/null +++ b/arm64_lower_sve_pmov_test.go @@ -0,0 +1,106 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEPMOVCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svepmovforms(SB),$0-0\n") + source.WriteString("\tZPMOV P0.B, Z0\n") + source.WriteString("\tZPMOV Z1, P1.B\n") + for _, spec := range []struct { + letter string + maxLane int + predicate int + vector int + }{ + {letter: "H", maxLane: 1, predicate: 2, vector: 2}, + {letter: "S", maxLane: 3, predicate: 3, vector: 3}, + {letter: "D", maxLane: 7, predicate: 4, vector: 4}, + } { + for lane := 0; lane <= spec.maxLane; lane++ { + fmt.Fprintf(&source, "\tZPMOV P%d.%s, Z%d[%d]\n", spec.predicate, spec.letter, spec.vector, lane) + fmt.Fprintf(&source, "\tZPMOV Z%d[%d], P%d.%s\n", spec.vector+1, lane, spec.predicate+1, spec.letter) + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestParseARM64SVEPMOVIndexedRegisters(t *testing.T) { + file, err := Parse(ArchARM64, "TEXT parsepmov(SB),$0-0\n\tZPMOV P3.S, Z25[2]\n\tZPMOV Z27[1], P13.S\n\tRET\n") + if err != nil { + t.Fatal(err) + } + for _, operand := range []Operand{file.Funcs[0].Instrs[1].Args[1], file.Funcs[0].Instrs[2].Args[0]} { + if operand.Kind != OpReg { + t.Fatalf("indexed Z register parsed as kind %v: %+v", operand.Kind, operand) + } + } +} + +func TestTranslateARM64SVEPMOVCompleteGo127Family(t *testing.T) { + source := arm64SVEPMOVCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepmovforms": {Name: "svepmovforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2p1"`, + "@llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8", + "@llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16", + "@llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32", + "@llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE PMOV lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-pmov.ll", "arm64-sve-pmov.o", ll) + }) + } +} + +func TestTranslateARM64SVEPMOVRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZPMOV P0.B, Z0[0]", + "ZPMOV P0.H, Z0", + "ZPMOV P0.H, Z0[2]", + "ZPMOV P0.S, Z0[4]", + "ZPMOV P0.D, Z0[8]", + "ZPMOV Z0[2], P0.H", + "ZPMOV Z0[4], P0.S", + "ZPMOV Z0[8], P0.D", + "ZPMOV P16.B, Z0", + "ZPMOV Z32, P0.B", + "ZPMOV.Z P0.B, Z0", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepmov(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepmov": {Name: "badsvepmov", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE PMOV forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_pmul.go b/arm64_lower_sve_pmul.go new file mode 100644 index 00000000..31f3d661 --- /dev/null +++ b/arm64_lower_sve_pmul.go @@ -0,0 +1,32 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEPMUL(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZPMUL" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 ZPMUL expects Zm.B, Zn.B, Zd.B without a suffix: %q", ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != 8 || firstBits != 8 || destinationBits != 8 { + return true, false, fmt.Errorf("arm64 ZPMUL requires B-element vectors: %q", ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(first, 8) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, 8) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.pmul.nxv16i8(%s %s, %s %s)\n", result, vectorType, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeZRegElements(destination, 8, "%"+result) +} diff --git a/arm64_lower_sve_pmul_test.go b/arm64_lower_sve_pmul_test.go new file mode 100644 index 00000000..17f3ea94 --- /dev/null +++ b/arm64_lower_sve_pmul_test.go @@ -0,0 +1,54 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEPMULCompleteGo127Family(t *testing.T) { + source := "TEXT svepmulforms(SB),$0-0\n\tZPMUL Z1.B, Z2.B, Z3.B\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepmulforms": {Name: "svepmulforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2"`, "@llvm.aarch64.sve.pmul.nxv16i8"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE PMUL lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-pmul.ll", "arm64-sve-pmul.o", ll) + }) + } +} + +func TestTranslateARM64SVEPMULRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZPMUL Z1.H, Z2.H, Z3.H", + "ZPMUL Z1.B, Z2.H, Z3.B", + "ZPMUL Z1.B, Z2.B", + "ZPMUL.Z Z1.B, Z2.B, Z3.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepmul(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepmul": {Name: "badsvepmul", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE PMUL forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_pmull.go b/arm64_lower_sve_pmull.go new file mode 100644 index 00000000..fb01ad11 --- /dev/null +++ b/arm64_lower_sve_pmull.go @@ -0,0 +1,76 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEPMULLIntrinsics = map[Op]string{ + "ZPMULLB": "pmullb.pair", + "ZPMULLT": "pmullt.pair", +} + +func arm64SVEPMULLNeedsSVE2AES(ins Instr) bool { + if len(ins.Args) != 3 { + return false + } + _, ok := arm64ParseSVEZQReg(ins.Args[2]) + return ok +} + +func (c *arm64Ctx) lowerARM64SVEPMULL(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEPMULLIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zm.B, Zn.B, Zd.H; Zm.S, Zn.S, Zd.D; or Zm.D, Zn.D, Zd.Q without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + if !secondOK || !firstOK || secondBits != firstBits || firstBits != 8 && firstBits != 32 && firstBits != 64 { + return true, false, fmt.Errorf("arm64 %s requires matching B, S, or D source vectors: %q", op, ins.Raw) + } + destinationRepresentationBits := firstBits * 2 + destination := 0 + if firstBits == 64 { + var destinationOK bool + destination, destinationOK = arm64ParseSVEZQReg(ins.Args[2]) + if !destinationOK { + return true, false, fmt.Errorf("arm64 %s D sources require a Q destination: %q", op, ins.Raw) + } + destinationRepresentationBits = 64 + } else { + var destinationBits int + var destinationOK bool + destination, destinationBits, destinationOK = arm64ParseSVEZElementReg(ins.Args[2]) + if !destinationOK || destinationBits != destinationRepresentationBits { + return true, false, fmt.Errorf("arm64 %s must widen B to H or S to D: %q", op, ins.Raw) + } + } + firstValue, sourceType, err := c.loadZRegElements(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, firstBits) + if err != nil { + return true, false, err + } + _, sourceLanes, err := arm64SVEVectorType(firstBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, sourceType, intrinsic, sourceLanes, firstBits, sourceType, firstValue, sourceType, secondValue) + resultValue := "%" + result + if firstBits != 64 { + destinationType, _, err := arm64SVEVectorType(destinationRepresentationBits) + if err != nil { + return true, false, err + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", converted, sourceType, resultValue, destinationType) + resultValue = "%" + converted + } + return true, false, c.storeZRegElements(destination, destinationRepresentationBits, resultValue) +} diff --git a/arm64_lower_sve_pmull_pair.go b/arm64_lower_sve_pmull_pair.go new file mode 100644 index 00000000..8e326099 --- /dev/null +++ b/arm64_lower_sve_pmull_pair.go @@ -0,0 +1,61 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func arm64ParseSVEQPair(operand Operand) (first, second int, ok bool) { + if operand.Kind != OpRegList || !operand.RegListRange || len(operand.RegList) != 2 { + return 0, 0, false + } + first, firstOK := arm64ParseSVEZQReg(Operand{Kind: OpReg, Reg: operand.RegList[0]}) + second, secondOK := arm64ParseSVEZQReg(Operand{Kind: OpReg, Reg: operand.RegList[1]}) + return first, second, firstOK && secondOK && first%2 == 0 && second == first+1 +} + +func (c *arm64Ctx) lowerARM64SVEPMULLPair(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZPMULL" && op != "ZPMLAL" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Zm.D, Zn.D, [Zd.Q-Zd+1.Q] without a suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + firstDestination, secondDestination, destinationOK := arm64ParseSVEQPair(ins.Args[2]) + if !secondOK || !firstOK || secondBits != 64 || firstBits != 64 || !destinationOK { + return true, false, fmt.Errorf("arm64 %s requires D sources and an even-odd consecutive Q destination pair: %q", op, ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(first, 64) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, 64) + if err != nil { + return true, false, err + } + aggregateType := fmt.Sprintf("{ %s, %s }", vectorType, vectorType) + result := c.newTmp() + if op == "ZPMULL" { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.pmull.pair.x2(%s %s, %s %s)\n", result, aggregateType, vectorType, firstValue, vectorType, secondValue) + } else { + firstAccumulator, _, err := c.loadZRegElements(firstDestination, 64) + if err != nil { + return true, false, err + } + secondAccumulator, _, err := c.loadZRegElements(secondDestination, 64) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.pmlal.pair.x2(%s %s, %s %s, %s %s, %s %s)\n", result, aggregateType, vectorType, firstAccumulator, vectorType, secondAccumulator, vectorType, firstValue, vectorType, secondValue) + } + firstResult := c.newTmp() + secondResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 0\n", firstResult, aggregateType, result) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 1\n", secondResult, aggregateType, result) + if err := c.storeZRegElements(firstDestination, 64, "%"+firstResult); err != nil { + return true, false, err + } + return true, false, c.storeZRegElements(secondDestination, 64, "%"+secondResult) +} diff --git a/arm64_lower_sve_pmull_pair_test.go b/arm64_lower_sve_pmull_pair_test.go new file mode 100644 index 00000000..3d6085ff --- /dev/null +++ b/arm64_lower_sve_pmull_pair_test.go @@ -0,0 +1,75 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEPMULLPairCompleteGo127Family(t *testing.T) { + const source = ` +TEXT svepmullpair(SB),$0-0 + ZPMULL Z1.D, Z2.D, [Z4.Q-Z5.Q] + ZPMULL Z30.D, Z31.D, [Z30.Q-Z31.Q] + RET +TEXT svepmlalpair(SB),$0-0 + ZPMLAL Z6.D, Z7.D, [Z8.Q-Z9.Q] + ZPMLAL Z28.D, Z29.D, [Z30.Q-Z31.Q] + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + sigs := map[string]FuncSig{ + "svepmullpair": {Name: "svepmullpair", Ret: Void}, + "svepmlalpair": {Name: "svepmlalpair", Ret: Void}, + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve-aes2"`, + "@llvm.aarch64.sve.pmull.pair.x2", + "@llvm.aarch64.sve.pmlal.pair.x2", + "extractvalue { , }", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE PMULL/PMLAL pair lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-pmull-pair.ll", "arm64-sve-pmull-pair.o", ll) + }) + } +} + +func TestTranslateARM64SVEPMULLPairRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZPMULL Z1.S, Z2.S, [Z4.Q-Z5.Q]", + "ZPMULL Z1.D, Z2.D, [Z5.Q-Z6.Q]", + "ZPMULL Z1.D, Z2.D, [Z4.Q-Z7.Q]", + "ZPMULL Z1.D, Z2.D, [Z4.Q, Z5.Q]", + "ZPMLAL Z1.D, Z2.D, [Z4.D-Z5.D]", + "ZPMLAL Z1.D, Z2.D", + "ZPMLAL.Z Z1.D, Z2.D, [Z4.Q-Z5.Q]", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_", "[", "", "]", "").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepmullpair(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepmullpair": {Name: "badsvepmullpair", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE PMULL/PMLAL pair forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_pmull_test.go b/arm64_lower_sve_pmull_test.go new file mode 100644 index 00000000..7b1d0b25 --- /dev/null +++ b/arm64_lower_sve_pmull_test.go @@ -0,0 +1,80 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEPMULLBottomTopCompleteGo127Family(t *testing.T) { + const source = ` +TEXT svepmulllow(SB),$0-0 + ZPMULLB Z1.B, Z2.B, Z3.H + ZPMULLB Z4.S, Z5.S, Z6.D + ZPMULLT Z7.B, Z8.B, Z9.H + ZPMULLT Z10.S, Z11.S, Z12.D + RET +TEXT svepmullq(SB),$0-0 + ZPMULLB Z13.D, Z14.D, Z15.Q + ZPMULLT Z16.D, Z17.D, Z18.Q + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + sigs := map[string]FuncSig{ + "svepmulllow": {Name: "svepmulllow", Ret: Void}, + "svepmullq": {Name: "svepmullq", Ret: Void}, + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + `"target-features"="+sve,+sve2,+sve2-aes"`, + "@llvm.aarch64.sve.pmullb.pair.nxv16i8", + "@llvm.aarch64.sve.pmullb.pair.nxv4i32", + "@llvm.aarch64.sve.pmullb.pair.nxv2i64", + "@llvm.aarch64.sve.pmullt.pair.nxv16i8", + "@llvm.aarch64.sve.pmullt.pair.nxv4i32", + "@llvm.aarch64.sve.pmullt.pair.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE PMULLB/T lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-pmull.ll", "arm64-sve-pmull.o", ll) + }) + } +} + +func TestTranslateARM64SVEPMULLBottomTopRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZPMULLB Z1.H, Z2.H, Z3.S", + "ZPMULLB Z1.B, Z2.B, Z3.D", + "ZPMULLB Z1.D, Z2.D, Z3.D", + "ZPMULLT Z1.Q, Z2.Q, Z3.Q", + "ZPMULLT Z1.S, Z2.S", + "ZPMULLB.Z Z1.B, Z2.B, Z3.H", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepmull(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepmull": {Name: "badsvepmull", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE PMULLB/T forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_break.go b/arm64_lower_sve_predicate_break.go new file mode 100644 index 00000000..57f41438 --- /dev/null +++ b/arm64_lower_sve_predicate_break.go @@ -0,0 +1,145 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEPredicateBreakKind uint8 + +const ( + arm64SVEPredicateBreakSimple arm64SVEPredicateBreakKind = iota + arm64SVEPredicateBreakNext + arm64SVEPredicateBreakPair +) + +type arm64SVEPredicateBreakSpec struct { + intrinsic string + kind arm64SVEPredicateBreakKind + allowMerge bool + flags bool +} + +var arm64SVEPredicateBreakSpecs = map[Op]arm64SVEPredicateBreakSpec{ + "PBRKA": {intrinsic: "brka", kind: arm64SVEPredicateBreakSimple, allowMerge: true}, + "PBRKAS": {intrinsic: "brka.z", kind: arm64SVEPredicateBreakSimple, flags: true}, + "PBRKB": {intrinsic: "brkb", kind: arm64SVEPredicateBreakSimple, allowMerge: true}, + "PBRKBS": {intrinsic: "brkb.z", kind: arm64SVEPredicateBreakSimple, flags: true}, + "PBRKN": {intrinsic: "brkn.z", kind: arm64SVEPredicateBreakNext}, + "PBRKNS": {intrinsic: "brkn.z", kind: arm64SVEPredicateBreakNext, flags: true}, + "PBRKPA": {intrinsic: "brkpa.z", kind: arm64SVEPredicateBreakPair}, + "PBRKPAS": {intrinsic: "brkpa.z", kind: arm64SVEPredicateBreakPair, flags: true}, + "PBRKPB": {intrinsic: "brkpb.z", kind: arm64SVEPredicateBreakPair}, + "PBRKPBS": {intrinsic: "brkpb.z", kind: arm64SVEPredicateBreakPair, flags: true}, +} + +func (c *arm64Ctx) lowerARM64SVEPredicateBreak(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEPredicateBreakSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + wantArgs := 3 + if spec.kind != arm64SVEPredicateBreakSimple { + wantArgs = 4 + } + if len(ins.Args) != wantArgs { + return true, false, fmt.Errorf("arm64 %s expects its %d-operand Go 1.27 predicate-break form: %q", op, wantArgs, ins.Raw) + } + + first, firstBits, firstOK := arm64ParseSVEPredicateElement(ins.Args[0]) + if !firstOK || firstBits != 8 { + return true, false, fmt.Errorf("arm64 %s first predicate must be P0..P15.B: %q", op, ins.Raw) + } + if spec.kind == arm64SVEPredicateBreakSimple { + governing, merging := arm64ParseSVEPredicateMode(ins.Args[1], "M", 15) + if merging && !spec.allowMerge { + return true, false, fmt.Errorf("arm64 %s only accepts a zeroing governing predicate: %q", op, ins.Raw) + } + if !merging { + var zeroing bool + governing, zeroing = arm64ParseSVEPredicateMode(ins.Args[1], "Z", 15) + if !zeroing { + return true, false, fmt.Errorf("arm64 %s governing predicate must be P0..P15/M or P0..P15/Z: %q", op, ins.Raw) + } + } + destination, destinationBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[2]) + if !destinationOK || destinationBits != 8 { + return true, false, fmt.Errorf("arm64 %s destination predicate must be P0..P15.B: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVEPredicateBreakSimple(spec, first, governing, destination, merging) + } + + second, secondBits, secondOK := arm64ParseSVEPredicateElement(ins.Args[1]) + governing, governingOK := arm64ParseSVEPredicateMode(ins.Args[2], "Z", 15) + destination, destinationBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[3]) + if !secondOK || secondBits != 8 || !governingOK || !destinationOK || destinationBits != 8 { + return true, false, fmt.Errorf("arm64 %s only accepts .B predicates and P0..P15/Z: %q", op, ins.Raw) + } + if spec.kind == arm64SVEPredicateBreakNext && first != destination { + return true, false, fmt.Errorf("arm64 %s requires the first and destination predicates to be identical: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVEPredicateBreakThreeSource(spec, first, second, governing, destination) +} + +func (c *arm64Ctx) lowerARM64SVEPredicateBreakSimple(spec arm64SVEPredicateBreakSpec, source, governing, destination int, merging bool) error { + sourceValue, predicateType, err := c.loadPRegElements(source, 8) + if err != nil { + return err + } + governingValue, _, err := c.loadPRegElements(governing, 8) + if err != nil { + return err + } + result := c.newTmp() + if merging { + destinationValue, _, err := c.loadPRegElements(destination, 8) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv16i1(%s %s, %s %s, %s %s)\n", result, predicateType, spec.intrinsic, predicateType, destinationValue, predicateType, governingValue, predicateType, sourceValue) + } else { + intrinsic := spec.intrinsic + if spec.allowMerge { + intrinsic += ".z" + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv16i1(%s %s, %s %s)\n", result, predicateType, intrinsic, predicateType, governingValue, predicateType, sourceValue) + } + if err := c.storePRegElements(destination, 8, "%"+result); err != nil { + return err + } + if spec.flags { + c.setSVEPredicateFlags(governingValue, "%"+result, predicateType, 16) + } + return nil +} + +func (c *arm64Ctx) lowerARM64SVEPredicateBreakThreeSource(spec arm64SVEPredicateBreakSpec, first, second, governing, destination int) error { + firstValue, predicateType, err := c.loadPRegElements(first, 8) + if err != nil { + return err + } + secondValue, _, err := c.loadPRegElements(second, 8) + if err != nil { + return err + } + governingValue, _, err := c.loadPRegElements(governing, 8) + if err != nil { + return err + } + result := c.newTmp() + if spec.kind == arm64SVEPredicateBreakNext { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv16i1(%s %s, %s %s, %s %s)\n", result, predicateType, spec.intrinsic, predicateType, firstValue, predicateType, governingValue, predicateType, secondValue) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv16i1(%s %s, %s %s, %s %s)\n", result, predicateType, spec.intrinsic, predicateType, governingValue, predicateType, secondValue, predicateType, firstValue) + } + if err := c.storePRegElements(destination, 8, "%"+result); err != nil { + return err + } + if spec.flags { + c.setSVEPredicateFlags(governingValue, "%"+result, predicateType, 16) + } + return nil +} diff --git a/arm64_lower_sve_predicate_break_test.go b/arm64_lower_sve_predicate_break_test.go new file mode 100644 index 00000000..75c99ae8 --- /dev/null +++ b/arm64_lower_sve_predicate_break_test.go @@ -0,0 +1,86 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEPredicateBreakCompleteForms() string { + return `TEXT svepredicatebreakforms(SB),$0-0 + PBRKA P15.B, P14.M, P13.B + PBRKA P12.B, P11.Z, P10.B + PBRKAS P9.B, P8.Z, P7.B + PBRKB P6.B, P5.M, P4.B + PBRKB P3.B, P2.Z, P1.B + PBRKBS P0.B, P15.Z, P14.B + PBRKN P13.B, P12.B, P11.Z, P13.B + PBRKNS P10.B, P9.B, P8.Z, P10.B + PBRKPA P7.B, P6.B, P5.Z, P4.B + PBRKPAS P3.B, P2.B, P1.Z, P0.B + PBRKPB P15.B, P14.B, P13.Z, P12.B + PBRKPBS P11.B, P10.B, P9.Z, P8.B + RET +` +} + +func TestTranslateARM64SVEPredicateBreakCompleteGo127Family(t *testing.T) { + source := arm64SVEPredicateBreakCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicatebreakforms": {Name: "svepredicatebreakforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.brka.nxv16i1", + "@llvm.aarch64.sve.brka.z.nxv16i1", + "@llvm.aarch64.sve.brkb.nxv16i1", + "@llvm.aarch64.sve.brkb.z.nxv16i1", + "@llvm.aarch64.sve.brkn.z.nxv16i1", + "@llvm.aarch64.sve.brkpa.z.nxv16i1", + "@llvm.aarch64.sve.brkpb.z.nxv16i1", + "@llvm.aarch64.sve.ptest.any.nxv16i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate break lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-break.ll", "arm64-sve-predicate-break.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicateBreakRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PBRKA P1.H, P2.M, P3.B", + "PBRKAS P1.B, P2.M, P3.B", + "PBRKN P1.B, P2.B, P3.Z, P4.B", + "PBRKPA P1.B, P2.B, P3.M, P4.B", + "PBRKPB P1.B, P2.B, P16.Z, P4.B", + "PBRKPBS P1.B, P2.B, P3.Z", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicatebreak(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicatebreak": {Name: "badsvepredicatebreak", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE predicate break forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_counter.go b/arm64_lower_sve_predicate_counter.go new file mode 100644 index 00000000..dd1e6ec2 --- /dev/null +++ b/arm64_lower_sve_predicate_counter.go @@ -0,0 +1,168 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEPredicateCounterOps = map[Op]struct{}{ + "PPTRUE": {}, + "PCNTP": {}, + "PPEXT": {}, +} + +func arm64SVEPredicateCounterNeedsSVE2P1(op Op, ins Instr) bool { + if op == "PPTRUE" || op == "PPEXT" { + return true + } + return op == "PCNTP" && len(ins.Args) == 3 && ins.Args[1].Kind == OpReg && strings.HasPrefix(strings.ToUpper(string(ins.Args[1].Reg)), "PN") +} + +func arm64ParseSVEPredicateCounterElement(operand Operand) (index, elementBits int, ok bool) { + if operand.Kind != OpReg { + return 0, 0, false + } + parts := strings.Split(strings.ToUpper(strings.TrimSpace(string(operand.Reg))), ".") + if len(parts) != 2 || !strings.HasPrefix(parts[0], "PN") { + return 0, 0, false + } + if _, err := fmt.Sscanf(parts[0], "PN%d", &index); err != nil || index < 0 || index > 15 { + return 0, 0, false + } + elementBits, ok = map[string]int{"B": 8, "H": 16, "S": 32, "D": 64}[parts[1]] + return index, elementBits, ok +} + +func arm64ParseSVEPredicateCounterIndexed(operand Operand) (index, lane int, ok bool) { + if operand.Kind != OpReg { + return 0, 0, false + } + text := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + open := strings.IndexByte(text, '[') + if open < 0 || !strings.HasSuffix(text, "]") || !strings.HasPrefix(text, "PN") { + return 0, 0, false + } + if _, err := fmt.Sscanf(text[:open], "PN%d", &index); err != nil || index < 8 || index > 15 { + return 0, 0, false + } + if _, err := fmt.Sscanf(text[open:], "[%d]", &lane); err != nil || lane < 0 || lane > 3 { + return 0, 0, false + } + return index, lane, true +} + +func (c *arm64Ctx) lowerARM64SVEPredicateCounter(op Op, ins Instr) (ok bool, terminated bool, err error) { + if _, ok := arm64SVEPredicateCounterOps[op]; !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if op == "PCNTP" { + return c.lowerARM64SVEPredicateCount(ins) + } + if op == "PPEXT" { + return c.lowerARM64SVEPredicateExtract(ins) + } + if len(ins.Args) != 1 { + return true, false, fmt.Errorf("arm64 PPTRUE expects PNd.T: %q", ins.Raw) + } + destination, elementBits, destinationOK := arm64ParseSVEPredicateCounterElement(ins.Args[0]) + if !destinationOK || destination < 8 { + return true, false, fmt.Errorf("arm64 PPTRUE only accepts PN8..PN15.B/H/S/D: %q", ins.Raw) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call target(\"aarch64.svcount\") @llvm.aarch64.sve.ptrue.c%d()\n", result, elementBits) + return true, false, c.storePNReg(destination, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEPredicateExtract(ins Instr) (ok bool, terminated bool, err error) { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 PPEXT expects PNn[index], Pd.T or PNn[index], [Pd1.T, Pd2.T]: %q", ins.Raw) + } + counter, lane, counterOK := arm64ParseSVEPredicateCounterIndexed(ins.Args[0]) + if !counterOK { + return true, false, fmt.Errorf("arm64 PPEXT source must be PN8..PN15[0..3]: %q", ins.Raw) + } + counterValue, err := c.loadPNReg(counter) + if err != nil { + return true, false, err + } + if ins.Args[1].Kind == OpReg { + destination, elementBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[1]) + if !destinationOK { + return true, false, fmt.Errorf("arm64 PPEXT destination must be P0..P15.B/H/S/D: %q", ins.Raw) + } + lanes := 128 / elementBits + predicateType := fmt.Sprintf("", lanes) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.pext.nxv%di1(target(\"aarch64.svcount\") %s, i32 %d)\n", result, predicateType, lanes, counterValue, lane) + return true, false, c.storePRegElements(destination, elementBits, "%"+result) + } + if ins.Args[1].Kind != OpRegList || len(ins.Args[1].RegList) != 2 || lane > 1 { + return true, false, fmt.Errorf("arm64 PPEXT pair form requires lane 0..1 and exactly two predicate destinations: %q", ins.Raw) + } + first, firstBits, firstOK := arm64ParseSVEPredicateElement(Operand{Kind: OpReg, Reg: ins.Args[1].RegList[0]}) + second, secondBits, secondOK := arm64ParseSVEPredicateElement(Operand{Kind: OpReg, Reg: ins.Args[1].RegList[1]}) + if !firstOK || !secondOK || firstBits != secondBits || second != first+1 { + return true, false, fmt.Errorf("arm64 PPEXT pair destinations must be two consecutive predicates with matching arrangements: %q", ins.Raw) + } + lanes := 128 / firstBits + predicateType := fmt.Sprintf("", lanes) + aggregateType := fmt.Sprintf("{ %s, %s }", predicateType, predicateType) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.pext.x2.nxv%di1(target(\"aarch64.svcount\") %s, i32 %d)\n", result, aggregateType, lanes, counterValue, lane) + firstValue := c.newTmp() + secondValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 0\n", firstValue, aggregateType, result) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 1\n", secondValue, aggregateType, result) + if err := c.storePRegElements(first, firstBits, "%"+firstValue); err != nil { + return true, false, err + } + return true, false, c.storePRegElements(second, secondBits, "%"+secondValue) +} + +func (c *arm64Ctx) lowerARM64SVEPredicateCount(ins Instr) (ok bool, terminated bool, err error) { + if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[2].Reg) { + return true, false, fmt.Errorf("arm64 PCNTP expects Pn.T, Pg, Xd or VLx2|VLx4, PNn.T, Xd: %q", ins.Raw) + } + if tested, elementBits, testedOK := arm64ParseSVEPredicateElement(ins.Args[0]); testedOK { + governing, governingOK := arm64ParseSVEPredicateBare(ins.Args[1], 15) + if !governingOK { + return true, false, fmt.Errorf("arm64 PCNTP ordinary predicate form requires a bare P0..P15 governing predicate: %q", ins.Raw) + } + governingValue, predicateType, err := c.loadPRegElements(governing, elementBits) + if err != nil { + return true, false, err + } + testedValue, _, err := c.loadPRegElements(tested, elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.aarch64.sve.cntp.nxv%di1(%s %s, %s %s)\n", result, lanes, predicateType, governingValue, predicateType, testedValue) + return true, false, c.storeReg(ins.Args[2].Reg, "%"+result) + } + + multiplier := 0 + if ins.Args[0].Kind == OpIdent { + switch strings.ToUpper(ins.Args[0].Ident) { + case "VLX2": + multiplier = 2 + case "VLX4": + multiplier = 4 + } + } + counter, elementBits, counterOK := arm64ParseSVEPredicateCounterElement(ins.Args[1]) + if multiplier == 0 || !counterOK { + return true, false, fmt.Errorf("arm64 PCNTP predicate-as-counter form requires VLx2|VLx4 and PN0..PN15.B/H/S/D: %q", ins.Raw) + } + counterValue, err := c.loadPNReg(counter) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.aarch64.sve.cntp.c%d(target(\"aarch64.svcount\") %s, i32 %d)\n", result, elementBits, counterValue, multiplier) + return true, false, c.storeReg(ins.Args[2].Reg, "%"+result) +} diff --git a/arm64_lower_sve_predicate_counter_test.go b/arm64_lower_sve_predicate_counter_test.go new file mode 100644 index 00000000..c8735c79 --- /dev/null +++ b/arm64_lower_sve_predicate_counter_test.go @@ -0,0 +1,96 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEPredicateCounterCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svepredicatecountertrueforms(SB),$0-0\n") + for index, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\tPPTRUE PN%d.%s\n", 8+index, width) + fmt.Fprintf(&source, "\tPCNTP P%d.%s, P%d, R%d\n", 15-index, width, 11-index, index) + fmt.Fprintf(&source, "\tPCNTP VLx2, PN%d.%s, R%d\n", index, width, 4+index) + fmt.Fprintf(&source, "\tPCNTP VLx4, PN%d.%s, R%d\n", 12+index, width, 8+index) + fmt.Fprintf(&source, "\tPPEXT PN%d[%d], P%d.%s\n", 8+index, index, index, width) + fmt.Fprintf(&source, "\tPPEXT PN%d[%d], [P%d.%s, P%d.%s]\n", 12+index, index%2, 2*index, width, 2*index+1, width) + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEPredicateCounterCompleteGo127Family(t *testing.T) { + source := arm64SVEPredicateCounterCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicatecountertrueforms": {Name: "svepredicatecountertrueforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2p1"`, + "@llvm.aarch64.sve.ptrue.c8", + "@llvm.aarch64.sve.ptrue.c16", + "@llvm.aarch64.sve.ptrue.c32", + "@llvm.aarch64.sve.ptrue.c64", + "@llvm.aarch64.sve.cntp.nxv16i1", + "@llvm.aarch64.sve.cntp.nxv2i1", + "@llvm.aarch64.sve.cntp.c8", + "@llvm.aarch64.sve.cntp.c64", + "@llvm.aarch64.sve.pext.nxv16i1", + "@llvm.aarch64.sve.pext.nxv2i1", + "@llvm.aarch64.sve.pext.x2.nxv8i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate-as-counter true lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-counter.ll", "arm64-sve-predicate-counter.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicateCounterRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PPTRUE P8.B", + "PPTRUE PN7.B", + "PPTRUE PN16.B", + "PPTRUE PN8.Q", + "PPTRUE PN8.B, PN9.B", + "PCNTP P1.B, P2.Z, R3", + "PCNTP VLx3, PN8.B, R3", + "PCNTP VLx2, PN16.B, R3", + "PCNTP VLx2, PN8.Q, R3", + "PCNTP VLx2, PN8.B, R31", + "PPEXT PN7[0], P1.B", + "PPEXT PN8[4], P1.B", + "PPEXT PN8[2], [P1.B, P2.B]", + "PPEXT PN8[0], [P1.B, P3.B]", + "PPEXT PN8[0], [P1.B, P2.H]", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicatecounter(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicatecounter": {Name: "badsvepredicatecounter", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's predicate-as-counter true forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_incdec.go b/arm64_lower_sve_predicate_incdec.go new file mode 100644 index 00000000..4c814e0b --- /dev/null +++ b/arm64_lower_sve_predicate_incdec.go @@ -0,0 +1,113 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEPredicateIncDecSpec struct { + increment bool + saturating bool + unsigned bool + word bool + splitWord bool +} + +var arm64SVEPredicateIncDecSpecs = map[Op]arm64SVEPredicateIncDecSpec{ + "PDECP": {}, + "PINCP": {increment: true}, + "PSQDECP": {saturating: true}, + "PSQDECPW": {saturating: true, word: true, splitWord: true}, + "PSQINCP": {increment: true, saturating: true}, + "PSQINCPW": {increment: true, saturating: true, word: true, splitWord: true}, + "PUQDECP": {saturating: true, unsigned: true}, + "PUQDECPW": {saturating: true, unsigned: true, word: true}, + "PUQINCP": {increment: true, saturating: true, unsigned: true}, + "PUQINCPW": {increment: true, saturating: true, unsigned: true, word: true}, +} + +func (c *arm64Ctx) lowerARM64SVEPredicateIncDec(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEPredicateIncDecSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + predicateOperand := 0 + registerOperand := 1 + if spec.splitWord { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Wdn, Pm.T, Xdn: %q", op, ins.Raw) + } + predicateOperand = 1 + registerOperand = 2 + if ins.Args[0].Kind != OpReg || ins.Args[2].Kind != OpReg || ins.Args[0].Reg != ins.Args[2].Reg { + return true, false, fmt.Errorf("arm64 %s requires matching Wdn and Xdn registers: %q", op, ins.Raw) + } + } else if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects Pm.T, Xdn: %q", op, ins.Raw) + } + predicate, elementBits, predicateOK := arm64ParseSVEPredicateElement(ins.Args[predicateOperand]) + register, registerOK := arm64SVEIncDecRegister(ins.Args[registerOperand]) + if !predicateOK || !registerOK { + return true, false, fmt.Errorf("arm64 %s requires P0..P15.B/H/S/D and a general register or ZR: %q", op, ins.Raw) + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + scalar, err := c.loadReg(register) + if err != nil { + return true, false, err + } + if !spec.saturating { + governing, _, err := c.allTruePRegElements(elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + count := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.aarch64.sve.cntp.nxv%di1(%s %s, %s %s)\n", count, lanes, predicateType, governing, predicateType, predicateValue) + result := c.newTmp() + operation := "sub" + if spec.increment { + operation = "add" + } + fmt.Fprintf(c.b, " %%%s = %s i64 %s, %%%s\n", result, operation, scalar, count) + return true, false, c.storeReg(register, "%"+result) + } + scalarType := "i64" + width := 64 + if spec.word { + width = 32 + scalarType = "i32" + truncated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", truncated, scalar) + scalar = "%" + truncated + } + intrinsic := "sqdec" + if spec.unsigned { + intrinsic = "uqdec" + } + if spec.increment { + intrinsic = strings.Replace(intrinsic, "dec", "inc", 1) + } + lanes := 128 / elementBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%sp.n%d.nxv%di1(%s %s, %s %s)\n", result, scalarType, intrinsic, width, lanes, scalarType, scalar, predicateType, predicateValue) + value := "%" + result + if spec.word { + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", extended, value) + value = "%" + extended + } + return true, false, c.storeReg(register, value) +} + +func arm64SVEIncDecRegister(operand Operand) (Reg, bool) { + if operand.Kind != OpReg || !isARM64GeneralOrZeroReg(operand.Reg) { + return "", false + } + return operand.Reg, true +} diff --git a/arm64_lower_sve_predicate_incdec_test.go b/arm64_lower_sve_predicate_incdec_test.go new file mode 100644 index 00000000..0b4dc7b9 --- /dev/null +++ b/arm64_lower_sve_predicate_incdec_test.go @@ -0,0 +1,88 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEPredicateIncDecCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svepredicateincdecforms(SB),$0-0\n") + for widthIndex, width := range []string{"B", "H", "S", "D"} { + predicate := 1 + widthIndex + register := 5 + widthIndex + fmt.Fprintf(&source, "\tPDECP P%d.%s, R%d\n", predicate, width, register) + fmt.Fprintf(&source, "\tPINCP P%d.%s, R%d\n", predicate, width, register) + for _, op := range []string{"PSQDECP", "PSQINCP", "PUQDECP", "PUQINCP"} { + fmt.Fprintf(&source, "\t%s P%d.%s, R%d\n", op, predicate, width, register) + } + for _, op := range []string{"PSQDECPW", "PSQINCPW"} { + fmt.Fprintf(&source, "\t%s R%d, P%d.%s, R%d\n", op, register, predicate, width, register) + } + for _, op := range []string{"PUQDECPW", "PUQINCPW"} { + fmt.Fprintf(&source, "\t%s P%d.%s, R%d\n", op, predicate, width, register) + } + } + source.WriteString("\tPDECP P14.S, ZR\n\tPSQDECP P14.S, ZR\n\tPUQINCPW P14.S, ZR\n\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEPredicateIncDecCompleteGo127Family(t *testing.T) { + source := arm64SVEPredicateIncDecCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicateincdecforms": {Name: "svepredicateincdecforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.cntp.nxv16i1", + "@llvm.aarch64.sve.cntp.nxv2i1", + "@llvm.aarch64.sve.sqdecp.n64.nxv8i1", + "@llvm.aarch64.sve.sqincp.n32.nxv4i1", + "@llvm.aarch64.sve.uqdecp.n64.nxv2i1", + "@llvm.aarch64.sve.uqincp.n32.nxv16i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate inc/dec lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-incdec.ll", "arm64-sve-predicate-incdec.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicateIncDecRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PDECP P1.Q, R2", + "PINCP P1.B, RSP", + "PSQDECPW R1, P2.B, R3", + "PUQINCPW R1, P2.B, R1", + "PSQINCP P1.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicateincdec(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicateincdec": {Name: "badsvepredicateincdec", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE predicate inc/dec forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_iterate.go b/arm64_lower_sve_predicate_iterate.go new file mode 100644 index 00000000..11968e82 --- /dev/null +++ b/arm64_lower_sve_predicate_iterate.go @@ -0,0 +1,48 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEPredicateIterateSpec struct { + intrinsic string + byteOnly bool +} + +var arm64SVEPredicateIterateSpecs = map[Op]arm64SVEPredicateIterateSpec{ + "PPFIRST": {intrinsic: "pfirst", byteOnly: true}, + "PPNEXT": {intrinsic: "pnext"}, +} + +func (c *arm64Ctx) lowerARM64SVEPredicateIterate(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEPredicateIterateSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Pdn.T, Pg, Pdn.T: %q", op, ins.Raw) + } + current, currentBits, currentOK := arm64ParseSVEPredicateElement(ins.Args[0]) + governing, governingOK := arm64ParseSVEPredicateBare(ins.Args[1], 15) + destination, destinationBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[2]) + if !currentOK || !governingOK || !destinationOK || current != destination || currentBits != destinationBits || (spec.byteOnly && currentBits != 8) { + return true, false, fmt.Errorf("arm64 %s operands do not match its Go 1.27 read-modify-write predicate form: %q", op, ins.Raw) + } + governingValue, predicateType, err := c.loadPRegElements(governing, currentBits) + if err != nil { + return true, false, err + } + currentValue, _, err := c.loadPRegElements(current, currentBits) + if err != nil { + return true, false, err + } + lanes := 128 / currentBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di1(%s %s, %s %s)\n", result, predicateType, spec.intrinsic, lanes, predicateType, governingValue, predicateType, currentValue) + if err := c.storePRegElements(destination, currentBits, "%"+result); err != nil { + return true, false, err + } + c.setSVEPredicateFlags(governingValue, "%"+result, predicateType, lanes) + return true, false, nil +} diff --git a/arm64_lower_sve_predicate_iterate_test.go b/arm64_lower_sve_predicate_iterate_test.go new file mode 100644 index 00000000..27f43d82 --- /dev/null +++ b/arm64_lower_sve_predicate_iterate_test.go @@ -0,0 +1,78 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEPredicateIterateCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svepredicateiterateforms(SB),$0-0\n") + source.WriteString("\tPPFIRST P15.B, P14, P15.B\n") + for index, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\tPPNEXT P%d.%s, P%d, P%d.%s\n", 13-index, width, 9-index, 13-index, width) + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEPredicateIterateCompleteGo127Family(t *testing.T) { + source := arm64SVEPredicateIterateCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicateiterateforms": {Name: "svepredicateiterateforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.pfirst.nxv16i1", + "@llvm.aarch64.sve.pnext.nxv16i1", + "@llvm.aarch64.sve.pnext.nxv8i1", + "@llvm.aarch64.sve.pnext.nxv4i1", + "@llvm.aarch64.sve.pnext.nxv2i1", + "@llvm.aarch64.sve.ptest.any.nxv16i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate iterate lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-iterate.ll", "arm64-sve-predicate-iterate.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicateIterateRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PPFIRST P1.H, P2, P1.H", + "PPFIRST P1.B, P2.Z, P1.B", + "PPFIRST P1.B, P2, P3.B", + "PPNEXT P1.B, P2.Z, P1.B", + "PPNEXT P1.B, P2, P3.B", + "PPNEXT P1.B, P2", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicateiterate(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicateiterate": {Name: "badsvepredicateiterate", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE predicate iterate forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_logical.go b/arm64_lower_sve_predicate_logical.go new file mode 100644 index 00000000..8acaf905 --- /dev/null +++ b/arm64_lower_sve_predicate_logical.go @@ -0,0 +1,96 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEPredicateLogicalSpec struct { + operation string + flags bool +} + +var arm64SVEPredicateLogicalSpecs = map[Op]arm64SVEPredicateLogicalSpec{ + "PAND": {operation: "and"}, + "PANDS": {operation: "and", flags: true}, + "PBIC": {operation: "bic"}, + "PBICS": {operation: "bic", flags: true}, + "PEOR": {operation: "xor"}, + "PEORS": {operation: "xor", flags: true}, + "PNAND": {operation: "nand"}, + "PNANDS": {operation: "nand", flags: true}, + "PNOR": {operation: "nor"}, + "PNORS": {operation: "nor", flags: true}, + "PORN": {operation: "orn"}, + "PORNS": {operation: "orn", flags: true}, + "PORR": {operation: "or"}, + "PORRS": {operation: "or", flags: true}, +} + +func (c *arm64Ctx) lowerARM64SVEPredicateLogical(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEPredicateLogicalSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects Pm.B, Pn.B, Pg/Z, Pd.B: %q", op, ins.Raw) + } + first, firstBits, firstOK := arm64ParseSVEPredicateElement(ins.Args[0]) + second, secondBits, secondOK := arm64ParseSVEPredicateElement(ins.Args[1]) + governing, governingOK := arm64ParseSVEPredicateMode(ins.Args[2], "Z", 15) + destination, destinationBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[3]) + if !firstOK || !secondOK || !governingOK || !destinationOK || firstBits != 8 || secondBits != 8 || destinationBits != 8 { + return true, false, fmt.Errorf("arm64 %s only accepts the Go 1.27 Pm.B, Pn.B, Pg/Z, Pd.B form: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVEPredicateLogicalForm(spec, first, second, governing, destination) +} + +func (c *arm64Ctx) lowerARM64SVEPredicateLogicalForm(spec arm64SVEPredicateLogicalSpec, first, second, governing, destination int) error { + firstValue, predicateType, err := c.loadPRegElements(first, 8) + if err != nil { + return err + } + secondValue, _, err := c.loadPRegElements(second, 8) + if err != nil { + return err + } + governingValue, _, err := c.loadPRegElements(governing, 8) + if err != nil { + return err + } + + result := c.newTmp() + switch spec.operation { + case "and", "xor", "or": + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", result, spec.operation, predicateType, secondValue, firstValue) + case "bic", "orn": + inverted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor %s %s, splat (i1 true)\n", inverted, predicateType, firstValue) + operation := "and" + if spec.operation == "orn" { + operation = "or" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s, %%%s\n", result, operation, predicateType, secondValue, inverted) + case "nand", "nor": + combined := c.newTmp() + operation := "and" + if spec.operation == "nor" { + operation = "or" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", combined, operation, predicateType, secondValue, firstValue) + fmt.Fprintf(c.b, " %%%s = xor %s %%%s, splat (i1 true)\n", result, predicateType, combined) + default: + return fmt.Errorf("unsupported ARM64 SVE predicate logical operation %q", spec.operation) + } + + active := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and %s %%%s, %s\n", active, predicateType, result, governingValue) + if err := c.storePRegElements(destination, 8, "%"+active); err != nil { + return err + } + if !spec.flags { + return nil + } + c.setSVEPredicateFlags(governingValue, "%"+active, predicateType, 16) + return nil +} diff --git a/arm64_lower_sve_predicate_logical_test.go b/arm64_lower_sve_predicate_logical_test.go new file mode 100644 index 00000000..e3cfc606 --- /dev/null +++ b/arm64_lower_sve_predicate_logical_test.go @@ -0,0 +1,70 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEPredicateLogicalCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svepredicatelogicalforms(SB),$0-0\n") + for index, op := range []string{"PAND", "PANDS", "PBIC", "PBICS", "PEOR", "PEORS", "PNAND", "PNANDS", "PNOR", "PNORS", "PORN", "PORNS", "PORR", "PORRS"} { + predicate := index % 16 + source.WriteString(fmt.Sprintf("\t%s P15.B, P14.B, P%d.Z, P13.B\n", op, predicate)) + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEPredicateLogicalCompleteGo127Family(t *testing.T) { + source := arm64SVEPredicateLogicalCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicatelogicalforms": {Name: "svepredicatelogicalforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve"`, "@llvm.aarch64.sve.ptest.any.nxv", "@llvm.aarch64.sve.ptest.first.nxv", "@llvm.aarch64.sve.ptest.last.nxv"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate logical lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-logical.ll", "arm64-sve-predicate-logical.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicateLogicalRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PAND P1.B, P2.H, P0.Z, P3.B", + "PBIC P1.B, P2.B, P0.M, P3.B", + "PEOR P1.B, P2.B, P16.Z, P3.B", + "PNAND P1.B, P2.B, P0.Z, P3.H", + "PORR P1, P2.B, P0.Z, P3.B", + "PORRS P1.B, P2.B, P0.Z", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicatelogical(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicatelogical": {Name: "badsvepredicatelogical", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE predicate logical forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_memory.go b/arm64_lower_sve_predicate_memory.go new file mode 100644 index 00000000..193193a1 --- /dev/null +++ b/arm64_lower_sve_predicate_memory.go @@ -0,0 +1,190 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEPredicateMemoryOps = map[Op]int{ + "PLDR": 0, + "PSTR": 0, + "PPRFB": 8, + "PPRFH": 16, + "PPRFW": 32, + "PPRFD": 64, +} + +func (c *arm64Ctx) lowerARM64SVEPredicateMemory(op Op, ins Instr) (ok bool, terminated bool, err error) { + elementBits, ok := arm64SVEPredicateMemoryOps[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if op == "PLDR" || op == "PSTR" { + return c.lowerARM64SVEPredicateLoadStore(op, ins) + } + return c.lowerARM64SVEPredicatePrefetch(op, elementBits, ins) +} + +func (c *arm64Ctx) lowerARM64SVEPredicateLoadStore(op Op, ins Instr) (ok bool, terminated bool, err error) { + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects its two-operand Go 1.27 form: %q", op, ins.Raw) + } + memoryOperand := 0 + predicateOperand := 1 + if op == "PSTR" { + predicateOperand, memoryOperand = memoryOperand, predicateOperand + } + if ins.Args[memoryOperand].Kind != OpMem { + return true, false, fmt.Errorf("arm64 %s requires a MUL VL memory operand: %q", op, ins.Raw) + } + predicate, predicateOK := arm64ParseSVEPredicateBare(ins.Args[predicateOperand], 15) + if !predicateOK { + return true, false, fmt.Errorf("arm64 %s predicate must be P0..P15 without an arrangement: %q", op, ins.Raw) + } + address, err := c.arm64SVEVLAddress(ins.Args[memoryOperand].Mem, -256, 255, 2) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + if op == "PLDR" { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load , ptr %%%s, align 1\n", value, pointer) + return true, false, c.storePReg(predicate, "%"+value) + } + value, err := c.loadPReg(predicate) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store %s, ptr %%%s, align 1\n", value, pointer) + return true, false, nil +} + +func (c *arm64Ctx) lowerARM64SVEPredicatePrefetch(op Op, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + if len(ins.Args) != 3 || ins.Args[0].Kind != OpMem { + return true, false, fmt.Errorf("arm64 %s expects memory, Pg, prfop: %q", op, ins.Raw) + } + predicate, predicateOK := arm64ParseSVEPredicateBare(ins.Args[1], 7) + hint, hintOK := arm64SVEPrefetchHint(ins.Args[2]) + if !predicateOK || !hintOK { + return true, false, fmt.Errorf("arm64 %s requires P0..P7 and an SVE data prefetch operation: %q", op, ins.Raw) + } + memory := ins.Args[0].Mem + var address string + if memory.Index != "" { + address, err = c.arm64SVERegisterOffsetAddress(memory, int64(elementBits/8)) + } else { + address, err = c.arm64SVEVLAddress(memory, -32, 31, 16) + } + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + lanes := 128 / elementBits + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.prf.nxv%di1(%s %s, ptr %%%s, i32 %d)\n", lanes, predicateType, predicateValue, pointer, hint) + return true, false, nil +} + +func (c *arm64Ctx) arm64SVEVLAddress(memory MemRef, minimum, maximum, bytesPerVScale int64) (string, error) { + if memory.Sym != "" || memory.Segment != "" || memory.Index != "" || memory.Off != 0 { + return "", fmt.Errorf("address is not a scalar base plus MUL VL immediate") + } + baseReg, ok := arm64SVEPhysicalMemoryBase(memory.Base) + if !ok { + return "", fmt.Errorf("address base must be R0..R30, RSP, or ZR") + } + multiplier := int64(0) + if memory.OffRaw != "" { + var parsed bool + multiplier, parsed = parseVectorLengthScaleExpr(memory.OffRaw) + if !parsed { + return "", fmt.Errorf("address displacement must be VL*imm") + } + } + if multiplier < minimum || multiplier > maximum { + return "", fmt.Errorf("MUL VL immediate %d is outside [%d,%d]", multiplier, minimum, maximum) + } + base, err := c.loadReg(baseReg) + if err != nil { + return "", err + } + if multiplier == 0 { + return base, nil + } + vscale := c.newTmp() + offset := c.newTmp() + address := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.vscale.i64()\n", vscale) + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %d\n", offset, vscale, multiplier*bytesPerVScale) + fmt.Fprintf(c.b, " %%%s = add i64 %s, %%%s\n", address, base, offset) + return "%" + address, nil +} + +func (c *arm64Ctx) arm64SVERegisterOffsetAddress(memory MemRef, expectedScale int64) (string, error) { + if memory.Sym != "" || memory.Segment != "" || memory.Off != 0 || memory.OffRaw != "" || memory.IndexExt != "" || memory.Scale != expectedScale { + return "", fmt.Errorf("register-offset address requires its exact LSL element scale") + } + baseReg := memory.Base + indexReg := memory.Index + // PPRFB's unshifted Go syntax is (Xm)(Xn|RSP); the generic Plan 9 + // memory parser records the first parenthesis as Base, so restore the + // architectural base/index order here. Shifted H/W/D forms are normalized + // by parseMem into the architectural order. + if expectedScale == 1 { + baseReg, indexReg = indexReg, baseReg + } + baseReg, baseOK := arm64SVEPhysicalMemoryBase(baseReg) + if !baseOK || !isARM64GeneralOrZeroReg(indexReg) || indexReg == ZR { + return "", fmt.Errorf("register-offset address requires R0..R30 index and scalar base") + } + base, err := c.loadReg(baseReg) + if err != nil { + return "", err + } + index, err := c.loadReg(indexReg) + if err != nil { + return "", err + } + scaled := index + if expectedScale != 1 { + shifted := c.newTmp() + shift := map[int64]int64{2: 1, 4: 2, 8: 3, 16: 4}[expectedScale] + fmt.Fprintf(c.b, " %%%s = shl i64 %s, %d\n", shifted, index, shift) + scaled = "%" + shifted + } + address := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %s\n", address, base, scaled) + return "%" + address, nil +} + +func arm64SVEPhysicalMemoryBase(register Reg) (Reg, bool) { + if register == Reg("RSP") || register == ZR { + return SP, true + } + if isARM64GeneralOrZeroReg(register) && register != ZR { + return register, true + } + return "", false +} + +func arm64SVEPrefetchHint(operand Operand) (int, bool) { + if operand.Kind != OpIdent { + return 0, false + } + encoded, ok := arm64PrefetchOperations[arm64PrefetchOperation(strings.ToUpper(strings.TrimSpace(operand.Ident)))] + if !ok || encoded >= 8 && encoded <= 13 { + return 0, false + } + if encoded >= 16 { + encoded -= 8 + } + return int(encoded), true +} diff --git a/arm64_lower_sve_predicate_memory_test.go b/arm64_lower_sve_predicate_memory_test.go new file mode 100644 index 00000000..e837d08d --- /dev/null +++ b/arm64_lower_sve_predicate_memory_test.go @@ -0,0 +1,111 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEPredicateMemoryCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svepredicatememoryforms(SB),$0-0\n") + source.WriteString("\tPLDR (-VL*256)(R0), P0\n") + source.WriteString("\tPLDR (VL*255)(RSP), P15\n") + source.WriteString("\tPSTR P14, (-VL*256)(R1)\n") + source.WriteString("\tPSTR P1, (VL*255)(RSP)\n") + hints := []string{ + "PLDL1KEEP", "PLDL1STRM", "PLDL2KEEP", "PLDL2STRM", "PLDL3KEEP", "PLDL3STRM", + "PSTL1KEEP", "PSTL1STRM", "PSTL2KEEP", "PSTL2STRM", "PSTL3KEEP", "PSTL3STRM", + } + for index, hint := range hints { + fmt.Fprintf(&source, "\tPPRFB (VL*%d)(R2), P%d, %s\n", index%32, index%8, hint) + } + source.WriteString("\tPPRFB (R8)(RSP), P3, PSTL3KEEP\n") + source.WriteString("\tPPRFH (R8<<1)(RSP), P3, PSTL3KEEP\n") + source.WriteString("\tPPRFW (R8<<2)(RSP), P3, PSTL3KEEP\n") + source.WriteString("\tPPRFD (R8<<3)(RSP), P3, PSTL3KEEP\n") + source.WriteString("\tPPRFB (-VL*32)(R3), P0, PLDL1KEEP\n") + source.WriteString("\tPPRFH (VL*31)(R4), P1, PLDL1STRM\n") + source.WriteString("\tPPRFW (-VL*32)(R5), P2, PSTL1KEEP\n") + source.WriteString("\tPPRFD (VL*31)(R6), P7, PSTL3STRM\n") + source.WriteString("\tRET\n") + return source.String() +} + +func TestParseARM64SVEPredicateMemoryRetainsAddressSemantics(t *testing.T) { + file, err := Parse(ArchARM64, "TEXT parsepredmem(SB),$0-0\n\tPLDR (-VL*2)(RSP), P5\n\tPPRFD (R8<<3)(RSP), P3, PSTL3KEEP\n\tRET\n") + if err != nil { + t.Fatal(err) + } + loadMemory := file.Funcs[0].Instrs[1].Args[0].Mem + if loadMemory.Base != Reg("RSP") || loadMemory.OffRaw != "-VL*2" { + t.Fatalf("PLDR address parsed as %+v, want RSP plus -VL*2", loadMemory) + } + prefetchMemory := file.Funcs[0].Instrs[2].Args[0].Mem + if prefetchMemory.Base != Reg("RSP") || prefetchMemory.Index != Reg("R8") || prefetchMemory.Scale != 8 { + t.Fatalf("PPRFD address parsed as %+v, want RSP plus R8<<3", prefetchMemory) + } +} + +func TestTranslateARM64SVEPredicateMemoryCompleteGo127Family(t *testing.T) { + source := arm64SVEPredicateMemoryCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicatememoryforms": {Name: "svepredicatememoryforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "load ", + "store ", + "@llvm.aarch64.sve.prf.nxv16i1", + "@llvm.aarch64.sve.prf.nxv8i1", + "@llvm.aarch64.sve.prf.nxv4i1", + "@llvm.aarch64.sve.prf.nxv2i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate memory lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-memory.ll", "arm64-sve-predicate-memory.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicateMemoryRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PLDR (-VL*257)(R0), P1", + "PSTR P1, (VL*256)(R0)", + "PLDR (VL*1)(R0), P1.B", + "PPRFB (-VL*33)(R0), P1, PLDL1KEEP", + "PPRFD (VL*32)(R0), P1, PLDL1KEEP", + "PPRFH (R8<<2)(RSP), P1, PLDL1KEEP", + "PPRFW (R8)(RSP), P1, PLDL1KEEP", + "PPRFD (R8<<3)(RSP), P8, PLDL1KEEP", + "PPRFB (VL*1)(R0), P1, PLIL1KEEP", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicatememory(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicatememory": {Name: "badsvepredicatememory", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE predicate memory forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_permute.go b/arm64_lower_sve_predicate_permute.go new file mode 100644 index 00000000..331d52e7 --- /dev/null +++ b/arm64_lower_sve_predicate_permute.go @@ -0,0 +1,101 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEPredicatePermuteSpec struct { + intrinsic string + inputs int + unpack bool +} + +var arm64SVEPredicatePermuteSpecs = map[Op]arm64SVEPredicatePermuteSpec{ + "PREV": {intrinsic: "rev", inputs: 1}, + "PTRN1": {intrinsic: "trn1", inputs: 2}, + "PTRN2": {intrinsic: "trn2", inputs: 2}, + "PUZP1": {intrinsic: "uzp1", inputs: 2}, + "PUZP2": {intrinsic: "uzp2", inputs: 2}, + "PZIP1": {intrinsic: "zip1", inputs: 2}, + "PZIP2": {intrinsic: "zip2", inputs: 2}, + "PPUNPKHI": {intrinsic: "punpkhi", inputs: 1, unpack: true}, + "PPUNPKLO": {intrinsic: "punpklo", inputs: 1, unpack: true}, +} + +func (c *arm64Ctx) lowerARM64SVEPredicatePermute(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEPredicatePermuteSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != spec.inputs+1 { + return true, false, fmt.Errorf("arm64 %s expects %d source predicate(s) and one destination: %q", op, spec.inputs, ins.Raw) + } + first, firstBits, firstOK := arm64ParseSVEPredicateElement(ins.Args[0]) + if !firstOK { + return true, false, fmt.Errorf("arm64 %s first source is not a Go 1.27 predicate arrangement: %q", op, ins.Raw) + } + if spec.unpack { + destination, destinationBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[1]) + if firstBits != 8 || !destinationOK || destinationBits != 16 { + return true, false, fmt.Errorf("arm64 %s only accepts Pn.B, Pd.H: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVEPredicateUnpack(spec, first, destination) + } + if spec.inputs == 1 { + destination, destinationBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[1]) + if !destinationOK || destinationBits != firstBits { + return true, false, fmt.Errorf("arm64 %s source and destination arrangements must match: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVEPredicateReverse(first, destination, firstBits) + } + + second, secondBits, secondOK := arm64ParseSVEPredicateElement(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[2]) + if !secondOK || !destinationOK || firstBits != secondBits || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s predicate arrangements must all match: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVEPredicatePermuteBinary(spec, first, second, destination, firstBits) +} + +func (c *arm64Ctx) lowerARM64SVEPredicateReverse(source, destination, elementBits int) error { + sourceValue, err := c.loadPReg(source) + if err != nil { + return err + } + result := c.newTmp() + if elementBits == 8 { + fmt.Fprintf(c.b, " %%%s = call @llvm.vector.reverse.nxv16i1( %s)\n", result, sourceValue) + } else { + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.rev.b%d( %s)\n", result, elementBits, sourceValue) + } + return c.storePReg(destination, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEPredicatePermuteBinary(spec arm64SVEPredicatePermuteSpec, plan9First, plan9Second, destination, elementBits int) error { + firstValue, err := c.loadPReg(plan9Second) + if err != nil { + return err + } + secondValue, err := c.loadPReg(plan9First) + if err != nil { + return err + } + intrinsic := spec.intrinsic + ".nxv16i1" + if elementBits != 8 { + intrinsic = fmt.Sprintf("%s.b%d", spec.intrinsic, elementBits) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.%s( %s, %s)\n", result, intrinsic, firstValue, secondValue) + return c.storePReg(destination, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEPredicateUnpack(spec arm64SVEPredicatePermuteSpec, source, destination int) error { + sourceValue, err := c.loadPReg(source) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.%s.nxv16i1( %s)\n", result, spec.intrinsic, sourceValue) + return c.storePRegElements(destination, 16, "%"+result) +} diff --git a/arm64_lower_sve_predicate_permute_test.go b/arm64_lower_sve_predicate_permute_test.go new file mode 100644 index 00000000..b5e037f5 --- /dev/null +++ b/arm64_lower_sve_predicate_permute_test.go @@ -0,0 +1,84 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEPredicatePermuteCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svepredicatepermuteforms(SB),$0-0\n") + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\tPREV P15.%s, P14.%s\n", width, width) + for _, op := range []string{"PTRN1", "PTRN2", "PUZP1", "PUZP2", "PZIP1", "PZIP2"} { + fmt.Fprintf(&source, "\t%s P13.%s, P12.%s, P11.%s\n", op, width, width, width) + } + } + source.WriteString("\tPPUNPKHI P10.B, P9.H\n") + source.WriteString("\tPPUNPKLO P8.B, P7.H\n") + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEPredicatePermuteCompleteGo127Family(t *testing.T) { + source := arm64SVEPredicatePermuteCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicatepermuteforms": {Name: "svepredicatepermuteforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.vector.reverse.nxv16i1", + "@llvm.aarch64.sve.rev.b16", + "@llvm.aarch64.sve.trn1.nxv16i1", + "@llvm.aarch64.sve.trn2.b64", + "@llvm.aarch64.sve.uzp1.b32", + "@llvm.aarch64.sve.zip2.b16", + "@llvm.aarch64.sve.punpkhi.nxv16i1", + "@llvm.aarch64.sve.punpklo.nxv16i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate permute lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-permute.ll", "arm64-sve-predicate-permute.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicatePermuteRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PREV P1.B, P2.H", + "PTRN1 P1.B, P2.H, P3.B", + "PUZP2 P1.B, P2.B, P16.B", + "PZIP1 P1.B, P2.B", + "PPUNPKHI P1.H, P2.H", + "PPUNPKLO P1.B, P2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicatepermute(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicatepermute": {Name: "badsvepredicatepermute", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE predicate permute forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_position.go b/arm64_lower_sve_predicate_position.go new file mode 100644 index 00000000..2acb9c47 --- /dev/null +++ b/arm64_lower_sve_predicate_position.go @@ -0,0 +1,38 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEPredicatePositionIntrinsics = map[Op]string{ + "PFIRSTP": "firstp", + "PLASTP": "lastp", +} + +func (c *arm64Ctx) lowerARM64SVEPredicatePosition(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEPredicatePositionIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Pn.T, Pg, Xd: %q", op, ins.Raw) + } + tested, elementBits, testedOK := arm64ParseSVEPredicateElement(ins.Args[0]) + governing, governingOK := arm64ParseSVEPredicateBare(ins.Args[1], 15) + if !testedOK || !governingOK || ins.Args[2].Kind != OpReg || !isARM64GeneralOrZeroReg(ins.Args[2].Reg) { + return true, false, fmt.Errorf("arm64 %s operands do not match its Go 1.27 predicate-position form: %q", op, ins.Raw) + } + governingValue, predicateType, err := c.loadPRegElements(governing, elementBits) + if err != nil { + return true, false, err + } + testedValue, _, err := c.loadPRegElements(tested, elementBits) + if err != nil { + return true, false, err + } + lanes := 128 / elementBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.aarch64.sve.%s.nxv%di1(%s %s, %s %s)\n", result, intrinsic, lanes, predicateType, governingValue, predicateType, testedValue) + return true, false, c.storeReg(ins.Args[2].Reg, "%"+result) +} diff --git a/arm64_lower_sve_predicate_position_test.go b/arm64_lower_sve_predicate_position_test.go new file mode 100644 index 00000000..a71c0ef7 --- /dev/null +++ b/arm64_lower_sve_predicate_position_test.go @@ -0,0 +1,76 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEPredicatePositionCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svepredicatepositionforms(SB),$0-0\n") + for index, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\tPFIRSTP P%d.%s, P%d, R%d\n", 15-index, width, 11-index, index) + fmt.Fprintf(&source, "\tPLASTP P%d.%s, P%d, R%d\n", 7-index, width, 3-index, 4+index) + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEPredicatePositionCompleteGo127Family(t *testing.T) { + source := arm64SVEPredicatePositionCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicatepositionforms": {Name: "svepredicatepositionforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2p2"`, + "@llvm.aarch64.sve.firstp.nxv16i1", + "@llvm.aarch64.sve.firstp.nxv8i1", + "@llvm.aarch64.sve.lastp.nxv4i1", + "@llvm.aarch64.sve.lastp.nxv2i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate position lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-position.ll", "arm64-sve-predicate-position.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicatePositionRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PFIRSTP P1.Q, P2, R3", + "PFIRSTP P1.B, P2.Z, R3", + "PFIRSTP P16.B, P2, R3", + "PLASTP P1.B, P16, R3", + "PLASTP P1.B, P2, R31", + "PLASTP P1.B, P2", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicateposition(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicateposition": {Name: "badsvepredicateposition", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE predicate position forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_select.go b/arm64_lower_sve_predicate_select.go new file mode 100644 index 00000000..19b404c1 --- /dev/null +++ b/arm64_lower_sve_predicate_select.go @@ -0,0 +1,41 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEPredicateSelectOps = map[Op]struct{}{ + "PSEL": {}, +} + +func (c *arm64Ctx) lowerARM64SVEPredicateSelect(op Op, ins Instr) (ok bool, terminated bool, err error) { + if _, ok := arm64SVEPredicateSelectOps[op]; !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 PSEL expects Pm.B, Pn.B, Pg, Pd.B: %q", ins.Raw) + } + first, firstBits, firstOK := arm64ParseSVEPredicateElement(ins.Args[0]) + second, secondBits, secondOK := arm64ParseSVEPredicateElement(ins.Args[1]) + governing, governingOK := arm64ParseSVEPredicateBare(ins.Args[2], 15) + destination, destinationBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[3]) + if !firstOK || !secondOK || !governingOK || !destinationOK || firstBits != 8 || secondBits != 8 || destinationBits != 8 { + return true, false, fmt.Errorf("arm64 PSEL only accepts the Go 1.27 Pm.B, Pn.B, Pg, Pd.B form: %q", ins.Raw) + } + firstValue, err := c.loadPReg(first) + if err != nil { + return true, false, err + } + secondValue, err := c.loadPReg(second) + if err != nil { + return true, false, err + } + governingValue, err := c.loadPReg(governing) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s, %s, %s\n", result, governingValue, secondValue, firstValue) + return true, false, c.storePReg(destination, "%"+result) +} diff --git a/arm64_lower_sve_predicate_select_test.go b/arm64_lower_sve_predicate_select_test.go new file mode 100644 index 00000000..d756099a --- /dev/null +++ b/arm64_lower_sve_predicate_select_test.go @@ -0,0 +1,57 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEPredicateSelectCompleteGo127Family(t *testing.T) { + const source = "TEXT svepredicateselectforms(SB),$0-0\n\tPSEL P15.B, P14.B, P13, P12.B\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicateselectforms": {Name: "svepredicateselectforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve"`, "select "} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate select lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-select.ll", "arm64-sve-predicate-select.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicateSelectRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PSEL P1.H, P2.H, P3, P4.H", + "PSEL P1.B, P2.B, P3.Z, P4.B", + "PSEL P1.B, P2.B, P16, P4.B", + "PSEL P1.B, P2.B, P3, P4.H", + "PSEL P1.B, P2.B, P3", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicateselect(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicateselect": {Name: "badsvepredicateselect", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE predicate select forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_state.go b/arm64_lower_sve_predicate_state.go new file mode 100644 index 00000000..1d3b65c9 --- /dev/null +++ b/arm64_lower_sve_predicate_state.go @@ -0,0 +1,130 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEPredicateStateKind uint8 + +const ( + arm64SVEPredicateFalse arm64SVEPredicateStateKind = iota + arm64SVEPredicateTest + arm64SVEPredicateReadFFR + arm64SVEPredicateReadFFRFlags + arm64SVEPredicateWriteFFR + arm64SVEPredicateSetFFR +) + +var arm64SVEPredicateStateSpecs = map[Op]arm64SVEPredicateStateKind{ + "PPFALSE": arm64SVEPredicateFalse, + "PPTEST": arm64SVEPredicateTest, + "PRDFFR": arm64SVEPredicateReadFFR, + "PRDFFRS": arm64SVEPredicateReadFFRFlags, + "PWRFFR": arm64SVEPredicateWriteFFR, + "SETFFR": arm64SVEPredicateSetFFR, +} + +func (c *arm64Ctx) lowerARM64SVEPredicateState(op Op, ins Instr) (ok bool, terminated bool, err error) { + kind, ok := arm64SVEPredicateStateSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + switch kind { + case arm64SVEPredicateFalse: + if len(ins.Args) != 1 { + return true, false, fmt.Errorf("arm64 PPFALSE expects Pd.B: %q", ins.Raw) + } + destination, elementBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[0]) + if !destinationOK || elementBits != 8 { + return true, false, fmt.Errorf("arm64 PPFALSE only accepts P0..P15.B: %q", ins.Raw) + } + return true, false, c.storePReg(destination, "zeroinitializer") + case arm64SVEPredicateTest: + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 PPTEST expects Pn.B, Pg: %q", ins.Raw) + } + tested, elementBits, testedOK := arm64ParseSVEPredicateElement(ins.Args[0]) + governing, governingOK := arm64ParseSVEPredicateBare(ins.Args[1], 15) + if !testedOK || elementBits != 8 || !governingOK { + return true, false, fmt.Errorf("arm64 PPTEST only accepts P0..P15.B, P0..P15: %q", ins.Raw) + } + testedValue, predicateType, err := c.loadPRegElements(tested, 8) + if err != nil { + return true, false, err + } + governingValue, _, err := c.loadPRegElements(governing, 8) + if err != nil { + return true, false, err + } + c.setSVEPredicateFlags(governingValue, testedValue, predicateType, 16) + return true, false, nil + case arm64SVEPredicateReadFFR, arm64SVEPredicateReadFFRFlags: + return c.lowerARM64SVEReadFFR(kind, ins) + case arm64SVEPredicateWriteFFR: + if len(ins.Args) != 1 { + return true, false, fmt.Errorf("arm64 PWRFFR expects Pn.B: %q", ins.Raw) + } + source, elementBits, sourceOK := arm64ParseSVEPredicateElement(ins.Args[0]) + if !sourceOK || elementBits != 8 { + return true, false, fmt.Errorf("arm64 PWRFFR only accepts P0..P15.B: %q", ins.Raw) + } + value, err := c.loadPReg(source) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.wrffr( %s)\n", value) + return true, false, nil + case arm64SVEPredicateSetFFR: + if len(ins.Args) != 0 { + return true, false, fmt.Errorf("arm64 SETFFR does not accept operands: %q", ins.Raw) + } + fmt.Fprintln(c.b, " call void @llvm.aarch64.sve.setffr()") + return true, false, nil + default: + return true, false, fmt.Errorf("unsupported ARM64 SVE predicate state kind %d", kind) + } +} + +func (c *arm64Ctx) lowerARM64SVEReadFFR(kind arm64SVEPredicateStateKind, ins Instr) (ok bool, terminated bool, err error) { + var destination int + var value string + if len(ins.Args) == 1 && kind == arm64SVEPredicateReadFFR { + var elementBits int + var destinationOK bool + destination, elementBits, destinationOK = arm64ParseSVEPredicateElement(ins.Args[0]) + if !destinationOK || elementBits != 8 { + return true, false, fmt.Errorf("arm64 PRDFFR unpredicated form expects Pd.B: %q", ins.Raw) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.rdffr()\n", result) + value = "%" + result + } else if len(ins.Args) == 2 { + governing, governingOK := arm64ParseSVEPredicateMode(ins.Args[0], "Z", 15) + var elementBits int + var destinationOK bool + destination, elementBits, destinationOK = arm64ParseSVEPredicateElement(ins.Args[1]) + if !governingOK || !destinationOK || elementBits != 8 { + return true, false, fmt.Errorf("arm64 %s predicated form expects Pg.Z, Pd.B: %q", ins.Op, ins.Raw) + } + governingValue, err := c.loadPReg(governing) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.rdffr.z( %s)\n", result, governingValue) + value = "%" + result + if kind == arm64SVEPredicateReadFFRFlags { + c.setSVEPredicateFlags(governingValue, value, "", 16) + } + } else { + return true, false, fmt.Errorf("arm64 %s expects its Go 1.27 FFR read form: %q", ins.Op, ins.Raw) + } + if err := c.storePReg(destination, value); err != nil { + return true, false, err + } + return true, false, nil +} diff --git a/arm64_lower_sve_predicate_state_test.go b/arm64_lower_sve_predicate_state_test.go new file mode 100644 index 00000000..a9a57843 --- /dev/null +++ b/arm64_lower_sve_predicate_state_test.go @@ -0,0 +1,73 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEPredicateStateCompleteGo127Family(t *testing.T) { + const source = "TEXT svepredicatestateforms(SB),$0-0\n\tPPFALSE P15.B\n\tPPTEST P14.B, P13\n\tPRDFFR P14.Z, P0.B\n\tPRDFFR P13.B\n\tPRDFFRS P12.Z, P1.B\n\tPWRFFR P11.B\n\tSETFFR\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicatestateforms": {Name: "svepredicatestateforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "store zeroinitializer", + "@llvm.aarch64.sve.ptest.any.nxv16i1", + "@llvm.aarch64.sve.ptest.first.nxv16i1", + "@llvm.aarch64.sve.ptest.last.nxv16i1", + "@llvm.aarch64.sve.rdffr()", + "@llvm.aarch64.sve.rdffr.z(", + "@llvm.aarch64.sve.wrffr(", + "@llvm.aarch64.sve.setffr()", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate state lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-state.ll", "arm64-sve-predicate-state.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicateStateRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PPFALSE P1.H", + "PPFALSE P16.B", + "PPTEST P1.H, P2", + "PPTEST P1.B, P2.Z", + "PPTEST P1.B, P16", + "PPTEST P1.B", + "PRDFFR P1.H", + "PRDFFR P1.M, P2.B", + "PRDFFRS P1.B", + "PWRFFR P1.H", + "SETFFR R1", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicatestate(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicatestate": {Name: "badsvepredicatestate", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE predicate state forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_predicate_while.go b/arm64_lower_sve_predicate_while.go new file mode 100644 index 00000000..51deaa65 --- /dev/null +++ b/arm64_lower_sve_predicate_while.go @@ -0,0 +1,237 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEPredicateWhileSpec struct { + condition string + word bool + pointer bool +} + +var arm64SVEPredicateWhileSpecs = map[Op]arm64SVEPredicateWhileSpec{ + "PWHILEGE": {condition: "whilege"}, + "PWHILEGT": {condition: "whilegt"}, + "PWHILEHI": {condition: "whilehi"}, + "PWHILEHS": {condition: "whilehs"}, + "PWHILELE": {condition: "whilele"}, + "PWHILELO": {condition: "whilelo"}, + "PWHILELS": {condition: "whilels"}, + "PWHILELT": {condition: "whilelt"}, + "PWHILEGEW": {condition: "whilege", word: true}, + "PWHILEGTW": {condition: "whilegt", word: true}, + "PWHILEHIW": {condition: "whilehi", word: true}, + "PWHILEHSW": {condition: "whilehs", word: true}, + "PWHILELEW": {condition: "whilele", word: true}, + "PWHILELOW": {condition: "whilelo", word: true}, + "PWHILELSW": {condition: "whilels", word: true}, + "PWHILELTW": {condition: "whilelt", word: true}, + "PWHILERW": {condition: "whilerw", pointer: true}, + "PWHILEWR": {condition: "whilewr", pointer: true}, +} + +func arm64SVEPredicateWhileNeedsSVE2P1(ins Instr) bool { + return len(ins.Args) >= 3 && (ins.Args[len(ins.Args)-1].Kind == OpRegList || ins.Args[0].Kind == OpIdent) +} + +func (c *arm64Ctx) lowerARM64SVEPredicateWhile(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEPredicateWhileSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + if spec.pointer { + return c.lowerARM64SVEPredicateWhilePointer(spec, ins) + } + if spec.word { + return c.lowerARM64SVEPredicateWhileSingle(spec, ins) + } + if len(ins.Args) == 4 && ins.Args[0].Kind == OpIdent { + return c.lowerARM64SVEPredicateWhileCounter(spec, ins) + } + if len(ins.Args) == 3 && ins.Args[2].Kind == OpRegList { + return c.lowerARM64SVEPredicateWhilePair(spec, ins) + } + return c.lowerARM64SVEPredicateWhileSingle(spec, ins) +} + +func arm64SVEWhileScalarRegister(operand Operand, allowZero bool) (Reg, bool) { + if operand.Kind != OpReg || !isARM64GeneralOrZeroReg(operand.Reg) { + return "", false + } + if !allowZero && operand.Reg == ZR { + return "", false + } + return operand.Reg, true +} + +func (c *arm64Ctx) loadARM64SVEWhileScalars(firstOperand, secondOperand Operand, word, allowZero bool) (first, second, scalarType string, err error) { + plan9First, firstOK := arm64SVEWhileScalarRegister(firstOperand, allowZero) + plan9Second, secondOK := arm64SVEWhileScalarRegister(secondOperand, allowZero) + if !firstOK || !secondOK { + return "", "", "", fmt.Errorf("predicate while operands must be valid general registers") + } + first64, err := c.loadReg(plan9Second) + if err != nil { + return "", "", "", err + } + second64, err := c.loadReg(plan9First) + if err != nil { + return "", "", "", err + } + if !word { + return first64, second64, "i64", nil + } + firstTmp := c.newTmp() + secondTmp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", firstTmp, first64) + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", secondTmp, second64) + return "%" + firstTmp, "%" + secondTmp, "i32", nil +} + +func (c *arm64Ctx) lowerARM64SVEPredicateWhileSingle(spec arm64SVEPredicateWhileSpec, ins Instr) (ok bool, terminated bool, err error) { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 predicate while expects Rm, Rn, Pd.T: %q", ins.Raw) + } + destination, elementBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[2]) + if !destinationOK { + return true, false, fmt.Errorf("arm64 predicate while destination must be P0..P15.B/H/S/D: %q", ins.Raw) + } + first, second, scalarType, err := c.loadARM64SVEWhileScalars(ins.Args[0], ins.Args[1], spec.word, true) + if err != nil { + return true, false, fmt.Errorf("arm64 predicate while scalar form: %w: %q", err, ins.Raw) + } + lanes := 128 / elementBits + predicateType := fmt.Sprintf("", lanes) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di1.%s(%s %s, %s %s)\n", result, predicateType, spec.condition, lanes, scalarType, scalarType, first, scalarType, second) + if err := c.storePRegElements(destination, elementBits, "%"+result); err != nil { + return true, false, err + } + governing, _, err := c.allTruePRegElements(elementBits) + if err != nil { + return true, false, err + } + c.setSVEPredicateFlags(governing, "%"+result, predicateType, lanes) + return true, false, nil +} + +func (c *arm64Ctx) lowerARM64SVEPredicateWhilePair(spec arm64SVEPredicateWhileSpec, ins Instr) (ok bool, terminated bool, err error) { + if len(ins.Args) != 3 || ins.Args[2].Kind != OpRegList || len(ins.Args[2].RegList) != 2 { + return true, false, fmt.Errorf("arm64 predicate while pair form expects Xm, Xn, [Pd1.T, Pd2.T]: %q", ins.Raw) + } + firstDestination, firstBits, firstOK := arm64ParseSVEPredicateElement(Operand{Kind: OpReg, Reg: ins.Args[2].RegList[0]}) + secondDestination, secondBits, secondOK := arm64ParseSVEPredicateElement(Operand{Kind: OpReg, Reg: ins.Args[2].RegList[1]}) + if !firstOK || !secondOK || firstBits != secondBits || firstDestination%2 != 0 || secondDestination != firstDestination+1 { + return true, false, fmt.Errorf("arm64 predicate while pair requires an even/odd consecutive predicate pair with matching arrangements: %q", ins.Raw) + } + first, second, _, err := c.loadARM64SVEWhileScalars(ins.Args[0], ins.Args[1], false, false) + if err != nil { + return true, false, fmt.Errorf("arm64 predicate while pair scalar form: %w: %q", err, ins.Raw) + } + lanes := 128 / firstBits + predicateType := fmt.Sprintf("", lanes) + aggregateType := fmt.Sprintf("{ %s, %s }", predicateType, predicateType) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.x2.nxv%di1(i64 %s, i64 %s)\n", result, aggregateType, spec.condition, lanes, first, second) + firstValue := c.newTmp() + secondValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 0\n", firstValue, aggregateType, result) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, 1\n", secondValue, aggregateType, result) + if err := c.storePRegElements(firstDestination, firstBits, "%"+firstValue); err != nil { + return true, false, err + } + if err := c.storePRegElements(secondDestination, secondBits, "%"+secondValue); err != nil { + return true, false, err + } + governing, _, err := c.allTruePRegElements(firstBits) + if err != nil { + return true, false, err + } + c.setSVEPredicateSequenceFlags(governing, []string{"%" + firstValue, "%" + secondValue}, predicateType, lanes) + return true, false, nil +} + +func arm64SVEWhileMultiplier(operand Operand) int { + if operand.Kind != OpIdent { + return 0 + } + switch strings.ToUpper(operand.Ident) { + case "VLX2": + return 2 + case "VLX4": + return 4 + default: + return 0 + } +} + +func (c *arm64Ctx) lowerARM64SVEPredicateWhileCounter(spec arm64SVEPredicateWhileSpec, ins Instr) (ok bool, terminated bool, err error) { + if len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 predicate while counter form expects VLx2|VLx4, Xm, Xn, PNd.T: %q", ins.Raw) + } + multiplier := arm64SVEWhileMultiplier(ins.Args[0]) + destination, elementBits, destinationOK := arm64ParseSVEPredicateCounterElement(ins.Args[3]) + if multiplier == 0 || !destinationOK || destination < 8 { + return true, false, fmt.Errorf("arm64 predicate while counter requires VLx2|VLx4 and PN8..PN15.B/H/S/D: %q", ins.Raw) + } + first, second, _, err := c.loadARM64SVEWhileScalars(ins.Args[1], ins.Args[2], false, false) + if err != nil { + return true, false, fmt.Errorf("arm64 predicate while counter scalar form: %w: %q", err, ins.Raw) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call target(\"aarch64.svcount\") @llvm.aarch64.sve.%s.c%d(i64 %s, i64 %s, i32 %d)\n", result, spec.condition, elementBits, first, second, multiplier) + if err := c.storePNReg(destination, "%"+result); err != nil { + return true, false, err + } + lanes := 128 / elementBits + predicateType := fmt.Sprintf("", lanes) + pieces := make([]string, 0, multiplier) + for lane := 0; lane < multiplier; lane++ { + piece := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.pext.nxv%di1(target(\"aarch64.svcount\") %%%s, i32 %d)\n", piece, predicateType, lanes, result, lane) + pieces = append(pieces, "%"+piece) + } + governing, _, err := c.allTruePRegElements(elementBits) + if err != nil { + return true, false, err + } + c.setSVEPredicateSequenceFlags(governing, pieces, predicateType, lanes) + return true, false, nil +} + +func (c *arm64Ctx) lowerARM64SVEPredicateWhilePointer(spec arm64SVEPredicateWhileSpec, ins Instr) (ok bool, terminated bool, err error) { + if len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Xm, Xn, Pd.T: %q", ins.Op, ins.Raw) + } + destination, elementBits, destinationOK := arm64ParseSVEPredicateElement(ins.Args[2]) + if !destinationOK { + return true, false, fmt.Errorf("arm64 %s destination must be P0..P15.B/H/S/D: %q", ins.Op, ins.Raw) + } + first, second, _, err := c.loadARM64SVEWhileScalars(ins.Args[0], ins.Args[1], false, false) + if err != nil { + return true, false, fmt.Errorf("arm64 %s scalar form: %w: %q", ins.Op, err, ins.Raw) + } + firstPointer := c.newTmp() + secondPointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", firstPointer, first) + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", secondPointer, second) + lanes := 128 / elementBits + predicateType := fmt.Sprintf("", lanes) + letter := strings.ToLower(map[int]string{8: "B", 16: "H", 32: "S", 64: "D"}[elementBits]) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.%s.nxv%di1.p0(ptr %%%s, ptr %%%s)\n", result, predicateType, spec.condition, letter, lanes, firstPointer, secondPointer) + if err := c.storePRegElements(destination, elementBits, "%"+result); err != nil { + return true, false, err + } + governing, _, err := c.allTruePRegElements(elementBits) + if err != nil { + return true, false, err + } + c.setSVEPredicateFlags(governing, "%"+result, predicateType, lanes) + return true, false, nil +} diff --git a/arm64_lower_sve_predicate_while_test.go b/arm64_lower_sve_predicate_while_test.go new file mode 100644 index 00000000..5291b735 --- /dev/null +++ b/arm64_lower_sve_predicate_while_test.go @@ -0,0 +1,94 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +var arm64SVEPredicateWhileConditions = []string{"GE", "GT", "HI", "HS", "LE", "LO", "LS", "LT"} + +func arm64SVEPredicateWhileCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svepredicatewhileforms(SB),$0-0\n") + for conditionIndex, condition := range arm64SVEPredicateWhileConditions { + for widthIndex, width := range []string{"B", "H", "S", "D"} { + destination := (conditionIndex + widthIndex) % 15 + pairDestination := 2 * ((conditionIndex + widthIndex) % 8) + fmt.Fprintf(&source, "\tPWHILE%s R1, R2, P%d.%s\n", condition, destination, width) + fmt.Fprintf(&source, "\tPWHILE%s R3, R4, [P%d.%s, P%d.%s]\n", condition, pairDestination, width, pairDestination+1, width) + fmt.Fprintf(&source, "\tPWHILE%s VLx2, R5, R6, PN%d.%s\n", condition, 8+(conditionIndex+widthIndex)%8, width) + fmt.Fprintf(&source, "\tPWHILE%s VLx4, R7, R8, PN%d.%s\n", condition, 8+(conditionIndex+widthIndex+1)%8, width) + fmt.Fprintf(&source, "\tPWHILE%sW R9, R10, P%d.%s\n", condition, destination, width) + } + } + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\tPWHILERW R11, R12, P13.%s\n", width) + fmt.Fprintf(&source, "\tPWHILEWR R13, R14, P15.%s\n", width) + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEPredicateWhileCompleteGo127Family(t *testing.T) { + source := arm64SVEPredicateWhileCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svepredicatewhileforms": {Name: "svepredicatewhileforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2,+sve2p1"`, + "@llvm.aarch64.sve.whilege.nxv16i1.i64", + "@llvm.aarch64.sve.whilelt.nxv2i1.i32", + "@llvm.aarch64.sve.whilehi.x2.nxv4i1", + "@llvm.aarch64.sve.whilels.c64", + "@llvm.aarch64.sve.whilerw.b.nxv16i1.p0", + "@llvm.aarch64.sve.whilewr.d.nxv2i1.p0", + "@llvm.aarch64.sve.ptest.any.nxv16i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE predicate while lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-predicate-while.ll", "arm64-sve-predicate-while.o", ll) + }) + } +} + +func TestTranslateARM64SVEPredicateWhileRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "PWHILELT R1, R2, P3.Q", + "PWHILEGE R1, R2, [P3.B, P4.H]", + "PWHILEGE R1, R2, [P3.B, P4.B]", + "PWHILEHI R1, R2, [P3.B, P5.B]", + "PWHILELO VLx3, R1, R2, PN8.B", + "PWHILELS VLx2, R1, R2, PN7.B", + "PWHILELTW R1, R2", + "PWHILERW R1, R2, P3.Q", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvepredicatewhile(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvepredicatewhile": {Name: "badsvepredicatewhile", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE predicate while forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_q_permute_test.go b/arm64_lower_sve_q_permute_test.go new file mode 100644 index 00000000..c7883ba9 --- /dev/null +++ b/arm64_lower_sve_q_permute_test.go @@ -0,0 +1,62 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEQPermuteCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT sveqpermuteforms(SB),$0-0\n") + for _, op := range []string{"ZZIPQ1", "ZZIPQ2", "ZUZPQ1", "ZUZPQ2"} { + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, Z3.%s\n", op, width, width, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveqpermuteforms": {Name: "sveqpermuteforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2p1"`, "@llvm.aarch64.sve.zipq1.nxv16i8", "@llvm.aarch64.sve.uzpq2.nxv2i64"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE Q permute lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-q-permute.ll", "arm64-sve-q-permute.o", ll) + }) + } +} + +func TestTranslateARM64SVEQPermuteRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZZIPQ1 Z1.B, Z2.H, Z3.B", + "ZZIPQ2 Z1.Q, Z2.Q, Z3.Q", + "ZUZPQ1 Z1.S, Z2.S", + "ZUZPQ2.Z Z1.D, Z2.D, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveqpermute(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveqpermute": {Name: "badsveqpermute", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE Q permute forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_replicate_memory.go b/arm64_lower_sve_replicate_memory.go new file mode 100644 index 00000000..733ecf49 --- /dev/null +++ b/arm64_lower_sve_replicate_memory.go @@ -0,0 +1,143 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEReplicateMemorySpec struct { + memoryBits int + signed bool + blockBytes int +} + +// arm64SVEReplicateMemorySpecs covers all 32 Go 1.27 replicate-load encoder +// forms: scalar LD1R, sign-extending LD1RS, and block LD1RO/LD1RQ. +var arm64SVEReplicateMemorySpecs = map[Op]arm64SVEReplicateMemorySpec{ + "ZLD1RB": {memoryBits: 8}, + "ZLD1RH": {memoryBits: 16}, + "ZLD1RW": {memoryBits: 32}, + "ZLD1RD": {memoryBits: 64}, + "ZLD1RSB": {memoryBits: 8, signed: true}, + "ZLD1RSH": {memoryBits: 16, signed: true}, + "ZLD1RSW": {memoryBits: 32, signed: true}, + "ZLD1ROB": {memoryBits: 8, blockBytes: 32}, + "ZLD1ROH": {memoryBits: 16, blockBytes: 32}, + "ZLD1ROW": {memoryBits: 32, blockBytes: 32}, + "ZLD1ROD": {memoryBits: 64, blockBytes: 32}, + "ZLD1RQB": {memoryBits: 8, blockBytes: 16}, + "ZLD1RQH": {memoryBits: 16, blockBytes: 16}, + "ZLD1RQW": {memoryBits: 32, blockBytes: 16}, + "ZLD1RQD": {memoryBits: 64, blockBytes: 16}, +} + +func (c *arm64Ctx) lowerARM64SVEReplicateMemory(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEReplicateMemorySpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[0].Kind != OpMem || ins.Args[2].Kind != OpRegList { + return true, false, fmt.Errorf("arm64 %s expects memory, predicate, vector-list operands: %q", op, ins.Raw) + } + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + vectors, elementBits, vectorsOK := arm64ParseSVEConsecutiveVectorList(ins.Args[2]) + widthOK := elementBits >= spec.memoryBits && (!spec.signed || elementBits > spec.memoryBits) + if spec.blockBytes != 0 { + widthOK = elementBits == spec.memoryBits + } + if !predicateOK || !vectorsOK || len(vectors) != 1 || !widthOK { + return true, false, fmt.Errorf("arm64 %s has predicate or destination widths outside its Go 1.27 table: %q", op, ins.Raw) + } + if spec.blockBytes != 0 { + return c.lowerARM64SVEReplicateBlockLoad(op, spec, ins.Args[0].Mem, predicate, vectors[0], elementBits, ins) + } + return c.lowerARM64SVEReplicateScalarLoad(op, spec, ins.Args[0].Mem, predicate, vectors[0], elementBits, ins) +} + +func (c *arm64Ctx) lowerARM64SVEReplicateScalarLoad(op Op, spec arm64SVEReplicateMemorySpec, memory MemRef, predicate, destination, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + memoryBytes := int64(spec.memoryBits / 8) + address, err := c.arm64SVEScalarByteOffsetAddress(memory, 0, 63*memoryBytes, memoryBytes) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i%d, ptr %%%s\n", loaded, spec.memoryBits, pointer) + scalar := "%" + loaded + if spec.memoryBits < elementBits { + extended := c.newTmp() + extension := "zext" + if spec.signed { + extension = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s i%d %s to i%d\n", extended, extension, spec.memoryBits, scalar, elementBits) + scalar = "%" + extended + } + vectorType, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s poison, i%d %s, i64 0\n", inserted, vectorType, elementBits, scalar) + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector %s %%%s, %s poison, zeroinitializer\n", splat, vectorType, inserted, vectorType, lanes) + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %%%s, %s zeroinitializer\n", result, predicateType, predicateValue, vectorType, splat, vectorType) + return true, false, c.storeZRegElements(destination, elementBits, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEReplicateBlockLoad(op Op, spec arm64SVEReplicateMemorySpec, memory MemRef, predicate, destination, elementBits int, ins Instr) (ok bool, terminated bool, err error) { + var address string + var addressErr error + if memory.Index != "" { + address, addressErr = c.arm64SVERegisterOffsetAddress(memory, int64(spec.memoryBits/8)) + } else { + address, addressErr = c.arm64SVEScalarByteOffsetAddress(memory, -8*int64(spec.blockBytes), 7*int64(spec.blockBytes), int64(spec.blockBytes)) + } + if addressErr != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, addressErr, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + vectorType, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + kind := "rq" + if spec.blockBytes == 32 { + kind = "ro" + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ld1%s.nxv%di%d(%s %s, ptr %%%s)\n", + result, vectorType, kind, lanes, elementBits, predicateType, predicateValue, pointer) + return true, false, c.storeZRegElements(destination, elementBits, "%"+result) +} + +func (c *arm64Ctx) arm64SVEScalarByteOffsetAddress(memory MemRef, minimum, maximum, alignment int64) (string, error) { + if memory.Sym != "" || memory.Segment != "" || memory.Index != "" || memory.IndexExt != "" || memory.OffRaw != "" || memory.Off < minimum || memory.Off > maximum || memory.Off%alignment != 0 { + return "", fmt.Errorf("scalar byte offset must be aligned to %d and in [%d,%d]", alignment, minimum, maximum) + } + baseReg, ok := arm64SVEPhysicalMemoryBase(memory.Base) + if !ok { + return "", fmt.Errorf("address base must be R0..R30, RSP, or ZR") + } + base, err := c.loadReg(baseReg) + if err != nil { + return "", err + } + if memory.Off == 0 { + return base, nil + } + address := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %d\n", address, base, memory.Off) + return "%" + address, nil +} diff --git a/arm64_lower_sve_replicate_memory_test.go b/arm64_lower_sve_replicate_memory_test.go new file mode 100644 index 00000000..b404ee78 --- /dev/null +++ b/arm64_lower_sve_replicate_memory_test.go @@ -0,0 +1,144 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEReplicateMemoryCompleteGo127Forms() string { + var source strings.Builder + source.WriteString("TEXT svereplicatememoryforms(SB),$0-0\n") + for _, spec := range []struct { + op string + arrangements []string + maxOffset int + }{ + {op: "ZLD1RB", arrangements: []string{"B", "H", "S", "D"}, maxOffset: 63}, + {op: "ZLD1RH", arrangements: []string{"H", "S", "D"}, maxOffset: 126}, + {op: "ZLD1RW", arrangements: []string{"S", "D"}, maxOffset: 252}, + {op: "ZLD1RD", arrangements: []string{"D"}, maxOffset: 504}, + {op: "ZLD1RSB", arrangements: []string{"H", "S", "D"}, maxOffset: 63}, + {op: "ZLD1RSH", arrangements: []string{"S", "D"}, maxOffset: 126}, + {op: "ZLD1RSW", arrangements: []string{"D"}, maxOffset: 252}, + } { + for i, arrangement := range spec.arrangements { + offset := 0 + if i == len(spec.arrangements)-1 { + offset = spec.maxOffset + } + fmt.Fprintf(&source, "\t%s %d(R14), P4.Z, [Z13.%s]\n", spec.op, offset, arrangement) + } + } + for _, kind := range []string{"O", "Q"} { + blockBytes := 32 + if kind == "Q" { + blockBytes = 16 + } + for _, width := range []struct { + name string + arrangement string + shift int + }{ + {name: "B", arrangement: "B"}, + {name: "H", arrangement: "H", shift: 1}, + {name: "W", arrangement: "S", shift: 2}, + {name: "D", arrangement: "D", shift: 3}, + } { + op := "ZLD1R" + kind + width.name + index := "R6" + if width.shift != 0 { + index = fmt.Sprintf("R6<<%d", width.shift) + } + fmt.Fprintf(&source, "\t%s (%s)(R14), P4.Z, [Z13.%s]\n", op, index, width.arrangement) + fmt.Fprintf(&source, "\t%s %d(R14), P4.Z, [Z13.%s]\n", op, -8*blockBytes, width.arrangement) + } + } + // Cover both ends of each signed immediate range. + source.WriteString("\tZLD1ROB 224(R14), P4.Z, [Z13.B]\n") + source.WriteString("\tZLD1RQB 112(R14), P4.Z, [Z13.B]\n") + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEReplicateMemoryCompleteGo127Family(t *testing.T) { + source := arm64SVEReplicateMemoryCompleteGo127Forms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svereplicatememoryforms": {Name: "svereplicatememoryforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+f64mm,+sve"`, + "@llvm.aarch64.sve.ld1ro.nxv16i8", + "@llvm.aarch64.sve.ld1ro.nxv8i16", + "@llvm.aarch64.sve.ld1ro.nxv4i32", + "@llvm.aarch64.sve.ld1ro.nxv2i64", + "@llvm.aarch64.sve.ld1rq.nxv16i8", + "@llvm.aarch64.sve.ld1rq.nxv8i16", + "@llvm.aarch64.sve.ld1rq.nxv4i32", + "@llvm.aarch64.sve.ld1rq.nxv2i64", + "shufflevector = 0 && index <= 31 +} + +func arm64SVERevdNeedsSVE2P2(ins Instr) bool { + return len(ins.Args) == 3 && func() bool { + _, ok := arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + return ok + }() +} + +func (c *arm64Ctx) lowerARM64SVERevd(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZREVD" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 ZREVD expects Zn.Q, Pg/M|Z, Zd.Q without a suffix: %q", ins.Raw) + } + source, sourceOK := arm64ParseSVEZQReg(ins.Args[0]) + destination, destinationOK := arm64ParseSVEZQReg(ins.Args[2]) + predicate, mergeOK := arm64ParseSVEPredicateMode(ins.Args[1], "M", 7) + zeroing := false + if !mergeOK { + predicate, zeroing = arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + } + if !sourceOK || !destinationOK || !mergeOK && !zeroing { + return true, false, fmt.Errorf("arm64 ZREVD requires Q vectors and P0..P7/M or P0..P7/Z: %q", ins.Raw) + } + sourceValue, vectorType, err := c.loadZRegElements(source, 64) + if err != nil { + return true, false, err + } + mergeValue := "zeroinitializer" + if !zeroing { + mergeValue, _, err = c.loadZRegElements(destination, 64) + if err != nil { + return true, false, err + } + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, 64) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.revd.nxv2i64(%s %s, %s %s, %s %s)\n", result, vectorType, vectorType, mergeValue, predicateType, predicateValue, vectorType, sourceValue) + return true, false, c.storeZRegElements(destination, 64, "%"+result) +} diff --git a/arm64_lower_sve_revd_test.go b/arm64_lower_sve_revd_test.go new file mode 100644 index 00000000..3c28bbfd --- /dev/null +++ b/arm64_lower_sve_revd_test.go @@ -0,0 +1,55 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVERevdCompleteGo127Family(t *testing.T) { + source := "TEXT sverevdforms(SB),$0-0\n\tZREVD Z1.Q, P0.M, Z2.Q\n\tZREVD Z3.Q, P7.Z, Z4.Q\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sverevdforms": {Name: "sverevdforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2p1,+sve2p2"`, "@llvm.aarch64.sve.revd.nxv2i64", "zeroinitializer"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE REVD lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-revd.ll", "arm64-sve-revd.o", ll) + }) + } +} + +func TestTranslateARM64SVERevdRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZREVD Z1.D, P0.M, Z2.D", + "ZREVD Z1.Q, P0, Z2.Q", + "ZREVD Z1.Q, P8.M, Z2.Q", + "ZREVD Z1.Q, P0.M", + "ZREVD.Z Z1.Q, P0.M, Z2.Q", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsverevd(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsverevd": {Name: "badsverevd", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE REVD forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_rounding_shift_test.go b/arm64_lower_sve_rounding_shift_test.go new file mode 100644 index 00000000..bdcec07e --- /dev/null +++ b/arm64_lower_sve_rounding_shift_test.go @@ -0,0 +1,82 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +var arm64SVERoundingShiftOps = []string{ + "ZSQRSHL", "ZSQRSHLR", "ZSQSHLR", + "ZUQRSHL", "ZUQRSHLR", "ZUQSHLR", + "ZSRSHL", "ZSRSHLR", "ZURSHL", "ZURSHLR", +} + +func arm64SVERoundingShiftCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveroundingshiftforms(SB),$0-0\n") + for _, op := range arm64SVERoundingShiftOps { + for _, width := range []string{"B", "H", "S", "D"} { + source.WriteString("\t" + op + " Z1." + width + ", Z2." + width + ", P0.M, Z2." + width + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVERoundingShiftCompleteGo127Family(t *testing.T) { + source := arm64SVERoundingShiftCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveroundingshiftforms": {Name: "sveroundingshiftforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.sqrshl.nxv", + "@llvm.aarch64.sve.uqrshl.nxv", + "@llvm.aarch64.sve.sqshl.nxv", + "@llvm.aarch64.sve.uqshl.nxv", + "@llvm.aarch64.sve.srshl.nxv", + "@llvm.aarch64.sve.urshl.nxv", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE rounding-shift lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-rounding-shift.ll", "arm64-sve-rounding-shift.o", ll) + }) + } +} + +func TestTranslateARM64SVERoundingShiftRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSQRSHL Z1.B, Z2.H, P0.M, Z2.H", + "ZSQRSHLR Z1.S, Z2.S, P0.M, Z3.S", + "ZSQSHLR $1, Z2.S, P0.M, Z2.S", + "ZUQRSHL Z1.D, Z2.D, P8.M, Z2.D", + "ZSRSHL Z1.S, Z2.S, P0, Z2.S", + "ZURSHLR.Z Z1.S, Z2.S, P0.M, Z2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_", "$", "imm").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveroundingshift(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveroundingshift": {Name: "badsveroundingshift", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE rounding-shift forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_saturating_multiply_high.go b/arm64_lower_sve_saturating_multiply_high.go new file mode 100644 index 00000000..feef4292 --- /dev/null +++ b/arm64_lower_sve_saturating_multiply_high.go @@ -0,0 +1,62 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVESaturatingMultiplyHighIntrinsics = map[Op]string{ + "ZSQDMULH": "sqdmulh", + "ZSQRDMULH": "sqrdmulh", +} + +func (c *arm64Ctx) lowerARM64SVESaturatingMultiplyHigh(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVESaturatingMultiplyHighIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 vector form without a suffix: %q", op, ins.Raw) + } + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !firstOK || !destinationOK || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s source and destination widths must match: %q", op, ins.Raw) + } + second, secondBits, lane, indexed := arm64ParseSVEZIndexedElementReg(ins.Args[0]) + if !indexed { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + if !secondOK || secondBits != firstBits { + return true, false, fmt.Errorf("arm64 %s vector operands must use one B/H/S/D width: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVESaturatingMultiplyHighForm(intrinsic, firstBits, first, second, 0, destination, false) + } + if secondBits != firstBits { + return true, false, fmt.Errorf("arm64 %s indexed operands must use one H/S/D width and an encodable lane: %q", op, ins.Raw) + } + return true, false, c.lowerARM64SVESaturatingMultiplyHighForm(intrinsic, firstBits, first, second, lane, destination, true) +} + +func (c *arm64Ctx) lowerARM64SVESaturatingMultiplyHighForm(intrinsic string, elementBits, first, second, lane, destination int, indexed bool) error { + firstValue, vectorType, err := c.loadZRegElements(first, elementBits) + if err != nil { + return err + } + secondValue, _, err := c.loadZRegElements(second, elementBits) + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return err + } + result := c.newTmp() + if indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.lane.nxv%di%d(%s %s, %s %s, i32 %d)\n", + result, vectorType, intrinsic, lanes, elementBits, vectorType, firstValue, vectorType, secondValue, lane) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", + result, vectorType, intrinsic, lanes, elementBits, vectorType, firstValue, vectorType, secondValue) + } + return c.storeZRegElements(destination, elementBits, "%"+result) +} diff --git a/arm64_lower_sve_saturating_multiply_high_test.go b/arm64_lower_sve_saturating_multiply_high_test.go new file mode 100644 index 00000000..38473808 --- /dev/null +++ b/arm64_lower_sve_saturating_multiply_high_test.go @@ -0,0 +1,77 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVESaturatingMultiplyHighCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svesaturatingmultiplyhighforms(SB),$0-0\n") + for _, op := range []string{"ZSQDMULH", "ZSQRDMULH"} { + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, Z3.%s\n", op, width, width, width) + } + for index, width := range []string{"H", "S", "D"} { + maximumVector := []int{7, 7, 15}[index] + maximumLane := []int{7, 3, 1}[index] + fmt.Fprintf(&source, "\t%s Z%d.%s[%d], Z4.%s, Z5.%s\n", op, maximumVector, width, maximumLane, width, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svesaturatingmultiplyhighforms": {Name: "svesaturatingmultiplyhighforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve,+sve2\"", + "@llvm.aarch64.sve.sqdmulh.nxv16i8", + "@llvm.aarch64.sve.sqdmulh.lane.nxv8i16", + "@llvm.aarch64.sve.sqrdmulh.nxv2i64", + "@llvm.aarch64.sve.sqrdmulh.lane.nxv4i32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE saturating multiply-high lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-saturating-multiply-high.ll", "arm64-sve-saturating-multiply-high.o", ll) + }) + } +} + +func TestTranslateARM64SVESaturatingMultiplyHighRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSQDMULH Z1.B, Z2.H, Z3.H", + "ZSQRDMULH Z1.B[0], Z2.B, Z3.B", + "ZSQDMULH Z8.H[0], Z2.H, Z3.H", + "ZSQRDMULH Z7.H[8], Z2.H, Z3.H", + "ZSQDMULH Z7.S[3], Z2.D, Z3.D", + "ZSQRDMULH.Z Z1.S, Z2.S, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvesaturatingmultiplyhigh(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvesaturatingmultiplyhigh": {Name: "badsvesaturatingmultiplyhigh", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE saturating multiply-high forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_saturating_narrow.go b/arm64_lower_sve_saturating_narrow.go new file mode 100644 index 00000000..bbda778f --- /dev/null +++ b/arm64_lower_sve_saturating_narrow.go @@ -0,0 +1,54 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVESaturatingNarrowSpec struct { + intrinsic string + top bool +} + +var arm64SVESaturatingNarrowSpecs = map[Op]arm64SVESaturatingNarrowSpec{ + "ZSQXTNB": {intrinsic: "sqxtnb"}, + "ZSQXTNT": {intrinsic: "sqxtnt", top: true}, + "ZSQXTUNB": {intrinsic: "sqxtunb"}, + "ZSQXTUNT": {intrinsic: "sqxtunt", top: true}, + "ZUQXTNB": {intrinsic: "uqxtnb"}, + "ZUQXTNT": {intrinsic: "uqxtnt", top: true}, +} + +func (c *arm64Ctx) lowerARM64SVESaturatingNarrow(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVESaturatingNarrowSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects Zn.H|S|D, Zd.B|H|S without a suffix: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[1]) + if !sourceOK || !destinationOK || (sourceBits != 16 && sourceBits != 32 && sourceBits != 64) || destinationBits*2 != sourceBits { + return true, false, fmt.Errorf("arm64 %s requires an H-to-B, S-to-H, or D-to-S narrowing pair: %q", op, ins.Raw) + } + sourceValue, sourceType, err := c.loadZRegElements(source, sourceBits) + if err != nil { + return true, false, err + } + destinationType, _, err := arm64SVEVectorType(destinationBits) + if err != nil { + return true, false, err + } + args := fmt.Sprintf("%s %s", sourceType, sourceValue) + if spec.top { + merged, _, err := c.loadZRegElements(destination, destinationBits) + if err != nil { + return true, false, err + } + args = fmt.Sprintf("%s %s, %s", destinationType, merged, args) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s)\n", result, destinationType, spec.intrinsic, 128/sourceBits, sourceBits, args) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_saturating_narrow_test.go b/arm64_lower_sve_saturating_narrow_test.go new file mode 100644 index 00000000..b8f9abc0 --- /dev/null +++ b/arm64_lower_sve_saturating_narrow_test.go @@ -0,0 +1,77 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVESaturatingNarrowCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svesaturatingnarrowforms(SB),$0-0\n") + for _, op := range []string{"ZSQXTNB", "ZSQXTNT", "ZSQXTUNB", "ZSQXTUNT", "ZUQXTNB", "ZUQXTNT"} { + for _, widths := range [][2]string{{"H", "B"}, {"S", "H"}, {"D", "S"}} { + source.WriteString("\t" + op + " Z1." + widths[0] + ", Z2." + widths[1] + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVESaturatingNarrowCompleteGo127Family(t *testing.T) { + source := arm64SVESaturatingNarrowCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svesaturatingnarrowforms": {Name: "svesaturatingnarrowforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.sqxtnb.nxv8i16", + "@llvm.aarch64.sve.sqxtnt.nxv4i32", + "@llvm.aarch64.sve.sqxtunb.nxv2i64", + "@llvm.aarch64.sve.sqxtunt.nxv8i16", + "@llvm.aarch64.sve.uqxtnb.nxv4i32", + "@llvm.aarch64.sve.uqxtnt.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE saturating-narrow lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-saturating-narrow.ll", "arm64-sve-saturating-narrow.o", ll) + }) + } +} + +func TestTranslateARM64SVESaturatingNarrowRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSQXTNB Z1.B, Z2.B", + "ZSQXTNT Z1.H, Z2.H", + "ZSQXTUNB Z1.S, Z2.B", + "ZSQXTUNT Z1.D, Z2.H", + "ZUQXTNB Z1.Q, Z2.D", + "ZUQXTNT Z1.D", + "ZSQXTNB.Z Z1.H, Z2.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvesaturatingnarrow(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvesaturatingnarrow": {Name: "badsvesaturatingnarrow", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE saturating-narrow forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_saturating_rounding_multiply_accumulate_high.go b/arm64_lower_sve_saturating_rounding_multiply_accumulate_high.go new file mode 100644 index 00000000..49e8d208 --- /dev/null +++ b/arm64_lower_sve_saturating_rounding_multiply_accumulate_high.go @@ -0,0 +1,61 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVESaturatingRoundingMultiplyAccumulateHighIntrinsics = map[Op]string{ + "ZSQRDMLAH": "sqrdmlah", + "ZSQRDMLSH": "sqrdmlsh", +} + +func (c *arm64Ctx) lowerARM64SVESaturatingRoundingMultiplyAccumulateHigh(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVESaturatingRoundingMultiplyAccumulateHighIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 vector form without a suffix: %q", op, ins.Raw) + } + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !firstOK || !destinationOK || firstBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s source and accumulator widths must match: %q", op, ins.Raw) + } + second, secondBits, lane, indexed := arm64ParseSVEZIndexedElementReg(ins.Args[0]) + if !indexed { + var secondOK bool + second, secondBits, secondOK = arm64ParseSVEZElementReg(ins.Args[0]) + if !secondOK || secondBits != firstBits { + return true, false, fmt.Errorf("arm64 %s vector operands must use one B/H/S/D width: %q", op, ins.Raw) + } + } else if secondBits != firstBits { + return true, false, fmt.Errorf("arm64 %s indexed operands must use one H/S/D width and an encodable lane: %q", op, ins.Raw) + } + accumulator, vectorType, err := c.loadZRegElements(destination, firstBits) + if err != nil { + return true, false, err + } + firstValue, _, err := c.loadZRegElements(first, firstBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, firstBits) + if err != nil { + return true, false, err + } + _, lanes, err := arm64SVEVectorType(firstBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + if indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.lane.nxv%di%d(%s %s, %s %s, %s %s, i32 %d)\n", + result, vectorType, intrinsic, lanes, firstBits, vectorType, accumulator, vectorType, firstValue, vectorType, secondValue, lane) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", + result, vectorType, intrinsic, lanes, firstBits, vectorType, accumulator, vectorType, firstValue, vectorType, secondValue) + } + return true, false, c.storeZRegElements(destination, firstBits, "%"+result) +} diff --git a/arm64_lower_sve_saturating_rounding_multiply_accumulate_high_test.go b/arm64_lower_sve_saturating_rounding_multiply_accumulate_high_test.go new file mode 100644 index 00000000..3921b049 --- /dev/null +++ b/arm64_lower_sve_saturating_rounding_multiply_accumulate_high_test.go @@ -0,0 +1,77 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVESaturatingRoundingMultiplyAccumulateHighCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svesaturatingroundingmultiplyaccumulatehighforms(SB),$0-0\n") + for _, op := range []string{"ZSQRDMLAH", "ZSQRDMLSH"} { + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, Z3.%s\n", op, width, width, width) + } + for index, width := range []string{"H", "S", "D"} { + maximumVector := []int{7, 7, 15}[index] + maximumLane := []int{7, 3, 1}[index] + fmt.Fprintf(&source, "\t%s Z%d.%s[%d], Z4.%s, Z5.%s\n", op, maximumVector, width, maximumLane, width, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svesaturatingroundingmultiplyaccumulatehighforms": {Name: "svesaturatingroundingmultiplyaccumulatehighforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve,+sve2\"", + "@llvm.aarch64.sve.sqrdmlah.nxv16i8", + "@llvm.aarch64.sve.sqrdmlah.lane.nxv8i16", + "@llvm.aarch64.sve.sqrdmlsh.nxv2i64", + "@llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE saturating rounding multiply-accumulate-high lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-saturating-rounding-multiply-accumulate-high.ll", "arm64-sve-saturating-rounding-multiply-accumulate-high.o", ll) + }) + } +} + +func TestTranslateARM64SVESaturatingRoundingMultiplyAccumulateHighRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSQRDMLAH Z1.B, Z2.H, Z3.H", + "ZSQRDMLSH Z1.B[0], Z2.B, Z3.B", + "ZSQRDMLAH Z8.H[0], Z2.H, Z3.H", + "ZSQRDMLSH Z7.H[8], Z2.H, Z3.H", + "ZSQRDMLAH Z7.S[3], Z2.D, Z3.D", + "ZSQRDMLSH.Z Z1.S, Z2.S, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvesaturatingroundingmultiplyaccumulatehigh(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvesaturatingroundingmultiplyaccumulatehigh": {Name: "badsvesaturatingroundingmultiplyaccumulatehigh", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE saturating rounding multiply-accumulate-high forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_saturating_shift.go b/arm64_lower_sve_saturating_shift.go new file mode 100644 index 00000000..34780765 --- /dev/null +++ b/arm64_lower_sve_saturating_shift.go @@ -0,0 +1,85 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEVariableShiftSpec struct { + intrinsic string + immediate bool + reverse bool +} + +var arm64SVEVariableShiftSpecs = map[Op]arm64SVEVariableShiftSpec{ + "ZSQSHL": {intrinsic: "sqshl", immediate: true}, + "ZUQSHL": {intrinsic: "uqshl", immediate: true}, + "ZSQRSHL": {intrinsic: "sqrshl"}, + "ZSQRSHLR": {intrinsic: "sqrshl", reverse: true}, + "ZSQSHLR": {intrinsic: "sqshl", reverse: true}, + "ZUQRSHL": {intrinsic: "uqrshl"}, + "ZUQRSHLR": {intrinsic: "uqrshl", reverse: true}, + "ZUQSHLR": {intrinsic: "uqshl", reverse: true}, + "ZSRSHL": {intrinsic: "srshl"}, + "ZSRSHLR": {intrinsic: "srshl", reverse: true}, + "ZURSHL": {intrinsic: "urshl"}, + "ZURSHLR": {intrinsic: "urshl", reverse: true}, +} + +func (c *arm64Ctx) lowerARM64SVESaturatingShift(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEVariableShiftSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects shift, Zdn.T, P0..P7.M, Zdn.T without a suffix: %q", op, ins.Raw) + } + data, elementBits, dataOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[2], "M", 7) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !dataOK || !predicateOK || !destinationOK || data != destination || elementBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s requires matching destructive data operands and P0..P7.M: %q", op, ins.Raw) + } + dataValue, vectorType, err := c.loadZRegElements(data, elementBits) + if err != nil { + return true, false, err + } + shiftValue := "" + if ins.Args[0].Kind == OpImm { + if !spec.immediate || ins.Args[0].ImmRaw != "" || ins.Args[0].Imm < 0 || ins.Args[0].Imm >= int64(elementBits) { + return true, false, fmt.Errorf("arm64 %s immediate must be in 0..%d: %q", op, elementBits-1, ins.Raw) + } + shiftValue = fmt.Sprintf("splat (i%d %d)", elementBits, ins.Args[0].Imm) + } else { + shifts, shiftBits, shiftsOK := arm64ParseSVEZElementReg(ins.Args[0]) + if !shiftsOK || shiftBits != elementBits { + return true, false, fmt.Errorf("arm64 %s shift vector must match the B/H/S/D data width: %q", op, ins.Raw) + } + shiftValue, _, err = c.loadZRegElements(shifts, elementBits) + if err != nil { + return true, false, err + } + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + firstValue, secondValue := dataValue, shiftValue + if spec.reverse { + firstValue, secondValue = shiftValue, dataValue + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", + result, vectorType, spec.intrinsic, lanes, elementBits, predicateType, predicateValue, vectorType, firstValue, vectorType, secondValue) + resultValue := "%" + result + if spec.reverse { + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", selected, predicateType, predicateValue, vectorType, resultValue, vectorType, dataValue) + resultValue = "%" + selected + } + return true, false, c.storeZRegElements(destination, elementBits, resultValue) +} diff --git a/arm64_lower_sve_saturating_shift_narrow.go b/arm64_lower_sve_saturating_shift_narrow.go new file mode 100644 index 00000000..c03a8e2c --- /dev/null +++ b/arm64_lower_sve_saturating_shift_narrow.go @@ -0,0 +1,61 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVESaturatingShiftNarrowSpec struct { + intrinsic string + top bool +} + +var arm64SVESaturatingShiftNarrowSpecs = map[Op]arm64SVESaturatingShiftNarrowSpec{ + "ZSQSHRNB": {intrinsic: "sqshrnb"}, + "ZSQSHRNT": {intrinsic: "sqshrnt", top: true}, + "ZSQRSHRNB": {intrinsic: "sqrshrnb"}, + "ZSQRSHRNT": {intrinsic: "sqrshrnt", top: true}, + "ZSQSHRUNB": {intrinsic: "sqshrunb"}, + "ZSQSHRUNT": {intrinsic: "sqshrunt", top: true}, + "ZSQRSHRUNB": {intrinsic: "sqrshrunb"}, + "ZSQRSHRUNT": {intrinsic: "sqrshrunt", top: true}, + "ZUQSHRNB": {intrinsic: "uqshrnb"}, + "ZUQSHRNT": {intrinsic: "uqshrnt", top: true}, + "ZUQRSHRNB": {intrinsic: "uqrshrnb"}, + "ZUQRSHRNT": {intrinsic: "uqrshrnt", top: true}, +} + +func (c *arm64Ctx) lowerARM64SVESaturatingShiftNarrow(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVESaturatingShiftNarrowSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 %s expects $shift, Zn.H|S|D, Zd.B|H|S without a suffix: %q", op, ins.Raw) + } + shift := ins.Args[0].Imm + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !sourceOK || !destinationOK || (sourceBits != 16 && sourceBits != 32 && sourceBits != 64) || destinationBits*2 != sourceBits || shift < 1 || shift > int64(destinationBits) { + return true, false, fmt.Errorf("arm64 %s requires matching H-to-B, S-to-H, or D-to-S operands and shift $1..$destinationBits: %q", op, ins.Raw) + } + sourceValue, sourceType, err := c.loadZRegElements(source, sourceBits) + if err != nil { + return true, false, err + } + destinationType, _, err := arm64SVEVectorType(destinationBits) + if err != nil { + return true, false, err + } + args := fmt.Sprintf("%s %s, i32 %d", sourceType, sourceValue, shift) + if spec.top { + merged, _, err := c.loadZRegElements(destination, destinationBits) + if err != nil { + return true, false, err + } + args = fmt.Sprintf("%s %s, %s", destinationType, merged, args) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s)\n", result, destinationType, spec.intrinsic, 128/sourceBits, sourceBits, args) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_saturating_shift_narrow_test.go b/arm64_lower_sve_saturating_shift_narrow_test.go new file mode 100644 index 00000000..c6d06fda --- /dev/null +++ b/arm64_lower_sve_saturating_shift_narrow_test.go @@ -0,0 +1,106 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +var arm64SVESaturatingShiftNarrowOps = []string{ + "ZSQSHRNB", "ZSQSHRNT", "ZSQRSHRNB", "ZSQRSHRNT", + "ZSQSHRUNB", "ZSQSHRUNT", "ZSQRSHRUNB", "ZSQRSHRUNT", + "ZUQSHRNB", "ZUQSHRNT", "ZUQRSHRNB", "ZUQRSHRNT", +} + +func arm64SVESaturatingShiftNarrowCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svesaturatingshiftnarrowforms(SB),$0-0\n") + for _, op := range arm64SVESaturatingShiftNarrowOps { + for _, form := range []struct { + source, destination string + max int + }{{"H", "B", 8}, {"S", "H", 16}, {"D", "S", 32}} { + for _, shift := range []int{1, form.max} { + fmt.Fprintf(&source, "\t%s $%d, Z1.%s, Z2.%s\n", op, shift, form.source, form.destination) + } + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVESaturatingShiftNarrowCompleteGo127Family(t *testing.T) { + source := arm64SVESaturatingShiftNarrowCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svesaturatingshiftnarrowforms": {Name: "svesaturatingshiftnarrowforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{ + "sqshrnb", "sqshrnt", "sqrshrnb", "sqrshrnt", + "sqshrunb", "sqshrunt", "sqrshrunb", "sqrshrunt", + "uqshrnb", "uqshrnt", "uqrshrnb", "uqrshrnt", + } { + if want := "@llvm.aarch64.sve." + intrinsic + ".nxv"; !strings.Contains(ll, want) { + t.Fatalf("%s SVE saturating-shift-narrow lowering omitted %q:\n%s", triple, want, ll) + } + } + if want := `"target-features"="+sve,+sve2"`; !strings.Contains(ll, want) { + t.Fatalf("%s SVE saturating-shift-narrow lowering omitted %q:\n%s", triple, want, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-saturating-shift-narrow.ll", "arm64-sve-saturating-shift-narrow.o", ll) + }) + } +} + +func TestTranslateARM64SVESaturatingShiftNarrowRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSQSHRNB $0, Z1.H, Z2.B", + "ZSQRSHRNT $1, Z1.S, Z2.B", + "ZSQSHRUNB $1, Z1.Q, Z2.D", + "ZSQRSHRUNT $1, Z1.D", + "ZUQSHRNB.Z $1, Z1.H, Z2.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_", "$", "imm").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvesaturatingshiftnarrow(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvesaturatingshiftnarrow": {Name: "badsvesaturatingshiftnarrow", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE saturating-shift-narrow forms", instruction) + } + }) + } +} + +func TestTranslateARM64SVESaturatingShiftNarrowRejectsGoAcceptedUnencodableShifts(t *testing.T) { + for _, instruction := range []string{ + "ZSQSHRNT $9, Z1.H, Z2.B", + "ZSQRSHRUNB $17, Z1.S, Z2.H", + "ZUQRSHRNT $33, Z1.D, Z2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_", "$", "imm").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvesaturatingshiftnarrowrange(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvesaturatingshiftnarrowrange": {Name: "badsvesaturatingshiftnarrowrange", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted Go-assembler form %q that LLVM 22 cannot encode", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_saturating_shift_test.go b/arm64_lower_sve_saturating_shift_test.go new file mode 100644 index 00000000..4b11dc0f --- /dev/null +++ b/arm64_lower_sve_saturating_shift_test.go @@ -0,0 +1,75 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVESaturatingShiftCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svesaturatingshiftforms(SB),$0-0\n") + for _, op := range []string{"ZSQSHL", "ZUQSHL"} { + for index, width := range []string{"B", "H", "S", "D"} { + maximum := []int{7, 15, 31, 63}[index] + fmt.Fprintf(&source, "\t%s Z1.%s, Z2.%s, P%d.M, Z2.%s\n", op, width, width, index, width) + fmt.Fprintf(&source, "\t%s $0, Z3.%s, P%d.M, Z3.%s\n", op, width, index, width) + fmt.Fprintf(&source, "\t%s $%d, Z4.%s, P%d.M, Z4.%s\n", op, maximum, width, index, width) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svesaturatingshiftforms": {Name: "svesaturatingshiftforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve,+sve2\"", + "@llvm.aarch64.sve.sqshl.nxv", + "@llvm.aarch64.sve.uqshl.nxv", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE saturating-shift lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-saturating-shift.ll", "arm64-sve-saturating-shift.o", ll) + }) + } +} + +func TestTranslateARM64SVESaturatingShiftRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSQSHL $-1, Z1.B, P0.M, Z1.B", + "ZUQSHL $8, Z1.B, P0.M, Z1.B", + "ZSQSHL $16, Z1.H, P0.M, Z1.H", + "ZUQSHL Z1.S, Z2.H, P0.M, Z2.H", + "ZSQSHL Z1.S, Z2.S, P0, Z2.S", + "ZUQSHL Z1.S, Z2.S, P8.M, Z2.S", + "ZSQSHL Z1.S, Z2.S, P0.M, Z3.S", + "ZUQSHL.Z Z1.S, Z2.S, P0.M, Z2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvesaturatingshift(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvesaturatingshift": {Name: "badsvesaturatingshift", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE saturating-shift forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_select.go b/arm64_lower_sve_select.go new file mode 100644 index 00000000..b54f7da7 --- /dev/null +++ b/arm64_lower_sve_select.go @@ -0,0 +1,81 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +type arm64RawSVESelect struct { + elementBits int + falseValue int + trueValue int + predicate int + destination int +} + +func decodeARM64RawSVESelect(word uint32) (arm64RawSVESelect, bool) { + if word&0xff20c000 != 0x0520c000 { + return arm64RawSVESelect{}, false + } + return arm64RawSVESelect{ + elementBits: 8 << (int(word>>22) & 3), + falseValue: int(word>>16) & 31, + trueValue: int(word>>5) & 31, + predicate: int(word>>10) & 15, + destination: int(word) & 31, + }, true +} + +func arm64ParseSVEPredicate(operand Operand) (int, bool) { + if operand.Kind != OpReg { + return 0, false + } + name := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + if strings.Contains(name, ".") || !strings.HasPrefix(name, "P") { + return 0, false + } + index, err := strconv.Atoi(strings.TrimPrefix(name, "P")) + return index, err == nil && index >= 0 && index < 16 +} + +func (c *arm64Ctx) lowerARM64SVESelect(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZSEL" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 ZSEL expects Zm.T, Zn.T, Pv, Zd.T: %q", ins.Raw) + } + falseValue, falseBits, falseOK := arm64ParseSVEZElementReg(ins.Args[0]) + trueValue, trueBits, trueOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicate(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !falseOK || !trueOK || !predicateOK || !destinationOK || falseBits != trueBits || trueBits != destinationBits { + return true, false, fmt.Errorf("arm64 ZSEL operands must share one element width and use a bare P0..P15 predicate: %q", ins.Raw) + } + return true, false, c.lowerRawSVESelect(arm64RawSVESelect{ + elementBits: falseBits, + falseValue: falseValue, + trueValue: trueValue, + predicate: predicate, + destination: destination, + }) +} + +func (c *arm64Ctx) lowerRawSVESelect(form arm64RawSVESelect) error { + falseValue, vectorType, err := c.loadZRegElements(form.falseValue, form.elementBits) + if err != nil { + return err + } + trueValue, _, err := c.loadZRegElements(form.trueValue, form.elementBits) + if err != nil { + return err + } + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", result, predicateType, predicate, vectorType, trueValue, vectorType, falseValue) + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) +} diff --git a/arm64_lower_sve_select_test.go b/arm64_lower_sve_select_test.go new file mode 100644 index 00000000..042be66b --- /dev/null +++ b/arm64_lower_sve_select_test.go @@ -0,0 +1,106 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64RawSVESelect(elementBits, falseValue, trueValue, predicate, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + return 0x0520c000 | size<<22 | uint32(falseValue)<<16 | uint32(trueValue)<<5 | uint32(predicate)<<10 | uint32(destination) +} + +func TestTranslateARM64SVESelectCompleteGo127Form(t *testing.T) { + const named = ` +TEXT sveselnamed(SB),$0-0 + ZSEL Z31.B, Z30.B, P0, Z29.B + ZSEL Z28.H, Z27.H, P5, Z26.H + ZSEL Z25.S, Z24.S, P10, Z23.S + ZSEL Z22.D, Z21.D, P15, Z20.D + RET +` + requireARM64SVEGoAssemblerResult(t, named, true) + + var raw strings.Builder + raw.WriteString("TEXT sveselraw(SB),$0-0\n") + for i, elementBits := range []int{8, 16, 32, 64} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVESelect(elementBits, i, i+4, i*5, i+8)) + } + raw.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, raw.String(), true) + + for name, source := range map[string]string{"named": named, "raw": raw.String()} { + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "svesel" + name + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve"`, " select ", " select ", " select ", " select "} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 SVE SEL lowering for %s/%s omitted %q:\n%s", name, triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-select.ll", "arm64-sve-select.o", ll) + }) + } + }) + } +} + +func TestARM64RawSVESelectDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for _, elementBits := range []int{8, 16, 32, 64} { + for falseValue := 0; falseValue < 32; falseValue++ { + for trueValue := 0; trueValue < 32; trueValue++ { + for predicate := 0; predicate < 16; predicate++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVESelect(elementBits, falseValue, trueValue, predicate, destination) + got, ok := decodeARM64RawSVESelect(word) + if !ok || got.elementBits != elementBits || got.falseValue != falseValue || got.trueValue != trueValue || got.predicate != predicate || got.destination != destination { + t.Fatalf("decoded SVE SEL %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + } + if count != 4*32*32*16*32 { + t.Fatalf("covered %d SVE SEL encodings, want %d", count, 4*32*32*16*32) + } +} + +func TestARM64SVESelectRejectsAdjacentAndPredicateSuffix(t *testing.T) { + for _, word := range []uint32{0x05208000, 0x0520a000, 0x05204000} { + if _, ok := decodeARM64RawSVESelect(word); ok { + t.Fatalf("SVE SEL decoder accepted adjacent encoding %#08x", word) + } + } + const invalid = ` +TEXT badsvesel(SB),$0-0 + ZSEL Z1.S, Z2.S, P3.M, Z4.S + RET +` + requireARM64SVEGoAssemblerResult(t, invalid, false) + file, err := Parse(ArchARM64, invalid) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvesel": {Name: "badsvesel", Ret: Void}}}); err == nil { + t.Fatal("translator accepted SVE SEL merge predicate syntax") + } +} diff --git a/arm64_lower_sve_shift_extra.go b/arm64_lower_sve_shift_extra.go new file mode 100644 index 00000000..55d2cd22 --- /dev/null +++ b/arm64_lower_sve_shift_extra.go @@ -0,0 +1,118 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEImmediateShiftSpec struct { + intrinsic string + predicated bool + minimum int64 + sve2 bool +} + +var arm64SVEImmediateShiftSpecs = map[Op]arm64SVEImmediateShiftSpec{ + "ZASRD": {intrinsic: "asrd", predicated: true, minimum: 1}, + "ZSLI": {intrinsic: "sli", sve2: true}, + "ZSQSHLU": {intrinsic: "sqshlu", predicated: true, sve2: true}, + "ZSRI": {intrinsic: "sri", minimum: 1, sve2: true}, + "ZSRSHR": {intrinsic: "srshr", predicated: true, minimum: 1, sve2: true}, + "ZSRSRA": {intrinsic: "srsra", minimum: 1, sve2: true}, + "ZSSRA": {intrinsic: "ssra", minimum: 1, sve2: true}, + "ZURSHR": {intrinsic: "urshr", predicated: true, minimum: 1, sve2: true}, + "ZURSRA": {intrinsic: "ursra", minimum: 1, sve2: true}, + "ZUSRA": {intrinsic: "usra", minimum: 1, sve2: true}, +} + +var arm64SVEReverseShiftIntrinsics = map[Op]string{ + "ZASRR": "asr", + "ZLSLR": "lsl", + "ZLSRR": "lsr", +} + +func (c *arm64Ctx) lowerARM64SVEExtraShift(op Op, ins Instr) (ok bool, terminated bool, err error) { + if spec, ok := arm64SVEImmediateShiftSpecs[op]; ok { + return c.lowerARM64SVEExtraImmediateShift(op, ins, spec) + } + intrinsic, ok := arm64SVEReverseShiftIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects Zm.T, Zdn.T, Pg/M, Zdn.T without a suffix: %q", op, ins.Raw) + } + data, dataBits, dataOK := arm64ParseSVEZElementReg(ins.Args[0]) + oldDestination, oldBits, oldOK := arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !dataOK || !oldOK || !predicateOK || !destinationOK || dataBits != oldBits || oldBits != destinationBits || oldDestination != destination { + return true, false, fmt.Errorf("arm64 %s requires matching vectors and a repeated destructive destination: %q", op, ins.Raw) + } + dataValue, vectorType, err := c.loadZRegElements(data, dataBits) + if err != nil { + return true, false, err + } + oldValue, _, err := c.loadZRegElements(destination, dataBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, dataBits) + if err != nil { + return true, false, err + } + allTrue, _, err := c.allTruePRegElements(dataBits) + if err != nil { + return true, false, err + } + _, lanes, _ := arm64SVEVectorType(dataBits) + active := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", active, vectorType, intrinsic, lanes, dataBits, predicateType, allTrue, vectorType, dataValue, vectorType, oldValue) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %%%s, %s %s\n", result, predicateType, predicateValue, vectorType, active, vectorType, oldValue) + return true, false, c.storeZRegElements(destination, dataBits, "%"+result) +} + +func (c *arm64Ctx) lowerARM64SVEExtraImmediateShift(op Op, ins Instr, spec arm64SVEImmediateShiftSpec) (ok bool, terminated bool, err error) { + wantArgs := 3 + if spec.predicated { + wantArgs = 4 + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != wantArgs || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 %s expects its Go 1.27 immediate form without a suffix: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[1]) + destinationIndex := wantArgs - 1 + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[destinationIndex]) + shift := ins.Args[0].Imm + if !sourceOK || !destinationOK || sourceBits != destinationBits || shift < spec.minimum || shift >= int64(sourceBits) { + return true, false, fmt.Errorf("arm64 %s immediate is outside Go 1.27's element-width range: %q", op, ins.Raw) + } + var predicateValue, predicateType string + if spec.predicated { + predicate, predicateOK := arm64ParseSVEPredicateMerge(ins.Args[2]) + if !predicateOK || source != destination { + return true, false, fmt.Errorf("arm64 %s requires a repeated destructive destination and Pg/M: %q", op, ins.Raw) + } + predicateValue, predicateType, err = c.loadPRegElements(predicate, sourceBits) + if err != nil { + return true, false, err + } + } + sourceValue, vectorType, err := c.loadZRegElements(source, sourceBits) + if err != nil { + return true, false, err + } + _, lanes, _ := arm64SVEVectorType(sourceBits) + result := c.newTmp() + if spec.predicated { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, i32 %d)\n", result, vectorType, spec.intrinsic, lanes, sourceBits, predicateType, predicateValue, vectorType, sourceValue, shift) + } else { + oldDestination, _, err := c.loadZRegElements(destination, sourceBits) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, i32 %d)\n", result, vectorType, spec.intrinsic, lanes, sourceBits, vectorType, oldDestination, vectorType, sourceValue, shift) + } + return true, false, c.storeZRegElements(destination, sourceBits, "%"+result) +} diff --git a/arm64_lower_sve_shift_extra_test.go b/arm64_lower_sve_shift_extra_test.go new file mode 100644 index 00000000..8e8a839f --- /dev/null +++ b/arm64_lower_sve_shift_extra_test.go @@ -0,0 +1,90 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEExtraShiftCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT sveextrashiftbase(SB),$0-0\n") + for _, suffix := range []string{"B", "H", "S", "D"} { + bits := map[string]int{"B": 8, "H": 16, "S": 32, "D": 64}[suffix] + fmt.Fprintf(&source, "\tZASRD $%d, Z1.%s, P0.M, Z1.%s\n", bits-1, suffix, suffix) + for _, op := range []string{"ZASRR", "ZLSLR", "ZLSRR"} { + fmt.Fprintf(&source, "\t%s Z2.%s, Z3.%s, P1.M, Z3.%s\n", op, suffix, suffix, suffix) + } + } + source.WriteString("\tRET\nTEXT sveextrashiftsve2(SB),$0-0\n") + for _, suffix := range []string{"B", "H", "S", "D"} { + bits := map[string]int{"B": 8, "H": 16, "S": 32, "D": 64}[suffix] + for _, op := range []string{"ZSLI", "ZSQSHLU"} { + if op == "ZSQSHLU" { + fmt.Fprintf(&source, "\t%s $%d, Z4.%s, P2.M, Z4.%s\n", op, bits-1, suffix, suffix) + } else { + fmt.Fprintf(&source, "\t%s $%d, Z4.%s, Z5.%s\n", op, bits-1, suffix, suffix) + } + } + for _, op := range []string{"ZSRI", "ZSRSRA", "ZSSRA", "ZURSRA", "ZUSRA"} { + fmt.Fprintf(&source, "\t%s $%d, Z6.%s, Z7.%s\n", op, bits-1, suffix, suffix) + } + for _, op := range []string{"ZSRSHR", "ZURSHR"} { + fmt.Fprintf(&source, "\t%s $%d, Z8.%s, P3.M, Z8.%s\n", op, bits-1, suffix, suffix) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + sigs := map[string]FuncSig{ + "sveextrashiftbase": {Name: "sveextrashiftbase", Ret: Void}, + "sveextrashiftsve2": {Name: "sveextrashiftsve2", Ret: Void}, + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: sigs}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve"`, `"target-features"="+sve,+sve2"`, "@llvm.aarch64.sve.asrd.", "@llvm.aarch64.sve.sli.", "@llvm.aarch64.sve.ursra."} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE extra shift lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-extra-shift.ll", "arm64-sve-extra-shift.o", ll) + }) + } +} + +func TestTranslateARM64SVEExtraShiftRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZASRD $0, Z1.B, P0.M, Z1.B", + "ZASRD $9, Z1.B, P0.M, Z1.B", + "ZASRR Z1.B, Z2.B, P0.M, Z3.B", + "ZSLI $8, Z1.B, Z2.B", + "ZSRI $0, Z1.B, Z2.B", + "ZSQSHLU $8, Z1.B, P0.M, Z1.B", + "ZSRSHR $1, Z1.H, P0.M, Z2.H", + "ZURSRA $1, Z1.H, Z2.S", + "ZUSRA.Z $1, Z1.B, Z2.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveextrashift(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveextrashift": {Name: "badsveextrashift", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE shift forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_shift_family_test.go b/arm64_lower_sve_shift_family_test.go new file mode 100644 index 00000000..c4ef2c42 --- /dev/null +++ b/arm64_lower_sve_shift_family_test.go @@ -0,0 +1,87 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEShiftNamedForms(op string) string { + var source strings.Builder + function := "sve" + strings.ToLower(op) + "forms" + source.WriteString("TEXT " + function + "(SB),$0-0\n") + for index, width := range []string{"B", "H", "S"} { + predicate := string(rune('0' + index)) + source.WriteString("\t" + op + " Z1.D, Z2." + width + ", P" + predicate + ".M, Z2." + width + "\n") + source.WriteString("\t" + op + " Z3.D, Z4." + width + ", Z5." + width + "\n") + } + for index, width := range []string{"B", "H", "S", "D"} { + predicate := string(rune('4' + index)) + maximum := map[string]string{"B": "7", "H": "15", "S": "31", "D": "63"}[width] + minimum := "1" + if op == "ZLSL" { + minimum = "0" + } + source.WriteString("\t" + op + " Z6." + width + ", Z7." + width + ", P" + predicate + ".M, Z7." + width + "\n") + source.WriteString("\t" + op + " $" + maximum + ", Z8." + width + ", P" + predicate + ".M, Z8." + width + "\n") + source.WriteString("\t" + op + " $" + minimum + ", Z9." + width + ", Z10." + width + "\n") + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEShiftCompleteASRLSLGo127Forms(t *testing.T) { + for _, op := range []string{"ZASR", "ZLSL"} { + t.Run(op, func(t *testing.T) { + source := arm64SVEShiftNamedForms(op) + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "sve" + strings.ToLower(op) + "forms" + intrinsic := strings.ToLower(strings.TrimPrefix(op, "Z")) + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve"`, "@llvm.aarch64.sve." + intrinsic + ".nxv", "@llvm.aarch64.sve." + intrinsic + ".wide.nxv", "@llvm.aarch64.sve.ptrue"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE shift lowering for %s omitted %q:\n%s", triple, op, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-shift.ll", "arm64-sve-shift.o", ll) + }) + } + }) + } +} + +func TestTranslateARM64SVEShiftRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZASR $0, Z1.S, Z2.S", + "ZLSL $32, Z1.S, Z2.S", + "ZASR Z1.H, Z2.H, Z3.H", + "ZLSL Z1.S, Z2.H, P0.M, Z2.H", + "ZASR $1, Z1.S, P0.M, Z2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveshift(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveshift": {Name: "badsveshift", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE shift forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_shift_long.go b/arm64_lower_sve_shift_long.go new file mode 100644 index 00000000..c4c50ad5 --- /dev/null +++ b/arm64_lower_sve_shift_long.go @@ -0,0 +1,40 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEShiftLongIntrinsics = map[Op]string{ + "ZSSHLLB": "sshllb", + "ZSSHLLT": "sshllt", + "ZUSHLLB": "ushllb", + "ZUSHLLT": "ushllt", +} + +func (c *arm64Ctx) lowerARM64SVEShiftLong(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEShiftLongIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 %s expects $shift, Zn.B|H|S, Zd.H|S|D without a suffix: %q", op, ins.Raw) + } + shift := ins.Args[0].Imm + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !sourceOK || !destinationOK || sourceBits == 64 || destinationBits != sourceBits*2 || shift < 0 || shift >= int64(sourceBits) { + return true, false, fmt.Errorf("arm64 %s requires B-to-H, H-to-S, or S-to-D operands and shift $0..$sourceBits-1: %q", op, ins.Raw) + } + sourceValue, sourceType, err := c.loadZRegElements(source, sourceBits) + if err != nil { + return true, false, err + } + destinationType, destinationLanes, err := arm64SVEVectorType(destinationBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, i32 %d)\n", result, destinationType, intrinsic, destinationLanes, destinationBits, sourceType, sourceValue, shift) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_shift_long_test.go b/arm64_lower_sve_shift_long_test.go new file mode 100644 index 00000000..92b4730c --- /dev/null +++ b/arm64_lower_sve_shift_long_test.go @@ -0,0 +1,83 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEShiftLongCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT sveshiftlong(SB),$0-0\n") + widths := []struct { + source string + destination string + maxShift int + }{ + {source: "B", destination: "H", maxShift: 7}, + {source: "H", destination: "S", maxShift: 15}, + {source: "S", destination: "D", maxShift: 31}, + } + for opIndex, op := range []string{"ZSSHLLB", "ZSSHLLT", "ZUSHLLB", "ZUSHLLT"} { + for widthIndex, width := range widths { + for boundaryIndex, shift := range []int{0, width.maxShift} { + reg := (opIndex*6 + widthIndex*2 + boundaryIndex) % 32 + fmt.Fprintf(&source, "\t%s $%d, Z%d.%s, Z%d.%s\n", op, shift, reg, width.source, (reg+1)%32, width.destination) + } + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveshiftlong": {Name: "sveshiftlong", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.sshllb.nxv8i16", + "@llvm.aarch64.sve.sshllt.nxv4i32", + "@llvm.aarch64.sve.ushllb.nxv2i64", + "@llvm.aarch64.sve.ushllt.nxv8i16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE shift-long lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-shift-long.ll", "arm64-sve-shift-long.o", ll) + }) + } +} + +func TestTranslateARM64SVEShiftLongRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSSHLLB $8, Z1.B, Z2.H", + "ZSSHLLT $16, Z1.H, Z2.S", + "ZUSHLLB $32, Z1.S, Z2.D", + "ZUSHLLT $-1, Z1.B, Z2.H", + "ZSSHLLB $0, Z1.B, Z2.S", + "ZUSHLLT $0, Z1.D, Z2.D", + "ZSSHLLB.Z $0, Z1.B, Z2.H", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveshiftlong(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveshiftlong": {Name: "badsveshiftlong", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE shift-long forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_shift_narrow.go b/arm64_lower_sve_shift_narrow.go new file mode 100644 index 00000000..e3706add --- /dev/null +++ b/arm64_lower_sve_shift_narrow.go @@ -0,0 +1,53 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEShiftNarrowSpec struct { + intrinsic string + top bool +} + +var arm64SVEShiftNarrowSpecs = map[Op]arm64SVEShiftNarrowSpec{ + "ZSHRNB": {intrinsic: "shrnb"}, + "ZSHRNT": {intrinsic: "shrnt", top: true}, + "ZRSHRNB": {intrinsic: "rshrnb"}, + "ZRSHRNT": {intrinsic: "rshrnt", top: true}, +} + +func (c *arm64Ctx) lowerARM64SVEShiftNarrow(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEShiftNarrowSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 %s expects $shift, Zn.H|S|D, Zd.B|H|S without a suffix: %q", op, ins.Raw) + } + shift := ins.Args[0].Imm + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !sourceOK || !destinationOK || (sourceBits != 16 && sourceBits != 32 && sourceBits != 64) || destinationBits*2 != sourceBits || shift < 1 || shift > int64(destinationBits) { + return true, false, fmt.Errorf("arm64 %s requires matching H-to-B, S-to-H, or D-to-S operands and shift $1..$destinationBits: %q", op, ins.Raw) + } + sourceValue, sourceType, err := c.loadZRegElements(source, sourceBits) + if err != nil { + return true, false, err + } + destinationType, _, err := arm64SVEVectorType(destinationBits) + if err != nil { + return true, false, err + } + args := fmt.Sprintf("%s %s, i32 %d", sourceType, sourceValue, shift) + if spec.top { + merged, _, err := c.loadZRegElements(destination, destinationBits) + if err != nil { + return true, false, err + } + args = fmt.Sprintf("%s %s, %s", destinationType, merged, args) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s)\n", result, destinationType, spec.intrinsic, 128/sourceBits, sourceBits, args) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_shift_narrow_test.go b/arm64_lower_sve_shift_narrow_test.go new file mode 100644 index 00000000..fd5058be --- /dev/null +++ b/arm64_lower_sve_shift_narrow_test.go @@ -0,0 +1,102 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEShiftNarrowCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveshiftnarrowforms(SB),$0-0\n") + for _, op := range []string{"ZSHRNB", "ZSHRNT", "ZRSHRNB", "ZRSHRNT"} { + for _, form := range []struct { + source, destination string + max int + }{{"H", "B", 8}, {"S", "H", 16}, {"D", "S", 32}} { + for _, shift := range []int{1, form.max} { + fmt.Fprintf(&source, "\t%s $%d, Z1.%s, Z2.%s\n", op, shift, form.source, form.destination) + } + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEShiftNarrowCompleteGo127Family(t *testing.T) { + source := arm64SVEShiftNarrowCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveshiftnarrowforms": {Name: "sveshiftnarrowforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.shrnb.nxv8i16", + "@llvm.aarch64.sve.shrnt.nxv4i32", + "@llvm.aarch64.sve.rshrnb.nxv2i64", + "@llvm.aarch64.sve.rshrnt.nxv8i16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE shift-narrow lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-shift-narrow.ll", "arm64-sve-shift-narrow.o", ll) + }) + } +} + +func TestTranslateARM64SVEShiftNarrowRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSHRNB $0, Z1.H, Z2.B", + "ZSHRNB $1, Z1.S, Z2.B", + "ZRSHRNT $1, Z1.Q, Z2.D", + "ZSHRNB $1, Z1.H", + "ZRSHRNT.Z $1, Z1.D, Z2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_", "$", "imm").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveshiftnarrow(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveshiftnarrow": {Name: "badsveshiftnarrow", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE shift-narrow forms", instruction) + } + }) + } +} + +func TestTranslateARM64SVEShiftNarrowRejectsGoAcceptedUnencodableShifts(t *testing.T) { + // Go 1.27's shared tsz operand accepts shifts up to sourceBits-1 here, + // although the architecture and LLVM narrowing intrinsics allow only + // $1..$destinationBits. Reject these before they can crash LLVM selection. + for _, instruction := range []string{ + "ZSHRNT $9, Z1.H, Z2.B", + "ZRSHRNB $17, Z1.S, Z2.H", + "ZRSHRNT $33, Z1.D, Z2.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_", "$", "imm").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveshiftnarrowrange(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveshiftnarrowrange": {Name: "badsveshiftnarrowrange", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted Go-assembler form %q that LLVM 22 cannot encode", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_splice.go b/arm64_lower_sve_splice.go new file mode 100644 index 00000000..1d216341 --- /dev/null +++ b/arm64_lower_sve_splice.go @@ -0,0 +1,66 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVESplice(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZSPLICE" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) < 3 || len(ins.Args) > 4 { + return true, false, fmt.Errorf("arm64 ZSPLICE expects one Go 1.27 vector form without a suffix: %q", ins.Raw) + } + + var first, second, predicate, destination, elementBits int + if len(ins.Args) == 4 { + var firstOK, secondOK, predicateOK, destinationOK bool + second, elementBits, secondOK = arm64ParseSVEZElementReg(ins.Args[0]) + first, _, firstOK = arm64ParseSVEZElementReg(ins.Args[1]) + predicate, predicateOK = arm64ParseSVEPredicateBare(ins.Args[2], 15) + destination, _, destinationOK = arm64ParseSVEZElementReg(ins.Args[3]) + _, firstBits, _ := arm64ParseSVEZElementReg(ins.Args[1]) + _, destinationBits, _ := arm64ParseSVEZElementReg(ins.Args[3]) + if !firstOK || !secondOK || !predicateOK || !destinationOK || + firstBits != elementBits || destinationBits != elementBits || first != destination { + return true, false, fmt.Errorf("arm64 ZSPLICE destructive form requires Zm.T, Zdn.T, P0..P15, Zdn.T with one B/H/S/D width: %q", ins.Raw) + } + } else { + if ins.Args[0].Kind != OpRegList || len(ins.Args[0].RegList) != 2 { + return true, false, fmt.Errorf("arm64 ZSPLICE list form requires exactly two consecutive vectors: %q", ins.Raw) + } + var firstOK, secondOK, predicateOK, destinationOK bool + first, elementBits, firstOK = arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: ins.Args[0].RegList[0]}) + second, _, secondOK = arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: ins.Args[0].RegList[1]}) + predicate, predicateOK = arm64ParseSVEPredicateBare(ins.Args[1], 15) + destination, _, destinationOK = arm64ParseSVEZElementReg(ins.Args[2]) + _, secondBits, _ := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: ins.Args[0].RegList[1]}) + _, destinationBits, _ := arm64ParseSVEZElementReg(ins.Args[2]) + if !firstOK || !secondOK || !predicateOK || !destinationOK || first == 31 || second != first+1 || + secondBits != elementBits || destinationBits != elementBits { + return true, false, fmt.Errorf("arm64 ZSPLICE list form requires [Zn.T, Z(n+1).T], P0..P15, Zd.T with one B/H/S/D width: %q", ins.Raw) + } + } + + predicateValue, predicateType, err := c.loadPRegElements(predicate, elementBits) + if err != nil { + return true, false, err + } + firstValue, vectorType, err := c.loadZRegElements(first, elementBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, elementBits) + if err != nil { + return true, false, err + } + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.splice.nxv%di%d(%s %s, %s %s, %s %s)\n", + result, vectorType, lanes, elementBits, predicateType, predicateValue, vectorType, firstValue, vectorType, secondValue) + return true, false, c.storeZRegElements(destination, elementBits, "%"+result) +} diff --git a/arm64_lower_sve_splice_test.go b/arm64_lower_sve_splice_test.go new file mode 100644 index 00000000..240c73c0 --- /dev/null +++ b/arm64_lower_sve_splice_test.go @@ -0,0 +1,77 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVESpliceCompleteGo127Family(t *testing.T) { + source := "TEXT svespliceforms(SB),$0-0\n" + + "\tZSPLICE Z2.B, Z1.B, P0, Z1.B\n" + + "\tZSPLICE Z4.H, Z3.H, P1, Z3.H\n" + + "\tZSPLICE Z6.S, Z5.S, P2, Z5.S\n" + + "\tZSPLICE Z8.D, Z7.D, P15, Z7.D\n" + + "\tZSPLICE [Z9.B, Z10.B], P0, Z11.B\n" + + "\tZSPLICE [Z12.H, Z13.H], P1, Z14.H\n" + + "\tZSPLICE [Z15.S, Z16.S], P2, Z17.S\n" + + "\tZSPLICE [Z30.D, Z31.D], P7, Z18.D\n" + + "\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svespliceforms": {Name: "svespliceforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "\"target-features\"=\"+sve\"", + "@llvm.aarch64.sve.splice.nxv16i8", + "@llvm.aarch64.sve.splice.nxv8i16", + "@llvm.aarch64.sve.splice.nxv4i32", + "@llvm.aarch64.sve.splice.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE SPLICE lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-splice.ll", "arm64-sve-splice.o", ll) + }) + } +} + +func TestTranslateARM64SVESpliceRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSPLICE Z2.B, Z1.B, P0, Z3.B", + "ZSPLICE Z2.B, Z1.H, P0, Z1.H", + "ZSPLICE Z2.B, Z1.B, P16, Z1.B", + "ZSPLICE Z2.B, Z1.B, P0.M, Z1.B", + "ZSPLICE [Z1.B], P0, Z3.B", + "ZSPLICE [Z1.B, Z3.B], P0, Z4.B", + "ZSPLICE [Z31.B, Z0.B], P0, Z4.B", + "ZSPLICE [Z1.B, Z2.H], P0, Z4.B", + "ZSPLICE [Z1.B, Z2.B], P0, Z4.H", + "ZSPLICE.Z Z2.B, Z1.B, P0, Z1.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvesplice(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvesplice": {Name: "badsvesplice", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE SPLICE forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_structured_memory.go b/arm64_lower_sve_structured_memory.go new file mode 100644 index 00000000..c9874341 --- /dev/null +++ b/arm64_lower_sve_structured_memory.go @@ -0,0 +1,174 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEStructuredMemorySpec struct { + load bool + vectorCount int + memoryBits int + q bool +} + +// arm64SVEStructuredMemorySpecs covers every Go 1.27 LD2/3/4 and ST2/3/4 +// structured SVE spelling, including the SVE2.1 Q-granule forms. +var arm64SVEStructuredMemorySpecs = map[Op]arm64SVEStructuredMemorySpec{ + "ZLD2B": {load: true, vectorCount: 2, memoryBits: 8}, + "ZLD2H": {load: true, vectorCount: 2, memoryBits: 16}, + "ZLD2W": {load: true, vectorCount: 2, memoryBits: 32}, + "ZLD2D": {load: true, vectorCount: 2, memoryBits: 64}, + "ZLD2Q": {load: true, vectorCount: 2, memoryBits: 128, q: true}, + "ZLD3B": {load: true, vectorCount: 3, memoryBits: 8}, + "ZLD3H": {load: true, vectorCount: 3, memoryBits: 16}, + "ZLD3W": {load: true, vectorCount: 3, memoryBits: 32}, + "ZLD3D": {load: true, vectorCount: 3, memoryBits: 64}, + "ZLD3Q": {load: true, vectorCount: 3, memoryBits: 128, q: true}, + "ZLD4B": {load: true, vectorCount: 4, memoryBits: 8}, + "ZLD4H": {load: true, vectorCount: 4, memoryBits: 16}, + "ZLD4W": {load: true, vectorCount: 4, memoryBits: 32}, + "ZLD4D": {load: true, vectorCount: 4, memoryBits: 64}, + "ZLD4Q": {load: true, vectorCount: 4, memoryBits: 128, q: true}, + "ZST2B": {vectorCount: 2, memoryBits: 8}, + "ZST2H": {vectorCount: 2, memoryBits: 16}, + "ZST2W": {vectorCount: 2, memoryBits: 32}, + "ZST2D": {vectorCount: 2, memoryBits: 64}, + "ZST2Q": {vectorCount: 2, memoryBits: 128, q: true}, + "ZST3B": {vectorCount: 3, memoryBits: 8}, + "ZST3H": {vectorCount: 3, memoryBits: 16}, + "ZST3W": {vectorCount: 3, memoryBits: 32}, + "ZST3D": {vectorCount: 3, memoryBits: 64}, + "ZST3Q": {vectorCount: 3, memoryBits: 128, q: true}, + "ZST4B": {vectorCount: 4, memoryBits: 8}, + "ZST4H": {vectorCount: 4, memoryBits: 16}, + "ZST4W": {vectorCount: 4, memoryBits: 32}, + "ZST4D": {vectorCount: 4, memoryBits: 64}, + "ZST4Q": {vectorCount: 4, memoryBits: 128, q: true}, +} + +func (c *arm64Ctx) lowerARM64SVEStructuredMemory(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEStructuredMemorySpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects its three-operand Go 1.27 form: %q", op, ins.Raw) + } + if spec.load { + return c.lowerARM64SVEStructuredLoad(op, spec, ins) + } + return c.lowerARM64SVEStructuredStore(op, spec, ins) +} + +func (c *arm64Ctx) lowerARM64SVEStructuredLoad(op Op, spec arm64SVEStructuredMemorySpec, ins Instr) (ok bool, terminated bool, err error) { + if ins.Args[0].Kind != OpMem || ins.Args[2].Kind != OpRegList { + return true, false, fmt.Errorf("arm64 %s requires memory, Pn.Z, and vector-list operands: %q", op, ins.Raw) + } + predicate, predicateOK := arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7) + vectors, elementBits, vectorsOK := arm64ParseSVEStructuredVectorList(ins.Args[2], spec.vectorCount) + if !predicateOK || !vectorsOK || elementBits != spec.memoryBits { + return true, false, fmt.Errorf("arm64 %s requires P0..P7.Z and %d consecutive natural-width destination vectors: %q", op, spec.vectorCount, ins.Raw) + } + address, err := c.arm64SVEStructuredAddress(ins.Args[0].Mem, spec) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + valueBits := spec.memoryBits + if spec.q { + valueBits = 64 + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, valueBits) + if err != nil { + return true, false, err + } + vectorType, _, err := arm64SVEVectorType(valueBits) + if err != nil { + return true, false, err + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + aggregateType := arm64SVEAggregateType(vectorType, spec.vectorCount) + result := c.newTmp() + q := "" + if spec.q { + q = "q" + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ld%d%s.sret.nxv%di%d(%s %s, ptr %%%s)\n", + result, aggregateType, spec.vectorCount, q, 128/valueBits, valueBits, predicateType, predicateValue, pointer) + for i, vector := range vectors { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractvalue %s %%%s, %d\n", value, aggregateType, result, i) + if err := c.storeZRegElements(vector, valueBits, "%"+value); err != nil { + return true, false, err + } + } + return true, false, nil +} + +func (c *arm64Ctx) lowerARM64SVEStructuredStore(op Op, spec arm64SVEStructuredMemorySpec, ins Instr) (ok bool, terminated bool, err error) { + if ins.Args[0].Kind != OpRegList || ins.Args[2].Kind != OpMem { + return true, false, fmt.Errorf("arm64 %s requires vector-list, Pn, and memory operands: %q", op, ins.Raw) + } + predicate, predicateOK := arm64ParseSVEPredicateBare(ins.Args[1], 7) + vectors, elementBits, vectorsOK := arm64ParseSVEStructuredVectorList(ins.Args[0], spec.vectorCount) + if !predicateOK || !vectorsOK || elementBits != spec.memoryBits { + return true, false, fmt.Errorf("arm64 %s requires %d consecutive natural-width source vectors and P0..P7: %q", op, spec.vectorCount, ins.Raw) + } + address, err := c.arm64SVEStructuredAddress(ins.Args[2].Mem, spec) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + valueBits := spec.memoryBits + if spec.q { + valueBits = 64 + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, valueBits) + if err != nil { + return true, false, err + } + vectorType, _, err := arm64SVEVectorType(valueBits) + if err != nil { + return true, false, err + } + values := make([]string, len(vectors)) + for i, vector := range vectors { + value, _, err := c.loadZRegElements(vector, valueBits) + if err != nil { + return true, false, err + } + values[i] = fmt.Sprintf("%s %s", vectorType, value) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + q := "" + if spec.q { + q = "q" + } + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.st%d%s.nxv%di%d(%s, %s %s, ptr %%%s)\n", + spec.vectorCount, q, 128/valueBits, valueBits, strings.Join(values, ", "), predicateType, predicateValue, pointer) + return true, false, nil +} + +func (c *arm64Ctx) arm64SVEStructuredAddress(memory MemRef, spec arm64SVEStructuredMemorySpec) (string, error) { + if memory.Index != "" { + return c.arm64SVERegisterOffsetAddress(memory, int64(spec.memoryBits/8)) + } + return c.arm64SVENonTemporalContiguousAddress(memory, spec.memoryBits, spec.vectorCount) +} + +func arm64ParseSVEStructuredVectorList(operand Operand, count int) (vectors []int, elementBits int, ok bool) { + if operand.Kind != OpRegList || len(operand.RegList) != count { + return nil, 0, false + } + vectors = make([]int, len(operand.RegList)) + for i, register := range operand.RegList { + vector, bits, valid := arm64ParseSVEOrdinaryZReg(register) + if !valid || i > 0 && (bits != elementBits || vector != (vectors[i-1]+1)%32) { + return nil, 0, false + } + vectors[i] = vector + elementBits = bits + } + return vectors, elementBits, true +} diff --git a/arm64_lower_sve_structured_memory_test.go b/arm64_lower_sve_structured_memory_test.go new file mode 100644 index 00000000..2460a50d --- /dev/null +++ b/arm64_lower_sve_structured_memory_test.go @@ -0,0 +1,133 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEStructuredMemoryCompleteGo127Forms() string { + var source strings.Builder + source.WriteString("TEXT svestructuredmemoryforms(SB),$0-0\n") + for _, count := range []int{2, 3, 4} { + for _, width := range []struct { + name string + arrangement string + shift int + }{ + {name: "B", arrangement: "B"}, + {name: "H", arrangement: "H", shift: 1}, + {name: "W", arrangement: "S", shift: 2}, + {name: "D", arrangement: "D", shift: 3}, + {name: "Q", arrangement: "Q", shift: 4}, + } { + registers := make([]string, count) + for i := range registers { + registers[i] = fmt.Sprintf("Z%d.%s", 12+i, width.arrangement) + } + list := "[" + strings.Join(registers, ", ") + "]" + index := "R6" + if width.shift != 0 { + index = fmt.Sprintf("R6<<%d", width.shift) + } + load := fmt.Sprintf("ZLD%d%s", count, width.name) + store := fmt.Sprintf("ZST%d%s", count, width.name) + fmt.Fprintf(&source, "\t%s (%s)(R14), P4.Z, %s\n", load, index, list) + fmt.Fprintf(&source, "\t%s (-VL*%d)(R14), P4.Z, %s\n", load, count, list) + fmt.Fprintf(&source, "\t%s %s, P4, (%s)(R14)\n", store, list, index) + fmt.Fprintf(&source, "\t%s %s, P4, (VL*%d)(R14)\n", store, list, count) + } + } + // The hardware encoding wraps consecutive Z lists modulo 32. + source.WriteString("\tZLD2B (R6)(R14), P4.Z, [Z31.B, Z0.B]\n") + source.WriteString("\tZST3H [Z31.H, Z0.H, Z1.H], P4, (R6<<1)(R14)\n") + source.WriteString("\tZLD4D (-VL*4)(R14), P4.Z, [Z30.D, Z31.D, Z0.D, Z1.D]\n") + // Exercise every architectural MUL VL boundary, not only representative values. + source.WriteString("\tZLD2B (-VL*16)(R14), P4.Z, [Z12.B, Z13.B]\n") + source.WriteString("\tZST2B [Z12.B, Z13.B], P4, (VL*14)(R14)\n") + source.WriteString("\tZLD3B (-VL*24)(R14), P4.Z, [Z12.B, Z13.B, Z14.B]\n") + source.WriteString("\tZST3B [Z12.B, Z13.B, Z14.B], P4, (VL*21)(R14)\n") + source.WriteString("\tZLD4B (-VL*32)(R14), P4.Z, [Z12.B, Z13.B, Z14.B, Z15.B]\n") + source.WriteString("\tZST4B [Z12.B, Z13.B, Z14.B, Z15.B], P4, (VL*28)(R14)\n") + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEStructuredMemoryCompleteGo127Family(t *testing.T) { + source := arm64SVEStructuredMemoryCompleteGo127Forms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svestructuredmemoryforms": {Name: "svestructuredmemoryforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2p1"`, + "@llvm.aarch64.sve.ld2.sret.", + "@llvm.aarch64.sve.ld3.sret.", + "@llvm.aarch64.sve.ld4.sret.", + "@llvm.aarch64.sve.st2.", + "@llvm.aarch64.sve.st3.", + "@llvm.aarch64.sve.st4.", + "@llvm.aarch64.sve.ld2q.sret.", + "@llvm.aarch64.sve.ld3q.sret.", + "@llvm.aarch64.sve.ld4q.sret.", + "@llvm.aarch64.sve.st2q.", + "@llvm.aarch64.sve.st3q.", + "@llvm.aarch64.sve.st4q.", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE structured memory lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-structured-memory.ll", "arm64-sve-structured-memory.o", ll) + }) + } +} + +func TestTranslateARM64SVEStructuredMemoryRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZLD2B (R6)(R14), P8.Z, [Z12.B, Z13.B]", + "ZLD2B (R6)(R14), P4, [Z12.B, Z13.B]", + "ZST2B [Z12.B, Z13.B], P4.Z, (R6)(R14)", + "ZLD2H (R6)(R14), P4.Z, [Z12.H, Z13.H]", + "ZLD3W (R6<<1)(R14), P4.Z, [Z12.S, Z13.S, Z14.S]", + "ZST4Q [Z12.Q, Z13.Q, Z14.Q, Z15.Q], P4, (R6<<3)(R14)", + "ZLD2B (R6)(R14), P4.Z, [Z12.B]", + "ZLD3B (R6)(R14), P4.Z, [Z12.B, Z14.B, Z15.B]", + "ZST4H [Z12.H, Z13.H, Z14.S, Z15.H], P4, (R6<<1)(R14)", + "ZLD2B (-VL*18)(R14), P4.Z, [Z12.B, Z13.B]", + "ZST2B [Z12.B, Z13.B], P4, (VL*16)(R14)", + "ZLD3B (-VL*27)(R14), P4.Z, [Z12.B, Z13.B, Z14.B]", + "ZST3B [Z12.B, Z13.B, Z14.B], P4, (VL*24)(R14)", + "ZLD4B (-VL*36)(R14), P4.Z, [Z12.B, Z13.B, Z14.B, Z15.B]", + "ZST4B [Z12.B, Z13.B, Z14.B, Z15.B], P4, (VL*32)(R14)", + "ZLD2B (VL*3)(R14), P4.Z, [Z12.B, Z13.B]", + "ZLD3B (VL*4)(R14), P4.Z, [Z12.B, Z13.B, Z14.B]", + "ZLD4B (VL*6)(R14), P4.Z, [Z12.B, Z13.B, Z14.B, Z15.B]", + "ZLD2B.Z (R6)(R14), P4.Z, [Z12.B, Z13.B]", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvestructuredmemory(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvestructuredmemory": {Name: "badsvestructuredmemory", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's structured memory forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_table.go b/arm64_lower_sve_table.go new file mode 100644 index 00000000..05a40539 --- /dev/null +++ b/arm64_lower_sve_table.go @@ -0,0 +1,95 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64RawSVETable struct { + elementBits int + tableCount int + index int + firstTable int + destination int +} + +func decodeARM64RawSVETable(word uint32) (arm64RawSVETable, bool) { + tableCount := 0 + switch word & 0xff20fc00 { + case 0x05203000: + tableCount = 1 + case 0x05202800: + tableCount = 2 + default: + return arm64RawSVETable{}, false + } + return arm64RawSVETable{ + elementBits: 8 << (int(word>>22) & 3), + tableCount: tableCount, + index: int(word>>16) & 31, + firstTable: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func arm64SVETableNeedsSVE2(ins Instr) bool { + return len(ins.Args) == 3 && ins.Args[1].Kind == OpRegList && len(ins.Args[1].RegList) == 2 +} + +func (c *arm64Ctx) lowerARM64SVETable(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZTBL" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[1].Kind != OpRegList { + return true, false, fmt.Errorf("arm64 ZTBL expects Zm.T, [Zn.T] or [Zn.T, Zn+1.T], Zd.T: %q", ins.Raw) + } + index, indexBits, indexOK := arm64ParseSVEZElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + tables := ins.Args[1].RegList + if !indexOK || !destinationOK || indexBits != destinationBits || (len(tables) != 1 && len(tables) != 2) { + return true, false, fmt.Errorf("arm64 ZTBL requires one width and one or two table registers: %q", ins.Raw) + } + firstTable, tableBits, tableOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: tables[0]}) + if !tableOK || tableBits != indexBits { + return true, false, fmt.Errorf("arm64 ZTBL table width must match its index and destination: %q", ins.Raw) + } + if len(tables) == 2 { + secondTable, secondBits, secondOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: tables[1]}) + if !secondOK || secondBits != tableBits || firstTable == 31 || secondTable != firstTable+1 { + return true, false, fmt.Errorf("arm64 named ZTBL pair must be consecutive without wrapping, as required by Go 1.27: %q", ins.Raw) + } + } + return true, false, c.lowerRawSVETable(arm64RawSVETable{ + elementBits: indexBits, + tableCount: len(tables), + index: index, + firstTable: firstTable, + destination: destination, + }) +} + +func (c *arm64Ctx) lowerRawSVETable(form arm64RawSVETable) error { + index, vectorType, err := c.loadZRegElements(form.index, form.elementBits) + if err != nil { + return err + } + firstTable, _, err := c.loadZRegElements(form.firstTable, form.elementBits) + if err != nil { + return err + } + _, lanes, err := arm64SVEVectorType(form.elementBits) + if err != nil { + return err + } + result := c.newTmp() + if form.tableCount == 1 { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.tbl.nxv%di%d(%s %s, %s %s)\n", result, vectorType, lanes, form.elementBits, vectorType, firstTable, vectorType, index) + } else { + secondTable, _, err := c.loadZRegElements((form.firstTable+1)%32, form.elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.tbl2.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, lanes, form.elementBits, vectorType, firstTable, vectorType, secondTable, vectorType, index) + } + return c.storeZRegElements(form.destination, form.elementBits, "%"+result) +} diff --git a/arm64_lower_sve_table_extension.go b/arm64_lower_sve_table_extension.go new file mode 100644 index 00000000..b35a2d4e --- /dev/null +++ b/arm64_lower_sve_table_extension.go @@ -0,0 +1,57 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVETableExtensionIntrinsics = map[Op]string{ + "ZTBLQ": "tblq", + "ZTBX": "tbx", + "ZTBXQ": "tbxq", +} + +func (c *arm64Ctx) lowerARM64SVETableExtension(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVETableExtensionIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 table form without a suffix: %q", op, ins.Raw) + } + index, indexBits, indexOK := arm64ParseSVEZElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + var table, tableBits int + var tableOK bool + if op == "ZTBLQ" { + if ins.Args[1].Kind != OpRegList || len(ins.Args[1].RegList) != 1 { + return true, false, fmt.Errorf("arm64 ZTBLQ requires exactly one table register list element: %q", ins.Raw) + } + table, tableBits, tableOK = arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: ins.Args[1].RegList[0]}) + } else { + table, tableBits, tableOK = arm64ParseSVEZElementReg(ins.Args[1]) + } + if !indexOK || !tableOK || !destinationOK || indexBits != tableBits || tableBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s operands must use one matching B/H/S/D width: %q", op, ins.Raw) + } + indexValue, vectorType, err := c.loadZRegElements(index, indexBits) + if err != nil { + return true, false, err + } + tableValue, _, err := c.loadZRegElements(table, tableBits) + if err != nil { + return true, false, err + } + lanes := 128 / destinationBits + result := c.newTmp() + if op == "ZTBLQ" { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, vectorType, intrinsic, lanes, destinationBits, vectorType, tableValue, vectorType, indexValue) + } else { + old, _, err := c.loadZRegElements(destination, destinationBits) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, vectorType, intrinsic, lanes, destinationBits, vectorType, old, vectorType, tableValue, vectorType, indexValue) + } + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_table_extension_test.go b/arm64_lower_sve_table_extension_test.go new file mode 100644 index 00000000..a154b8a1 --- /dev/null +++ b/arm64_lower_sve_table_extension_test.go @@ -0,0 +1,63 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVETableExtensionCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svetableextensionforms(SB),$0-0\n") + for _, width := range []string{"B", "H", "S", "D"} { + fmt.Fprintf(&source, "\tZTBLQ Z1.%s, [Z2.%s], Z3.%s\n", width, width, width) + fmt.Fprintf(&source, "\tZTBX Z1.%s, Z2.%s, Z3.%s\n", width, width, width) + fmt.Fprintf(&source, "\tZTBXQ Z1.%s, Z2.%s, Z3.%s\n", width, width, width) + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svetableextensionforms": {Name: "svetableextensionforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2,+sve2p1"`, "@llvm.aarch64.sve.tblq.nxv16i8", "@llvm.aarch64.sve.tbx.nxv4i32", "@llvm.aarch64.sve.tbxq.nxv2i64"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE table extension lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-table-extension.ll", "arm64-sve-table-extension.o", ll) + }) + } +} + +func TestTranslateARM64SVETableExtensionRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZTBLQ Z1.B, [Z2.B, Z3.B], Z4.B", + "ZTBLQ Z1.B, [Z2.H], Z3.B", + "ZTBX Z1.B, Z2.H, Z3.B", + "ZTBXQ Z1.Q, Z2.Q, Z3.Q", + "ZTBXQ.Z Z1.D, Z2.D, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvetableextension(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvetableextension": {Name: "badsvetableextension", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE table extension forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_table_test.go b/arm64_lower_sve_table_test.go new file mode 100644 index 00000000..2c9c46b8 --- /dev/null +++ b/arm64_lower_sve_table_test.go @@ -0,0 +1,116 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64RawSVETable(elementBits, tableCount, index, firstTable, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + base := uint32(0x05203000) + if tableCount == 2 { + base = 0x05202800 + } + return base | size<<22 | uint32(index)<<16 | uint32(firstTable)<<5 | uint32(destination) +} + +func TestTranslateARM64SVETableCompleteGo127Forms(t *testing.T) { + const named = ` +TEXT svetblnamed(SB),$0-0 + ZTBL Z31.B, [Z0.B], Z1.B + ZTBL Z30.H, [Z2.H], Z3.H + ZTBL Z29.S, [Z4.S], Z5.S + ZTBL Z28.D, [Z6.D], Z7.D + ZTBL Z27.B, [Z8.B, Z9.B], Z10.B + ZTBL Z26.H, [Z11.H, Z12.H], Z13.H + ZTBL Z25.S, [Z14.S, Z15.S], Z16.S + ZTBL Z24.D, [Z30.D, Z31.D], Z17.D + RET +` + requireARM64SVEGoAssemblerResult(t, named, true) + + var raw strings.Builder + raw.WriteString("TEXT svetblraw(SB),$0-0\n") + for _, elementBits := range []int{8, 16, 32, 64} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVETable(elementBits, 1, 1, 2, 3)) + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVETable(elementBits, 2, 4, 31, 5)) + } + raw.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, raw.String(), true) + + for name, source := range map[string]string{"named": named, "raw": raw.String()} { + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "svetbl" + name + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2"`, "@llvm.aarch64.sve.tbl.nxv", "@llvm.aarch64.sve.tbl2.nxv"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 SVE TBL lowering for %s/%s omitted %q:\n%s", name, triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-table.ll", "arm64-sve-table.o", ll) + }) + } + }) + } +} + +func TestARM64RawSVETableDecoderCoversEveryEncodingField(t *testing.T) { + for _, elementBits := range []int{8, 16, 32, 64} { + for _, tableCount := range []int{1, 2} { + for index := 0; index < 32; index++ { + for firstTable := 0; firstTable < 32; firstTable++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVETable(elementBits, tableCount, index, firstTable, destination) + got, ok := decodeARM64RawSVETable(word) + if !ok || got.elementBits != elementBits || got.tableCount != tableCount || got.index != index || got.firstTable != firstTable || got.destination != destination { + t.Fatalf("decoded SVE TBL %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } + } +} + +func TestARM64SVETableRejectsAdjacentAndGoRejectsWrappingNamedPair(t *testing.T) { + for _, word := range []uint32{0x05202c00, 0x05202000, 0x05203800} { + if _, ok := decodeARM64RawSVETable(word); ok { + t.Fatalf("SVE TBL decoder accepted adjacent encoding %#08x", word) + } + } + const invalid = ` +TEXT badsvetbl(SB),$0-0 + ZTBL Z0.B, [Z31.B, Z0.B], Z1.B + RET +` + requireARM64SVEGoAssemblerResult(t, invalid, false) + file, err := Parse(ArchARM64, invalid) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvetbl": {Name: "badsvetbl", Ret: Void}}}); err == nil { + t.Fatal("translator accepted the wrapping named SVE TBL pair rejected by Go 1.27") + } + + // The machine encoding and LLVM accept the architectural Z31,Z0 wrap even + // though Go's named reglist encoder rejects it. + if got, ok := decodeARM64RawSVETable(encodeARM64RawSVETable(8, 2, 0, 31, 1)); !ok || got.firstTable != 31 { + t.Fatalf("raw SVE TBL pair wrap was not preserved: %+v, ok=%v", got, ok) + } +} diff --git a/arm64_lower_sve_ternary_bitwise.go b/arm64_lower_sve_ternary_bitwise.go new file mode 100644 index 00000000..bd0fcf71 --- /dev/null +++ b/arm64_lower_sve_ternary_bitwise.go @@ -0,0 +1,47 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVETernaryBitwiseIntrinsics = map[Op]string{ + "ZBCAX": "bcax", + "ZBSL": "bsl", + "ZBSL1N": "bsl1n", + "ZBSL2N": "bsl2n", + "ZEOR3": "eor3", + "ZNBSL": "nbsl", +} + +func (c *arm64Ctx) lowerARM64SVETernaryBitwise(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVETernaryBitwiseIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 { + return true, false, fmt.Errorf("arm64 %s expects Zk.D, Zm.D, Zdn.D, Zdn.D without a suffix: %q", op, ins.Raw) + } + third, thirdBits, thirdOK := arm64ParseSVEZElementReg(ins.Args[0]) + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[1]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[2]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !thirdOK || !secondOK || !firstOK || !destinationOK || thirdBits != 64 || secondBits != 64 || firstBits != 64 || destinationBits != 64 || first != destination { + return true, false, fmt.Errorf("arm64 %s requires D-width operands and one destructive destination: %q", op, ins.Raw) + } + firstValue, vectorType, err := c.loadZRegElements(first, 64) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, 64) + if err != nil { + return true, false, err + } + thirdValue, _, err := c.loadZRegElements(third, 64) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv2i64(%s %s, %s %s, %s %s)\n", result, vectorType, intrinsic, vectorType, firstValue, vectorType, secondValue, vectorType, thirdValue) + return true, false, c.storeZRegElements(destination, 64, "%"+result) +} diff --git a/arm64_lower_sve_ternary_bitwise_test.go b/arm64_lower_sve_ternary_bitwise_test.go new file mode 100644 index 00000000..9b717986 --- /dev/null +++ b/arm64_lower_sve_ternary_bitwise_test.go @@ -0,0 +1,74 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVETernaryBitwiseCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveternarybitwiseforms(SB),$0-0\n") + for _, op := range []string{"ZBCAX", "ZBSL", "ZBSL1N", "ZBSL2N", "ZEOR3", "ZNBSL"} { + source.WriteString("\t" + op + " Z1.D, Z2.D, Z3.D, Z3.D\n") + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVETernaryBitwiseCompleteGo127Family(t *testing.T) { + source := arm64SVETernaryBitwiseCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveternarybitwiseforms": {Name: "sveternarybitwiseforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.bcax.nxv2i64", + "@llvm.aarch64.sve.bsl.nxv2i64", + "@llvm.aarch64.sve.bsl1n.nxv2i64", + "@llvm.aarch64.sve.bsl2n.nxv2i64", + "@llvm.aarch64.sve.eor3.nxv2i64", + "@llvm.aarch64.sve.nbsl.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE ternary-bitwise lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-ternary-bitwise.ll", "arm64-sve-ternary-bitwise.o", ll) + }) + } +} + +func TestTranslateARM64SVETernaryBitwiseRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZBCAX Z1.S, Z2.S, Z3.S, Z3.S", + "ZBSL Z1.D, Z2.S, Z3.D, Z3.D", + "ZBSL1N Z1.D, Z2.D, Z3.D, Z4.D", + "ZBSL2N Z1.D, Z2.D, Z3.D", + "ZEOR3 Z1.Q, Z2.Q, Z3.Q, Z3.Q", + "ZNBSL.Z Z1.D, Z2.D, Z3.D, Z3.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveternarybitwise(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveternarybitwise": {Name: "badsveternarybitwise", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE ternary-bitwise forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_umullb.go b/arm64_lower_sve_umullb.go new file mode 100644 index 00000000..1d84ce15 --- /dev/null +++ b/arm64_lower_sve_umullb.go @@ -0,0 +1,187 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +type arm64SVEUMULLBMode uint8 + +const ( + arm64SVEUMULLBVector arm64SVEUMULLBMode = iota + arm64SVEUMULLBLane +) + +type arm64RawSVEUMULLB struct { + op Op + mode arm64SVEUMULLBMode + sourceBits int + first int + second int + laneVector int + lane int + destination int +} + +type arm64SVEMultiplyLongSpec struct { + intrinsic string + accumulate bool + vectorBase uint32 + laneHBase uint32 + laneSBase uint32 +} + +var arm64SVEMultiplyLongSpecs = map[Op]arm64SVEMultiplyLongSpec{ + "ZSMULLB": {intrinsic: "smullb", vectorBase: 0x45007000, laneHBase: 0x44a0c000, laneSBase: 0x44e0c000}, + "ZSMULLT": {intrinsic: "smullt", vectorBase: 0x45007400, laneHBase: 0x44a0c400, laneSBase: 0x44e0c400}, + "ZUMULLB": {intrinsic: "umullb", vectorBase: 0x45007800, laneHBase: 0x44a0d000, laneSBase: 0x44e0d000}, + "ZUMULLT": {intrinsic: "umullt", vectorBase: 0x45007c00, laneHBase: 0x44a0d400, laneSBase: 0x44e0d400}, + "ZSQDMULLB": {intrinsic: "sqdmullb", vectorBase: 0x45006000, laneHBase: 0x44a0e000, laneSBase: 0x44e0e000}, + "ZSQDMULLT": {intrinsic: "sqdmullt", vectorBase: 0x45006400, laneHBase: 0x44a0e400, laneSBase: 0x44e0e400}, + "ZSQDMLALB": {intrinsic: "sqdmlalb", accumulate: true, vectorBase: 0x44006000, laneHBase: 0x44a02000, laneSBase: 0x44e02000}, + "ZSQDMLALT": {intrinsic: "sqdmlalt", accumulate: true, vectorBase: 0x44006400, laneHBase: 0x44a02400, laneSBase: 0x44e02400}, + "ZSQDMLALBT": {intrinsic: "sqdmlalbt", accumulate: true, vectorBase: 0x44000800}, + "ZSQDMLSLB": {intrinsic: "sqdmlslb", accumulate: true, vectorBase: 0x44006800, laneHBase: 0x44a03000, laneSBase: 0x44e03000}, + "ZSQDMLSLT": {intrinsic: "sqdmlslt", accumulate: true, vectorBase: 0x44006c00, laneHBase: 0x44a03400, laneSBase: 0x44e03400}, + "ZSQDMLSLBT": {intrinsic: "sqdmlslbt", accumulate: true, vectorBase: 0x44000c00}, +} + +var arm64SVEMultiplyLongOps = [...]Op{ + "ZSMULLB", "ZSMULLT", "ZUMULLB", "ZUMULLT", + "ZSQDMULLB", "ZSQDMULLT", + "ZSQDMLALB", "ZSQDMLALT", "ZSQDMLALBT", + "ZSQDMLSLB", "ZSQDMLSLT", "ZSQDMLSLBT", +} + +func decodeARM64RawSVEUMULLB(word uint32) (arm64RawSVEUMULLB, bool) { + for _, op := range arm64SVEMultiplyLongOps { + spec := arm64SVEMultiplyLongSpecs[op] + form := arm64RawSVEUMULLB{op: op} + switch { + case word&0xff20fc00 == spec.vectorBase: + size := int(word>>22) & 3 + if size == 0 { + continue + } + form.mode = arm64SVEUMULLBVector + form.sourceBits = 4 << size + form.second = int(word>>16) & 31 + case spec.laneHBase != 0 && word&0xffe0f400 == spec.laneHBase: + form.mode = arm64SVEUMULLBLane + form.sourceBits = 16 + form.laneVector = int(word>>16) & 7 + form.lane = int(word>>11)&1 | (int(word>>19)&3)<<1 + case spec.laneSBase != 0 && word&0xffe0f400 == spec.laneSBase: + form.mode = arm64SVEUMULLBLane + form.sourceBits = 32 + form.laneVector = int(word>>16) & 15 + form.lane = int(word>>11)&1 | (int(word>>20)&1)<<1 + default: + continue + } + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + return form, true + } + return arm64RawSVEUMULLB{}, false +} + +func arm64ParseSVEUMULLBIndexedReg(operand Operand) (index, elementBits, lane int, ok bool) { + if operand.Kind != OpReg { + return 0, 0, 0, false + } + name := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + dot := strings.IndexByte(name, '.') + open := strings.IndexByte(name, '[') + if dot <= 1 || open <= dot+1 || !strings.HasSuffix(name, "]") || !strings.HasPrefix(name, "Z") { + return 0, 0, 0, false + } + index, err := strconv.Atoi(name[1:dot]) + if err != nil { + return 0, 0, 0, false + } + elementBits, bitsOK := map[string]int{"H": 16, "S": 32}[name[dot+1:open]] + lane, err = strconv.Atoi(name[open+1 : len(name)-1]) + if err != nil || !bitsOK { + return 0, 0, 0, false + } + maxVector := map[int]int{16: 7, 32: 15}[elementBits] + maxLane := map[int]int{16: 7, 32: 3}[elementBits] + return index, elementBits, lane, index >= 0 && index <= maxVector && lane >= 0 && lane <= maxLane +} + +func (c *arm64Ctx) lowerARM64SVEUMULLB(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEMultiplyLongSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects one of its Go 1.27 SVE2 multiply-long forms: %q", op, ins.Raw) + } + form := arm64RawSVEUMULLB{op: op} + if laneVector, laneBits, lane, laneOK := arm64ParseSVEUMULLBIndexedReg(ins.Args[0]); laneOK { + if spec.laneHBase == 0 { + return true, false, fmt.Errorf("arm64 %s has no indexed Go 1.27 form: %q", op, ins.Raw) + } + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !firstOK || !destinationOK || firstBits != laneBits || destinationBits != 2*laneBits { + return true, false, fmt.Errorf("arm64 %s indexed operands must widen H to S or S to D: %q", op, ins.Raw) + } + form = arm64RawSVEUMULLB{op: op, mode: arm64SVEUMULLBLane, sourceBits: firstBits, first: first, laneVector: laneVector, lane: lane, destination: destination} + } else { + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK || secondBits != firstBits || firstBits == 64 || destinationBits != 2*firstBits { + return true, false, fmt.Errorf("arm64 %s vector operands must widen B/H/S to H/S/D: %q", op, ins.Raw) + } + form = arm64RawSVEUMULLB{op: op, mode: arm64SVEUMULLBVector, sourceBits: firstBits, first: first, second: second, destination: destination} + } + return true, false, c.lowerRawSVEUMULLB(form) +} + +func (c *arm64Ctx) lowerRawSVEUMULLB(form arm64RawSVEUMULLB) error { + spec, ok := arm64SVEMultiplyLongSpecs[form.op] + if !ok { + return fmt.Errorf("unsupported ARM64 SVE2 multiply-long operation %s", form.op) + } + first, sourceType, err := c.loadZRegElements(form.first, form.sourceBits) + if err != nil { + return err + } + secondIndex := form.second + if form.mode == arm64SVEUMULLBLane { + secondIndex = form.laneVector + } + second, _, err := c.loadZRegElements(secondIndex, form.sourceBits) + if err != nil { + return err + } + destinationBits := form.sourceBits * 2 + destinationType, destinationLanes, err := arm64SVEVectorType(destinationBits) + if err != nil { + return err + } + var accumulator string + if spec.accumulate { + accumulator, _, err = c.loadZRegElements(form.destination, destinationBits) + if err != nil { + return err + } + } + result := c.newTmp() + if spec.accumulate { + if form.mode == arm64SVEUMULLBVector { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, destinationType, spec.intrinsic, destinationLanes, destinationBits, destinationType, accumulator, sourceType, first, sourceType, second) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.lane.nxv%di%d(%s %s, %s %s, %s %s, i32 %d)\n", result, destinationType, spec.intrinsic, destinationLanes, destinationBits, destinationType, accumulator, sourceType, first, sourceType, second, form.lane) + } + } else if form.mode == arm64SVEUMULLBVector { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, destinationType, spec.intrinsic, destinationLanes, destinationBits, sourceType, first, sourceType, second) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.lane.nxv%di%d(%s %s, %s %s, i32 %d)\n", result, destinationType, spec.intrinsic, destinationLanes, destinationBits, sourceType, first, sourceType, second, form.lane) + } + return c.storeZRegElements(form.destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_umullb_test.go b/arm64_lower_sve_umullb_test.go new file mode 100644 index 00000000..87d134de --- /dev/null +++ b/arm64_lower_sve_umullb_test.go @@ -0,0 +1,124 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64RawSVEUMULLBVector(sourceBits, second, first, destination int) uint32 { + size := map[int]uint32{8: 1, 16: 2, 32: 3}[sourceBits] + return 0x45007800 | size<<22 | uint32(second)<<16 | uint32(first)<<5 | uint32(destination) +} + +func encodeARM64RawSVEUMULLBLane(sourceBits, laneVector, lane, first, destination int) uint32 { + base := uint32(0x44a0d000) + if sourceBits == 16 { + return base | uint32(laneVector)<<16 | uint32(lane&1)<<11 | uint32(lane>>1)<<19 | uint32(first)<<5 | uint32(destination) + } + return 0x44e0d000 | uint32(laneVector)<<16 | uint32(lane&1)<<11 | uint32(lane>>1)<<20 | uint32(first)<<5 | uint32(destination) +} + +func TestTranslateARM64SVEUMULLBCompleteGo127Forms(t *testing.T) { + const named = ` +TEXT sveumullbnamed(SB),$0-0 + ZUMULLB Z31.B, Z30.B, Z29.H + ZUMULLB Z28.H, Z27.H, Z26.S + ZUMULLB Z25.S, Z24.S, Z23.D + ZUMULLB Z7.H[7], Z22.H, Z21.S + ZUMULLB Z15.S[3], Z20.S, Z19.D + RET +` + requireARM64SVEGoAssemblerResult(t, named, true) + + var raw strings.Builder + raw.WriteString("TEXT sveumullbraw(SB),$0-0\n") + for _, sourceBits := range []int{8, 16, 32} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEUMULLBVector(sourceBits, 1, 2, 3)) + } + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEUMULLBLane(16, 7, 7, 4, 5)) + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEUMULLBLane(32, 15, 3, 6, 7)) + raw.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, raw.String(), true) + + for name, source := range map[string]string{"named": named, "raw": raw.String()} { + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "sveumullb" + name + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve,+sve2"`, "@llvm.aarch64.sve.umullb.nxv", "@llvm.aarch64.sve.umullb.lane.nxv"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 SVE UMULLB lowering for %s/%s omitted %q:\n%s", name, triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-umullb.ll", "arm64-sve-umullb.o", ll) + }) + } + }) + } +} + +func TestARM64RawSVEUMULLBDecoderCoversEveryEncodingField(t *testing.T) { + for _, sourceBits := range []int{8, 16, 32} { + for second := 0; second < 32; second++ { + for first := 0; first < 32; first++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVEUMULLBVector(sourceBits, second, first, destination) + got, ok := decodeARM64RawSVEUMULLB(word) + if !ok || got.mode != arm64SVEUMULLBVector || got.sourceBits != sourceBits || got.second != second || got.first != first || got.destination != destination { + t.Fatalf("decoded vector SVE UMULLB %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } + for _, domain := range []struct{ bits, vectors, lanes int }{{16, 8, 8}, {32, 16, 4}} { + for laneVector := 0; laneVector < domain.vectors; laneVector++ { + for lane := 0; lane < domain.lanes; lane++ { + for first := 0; first < 32; first++ { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawSVEUMULLBLane(domain.bits, laneVector, lane, first, destination) + got, ok := decodeARM64RawSVEUMULLB(word) + if !ok || got.mode != arm64SVEUMULLBLane || got.sourceBits != domain.bits || got.laneVector != laneVector || got.lane != lane || got.first != first || got.destination != destination { + t.Fatalf("decoded lane SVE UMULLB %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } + } +} + +func TestARM64SVEUMULLBRejectsReservedAndAdjacentForms(t *testing.T) { + for _, word := range []uint32{0x45007800, 0x45007c00, 0x44a0f000, 0x44e0f000} { + if _, ok := decodeARM64RawSVEUMULLB(word); ok { + t.Fatalf("SVE UMULLB decoder accepted reserved/adjacent encoding %#08x", word) + } + } + const invalid = ` +TEXT badsveumullb(SB),$0-0 + ZUMULLB Z8.H[0], Z1.H, Z2.S + ZUMULLB Z1.S, Z2.S, Z3.S + RET +` + requireARM64SVEGoAssemblerResult(t, invalid, false) + file, err := Parse(ArchARM64, invalid) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveumullb": {Name: "badsveumullb", Ret: Void}}}); err == nil { + t.Fatal("translator accepted invalid SVE UMULLB forms") + } +} diff --git a/arm64_lower_sve_unpack.go b/arm64_lower_sve_unpack.go new file mode 100644 index 00000000..6326be40 --- /dev/null +++ b/arm64_lower_sve_unpack.go @@ -0,0 +1,40 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEUnpackIntrinsics = map[Op]string{ + "ZSUNPKHI": "sunpkhi", + "ZSUNPKLO": "sunpklo", + "ZUUNPKHI": "uunpkhi", + "ZUUNPKLO": "uunpklo", +} + +func (c *arm64Ctx) lowerARM64SVEUnpack(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, ok := arm64SVEUnpackIntrinsics[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects Zn.B|H|S, Zd.H|S|D without a suffix: %q", op, ins.Raw) + } + source, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[1]) + if !sourceOK || !destinationOK || (sourceBits != 8 && sourceBits != 16 && sourceBits != 32) || destinationBits != sourceBits*2 { + return true, false, fmt.Errorf("arm64 %s requires a B-to-H, H-to-S, or S-to-D widening pair: %q", op, ins.Raw) + } + sourceValue, sourceType, err := c.loadZRegElements(source, sourceBits) + if err != nil { + return true, false, err + } + destinationType, _, err := arm64SVEVectorType(destinationBits) + if err != nil { + return true, false, err + } + destinationLanes := 128 / destinationBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s)\n", result, destinationType, intrinsic, destinationLanes, destinationBits, sourceType, sourceValue) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_unpack_test.go b/arm64_lower_sve_unpack_test.go new file mode 100644 index 00000000..b4c1a929 --- /dev/null +++ b/arm64_lower_sve_unpack_test.go @@ -0,0 +1,74 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEUnpackCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT sveunpackforms(SB),$0-0\n") + for _, op := range []string{"ZSUNPKHI", "ZSUNPKLO", "ZUUNPKHI", "ZUUNPKLO"} { + for _, widths := range [][2]string{{"B", "H"}, {"H", "S"}, {"S", "D"}} { + source.WriteString("\t" + op + " Z1." + widths[0] + ", Z2." + widths[1] + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEUnpackCompleteGo127Family(t *testing.T) { + source := arm64SVEUnpackCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveunpackforms": {Name: "sveunpackforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.sunpkhi.nxv8i16", + "@llvm.aarch64.sve.sunpklo.nxv4i32", + "@llvm.aarch64.sve.uunpkhi.nxv2i64", + "@llvm.aarch64.sve.uunpklo.nxv8i16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE unpack lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-unpack.ll", "arm64-sve-unpack.o", ll) + }) + } +} + +func TestTranslateARM64SVEUnpackRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSUNPKHI Z1.B, Z2.B", + "ZSUNPKLO Z1.S, Z2.S", + "ZUUNPKHI Z1.H, Z2.D", + "ZUUNPKLO Z1.D, Z2.Q", + "ZSUNPKHI Z1.B", + "ZUUNPKLO.Z Z1.S, Z2.D", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsveunpack(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsveunpack": {Name: "badsveunpack", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE unpack forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_vector_predicate_incdec.go b/arm64_lower_sve_vector_predicate_incdec.go new file mode 100644 index 00000000..4f4af577 --- /dev/null +++ b/arm64_lower_sve_vector_predicate_incdec.go @@ -0,0 +1,72 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEVectorPredicateIncDecSpec struct { + intrinsic string + increment bool + saturating bool +} + +var arm64SVEVectorPredicateIncDecSpecs = map[Op]arm64SVEVectorPredicateIncDecSpec{ + "ZDECP": {}, + "ZINCP": {increment: true}, + "ZSQDECP": {intrinsic: "sqdecp", saturating: true}, + "ZSQINCP": {intrinsic: "sqincp", increment: true, saturating: true}, + "ZUQDECP": {intrinsic: "uqdecp", saturating: true}, + "ZUQINCP": {intrinsic: "uqincp", increment: true, saturating: true}, +} + +func (c *arm64Ctx) lowerARM64SVEVectorPredicateIncDec(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEVectorPredicateIncDecSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects Pm.H/S/D, Zdn.H/S/D without a suffix: %q", op, ins.Raw) + } + predicate, predicateBits, predicateOK := arm64ParseSVEPredicateElement(ins.Args[0]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[1]) + if !predicateOK || !destinationOK || predicateBits == 8 || predicateBits != destinationBits { + return true, false, fmt.Errorf("arm64 %s requires matching H/S/D predicate and vector arrangements: %q", op, ins.Raw) + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, predicateBits) + if err != nil { + return true, false, err + } + value, vectorType, err := c.loadZRegElements(destination, destinationBits) + if err != nil { + return true, false, err + } + lanes := 128 / destinationBits + result := c.newTmp() + if spec.saturating { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, vectorType, spec.intrinsic, lanes, destinationBits, vectorType, value, predicateType, predicateValue) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) + } + governing, _, err := c.allTruePRegElements(destinationBits) + if err != nil { + return true, false, err + } + count := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.aarch64.sve.cntp.nxv%di1(%s %s, %s %s)\n", count, lanes, predicateType, governing, predicateType, predicateValue) + countValue := "%" + count + if destinationBits != 64 { + narrowed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i%d\n", narrowed, countValue, destinationBits) + countValue = "%" + narrowed + } + inserted := c.newTmp() + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement %s poison, i%d %s, i64 0\n", inserted, vectorType, destinationBits, countValue) + fmt.Fprintf(c.b, " %%%s = shufflevector %s %%%s, %s poison, zeroinitializer\n", splat, vectorType, inserted, vectorType, lanes) + operation := "sub" + if spec.increment { + operation = "add" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s, %%%s\n", result, operation, vectorType, value, splat) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_vector_predicate_incdec_test.go b/arm64_lower_sve_vector_predicate_incdec_test.go new file mode 100644 index 00000000..e3e60030 --- /dev/null +++ b/arm64_lower_sve_vector_predicate_incdec_test.go @@ -0,0 +1,73 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEVectorPredicateIncDecCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svevectorpredicateincdec(SB),$0-0\n") + for opIndex, op := range []string{"ZDECP", "ZINCP", "ZSQDECP", "ZSQINCP", "ZUQDECP", "ZUQINCP"} { + for widthIndex, suffix := range []string{"H", "S", "D"} { + reg := (opIndex*3 + widthIndex) % 32 + fmt.Fprintf(&source, "\t%s P%d.%s, Z%d.%s\n", op, (opIndex+widthIndex)%16, suffix, reg, suffix) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svevectorpredicateincdec": {Name: "svevectorpredicateincdec", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "sub ", "add ", + "@llvm.aarch64.sve.sqdecp.nxv8i16", + "@llvm.aarch64.sve.sqincp.nxv8i16", + "@llvm.aarch64.sve.uqdecp.nxv4i32", + "@llvm.aarch64.sve.uqincp.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE vector predicate inc/dec lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-vector-predicate-incdec.ll", "arm64-sve-vector-predicate-incdec.o", ll) + }) + } +} + +func TestTranslateARM64SVEVectorPredicateIncDecRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZDECP P0.B, Z1.B", + "ZDECP P0.B, Z1.H", + "ZINCP P0, Z1.B", + "ZSQDECP P16.B, Z1.B", + "ZSQINCP P0.Q, Z1.Q", + "ZUQDECP P0.B, R1", + "ZUQINCP.Z P0.B, Z1.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvevectorpredicateincdec(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvevectorpredicateincdec": {Name: "badsvevectorpredicateincdec", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector predicate inc/dec forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_vector_prefetch.go b/arm64_lower_sve_vector_prefetch.go new file mode 100644 index 00000000..d415ac0d --- /dev/null +++ b/arm64_lower_sve_vector_prefetch.go @@ -0,0 +1,101 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +var arm64SVEVectorPrefetchBits = map[Op]int{ + "ZPRFB": 8, + "ZPRFH": 16, + "ZPRFW": 32, + "ZPRFD": 64, +} + +func (c *arm64Ctx) lowerARM64SVEVectorPrefetch(op Op, ins Instr) (ok bool, terminated bool, err error) { + elementBits, ok := arm64SVEVectorPrefetchBits[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[0].Kind != OpMem { + return true, false, fmt.Errorf("arm64 %s expects memory, Pg, prfop: %q", op, ins.Raw) + } + predicate, predicateOK := arm64ParseSVEPredicateBare(ins.Args[1], 7) + hint, hintOK := arm64SVEPrefetchHint(ins.Args[2]) + if !predicateOK || !hintOK { + return true, false, fmt.Errorf("arm64 %s requires P0..P7 and an SVE data prefetch operation: %q", op, ins.Raw) + } + memory := ins.Args[0].Mem + if memory.Index != "" { + return c.lowerARM64SVEVectorPrefetchScalarBase(op, elementBits, predicate, hint, memory, ins) + } + return c.lowerARM64SVEVectorPrefetchVectorBase(op, elementBits, predicate, hint, memory, ins) +} + +func (c *arm64Ctx) lowerARM64SVEVectorPrefetchScalarBase(op Op, elementBits, predicate, hint int, memory MemRef, ins Instr) (ok bool, terminated bool, err error) { + if memory.Sym != "" || memory.Segment != "" || memory.Off != 0 || memory.OffRaw != "" { + return true, false, fmt.Errorf("arm64 %s scalar-base vector-offset address has an invalid displacement: %q", op, ins.Raw) + } + baseReg, baseOK := arm64SVEPhysicalMemoryBase(memory.Base) + index, indexBits, indexOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Index}) + expectedScale := int64(elementBits / 8) + if !baseOK || !indexOK || (indexBits != 32 && indexBits != 64) || memory.Scale != expectedScale { + return true, false, fmt.Errorf("arm64 %s vector offset requires Zm.S/D and exact element shift: %q", op, ins.Raw) + } + extension := "" + if memory.IndexExt == "" { + if indexBits != 64 { + return true, false, fmt.Errorf("arm64 %s unextended vector offset requires Zm.D: %q", op, ins.Raw) + } + } else if memory.IndexExt == ExtendUXTW { + extension = "uxtw." + } else if memory.IndexExt == ExtendSXTW { + extension = "sxtw." + } else { + return true, false, fmt.Errorf("arm64 %s vector offset only accepts UXTW or SXTW: %q", op, ins.Raw) + } + base, err := c.loadReg(baseReg) + if err != nil { + return true, false, err + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, base) + indexValue, vectorType, err := c.loadZRegElements(index, indexBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, indexBits) + if err != nil { + return true, false, err + } + lanes := 128 / indexBits + letter := strings.ToLower(strings.TrimPrefix(string(op), "ZPRF")) + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.prf%s.gather.%sindex.nxv%di%d(%s %s, ptr %%%s, %s %s, i32 %d)\n", + letter, extension, lanes, indexBits, predicateType, predicateValue, pointer, vectorType, indexValue, hint) + return true, false, nil +} + +func (c *arm64Ctx) lowerARM64SVEVectorPrefetchVectorBase(op Op, elementBits, predicate, hint int, memory MemRef, ins Instr) (ok bool, terminated bool, err error) { + if memory.Sym != "" || memory.Segment != "" || memory.OffRaw != "" { + return true, false, fmt.Errorf("arm64 %s vector-base address only accepts an unsigned byte offset: %q", op, ins.Raw) + } + base, baseBits, baseOK := arm64ParseSVEZElementReg(Operand{Kind: OpReg, Reg: memory.Base}) + alignment := int64(elementBits / 8) + maximum := int64(31) * alignment + if !baseOK || (baseBits != 32 && baseBits != 64) || memory.Off < 0 || memory.Off > maximum || memory.Off%alignment != 0 { + return true, false, fmt.Errorf("arm64 %s vector-base offset must be aligned to %d and in [0,%d]: %q", op, alignment, maximum, ins.Raw) + } + baseValue, vectorType, err := c.loadZRegElements(base, baseBits) + if err != nil { + return true, false, err + } + predicateValue, predicateType, err := c.loadPRegElements(predicate, baseBits) + if err != nil { + return true, false, err + } + lanes := 128 / baseBits + letter := strings.ToLower(strings.TrimPrefix(string(op), "ZPRF")) + fmt.Fprintf(c.b, " call void @llvm.aarch64.sve.prf%s.gather.scalar.offset.nxv%di%d(%s %s, %s %s, i64 %d, i32 %d)\n", + letter, lanes, baseBits, predicateType, predicateValue, vectorType, baseValue, memory.Off, hint) + return true, false, nil +} diff --git a/arm64_lower_sve_vector_prefetch_test.go b/arm64_lower_sve_vector_prefetch_test.go new file mode 100644 index 00000000..042e828f --- /dev/null +++ b/arm64_lower_sve_vector_prefetch_test.go @@ -0,0 +1,116 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func arm64SVEVectorPrefetchCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svevectorprefetchforms(SB),$0-0\n") + for _, spec := range []struct { + op string + shift int + maximum int + }{ + {op: "ZPRFB", shift: 0, maximum: 31}, + {op: "ZPRFH", shift: 1, maximum: 62}, + {op: "ZPRFW", shift: 2, maximum: 124}, + {op: "ZPRFD", shift: 3, maximum: 248}, + } { + shift := "" + if spec.shift != 0 { + shift = fmt.Sprintf("<<%d", spec.shift) + } + fmt.Fprintf(&source, "\t%s (Z8.D%s)(RSP), P0, PLDL1KEEP\n", spec.op, shift) + for _, extension := range []string{"UXTW", "SXTW"} { + fmt.Fprintf(&source, "\t%s (Z6.D.%s%s)(R14), P1, PLDL1STRM\n", spec.op, extension, shift) + fmt.Fprintf(&source, "\t%s (Z7.S.%s%s)(R15), P2, PSTL1KEEP\n", spec.op, extension, shift) + } + fmt.Fprintf(&source, "\t%s (Z10.S), P3, PSTL2KEEP\n", spec.op) + fmt.Fprintf(&source, "\t%s %d(Z10.S), P4, PSTL2STRM\n", spec.op, spec.maximum) + fmt.Fprintf(&source, "\t%s (Z11.D), P5, PSTL3KEEP\n", spec.op) + fmt.Fprintf(&source, "\t%s %d(Z11.D), P7, PSTL3STRM\n", spec.op, spec.maximum) + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestParseARM64SVEVectorPrefetchRetainsAddressSemantics(t *testing.T) { + file, err := Parse(ArchARM64, "TEXT parsezprf(SB),$0-0\n\tZPRFB (Z6.S.SXTW)(R14), P2, PLDL1STRM\n\tZPRFD (Z8.D<<3)(RSP), P3, PSTL3KEEP\n\tRET\n") + if err != nil { + t.Fatal(err) + } + first := file.Funcs[0].Instrs[1].Args[0].Mem + if first.Base != Reg("R14") || first.Index != Reg("Z6.S") || first.IndexExt != ExtendSXTW || first.Scale != 1 { + t.Fatalf("extended Z prefetch address parsed as %+v", first) + } + second := file.Funcs[0].Instrs[2].Args[0].Mem + if second.Base != Reg("RSP") || second.Index != Reg("Z8.D") || second.IndexExt != "" || second.Scale != 8 { + t.Fatalf("shifted Z prefetch address parsed as %+v", second) + } +} + +func TestTranslateARM64SVEVectorPrefetchCompleteGo127Family(t *testing.T) { + source := arm64SVEVectorPrefetchCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svevectorprefetchforms": {Name: "svevectorprefetchforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.prfb.gather.index.nxv2i64", + "@llvm.aarch64.sve.prfh.gather.uxtw.index.nxv4i32", + "@llvm.aarch64.sve.prfw.gather.sxtw.index.nxv2i64", + "@llvm.aarch64.sve.prfd.gather.scalar.offset.nxv2i64", + "@llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE vector prefetch lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-vector-prefetch.ll", "arm64-sve-vector-prefetch.o", ll) + }) + } +} + +func TestTranslateARM64SVEVectorPrefetchRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZPRFB (Z1.D<<1)(R0), P0, PLDL1KEEP", + "ZPRFH (Z1.D)(R0), P0, PLDL1KEEP", + "ZPRFW (Z1.S.SXTW<<1)(R0), P0, PLDL1KEEP", + "ZPRFD (Z1.H.SXTW<<3)(R0), P0, PLDL1KEEP", + "ZPRFB 32(Z1.S), P0, PLDL1KEEP", + "ZPRFH 3(Z1.D), P0, PLDL1KEEP", + "ZPRFW 128(Z1.S), P0, PLDL1KEEP", + "ZPRFD 256(Z1.D), P0, PLDL1KEEP", + "ZPRFD 8(Z1.D), P8, PLDL1KEEP", + "ZPRFD 8(Z1.D), P0, PLIL1KEEP", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvevectorprefetch(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvevectorprefetch": {Name: "badsvevectorprefetch", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE vector prefetch forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_whole_vector_memory.go b/arm64_lower_sve_whole_vector_memory.go new file mode 100644 index 00000000..959655a0 --- /dev/null +++ b/arm64_lower_sve_whole_vector_memory.go @@ -0,0 +1,60 @@ +package plan9asm + +import ( + "fmt" + "strconv" + "strings" +) + +var arm64SVEWholeVectorMemoryOps = map[Op]bool{ + "ZLDR": true, + "ZSTR": false, +} + +func (c *arm64Ctx) lowerARM64SVEWholeVectorMemory(op Op, ins Instr) (ok bool, terminated bool, err error) { + load, ok := arm64SVEWholeVectorMemoryOps[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm64 %s expects its two-operand Go 1.27 form: %q", op, ins.Raw) + } + memoryOperand := 0 + vectorOperand := 1 + if !load { + vectorOperand, memoryOperand = memoryOperand, vectorOperand + } + vector, vectorOK := arm64ParseSVEBareZReg(ins.Args[vectorOperand]) + if !vectorOK || ins.Args[memoryOperand].Kind != OpMem { + return true, false, fmt.Errorf("arm64 %s requires a MUL VL address and bare Z0..Z31: %q", op, ins.Raw) + } + address, err := c.arm64SVEVLAddress(ins.Args[memoryOperand].Mem, -256, 255, 16) + if err != nil { + return true, false, fmt.Errorf("arm64 %s: %w: %q", op, err, ins.Raw) + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + if load { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load , ptr %%%s, align 1\n", value, pointer) + return true, false, c.storeZReg(vector, "%"+value) + } + value, err := c.loadZReg(vector) + if err != nil { + return true, false, err + } + fmt.Fprintf(c.b, " store %s, ptr %%%s, align 1\n", value, pointer) + return true, false, nil +} + +func arm64ParseSVEBareZReg(operand Operand) (int, bool) { + if operand.Kind != OpReg { + return 0, false + } + name := strings.ToUpper(strings.TrimSpace(string(operand.Reg))) + if strings.Contains(name, ".") || !strings.HasPrefix(name, "Z") { + return 0, false + } + index, err := strconv.Atoi(strings.TrimPrefix(name, "Z")) + return index, err == nil && index >= 0 && index <= 31 +} diff --git a/arm64_lower_sve_whole_vector_memory_test.go b/arm64_lower_sve_whole_vector_memory_test.go new file mode 100644 index 00000000..ea822ab2 --- /dev/null +++ b/arm64_lower_sve_whole_vector_memory_test.go @@ -0,0 +1,64 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEWholeVectorMemoryCompleteGo127Family(t *testing.T) { + const source = ` +TEXT svewholevectormemoryforms(SB),$0-0 + ZLDR (-VL*256)(R0), Z0 + ZLDR (VL*255)(RSP), Z31 + ZSTR Z30, (-VL*256)(R1) + ZSTR Z1, (VL*255)(ZR) + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svewholevectormemoryforms": {Name: "svewholevectormemoryforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"="+sve"`, "load ", "store ", "@llvm.vscale.i64()"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE whole-vector memory lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-whole-vector-memory.ll", "arm64-sve-whole-vector-memory.o", ll) + }) + } +} + +func TestTranslateARM64SVEWholeVectorMemoryRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZLDR (-VL*257)(R0), Z1", + "ZLDR (VL*256)(R0), Z1", + "ZLDR (VL*1)(R0), Z1.B", + "ZSTR Z1.B, (VL*1)(R0)", + "ZSTR Z32, (VL*1)(R0)", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvewholevectormemory(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvewholevectormemory": {Name: "badsvewholevectormemory", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE whole-vector memory forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_widening_add_sub.go b/arm64_lower_sve_widening_add_sub.go new file mode 100644 index 00000000..8ee129a1 --- /dev/null +++ b/arm64_lower_sve_widening_add_sub.go @@ -0,0 +1,123 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEWideningAddSubKind uint8 + +const ( + arm64SVEAddSubLong arm64SVEWideningAddSubKind = iota + arm64SVEAddSubWide + arm64SVEAddSubNarrowBottom + arm64SVEAddSubNarrowTop +) + +type arm64SVEWideningAddSubSpec struct { + intrinsic string + kind arm64SVEWideningAddSubKind +} + +var arm64SVEWideningAddSubSpecs = map[Op]arm64SVEWideningAddSubSpec{ + "ZADDHNB": {intrinsic: "addhnb", kind: arm64SVEAddSubNarrowBottom}, + "ZADDHNT": {intrinsic: "addhnt", kind: arm64SVEAddSubNarrowTop}, + "ZRADDHNB": {intrinsic: "raddhnb", kind: arm64SVEAddSubNarrowBottom}, + "ZRADDHNT": {intrinsic: "raddhnt", kind: arm64SVEAddSubNarrowTop}, + "ZSADDLB": {intrinsic: "saddlb", kind: arm64SVEAddSubLong}, + "ZSADDLBT": {intrinsic: "saddlbt", kind: arm64SVEAddSubLong}, + "ZSADDLT": {intrinsic: "saddlt", kind: arm64SVEAddSubLong}, + "ZSADDWB": {intrinsic: "saddwb", kind: arm64SVEAddSubWide}, + "ZSADDWT": {intrinsic: "saddwt", kind: arm64SVEAddSubWide}, + "ZSSUBLB": {intrinsic: "ssublb", kind: arm64SVEAddSubLong}, + "ZSSUBLBT": {intrinsic: "ssublbt", kind: arm64SVEAddSubLong}, + "ZSSUBLT": {intrinsic: "ssublt", kind: arm64SVEAddSubLong}, + "ZSSUBLTB": {intrinsic: "ssubltb", kind: arm64SVEAddSubLong}, + "ZSSUBWB": {intrinsic: "ssubwb", kind: arm64SVEAddSubWide}, + "ZSSUBWT": {intrinsic: "ssubwt", kind: arm64SVEAddSubWide}, + "ZSUBHNB": {intrinsic: "subhnb", kind: arm64SVEAddSubNarrowBottom}, + "ZSUBHNT": {intrinsic: "subhnt", kind: arm64SVEAddSubNarrowTop}, + "ZRSUBHNB": {intrinsic: "rsubhnb", kind: arm64SVEAddSubNarrowBottom}, + "ZRSUBHNT": {intrinsic: "rsubhnt", kind: arm64SVEAddSubNarrowTop}, + "ZUADDLB": {intrinsic: "uaddlb", kind: arm64SVEAddSubLong}, + "ZUADDLT": {intrinsic: "uaddlt", kind: arm64SVEAddSubLong}, + "ZUADDWB": {intrinsic: "uaddwb", kind: arm64SVEAddSubWide}, + "ZUADDWT": {intrinsic: "uaddwt", kind: arm64SVEAddSubWide}, + "ZUSUBLB": {intrinsic: "usublb", kind: arm64SVEAddSubLong}, + "ZUSUBLT": {intrinsic: "usublt", kind: arm64SVEAddSubLong}, + "ZUSUBWB": {intrinsic: "usubwb", kind: arm64SVEAddSubWide}, + "ZUSUBWT": {intrinsic: "usubwt", kind: arm64SVEAddSubWide}, +} + +type arm64SVEWideningAddSubForm struct { + sourceBits int + destinationBits int + first int + second int + destination int +} + +func (c *arm64Ctx) lowerARM64SVEWideningAddSub(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEWideningAddSubSpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects its three-register Go 1.27 SVE2 form without suffix: %q", op, ins.Raw) + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[0]) + first, firstBits, firstOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + if !secondOK || !firstOK || !destinationOK { + return true, false, fmt.Errorf("arm64 %s requires three scalable vector element registers: %q", op, ins.Raw) + } + form := arm64SVEWideningAddSubForm{first: first, second: second, destination: destination, destinationBits: destinationBits} + switch spec.kind { + case arm64SVEAddSubLong: + if secondBits != firstBits || firstBits == 64 || destinationBits != 2*firstBits { + return true, false, fmt.Errorf("arm64 %s requires matching B/H/S sources widened to H/S/D: %q", op, ins.Raw) + } + form.sourceBits = firstBits + case arm64SVEAddSubWide: + if secondBits == 64 || firstBits != 2*secondBits || destinationBits != firstBits { + return true, false, fmt.Errorf("arm64 %s requires a narrow B/H/S source plus matching H/S/D wide source and destination: %q", op, ins.Raw) + } + form.sourceBits = secondBits + case arm64SVEAddSubNarrowBottom, arm64SVEAddSubNarrowTop: + if secondBits != firstBits || firstBits == 8 || destinationBits*2 != firstBits { + return true, false, fmt.Errorf("arm64 %s requires matching H/S/D sources narrowed to B/H/S: %q", op, ins.Raw) + } + form.sourceBits = firstBits + default: + return true, false, fmt.Errorf("arm64 %s has an unknown widening/narrowing form", op) + } + return true, false, c.lowerARM64SVEWideningAddSubForm(spec, form) +} + +func (c *arm64Ctx) lowerARM64SVEWideningAddSubForm(spec arm64SVEWideningAddSubSpec, form arm64SVEWideningAddSubForm) error { + first, firstType, err := c.loadZRegElements(form.first, map[arm64SVEWideningAddSubKind]int{arm64SVEAddSubLong: form.sourceBits, arm64SVEAddSubWide: form.destinationBits, arm64SVEAddSubNarrowBottom: form.sourceBits, arm64SVEAddSubNarrowTop: form.sourceBits}[spec.kind]) + if err != nil { + return err + } + second, secondType, err := c.loadZRegElements(form.second, form.sourceBits) + if err != nil { + return err + } + destinationType, destinationLanes, err := arm64SVEVectorType(form.destinationBits) + if err != nil { + return err + } + result := c.newTmp() + if spec.kind == arm64SVEAddSubNarrowTop { + merged, _, err := c.loadZRegElements(form.destination, form.destinationBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s, %s %s)\n", result, destinationType, spec.intrinsic, 128/form.sourceBits, form.sourceBits, destinationType, merged, firstType, first, secondType, second) + } else if spec.kind == arm64SVEAddSubNarrowBottom { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, destinationType, spec.intrinsic, 128/form.sourceBits, form.sourceBits, firstType, first, secondType, second) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv%di%d(%s %s, %s %s)\n", result, destinationType, spec.intrinsic, destinationLanes, form.destinationBits, firstType, first, secondType, second) + } + return c.storeZRegElements(form.destination, form.destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_widening_add_sub_test.go b/arm64_lower_sve_widening_add_sub_test.go new file mode 100644 index 00000000..e3ac49fe --- /dev/null +++ b/arm64_lower_sve_widening_add_sub_test.go @@ -0,0 +1,112 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func arm64SVEWideningAddSubCompleteForms() string { + var source strings.Builder + source.WriteString("TEXT svewidenaddsubforms(SB),$0-0\n") + for _, op := range []string{ + "ZSADDLB", "ZSADDLBT", "ZSADDLT", + "ZSSUBLB", "ZSSUBLBT", "ZSSUBLT", "ZSSUBLTB", + "ZUADDLB", "ZUADDLT", "ZUSUBLB", "ZUSUBLT", + } { + for _, width := range []string{"B", "H", "S"} { + destinationWidth := map[string]string{"B": "H", "H": "S", "S": "D"}[width] + source.WriteString("\t" + op + " Z1." + width + ", Z2." + width + ", Z3." + destinationWidth + "\n") + } + } + for _, op := range []string{ + "ZSADDWB", "ZSADDWT", "ZSSUBWB", "ZSSUBWT", + "ZUADDWB", "ZUADDWT", "ZUSUBWB", "ZUSUBWT", + } { + for _, narrowWidth := range []string{"B", "H", "S"} { + wideWidth := map[string]string{"B": "H", "H": "S", "S": "D"}[narrowWidth] + source.WriteString("\t" + op + " Z4." + narrowWidth + ", Z5." + wideWidth + ", Z6." + wideWidth + "\n") + } + } + for _, op := range []string{ + "ZADDHNB", "ZADDHNT", "ZRADDHNB", "ZRADDHNT", + "ZSUBHNB", "ZSUBHNT", "ZRSUBHNB", "ZRSUBHNT", + } { + for _, wideWidth := range []string{"H", "S", "D"} { + narrowWidth := map[string]string{"H": "B", "S": "H", "D": "S"}[wideWidth] + source.WriteString("\t" + op + " Z7." + wideWidth + ", Z8." + wideWidth + ", Z9." + narrowWidth + "\n") + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64SVEWideningAddSubCompleteGo127Family(t *testing.T) { + source := arm64SVEWideningAddSubCompleteForms() + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svewidenaddsubforms": {Name: "svewidenaddsubforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.saddlb.nxv8i16", + "@llvm.aarch64.sve.saddlbt.nxv4i32", + "@llvm.aarch64.sve.ssubltb.nxv2i64", + "@llvm.aarch64.sve.uaddlt.nxv8i16", + "@llvm.aarch64.sve.usublt.nxv2i64", + "@llvm.aarch64.sve.saddwb.nxv8i16", + "@llvm.aarch64.sve.usubwt.nxv2i64", + "@llvm.aarch64.sve.addhnb.nxv8i16", + "@llvm.aarch64.sve.raddhnt.nxv4i32", + "@llvm.aarch64.sve.rsubhnb.nxv2i64", + "@llvm.aarch64.sve.subhnt.nxv8i16", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE widening/narrowing add/sub lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-widening-add-sub.ll", "arm64-sve-widening-add-sub.o", ll) + }) + } +} + +func TestTranslateARM64SVEWideningAddSubRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZSADDLB Z1.B, Z2.H, Z3.H", + "ZSADDLT Z1.B, Z2.B, Z3.S", + "ZUADDLB Z1.D, Z2.D, Z3.D", + "ZSSUBLBT Z1.H, Z2.H, Z3.H", + "ZSSUBLTB Z1.S, Z2.H, Z3.D", + "ZSADDWB Z1.B, Z2.B, Z3.H", + "ZUADDWT Z1.S, Z2.S, Z3.D", + "ZSSUBWB Z1.D, Z2.D, Z3.D", + "ZUSUBWT Z1.H, Z2.S, Z3.H", + "ZADDHNB Z1.B, Z2.B, Z3.B", + "ZRADDHNT Z1.S, Z2.S, Z3.S", + "ZSUBHNB Z1.D, Z2.S, Z3.S", + "ZRSUBHNT Z1.D, Z2.D, Z3.H", + "ZSADDLB.Z Z1.B, Z2.B, Z3.H", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvewidenaddsub(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvewidenaddsub": {Name: "badsvewidenaddsub", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's SVE widening/narrowing add/sub forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_widening_float_mla.go b/arm64_lower_sve_widening_float_mla.go new file mode 100644 index 00000000..3f633b28 --- /dev/null +++ b/arm64_lower_sve_widening_float_mla.go @@ -0,0 +1,119 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64SVEWideningFloatMLASpec struct { + intrinsic string + fp16 bool + fp8ToHalf bool + fp8ToWord bool +} + +var arm64SVEWideningFloatMLASpecs = map[Op]arm64SVEWideningFloatMLASpec{ + "ZFMLALB": {intrinsic: "fmlalb", fp16: true, fp8ToHalf: true}, + "ZFMLALT": {intrinsic: "fmlalt", fp16: true, fp8ToHalf: true}, + "ZFMLSLB": {intrinsic: "fmlslb", fp16: true}, + "ZFMLSLT": {intrinsic: "fmlslt", fp16: true}, + "ZFMLALLBB": {intrinsic: "fmlallbb", fp8ToWord: true}, + "ZFMLALLBT": {intrinsic: "fmlallbt", fp8ToWord: true}, + "ZFMLALLTB": {intrinsic: "fmlalltb", fp8ToWord: true}, + "ZFMLALLTT": {intrinsic: "fmlalltt", fp8ToWord: true}, +} + +type arm64SVEWideningFloatMLAForm struct { + intrinsic string + first, second, destination int + sourceBits, destinationBits int + lane int + indexed bool +} + +func (c *arm64Ctx) lowerARM64SVEWideningFloatMLA(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, ok := arm64SVEWideningFloatMLASpecs[op] + if !ok { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects one complete Go 1.27 vector or indexed widening floating multiply-accumulate form without a suffix: %q", op, ins.Raw) + } + form := arm64SVEWideningFloatMLAForm{intrinsic: spec.intrinsic} + if first, sourceBits, firstOK := arm64ParseSVEZElementReg(ins.Args[0]); firstOK { + form.first, form.sourceBits = first, sourceBits + } else { + first, sourceBits, lane, firstOK := arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[0]) + if !firstOK || first > 7 { + return true, false, fmt.Errorf("arm64 %s indexed source must use Z0..Z7: %q", op, ins.Raw) + } + form.first, form.sourceBits, form.lane, form.indexed = first, sourceBits, lane, true + } + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64SVEFloatElementReg(ins.Args[2]) + validWidth := form.sourceBits == 16 && destinationBits == 32 && spec.fp16 || + form.sourceBits == 8 && destinationBits == 16 && spec.fp8ToHalf || + form.sourceBits == 8 && destinationBits == 32 && spec.fp8ToWord + if !secondOK || !destinationOK || secondBits != form.sourceBits || !validWidth { + return true, false, fmt.Errorf("arm64 %s source/destination widths are outside its complete Go 1.27 forms: %q", op, ins.Raw) + } + if form.indexed { + maxLane := map[int]int{8: 15, 16: 7}[form.sourceBits] + if form.lane > maxLane { + return true, false, fmt.Errorf("arm64 %s indexed lane exceeds the Go 1.27 range for its source width: %q", op, ins.Raw) + } + } + form.second, form.destination, form.destinationBits = second, destination, destinationBits + return true, false, c.lowerARM64SVEWideningFloatMLAForm(form) +} + +func (c *arm64Ctx) lowerARM64SVEWideningFloatMLAForm(form arm64SVEWideningFloatMLAForm) error { + accumulator, accumulatorType, err := c.loadRawSVEFloatVector(form.destination, form.destinationBits) + if err != nil { + return err + } + result := c.newTmp() + lanes := 128 / form.destinationBits + mangle := map[int]string{16: "f16", 32: "f32"}[form.destinationBits] + if form.sourceBits == 8 { + first, err := c.loadZReg(form.first) + if err != nil { + return err + } + second, err := c.loadZReg(form.second) + if err != nil { + return err + } + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fp8.%s.lane.nxv%d%s(%s %s, %s, %s, i32 %d)\n", result, accumulatorType, form.intrinsic, lanes, mangle, accumulatorType, accumulator, second, first, form.lane) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.fp8.%s.nxv%d%s(%s %s, %s, %s)\n", result, accumulatorType, form.intrinsic, lanes, mangle, accumulatorType, accumulator, second, first) + } + } else { + first, sourceType, err := c.loadRawSVEFloatVector(form.first, 16) + if err != nil { + return err + } + second, _, err := c.loadRawSVEFloatVector(form.second, 16) + if err != nil { + return err + } + if form.indexed { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.lane.nxv4f32(%s %s, %s %s, %s %s, i32 %d)\n", result, accumulatorType, form.intrinsic, accumulatorType, accumulator, sourceType, second, sourceType, first, form.lane) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.%s.nxv4f32(%s %s, %s %s, %s %s)\n", result, accumulatorType, form.intrinsic, accumulatorType, accumulator, sourceType, second, sourceType, first) + } + } + return c.storeRawSVEFloatVector(form.destination, form.destinationBits, "%"+result, accumulatorType) +} + +func arm64SVEWideningFloatMLAFeatureClass(ins Instr) (sourceBits int, ok bool) { + if len(ins.Args) != 3 { + return 0, false + } + _, sourceBits, sourceOK := arm64ParseSVEZElementReg(ins.Args[0]) + if !sourceOK { + _, sourceBits, _, sourceOK = arm64ParseSVEZIndexedElementRegUnbounded(ins.Args[0]) + } + return sourceBits, sourceOK +} diff --git a/arm64_lower_sve_widening_float_mla_test.go b/arm64_lower_sve_widening_float_mla_test.go new file mode 100644 index 00000000..efe3c4fe --- /dev/null +++ b/arm64_lower_sve_widening_float_mla_test.go @@ -0,0 +1,111 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64SVEWideningFloatMLACompleteGo127Family(t *testing.T) { + const source = `TEXT svefmlhalf(SB),$0-0 + ZFMLALB Z0.H, Z1.H, Z2.S + ZFMLALB Z7.H[7], Z3.H, Z4.S + ZFMLALT Z5.H, Z6.H, Z7.S + ZFMLALT Z0.H[0], Z8.H, Z9.S + ZFMLSLB Z10.H, Z11.H, Z12.S + ZFMLSLB Z7.H[7], Z13.H, Z14.S + ZFMLSLT Z15.H, Z16.H, Z17.S + ZFMLSLT Z0.H[0], Z18.H, Z19.S + RET +TEXT svefmlfp8(SB),$0-0 + ZFMLALB Z20.B, Z21.B, Z22.H + ZFMLALB Z7.B[15], Z23.B, Z24.H + ZFMLALT Z25.B, Z26.B, Z27.H + ZFMLALT Z0.B[0], Z28.B, Z29.H + ZFMLALLBB Z1.B, Z2.B, Z3.S + ZFMLALLBB Z7.B[15], Z4.B, Z5.S + ZFMLALLBT Z6.B, Z7.B, Z8.S + ZFMLALLBT Z0.B[0], Z9.B, Z10.S + ZFMLALLTB Z11.B, Z12.B, Z13.S + ZFMLALLTB Z7.B[15], Z14.B, Z15.S + ZFMLALLTT Z16.B, Z17.B, Z18.S + ZFMLALLTT Z0.B[0], Z19.B, Z20.S + RET +` + requireARM64SVEGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{ + "svefmlhalf": {Name: "svefmlhalf", Ret: Void}, + "svefmlfp8": {Name: "svefmlfp8", Ret: Void}, + }}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + `"target-features"="+fp8,+ssve-fp8fma,+sve,+sve2,+sve2p2"`, + "@llvm.aarch64.sve.fmlalb.nxv4f32", + "@llvm.aarch64.sve.fmlalb.lane.nxv4f32", + "@llvm.aarch64.sve.fmlalt.nxv4f32", + "@llvm.aarch64.sve.fmlalt.lane.nxv4f32", + "@llvm.aarch64.sve.fmlslb.nxv4f32", + "@llvm.aarch64.sve.fmlslb.lane.nxv4f32", + "@llvm.aarch64.sve.fmlslt.nxv4f32", + "@llvm.aarch64.sve.fmlslt.lane.nxv4f32", + "@llvm.aarch64.sve.fp8.fmlalb.nxv8f16", + "@llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16", + "@llvm.aarch64.sve.fp8.fmlalt.nxv8f16", + "@llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16", + "@llvm.aarch64.sve.fp8.fmlallbb.nxv4f32", + "@llvm.aarch64.sve.fp8.fmlallbb.lane.nxv4f32", + "@llvm.aarch64.sve.fp8.fmlallbt.nxv4f32", + "@llvm.aarch64.sve.fp8.fmlallbt.lane.nxv4f32", + "@llvm.aarch64.sve.fp8.fmlalltb.nxv4f32", + "@llvm.aarch64.sve.fp8.fmlalltb.lane.nxv4f32", + "@llvm.aarch64.sve.fp8.fmlalltt.nxv4f32", + "@llvm.aarch64.sve.fp8.fmlalltt.lane.nxv4f32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s widening floating MLA lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-widening-fml.ll", "arm64-sve-widening-fml.o", ll) + }) + } +} + +func TestTranslateARM64SVEWideningFloatMLARejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZFMLALB Z8.H[0], Z2.H, Z3.S", + "ZFMLALT Z7.H[8], Z2.H, Z3.S", + "ZFMLSLB Z1.B, Z2.B, Z3.H", + "ZFMLSLT Z1.H, Z2.H, Z3.H", + "ZFMLALB Z8.B[0], Z2.B, Z3.H", + "ZFMLALT Z7.B[16], Z2.B, Z3.H", + "ZFMLALLBB Z8.B[0], Z2.B, Z3.S", + "ZFMLALLBT Z7.B[16], Z2.B, Z3.S", + "ZFMLALLTB Z1.B, Z2.H, Z3.S", + "ZFMLALLTT Z1.B, Z2.B, Z3.H", + "ZFMLALB.Z Z1.H, Z2.H, Z3.S", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvefml(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvefml": {Name: "badsvefml", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's widening floating MLA forms", instruction) + } + }) + } +} diff --git a/arm64_lower_sve_xar.go b/arm64_lower_sve_xar.go new file mode 100644 index 00000000..3476a2ed --- /dev/null +++ b/arm64_lower_sve_xar.go @@ -0,0 +1,34 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64SVEXAR(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "ZXAR" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 4 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 ZXAR expects $shift, Zm.T, Zdn.T, Zdn.T without a suffix: %q", ins.Raw) + } + shift := ins.Args[0].Imm + second, secondBits, secondOK := arm64ParseSVEZElementReg(ins.Args[1]) + destination, destinationBits, destinationOK := arm64ParseSVEZElementReg(ins.Args[2]) + repeatedDestination, repeatedBits, repeatedOK := arm64ParseSVEZElementReg(ins.Args[3]) + if !secondOK || !destinationOK || !repeatedOK || secondBits != destinationBits || repeatedBits != destinationBits || repeatedDestination != destination || shift < 1 || shift >= int64(destinationBits) { + return true, false, fmt.Errorf("arm64 ZXAR requires matching destructive B/H/S/D operands and shift $1..$elementBits-1: %q", ins.Raw) + } + destinationValue, vectorType, err := c.loadZRegElements(destination, destinationBits) + if err != nil { + return true, false, err + } + secondValue, _, err := c.loadZRegElements(second, secondBits) + if err != nil { + return true, false, err + } + lanes := 128 / destinationBits + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.xar.nxv%di%d(%s %s, %s %s, i32 %d)\n", result, vectorType, lanes, destinationBits, vectorType, destinationValue, vectorType, secondValue, shift) + return true, false, c.storeZRegElements(destination, destinationBits, "%"+result) +} diff --git a/arm64_lower_sve_xar_test.go b/arm64_lower_sve_xar_test.go new file mode 100644 index 00000000..85077ab0 --- /dev/null +++ b/arm64_lower_sve_xar_test.go @@ -0,0 +1,76 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64SVEXARCompleteGo127Family(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT svexar(SB),$0-0\n") + for widthIndex, width := range []struct { + suffix string + bits int + }{{"B", 8}, {"H", 16}, {"S", 32}, {"D", 64}} { + for boundaryIndex, shift := range []int{1, width.bits - 1} { + destination := widthIndex*2 + boundaryIndex + fmt.Fprintf(&source, "\tZXAR $%d, Z%d.%s, Z%d.%s, Z%d.%s\n", shift, destination+1, width.suffix, destination, width.suffix, destination, width.suffix) + } + } + source.WriteString("\tRET\n") + requireARM64SVEGoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"svexar": {Name: "svexar", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve,+sve2"`, + "@llvm.aarch64.sve.xar.nxv16i8", + "@llvm.aarch64.sve.xar.nxv8i16", + "@llvm.aarch64.sve.xar.nxv4i32", + "@llvm.aarch64.sve.xar.nxv2i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("%s SVE XAR lowering omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-xar.ll", "arm64-sve-xar.o", ll) + }) + } +} + +func TestTranslateARM64SVEXARRejectsFormsOutsideGo127Table(t *testing.T) { + for _, instruction := range []string{ + "ZXAR $0, Z1.B, Z2.B, Z2.B", + "ZXAR $8, Z1.B, Z2.B, Z2.B", + "ZXAR $16, Z1.H, Z2.H, Z2.H", + "ZXAR $32, Z1.S, Z2.S, Z2.S", + "ZXAR $64, Z1.D, Z2.D, Z2.D", + "ZXAR $1, Z1.H, Z2.S, Z2.S", + "ZXAR $1, Z1.D, Z2.D, Z3.D", + "ZXAR.Z $1, Z1.B, Z2.B, Z2.B", + } { + t.Run(strings.NewReplacer(" ", "_", ".", "_", ",", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badsvexar(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64SVEGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badsvexar": {Name: "badsvexar", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's XAR forms", instruction) + } + }) + } +} diff --git a/arm64_lower_table_lookup.go b/arm64_lower_table_lookup.go new file mode 100644 index 00000000..21facb09 --- /dev/null +++ b/arm64_lower_table_lookup.go @@ -0,0 +1,93 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorTableLookup(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VTBL" && op != "VTBX" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpRegList || ins.Args[2].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects Vindex.B8/B16, [Vtable...], Vdest.B8/B16 and no suffix: %q", op, ins.Raw) + } + indexArrangement, indexOK := parseARM64VectorArrangement(ins.Args[0].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[2].Reg) + byteVector := func(a arm64VectorArrangement) bool { + return a.elementBits == 8 && (a.lanes == 8 || a.lanes == 16) + } + if !indexOK || !destinationOK || indexArrangement != destinationArrangement || !byteVector(indexArrangement) { + return true, false, fmt.Errorf("arm64 %s requires matching B8 or B16 index and destination arrangements: %q", op, ins.Raw) + } + tables := ins.Args[1].RegList + if len(tables) < 1 || len(tables) > 4 { + return true, false, fmt.Errorf("arm64 %s requires one through four table registers: %q", op, ins.Raw) + } + firstTableArrangement, firstArrangementOK := parseARM64VectorArrangement(tables[0]) + firstTable, firstTableOK := arm64ParseVReg(tables[0]) + if !firstArrangementOK || !firstTableOK { + return true, false, fmt.Errorf("arm64 %s requires arranged table registers: %q", op, ins.Raw) + } + for i, table := range tables { + arrangement, arrangementOK := parseARM64VectorArrangement(table) + register, registerOK := arm64ParseVReg(table) + if !arrangementOK || arrangement != firstTableArrangement || !registerOK || register != (firstTable+i)%32 { + return true, false, fmt.Errorf("arm64 %s requires consecutive table registers with a consistent arrangement: %q", op, ins.Raw) + } + } + + index, err := c.loadARM64VectorInteger(ins.Args[0].Reg, indexArrangement) + if err != nil { + return true, false, err + } + tableBytes := len(tables) * 16 + tableType := fmt.Sprintf("<%d x i8>", tableBytes) + tableVector := "poison" + for tableIndex := range tables { + register := Reg(fmt.Sprintf("V%d.B16", (firstTable+tableIndex)%32)) + loaded, err := c.loadARM64VectorInteger(register, arm64VectorArrangement{elementBits: 8, lanes: 16}) + if err != nil { + return true, false, err + } + for lane := 0; lane < 16; lane++ { + element := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <16 x i8> %s, i32 %d\n", element, loaded, lane) + fmt.Fprintf(c.b, " %%%s = insertelement %s %s, i8 %%%s, i32 %d\n", inserted, tableType, tableVector, element, tableIndex*16+lane) + tableVector = "%" + inserted + } + } + result := "zeroinitializer" + destination := "" + if op == "VTBX" { + destination, err = c.loadARM64VectorInteger(ins.Args[2].Reg, destinationArrangement) + if err != nil { + return true, false, err + } + } + for lane := 0; lane < indexArrangement.lanes; lane++ { + indexByte := c.newTmp() + index32 := c.newTmp() + inRange := c.newTmp() + safeIndex := c.newTmp() + lookup := c.newTmp() + selected := c.newTmp() + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i8> %s, i32 %d\n", indexByte, indexArrangement.lanes, index, lane) + fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i32\n", index32, indexByte) + fmt.Fprintf(c.b, " %%%s = icmp ult i32 %%%s, %d\n", inRange, index32, tableBytes) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %%%s, i32 0\n", safeIndex, inRange, index32) + fmt.Fprintf(c.b, " %%%s = extractelement %s %s, i32 %%%s\n", lookup, tableType, tableVector, safeIndex) + fallback := "0" + if op == "VTBX" { + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i8> %s, i32 %d\n", old, destinationArrangement.lanes, destination, lane) + fallback = "%" + old + } + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i8 %%%s, i8 %s\n", selected, inRange, lookup, fallback) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i8> %s, i8 %%%s, i32 %d\n", inserted, destinationArrangement.lanes, result, selected, lane) + result = "%" + inserted + } + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, destinationArrangement, result) +} diff --git a/arm64_lower_table_lookup_test.go b/arm64_lower_table_lookup_test.go new file mode 100644 index 00000000..c7b0a061 --- /dev/null +++ b/arm64_lower_table_lookup_test.go @@ -0,0 +1,144 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64VectorTableLookupCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT vectortablelookupforms(SB),$0-0\n") + for _, op := range []string{"VTBL", "VTBX"} { + for _, arrangement := range []string{"B8", "B16"} { + for _, tableArrangement := range []string{"B8", "B16", "H4", "H8", "S2", "S4", "D1", "D2"} { + for count := 1; count <= 4; count++ { + fmt.Fprintf(&source, "\t%s V8.%s, %s, V9.%s\n", op, arrangement, arm64TestVectorList(30, count, tableArrangement), arrangement) + } + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"vectortablelookupforms": {Name: "vectortablelookupforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"icmp ult i32", "extractelement", "insertelement", "select i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 vector table lookup lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-table-lookup.ll", "arm64-vector-table-lookup.o", ll) + }) + } +} + +func TestTranslateARM64VectorTableLookupRejectsInvalidForms(t *testing.T) { + for _, instruction := range []string{ + "VTBL V0.B16, [V1.B16, V3.B16], V4.B16", + "VTBL V0.B16, [V1.B8, V2.H8], V4.B16", + "VTBX V0.B8, [V1.B16], V4.B16", + "VTBL V0.H8, [V1.B16], V4.H8", + "VTBL V0.B16, [V1.B16, V2.B16, V3.B16, V4.B16, V5.B16], V6.B16", + "VTBL.P V0.B16, [V1.B16], V4.B16", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badvectortablelookup(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", + Sigs: map[string]FuncSig{"badvectortablelookup": {Name: "badvectortablelookup", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted invalid vector table lookup form %q", instruction) + } + }) + } +} + +func TestARM64VectorTableLookupRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectortablelookup(SB),$0-32 + MOVD table+0(FP), R0 + MOVD indices+8(FP), R1 + MOVD initial+16(FP), R2 + MOVD out+24(FP), R3 + VLD1 (R0), [V0.B16, V1.B16, V2.B16, V3.B16] + VLD1 (R1), [V4.B16] + VTBL V4.B16, [V0.B16, V1.B16, V2.B16, V3.B16], V5.B16 + VST1.P [V5.B16], 16(R3) + VLD1 (R2), [V6.B16] + VTBX V4.B16, [V0.B16, V1.B16, V2.B16, V3.B16], V6.B16 + VST1 [V6.B16], (R3) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectortablelookup": { + Name: "vectortablelookup", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void vectortablelookup(const uint8_t *, const uint8_t *, const uint8_t *, uint8_t *); +int main(void) { + uint8_t table[64], initial[16], got[32] = {0}; + const uint8_t indices[16] = {0,15,16,31,32,47,48,63,64,255,7,23,39,55,62,1}; + for (int i = 0; i < 64; i++) table[i] = (uint8_t)(10+i); + for (int i = 0; i < 16; i++) initial[i] = (uint8_t)(200+i); + vectortablelookup(table, indices, initial, got); + for (int i = 0; i < 16; i++) { + uint8_t tbl = indices[i] < 64 ? table[indices[i]] : 0; + uint8_t tbx = indices[i] < 64 ? table[indices[i]] : initial[i]; + if (got[i] != tbl) return i + 1; + if (got[16+i] != tbx) return i + 21; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_table_lookup", triple, ll, mainC, nil) +} diff --git a/arm64_lower_variable_shift.go b/arm64_lower_variable_shift.go new file mode 100644 index 00000000..aa743a9b --- /dev/null +++ b/arm64_lower_variable_shift.go @@ -0,0 +1,83 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerARM64VectorVariableShift implements the complete AdvSIMD signed-count +// variable-shift family. The first Go-syntax operand supplies signed per-lane +// shift counts; the second is the value to shift. VSRSHL/VURSHL round right +// shifts, while VSSHL/VUSHL do not. +func (c *arm64Ctx) lowerARM64VectorVariableShift(op Op, ins Instr) (ok bool, terminated bool, err error) { + intrinsic, handled := map[Op]string{ + "VSSHL": "sshl", "VSRSHL": "srshl", + "VUSHL": "ushl", "VURSHL": "urshl", + }[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects Vshifts.T, Vvalue.T, Vdst.T with no suffix: %q", op, ins.Raw) + } + scalar := true + for _, arg := range ins.Args { + if arg.Kind != OpReg || strings.Contains(string(arg.Reg), ".") { + scalar = false + break + } + if _, ok := arm64ParseVReg(arg.Reg); !ok { + scalar = false + break + } + } + arrangement := arm64VectorArrangement{elementBits: 64, lanes: 1} + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + if scalar { + continue + } + parsed, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || !arm64VDUPArrangementAllowed(parsed) { + return true, false, fmt.Errorf("arm64 %s accepts a bare scalar D form or B8/B16/H4/H8/S2/S4/D2 vector arrangements: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + shifts, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + value, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + if scalar { + scalarShifts := c.newTmp() + scalarValue := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i64> %s, i32 0\n", scalarShifts, shifts) + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i64> %s, i32 0\n", scalarValue, value) + shifts = "%" + scalarShifts + value = "%" + scalarValue + } + vectorType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, arrangement.elementBits) + typeName := fmt.Sprintf("v%di%d", arrangement.lanes, arrangement.elementBits) + if scalar { + vectorType = "i64" + typeName = "i64" + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.neon.%s.%s(%s %s, %s %s)\n", result, vectorType, intrinsic, typeName, vectorType, value, vectorType, shifts) + storedResult := "%" + result + if scalar { + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i64> zeroinitializer, i64 %%%s, i32 0\n", inserted, result) + storedResult = "%" + inserted + } + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, storedResult) +} diff --git a/arm64_lower_variable_shift_test.go b/arm64_lower_variable_shift_test.go new file mode 100644 index 00000000..6fb69823 --- /dev/null +++ b/arm64_lower_variable_shift_test.go @@ -0,0 +1,70 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorVariableShiftCompleteGoAssemblerForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT ·vectorVariableShiftForms(SB), $0-0\n") + for _, op := range []string{"VSSHL", "VUSHL"} { + for _, arrangement := range []string{"B8", "B16", "H4", "H8", "S2", "S4", "D2"} { + source.WriteString("\t" + op + " V0." + arrangement + ", V1." + arrangement + ", V31." + arrangement + "\n") + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorVariableShiftForms": {Name: "vectorVariableShiftForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"llvm.aarch64.neon.sshl", "llvm.aarch64.neon.ushl"} { + if !strings.Contains(ir, want) { + t.Fatalf("%s variable-shift IR omitted %q:\n%s", triple, want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-variable-shift.ll", "arm64-vector-variable-shift.o", ir) + }) + } +} + +func TestTranslateARM64VectorVariableShiftRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VSSHL V0.B8, V1.B8", + "VUSHL V0.B8, V1.B16, V2.B8", + "VSSHL V0.D1, V1.D1, V2.D1", + "VUSHL V0.S4, V1.S4, V2.S2", + "VSSHL.P V0.H8, V1.H8, V2.H8", + } { + source := "TEXT ·badVectorVariableShift(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", Sigs: map[string]FuncSig{"badVectorVariableShift": {Name: "badVectorVariableShift", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VSSHL/VUSHL row", instruction) + } + } +} diff --git a/arm64_lower_vec.go b/arm64_lower_vec.go index e6282336..c776075b 100644 --- a/arm64_lower_vec.go +++ b/arm64_lower_vec.go @@ -43,6 +43,138 @@ func arm64ParseVRegLane(r Reg) (kind byte, lane int, ok bool) { // Vector/NEON lowering for a small subset used by stdlib asm. // We model V0..V31 as <16 x i8>. func (c *arm64Ctx) lowerVec(op Op, postInc bool, ins Instr) (ok bool, terminated bool, err error) { + if ok, terminated, err := c.lowerARM64WideningAddSubtract(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorAbsDiff(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorFloatImmediate(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorConstant(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorDuplicate(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64SHA3(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64AES(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64SHA(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64FloatPair(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64StructureLoadStore(op, postInc, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorBitReverse(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorCountBits(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorReverse(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorTableLookup(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64PolynomialMultiply(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorWideningMultiply(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorFloatNarrow(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorFloatWiden(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorLogical(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorIntegerCompare(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorIntegerMinMax(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorIntegerMinMaxAcross(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorIntegerAbsNeg(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorIntegerNarrow(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorSaturatingShiftNarrow(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorShiftNarrow(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorShiftLeft(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorVariableShift(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorSaturatingShift(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorShiftRight(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorShiftInsert(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorFloatUnary(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorFloatMinMaxAcross(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorFloatArithmetic(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorFloatCompare(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorHalvingAdd(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorSaturatingArithmetic(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorIntegerMultiply(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64AddAcross(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorIntegerAddSub(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorFMA(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorExtract(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64VectorPermute(op, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARM64WideningShift(op, ins); ok { + return ok, terminated, err + } switch op { case "FMOVQ": if len(ins.Args) != 2 { @@ -51,10 +183,20 @@ func (c *arm64Ctx) lowerVec(op Op, postInc bool, ins Instr) (ok bool, terminated src, dst := ins.Args[0], ins.Args[1] preInc := strings.Contains(strings.ToUpper(string(ins.Op)), ".W") switch { - case (src.Kind == OpMem || src.Kind == OpSym) && dst.Kind == OpReg: + case (src.Kind == OpFP || src.Kind == OpMem || src.Kind == OpSym) && dst.Kind == OpReg: if _, ok := arm64ParseFReg(dst.Reg); !ok { return true, false, fmt.Errorf("arm64 FMOVQ expects an F register destination: %q", ins.Raw) } + if src.Kind == OpFP { + if preInc || postInc { + return true, false, fmt.Errorf("arm64 FMOVQ .P/.W requires register memory: %q", ins.Raw) + } + value, err := c.loadFMOVQFrame(src.FPOffset) + if err != nil { + return true, false, err + } + return true, false, c.storeVReg(dst.Reg, value) + } ptr, base, inc, update, err := c.arm64VectorMemoryPointer(src, preInc, postInc) if err != nil { return true, false, err @@ -70,7 +212,7 @@ func (c *arm64Ctx) lowerVec(op Op, postInc bool, ins Instr) (ok bool, terminated } } return true, false, nil - case src.Kind == OpReg && (dst.Kind == OpMem || dst.Kind == OpSym): + case src.Kind == OpReg && (dst.Kind == OpFP || dst.Kind == OpMem || dst.Kind == OpSym): if _, ok := arm64ParseFReg(src.Reg); !ok { return true, false, fmt.Errorf("arm64 FMOVQ expects an F register source: %q", ins.Raw) } @@ -78,6 +220,12 @@ func (c *arm64Ctx) lowerVec(op Op, postInc bool, ins Instr) (ok bool, terminated if err != nil { return true, false, err } + if dst.Kind == OpFP { + if preInc || postInc { + return true, false, fmt.Errorf("arm64 FMOVQ .P/.W requires register memory: %q", ins.Raw) + } + return true, false, c.storeFMOVQFrame(dst.FPOffset, value) + } ptr, base, inc, update, err := c.arm64VectorMemoryPointer(dst, preInc, postInc) if err != nil { return true, false, err @@ -93,41 +241,6 @@ func (c *arm64Ctx) lowerVec(op Op, postInc bool, ins Instr) (ok bool, terminated return true, false, fmt.Errorf("arm64 FMOVQ expects memory and F register operands: %q", ins.Raw) } - case "FLDPQ": - if len(ins.Args) != 2 || ins.Args[0].Kind != OpMem || ins.Args[1].Kind != OpRegList || len(ins.Args[1].RegList) != 2 { - return true, false, fmt.Errorf("arm64 FLDPQ expects mem, (Freg,Freg): %q", ins.Raw) - } - mem := ins.Args[0].Mem - addr, base, inc, err := c.addrI64(mem, postInc) - if err != nil { - return true, false, err - } - for i, f := range ins.Args[1].RegList { - idx, ok := arm64ParseFReg(f) - if !ok { - return true, false, fmt.Errorf("arm64 FLDPQ expects FP register pair: %q", ins.Raw) - } - loadAddr := addr - if i != 0 { - next := c.newTmp() - fmt.Fprintf(c.b, " %%%s = add i64 %s, 16\n", next, addr) - loadAddr = "%" + next - } - ptr := c.newTmp() - fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", ptr, loadAddr) - value := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load <16 x i8>, ptr %%%s, align 1\n", value, ptr) - if err := c.storeVReg(Reg(fmt.Sprintf("V%d", idx)), "%"+value); err != nil { - return true, false, err - } - } - if postInc { - if err := c.updatePostInc(base, inc); err != nil { - return true, false, err - } - } - return true, false, nil - case "VMOVI": if len(ins.Args) != 2 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg { return true, false, fmt.Errorf("arm64 VMOVI expects $imm, Vreg.B8/B16: %q", ins.Raw) @@ -155,17 +268,6 @@ func (c *arm64Ctx) lowerVec(op Op, postInc bool, ins Instr) (ok bool, terminated } return true, false, c.storeVReg(ins.Args[1].Reg, "<"+strings.Join(elems, ", ")+">") - case "AESE", "AESD", "AESMC", "AESIMC", - "SHA1C", "SHA1H", "SHA1M", "SHA1P", "SHA1SU0", "SHA1SU1", - "SHA256H", "SHA256H2", "SHA256SU0", "SHA256SU1", - "SHA512H", "SHA512H2", "SHA512SU0", "SHA512SU1", - "VEOR3", "VBCAX", "VRAX1", "VXAR", - "VPMULL", "VPMULL2", - "VREV32", "VREV64", "VSHL", "VSRI", "VTBL", "VZIP1", "VZIP2", "VEXT", "VUSHR", - "VLD1R", "VLD4R", "VDUP": - // Keep translation permissive for crypto/NEON ops not yet modeled. - return true, false, nil - case "VMOV": // Patterns used by stdlib: // - VMOV Rn, Vm.B16 (broadcast low byte) @@ -470,6 +572,72 @@ func (c *arm64Ctx) lowerVec(op Op, postInc bool, ins Instr) (ok bool, terminated return true, false, nil case "VST1": + // VST1(.P) also has a single-lane element form (Vn.{B,H,S,D}[lane], + // memory). This is a distinct Go 1.27 C_ELEM table from the register + // list form handled below. + if len(ins.Args) == 2 && ins.Args[0].Kind == OpReg && ins.Args[1].Kind == OpMem { + kind, lane, ok := arm64ParseVRegLane(ins.Args[0].Reg) + if !ok { + return true, false, fmt.Errorf("arm64 VST1 expects an arranged vector lane: %q", ins.Raw) + } + index, ok := arm64ParseVReg(ins.Args[0].Reg) + if !ok { + return true, false, fmt.Errorf("arm64 VST1 expects a vector register lane: %q", ins.Raw) + } + width := int64(1) + switch kind { + case 'H': + width = 2 + case 'S': + width = 4 + case 'D': + width = 8 + } + mem := ins.Args[1].Mem + addr, base, inc, err := c.addrI64(mem, postInc) + if err != nil { + return true, false, err + } + if postInc && inc == 0 { + inc = width + } + vector, err := c.loadVReg(Reg(fmt.Sprintf("V%d", index))) + if err != nil { + return true, false, err + } + ptr := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", ptr, addr) + switch kind { + case 'B': + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <16 x i8> %s, i32 %d\n", element, vector, lane) + fmt.Fprintf(c.b, " store i8 %%%s, ptr %%%s, align 1\n", element, ptr) + case 'H': + words := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <8 x i16>\n", words, vector) + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <8 x i16> %%%s, i32 %d\n", element, words, lane) + fmt.Fprintf(c.b, " store i16 %%%s, ptr %%%s, align 1\n", element, ptr) + case 'S': + words := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <4 x i32>\n", words, vector) + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x i32> %%%s, i32 %d\n", element, words, lane) + fmt.Fprintf(c.b, " store i32 %%%s, ptr %%%s, align 1\n", element, ptr) + case 'D': + words := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <2 x i64>\n", words, vector) + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x i64> %%%s, i32 %d\n", element, words, lane) + fmt.Fprintf(c.b, " store i64 %%%s, ptr %%%s, align 1\n", element, ptr) + } + if postInc { + if err := c.updatePostInc(base, inc); err != nil { + return true, false, err + } + } + return true, false, nil + } // VST1.P [Vn...], mem if len(ins.Args) != 2 || ins.Args[0].Kind != OpRegList || ins.Args[1].Kind != OpMem { return true, false, fmt.Errorf("arm64 VST1 expects [v,...], mem: %q", ins.Raw) diff --git a/arm64_lower_vector_abs_diff.go b/arm64_lower_vector_abs_diff.go new file mode 100644 index 00000000..1781b461 --- /dev/null +++ b/arm64_lower_vector_abs_diff.go @@ -0,0 +1,94 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerARM64VectorAbsDiff lowers the complete Advanced SIMD absolute- +// difference family decoded from WORD forms. Go 1.27 has no named NEON optab +// row for these instructions; x/arch prints the V-prefixed aliases. +func (c *arm64Ctx) lowerARM64VectorAbsDiff(op Op, ins Instr) (ok bool, terminated bool, err error) { + type operationSpec struct { + signed bool + accumulate bool + } + spec, handled := map[Op]operationSpec{ + "VSABD": {signed: true}, + "VUABD": {}, + "VSABA": {signed: true, accumulate: true}, + "VUABA": {accumulate: true}, + }[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects three same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + var arrangement arm64VectorArrangement + for i, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + parsed, valid := parseARM64VectorArrangement(arg.Reg) + if !valid || parsed.elementBits > 32 || (parsed.elementBits == 8 && parsed.lanes != 8 && parsed.lanes != 16) || + (parsed.elementBits == 16 && parsed.lanes != 4 && parsed.lanes != 8) || + (parsed.elementBits == 32 && parsed.lanes != 2 && parsed.lanes != 4) { + return true, false, fmt.Errorf("arm64 %s accepts only B8/B16/H4/H8/S2/S4 arrangements: %q", op, ins.Raw) + } + if i == 0 { + arrangement = parsed + } else if parsed != arrangement { + return true, false, fmt.Errorf("arm64 %s arrangements must match: %q", op, ins.Raw) + } + } + first, err := c.loadARM64VectorInteger(ins.Args[0].Reg, arrangement) + if err != nil { + return true, false, err + } + second, err := c.loadARM64VectorInteger(ins.Args[1].Reg, arrangement) + if err != nil { + return true, false, err + } + vectorType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, arrangement.elementBits) + result := "" + if spec.signed { + wideBits := arrangement.elementBits * 2 + wideType := fmt.Sprintf("<%d x i%d>", arrangement.lanes, wideBits) + wideFirst := c.newTmp() + wideSecond := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", wideFirst, vectorType, first, wideType) + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", wideSecond, vectorType, second, wideType) + condition := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp sgt %s %%%s, %%%s\n", condition, wideType, wideFirst, wideSecond) + firstDifference := c.newTmp() + secondDifference := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s %%%s, %%%s\n", firstDifference, wideType, wideFirst, wideSecond) + fmt.Fprintf(c.b, " %%%s = sub %s %%%s, %%%s\n", secondDifference, wideType, wideSecond, wideFirst) + wideResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %%%s, %s %%%s\n", wideResult, arrangement.lanes, condition, wideType, firstDifference, wideType, secondDifference) + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", narrow, wideType, wideResult, vectorType) + result = "%" + narrow + } else { + condition := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp ugt %s %s, %s\n", condition, vectorType, first, second) + firstDifference := c.newTmp() + secondDifference := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub %s %s, %s\n", firstDifference, vectorType, first, second) + fmt.Fprintf(c.b, " %%%s = sub %s %s, %s\n", secondDifference, vectorType, second, first) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %%%s, %s %%%s\n", selected, arrangement.lanes, condition, vectorType, firstDifference, vectorType, secondDifference) + result = "%" + selected + } + if spec.accumulate { + accumulator, err := c.loadARM64VectorInteger(ins.Args[2].Reg, arrangement) + if err != nil { + return true, false, err + } + accumulated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", accumulated, vectorType, accumulator, result) + result = "%" + accumulated + } + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, arrangement, result) +} diff --git a/arm64_lower_vector_abs_diff_test.go b/arm64_lower_vector_abs_diff_test.go new file mode 100644 index 00000000..6bd4f2dc --- /dev/null +++ b/arm64_lower_vector_abs_diff_test.go @@ -0,0 +1,130 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64RawVectorAbsoluteDifferenceCompleteArchitecturalFormats(t *testing.T) { + ops := []struct { + name string + bases []uint32 + }{ + {"sabd", []uint32{0x0e207400, 0x4e207400, 0x0e607400, 0x4e607400, 0x0ea07400, 0x4ea07400}}, + {"uabd", []uint32{0x2e207400, 0x6e207400, 0x2e607400, 0x6e607400, 0x2ea07400, 0x6ea07400}}, + {"saba", []uint32{0x0e207c00, 0x4e207c00, 0x0e607c00, 0x4e607c00, 0x0ea07c00, 0x4ea07c00}}, + {"uaba", []uint32{0x2e207c00, 0x6e207c00, 0x2e607c00, 0x6e607c00, 0x2ea07c00, 0x6ea07c00}}, + } + var source strings.Builder + source.WriteString("TEXT vectorabsolutedifferenceforms(SB),$0-0\n") + for _, op := range ops { + for _, base := range op.bases { + fmt.Fprintf(&source, "\tWORD $%#08x // %s\n", base|29<<16|30<<5|28, op.name) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"vectorabsolutedifferenceforms": {Name: "vectorabsolutedifferenceforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sext <", "icmp sgt <", "icmp ugt <", "add <"} { + if !strings.Contains(ir, want) { + t.Fatalf("absolute-difference family for %s omitted %q:\n%s", triple, want, ir) + } + } + compileLLVMToObject(t, llc, triple, "arm64-vector-absolute-difference.ll", "arm64-vector-absolute-difference.o", ir) + }) + } +} + +func TestARM64RawVectorAbsoluteDifferenceRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectorabsolutedifference(SB),$0-32 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD accumulator+16(FP), R2 + MOVD output+24(FP), R3 + VLD1 (R0), [V0.B16] + VLD1 (R1), [V1.B16] + VLD1 (R2), [V2.B16] + VLD1 (R2), [V5.B16] + WORD $0x4e217403 // SABD V3.16B, V0.16B, V1.16B + WORD $0x6e217404 // UABD V4.16B, V0.16B, V1.16B + WORD $0x4e217c02 // SABA V2.16B, V0.16B, V1.16B + WORD $0x6e217c05 // UABA V5.16B, V0.16B, V1.16B + VST1.P [V3.B16], 16(R3) + VST1.P [V4.B16], 16(R3) + VST1.P [V2.B16], 16(R3) + VST1.P [V5.B16], 16(R3) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"vectorabsolutedifference": { + Name: "vectorabsolutedifference", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void vectorabsolutedifference(const int8_t *, const int8_t *, const uint8_t *, uint8_t *); +int main(void) { + const int8_t a[16] = {127,-128,12,-20,0,1,-1,64,-64,100,-100,5,-5,30,-30,42}; + const int8_t b[16] = {-128,127,-12,20,0,-1,1,-64,64,-100,100,-5,5,-30,30,-42}; + const uint8_t accumulator[16] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + uint8_t got[64] = {0}; + vectorabsolutedifference(a, b, accumulator, got); + for (int i = 0; i < 16; i++) { + int signed_diff = (int)a[i] - (int)b[i]; + if (signed_diff < 0) signed_diff = -signed_diff; + int unsigned_diff = (int)(uint8_t)a[i] - (int)(uint8_t)b[i]; + if (unsigned_diff < 0) unsigned_diff = -unsigned_diff; + if (got[i] != (uint8_t)signed_diff) return i + 1; + if (got[16+i] != (uint8_t)unsigned_diff) return i + 17; + if (got[32+i] != (uint8_t)(accumulator[i] + signed_diff)) return i + 33; + if (got[48+i] != (uint8_t)(accumulator[i] + unsigned_diff)) return i + 49; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_absolute_difference", triple, ir, mainC, nil) +} diff --git a/arm64_lower_vector_bit_reverse.go b/arm64_lower_vector_bit_reverse.go new file mode 100644 index 00000000..9584577c --- /dev/null +++ b/arm64_lower_vector_bit_reverse.go @@ -0,0 +1,30 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorBitReverse(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "VRBIT" { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != "VRBIT" || len(ins.Args) != 2 || + ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 VRBIT expects Vm.B8/B16, Vd.B8/B16: %q", ins.Raw) + } + sourceArrangement, sourceOK := parseARM64VectorArrangement(ins.Args[0].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[1].Reg) + if !sourceOK || !destinationOK || sourceArrangement != destinationArrangement || + sourceArrangement.elementBits != 8 || sourceArrangement.lanes != 8 && sourceArrangement.lanes != 16 { + return true, false, fmt.Errorf("arm64 VRBIT requires matching B8 or B16 arrangements: %q", ins.Raw) + } + source, err := c.loadARM64VectorInteger(ins.Args[0].Reg, sourceArrangement) + if err != nil { + return true, false, err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <%d x i8> @llvm.bitreverse.v%di8(<%d x i8> %s)\n", + result, sourceArrangement.lanes, sourceArrangement.lanes, sourceArrangement.lanes, source) + return true, false, c.storeARM64VectorInteger(ins.Args[1].Reg, destinationArrangement, "%"+result) +} diff --git a/arm64_lower_vector_bit_reverse_test.go b/arm64_lower_vector_bit_reverse_test.go new file mode 100644 index 00000000..8ff003a6 --- /dev/null +++ b/arm64_lower_vector_bit_reverse_test.go @@ -0,0 +1,64 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64VectorBitReverseCompleteFormats(t *testing.T) { + const source = `TEXT vectorBitReverse(SB),$0-0 + VRBIT V0.B8, V1.B8 + VRBIT V2.B16, V3.B16 + VRBIT V4.B16, V4.B16 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"vectorBitReverse": {Name: "vectorBitReverse", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"@llvm.bitreverse.v8i8", "@llvm.bitreverse.v16i8"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 VRBIT lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-vector-bit-reverse.ll", "arm64-vector-bit-reverse.o", ll) +} + +func TestTranslateARM64VectorBitReverseRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "VRBIT V0.H4, V1.H4", + "VRBIT V0.B8, V1.B16", + "VRBIT V0, V1", + "VRBIT R0, V1.B8", + "VRBIT.P V0.B8, V1.B8", + } { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM64 VRBIT optab", instruction) + } + } +} diff --git a/arm64_lower_vector_constant.go b/arm64_lower_vector_constant.go new file mode 100644 index 00000000..8e76f648 --- /dev/null +++ b/arm64_lower_vector_constant.go @@ -0,0 +1,69 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerARM64VectorConstant implements the complete Go assembler family for +// materializing 32-, 64-, and 128-bit constants in a vector register: +// +// VMOVS $lo32, Vd +// VMOVD $lo64, Vd +// VMOVQ $lo64, $hi64, Vd +func (c *arm64Ctx) lowerARM64VectorConstant(op Op, ins Instr) (ok bool, terminated bool, err error) { + var bits int + switch op { + case "VMOVS": + bits = 32 + case "VMOVD": + bits = 64 + case "VMOVQ": + bits = 128 + default: + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an instruction suffix: %q", op, ins.Raw) + } + wantArgs := 2 + if bits == 128 { + wantArgs = 3 + } + if len(ins.Args) != wantArgs { + return true, false, fmt.Errorf("arm64 %s expects %d operands: %q", op, wantArgs, ins.Raw) + } + for i := 0; i < wantArgs-1; i++ { + if ins.Args[i].Kind != OpImm { + return true, false, fmt.Errorf("arm64 %s operand %d must be an immediate: %q", op, i+1, ins.Raw) + } + } + dst := ins.Args[wantArgs-1] + if dst.Kind != OpReg || strings.Contains(string(dst.Reg), ".") { + return true, false, fmt.Errorf("arm64 %s destination must be a bare V register: %q", op, ins.Raw) + } + if _, valid := arm64ParseVReg(dst.Reg); !valid { + return true, false, fmt.Errorf("arm64 %s destination must be a bare V register: %q", op, ins.Raw) + } + + var vector, vectorType string + switch bits { + case 32: + vectorType = "<4 x i32>" + vector = c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <4 x i32> zeroinitializer, i32 %d, i32 0\n", vector, uint32(ins.Args[0].Imm)) + case 64: + vectorType = "<2 x i64>" + vector = c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> zeroinitializer, i64 %d, i32 0\n", vector, uint64(ins.Args[0].Imm)) + case 128: + vectorType = "<2 x i64>" + low := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> zeroinitializer, i64 %d, i32 0\n", low, uint64(ins.Args[0].Imm)) + vector = c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <2 x i64> %%%s, i64 %d, i32 1\n", vector, low, uint64(ins.Args[1].Imm)) + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %%%s to <16 x i8>\n", bytes, vectorType, vector) + return true, false, c.storeVReg(dst.Reg, "%"+bytes) +} diff --git a/arm64_lower_vector_constant_test.go b/arm64_lower_vector_constant_test.go new file mode 100644 index 00000000..2c39805f --- /dev/null +++ b/arm64_lower_vector_constant_test.go @@ -0,0 +1,146 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64VectorConstantForms = ` +TEXT vectorconstantforms(SB),$0-0 + VMOVS $0x80402010, V1 + VMOVD $0x7040201008040201, V2 + VMOVQ $0x7040201008040201, $0x3040201008040201, V3 + RET +` + +func TestTranslateARM64VectorConstantCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64VectorConstantForms, true) + file, err := Parse(ArchARM64, arm64VectorConstantForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorconstantforms": {Name: "vectorconstantforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"insertelement <4 x i32> zeroinitializer", "insertelement <2 x i64> zeroinitializer", "bitcast <2 x i64>"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 vector constant lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-constants.ll", "arm64-vector-constants.o", ll) + }) + } +} + +func TestTranslateARM64VectorConstantRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VMOVS V0, V1", + "VMOVS $1, V1.S4", + "VMOVS $1, $2, V1", + "VMOVD $1", + "VMOVD $1, R1", + "VMOVQ $1, V1", + "VMOVQ $1, $2, V1, V2", + "VMOVQ.P $1, $2, V1", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badvectorconstant(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorconstant": {Name: "badvectorconstant", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VMOVS/VMOVD/VMOVQ table", instruction) + } + }) + } +} + +func TestARM64VectorConstantRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectorconstants(SB),$0-8 + MOVD out+0(FP), R0 + VMOVS $0x80402010, V1 + VMOV V1.S[0], R1 + MOVW R1, 0(R0) + VMOVD $0x7040201008040201, V2 + VMOV V2.D[0], R2 + VMOV V2.D[1], R3 + MOVD R2, 8(R0) + MOVD R3, 16(R0) + VMOVQ $0x7040201008040201, $0x3040201008040201, V4 + VMOV V4.D[0], R4 + VMOV V4.D[1], R5 + MOVD R4, 24(R0) + MOVD R5, 32(R0) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorconstants": { + Name: "vectorconstants", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +struct values { uint32_t s; uint32_t pad; uint64_t d; uint64_t dzero; uint64_t qlo; uint64_t qhi; }; +extern void vectorconstants(struct values *); +int main(void) { + struct values got = {0}; + vectorconstants(&got); + if (got.s != UINT32_C(0x80402010)) return 1; + if (got.d != UINT64_C(0x7040201008040201) || got.dzero != 0) return 2; + if (got.qlo != UINT64_C(0x7040201008040201)) return 3; + if (got.qhi != UINT64_C(0x3040201008040201)) return 4; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_constants", triple, ll, mainC, nil) +} diff --git a/arm64_lower_vector_count_leading_test.go b/arm64_lower_vector_count_leading_test.go new file mode 100644 index 00000000..50fabee9 --- /dev/null +++ b/arm64_lower_vector_count_leading_test.go @@ -0,0 +1,149 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64VectorCountLeadingForms = ` +TEXT vectorcountleadingforms(SB),$0-0 + VCLS V0.B8, V1.B8 + VCLS V2.B16, V3.B16 + VCLS V4.H4, V5.H4 + VCLS V6.H8, V7.H8 + VCLS V8.S2, V9.S2 + VCLS V10.S4, V11.S4 + VCLZ V12.B8, V13.B8 + VCLZ V14.B16, V15.B16 + VCLZ V16.H4, V17.H4 + VCLZ V18.H8, V19.H8 + VCLZ V20.S2, V21.S2 + VCLZ V22.S4, V23.S4 + RET +` + +func TestTranslateARM64VectorCountLeadingCompleteGoAssemblerForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64VectorCountLeadingForms, true) + file, err := Parse(ArchARM64, arm64VectorCountLeadingForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorcountleadingforms": {Name: "vectorcountleadingforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if got := strings.Count(ll, " = call <"); got != 12 { + t.Fatalf("ARM64 VCLS/VCLZ emitted %d vector ctlz calls, want 12:\n%s", got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-count-leading.ll", "arm64-vector-count-leading.o", ll) + }) + } +} + +func TestTranslateARM64VectorCountLeadingRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VCLS V0.D1, V1.D1", + "VCLS V0.D2, V1.D2", + "VCLZ V0.D1, V1.D1", + "VCLZ V0.D2, V1.D2", + "VCLS V0.B8, V1.B16", + "VCLZ V0.H4, V1.H8", + "VCLS V0.B8, V1.B8, V2.B8", + "VCLZ.P V0.S4, V1.S4", + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(instruction), func(t *testing.T) { + source := "TEXT badvectorcountleading(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "badvectorcountleading": {Name: "badvectorcountleading", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VCLS/VCLZ forms", instruction) + } + }) + } +} + +func TestARM64VectorCountLeadingRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectorcountleading(SB),$0-16 + MOVD in+0(FP), R0 + MOVD out+8(FP), R1 + VLD1 (R0), [V0.B16] + VCLZ V0.B16, V1.B16 + VCLS V0.B16, V2.B16 + VST1 [V1.B16, V2.B16], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorcountleading": { + Name: "vectorcountleading", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void vectorcountleading(const uint8_t *, uint8_t *); +int main(void) { + const uint8_t input[16] = {0x00,0x01,0x02,0x03,0x7f,0x80,0xff,0xfe,0xf0,0x10,0x08,0x04,0xc0,0x40,0xaa,0x55}; + const uint8_t want[32] = { + 8,7,6,6,1,0,0,0,0,3,4,5,0,1,0,1, + 7,6,5,5,0,0,7,6,3,2,3,4,1,0,0,0 + }; + uint8_t got[32] = {0}; + vectorcountleading(input, got); + for (int i = 0; i < 32; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_count_leading", triple, ll, mainC, nil) +} diff --git a/arm64_lower_vector_float_immediate.go b/arm64_lower_vector_float_immediate.go new file mode 100644 index 00000000..11c5a1bd --- /dev/null +++ b/arm64_lower_vector_float_immediate.go @@ -0,0 +1,86 @@ +package plan9asm + +import ( + "fmt" + "math" + "strings" +) + +// lowerARM64VectorFloatImmediate handles the Advanced SIMD floating-point +// modified-immediate form. x/arch prints this raw encoding as FMOV $f, Vd.T; +// Go's named optab has no VFMOV spelling, so keep the decoder spelling and +// lower it directly to the repeated IEEE value (with inactive lanes zero). +func (c *arm64Ctx) lowerARM64VectorFloatImmediate(op Op, ins Instr) (ok bool, terminated bool, err error) { + if op != "FMOV" || len(ins.Args) != 2 || ins.Args[0].Kind != OpImm || ins.Args[1].Kind != OpReg { + return false, false, nil + } + if !ins.Args[0].ImmIsFloat || ins.Args[0].ImmRaw != "" { + return true, false, fmt.Errorf("arm64 FMOV vector immediate requires a resolved floating constant: %q", ins.Raw) + } + arrangement, valid := parseARM64VectorArrangement(ins.Args[1].Reg) + if !valid || (arrangement.elementBits != 16 && arrangement.elementBits != 32) || + arrangement.lanes <= 0 || arrangement.lanes > 128/arrangement.elementBits { + return true, false, fmt.Errorf("arm64 FMOV vector immediate requires H4/H8 or S2/S4 destination: %q", ins.Raw) + } + value := math.Float64frombits(uint64(ins.Args[0].Imm)) + physicalLanes := 128 / arrangement.elementBits + values := make([]string, physicalLanes) + for i := range values { + if i >= arrangement.lanes { + values[i] = "0" + continue + } + if arrangement.elementBits == 16 { + values[i] = fmt.Sprintf("%d", arm64Float16Bits(value)) + } else { + values[i] = fmt.Sprintf("%d", math.Float32bits(float32(value))) + } + } + elements := make([]string, len(values)) + for i, element := range values { + elements[i] = fmt.Sprintf("i%d %s", arrangement.elementBits, element) + } + vector := c.newTmp() + vectorType := fmt.Sprintf("<%d x i%d>", physicalLanes, arrangement.elementBits) + fmt.Fprintf(c.b, " %%%s = bitcast %s <%s> to <16 x i8>\n", vector, vectorType, strings.Join(elements, ", ")) + return true, false, c.storeVReg(ins.Args[1].Reg, "%"+vector) +} + +// arm64Float16Bits converts the ordinary floating-point constant used by the +// parser into IEEE binary16 bits for the H-form modified immediate. +func arm64Float16Bits(value float64) uint16 { + bits := math.Float32bits(float32(value)) + sign := uint16((bits >> 16) & 0x8000) + exponent := int((bits >> 23) & 0xff) + fraction := bits & 0x7fffff + if exponent == 0xff { + if fraction == 0 { + return sign | 0x7c00 + } + return sign | 0x7e00 + } + exponent -= 127 + if exponent < -24 { + return sign + } + if exponent < -14 { + shift := uint(-exponent - 14) + mantissa := (fraction | 0x800000) >> (shift + 1) + if (fraction|0x800000)&(1< 15 { + return sign | 0x7c00 + } + halfExponent := uint16(exponent+15) << 10 + mantissa := fraction >> 13 + if fraction&0x1000 != 0 { + mantissa++ + if mantissa == 0x400 { + return sign | halfExponent + 0x400 + } + } + return sign | halfExponent | uint16(mantissa) +} diff --git a/arm64_lower_vector_reverse.go b/arm64_lower_vector_reverse.go new file mode 100644 index 00000000..83da34f9 --- /dev/null +++ b/arm64_lower_vector_reverse.go @@ -0,0 +1,47 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorReverse(op Op, ins Instr) (ok bool, terminated bool, err error) { + groupBytes, handled := map[Op]int{ + "VREV16": 2, + "VREV32": 4, + "VREV64": 8, + }[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects two same-arrangement vector registers and no suffix: %q", op, ins.Raw) + } + sourceArrangement, sourceOK := parseARM64VectorArrangement(ins.Args[0].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[1].Reg) + if !sourceOK || !destinationOK || sourceArrangement != destinationArrangement { + return true, false, fmt.Errorf("arm64 %s expects matching vector arrangements: %q", op, ins.Raw) + } + elementBytes := sourceArrangement.elementBits / 8 + if elementBytes == 0 || elementBytes >= groupBytes { + return true, false, fmt.Errorf("arm64 %s requires elements narrower than its %d-bit reversal groups: %q", op, groupBytes*8, ins.Raw) + } + source, err := c.loadARM64VectorInteger(ins.Args[0].Reg, sourceArrangement) + if err != nil { + return true, false, err + } + vectorType := fmt.Sprintf("<%d x i%d>", sourceArrangement.lanes, sourceArrangement.elementBits) + groupElements := groupBytes / elementBytes + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector %s %s, %s poison, <%d x i32> <", result, vectorType, source, vectorType, sourceArrangement.lanes) + for lane := 0; lane < sourceArrangement.lanes; lane++ { + if lane != 0 { + c.b.WriteString(", ") + } + groupStart := lane / groupElements * groupElements + reversedLane := groupStart + groupElements - 1 - lane%groupElements + fmt.Fprintf(c.b, "i32 %d", reversedLane) + } + c.b.WriteString(">\n") + return true, false, c.storeARM64VectorInteger(ins.Args[1].Reg, destinationArrangement, "%"+result) +} diff --git a/arm64_lower_vector_reverse_test.go b/arm64_lower_vector_reverse_test.go new file mode 100644 index 00000000..35fcef44 --- /dev/null +++ b/arm64_lower_vector_reverse_test.go @@ -0,0 +1,145 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64VectorReverseForms = ` +TEXT vectorreverseforms(SB),$0-0 + VREV16 V0.B8, V1.B8 + VREV16 V2.B16, V3.B16 + VREV32 V4.B8, V5.B8 + VREV32 V6.B16, V7.B16 + VREV32 V8.H4, V9.H4 + VREV32 V10.H8, V11.H8 + VREV64 V12.B8, V13.B8 + VREV64 V14.B16, V15.B16 + VREV64 V16.H4, V17.H4 + VREV64 V18.H8, V19.H8 + VREV64 V20.S2, V21.S2 + VREV64 V22.S4, V23.S4 + RET +` + +func TestTranslateARM64VectorReverseCompleteArchitecturalForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64VectorReverseForms, true) + file, err := Parse(ArchARM64, arm64VectorReverseForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"vectorreverseforms": {Name: "vectorreverseforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + // The twelve reverse operations plus six low-half extraction shuffles + // for the 64-bit arrangements must all survive LLVM normalization. + if got := strings.Count(ll, "shufflevector"); got != 18 { + t.Fatalf("ARM64 vector reverse emitted %d shuffles, want 18:\n%s", got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-reverse.ll", "arm64-vector-reverse.o", ll) + }) + } +} + +func TestTranslateARM64VectorReverseRejectsInvalidForms(t *testing.T) { + for _, tc := range []struct { + instruction string + goAccepts bool + }{ + {"VREV16 V0.H4, V1.H4", false}, + {"VREV32 V0.S2, V1.S2", false}, + // Go 1.27 accepts these reserved size=3 encodings; LLVM 22 and the ARM + // architecture reject them, so the translator must not mirror that bug. + {"VREV32 V0.D2, V1.D2", true}, + {"VREV64 V0.D2, V1.D2", true}, + {"VREV64 V0.B8, V1.B16", false}, + {"VREV64.P V0.S4, V1.S4", false}, + } { + t.Run(strings.NewReplacer(" ", "_", ",", "", ".", "_").Replace(tc.instruction), func(t *testing.T) { + source := "TEXT badvectorreverse(SB),$0-0\n\t" + tc.instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, tc.goAccepts) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", Goarch: "arm64", + Sigs: map[string]FuncSig{"badvectorreverse": {Name: "badvectorreverse", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted invalid vector reverse form %q", tc.instruction) + } + }) + } +} + +func TestARM64VectorReverseRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT vectorreverse(SB),$0-16 + MOVD in+0(FP), R0 + MOVD out+8(FP), R1 + VLD1 (R0), [V0.B16] + VREV16 V0.B16, V1.B16 + VREV32 V0.B16, V2.B16 + VREV64 V0.B16, V3.B16 + VST1 [V1.B16, V2.B16, V3.B16], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "vectorreverse": { + Name: "vectorreverse", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void vectorreverse(const uint8_t *, uint8_t *); +int main(void) { + const uint8_t input[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + const uint8_t want[48] = { + 1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14, + 3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12, + 7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8 + }; + uint8_t got[48] = {0}; + vectorreverse(input, got); + for (int i = 0; i < 48; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_vector_reverse", triple, ll, mainC, nil) +} diff --git a/arm64_lower_widening_add.go b/arm64_lower_widening_add.go new file mode 100644 index 00000000..8b2ee588 --- /dev/null +++ b/arm64_lower_widening_add.go @@ -0,0 +1,113 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64WideningAddSubtractSpec struct { + signed bool + subtract bool + wide bool + highHalf bool +} + +var arm64WideningAddSubtractOps = map[Op]arm64WideningAddSubtractSpec{ + "VSADDL": {signed: true}, + "VSADDL2": {signed: true, highHalf: true}, + "VSADDW": {signed: true, wide: true}, + "VSADDW2": {signed: true, wide: true, highHalf: true}, + "VSSUBL": {signed: true, subtract: true}, + "VSSUBL2": {signed: true, subtract: true, highHalf: true}, + "VSSUBW": {signed: true, subtract: true, wide: true}, + "VSSUBW2": {signed: true, subtract: true, wide: true, highHalf: true}, + "VUADDL": {}, + "VUADDL2": {highHalf: true}, + "VUADDW": {wide: true}, + "VUADDW2": {wide: true, highHalf: true}, + "VUSUBL": {subtract: true}, + "VUSUBL2": {subtract: true, highHalf: true}, + "VUSUBW": {subtract: true, wide: true}, + "VUSUBW2": {subtract: true, wide: true, highHalf: true}, +} + +// lowerARM64WideningAddSubtract implements the complete AdvSIMD +// three-different add/subtract-long and add/subtract-wide family. Go 1.27 has +// named forms for VUADDW/VUADDW2; the remaining architectural forms enter +// through WORD decoding from external assembly. +func (c *arm64Ctx) lowerARM64WideningAddSubtract(op Op, ins Instr) (ok bool, terminated bool, err error) { + spec, handled := arm64WideningAddSubtractOps[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects two sources, one wide destination, and no suffix: %q", op, ins.Raw) + } + for _, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + } + + firstArrangement, firstOK := parseARM64VectorArrangement(ins.Args[0].Reg) + secondArrangement, secondOK := parseARM64VectorArrangement(ins.Args[1].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[2].Reg) + wantNarrowLanes := destinationArrangement.lanes + if spec.highHalf { + wantNarrowLanes *= 2 + } + valid := firstOK && secondOK && destinationOK && + destinationArrangement.lanes*destinationArrangement.elementBits == 128 && + destinationArrangement.elementBits >= 16 && destinationArrangement.elementBits <= 64 && + firstArrangement.elementBits*2 == destinationArrangement.elementBits && + firstArrangement.lanes == wantNarrowLanes + if spec.wide { + valid = valid && secondArrangement == destinationArrangement + } else { + valid = valid && secondArrangement == firstArrangement + } + if !valid { + return true, false, fmt.Errorf("arm64 %s arrangements do not form an 8->16, 16->32, or 32->64 widening row: %q", op, ins.Raw) + } + + first, err := c.loadARM64VectorInteger(ins.Args[0].Reg, firstArrangement) + if err != nil { + return true, false, err + } + if spec.highHalf { + first = c.selectARM64VectorHighHalf(firstArrangement, destinationArrangement.lanes, first) + } + narrowType := fmt.Sprintf("<%d x i%d>", destinationArrangement.lanes, firstArrangement.elementBits) + wideType := fmt.Sprintf("<%d x i%d>", destinationArrangement.lanes, destinationArrangement.elementBits) + extension := "zext" + if spec.signed { + extension = "sext" + } + wideFirst := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", wideFirst, extension, narrowType, first, wideType) + + second, err := c.loadARM64VectorInteger(ins.Args[1].Reg, secondArrangement) + if err != nil { + return true, false, err + } + if !spec.wide { + if spec.highHalf { + second = c.selectARM64VectorHighHalf(secondArrangement, destinationArrangement.lanes, second) + } + wideSecond := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", wideSecond, extension, narrowType, second, wideType) + second = "%" + wideSecond + } + + operation := "add" + left, right := "%"+wideFirst, second + if spec.subtract { + operation = "sub" + // Go syntax reverses the architectural Vn/Vm sources. Both SUBL and + // SUBW therefore compute the second source minus the widened first. + left, right = second, "%"+wideFirst + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", result, operation, wideType, left, right) + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, destinationArrangement, "%"+result) +} diff --git a/arm64_lower_widening_add_sub_test.go b/arm64_lower_widening_add_sub_test.go new file mode 100644 index 00000000..16762804 --- /dev/null +++ b/arm64_lower_widening_add_sub_test.go @@ -0,0 +1,130 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64VectorWideningAddSubtract(base uint32, elementBits, narrow, wide, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2}[elementBits] + return base | size<<22 | uint32(narrow)<<16 | uint32(wide)<<5 | uint32(destination) +} + +func TestTranslateARM64RawWideningAddSubtractCompleteArchitectureFamily(t *testing.T) { + // These are the complete AdvSIMD three-different add/subtract-long and + // add/subtract-wide rows in x/arch's ARM64 architecture table. + families := []struct { + name string + base uint32 + }{ + {name: "VSADDL", base: 0x0e200000}, + {name: "VSADDL2", base: 0x4e200000}, + {name: "VSADDW", base: 0x0e201000}, + {name: "VSADDW2", base: 0x4e201000}, + {name: "VSSUBL", base: 0x0e202000}, + {name: "VSSUBL2", base: 0x4e202000}, + {name: "VSSUBW", base: 0x0e203000}, + {name: "VSSUBW2", base: 0x4e203000}, + {name: "VUADDL", base: 0x2e200000}, + {name: "VUADDL2", base: 0x6e200000}, + {name: "VUADDW", base: 0x2e201000}, + {name: "VUADDW2", base: 0x6e201000}, + {name: "VUSUBL", base: 0x2e202000}, + {name: "VUSUBL2", base: 0x6e202000}, + {name: "VUSUBW", base: 0x2e203000}, + {name: "VUSUBW2", base: 0x6e203000}, + } + + var source strings.Builder + source.WriteString("TEXT ·wideningAddSubtractForms(SB), $0-0\n") + for _, family := range families { + for _, elementBits := range []int{8, 16, 32} { + word := encodeARM64VectorWideningAddSubtract(family.base, elementBits, 30, 29, 28) + decoded, err := decodeARM64RawWordInstruction(Instr{Op: OpWORD, Args: []Operand{{Kind: OpImm, Imm: int64(word)}}}) + if err != nil { + t.Fatalf("decode %s %d-bit: %v", family.name, elementBits, err) + } + if decoded.Op != Op(family.name) || len(decoded.Args) != 3 || + !strings.HasPrefix(string(decoded.Args[0].Reg), "V30.") || + !strings.HasPrefix(string(decoded.Args[1].Reg), "V29.") || + !strings.HasPrefix(string(decoded.Args[2].Reg), "V28.") { + t.Fatalf("decoded %s %d-bit %#08x as %#v; want reversed Vm=V30, Vn=V29, Vd=V28", family.name, elementBits, word, decoded) + } + fmt.Fprintf(&source, "\tWORD $%#08x // %s %d-bit\n", word, family.name, elementBits) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "wideningAddSubtractForms": {Name: "wideningAddSubtractForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for operation, want := range map[string]int{ + " = zext <": 36, + " = sext <": 36, + " = add <": 24, + " = sub <": 24, + " = shufflevector <": 72, + } { + if got := strings.Count(ll, operation); got != want { + t.Fatalf("%s emitted %d occurrences of %q, want %d:\n%s", triple, got, operation, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-widening-add-sub.ll", "arm64-widening-add-sub.o", ll) + }) + } +} + +func TestTranslateARM64WideningAddSubtractRejectsInvalidArrangements(t *testing.T) { + for _, instruction := range []string{ + "VUADDL V0.B16, V1.B16, V2.H8", + "VUADDL2 V0.B8, V1.B8, V2.H8", + "VSADDL V0.B8, V1.H4, V2.H8", + "VSSUBL V0.H4, V1.H4, V2.S2", + "VUSUBW V0.B16, V1.H8, V2.H8", + "VUSUBW2 V0.B8, V1.H8, V2.H8", + "VSADDW V0.B8, V1.H8, V2.S4", + "VSSUBW V0.B8, V1.H8", + "VSSUBW.P V0.B8, V1.H8, V2.H8", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + file, err := Parse(ArchARM64, "TEXT ·badWidening(SB), $0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{"badWidening": {Name: "badWidening", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted invalid ARM64 widening add/subtract form %q", instruction) + } + }) + } +} diff --git a/arm64_lower_widening_add_test.go b/arm64_lower_widening_add_test.go new file mode 100644 index 00000000..f69fb221 --- /dev/null +++ b/arm64_lower_widening_add_test.go @@ -0,0 +1,91 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64UnsignedWideningAddCompleteGoAssemblerForms(t *testing.T) { + type form struct{ narrow, wide string } + var source strings.Builder + source.WriteString("TEXT ·unsignedWideningAddForms(SB), $0-0\n") + for _, family := range []struct { + op string + forms []form + }{ + {op: "VUADDW", forms: []form{{"B8", "H8"}, {"H4", "S4"}, {"S2", "D2"}}}, + {op: "VUADDW2", forms: []form{{"B16", "H8"}, {"H8", "S4"}, {"S4", "D2"}}}, + } { + for _, form := range family.forms { + fmt.Fprintf(&source, "\t%s V0.%s, V1.%s, V2.%s\n", family.op, form.narrow, form.wide, form.wide) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "unsignedWideningAddForms": {Name: "unsignedWideningAddForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + if got := strings.Count(ll, " = zext <"); got != 6 { + t.Fatalf("%s emitted %d widening extensions, want 6:\n%s", triple, got, ll) + } + if got := strings.Count(ll, " = add <"); got != 6 { + t.Fatalf("%s emitted %d vector additions, want 6:\n%s", triple, got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-unsigned-widening-add.ll", "arm64-unsigned-widening-add.o", ll) + } +} + +func TestTranslateARM64UnsignedWideningAddRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VUADDW V0.B16, V1.H8, V2.H8", + "VUADDW2 V0.B8, V1.H8, V2.H8", + "VUADDW V0.B8, V1.H8, V2.S4", + "VUADDW V0.H4, V1.D2, V2.D2", + "VUADDW V0.B8, V1.H8", + "VUADDW.P V0.B8, V1.H8, V2.H8", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT ·badUnsignedWideningAdd(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badUnsignedWideningAdd": {Name: "badUnsignedWideningAdd", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's VUADDW family", instruction) + } + }) + } +} diff --git a/arm64_lower_widening_multiply.go b/arm64_lower_widening_multiply.go new file mode 100644 index 00000000..e12f708c --- /dev/null +++ b/arm64_lower_widening_multiply.go @@ -0,0 +1,137 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64VectorWideningMultiply(op Op, ins Instr) (ok bool, terminated bool, err error) { + type operationSpec struct { + signed bool + accumulate string + highHalf bool + } + spec, handled := map[Op]operationSpec{ + "VSMULL": {signed: true}, "VSMULL2": {signed: true, highHalf: true}, + "VSMLAL": {signed: true, accumulate: "add"}, "VSMLAL2": {signed: true, accumulate: "add", highHalf: true}, + "VSMLSL": {signed: true, accumulate: "sub"}, "VSMLSL2": {signed: true, accumulate: "sub", highHalf: true}, + "VUMULL": {}, "VUMULL2": {highHalf: true}, + "VUMLAL": {accumulate: "add"}, "VUMLAL2": {accumulate: "add", highHalf: true}, + "VUMLSL": {accumulate: "sub"}, "VUMLSL2": {accumulate: "sub", highHalf: true}, + }[op] + if !handled { + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) || len(ins.Args) != 3 { + return true, false, fmt.Errorf("arm64 %s expects two narrow sources, one wide destination, and no suffix: %q", op, ins.Raw) + } + for _, arg := range ins.Args { + if arg.Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s accepts only vector registers: %q", op, ins.Raw) + } + } + firstArrangement, firstOK := parseARM64VectorArrangement(ins.Args[0].Reg) + laneKind, lane, laneForm := arm64ParseVRegLane(ins.Args[0].Reg) + secondArrangement, secondOK := parseARM64VectorArrangement(ins.Args[1].Reg) + destinationArrangement, destinationOK := parseARM64VectorArrangement(ins.Args[2].Reg) + wantSourceLanes := destinationArrangement.lanes + if spec.highHalf { + wantSourceLanes *= 2 + } + if laneForm { + sourceBits := 0 + switch laneKind { + case 'H': + sourceBits = 16 + case 'S': + sourceBits = 32 + } + laneRegister, laneRegisterOK := arm64ParseVReg(ins.Args[0].Reg) + physicalLanes := 0 + if sourceBits != 0 { + physicalLanes = 128 / sourceBits + } + firstArrangement = arm64VectorArrangement{elementBits: sourceBits, lanes: destinationArrangement.lanes} + firstOK = sourceBits != 0 && lane >= 0 && lane < physicalLanes && laneRegisterOK && + (sourceBits != 16 || laneRegister <= 15) + } + if !firstOK || !secondOK || !destinationOK || + firstArrangement.elementBits != secondArrangement.elementBits || + firstArrangement.elementBits*2 != destinationArrangement.elementBits || + secondArrangement.lanes != wantSourceLanes || + (!laneForm && firstArrangement != secondArrangement) || + destinationArrangement.lanes*destinationArrangement.elementBits != 128 { + return true, false, fmt.Errorf("arm64 %s arrangements do not form a B->H, H->S, or S->D widening multiply row: %q", op, ins.Raw) + } + var first string + if laneForm { + physical := arm64VectorArrangement{elementBits: firstArrangement.elementBits, lanes: 128 / firstArrangement.elementBits} + loaded, err := c.loadARM64VectorInteger(ins.Args[0].Reg, physical) + if err != nil { + return true, false, err + } + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", element, physical.lanes, physical.elementBits, loaded, lane) + first = "poison" + for index := 0; index < destinationArrangement.lanes; index++ { + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %%%s, i32 %d\n", + inserted, destinationArrangement.lanes, firstArrangement.elementBits, first, + firstArrangement.elementBits, element, index) + first = "%" + inserted + } + } else { + var err error + first, err = c.loadARM64VectorInteger(ins.Args[0].Reg, firstArrangement) + if err != nil { + return true, false, err + } + } + second, err := c.loadARM64VectorInteger(ins.Args[1].Reg, secondArrangement) + if err != nil { + return true, false, err + } + if spec.highHalf { + if !laneForm { + first = c.selectARM64VectorHighHalf(firstArrangement, destinationArrangement.lanes, first) + } + second = c.selectARM64VectorHighHalf(secondArrangement, destinationArrangement.lanes, second) + } + narrowType := fmt.Sprintf("<%d x i%d>", destinationArrangement.lanes, firstArrangement.elementBits) + wideType := fmt.Sprintf("<%d x i%d>", destinationArrangement.lanes, destinationArrangement.elementBits) + extension := "zext" + if spec.signed { + extension = "sext" + } + wideFirst := c.newTmp() + wideSecond := c.newTmp() + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", wideFirst, extension, narrowType, first, wideType) + fmt.Fprintf(c.b, " %%%s = %s %s %s to %s\n", wideSecond, extension, narrowType, second, wideType) + fmt.Fprintf(c.b, " %%%s = mul %s %%%s, %%%s\n", product, wideType, wideFirst, wideSecond) + result := "%" + product + if spec.accumulate != "" { + accumulator, err := c.loadARM64VectorInteger(ins.Args[2].Reg, destinationArrangement) + if err != nil { + return true, false, err + } + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %%%s\n", combined, spec.accumulate, wideType, accumulator, product) + result = "%" + combined + } + return true, false, c.storeARM64VectorInteger(ins.Args[2].Reg, destinationArrangement, result) +} + +func (c *arm64Ctx) selectARM64VectorHighHalf(arrangement arm64VectorArrangement, resultLanes int, value string) string { + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %s, <%d x i%d> poison, <%d x i32> <", + selected, arrangement.lanes, arrangement.elementBits, value, arrangement.lanes, arrangement.elementBits, resultLanes) + for lane := 0; lane < resultLanes; lane++ { + if lane != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", resultLanes+lane) + } + c.b.WriteString(">\n") + return "%" + selected +} diff --git a/arm64_lower_widening_multiply_test.go b/arm64_lower_widening_multiply_test.go new file mode 100644 index 00000000..abad9840 --- /dev/null +++ b/arm64_lower_widening_multiply_test.go @@ -0,0 +1,265 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64VectorWideningMultiplyCompleteGoAssemblerForms(t *testing.T) { + type form struct{ narrow, wide string } + lowForms := []form{{"B8", "H8"}, {"H4", "S4"}, {"S2", "D2"}} + highForms := []form{{"B16", "H8"}, {"H8", "S4"}, {"S4", "D2"}} + var source strings.Builder + source.WriteString("TEXT ·vectorWideningMultiplyForms(SB), $0-0\n") + for _, op := range []string{"VSMULL", "VSMLAL", "VSMLSL", "VUMULL", "VUMLAL", "VUMLSL"} { + for _, form := range lowForms { + fmt.Fprintf(&source, "\t%s V0.%s, V1.%s, V31.%s\n", op, form.narrow, form.narrow, form.wide) + } + for _, form := range highForms { + fmt.Fprintf(&source, "\t%s2 V2.%s, V3.%s, V30.%s\n", op, form.narrow, form.narrow, form.wide) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "vectorWideningMultiplyForms": {Name: "vectorWideningMultiplyForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{"sext <", "zext <", "mul <", "add <", "sub <", "shufflevector <"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s widening-multiply IR omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vector-widening-multiply.ll", "arm64-vector-widening-multiply.o", ll) + } +} + +func TestTranslateARM64RawWideningMultiplyByElementCompleteArchitecturalForms(t *testing.T) { + type operation struct { + name string + base uint32 + } + operations := []operation{ + {"SMLAL", 0x0f002000}, {"SMLAL2", 0x4f002000}, + {"SMLSL", 0x0f006000}, {"SMLSL2", 0x4f006000}, + {"SMULL", 0x0f00a000}, {"SMULL2", 0x4f00a000}, + {"UMLAL", 0x2f002000}, {"UMLAL2", 0x6f002000}, + {"UMLSL", 0x2f006000}, {"UMLSL2", 0x6f006000}, + {"UMULL", 0x2f00a000}, {"UMULL2", 0x6f00a000}, + } + var source strings.Builder + source.WriteString("TEXT rawwideningmultiplyelementforms(SB),$0-0\n") + for _, operation := range operations { + for _, size := range []int{1, 2} { + laneCount := 8 + laneRegister := 15 + if size == 2 { + laneCount = 4 + laneRegister = 31 + } + for lane := 0; lane < laneCount; lane++ { + word := encodeARM64RawWideningMultiplyByElement(operation.base, size, lane, 30, laneRegister, 29) + if strings.HasPrefix(operation.name, "UMULL") { + form, ok := decodeARM64RawUMULL(word) + if !ok || !form.byElement || form.element != lane || form.first != 30 || form.second != laneRegister || form.destReg != 29 { + t.Fatalf("decode UMULL by-element %#08x = %#v, %v; want lane=%d first=30 second=%d destination=29", word, form, ok, lane, laneRegister) + } + } + fmt.Fprintf(&source, "\tWORD $%#08x // %s size=%d lane=%d\n", word, operation.name, size, lane) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawwideningmultiplyelementforms": {Name: "rawwideningmultiplyelementforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"extractelement <8 x i16>", "extractelement <4 x i32>", "sext <", "zext <", "mul <", "add <", "sub <"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw widening-multiply by-element family for %s omitted %q:\n%s", triple, want, ir) + } + } + compileLLVMToObject(t, llc, triple, "arm64-raw-widening-multiply-element.ll", "arm64-raw-widening-multiply-element.o", ir) + }) + } +} + +func encodeARM64RawWideningMultiplyByElement(base uint32, size, lane, sourceReg, laneReg, destinationReg int) uint32 { + word := base | uint32(size)<<22 | uint32(sourceReg)<<5 | uint32(destinationReg) + if size == 1 { + word |= uint32(laneReg&15) << 16 + word |= uint32(lane&1) << 20 + word |= uint32((lane>>1)&1) << 21 + word |= uint32((lane>>2)&1) << 11 + return word + } + word |= uint32(laneReg&15) << 16 + word |= uint32((laneReg>>4)&1) << 20 + word |= uint32(lane&1) << 21 + word |= uint32((lane>>1)&1) << 11 + return word +} + +func TestARM64RawWideningMultiplyByElementRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + words := []uint32{ + encodeARM64RawWideningMultiplyByElement(0x0f002000, 1, 0, 0, 1, 2), // SMLAL H4. + encodeARM64RawWideningMultiplyByElement(0x4f002000, 1, 7, 0, 1, 2), // SMLAL2 H8. + encodeARM64RawWideningMultiplyByElement(0x2f006000, 2, 3, 0, 1, 2), // UMLSL S2. + encodeARM64RawWideningMultiplyByElement(0x6f00a000, 2, 2, 0, 1, 2), // UMULL2 S4. + } + source := fmt.Sprintf(` +TEXT rawwideningmultiplyelement(SB),$0-32 + MOVD source+0(FP), R0 + MOVD elements+8(FP), R1 + MOVD accumulator+16(FP), R2 + MOVD output+24(FP), R3 + VLD1 (R0), [V0.B16] + VLD1 (R1), [V1.B16] + VLD1 (R2), [V2.B16] + WORD $%#08x + VST1 [V2.B16], (R3) + ADD $16, R3 + VLD1 (R2), [V2.B16] + WORD $%#08x + VST1 [V2.B16], (R3) + ADD $16, R3 + VLD1 (R2), [V2.B16] + WORD $%#08x + VST1 [V2.B16], (R3) + ADD $16, R3 + VLD1 (R2), [V2.B16] + WORD $%#08x + VST1 [V2.B16], (R3) + RET +`, words[0], words[1], words[2], words[3]) + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawwideningmultiplyelement": { + Name: "rawwideningmultiplyelement", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void rawwideningmultiplyelement(const void *, const void *, const void *, void *); +int main(void) { + const uint16_t source_h[8] = {0xffff,2,0xfffd,4,0xfffb,6,0xfff9,8}; + const uint16_t element_h[8] = {3,4,5,6,7,8,9,0xfff6}; + const uint32_t accumulator_s[4] = {10,20,30,40}; + uint8_t got[64] = {0}; + uint8_t want[64] = {0}; + rawwideningmultiplyelement(source_h, element_h, accumulator_s, got); + int32_t *want_s0 = (int32_t *)(want + 0); + int32_t *want_s1 = (int32_t *)(want + 16); + for (int i = 0; i < 4; i++) { + want_s0[i] = (int32_t)accumulator_s[i] + (int16_t)source_h[i] * (int16_t)element_h[0]; + want_s1[i] = (int32_t)accumulator_s[i] + (int16_t)source_h[i + 4] * (int16_t)element_h[7]; + } + const uint32_t *source_s = (const uint32_t *)source_h; + const uint32_t *element_s = (const uint32_t *)element_h; + const uint64_t *accumulator_d = (const uint64_t *)accumulator_s; + uint64_t *want_d0 = (uint64_t *)(want + 32); + uint64_t *want_d1 = (uint64_t *)(want + 48); + for (int i = 0; i < 2; i++) { + want_d0[i] = accumulator_d[i] - (uint64_t)source_s[i] * element_s[3]; + want_d1[i] = (uint64_t)source_s[i + 2] * element_s[2]; + } + for (int i = 0; i < 64; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_widening_multiply_element", triple, ir, mainC, nil) +} + +func TestTranslateARM64VectorWideningMultiplyRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VUMULL V0.B16, V1.B16, V2.H8", + "VUMULL2 V0.B8, V1.B8, V2.H8", + "VUMLAL V0.H4, V1.H4, V2.H4", + "VUMLSL V0.H8, V1.H8, V2.S4", + "VSMULL V0.D1, V1.D1, V2.D2", + "VSMLAL V0.S2, V1.S2, V2.S2", + "VSMLSL2 V0.B8, V1.B8, V2.H8", + "VUMULL.P V0.B8, V1.B8, V2.H8", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT ·badVectorWideningMultiply(SB), $0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, false) + file, err := Parse(ArchARM64, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badVectorWideningMultiply": {Name: "badVectorWideningMultiply", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's vector widening-multiply forms", instruction) + } + }) + } +} diff --git a/arm64_lower_widening_shift.go b/arm64_lower_widening_shift.go new file mode 100644 index 00000000..c612cc33 --- /dev/null +++ b/arm64_lower_widening_shift.go @@ -0,0 +1,96 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *arm64Ctx) lowerARM64WideningShift(op Op, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "VUSHLL", "VUSHLL2", "VSSHLL", "VSSHLL2", "VUXTL", "VUXTL2", "VSXTL", "VSXTL2": + default: + return false, false, nil + } + if strings.ToUpper(string(ins.Op)) != string(op) { + return true, false, fmt.Errorf("arm64 %s does not accept an opcode suffix: %q", op, ins.Raw) + } + isExtendAlias := strings.Contains(string(op), "XTL") + wantArgs := 3 + if isExtendAlias { + wantArgs = 2 + } + if len(ins.Args) != wantArgs { + return true, false, fmt.Errorf("arm64 %s expects %d operands: %q", op, wantArgs, ins.Raw) + } + shift := int64(0) + sourceIndex := 0 + if !isExtendAlias { + if ins.Args[0].Kind != OpImm { + return true, false, fmt.Errorf("arm64 %s expects an immediate shift: %q", op, ins.Raw) + } + shift = ins.Args[0].Imm + sourceIndex = 1 + } + if ins.Args[sourceIndex].Kind != OpReg || ins.Args[sourceIndex+1].Kind != OpReg { + return true, false, fmt.Errorf("arm64 %s expects vector register source and destination: %q", op, ins.Raw) + } + sourceArrangement, valid := parseARM64VectorArrangement(ins.Args[sourceIndex].Reg) + if !valid { + return true, false, fmt.Errorf("arm64 %s has an invalid source arrangement: %q", op, ins.Raw) + } + destinationArrangement, valid := parseARM64VectorArrangement(ins.Args[sourceIndex+1].Reg) + if !valid { + return true, false, fmt.Errorf("arm64 %s has an invalid destination arrangement: %q", op, ins.Raw) + } + highHalf := strings.HasSuffix(string(op), "2") + wantSourceLanes := destinationArrangement.lanes + if highHalf { + wantSourceLanes *= 2 + } + if sourceArrangement.lanes != wantSourceLanes || + destinationArrangement.elementBits != sourceArrangement.elementBits*2 || + destinationArrangement.lanes*destinationArrangement.elementBits != 128 { + return true, false, fmt.Errorf("arm64 %s source and destination arrangements do not form a widening pair: %q", op, ins.Raw) + } + if shift < 0 || shift >= int64(sourceArrangement.elementBits) { + return true, false, fmt.Errorf("arm64 %s shift must be in [0,%d]: %q", op, sourceArrangement.elementBits-1, ins.Raw) + } + + source, err := c.loadARM64VectorInteger(ins.Args[sourceIndex].Reg, sourceArrangement) + if err != nil { + return true, false, err + } + if highHalf { + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %s, <%d x i%d> poison, <%d x i32> <", selected, sourceArrangement.lanes, sourceArrangement.elementBits, source, sourceArrangement.lanes, sourceArrangement.elementBits, destinationArrangement.lanes) + for i := 0; i < destinationArrangement.lanes; i++ { + if i != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", destinationArrangement.lanes+i) + } + c.b.WriteString(">\n") + source = "%" + selected + } + + extended := c.newTmp() + extension := "zext" + if strings.HasPrefix(string(op), "VS") { + extension = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s <%d x i%d> %s to <%d x i%d>\n", extended, extension, destinationArrangement.lanes, sourceArrangement.elementBits, source, destinationArrangement.lanes, destinationArrangement.elementBits) + result := "%" + extended + if !isExtendAlias { + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl <%d x i%d> %s, <", shifted, destinationArrangement.lanes, destinationArrangement.elementBits, result) + for i := 0; i < destinationArrangement.lanes; i++ { + if i != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i%d %d", destinationArrangement.elementBits, shift) + } + c.b.WriteString(">\n") + result = "%" + shifted + } + return true, false, c.storeARM64VectorInteger(ins.Args[sourceIndex+1].Reg, destinationArrangement, result) +} diff --git a/arm64_lower_widening_shift_test.go b/arm64_lower_widening_shift_test.go new file mode 100644 index 00000000..dcb47de9 --- /dev/null +++ b/arm64_lower_widening_shift_test.go @@ -0,0 +1,124 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strconv" + "strings" + "testing" +) + +func TestTranslateARM64WideningShiftCompleteGoAssemblerForms(t *testing.T) { + type form struct { + source string + destination string + maxShift int + } + low := []form{{"B8", "H8", 7}, {"H4", "S4", 15}, {"S2", "D2", 31}} + high := []form{{"B16", "H8", 7}, {"H8", "S4", 15}, {"S4", "D2", 31}} + var src strings.Builder + src.WriteString("TEXT ·wideningforms(SB), $0-0\n") + for _, signed := range []bool{false, true} { + prefix := "VU" + if signed { + prefix = "VS" + } + for _, variant := range []struct { + suffix string + forms []form + }{{"", low}, {"2", high}} { + for _, form := range variant.forms { + for _, shift := range []int{0, form.maxShift} { + fmt.Fprintf(&src, "\t%sSHLL%s $%d, V0.%s, V1.%s\n", prefix, variant.suffix, shift, form.source, form.destination) + } + fmt.Fprintf(&src, "\t%sXTL%s V0.%s, V1.%s\n", prefix, variant.suffix, form.source, form.destination) + } + } + } + src.WriteString("\tRET\n") + if currentGoMinorAtLeast(27) { + requireARM64GoAssemblerResult(t, src.String(), true) + } + + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "wideningforms": {Name: "wideningforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for operation, want := range map[string]int{"zext <": 18, "sext <": 18, "shl <": 24} { + if got := strings.Count(ll, operation); got != want { + t.Fatalf("%s emitted %d %q operations, want %d:\n%s", triple, got, operation, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-widening-shift.ll", "arm64-widening-shift.o", ll) + } +} + +func TestTranslateARM64WideningShiftRejectsFormsOutsideGoAssemblerTable(t *testing.T) { + for _, instruction := range []string{ + "VUSHLL $8, V0.B8, V1.H8", + "VSSHLL $-1, V0.H4, V1.S4", + "VUSHLL2 $0, V0.B8, V1.H8", + "VSSHLL2 $0, V0.B16, V1.S4", + "VUXTL V0.B16, V1.H8", + "VSXTL2 V0.H4, V1.S4", + "VUXTL $0, V0.B8, V1.H8", + "VSSHLL.P $0, V0.B8, V1.H8", + } { + t.Run(strings.Fields(instruction)[0]+"-"+strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT ·badwidening(SB), $0-0\n\t" + instruction + "\n\tRET\n" + if currentGoMinorAtLeast(27) { + requireARM64GoAssemblerResult(t, src, false) + } + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "badwidening": {Name: "badwidening", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's widening optab", instruction) + } + }) + } +} + +func currentGoMinorAtLeast(want int) bool { + version := runtime.Version() + start := strings.Index(version, "go1.") + if start < 0 { + return false + } + minor := version[start+len("go1."):] + if end := strings.IndexFunc(minor, func(r rune) bool { return r < '0' || r > '9' }); end >= 0 { + minor = minor[:end] + } + got, err := strconv.Atoi(minor) + return err == nil && got >= want +} diff --git a/arm64_lower_word.go b/arm64_lower_word.go index fc79f7df..409b762e 100644 --- a/arm64_lower_word.go +++ b/arm64_lower_word.go @@ -2,15 +2,199 @@ package plan9asm import "fmt" -// lowerRawWord models the small set of flag-writing instructions emitted as -// raw encodings by generated Go assembly. Unknown WORD values remain ignored, -// matching the translator's existing permissive behavior for embedded opcodes. +// lowerRawWord models raw encodings only when their register and flag effects +// are known. Silently emitting nothing for an unknown machine instruction +// would report success while changing program semantics. func (c *arm64Ctx) lowerRawWord(ins Instr) error { if len(ins.Args) != 1 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { - return nil + return fmt.Errorf("arm64 WORD expects exactly one resolved integer constant: %q", ins.Raw) } word := uint32(ins.Args[0].Imm) + if form, ok := decodeARM64RawSystemRegister(word); ok { + return c.lowerRawSystemRegister(form) + } + if immediate, ok := decodeARM64RawHint(word); ok { + c.emitARM64Hint(immediate) + return nil + } + if form, ok := decodeARM64RawCASP(word); ok { + return c.lowerRawCASP(form) + } + if form, ok := decodeARM64RawAES(word); ok { + return c.lowerRawAES(form) + } + if form, ok := decodeARM64RawDotProduct(word); ok { + return c.lowerRawDotProduct(form) + } + if form, ok := decodeARM64RawMatrixMultiply(word); ok { + return c.lowerRawMatrixMultiply(form) + } + if form, ok := decodeARM64RawFloatMultiplyLong(word); ok { + return c.lowerRawFloatMultiplyLong(form) + } + if form, ok := decodeARM64RawTableLookup(word); ok { + return c.lowerRawTableLookup(form) + } + if form, ok := decodeARM64RawSQRDMULH(word); ok { + return c.lowerRawSQRDMULH(form) + } + if form, ok := decodeARM64RawSQDMULH(word); ok { + return c.lowerRawSQDMULH(form) + } + if form, ok := decodeARM64RawMUL(word); ok { + return c.lowerRawMUL(form) + } + if form, ok := decodeARM64RawSHSUB(word); ok { + return c.lowerRawSHSUB(form) + } + if form, ok := decodeARM64RawCMGT(word); ok { + return c.lowerRawCMGT(form) + } + if form, ok := decodeARM64RawMLS(word); ok { + return c.lowerRawMLS(form) + } + if form, ok := decodeARM64RawPairwiseAddLong(word); ok { + return c.lowerRawPairwiseAddLong(form) + } + if form, ok := decodeARM64RawUMULL(word); ok { + return c.lowerRawUMULL(form) + } + if form, ok := decodeARM64RawUZP(word); ok { + return c.lowerRawUZP(form) + } + if form, ok := decodeARM64RawSaturatingShiftNarrow(word); ok { + return c.lowerRawSaturatingShiftNarrow(form) + } + if form, ok := decodeARM64RawUHADD(word); ok { + return c.lowerRawUHADD(form) + } + if form, ok := decodeARM64RawUSHLL(word); ok { + return c.lowerRawUSHLL(form) + } + if form, ok := decodeARM64RawStructureLane(word); ok { + return c.lowerRawStructureLane(form) + } + if form, ok := decodeARM64RawLDnR(word); ok { + return c.lowerRawLDnR(form) + } + if form, ok := decodeARM64RawUMLAL(word); ok { + return c.lowerRawUMLAL(form) + } + if form, ok := decodeARM64RawDUPElement(word); ok { + return c.lowerRawDUPElement(form) + } + if form, ok := decodeARM64RawMLA(word); ok { + return c.lowerRawMLA(form) + } + if form, ok := decodeARM64RawCVTF(word); ok { + return c.lowerRawCVTF(form) + } + if form, ok := decodeARM64RawFMLA(word); ok { + return c.lowerRawFMLA(form) + } + if form, ok := decodeARM64RawFMULByElement(word); ok { + return c.lowerRawFMULByElement(form) + } + if form, ok := decodeARM64RawVectorFloatRound(word); ok { + return c.lowerRawVectorFloatRound(form) + } + if form, ok := decodeARM64RawVectorFloatNarrow(word); ok { + return c.lowerRawVectorFloatNarrow(form) + } + if form, ok := decodeARM64RawVectorFloatWiden(word); ok { + return c.lowerRawVectorFloatWiden(form) + } + if form, ok := decodeARM64RawFADDP(word); ok { + return c.lowerRawFADDP(form) + } + if form, ok := decodeARM64RawFloatPairwiseMinMax(word); ok { + return c.lowerRawFloatPairwiseMinMax(form) + } + if form, ok := decodeARM64RawFloatBinary(word); ok { + return c.lowerRawFloatBinary(form) + } + if form, ok := decodeARM64RawFSQRT(word); ok { + return c.lowerRawFSQRT(form) + } + if form, ok := decodeARM64RawFloatAbsNeg(word); ok { + return c.lowerRawFloatAbsNeg(form) + } + if form, ok := decodeARM64RawFloatCompare(word); ok { + return c.lowerRawFloatCompare(form) + } + if form, ok := decodeARM64RawLogical(word); ok { + return c.lowerRawLogical(form) + } + if form, ok := decodeARM64RawModifiedImmediate(word); ok { + return c.lowerRawModifiedImmediate(form) + } + if form, ok := decodeARM64RawFCVTZ(word); ok { + return c.lowerRawFCVTZ(form) + } + if form, ok := decodeARM64RawMoveWide(word); ok { + return c.lowerRawMoveWide(form) + } + if form, ok := decodeARM64RawSVEAddress(word); ok { + return c.lowerRawSVEAddress(form) + } + if form, ok := decodeARM64RawSVECnt(word); ok { + return c.lowerRawSVECnt(form) + } + if form, ok := decodeARM64RawBitfield(word); ok { + return c.lowerRawBitfield(form) + } + if form, ok := decodeARM64RawSVEPTrue(word); ok { + return c.lowerRawSVEPTrue(form) + } + if form, ok := decodeARM64RawSVELDST1D(word); ok { + return c.lowerRawSVELDST1D(form) + } + if form, ok := decodeARM64RawSVELDST1W(word); ok { + return c.lowerRawSVELDST1W(form) + } + if form, ok := decodeARM64RawSVEFloat(word); ok { + return c.lowerRawSVEFloat(form) + } + if form, ok := decodeARM64RawSVELoadStore(word); ok { + return c.lowerRawSVELoadStore(form) + } + if form, ok := decodeARM64RawSVEDupImmediate(word); ok { + return c.lowerRawSVEDupImmediate(form) + } + if form, ok := decodeARM64RawSVEDupGeneral(word); ok { + return c.lowerRawSVEDupGeneral(form) + } + if form, ok := decodeARM64RawSVEDupElement(word); ok { + return c.lowerRawSVEDupElement(form) + } + if form, ok := decodeARM64RawSVEAdd(word); ok { + return c.lowerRawSVEAdd(form) + } + if form, ok := decodeARM64RawSVELSR(word); ok { + return c.lowerRawSVELSR(form) + } + if form, ok := decodeARM64RawSVESelect(word); ok { + return c.lowerRawSVESelect(form) + } + if form, ok := decodeARM64RawSVEMultiply(word); ok { + return c.lowerRawSVEMultiply(form) + } + if form, ok := decodeARM64RawSVEEOR(word); ok { + return c.lowerRawSVEEOR(form) + } + if form, ok := decodeARM64RawSVETable(word); ok { + return c.lowerRawSVETable(form) + } + if form, ok := decodeARM64RawSVEUMULLB(word); ok { + return c.lowerRawSVEUMULLB(form) + } + if form, ok := decodeARM64RawSVEMultiplyAccumulateLong(word); ok { + return c.lowerRawSVEMultiplyAccumulateLong(form) + } + if form, ok := decodeARM64RawSVEPermute(word); ok { + return c.lowerRawSVEPermute(form) + } switch { case word == 0xea00001f: // TST X0, X0 (ANDS XZR, X0, X0) value, err := c.loadReg("R0") @@ -49,5 +233,5 @@ func (c *arm64Ctx) lowerRawWord(ins Instr) error { return nil } - return nil + return fmt.Errorf("unsupported ARM64 WORD encoding %#08x: %q", word, ins.Raw) } diff --git a/arm64_lower_word_bitfield.go b/arm64_lower_word_bitfield.go new file mode 100644 index 00000000..896d38d5 --- /dev/null +++ b/arm64_lower_word_bitfield.go @@ -0,0 +1,103 @@ +package plan9asm + +import "fmt" + +type arm64RawBitfield struct { + op Op + width int + immr int + imms int + source int + destination int +} + +func decodeARM64RawBitfield(word uint32) (arm64RawBitfield, bool) { + if word&0x1f800000 != 0x13000000 { + return arm64RawBitfield{}, false + } + var op Op + switch (word >> 29) & 3 { + case 0: + op = "SBFM" + case 1: + op = "BFM" + case 2: + op = "UBFM" + default: + return arm64RawBitfield{}, false + } + width := 32 + n := word&(1<<22) != 0 + if word&(1<<31) != 0 { + width = 64 + if !n { + return arm64RawBitfield{}, false + } + } else if n { + return arm64RawBitfield{}, false + } + immr := int(word>>16) & 63 + imms := int(word>>10) & 63 + if width == 32 && (immr >= 32 || imms >= 32) { + return arm64RawBitfield{}, false + } + return arm64RawBitfield{ + op: op, + width: width, + immr: immr, + imms: imms, + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawBitfield(form arm64RawBitfield) error { + // Rd=31 is WZR/XZR for bitfield instructions, so the result is discarded. + if form.destination == 31 { + return nil + } + source := Reg(fmt.Sprintf("R%d", form.source)) + if form.source == 31 { + source = ZR + } + destination := Reg(fmt.Sprintf("R%d", form.destination)) + var alias Op + var lsb, width int + if form.imms >= form.immr { + lsb = form.immr + width = form.imms - form.immr + 1 + switch form.op { + case "SBFM": + alias = "SBFX" + case "BFM": + alias = "BFXIL" + case "UBFM": + alias = "UBFX" + } + } else { + lsb = form.width - form.immr + width = form.imms + 1 + switch form.op { + case "SBFM": + alias = "SBFIZ" + case "BFM": + alias = "BFI" + case "UBFM": + alias = "UBFIZ" + } + } + if form.width == 32 { + alias += "W" + } + ins := Instr{ + Op: alias, + Raw: fmt.Sprintf("decoded ARM64 WORD as %s alias %s", form.op, alias), + Args: []Operand{ + {Kind: OpImm, Imm: int64(lsb)}, + {Kind: OpReg, Reg: source}, + {Kind: OpImm, Imm: int64(width)}, + {Kind: OpReg, Reg: destination}, + }, + } + return c.lowerBitfield(alias, ins) +} diff --git a/arm64_lower_word_bitfield_test.go b/arm64_lower_word_bitfield_test.go new file mode 100644 index 00000000..74a8e06a --- /dev/null +++ b/arm64_lower_word_bitfield_test.go @@ -0,0 +1,152 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func encodeARM64RawBitfield(opc uint32, width, immr, imms, source, destination int) uint32 { + word := uint32(0x13000000) | opc<<29 | uint32(immr)<<16 | uint32(imms)<<10 | uint32(source)<<5 | uint32(destination) + if width == 64 { + word |= 1<<31 | 1<<22 + } + return word +} + +func TestTranslateARM64RawBitfieldCompleteFormats(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawbitfieldforms(SB),$0-0\n") + for _, opc := range []uint32{0, 1, 2} { // SBFM, BFM, UBFM. + for _, width := range []int{32, 64} { + for _, immediates := range [][2]int{{0, 0}, {0, width - 1}, {width - 1, 0}, {width - 1, width - 1}, {3, 17}, {width - 3, 11}} { + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawBitfield(opc, width, immediates[0], immediates[1], 1, 2)) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawbitfieldforms": {Name: "rawbitfieldforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-bitfield.ll", "arm64-raw-bitfield.o", ll) + }) + } +} + +func TestARM64RawBitfieldDecoderCoversEntireImmediateDomain(t *testing.T) { + operations := []Op{"SBFM", "BFM", "UBFM"} + for opc, operation := range operations { + for _, width := range []int{32, 64} { + for immr := 0; immr < width; immr++ { + for imms := 0; imms < width; imms++ { + word := encodeARM64RawBitfield(uint32(opc), width, immr, imms, 29, 30) + got, ok := decodeARM64RawBitfield(word) + if !ok { + t.Fatalf("decoder rejected %s width=%d immr=%d imms=%d", operation, width, immr, imms) + } + if got.op != operation || got.width != width || got.immr != immr || got.imms != imms || got.source != 29 || got.destination != 30 { + t.Fatalf("decoded word %#08x as %+v", word, got) + } + } + } + } + } +} + +func TestARM64RawBitfieldRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + var source strings.Builder + source.WriteString("TEXT rawbitfield(SB),$0-24\n\tMOVD out+0(FP), R0\n\tMOVD input+8(FP), R1\n\tMOVD initial+16(FP), R2\n") + words := []uint32{ + encodeARM64RawBitfield(2, 64, 61, 60, 1, 3), // LSL #3. + encodeARM64RawBitfield(2, 64, 8, 63, 1, 4), // LSR #8. + encodeARM64RawBitfield(2, 64, 8, 15, 1, 5), // UBFX #8, #8. + encodeARM64RawBitfield(2, 64, 56, 7, 1, 6), // UBFIZ #8, #8. + encodeARM64RawBitfield(0, 64, 8, 63, 1, 7), // ASR #8. + encodeARM64RawBitfield(0, 64, 32, 39, 1, 8), // SBFX #32, #8. + } + for _, word := range words { + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + source.WriteString("\tMOVD R2, R9\n\tMOVD R2, R10\n") + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawBitfield(1, 64, 0, 7, 1, 9)) // BFXIL #0, #8. + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawBitfield(1, 64, 56, 7, 1, 10)) // BFI #8, #8. + for i, reg := range []int{3, 4, 5, 6, 7, 8, 9, 10} { + fmt.Fprintf(&source, "\tMOVD R%d, %d(R0)\n", reg, i*8) + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawbitfield": { + Name: "rawbitfield", Args: []LLVMType{Ptr, I64, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + {Offset: 16, Type: I64, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawbitfield(uint64_t *, uint64_t, uint64_t); +int main(void) { + uint64_t got[8] = {0}; + rawbitfield(got, UINT64_C(0xfedcba9876543210), UINT64_C(0x1111222233334444)); + const uint64_t want[8] = { + UINT64_C(0xf6e5d4c3b2a19080), UINT64_C(0x00fedcba98765432), UINT64_C(0x32), UINT64_C(0x1000), + UINT64_C(0xfffedcba98765432), UINT64_C(0xffffffffffffff98), UINT64_C(0x1111222233334410), UINT64_C(0x1111222233331044), + }; + for (int i = 0; i < 8; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_bitfield", triple, ll, mainC, nil) +} + +func TestARM64RawBitfieldDecoderRejectsReservedAndAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{ + encodeARM64RawBitfield(3, 64, 0, 0, 0, 0), // reserved opc. + encodeARM64RawBitfield(2, 32, 32, 0, 0, 0), + encodeARM64RawBitfield(2, 32, 0, 32, 0, 0), + 0x12000000, // logical immediate. + } { + if _, ok := decodeARM64RawBitfield(word); ok { + t.Fatalf("bitfield decoder accepted reserved/adjacent encoding %#08x", word) + } + } +} diff --git a/arm64_lower_word_casp.go b/arm64_lower_word_casp.go new file mode 100644 index 00000000..5eb1de20 --- /dev/null +++ b/arm64_lower_word_casp.go @@ -0,0 +1,63 @@ +package plan9asm + +import "fmt" + +type arm64RawCASP struct { + elementBits int + acquire bool + release bool + expected int + newValue int + base int +} + +func decodeARM64RawCASP(word uint32) (arm64RawCASP, bool) { + const variable = uint32(1<<30 | 1<<22 | 1<<15 | 0x1e<<16 | 31<<5 | 0x1e) + if word&^variable != 0x08207c00 { + return arm64RawCASP{}, false + } + elementBits := 32 + if word&(1<<30) != 0 { + elementBits = 64 + } + return arm64RawCASP{ + elementBits: elementBits, + acquire: word&(1<<22) != 0, + release: word&(1<<15) != 0, + expected: int(word>>16) & 31, + newValue: int(word) & 31, + base: int(word>>5) & 31, + }, true +} + +func arm64RawCASPRegisterPair(first int) []Reg { + second := Reg(fmt.Sprintf("R%d", first+1)) + if first == 30 { + second = ZR + } + return []Reg{Reg(fmt.Sprintf("R%d", first)), second} +} + +func (c *arm64Ctx) lowerRawCASP(form arm64RawCASP) error { + base := Reg(fmt.Sprintf("R%d", form.base)) + if form.base == 31 { + base = Reg("RSP") + } + ptr, err := c.atomicPairMemPtr(MemRef{Base: base}, false) + if err != nil { + return err + } + successOrder, failureOrder := "monotonic", "monotonic" + if form.acquire && form.release { + successOrder, failureOrder = "acq_rel", "acquire" + } else if form.acquire { + successOrder, failureOrder = "acquire", "acquire" + } else if form.release { + successOrder = "release" + } + return c.lowerAtomicPairCompareExchange( + arm64RawCASPRegisterPair(form.expected), + arm64RawCASPRegisterPair(form.newValue), + form.elementBits, ptr, successOrder, failureOrder, + ) +} diff --git a/arm64_lower_word_casp_test.go b/arm64_lower_word_casp_test.go new file mode 100644 index 00000000..8e1e4c5b --- /dev/null +++ b/arm64_lower_word_casp_test.go @@ -0,0 +1,150 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func arm64EncodeRawCASP(bits int, acquire, release bool, expected, newValue, base int) uint32 { + word := uint32(0x08207c00) + if bits == 64 { + word |= 1 << 30 + } + if acquire { + word |= 1 << 22 + } + if release { + word |= 1 << 15 + } + return word | uint32(expected)<<16 | uint32(base)<<5 | uint32(newValue) +} + +func TestTranslateARM64RawCASPCompleteArchitecturalFormats(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawcaspforms(SB),$0-0\n") + for _, bits := range []int{32, 64} { + for _, order := range []struct{ acquire, release bool }{ + {}, {acquire: true}, {release: true}, {acquire: true, release: true}, + } { + for _, registers := range []struct{ expected, newValue, base int }{{0, 2, 4}, {30, 28, 31}} { + word := arm64EncodeRawCASP(bits, order.acquire, order.release, registers.expected, registers.newValue, registers.base) + decoded, ok := decodeARM64RawCASP(word) + if !ok || decoded.elementBits != bits || decoded.acquire != order.acquire || decoded.release != order.release || + decoded.expected != registers.expected || decoded.newValue != registers.newValue || decoded.base != registers.base { + t.Fatalf("decode CASP word %#08x = %+v, ok=%v", word, decoded, ok) + } + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawcaspforms": {Name: "rawcaspforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, ordering := range []string{"monotonic monotonic", "acquire acquire", "release monotonic", "acq_rel acquire"} { + if !strings.Contains(ir, ordering) { + t.Fatalf("raw CASP lowering for %s omitted %q:\n%s", triple, ordering, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-casp.ll", "arm64-raw-casp.o", ir) + }) + } +} + +func TestARM64RawCASPDecoderRejectsAdjacentAndInvalidPairs(t *testing.T) { + for _, word := range []uint32{ + 0x08217c02, // odd expected-pair start. + 0x08207c01, // odd new-value-pair start. + 0x08207800, // adjacent opcode bits. + 0x88207c00, // single-register CAS instruction class. + } { + if _, ok := decodeARM64RawCASP(word); ok { + t.Fatalf("CASP decoder accepted adjacent/invalid encoding %#08x", word) + } + } +} + +func TestARM64RawCASPRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawcaspl(SB),$0-32 + MOVD memory+0(FP), R4 + MOVD expected+8(FP), R5 + MOVD desired+16(FP), R6 + MOVD observed+24(FP), R7 + MOVD 0(R5), R0 + MOVD 8(R5), R1 + MOVD 0(R6), R2 + MOVD 8(R6), R3 + WORD $0x4820fc82 // CASPL X0, X1, X2, X3, [X4] + MOVD R0, 0(R7) + MOVD R1, 8(R7) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawcaspl": { + Name: "rawcaspl", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawcaspl(uint64_t *, const uint64_t *, const uint64_t *, uint64_t *); +int main(void) { + _Alignas(16) uint64_t memory[2] = {11,22}; + const uint64_t success_expected[2] = {11,22}; + const uint64_t failure_expected[2] = {10,22}; + const uint64_t desired[2] = {33,44}; + uint64_t observed[2] = {0,0}; + rawcaspl(memory, success_expected, desired, observed); + if (memory[0] != 33 || memory[1] != 44 || observed[0] != 11 || observed[1] != 22) return 1; + memory[0] = 11; memory[1] = 22; observed[0] = 0; observed[1] = 0; + rawcaspl(memory, failure_expected, desired, observed); + if (memory[0] != 11 || memory[1] != 22 || observed[0] != 11 || observed[1] != 22) return 2; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_casp", triple, ir, mainC, nil) +} diff --git a/arm64_lower_word_cmgt.go b/arm64_lower_word_cmgt.go new file mode 100644 index 00000000..aa20412d --- /dev/null +++ b/arm64_lower_word_cmgt.go @@ -0,0 +1,70 @@ +package plan9asm + +import "fmt" + +type arm64RawCMGT struct { + scalar bool + zero bool + arrangement arm64VectorArrangement + destination int + first int + second int +} + +func decodeARM64RawCMGT(word uint32) (arm64RawCMGT, bool) { + form := arm64RawCMGT{} + switch { + case word&0xffe0fc00 == 0x5ee03400: // scalar D, register + form.scalar = true + case word&0xfffffc00 == 0x5ee08800: // scalar D, zero + form.scalar = true + form.zero = true + case word&0xbf20fc00 == 0x0e203400: // vector, register + case word&0xbf3ffc00 == 0x0e208800: // vector, zero + form.zero = true + default: + return arm64RawCMGT{}, false + } + + bits := 64 + lanes := 1 + if !form.scalar { + size := int(word>>22) & 3 + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + if size == 3 && vectorBits != 128 { + return arm64RawCMGT{}, false + } + bits = 8 << size + lanes = vectorBits / bits + } + form.arrangement = arm64VectorArrangement{elementBits: bits, lanes: lanes} + form.destination = int(word & 31) + form.first = int(word>>5) & 31 + if !form.zero { + form.second = int(word>>16) & 31 + } + return form, true +} + +func (c *arm64Ctx) lowerRawCMGT(form arm64RawCMGT) error { + first, err := c.loadRawARM64VectorOperand(form.first, form.arrangement, 0, form.scalar) + if err != nil { + return err + } + second := "zeroinitializer" + if !form.zero { + second, err = c.loadRawARM64VectorOperand(form.second, form.arrangement, 0, form.scalar) + if err != nil { + return err + } + } + vectorType := fmt.Sprintf("<%d x i%d>", form.arrangement.lanes, form.arrangement.elementBits) + compared := c.newTmp() + allBits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp sgt %s %s, %s\n", compared, vectorType, first, second) + fmt.Fprintf(c.b, " %%%s = sext <%d x i1> %%%s to %s\n", allBits, form.arrangement.lanes, compared, vectorType) + return c.storeRawARM64VectorResult(form.destination, form.arrangement, "%"+allBits, form.scalar) +} diff --git a/arm64_lower_word_cmgt_test.go b/arm64_lower_word_cmgt_test.go new file mode 100644 index 00000000..7c9d7a04 --- /dev/null +++ b/arm64_lower_word_cmgt_test.go @@ -0,0 +1,130 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +// CMGT has register and compare-with-zero encodings. Each has all seven legal +// vector arrangements plus the scalar D form. +const arm64RawCMGTForms = ` +TEXT rawcmgtforms(SB),$0-0 + WORD $0x0e223420 // CMGT V0.8B, V1.8B, V2.8B + WORD $0x4e223420 // CMGT V0.16B, V1.16B, V2.16B + WORD $0x0e623420 // CMGT V0.4H, V1.4H, V2.4H + WORD $0x4e623420 // CMGT V0.8H, V1.8H, V2.8H + WORD $0x0ea23420 // CMGT V0.2S, V1.2S, V2.2S + WORD $0x4ea23420 // CMGT V0.4S, V1.4S, V2.4S + WORD $0x4ee23420 // CMGT V0.2D, V1.2D, V2.2D + WORD $0x5ee23420 // CMGT D0, D1, D2 + WORD $0x0e208820 // CMGT V0.8B, V1.8B, #0 + WORD $0x4e208820 // CMGT V0.16B, V1.16B, #0 + WORD $0x0e608820 // CMGT V0.4H, V1.4H, #0 + WORD $0x4e608820 // CMGT V0.8H, V1.8H, #0 + WORD $0x0ea08820 // CMGT V0.2S, V1.2S, #0 + WORD $0x4ea08820 // CMGT V0.4S, V1.4S, #0 + WORD $0x4ee08820 // CMGT V0.2D, V1.2D, #0 + WORD $0x5ee08820 // CMGT D0, D1, #0 + RET +` + +func TestTranslateARM64RawCMGTCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawCMGTForms, true) + file, err := Parse(ArchARM64, arm64RawCMGTForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawcmgtforms": {Name: "rawcmgtforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "icmp sgt <8 x i8>", "icmp sgt <16 x i8>", + "icmp sgt <4 x i16>", "icmp sgt <8 x i16>", + "icmp sgt <2 x i32>", "icmp sgt <4 x i32>", + "icmp sgt <2 x i64>", "icmp sgt <1 x i64>", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw CMGT lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-cmgt.ll", "arm64-raw-cmgt.o", ll) + }) + } +} + +func TestARM64RawCMGTRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawcmgt(SB),$0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V4.S4] + VLD1 (R1), [V2.S4] + WORD $0x4ea23488 // CMGT V8.4S, V4.4S, V2.4S + VST1 [V8.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawcmgt": { + Name: "rawcmgt", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void rawcmgt(const int32_t *, const int32_t *, uint32_t *); +int main(void) { + const int32_t a[4] = {INT32_MIN, -1, 0, INT32_MAX}; + const int32_t b[4] = {INT32_MAX, -2, 0, INT32_MIN}; + const uint32_t want[4] = {0, 0xffffffffu, 0, 0xffffffffu}; + uint32_t got[4] = {0}; + rawcmgt(a, b, got); + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_cmgt", triple, ll, mainC, nil) +} + +func TestARM64RawCMGTDecoderRejectsAdjacentCMHIEncoding(t *testing.T) { + if _, ok := decodeARM64RawCMGT(0x6e223420); ok { + t.Fatal("CMGT decoder claimed adjacent CMHI encoding") + } +} diff --git a/arm64_lower_word_cvtf.go b/arm64_lower_word_cvtf.go new file mode 100644 index 00000000..0ac24a91 --- /dev/null +++ b/arm64_lower_word_cvtf.go @@ -0,0 +1,54 @@ +package plan9asm + +import "fmt" + +type arm64RawCVTF struct { + unsigned bool + arrangement arm64VectorArrangement + source int + destination int +} + +func decodeARM64RawCVTF(word uint32) (arm64RawCVTF, bool) { + if word&0x9fbffc00 != 0x0e21d800 { + return arm64RawCVTF{}, false + } + bits := 32 + if word&(1<<22) != 0 { + bits = 64 + } + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + if bits == 64 && vectorBits == 64 { + return arm64RawCVTF{}, false + } + return arm64RawCVTF{ + unsigned: word&(1<<29) != 0, + arrangement: arm64VectorArrangement{elementBits: bits, lanes: vectorBits / bits}, + source: int(word>>5) & 31, + destination: int(word & 31), + }, true +} + +func (c *arm64Ctx) lowerRawCVTF(form arm64RawCVTF) error { + op := Op("VSCVTF") + if form.unsigned { + op = "VUCVTF" + } + arrangement := arm64VectorArrangementName(form.arrangement) + ins := Instr{ + Op: op, + Raw: fmt.Sprintf("decoded ARM64 WORD as %s", op), + Args: []Operand{ + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.source, arrangement))}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.destination, arrangement))}, + }, + } + ok, _, err := c.lowerARM64VectorFloatUnary(op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", op) + } + return err +} diff --git a/arm64_lower_word_cvtf_test.go b/arm64_lower_word_cvtf_test.go new file mode 100644 index 00000000..255a6105 --- /dev/null +++ b/arm64_lower_word_cvtf_test.go @@ -0,0 +1,114 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawCVTFForms = ` +TEXT rawcvtfforms(SB),$0-0 + WORD $0x0e21d820 // SCVTF V0.2S, V1.2S + WORD $0x4e21d862 // SCVTF V2.4S, V3.4S + WORD $0x4e61d8a4 // SCVTF V4.2D, V5.2D + WORD $0x2e21d8e6 // UCVTF V6.2S, V7.2S + WORD $0x6e21d928 // UCVTF V8.4S, V9.4S + WORD $0x6e61d96a // UCVTF V10.2D, V11.2D + RET +` + +func TestTranslateARM64RawCVTFCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawCVTFForms, true) + file, err := Parse(ArchARM64, arm64RawCVTFForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawcvtfforms": {Name: "rawcvtfforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sitofp <2 x i32>", "sitofp <4 x i32>", "sitofp <2 x i64>", "uitofp <2 x i32>", "uitofp <4 x i32>", "uitofp <2 x i64>"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw SCVTF/UCVTF lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-cvtf.ll", "arm64-raw-cvtf.o", ll) + }) + } +} + +func TestARM64RawCVTFRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawcvtf(SB),$0-16 + MOVD in+0(FP), R0 + MOVD out+8(FP), R1 + VLD1 (R0), [V0.S4] + WORD $0x4e21d801 // SCVTF V1.4S, V0.4S + WORD $0x6e21d802 // UCVTF V2.4S, V0.4S + VST1 [V1.S4, V2.S4], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawcvtf": { + Name: "rawcvtf", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void rawcvtf(const uint32_t *, float *); +int main(void) { + const uint32_t input[4] = {UINT32_MAX, 0x80000000u, 0u, INT32_MAX}; + float got[8] = {0}; + rawcvtf(input, got); + for (int i = 0; i < 4; i++) { + if (got[i] != (float)(int32_t)input[i]) return i + 1; + if (got[4+i] != (float)input[i]) return i + 11; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_cvtf", triple, ll, mainC, nil) +} + +func TestARM64RawCVTFDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{0x4ea1b9ac, 0x0e61d800} { // FCVTZS and reserved D1. + if _, ok := decodeARM64RawCVTF(word); ok { + t.Fatalf("SCVTF/UCVTF decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} diff --git a/arm64_lower_word_dot_product.go b/arm64_lower_word_dot_product.go new file mode 100644 index 00000000..d0712bc5 --- /dev/null +++ b/arm64_lower_word_dot_product.go @@ -0,0 +1,128 @@ +package plan9asm + +import "fmt" + +type arm64RawDotProduct struct { + leftSigned bool + rightSigned bool + indexed bool + lane int + lanes int + destination int + left int + right int +} + +func decodeARM64RawDotProduct(word uint32) (arm64RawDotProduct, bool) { + form := arm64RawDotProduct{lane: -1} + switch word & 0xbfe0fc00 { + case 0x0e809400: // SDOT (vector). + form.leftSigned, form.rightSigned = true, true + case 0x2e809400: // UDOT (vector). + case 0x0e809c00: // USDOT (vector). + form.rightSigned = true + default: + switch word & 0xbfc0f400 { + case 0x0f80e000: // SDOT (by element). + form.leftSigned, form.rightSigned = true, true + case 0x2f80e000: // UDOT (by element). + case 0x0f80f000: // USDOT (by element). + form.rightSigned = true + case 0x0f00f000: // SUDOT (by element). + form.leftSigned = true + default: + return arm64RawDotProduct{}, false + } + form.indexed = true + form.lane = int(word>>21)&1 | int(word>>10)&2 + } + + form.lanes = 2 + if word&(1<<30) != 0 { + form.lanes = 4 + } + form.destination = int(word) & 31 + form.left = int(word>>5) & 31 + form.right = int(word>>16) & 31 + return form, true +} + +func (c *arm64Ctx) lowerRawDotProduct(form arm64RawDotProduct) error { + byteLanes := form.lanes * 4 + inputArrangement := arm64VectorArrangement{elementBits: 8, lanes: byteLanes} + accumulatorArrangement := arm64VectorArrangement{elementBits: 32, lanes: form.lanes} + left, err := c.loadARM64VectorInteger( + Reg(fmt.Sprintf("V%d.%s", form.left, arm64VectorArrangementName(inputArrangement))), + inputArrangement, + ) + if err != nil { + return err + } + + var right string + if form.indexed { + physical := arm64VectorArrangement{elementBits: 8, lanes: 16} + loaded, err := c.loadARM64VectorInteger( + Reg(fmt.Sprintf("V%d.%s", form.right, arm64VectorArrangementName(physical))), + physical, + ) + if err != nil { + return err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %s, <16 x i8> poison, <%d x i32> <", selected, loaded, byteLanes) + for i := 0; i < byteLanes; i++ { + if i != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", form.lane*4+i%4) + } + c.b.WriteString(">\n") + right = "%" + selected + } else { + right, err = c.loadARM64VectorInteger( + Reg(fmt.Sprintf("V%d.%s", form.right, arm64VectorArrangementName(inputArrangement))), + inputArrangement, + ) + if err != nil { + return err + } + } + + wideType := fmt.Sprintf("<%d x i32>", byteLanes) + widen := func(value string, signed bool) string { + result := c.newTmp() + op := "zext" + if signed { + op = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s <%d x i8> %s to %s\n", result, op, byteLanes, value, wideType) + return "%" + result + } + wideLeft := widen(left, form.leftSigned) + wideRight := widen(right, form.rightSigned) + products := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul %s %s, %s\n", products, wideType, wideLeft, wideRight) + + accumulatorReg := Reg(fmt.Sprintf("V%d.%s", form.destination, arm64VectorArrangementName(accumulatorArrangement))) + result, err := c.loadARM64VectorInteger(accumulatorReg, accumulatorArrangement) + if err != nil { + return err + } + for lane := 0; lane < form.lanes; lane++ { + accumulated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i32> %s, i32 %d\n", accumulated, form.lanes, result, lane) + value := "%" + accumulated + for element := 0; element < 4; element++ { + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement %s %%%s, i32 %d\n", product, wideType, products, lane*4+element) + sum := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %%%s\n", sum, value, product) + value = "%" + sum + } + updated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i32> %s, i32 %s, i32 %d\n", updated, form.lanes, result, value, lane) + result = "%" + updated + } + return c.storeARM64VectorInteger(accumulatorReg, accumulatorArrangement, result) +} diff --git a/arm64_lower_word_dot_product_test.go b/arm64_lower_word_dot_product_test.go new file mode 100644 index 00000000..755398d1 --- /dev/null +++ b/arm64_lower_word_dot_product_test.go @@ -0,0 +1,170 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64RawDotProductCompleteArchitecturalFormats(t *testing.T) { + vectorBases := []uint32{ + 0x0e809400, // SDOT. + 0x2e809400, // UDOT. + 0x0e809c00, // USDOT. + } + indexedBases := []uint32{ + 0x0f80e000, // SDOT (by element). + 0x2f80e000, // UDOT (by element). + 0x0f80f000, // USDOT (by element). + 0x0f00f000, // SUDOT (by element; no vector form exists). + } + var source strings.Builder + source.WriteString("TEXT rawdotproductforms(SB),$0-0\n") + for _, base := range vectorBases { + for _, q := range []uint32{0, 1 << 30} { + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|q|31<<16|30<<5|29) + } + } + for _, base := range indexedBases { + for _, q := range []uint32{0, 1 << 30} { + for lane := uint32(0); lane < 4; lane++ { + laneBits := (lane&1)<<21 | (lane&2)<<10 + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|q|laneBits|31<<16|30<<5|29) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawdotproductforms": {Name: "rawdotproductforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sext <", "zext <", "mul <", "add i32"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw dot-product lowering omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-dot-product.ll", "arm64-raw-dot-product.o", ir) + }) + } +} + +func TestARM64RawDotProductDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x0ea09400, // Reserved size bit in SDOT (vector). + 0x2e809c00, // Unallocated U bit in USDOT (vector). + 0x2f00f000, // Unallocated U bit in SUDOT (by element). + 0x0f40e000, // Unallocated size in SDOT (by element). + 0x0fc0e000, // Unallocated size in SDOT (by element). + 0x0f80e400, // Reserved bit 10 in SDOT (by element). + } { + if _, ok := decodeARM64RawDotProduct(word); ok { + t.Fatalf("dot-product decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} + +func TestARM64RawDotProductRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawdotproduct(SB),$0-32 + MOVD accumulator+0(FP), R0 + MOVD lhs+8(FP), R1 + MOVD rhs+16(FP), R2 + MOVD output+24(FP), R3 + VLD1 (R1), [V1.B16] + VLD1 (R2), [V2.B16] + VLD1 (R0), [V3.S4] + WORD $0x4e829423 // SDOT V3.4S, V1.16B, V2.16B + VST1 [V3.S4], (R3) + ADD $16, R3 + VLD1 (R0), [V4.S4] + WORD $0x6e829424 // UDOT V4.4S, V1.16B, V2.16B + VST1 [V4.S4], (R3) + ADD $16, R3 + VLD1 (R0), [V5.S4] + WORD $0x4e829c25 // USDOT V5.4S, V1.16B, V2.16B + VST1 [V5.S4], (R3) + ADD $16, R3 + VLD1 (R0), [V6.S4] + WORD $0x4f82e826 // SDOT V6.4S, V1.16B, V2.4B[2] + VST1 [V6.S4], (R3) + ADD $16, R3 + VLD1 (R0), [V7.S4] + WORD $0x6f82e827 // UDOT V7.4S, V1.16B, V2.4B[2] + VST1 [V7.S4], (R3) + ADD $16, R3 + VLD1 (R0), [V8.S4] + WORD $0x4f82f828 // USDOT V8.4S, V1.16B, V2.4B[2] + VST1 [V8.S4], (R3) + ADD $16, R3 + VLD1 (R0), [V9.S4] + WORD $0x4f02f829 // SUDOT V9.4S, V1.16B, V2.4B[2] + VST1 [V9.S4], (R3) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawdotproduct": { + Name: "rawdotproduct", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawdotproduct(const int32_t *, const int8_t *, const int8_t *, int32_t *); +int main(void) { + const int32_t accumulator[4] = {10, 20, 30, 40}; + const int8_t lhs[16] = {-1,2,-3,4, -1,2,-3,4, -1,2,-3,4, -1,2,-3,4}; + const int8_t rhs[16] = {1,2,3,4, 9,10,11,12, 5,-6,7,-8, 13,14,15,16}; + const int32_t want[28] = { + 20,46,-40,74, 1044,5166,4568,7242, 1044,5166,3032,7242, + -60,-50,-40,-30, 4548,4558,4568,4578, 3012,3022,3032,3042, + 1476,1486,1496,1506, + }; + int32_t got[28] = {0}; + rawdotproduct(accumulator, lhs, rhs, got); + for (int i = 0; i < 28; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_dot_product", triple, ir, mainC, nil) +} diff --git a/arm64_lower_word_dup_element.go b/arm64_lower_word_dup_element.go new file mode 100644 index 00000000..c0d424a4 --- /dev/null +++ b/arm64_lower_word_dup_element.go @@ -0,0 +1,50 @@ +package plan9asm + +type arm64RawDUPElement struct { + arrangement arm64VectorArrangement + element int + source int + destination int +} + +func decodeARM64RawDUPElement(word uint32) (arm64RawDUPElement, bool) { + if word&0xbfe0fc00 != 0x0e000400 { + return arm64RawDUPElement{}, false + } + imm5 := int(word>>16) & 31 + bits := 0 + element := 0 + switch { + case imm5&1 != 0: + bits, element = 8, imm5>>1 + case imm5&2 != 0: + bits, element = 16, imm5>>2 + case imm5&4 != 0: + bits, element = 32, imm5>>3 + case imm5&8 != 0: + bits, element = 64, imm5>>4 + default: + return arm64RawDUPElement{}, false + } + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + if bits == 64 && vectorBits == 64 { + return arm64RawDUPElement{}, false + } + return arm64RawDUPElement{ + arrangement: arm64VectorArrangement{elementBits: bits, lanes: vectorBits / bits}, + element: element, + source: int(word>>5) & 31, + destination: int(word & 31), + }, true +} + +func (c *arm64Ctx) lowerRawDUPElement(form arm64RawDUPElement) error { + value, err := c.loadRawARM64VectorOperand(form.source, form.arrangement, form.element, true) + if err != nil { + return err + } + return c.storeRawARM64VectorResult(form.destination, form.arrangement, value, false) +} diff --git a/arm64_lower_word_dup_element_test.go b/arm64_lower_word_dup_element_test.go new file mode 100644 index 00000000..eda93268 --- /dev/null +++ b/arm64_lower_word_dup_element_test.go @@ -0,0 +1,142 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func encodeARM64RawDUPElementForTest(bits, element, source, destination int, q bool) uint32 { + position := map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[bits] + imm5 := element<<(position+1) | 1<", "<16 x i8>", "<4 x i16>", "<8 x i16>", "<2 x i32>", "<4 x i32>", "<2 x i64>"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw DUP-element lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-dup-element.ll", "arm64-raw-dup-element.o", ll) + }) + } +} + +func TestARM64RawDUPElementDecoderCoversEveryLane(t *testing.T) { + for _, bits := range []int{8, 16, 32, 64} { + for element := 0; element < 128/bits; element++ { + for _, q := range []bool{false, true} { + if bits == 64 && !q { + continue + } + word := encodeARM64RawDUPElementForTest(bits, element, 7, 23, q) + form, ok := decodeARM64RawDUPElement(word) + if !ok || form.arrangement.elementBits != bits || form.element != element || form.source != 7 || form.destination != 23 { + t.Fatalf("decode DUP element bits=%d lane=%d q=%v: form=%#v ok=%v", bits, element, q, form, ok) + } + } + } + } +} + +func TestARM64RawDUPElementRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawdupelement(SB),$0-16 + MOVD in+0(FP), R0 + MOVD out+8(FP), R1 + VLD1 (R0), [V1.S4] + WORD $0x4e040430 // DUP V16.4S, V1.S[0] + VST1 [V16.S4], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawdupelement": { + Name: "rawdupelement", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawdupelement(const uint32_t *, uint32_t *); +int main(void) { + const uint32_t input[4] = {0x12345678u, 2, 3, 4}; + uint32_t got[4] = {0}; + rawdupelement(input, got); + for (int i = 0; i < 4; i++) if (got[i] != input[0]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_dup_element", triple, ll, mainC, nil) +} + +func TestARM64RawDUPElementDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x4e040c20, // DUP from W register. + 0x5e040420, // Scalar DUP from vector element. + encodeARM64RawDUPElementForTest(64, 0, 1, 0, false), // Reserved D1 vector form. + } { + t.Run(fmt.Sprintf("%08x", word), func(t *testing.T) { + if _, ok := decodeARM64RawDUPElement(word); ok { + t.Fatalf("DUP-element decoder claimed adjacent/reserved encoding %#08x", word) + } + }) + } +} diff --git a/arm64_lower_word_faddp.go b/arm64_lower_word_faddp.go new file mode 100644 index 00000000..0cd7d494 --- /dev/null +++ b/arm64_lower_word_faddp.go @@ -0,0 +1,113 @@ +package plan9asm + +import "fmt" + +type arm64RawFADDP struct { + scalar bool + arrangement arm64VectorArrangement + first int + second int + destination int +} + +func decodeARM64RawFADDP(word uint32) (arm64RawFADDP, bool) { + const vectorRegisters = uint32(31 | 31<<5 | 31<<16) + var vectorArrangement arm64VectorArrangement + switch word &^ vectorRegisters { + case 0x2e401400: + vectorArrangement = arm64VectorArrangement{elementBits: 16, lanes: 4} + case 0x6e401400: + vectorArrangement = arm64VectorArrangement{elementBits: 16, lanes: 8} + case 0x2e20d400: + vectorArrangement = arm64VectorArrangement{elementBits: 32, lanes: 2} + case 0x6e20d400: + vectorArrangement = arm64VectorArrangement{elementBits: 32, lanes: 4} + case 0x6e60d400: + vectorArrangement = arm64VectorArrangement{elementBits: 64, lanes: 2} + } + if vectorArrangement.elementBits != 0 { + return arm64RawFADDP{ + arrangement: vectorArrangement, + first: int(word>>5) & 31, + second: int(word>>16) & 31, + destination: int(word) & 31, + }, true + } + + const scalarRegisters = uint32(31 | 31<<5) + scalarBits := 0 + switch word &^ scalarRegisters { + case 0x5e30d800: + scalarBits = 16 + case 0x7e30d800: + scalarBits = 32 + case 0x7e70d800: + scalarBits = 64 + } + if scalarBits != 0 { + return arm64RawFADDP{ + scalar: true, + arrangement: arm64VectorArrangement{elementBits: scalarBits, lanes: 2}, + first: int(word>>5) & 31, + second: -1, + destination: int(word) & 31, + }, true + } + return arm64RawFADDP{}, false +} + +func arm64RawFloatType(bits int) string { + switch bits { + case 16: + return "half" + case 32: + return "float" + case 64: + return "double" + default: + panic(fmt.Sprintf("unsupported ARM64 floating width %d", bits)) + } +} + +func (c *arm64Ctx) lowerRawFADDP(form arm64RawFADDP) error { + firstReg := Reg(fmt.Sprintf("V%d", form.first)) + first, err := c.loadARM64VectorFloat(firstReg, form.arrangement) + if err != nil { + return err + } + floatType := arm64RawFloatType(form.arrangement.elementBits) + if form.scalar { + left := c.newTmp() + right := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x %s> %s, i32 0\n", left, floatType, first) + fmt.Fprintf(c.b, " %%%s = extractelement <2 x %s> %s, i32 1\n", right, floatType, first) + fmt.Fprintf(c.b, " %%%s = fadd %s %%%s, %%%s\n", result, floatType, left, right) + return c.storeARM64ScalarFloatReg(Reg(fmt.Sprintf("F%d", form.destination)), form.arrangement.elementBits, "%"+result) + } + + second, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.second)), form.arrangement) + if err != nil { + return err + } + result := "poison" + half := form.arrangement.lanes / 2 + for lane := 0; lane < form.arrangement.lanes; lane++ { + source := first + if lane >= half { + source = second + } + pair := (lane % half) * 2 + left := c.newTmp() + right := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %s, i32 %d\n", left, form.arrangement.lanes, floatType, source, pair) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %s, i32 %d\n", right, form.arrangement.lanes, floatType, source, pair+1) + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fadd %s %%%s, %%%s\n", combined, floatType, left, right) + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x %s> %s, %s %%%s, i32 %d\n", + inserted, form.arrangement.lanes, floatType, result, floatType, combined, lane) + result = "%" + inserted + } + return c.storeARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.destination)), form.arrangement, result) +} diff --git a/arm64_lower_word_faddp_test.go b/arm64_lower_word_faddp_test.go new file mode 100644 index 00000000..7b3d5a9b --- /dev/null +++ b/arm64_lower_word_faddp_test.go @@ -0,0 +1,159 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64RawFADDPCompleteArchitecturalFormats(t *testing.T) { + vectorBases := []uint32{ + 0x2e401400, // FADDP Vd.4H, Vn.4H, Vm.4H. + 0x6e401400, // FADDP Vd.8H, Vn.8H, Vm.8H. + 0x2e20d400, // FADDP Vd.2S, Vn.2S, Vm.2S. + 0x6e20d400, // FADDP Vd.4S, Vn.4S, Vm.4S. + 0x6e60d400, // FADDP Vd.2D, Vn.2D, Vm.2D. + } + scalarBases := []uint32{ + 0x5e30d800, // FADDP Hd, Vn.2H. + 0x7e30d800, // FADDP Sd, Vn.2S. + 0x7e70d800, // FADDP Dd, Vn.2D. + } + var source strings.Builder + source.WriteString("TEXT rawfaddpforms(SB),$0-0\n") + for _, base := range vectorBases { + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|29<<16|30<<5|28) + } + for _, base := range scalarBases { + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|30<<5|29) + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfaddpforms": {Name: "rawfaddpforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-faddp.ll", "arm64-raw-faddp.o", ir) + }) + } +} + +func TestARM64RawFADDPDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x2e60d400, // reserved D1 vector arrangement. + 0x2e20f400, // FMAXP vector instruction. + 0x7e30f800, // FMAXP scalar instruction. + 0x2e401800, // adjacent opcode bits in the FP16 vector encoding. + 0x5e70d800, // reserved scalar FP16 size combination. + } { + if _, ok := decodeARM64RawFADDP(word); ok { + t.Fatalf("FADDP decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} + +func TestARM64RawFADDPRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawfaddp(SB),$0-32 + MOVD halfs+0(FP), R0 + MOVD singles+8(FP), R1 + MOVD doubles+16(FP), R2 + MOVD output+24(FP), R3 + VLD1.P 16(R0), [V0.H8] + VLD1 (R0), [V1.H8] + WORD $0x2e411402 // FADDP V2.4H, V0.4H, V1.4H + WORD $0x6e411403 // FADDP V3.8H, V0.8H, V1.8H + WORD $0x5e30d804 // FADDP H4, V0.2H + VST1.P [V2.H4], 8(R3) + VST1.P [V3.H8], 16(R3) + VST1.P [V4.H4], 8(R3) + VLD1.P 16(R1), [V5.S4] + VLD1 (R1), [V6.S4] + WORD $0x2e26d4a7 // FADDP V7.2S, V5.2S, V6.2S + WORD $0x6e26d4a8 // FADDP V8.4S, V5.4S, V6.4S + WORD $0x7e30d8a9 // FADDP S9, V5.2S + VST1.P [V7.S2], 8(R3) + VST1.P [V8.S4], 16(R3) + VST1.P [V9.S2], 8(R3) + VLD1.P 16(R2), [V10.D2] + VLD1 (R2), [V11.D2] + WORD $0x6e6bd54c // FADDP V12.2D, V10.2D, V11.2D + WORD $0x7e70d94d // FADDP D13, V10.2D + VST1.P [V12.D2], 16(R3) + VST1 [V13.D2], (R3) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawfaddp": { + Name: "rawfaddp", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawfaddp(const uint16_t *, const float *, const double *, void *); +int main(void) { + const uint16_t halfs[16] = { + 0x3c00,0x3c00,0x4000,0x4000,0x4200,0x4200,0x4400,0x4400, + 0x4500,0x4500,0x4600,0x4600,0x4700,0x4700,0x4800,0x4800 + }; + const float singles[8] = {1,2,3,4,10,20,30,40}; + const double doubles[4] = {1,2,10,20}; + _Alignas(16) unsigned char output[96] = {0}; + rawfaddp(halfs, singles, doubles, output); + const uint16_t want_h4[4] = {0x4000,0x4400,0x4900,0x4a00}; + const uint16_t want_h8[8] = {0x4000,0x4400,0x4600,0x4800,0x4900,0x4a00,0x4b00,0x4c00}; + for (int i = 0; i < 4; i++) if (((uint16_t *)(output + 0))[i] != want_h4[i]) return 1 + i; + for (int i = 0; i < 8; i++) if (((uint16_t *)(output + 8))[i] != want_h8[i]) return 10 + i; + if (((uint16_t *)(output + 24))[0] != 0x4000) return 20; + if (((float *)(output + 32))[0] != 3 || ((float *)(output + 32))[1] != 30) return 21; + const float want_s4[4] = {3,7,30,70}; + for (int i = 0; i < 4; i++) if (((float *)(output + 40))[i] != want_s4[i]) return 22 + i; + if (((float *)(output + 56))[0] != 3) return 30; + if (((double *)(output + 64))[0] != 3 || ((double *)(output + 64))[1] != 30) return 31; + if (((double *)(output + 80))[0] != 3) return 32; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_faddp", triple, ir, mainC, nil) +} diff --git a/arm64_lower_word_fcvt_round_test.go b/arm64_lower_word_fcvt_round_test.go new file mode 100644 index 00000000..8a61b819 --- /dev/null +++ b/arm64_lower_word_fcvt_round_test.go @@ -0,0 +1,139 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64RawFloatToIntegerRoundingCompleteBaseFormats(t *testing.T) { + // The base A64 Advanced SIMD family has five rounding modes, signed and + // unsigned results, and S2/S4/D2 arrangements. H4/H8 belong to the + // optional FP16 extension and are deliberately outside this base matrix. + bases := []uint32{ + 0x0e21a800, // FCVTNS + 0x0e21b800, // FCVTMS + 0x0e21c800, // FCVTAS + 0x0ea1a800, // FCVTPS + 0x0ea1b800, // FCVTZS + } + modifiers := []uint32{0, 1 << 30, 1<<30 | 1<<22} // S2, S4, D2. + var source strings.Builder + source.WriteString("TEXT rawfcvtroundforms(SB),$0-0\n") + for _, base := range bases { + for _, unsigned := range []uint32{0, 1 << 29} { + for _, modifier := range modifiers { + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|unsigned|modifier|30<<5|29) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawfcvtroundforms": {Name: "rawfcvtroundforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{ + "@llvm.roundeven.", "@llvm.floor.", "@llvm.round.", "@llvm.ceil.", + "@llvm.fptosi.sat.", "@llvm.fptoui.sat.", + } { + if !strings.Contains(ll, intrinsic) { + t.Fatalf("raw FCVT rounding family omitted %s for %s:\n%s", intrinsic, triple, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-fcvt-round.ll", "arm64-raw-fcvt-round.o", ll) + }) + } +} + +func TestARM64RawFloatToIntegerRoundingRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawfcvtround(SB),$0-16 + MOVD input+0(FP), R0 + MOVD output+8(FP), R1 + VLD1 (R0), [V0.S4] + WORD $0x4e21a801 // FCVTNS V0.4S, V1.4S + WORD $0x6e21a802 // FCVTNU V0.4S, V2.4S + WORD $0x4e21b803 // FCVTMS V0.4S, V3.4S + WORD $0x6e21b804 // FCVTMU V0.4S, V4.4S + WORD $0x4e21c805 // FCVTAS V0.4S, V5.4S + WORD $0x6e21c806 // FCVTAU V0.4S, V6.4S + WORD $0x4ea1a807 // FCVTPS V0.4S, V7.4S + WORD $0x6ea1a808 // FCVTPU V0.4S, V8.4S + WORD $0x4ea1b809 // FCVTZS V0.4S, V9.4S + WORD $0x6ea1b80a // FCVTZU V0.4S, V10.4S + VST1 [V1.S4, V2.S4, V3.S4, V4.S4], (R1) + ADD $64, R1 + VST1 [V5.S4, V6.S4, V7.S4, V8.S4], (R1) + ADD $64, R1 + VST1 [V9.S4, V10.S4], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfcvtround": { + Name: "rawfcvtround", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawfcvtround(const float *, uint32_t *); +int main(void) { + const float input[4] = {1.5f, 2.5f, -1.5f, -2.5f}; + const int32_t want[40] = { + 2,2,-2,-2, 2,2,0,0, + 1,2,-2,-3, 1,2,0,0, + 2,3,-2,-3, 2,3,0,0, + 2,3,-1,-2, 2,3,0,0, + 1,2,-1,-2, 1,2,0,0, + }; + uint32_t got[40] = {0}; + rawfcvtround(input, got); + for (int i = 0; i < 40; i++) { + if ((int32_t)got[i] != want[i]) return i + 1; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_fcvt_round", triple, ll, mainC, nil) +} diff --git a/arm64_lower_word_fcvtz.go b/arm64_lower_word_fcvtz.go new file mode 100644 index 00000000..dff88dd8 --- /dev/null +++ b/arm64_lower_word_fcvtz.go @@ -0,0 +1,55 @@ +package plan9asm + +import "fmt" + +type arm64RawFCVTZ struct { + unsigned bool + arrangement arm64VectorArrangement + source int + destination int +} + +func decodeARM64RawFCVTZ(word uint32) (arm64RawFCVTZ, bool) { + masked := word & 0xbfbffc00 // Ignore Q, size, Rn, and Rd. + if masked != 0x0ea1b800 && masked != 0x2ea1b800 { + return arm64RawFCVTZ{}, false + } + elementBits := 32 + if word&(1<<22) != 0 { + elementBits = 64 + } + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + if elementBits == 64 && vectorBits == 64 { + return arm64RawFCVTZ{}, false + } + return arm64RawFCVTZ{ + unsigned: word&(1<<29) != 0, + arrangement: arm64VectorArrangement{elementBits: elementBits, lanes: vectorBits / elementBits}, + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawFCVTZ(form arm64RawFCVTZ) error { + op := Op("VFCVTZS") + if form.unsigned { + op = "VFCVTZU" + } + arrangement := arm64VectorArrangementName(form.arrangement) + ins := Instr{ + Op: op, + Raw: fmt.Sprintf("decoded ARM64 WORD as %s", op), + Args: []Operand{ + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.source, arrangement))}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.destination, arrangement))}, + }, + } + ok, _, err := c.lowerARM64VectorFloatUnary(op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", op) + } + return err +} diff --git a/arm64_lower_word_fcvtz_test.go b/arm64_lower_word_fcvtz_test.go new file mode 100644 index 00000000..b5827910 --- /dev/null +++ b/arm64_lower_word_fcvtz_test.go @@ -0,0 +1,126 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawFCVTZForms = ` +TEXT rawfcvtzforms(SB),$0-0 + WORD $0x0ea1b820 // FCVTZS V1.S2, V0.S2 + WORD $0x4ea1b862 // FCVTZS V3.S4, V2.S4 + WORD $0x4ee1b8a4 // FCVTZS V5.D2, V4.D2 + WORD $0x2ea1b8e6 // FCVTZU V7.S2, V6.S2 + WORD $0x6ea1b928 // FCVTZU V9.S4, V8.S4 + WORD $0x6ee1b96a // FCVTZU V11.D2, V10.D2 + RET +` + +func TestTranslateARM64RawFCVTZCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawFCVTZForms, true) + file, err := Parse(ArchARM64, arm64RawFCVTZForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfcvtzforms": {Name: "rawfcvtzforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "@llvm.fptosi.sat.v2i32.v2f32", "@llvm.fptosi.sat.v4i32.v4f32", "@llvm.fptosi.sat.v2i64.v2f64", + "@llvm.fptoui.sat.v2i32.v2f32", "@llvm.fptoui.sat.v4i32.v4f32", "@llvm.fptoui.sat.v2i64.v2f64", + } { + found := false + for _, line := range strings.Split(ll, "\n") { + if strings.Contains(line, " = call ") && strings.Contains(line, want) { + found = true + break + } + } + if !found { + t.Fatalf("ARM64 raw FCVTZS/FCVTZU lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-fcvtz.ll", "arm64-raw-fcvtz.o", ll) + }) + } +} + +func TestARM64RawFCVTZRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawfcvtz(SB),$0-16 + MOVD in+0(FP), R0 + MOVD out+8(FP), R1 + VLD1 (R0), [V0.S4] + WORD $0x4ea1b801 // FCVTZS V0.4S, V1.4S + WORD $0x6ea1b802 // FCVTZU V0.4S, V2.4S + VST1 [V1.S4, V2.S4], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfcvtz": { + Name: "rawfcvtz", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void rawfcvtz(const float *, uint32_t *); +int main(void) { + const float in[4] = {-1.75f, 1.75f, 1.0e30f, -1.0e30f}; + const int32_t signed_want[4] = {-1, 1, INT32_MAX, INT32_MIN}; + const uint32_t unsigned_want[4] = {0, 1, UINT32_MAX, 0}; + uint32_t got[8] = {0}; + rawfcvtz(in, got); + for (int i = 0; i < 4; i++) { + if ((int32_t)got[i] != signed_want[i]) return i + 1; + if (got[4+i] != unsigned_want[i]) return i + 11; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_fcvtz", triple, ll, mainC, nil) +} + +func TestARM64RawFCVTZDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{0x4e21d800, 0x1e38c000, 0x0ee1b800} { // SCVTF, scalar FCVTZS, reserved D1. + if _, ok := decodeARM64RawFCVTZ(word); ok { + t.Fatalf("FCVTZS/FCVTZU decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} diff --git a/arm64_lower_word_float_abs_neg.go b/arm64_lower_word_float_abs_neg.go new file mode 100644 index 00000000..e4f682be --- /dev/null +++ b/arm64_lower_word_float_abs_neg.go @@ -0,0 +1,51 @@ +package plan9asm + +import "fmt" + +type arm64RawFloatAbsNeg struct { + negate bool + arrangement arm64VectorArrangement + source int + destination int +} + +// decodeARM64RawFloatAbsNeg recognizes the FP16 Advanced SIMD forms that Go's +// named VFABS/VFNEG optab cannot express. S2/S4/D2 WORD encodings are decoded +// by x/arch and flow through the complete named-form lowerer. +func decodeARM64RawFloatAbsNeg(word uint32) (arm64RawFloatAbsNeg, bool) { + const registers = uint32(31 | 31<<5) + key := word &^ registers + negate := false + switch key { + case 0x0ef8f800, 0x4ef8f800: + case 0x2ef8f800, 0x6ef8f800: + negate = true + default: + return arm64RawFloatAbsNeg{}, false + } + lanes := 4 + if word&(1<<30) != 0 { + lanes = 8 + } + return arm64RawFloatAbsNeg{ + negate: negate, + arrangement: arm64VectorArrangement{elementBits: 16, lanes: lanes}, + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawFloatAbsNeg(form arm64RawFloatAbsNeg) error { + source, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.source)), form.arrangement) + if err != nil { + return err + } + result := c.newTmp() + vectorType := fmt.Sprintf("<%d x half>", form.arrangement.lanes) + if form.negate { + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", result, vectorType, source) + } else { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.fabs.v%df16(%s %s)\n", result, vectorType, form.arrangement.lanes, vectorType, source) + } + return c.storeARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.destination)), form.arrangement, "%"+result) +} diff --git a/arm64_lower_word_float_abs_neg_test.go b/arm64_lower_word_float_abs_neg_test.go new file mode 100644 index 00000000..56b0b1dc --- /dev/null +++ b/arm64_lower_word_float_abs_neg_test.go @@ -0,0 +1,108 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawFloatAbsNegForms = ` +TEXT rawfloatabsnegforms(SB),$0-0 + WORD $0x0ef8f820 // FABS V0.4H, V1.4H + WORD $0x4ef8f820 // FABS V0.8H, V1.8H + WORD $0x0ea0f820 // FABS V0.2S, V1.2S + WORD $0x4ea0f820 // FABS V0.4S, V1.4S + WORD $0x4ee0f820 // FABS V0.2D, V1.2D + WORD $0x2ef8f820 // FNEG V0.4H, V1.4H + WORD $0x6ef8f820 // FNEG V0.8H, V1.8H + WORD $0x2ea0f820 // FNEG V0.2S, V1.2S + WORD $0x6ea0f820 // FNEG V0.4S, V1.4S + WORD $0x6ee0f820 // FNEG V0.2D, V1.2D + RET +` + +func TestTranslateARM64RawFloatAbsNegCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawFloatAbsNegForms, true) + file, err := Parse(ArchARM64, arm64RawFloatAbsNegForms) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfloatabsnegforms": {Name: "rawfloatabsnegforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"@llvm.fabs.v4f16", "@llvm.fabs.v8f16", "fneg <4 x half>", "fneg <8 x half>", "@llvm.fabs.v2f32", "@llvm.fabs.v4f32", "@llvm.fabs.v2f64", "fneg <2 x float>", "fneg <4 x float>", "fneg <2 x double>"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw float abs/neg for %s omitted %s:\n%s", triple, want, ir) + } + } + compileLLVMToObject(t, llc, triple, "raw-float-abs-neg.ll", "raw-float-abs-neg.o", ir) + }) + } +} + +func TestARM64RawFloatAbsNegRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawfloatabsneg(SB),$0-16 + MOVD input+0(FP), R0 + MOVD output+8(FP), R1 + VLD1 (R0), [V0.H8] + WORD $0x4ef8f801 // FABS V1.8H, V0.8H + WORD $0x6ef8f802 // FNEG V2.8H, V0.8H + VST1.P [V1.H8], 16(R1) + VST1 [V2.H8], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfloatabsneg": { + Name: "rawfloatabsneg", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawfloatabsneg(const uint16_t *, uint16_t *); +int main(void) { + const uint16_t input[8] = {0xbc00,0x4000,0xc200,0x4400,0xc500,0x4600,0xc700,0x4800}; + uint16_t got[16] = {0}; + rawfloatabsneg(input, got); + for (int i = 0; i < 8; i++) { + if (got[i] != (input[i] & 0x7fff)) return i + 1; + if (got[8+i] != (input[i] ^ 0x8000)) return i + 9; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_float_abs_neg", triple, ir, mainC, nil) +} diff --git a/arm64_lower_word_float_binary.go b/arm64_lower_word_float_binary.go new file mode 100644 index 00000000..e0328f20 --- /dev/null +++ b/arm64_lower_word_float_binary.go @@ -0,0 +1,126 @@ +package plan9asm + +import "fmt" + +type arm64RawFloatBinary struct { + op Op + arrangement arm64VectorArrangement + first int + second int + destination int +} + +func decodeARM64RawFloatBinary(word uint32) (arm64RawFloatBinary, bool) { + const registers = uint32(31 | 31<<5 | 31<<16) + halfForms := map[uint32]Op{ + 0x0e401400: "VFADD", 0x4e401400: "VFADD", + 0x0ec01400: "VFSUB", 0x4ec01400: "VFSUB", + 0x2e401c00: "VFMUL", 0x6e401c00: "VFMUL", + 0x2e403c00: "VFDIV", 0x6e403c00: "VFDIV", + 0x0e403400: "VFMAX", 0x4e403400: "VFMAX", + 0x0ec03400: "VFMIN", 0x4ec03400: "VFMIN", + 0x0e400400: "VFMAXNM", 0x4e400400: "VFMAXNM", + 0x0ec00400: "VFMINNM", 0x4ec00400: "VFMINNM", + } + if op, ok := halfForms[word&^registers]; ok { + lanes := 4 + if word&(1<<30) != 0 { + lanes = 8 + } + return arm64RawFloatBinary{ + op: op, + arrangement: arm64VectorArrangement{elementBits: 16, lanes: lanes}, + first: int(word>>5) & 31, + second: int(word>>16) & 31, + destination: int(word) & 31, + }, true + } + + var op Op + switch word & 0xbfa0fc00 { // Ignore Q, size, Rm, Rn, and Rd. + case 0x0e20d400: + op = "VFADD" + case 0x0ea0d400: + op = "VFSUB" + case 0x2e20dc00: + op = "VFMUL" + case 0x2e20fc00: + op = "VFDIV" + case 0x0e20f400: + op = "VFMAX" + case 0x0ea0f400: + op = "VFMIN" + case 0x0e20c400: + op = "VFMAXNM" + case 0x0ea0c400: + op = "VFMINNM" + default: + return arm64RawFloatBinary{}, false + } + + elementBits := 32 + if word&(1<<22) != 0 { + elementBits = 64 + } + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + // The 64-bit scalar-sized D1 combination is reserved for this vector class. + if elementBits == 64 && vectorBits == 64 { + return arm64RawFloatBinary{}, false + } + + return arm64RawFloatBinary{ + op: op, + arrangement: arm64VectorArrangement{elementBits: elementBits, lanes: vectorBits / elementBits}, + first: int(word>>5) & 31, + second: int(word>>16) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawFloatBinary(form arm64RawFloatBinary) error { + if form.arrangement.elementBits == 16 { + first, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.first)), form.arrangement) + if err != nil { + return err + } + second, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.second)), form.arrangement) + if err != nil { + return err + } + vectorType := fmt.Sprintf("<%d x half>", form.arrangement.lanes) + result := c.newTmp() + switch form.op { + case "VFADD", "VFSUB", "VFMUL", "VFDIV": + operation := map[Op]string{"VFADD": "add", "VFSUB": "sub", "VFMUL": "mul", "VFDIV": "div"}[form.op] + fmt.Fprintf(c.b, " %%%s = f%s %s %s, %s\n", result, operation, vectorType, first, second) + case "VFMAX", "VFMIN", "VFMAXNM", "VFMINNM": + operation := map[Op]string{"VFMAX": "maximum", "VFMIN": "minimum", "VFMAXNM": "maxnum", "VFMINNM": "minnum"}[form.op] + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.v%df16(%s %s, %s %s)\n", + result, vectorType, operation, form.arrangement.lanes, vectorType, first, vectorType, second) + default: + return fmt.Errorf("arm64 raw half-precision float decoder reached unknown operation %s", form.op) + } + return c.storeARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.destination)), form.arrangement, "%"+result) + } + + arrangement := arm64VectorArrangementName(form.arrangement) + ins := Instr{ + Op: form.op, + Raw: fmt.Sprintf("decoded ARM64 WORD as %s", form.op), + Args: []Operand{ + // Plan 9 vector arithmetic lists Vm, Vn, Vd; the architectural + // encoding stores Vn in Rn and Vm in Rm. + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.second, arrangement))}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.first, arrangement))}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.destination, arrangement))}, + }, + } + ok, _, err := c.lowerARM64VectorFloatArithmetic(form.op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", form.op) + } + return err +} diff --git a/arm64_lower_word_float_binary_test.go b/arm64_lower_word_float_binary_test.go new file mode 100644 index 00000000..099b45b9 --- /dev/null +++ b/arm64_lower_word_float_binary_test.go @@ -0,0 +1,139 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64RawFloatBinaryCompleteAdvancedSIMDFormats(t *testing.T) { + bases := []uint32{0x0e20d400, 0x0ea0d400, 0x2e20dc00, 0x2e20fc00, 0x0e20f400, 0x0ea0f400, 0x0e20c400, 0x0ea0c400} + halfBases := []uint32{0x0e401400, 0x0ec01400, 0x2e401c00, 0x2e403c00, 0x0e403400, 0x0ec03400, 0x0e400400, 0x0ec00400} + var source strings.Builder + source.WriteString("TEXT rawfloatbinaryforms(SB),$0-0\n") + for _, base := range halfBases { + for _, modifier := range []uint32{0, 1 << 30} { // H4, H8. + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|modifier|2<<16|1<<5) + } + } + for _, base := range bases { + for _, modifier := range []uint32{0, 1 << 30, 1<<30 | 1<<22} { // S2, S4, D2. + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|modifier|2<<16|1<<5) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfloatbinaryforms": {Name: "rawfloatbinaryforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "fadd <4 x half>", "fadd <8 x half>", + "fsub <4 x half>", "fsub <8 x half>", + "fmul <4 x half>", "fmul <8 x half>", + "fdiv <4 x half>", "fdiv <8 x half>", + "@llvm.maximum.v4f16", "@llvm.maximum.v8f16", + "@llvm.minimum.v4f16", "@llvm.minimum.v8f16", + "@llvm.maxnum.v4f16", "@llvm.maxnum.v8f16", + "@llvm.minnum.v4f16", "@llvm.minnum.v8f16", + "fadd <", "fsub <", "fmul <", "fdiv <", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw float binary lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-float-binary.ll", "arm64-raw-float-binary.o", ll) + }) + } +} + +func TestARM64RawFloatBinaryRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawfloatbinary(SB),$0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V1.S4] + WORD $0x4e21d402 // FADD V2.4S, V0.4S, V1.4S + WORD $0x4ea1d403 // FSUB V3.4S, V0.4S, V1.4S + WORD $0x6e21dc04 // FMUL V4.4S, V0.4S, V1.4S + WORD $0x6e21fc05 // FDIV V5.4S, V0.4S, V1.4S + WORD $0x4e21f406 // FMAX V6.4S, V0.4S, V1.4S + WORD $0x4ea1f407 // FMIN V7.4S, V0.4S, V1.4S + WORD $0x4e21c408 // FMAXNM V8.4S, V0.4S, V1.4S + WORD $0x4ea1c409 // FMINNM V9.4S, V0.4S, V1.4S + VST1.P [V2.S4, V3.S4, V4.S4, V5.S4], 64(R2) + VST1 [V6.S4, V7.S4, V8.S4, V9.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawfloatbinary": { + Name: "rawfloatbinary", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawfloatbinary(const float *, const float *, float *); +int main(void) { + const float a[4] = {8.0f, -6.0f, 1.5f, -4.0f}; + const float b[4] = {2.0f, 3.0f, -2.0f, 4.0f}; + float got[32] = {0}; + rawfloatbinary(a, b, got); + for (int i = 0; i < 4; i++) { + const float want[8] = {a[i]+b[i], a[i]-b[i], a[i]*b[i], a[i]/b[i], a[i]>b[i]?a[i]:b[i], a[i]b[i]?a[i]:b[i], a[i]>5) & 31, + second: int(word>>16) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawFloatCompare(form arm64RawFloatCompare) error { + arrangement := arm64VectorArrangementName(form.arrangement) + first := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.first, arrangement))} + destination := Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.destination, arrangement))} + args := []Operand{{Kind: OpImm, Imm: 0}, first, destination} + if !form.zero { + args[0] = Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.second, arrangement))} + } + ins := Instr{Op: form.op, Raw: fmt.Sprintf("decoded ARM64 WORD as %s", form.op), Args: args} + ok, _, err := c.lowerARM64VectorFloatCompare(form.op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", form.op) + } + return err +} diff --git a/arm64_lower_word_float_compare_test.go b/arm64_lower_word_float_compare_test.go new file mode 100644 index 00000000..8c798aa4 --- /dev/null +++ b/arm64_lower_word_float_compare_test.go @@ -0,0 +1,164 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func arm64FloatCompareCompleteSource(raw bool) string { + arrangements := []struct { + name string + modifier uint32 + }{ + {name: "S2"}, + {name: "S4", modifier: 1 << 30}, + {name: "D2", modifier: 1<<30 | 1<<22}, + } + var source strings.Builder + if raw { + source.WriteString("TEXT rawfloatcompareforms(SB),$0-0\n") + for _, base := range []uint32{0x0e20e400, 0x2e20e400, 0x2ea0e400} { // FCMEQ, FCMGE, FCMGT. + for _, arrangement := range arrangements { + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|arrangement.modifier|1<<16|2<<5|3) + } + } + for _, base := range []uint32{0x0ea0d800, 0x2ea0c800, 0x0ea0c800, 0x2ea0d800, 0x0ea0e800} { // FCMEQ/GE/GT/LE/LT zero. + for _, arrangement := range arrangements { + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|arrangement.modifier|2<<5|3) + } + } + } else { + source.WriteString("TEXT floatcompareforms(SB),$0-0\n") + for _, op := range []string{"VFCMEQ", "VFCMGE", "VFCMGT"} { + for _, arrangement := range arrangements { + fmt.Fprintf(&source, "\t%s V1.%s, V2.%s, V3.%s\n", op, arrangement.name, arrangement.name, arrangement.name) + } + } + for _, op := range []string{"VFCMEQ", "VFCMGE", "VFCMGT", "VFCMLE", "VFCMLT"} { + for _, arrangement := range arrangements { + fmt.Fprintf(&source, "\t%s $(0.0), V2.%s, V3.%s\n", op, arrangement.name, arrangement.name) + } + } + } + source.WriteString("\tRET\n") + return source.String() +} + +func TestTranslateARM64FloatCompareCompleteGo127Formats(t *testing.T) { + for _, raw := range []bool{false, true} { + name := "named" + function := "floatcompareforms" + if raw { + name = "raw" + function = "rawfloatcompareforms" + } + t.Run(name, func(t *testing.T) { + source := arm64FloatCompareCompleteSource(raw) + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if got := strings.Count(ll, "fcmp o"); got != 24 { + t.Fatalf("ARM64 %s float-compare lowering for %s emitted %d compares, want 24:\n%s", name, triple, got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-"+name+"-float-compare.ll", "arm64-"+name+"-float-compare.o", ll) + }) + } + }) + } +} + +func TestARM64RawFloatCompareRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawfloatcompare(SB),$0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V1.S4] + WORD $0x4e21e402 // FCMEQ V2.4S, V0.4S, V1.4S + WORD $0x6e21e403 // FCMGE V3.4S, V0.4S, V1.4S + WORD $0x6ea1e404 // FCMGT V4.4S, V0.4S, V1.4S + WORD $0x4ea0d805 // FCMEQ V5.4S, V0.4S, #0.0 + WORD $0x6ea0c806 // FCMGE V6.4S, V0.4S, #0.0 + WORD $0x4ea0c807 // FCMGT V7.4S, V0.4S, #0.0 + WORD $0x6ea0d808 // FCMLE V8.4S, V0.4S, #0.0 + WORD $0x4ea0e809 // FCMLT V9.4S, V0.4S, #0.0 + VST1.P [V2.S4, V3.S4, V4.S4, V5.S4], 64(R2) + VST1 [V6.S4, V7.S4, V8.S4, V9.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfloatcompare": { + Name: "rawfloatcompare", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawfloatcompare(const float *, const float *, uint32_t *); +int main(void) { + const float a[4] = {-2.0f, 0.0f, 3.0f, 4.0f}; + const float b[4] = {-2.0f, 1.0f, 2.0f, 5.0f}; + const unsigned truth[8][4] = { + {1,0,0,0}, {1,0,1,0}, {0,0,1,0}, {0,1,0,0}, + {0,1,1,1}, {0,0,1,1}, {1,1,0,0}, {1,0,0,0}, + }; + uint32_t got[32] = {0}; + rawfloatcompare(a, b, got); + for (int op = 0; op < 8; op++) for (int lane = 0; lane < 4; lane++) + if (got[op*4+lane] != (truth[op][lane] ? UINT32_MAX : 0)) return op*4+lane+1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_float_compare", triple, ll, mainC, nil) +} + +func TestARM64RawFloatCompareDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{0x2e20d400, 0x1e21e400, 0x0e60e400, 0x0ee0d800} { // FADDP, scalar compare, binary D1, zero D1. + if _, ok := decodeARM64RawFloatCompare(word); ok { + t.Fatalf("float-compare decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} diff --git a/arm64_lower_word_float_multiply_element.go b/arm64_lower_word_float_multiply_element.go new file mode 100644 index 00000000..3fd9b6de --- /dev/null +++ b/arm64_lower_word_float_multiply_element.go @@ -0,0 +1,110 @@ +package plan9asm + +import "fmt" + +type arm64RawFMULByElement struct { + vector bool + arrangement arm64VectorArrangement + lane int + elementReg int + sourceReg int + destination int +} + +func decodeARM64RawFMULByElement(word uint32) (arm64RawFMULByElement, bool) { + scalarHalf := word&0xffc0f400 == 0x5f009000 + vectorHalf := word&0xbfc0f400 == 0x0f009000 + scalar := scalarHalf || word&0xff80f400 == 0x5f809000 + vector := vectorHalf || word&0xbf80f400 == 0x0f809000 + if !scalar && !vector { + return arm64RawFMULByElement{}, false + } + + elementBits := 16 + if !scalarHalf && !vectorHalf { + elementBits = 32 + } + if elementBits == 32 && word&(1<<22) != 0 { + elementBits = 64 + } + // The L bit is part of the lane index for S elements, but is reserved for + // D elements. The vector encoding also reserves its 64-bit D1 combination. + if elementBits == 64 && word&(1<<21) != 0 { + return arm64RawFMULByElement{}, false + } + vectorBits := elementBits + if vector { + vectorBits = 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + if elementBits == 64 && vectorBits == 64 { + return arm64RawFMULByElement{}, false + } + } + lane := int(word>>11) & 1 + if elementBits == 16 { + lane = lane<<2 | (int(word>>21)&1)<<1 | int(word>>20)&1 + } else if elementBits == 32 { + lane = lane<<1 | int(word>>21)&1 + } + elementReg := int(word>>16) & 31 + if elementBits == 16 { + elementReg &= 15 + } + return arm64RawFMULByElement{ + vector: vector, + arrangement: arm64VectorArrangement{elementBits: elementBits, lanes: vectorBits / elementBits}, + lane: lane, + elementReg: elementReg, + sourceReg: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawFMULByElement(form arm64RawFMULByElement) error { + bits := form.arrangement.elementBits + floatType := "float" + if bits == 16 { + floatType = "half" + } else if bits == 64 { + floatType = "double" + } + elementBytes, err := c.loadVReg(Reg(fmt.Sprintf("V%d", form.elementReg))) + if err != nil { + return err + } + physicalLanes := 128 / bits + typedElements := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x %s>\n", typedElements, elementBytes, physicalLanes, floatType) + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %%%s, i32 %d\n", element, physicalLanes, floatType, typedElements, form.lane) + + if !form.vector { + sourceReg := Reg(fmt.Sprintf("F%d", form.sourceReg)) + destinationReg := Reg(fmt.Sprintf("F%d", form.destination)) + source, err := c.loadARM64ScalarFloatReg(sourceReg, bits) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fmul %s %s, %%%s\n", result, floatType, source, element) + return c.storeARM64ScalarFloatReg(destinationReg, bits, "%"+result) + } + + arrangementName := arm64VectorArrangementName(form.arrangement) + sourceReg := Reg(fmt.Sprintf("V%d.%s", form.sourceReg, arrangementName)) + destinationReg := Reg(fmt.Sprintf("V%d.%s", form.destination, arrangementName)) + source, err := c.loadARM64VectorFloat(sourceReg, form.arrangement) + if err != nil { + return err + } + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x %s> poison, %s %%%s, i32 0\n", seed, form.arrangement.lanes, floatType, floatType, element) + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x %s> %%%s, <%d x %s> poison, <%d x i32> zeroinitializer\n", + splat, form.arrangement.lanes, floatType, seed, form.arrangement.lanes, floatType, form.arrangement.lanes) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fmul <%d x %s> %s, %%%s\n", result, form.arrangement.lanes, floatType, source, splat) + return c.storeARM64VectorFloat(destinationReg, form.arrangement, "%"+result) +} diff --git a/arm64_lower_word_float_multiply_element_test.go b/arm64_lower_word_float_multiply_element_test.go new file mode 100644 index 00000000..12c76ce9 --- /dev/null +++ b/arm64_lower_word_float_multiply_element_test.go @@ -0,0 +1,193 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func arm64EncodeRawFMULByElement(vector bool, bits, vectorBits, lane, rm, rn, rd int) uint32 { + base := uint32(0x5f009000) + if vector { + base = 0x0f009000 + if vectorBits == 128 { + base |= 1 << 30 + } + } + if bits >= 32 { + base |= 1 << 23 + } + if bits == 16 { + base |= uint32(lane&1) << 20 + base |= uint32((lane>>1)&1) << 21 + base |= uint32((lane>>2)&1) << 11 + rm &= 15 + } else if bits == 64 { + base |= 1 << 22 + base |= uint32(lane&1) << 11 + } else { + base |= uint32(lane&1) << 21 + base |= uint32((lane>>1)&1) << 11 + } + return base | uint32(rm)<<16 | uint32(rn)<<5 | uint32(rd) +} + +func TestTranslateARM64RawFMULByElementCompleteArchitecturalFormats(t *testing.T) { + type format struct { + vector bool + bits int + vectorBits int + lanes int + } + formats := []format{ + {vector: false, bits: 16, vectorBits: 16, lanes: 8}, + {vector: false, bits: 32, vectorBits: 32, lanes: 4}, + {vector: false, bits: 64, vectorBits: 64, lanes: 2}, + {vector: true, bits: 16, vectorBits: 64, lanes: 8}, + {vector: true, bits: 16, vectorBits: 128, lanes: 8}, + {vector: true, bits: 32, vectorBits: 64, lanes: 4}, + {vector: true, bits: 32, vectorBits: 128, lanes: 4}, + {vector: true, bits: 64, vectorBits: 128, lanes: 2}, + } + var source strings.Builder + source.WriteString("TEXT rawfmulbyelementforms(SB),$0-0\n") + for _, form := range formats { + for lane := 0; lane < form.lanes; lane++ { + lastElementRegister := 31 + if form.bits == 16 { + lastElementRegister = 15 + } + for _, rm := range []int{0, lastElementRegister} { + word := arm64EncodeRawFMULByElement(form.vector, form.bits, form.vectorBits, lane, rm, 30, 29) + decoded, ok := decodeARM64RawFMULByElement(word) + if !ok || decoded.vector != form.vector || decoded.arrangement.elementBits != form.bits || decoded.arrangement.lanes != form.vectorBits/form.bits || decoded.lane != lane || decoded.elementReg != rm || decoded.sourceReg != 30 || decoded.destination != 29 { + t.Fatalf("decode FMUL element %#08x = %#v, %v", word, decoded, ok) + } + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfmulbyelementforms": {Name: "rawfmulbyelementforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if got, want := strings.Count(ir, "fmul "), 80; got != want { + t.Fatalf("raw FMUL-by-element emitted %d multiplies, want %d:\n%s", got, want, ir) + } + if !strings.Contains(ir, "+fullfp16") { + t.Fatalf("raw half-precision FMUL-by-element for %s omitted +fullfp16:\n%s", triple, ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-fmul-by-element.ll", "arm64-raw-fmul-by-element.o", ir) + }) + } +} + +func TestARM64RawFMULByElementDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x0fc09000, // reserved vector D1 + 0x4fe09000, // reserved D2 with L=1 + 0x0f801000, // FMLA by element + 0x2f809000, // FMULX by element + } { + if _, ok := decodeARM64RawFMULByElement(word); ok { + t.Fatalf("FMUL-by-element decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} + +func TestARM64RawFMULByElementRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawfmulbyelement(SB),$0-24 + MOVD input+0(FP), R0 + MOVD factors+8(FP), R1 + MOVD output+16(FP), R2 + VLD1 (R0), [V1.S4] + VLD1 (R1), [V0.S4] + WORD $0x4f809021 // FMUL V1.4S, V1.4S, V0.S[0] + VST1 [V1.S4], (R2) + RET + +TEXT rawfmulbyelementhalf(SB),$0-24 + MOVD input+0(FP), R0 + MOVD factors+8(FP), R1 + MOVD output+16(FP), R2 + VLD1 (R0), [V1.H8] + VLD1 (R1), [V0.H8] + WORD $0x4f309821 // FMUL V1.8H, V1.8H, V0.H[7] + VST1 [V1.H8], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawfmulbyelement": { + Name: "rawfmulbyelement", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + "rawfmulbyelementhalf": { + Name: "rawfmulbyelementhalf", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +extern void rawfmulbyelement(const float *, const float *, float *); +extern void rawfmulbyelementhalf(const _Float16 *, const _Float16 *, _Float16 *); +int main(void) { + const float input[4] = {1.5f, -2.0f, 3.25f, -4.5f}; + const float factors[4] = {2.0f, 7.0f, 11.0f, 13.0f}; + float got[4] = {0}; + rawfmulbyelement(input, factors, got); + for (int i = 0; i < 4; i++) if (got[i] != input[i] * factors[0]) return i + 1; + const _Float16 input_h[8] = {1,2,3,4,5,6,7,8}; + const _Float16 factors_h[8] = {2,3,4,5,6,7,8,9}; + _Float16 got_h[8] = {0}; + rawfmulbyelementhalf(input_h, factors_h, got_h); + for (int i = 0; i < 8; i++) if (got_h[i] != input_h[i] * factors_h[7]) return i + 5; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_fmul_by_element", triple, ir, mainC, nil) +} diff --git a/arm64_lower_word_float_multiply_long.go b/arm64_lower_word_float_multiply_long.go new file mode 100644 index 00000000..3d3c2c58 --- /dev/null +++ b/arm64_lower_word_float_multiply_long.go @@ -0,0 +1,137 @@ +package plan9asm + +import "fmt" + +// arm64RawFloatMultiplyLong describes the complete Advanced SIMD FP16FML +// FMLAL/FMLAL2/FMLSL/FMLSL2 family. The inputs are half-precision values and +// the accumulator/result is single precision. +type arm64RawFloatMultiplyLong struct { + subtract bool + highHalf bool + byElement bool + lanes int + lane int + second int + first int + destination int +} + +func decodeARM64RawFloatMultiplyLong(word uint32) (arm64RawFloatMultiplyLong, bool) { + form := arm64RawFloatMultiplyLong{ + lanes: 2, + lane: -1, + second: int(word>>16) & 31, + first: int(word>>5) & 31, + destination: int(word) & 31, + } + if word&(1<<30) != 0 { + form.lanes = 4 + } + + // Vector encodings vary Q and the three five-bit register fields. + switch word & 0xbfe0fc00 { + case 0x0e20ec00: // FMLAL. + return form, true + case 0x2e20cc00: // FMLAL2. + form.highHalf = true + return form, true + case 0x0ea0ec00: // FMLSL. + form.subtract = true + return form, true + case 0x2ea0cc00: // FMLSL2. + form.subtract, form.highHalf = true, true + return form, true + } + + // By-element encodings limit Rm to V0..V15 and encode lane H:L:M in + // bits 11, 21, and 20. Q selects a two- or four-lane result. + form.byElement = true + form.second &= 15 + form.lane = int(word>>11)&1<<2 | int(word>>21)&1<<1 | int(word>>20)&1 + switch word & 0xbfc0f400 { + case 0x0f800000: // FMLAL by element. + return form, true + case 0x2f808000: // FMLAL2 by element. + form.highHalf = true + return form, true + case 0x0f804000: // FMLSL by element. + form.subtract = true + return form, true + case 0x2f80c000: // FMLSL2 by element. + form.subtract, form.highHalf = true, true + return form, true + default: + return arm64RawFloatMultiplyLong{}, false + } +} + +func (c *arm64Ctx) lowerRawFloatMultiplyLong(form arm64RawFloatMultiplyLong) error { + halfArrangement := arm64VectorArrangement{elementBits: 16, lanes: 8} + floatArrangement := arm64VectorArrangement{elementBits: 32, lanes: form.lanes} + first, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.first)), halfArrangement) + if err != nil { + return err + } + + selectHalf := func(value string) string { + selected := c.newTmp() + offset := 0 + if form.highHalf { + offset = form.lanes + } + fmt.Fprintf(c.b, " %%%s = shufflevector <8 x half> %s, <8 x half> poison, <%d x i32> <", selected, value, form.lanes) + for lane := 0; lane < form.lanes; lane++ { + if lane != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", offset+lane) + } + c.b.WriteString(">\n") + return "%" + selected + } + first = selectHalf(first) + + var second string + if form.byElement { + all, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.second)), halfArrangement) + if err != nil { + return err + } + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <8 x half> %s, i32 %d\n", element, all, form.lane) + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x half> poison, half %%%s, i32 0\n", seed, form.lanes, element) + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x half> %%%s, <%d x half> poison, <%d x i32> zeroinitializer\n", + splat, form.lanes, seed, form.lanes, form.lanes) + second = "%" + splat + } else { + all, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.second)), halfArrangement) + if err != nil { + return err + } + second = selectHalf(all) + } + + vectorHalfType := fmt.Sprintf("<%d x half>", form.lanes) + vectorFloatType := fmt.Sprintf("<%d x float>", form.lanes) + wideFirst := c.newTmp() + wideSecond := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fpext %s %s to %s\n", wideFirst, vectorHalfType, first, vectorFloatType) + fmt.Fprintf(c.b, " %%%s = fpext %s %s to %s\n", wideSecond, vectorHalfType, second, vectorFloatType) + firstOperand := "%" + wideFirst + if form.subtract { + negated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", negated, vectorFloatType, firstOperand) + firstOperand = "%" + negated + } + accumulator, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.destination)), floatArrangement) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.fma.v%df32(%s %s, %s %%%s, %s %s)\n", + result, vectorFloatType, form.lanes, + vectorFloatType, firstOperand, vectorFloatType, wideSecond, vectorFloatType, accumulator) + return c.storeARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.destination)), floatArrangement, "%"+result) +} diff --git a/arm64_lower_word_float_multiply_long_test.go b/arm64_lower_word_float_multiply_long_test.go new file mode 100644 index 00000000..9c8a0af3 --- /dev/null +++ b/arm64_lower_word_float_multiply_long_test.go @@ -0,0 +1,201 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +type arm64RawFloatMultiplyLongTestOperation struct { + name string + vectorBase uint32 + elementBase uint32 + subtract bool + highHalf bool +} + +var arm64RawFloatMultiplyLongTestOperations = []arm64RawFloatMultiplyLongTestOperation{ + {name: "FMLAL", vectorBase: 0x0e20ec00, elementBase: 0x0f800000}, + {name: "FMLAL2", vectorBase: 0x2e20cc00, elementBase: 0x2f808000, highHalf: true}, + {name: "FMLSL", vectorBase: 0x0ea0ec00, elementBase: 0x0f804000, subtract: true}, + {name: "FMLSL2", vectorBase: 0x2ea0cc00, elementBase: 0x2f80c000, subtract: true, highHalf: true}, +} + +func encodeARM64RawFloatMultiplyLongVector(base uint32, lanes, second, first, destination int) uint32 { + word := base | uint32(second)<<16 | uint32(first)<<5 | uint32(destination) + if lanes == 4 { + word |= 1 << 30 + } + return word +} + +func encodeARM64RawFloatMultiplyLongElement(base uint32, lanes, lane, element, first, destination int) uint32 { + word := base | uint32(element&15)<<16 | uint32(first)<<5 | uint32(destination) + if lanes == 4 { + word |= 1 << 30 + } + word |= uint32(lane&1) << 20 + word |= uint32((lane>>1)&1) << 21 + word |= uint32((lane>>2)&1) << 11 + return word +} + +func TestTranslateARM64RawFloatMultiplyLongCompleteArchitecturalFamily(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawfloatmultiplylongforms(SB),$0-0\n") + for _, operation := range arm64RawFloatMultiplyLongTestOperations { + for _, lanes := range []int{2, 4} { + word := encodeARM64RawFloatMultiplyLongVector(operation.vectorBase, lanes, 31, 30, 29) + fmt.Fprintf(&source, "\tWORD $%#08x // %s vector %dS\n", word, operation.name, lanes) + for lane := 0; lane < 8; lane++ { + word = encodeARM64RawFloatMultiplyLongElement(operation.elementBase, lanes, lane, 15, 28, 27) + fmt.Fprintf(&source, "\tWORD $%#08x // %s element %dS lane %d\n", word, operation.name, lanes, lane) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfloatmultiplylongforms": {Name: "rawfloatmultiplylongforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"fpext <2 x half>", "fpext <4 x half>", "@llvm.fma.v2f32", "@llvm.fma.v4f32", "extractelement <8 x half>", "shufflevector", "+fp16fml"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw floating multiply-long family for %s omitted %q:\n%s", triple, want, ir) + } + } + compileLLVMToObject(t, llc, triple, "arm64-raw-float-multiply-long.ll", "arm64-raw-float-multiply-long.o", ir) + }) + } +} + +func TestARM64RawFloatMultiplyLongDecoderCoversEveryEncodingField(t *testing.T) { + for _, operation := range arm64RawFloatMultiplyLongTestOperations { + for _, lanes := range []int{2, 4} { + for destination := 0; destination < 32; destination++ { + word := encodeARM64RawFloatMultiplyLongVector(operation.vectorBase, lanes, 31-destination, destination, destination) + got, ok := decodeARM64RawFloatMultiplyLong(word) + if !ok || got.byElement || got.lanes != lanes || got.first != destination || got.second != 31-destination || got.destination != destination || got.subtract != operation.subtract || got.highHalf != operation.highHalf { + t.Fatalf("decode %s vector %#08x = %#v, %v", operation.name, word, got, ok) + } + } + for lane := 0; lane < 8; lane++ { + for element := 0; element < 16; element++ { + word := encodeARM64RawFloatMultiplyLongElement(operation.elementBase, lanes, lane, element, 31-element, element) + got, ok := decodeARM64RawFloatMultiplyLong(word) + if !ok || !got.byElement || got.lanes != lanes || got.lane != lane || got.first != 31-element || got.second != element || got.destination != element || got.subtract != operation.subtract || got.highHalf != operation.highHalf { + t.Fatalf("decode %s element %#08x = %#v, %v", operation.name, word, got, ok) + } + } + } + } + } +} + +func TestARM64RawFloatMultiplyLongDecoderRejectsAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x0e20e800, 0x0e20f000, 0x2e20ec00, + 0x0f800400, 0x0f801000, 0x2f800000, + } { + if _, ok := decodeARM64RawFloatMultiplyLong(word); ok { + t.Fatalf("floating multiply-long decoder accepted adjacent encoding %#08x", word) + } + } +} + +func TestARM64RawFloatMultiplyLongRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + words := []uint32{ + encodeARM64RawFloatMultiplyLongVector(0x0e20ec00, 4, 2, 1, 0), + encodeARM64RawFloatMultiplyLongVector(0x2e20cc00, 4, 2, 1, 0), + encodeARM64RawFloatMultiplyLongVector(0x0ea0ec00, 4, 2, 1, 0), + encodeARM64RawFloatMultiplyLongVector(0x2ea0cc00, 4, 2, 1, 0), + encodeARM64RawFloatMultiplyLongElement(0x0f800000, 4, 7, 2, 1, 0), + encodeARM64RawFloatMultiplyLongElement(0x2f808000, 4, 3, 2, 1, 0), + encodeARM64RawFloatMultiplyLongElement(0x0f804000, 4, 1, 2, 1, 0), + encodeARM64RawFloatMultiplyLongElement(0x2f80c000, 4, 6, 2, 1, 0), + } + var source strings.Builder + source.WriteString(`TEXT rawfloatmultiplylong(SB),$0-32 + MOVD source+0(FP), R0 + MOVD elements+8(FP), R1 + MOVD accumulator+16(FP), R2 + MOVD output+24(FP), R3 + VLD1 (R0), [V1.H8] + VLD1 (R1), [V2.H8] +`) + for _, word := range words { + source.WriteString("\tVLD1 (R2), [V0.S4]\n") + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + source.WriteString("\tVST1 [V0.S4], (R3)\n\tADD $16, R3\n") + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfloatmultiplylong": { + Name: "rawfloatmultiplylong", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawfloatmultiplylong(const _Float16 *, const _Float16 *, const float *, float *); +int main(void) { + const _Float16 source[8] = {1,2,3,4,5,6,7,8}; + const _Float16 elements[8] = {10,20,30,40,50,60,70,80}; + const float accumulator[4] = {1000,2000,3000,4000}; + float got[32] = {0}; + float want[32] = {0}; + rawfloatmultiplylong(source, elements, accumulator, got); + for (int i = 0; i < 4; i++) { + want[0*4+i] = accumulator[i] + (float)source[i] * (float)elements[i]; + want[1*4+i] = accumulator[i] + (float)source[i+4] * (float)elements[i+4]; + want[2*4+i] = accumulator[i] - (float)source[i] * (float)elements[i]; + want[3*4+i] = accumulator[i] - (float)source[i+4] * (float)elements[i+4]; + want[4*4+i] = accumulator[i] + (float)source[i] * (float)elements[7]; + want[5*4+i] = accumulator[i] + (float)source[i+4] * (float)elements[3]; + want[6*4+i] = accumulator[i] - (float)source[i] * (float)elements[1]; + want[7*4+i] = accumulator[i] - (float)source[i+4] * (float)elements[6]; + } + for (int i = 0; i < 32; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_float_multiply_long", triple, ir, mainC, nil) +} diff --git a/arm64_lower_word_float_pairwise_minmax.go b/arm64_lower_word_float_pairwise_minmax.go new file mode 100644 index 00000000..267bfd60 --- /dev/null +++ b/arm64_lower_word_float_pairwise_minmax.go @@ -0,0 +1,118 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +type arm64RawFloatPairwiseMinMax struct { + operation string + scalar bool + arrangement arm64VectorArrangement + first int + second int + destination int +} + +func arm64LLVMShuffleMask(indices []int) string { + values := make([]string, len(indices)) + for i, index := range indices { + values[i] = fmt.Sprintf("i32 %d", index) + } + return fmt.Sprintf("<%d x i32> <%s>", len(indices), strings.Join(values, ", ")) +} + +func decodeARM64RawFloatPairwiseMinMax(word uint32) (arm64RawFloatPairwiseMinMax, bool) { + const vectorRegisters = uint32(31 | 31<<5 | 31<<16) + vectorForms := map[uint32]struct { + operation string + bits int + lanes int + }{ + 0x2e403400: {"maximum", 16, 4}, 0x6e403400: {"maximum", 16, 8}, + 0x2e20f400: {"maximum", 32, 2}, 0x6e20f400: {"maximum", 32, 4}, 0x6e60f400: {"maximum", 64, 2}, + 0x2ec03400: {"minimum", 16, 4}, 0x6ec03400: {"minimum", 16, 8}, + 0x2ea0f400: {"minimum", 32, 2}, 0x6ea0f400: {"minimum", 32, 4}, 0x6ee0f400: {"minimum", 64, 2}, + 0x2e400400: {"maxnum", 16, 4}, 0x6e400400: {"maxnum", 16, 8}, + 0x2e20c400: {"maxnum", 32, 2}, 0x6e20c400: {"maxnum", 32, 4}, 0x6e60c400: {"maxnum", 64, 2}, + 0x2ec00400: {"minnum", 16, 4}, 0x6ec00400: {"minnum", 16, 8}, + 0x2ea0c400: {"minnum", 32, 2}, 0x6ea0c400: {"minnum", 32, 4}, 0x6ee0c400: {"minnum", 64, 2}, + } + if form, ok := vectorForms[word&^vectorRegisters]; ok { + return arm64RawFloatPairwiseMinMax{ + operation: form.operation, + arrangement: arm64VectorArrangement{ + elementBits: form.bits, + lanes: form.lanes, + }, + first: int(word>>5) & 31, + second: int(word>>16) & 31, + destination: int(word) & 31, + }, true + } + + const scalarRegisters = uint32(31 | 31<<5) + scalarForms := map[uint32]struct { + operation string + bits int + }{ + 0x5e30f800: {"maximum", 16}, 0x7e30f800: {"maximum", 32}, 0x7e70f800: {"maximum", 64}, + 0x5eb0f800: {"minimum", 16}, 0x7eb0f800: {"minimum", 32}, 0x7ef0f800: {"minimum", 64}, + 0x5e30c800: {"maxnum", 16}, 0x7e30c800: {"maxnum", 32}, 0x7e70c800: {"maxnum", 64}, + 0x5eb0c800: {"minnum", 16}, 0x7eb0c800: {"minnum", 32}, 0x7ef0c800: {"minnum", 64}, + } + if form, ok := scalarForms[word&^scalarRegisters]; ok { + return arm64RawFloatPairwiseMinMax{ + operation: form.operation, + scalar: true, + arrangement: arm64VectorArrangement{elementBits: form.bits, lanes: 2}, + first: int(word>>5) & 31, + second: -1, + destination: int(word) & 31, + }, true + } + return arm64RawFloatPairwiseMinMax{}, false +} + +func (c *arm64Ctx) lowerRawFloatPairwiseMinMax(form arm64RawFloatPairwiseMinMax) error { + first, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.first)), form.arrangement) + if err != nil { + return err + } + floatType := arm64RawFloatType(form.arrangement.elementBits) + intrinsicSuffix := fmt.Sprintf("f%d", form.arrangement.elementBits) + if form.scalar { + left := c.newTmp() + right := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <2 x %s> %s, i32 0\n", left, floatType, first) + fmt.Fprintf(c.b, " %%%s = extractelement <2 x %s> %s, i32 1\n", right, floatType, first) + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.%s(%s %%%s, %s %%%s)\n", + result, floatType, form.operation, intrinsicSuffix, floatType, left, floatType, right) + return c.storeARM64ScalarFloatReg(Reg(fmt.Sprintf("F%d", form.destination)), form.arrangement.elementBits, "%"+result) + } + + second, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.second)), form.arrangement) + if err != nil { + return err + } + lanes := form.arrangement.lanes + leftMask := make([]int, 0, lanes) + rightMask := make([]int, 0, lanes) + for source := 0; source < 2; source++ { + base := source * lanes + for lane := 0; lane < lanes/2; lane++ { + leftMask = append(leftMask, base+lane*2) + rightMask = append(rightMask, base+lane*2+1) + } + } + left := c.newTmp() + right := c.newTmp() + vectorType := fmt.Sprintf("<%d x %s>", lanes, floatType) + fmt.Fprintf(c.b, " %%%s = shufflevector %s %s, %s %s, %s\n", left, vectorType, first, vectorType, second, arm64LLVMShuffleMask(leftMask)) + fmt.Fprintf(c.b, " %%%s = shufflevector %s %s, %s %s, %s\n", right, vectorType, first, vectorType, second, arm64LLVMShuffleMask(rightMask)) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.v%d%s(%s %%%s, %s %%%s)\n", + result, vectorType, form.operation, lanes, intrinsicSuffix, vectorType, left, vectorType, right) + return c.storeARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.destination)), form.arrangement, "%"+result) +} diff --git a/arm64_lower_word_float_pairwise_minmax_test.go b/arm64_lower_word_float_pairwise_minmax_test.go new file mode 100644 index 00000000..642ac408 --- /dev/null +++ b/arm64_lower_word_float_pairwise_minmax_test.go @@ -0,0 +1,140 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64RawFloatPairwiseMinMaxCompleteArchitecturalFormats(t *testing.T) { + ops := []struct { + name string + vectorBases []uint32 + scalarBases []uint32 + intrinsic string + }{ + {"fmaxp", []uint32{0x2e403400, 0x6e403400, 0x2e20f400, 0x6e20f400, 0x6e60f400}, []uint32{0x5e30f800, 0x7e30f800, 0x7e70f800}, "maximum"}, + {"fminp", []uint32{0x2ec03400, 0x6ec03400, 0x2ea0f400, 0x6ea0f400, 0x6ee0f400}, []uint32{0x5eb0f800, 0x7eb0f800, 0x7ef0f800}, "minimum"}, + {"fmaxnmp", []uint32{0x2e400400, 0x6e400400, 0x2e20c400, 0x6e20c400, 0x6e60c400}, []uint32{0x5e30c800, 0x7e30c800, 0x7e70c800}, "maxnum"}, + {"fminnmp", []uint32{0x2ec00400, 0x6ec00400, 0x2ea0c400, 0x6ea0c400, 0x6ee0c400}, []uint32{0x5eb0c800, 0x7eb0c800, 0x7ef0c800}, "minnum"}, + } + var source strings.Builder + source.WriteString("TEXT rawfloatpairwiseminmaxforms(SB),$0-0\n") + for _, op := range ops { + for _, base := range op.vectorBases { + fmt.Fprintf(&source, "\tWORD $%#08x // %s vector\n", base|29<<16|30<<5|28, op.name) + } + for _, base := range op.scalarBases { + fmt.Fprintf(&source, "\tWORD $%#08x // %s scalar\n", base|30<<5|29, op.name) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfloatpairwiseminmaxforms": {Name: "rawfloatpairwiseminmaxforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, op := range ops { + for _, suffix := range []string{"f16", "f32", "f64", "v4f16", "v8f16", "v2f32", "v4f32", "v2f64"} { + want := "@llvm." + op.intrinsic + "." + suffix + if !strings.Contains(ir, want) { + t.Fatalf("raw %s for %s omitted %s:\n%s", op.name, triple, want, ir) + } + } + } + compileLLVMToObject(t, llc, triple, "raw-float-pairwise-minmax.ll", "raw-float-pairwise-minmax.o", ir) + }) + } +} + +func TestARM64RawFloatPairwiseMinMaxDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x2e60f400, // reserved D1 vector arrangement + 0x2e20d400, // FADDP + 0x7e30d800, // scalar FADDP + 0x2e403800, // adjacent FP16 opcode bits + 0x5e70f800, // reserved scalar FP16 size combination + } { + if _, ok := decodeARM64RawFloatPairwiseMinMax(word); ok { + t.Fatalf("pairwise min/max decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} + +func TestARM64RawFloatPairwiseMinMaxRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawfloatpairwiseminmax(SB),$0-16 + MOVD input+0(FP), R0 + MOVD output+8(FP), R1 + VLD1 (R0), [V0.S4] + WORD $0x6e20f401 // FMAXP V1.4S, V0.4S, V0.4S + WORD $0x6ea0f402 // FMINP V2.4S, V0.4S, V0.4S + WORD $0x6e20c403 // FMAXNMP V3.4S, V0.4S, V0.4S + WORD $0x6ea0c404 // FMINNMP V4.4S, V0.4S, V0.4S + WORD $0x7e30f805 // FMAXP S5, V0.2S + WORD $0x7eb0f806 // FMINP S6, V0.2S + VST1.P [V1.S4], 16(R1) + VST1.P [V2.S4], 16(R1) + VST1.P [V3.S4], 16(R1) + VST1.P [V4.S4], 16(R1) + FMOVS F5, 0(R1) + FMOVS F6, 4(R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfloatpairwiseminmax": { + Name: "rawfloatpairwiseminmax", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +extern void rawfloatpairwiseminmax(const float *, float *); +int main(void) { + const float input[4] = {-2, 7, 3, 1}; + const float want[18] = { + 7,3,7,3, -2,1,-2,1, 7,3,7,3, -2,1,-2,1, 7,-2 + }; + float got[18] = {0}; + rawfloatpairwiseminmax(input, got); + for (int i = 0; i < 18; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_float_pairwise_minmax", triple, ir, mainC, nil) +} diff --git a/arm64_lower_word_float_round.go b/arm64_lower_word_float_round.go new file mode 100644 index 00000000..8500df9b --- /dev/null +++ b/arm64_lower_word_float_round.go @@ -0,0 +1,62 @@ +package plan9asm + +import "fmt" + +type arm64RawVectorFloatRound struct { + operation string + arrangement arm64VectorArrangement + source int + destination int +} + +func decodeARM64RawVectorFloatRound(word uint32) (arm64RawVectorFloatRound, bool) { + operation := "" + switch word & 0xbfbffc00 { + case 0x2e218800: + operation = "round" + case 0x2e219800: + operation = "rint" + case 0x2ea19800: + operation = "nearbyint" + default: + return arm64RawVectorFloatRound{}, false + } + elementBits := 32 + if word&(1<<22) != 0 { + elementBits = 64 + } + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + if elementBits == 64 && vectorBits == 64 { + return arm64RawVectorFloatRound{}, false + } + return arm64RawVectorFloatRound{ + operation: operation, + arrangement: arm64VectorArrangement{elementBits: elementBits, lanes: vectorBits / elementBits}, + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawVectorFloatRound(form arm64RawVectorFloatRound) error { + arrangementName := arm64VectorArrangementName(form.arrangement) + sourceReg := Reg(fmt.Sprintf("V%d.%s", form.source, arrangementName)) + destinationReg := Reg(fmt.Sprintf("V%d.%s", form.destination, arrangementName)) + source, err := c.loadARM64VectorFloat(sourceReg, form.arrangement) + if err != nil { + return err + } + floatType := "float" + suffix := fmt.Sprintf("v%df32", form.arrangement.lanes) + if form.arrangement.elementBits == 64 { + floatType = "double" + suffix = fmt.Sprintf("v%df64", form.arrangement.lanes) + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call <%d x %s> @llvm.%s.%s(<%d x %s> %s)\n", + result, form.arrangement.lanes, floatType, form.operation, suffix, + form.arrangement.lanes, floatType, source) + return c.storeARM64VectorFloat(destinationReg, form.arrangement, "%"+result) +} diff --git a/arm64_lower_word_float_round_test.go b/arm64_lower_word_float_round_test.go new file mode 100644 index 00000000..f49e858a --- /dev/null +++ b/arm64_lower_word_float_round_test.go @@ -0,0 +1,116 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64RawVectorFloatRoundCompleteArchitecturalFormats(t *testing.T) { + bases := []uint32{0x2e218800, 0x2e219800, 0x2ea19800} // FRINTA, FRINTX, FRINTI. + modifiers := []uint32{0, 1 << 30, 1<<30 | 1<<22} // S2, S4, D2. + var source strings.Builder + source.WriteString("TEXT rawvectorfloatroundforms(SB),$0-0\n") + for _, base := range bases { + for _, modifier := range modifiers { + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|modifier|30<<5|29) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawvectorfloatroundforms": {Name: "rawvectorfloatroundforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{"@llvm.round.", "@llvm.rint.", "@llvm.nearbyint."} { + if !strings.Contains(ir, intrinsic) { + t.Fatalf("raw vector floating round omitted %s:\n%s", intrinsic, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-vector-float-round.ll", "arm64-raw-vector-float-round.o", ir) + }) + } +} + +func TestARM64RawVectorFloatRoundDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x2e618800, // reserved FRINTA D1 + 0x2e218000, // FRINTN + 0x2e219000, // FRINTP + 0x2e219800 | 1<<10, + } { + if _, ok := decodeARM64RawVectorFloatRound(word); ok { + t.Fatalf("vector floating round decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} + +func TestARM64RawVectorFloatRoundRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawvectorfloatround(SB),$0-16 + MOVD input+0(FP), R0 + MOVD output+8(FP), R1 + VLD1 (R0), [V0.S4] + WORD $0x6e218801 // FRINTA V0.S4, V1.S4 + WORD $0x6e219802 // FRINTX V0.S4, V2.S4 + WORD $0x6ea19803 // FRINTI V0.S4, V3.S4 + VST1 [V1.S4, V2.S4, V3.S4], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawvectorfloatround": { + Name: "rawvectorfloatround", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +extern void rawvectorfloatround(const float *, float *); +int main(void) { + const float input[4] = {1.5f, 2.5f, -1.5f, -2.5f}; + const float want[12] = {2,3,-2,-3, 2,2,-2,-2, 2,2,-2,-2}; + float got[12] = {0}; + rawvectorfloatround(input, got); + for (int i = 0; i < 12; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_vector_float_round", triple, ir, mainC, nil) +} diff --git a/arm64_lower_word_fmla.go b/arm64_lower_word_fmla.go new file mode 100644 index 00000000..00ca857b --- /dev/null +++ b/arm64_lower_word_fmla.go @@ -0,0 +1,178 @@ +package plan9asm + +import "fmt" + +type arm64RawFMLA struct { + subtract bool + indexed bool + scalar bool + arrangement arm64VectorArrangement + lane int + elementReg int + sourceReg int + destination int +} + +type arm64RawFMLAIndexedFormat struct { + base uint32 + subtract bool + scalar bool + elementBits int + vectorBits int +} + +var arm64RawFMLAIndexedFormats = [...]arm64RawFMLAIndexedFormat{ + {base: 0x5f001000, scalar: true, elementBits: 16, vectorBits: 16}, + {base: 0x5f005000, subtract: true, scalar: true, elementBits: 16, vectorBits: 16}, + {base: 0x5f801000, scalar: true, elementBits: 32, vectorBits: 32}, + {base: 0x5f805000, subtract: true, scalar: true, elementBits: 32, vectorBits: 32}, + {base: 0x5fc01000, scalar: true, elementBits: 64, vectorBits: 64}, + {base: 0x5fc05000, subtract: true, scalar: true, elementBits: 64, vectorBits: 64}, + {base: 0x0f001000, elementBits: 16, vectorBits: 64}, + {base: 0x0f005000, subtract: true, elementBits: 16, vectorBits: 64}, + {base: 0x4f001000, elementBits: 16, vectorBits: 128}, + {base: 0x4f005000, subtract: true, elementBits: 16, vectorBits: 128}, + {base: 0x0f801000, elementBits: 32, vectorBits: 64}, + {base: 0x0f805000, subtract: true, elementBits: 32, vectorBits: 64}, + {base: 0x4f801000, elementBits: 32, vectorBits: 128}, + {base: 0x4f805000, subtract: true, elementBits: 32, vectorBits: 128}, + {base: 0x4fc01000, elementBits: 64, vectorBits: 128}, + {base: 0x4fc05000, subtract: true, elementBits: 64, vectorBits: 128}, +} + +func decodeARM64RawFMLA(word uint32) (arm64RawFMLA, bool) { + const vectorRegisters = uint32(31 | 31<<5 | 31<<16) + form := arm64RawFMLA{} + switch word &^ vectorRegisters { + case 0x0e400c00: + form.arrangement = arm64VectorArrangement{elementBits: 16, lanes: 4} + case 0x4e400c00: + form.arrangement = arm64VectorArrangement{elementBits: 16, lanes: 8} + case 0x0e20cc00: + form.arrangement = arm64VectorArrangement{elementBits: 32, lanes: 2} + case 0x4e20cc00: + form.arrangement = arm64VectorArrangement{elementBits: 32, lanes: 4} + case 0x4e60cc00: + form.arrangement = arm64VectorArrangement{elementBits: 64, lanes: 2} + case 0x0ec00c00: + form.subtract, form.arrangement = true, arm64VectorArrangement{elementBits: 16, lanes: 4} + case 0x4ec00c00: + form.subtract, form.arrangement = true, arm64VectorArrangement{elementBits: 16, lanes: 8} + case 0x0ea0cc00: + form.subtract, form.arrangement = true, arm64VectorArrangement{elementBits: 32, lanes: 2} + case 0x4ea0cc00: + form.subtract, form.arrangement = true, arm64VectorArrangement{elementBits: 32, lanes: 4} + case 0x4ee0cc00: + form.subtract, form.arrangement = true, arm64VectorArrangement{elementBits: 64, lanes: 2} + } + if form.arrangement.elementBits != 0 { + form.elementReg = int(word>>16) & 31 + form.sourceReg = int(word>>5) & 31 + form.destination = int(word) & 31 + form.lane = -1 + return form, true + } + + for _, format := range arm64RawFMLAIndexedFormats { + variable := uint32(31 | 31<<5 | 31<<16 | 1<<11) + if format.elementBits == 16 { + variable = uint32(31 | 31<<5 | 15<<16 | 1<<20 | 1<<21 | 1<<11) + } else if format.elementBits == 32 { + variable |= 1 << 21 + } + if word&^variable != format.base { + continue + } + lane := int(word>>11) & 1 + elementReg := int(word>>16) & 31 + if format.elementBits == 16 { + lane = lane<<2 | (int(word>>21)&1)<<1 | int(word>>20)&1 + elementReg &= 15 + } else if format.elementBits == 32 { + lane = lane<<1 | int(word>>21)&1 + } + return arm64RawFMLA{ + subtract: format.subtract, + indexed: true, + scalar: format.scalar, + arrangement: arm64VectorArrangement{elementBits: format.elementBits, lanes: format.vectorBits / format.elementBits}, + lane: lane, + elementReg: elementReg, + sourceReg: int(word>>5) & 31, + destination: int(word) & 31, + }, true + } + return arm64RawFMLA{}, false +} + +func (c *arm64Ctx) lowerRawFMLA(form arm64RawFMLA) error { + bits := form.arrangement.elementBits + floatType := arm64RawFloatType(bits) + sourceReg := Reg(fmt.Sprintf("V%d", form.sourceReg)) + destinationReg := Reg(fmt.Sprintf("V%d", form.destination)) + var source, accumulator string + var err error + if form.scalar { + source, err = c.loadARM64ScalarFloatReg(Reg(fmt.Sprintf("F%d", form.sourceReg)), bits) + if err == nil { + accumulator, err = c.loadARM64ScalarFloatReg(Reg(fmt.Sprintf("F%d", form.destination)), bits) + } + } else { + source, err = c.loadARM64VectorFloat(sourceReg, form.arrangement) + if err == nil { + accumulator, err = c.loadARM64VectorFloat(destinationReg, form.arrangement) + } + } + if err != nil { + return err + } + + multiplier := "" + if form.indexed { + elementBytes, err := c.loadVReg(Reg(fmt.Sprintf("V%d", form.elementReg))) + if err != nil { + return err + } + physicalLanes := 128 / bits + typedElements := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <16 x i8> %s to <%d x %s>\n", typedElements, elementBytes, physicalLanes, floatType) + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %%%s, i32 %d\n", element, physicalLanes, floatType, typedElements, form.lane) + multiplier = "%" + element + if !form.scalar { + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x %s> poison, %s %s, i32 0\n", + seed, form.arrangement.lanes, floatType, floatType, multiplier) + splat := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x %s> %%%s, <%d x %s> poison, <%d x i32> zeroinitializer\n", + splat, form.arrangement.lanes, floatType, seed, form.arrangement.lanes, floatType, form.arrangement.lanes) + multiplier = "%" + splat + } + } else { + multiplier, err = c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.elementReg)), form.arrangement) + if err != nil { + return err + } + } + + if form.subtract { + negated := c.newTmp() + if form.scalar { + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", negated, floatType, source) + } else { + fmt.Fprintf(c.b, " %%%s = fneg <%d x %s> %s\n", negated, form.arrangement.lanes, floatType, source) + } + source = "%" + negated + } + result := c.newTmp() + if form.scalar { + fmt.Fprintf(c.b, " %%%s = call %s @llvm.fma.f%d(%s %s, %s %s, %s %s)\n", + result, floatType, bits, floatType, source, floatType, multiplier, floatType, accumulator) + return c.storeARM64ScalarFloatReg(Reg(fmt.Sprintf("F%d", form.destination)), bits, "%"+result) + } + vectorType := fmt.Sprintf("<%d x %s>", form.arrangement.lanes, floatType) + fmt.Fprintf(c.b, " %%%s = call %s @llvm.fma.v%df%d(%s %s, %s %s, %s %s)\n", + result, vectorType, form.arrangement.lanes, bits, + vectorType, source, vectorType, multiplier, vectorType, accumulator) + return c.storeARM64VectorFloat(destinationReg, form.arrangement, "%"+result) +} diff --git a/arm64_lower_word_fmla_test.go b/arm64_lower_word_fmla_test.go new file mode 100644 index 00000000..7ee01fa9 --- /dev/null +++ b/arm64_lower_word_fmla_test.go @@ -0,0 +1,207 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func arm64EncodeRawFMLAByElement(subtract, scalar bool, bits, vectorBits, lane, rm, rn, rd int) uint32 { + base := uint32(0x0f001000) + if scalar { + base = 0x5f001000 + } else if vectorBits == 128 { + base |= 1 << 30 + } + if subtract { + base |= 1 << 14 + } + switch bits { + case 16: + base |= uint32(lane&1) << 20 + base |= uint32((lane>>1)&1) << 21 + base |= uint32((lane>>2)&1) << 11 + case 32: + base |= 1 << 23 + base |= uint32(lane&1) << 21 + base |= uint32((lane>>1)&1) << 11 + case 64: + base |= 3 << 22 + base |= uint32(lane&1) << 11 + default: + panic(fmt.Sprintf("unsupported FMLA element width %d", bits)) + } + return base | uint32(rm)<<16 | uint32(rn)<<5 | uint32(rd) +} + +func TestARM64RawFMLADecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x0e60cc00, // reserved FMLA D1 vector arrangement. + 0x0ee0cc00, // reserved FMLS D1 vector arrangement. + 0x0fc01000, // reserved indexed FMLA D1 arrangement. + 0x0fc05000, // reserved indexed FMLS D1 arrangement. + 0x4fe01000, // indexed D form with reserved L bit. + 0x4fe05000, // indexed D subtract form with reserved L bit. + 0x0f809000, // FMUL by element. + 0x0e400800, // adjacent same-vector opcode. + } { + if _, ok := decodeARM64RawFMLA(word); ok { + t.Fatalf("FMLA/FMLS decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} + +func TestARM64RawFMLARuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + indexedAdd := arm64EncodeRawFMLAByElement(false, false, 16, 128, 7, 2, 1, 4) + indexedSubtract := arm64EncodeRawFMLAByElement(true, false, 16, 128, 6, 2, 1, 5) + scalarAdd := arm64EncodeRawFMLAByElement(false, true, 16, 16, 3, 2, 7, 6) + source := fmt.Sprintf(` +TEXT rawfmla(SB),$0-32 + MOVD accumulator+0(FP), R0 + MOVD multiplicand+8(FP), R1 + MOVD multiplier+16(FP), R2 + MOVD output+24(FP), R3 + VLD1 (R0), [V0.H8] + VLD1 (R0), [V3.H8] + VLD1 (R0), [V4.H8] + VLD1 (R0), [V5.H8] + VLD1 (R0), [V6.H8] + VLD1 (R1), [V1.H8] + VLD1 (R1), [V7.H8] + VLD1 (R2), [V2.H8] + WORD $0x4e420c20 // FMLA V0.8H, V1.8H, V2.8H + WORD $0x4ec20c23 // FMLS V3.8H, V1.8H, V2.8H + WORD $%#08x // FMLA V4.8H, V1.8H, V2.H[7] + WORD $%#08x // FMLS V5.8H, V1.8H, V2.H[6] + WORD $%#08x // FMLA H6, H7, V2.H[3] + VST1.P [V0.H8], 16(R3) + VST1.P [V3.H8], 16(R3) + VST1.P [V4.H8], 16(R3) + VST1.P [V5.H8], 16(R3) + VST1 [V6.H8], (R3) + RET +`, indexedAdd, indexedSubtract, scalarAdd) + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawfmla": { + Name: "rawfmla", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +typedef _Float16 f16; +extern void rawfmla(const f16 *, const f16 *, const f16 *, f16 *); +int main(void) { + const f16 accumulator[8] = {1,1,1,1,1,1,1,1}; + const f16 multiplicand[8] = {1,2,3,4,5,6,7,8}; + const f16 multiplier[8] = {2,3,4,5,6,7,8,9}; + const f16 same_add[8] = {3,7,13,21,31,43,57,73}; + const f16 same_sub[8] = {-1,-5,-11,-19,-29,-41,-55,-71}; + const f16 indexed_add[8] = {10,19,28,37,46,55,64,73}; + const f16 indexed_sub[8] = {-7,-15,-23,-31,-39,-47,-55,-63}; + f16 got[40] = {0}; + rawfmla(accumulator, multiplicand, multiplier, got); + for (int lane = 0; lane < 8; lane++) { + if (got[lane] != same_add[lane]) return 1 + lane; + if (got[8 + lane] != same_sub[lane]) return 10 + lane; + if (got[16 + lane] != indexed_add[lane]) return 20 + lane; + if (got[24 + lane] != indexed_sub[lane]) return 30 + lane; + } + if (got[32] != 6) return 40; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_fmla", triple, ir, mainC, nil) +} + +func TestTranslateARM64RawFMLACompleteArchitecturalFormats(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawfmlaforms(SB),$0-0\n") + for _, base := range []uint32{ + 0x0e400c00, 0x4e400c00, 0x0e20cc00, 0x4e20cc00, 0x4e60cc00, // FMLA H4/H8/S2/S4/D2. + 0x0ec00c00, 0x4ec00c00, 0x0ea0cc00, 0x4ea0cc00, 0x4ee0cc00, // FMLS H4/H8/S2/S4/D2. + } { + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|29<<16|30<<5|28) + } + type indexedFormat struct { + scalar bool + bits int + vectorBits int + lanes int + maxRm int + } + formats := []indexedFormat{ + {scalar: true, bits: 16, vectorBits: 16, lanes: 8, maxRm: 15}, + {scalar: true, bits: 32, vectorBits: 32, lanes: 4, maxRm: 31}, + {scalar: true, bits: 64, vectorBits: 64, lanes: 2, maxRm: 31}, + {bits: 16, vectorBits: 64, lanes: 8, maxRm: 15}, + {bits: 16, vectorBits: 128, lanes: 8, maxRm: 15}, + {bits: 32, vectorBits: 64, lanes: 4, maxRm: 31}, + {bits: 32, vectorBits: 128, lanes: 4, maxRm: 31}, + {bits: 64, vectorBits: 128, lanes: 2, maxRm: 31}, + } + for _, subtract := range []bool{false, true} { + for _, form := range formats { + for lane := 0; lane < form.lanes; lane++ { + for _, rm := range []int{0, form.maxRm} { + word := arm64EncodeRawFMLAByElement(subtract, form.scalar, form.bits, form.vectorBits, lane, rm, 30, 29) + decoded, ok := decodeARM64RawFMLA(word) + if !ok || !decoded.indexed || decoded.subtract != subtract || decoded.scalar != form.scalar || + decoded.arrangement != (arm64VectorArrangement{elementBits: form.bits, lanes: form.vectorBits / form.bits}) || + decoded.lane != lane || decoded.elementReg != rm || decoded.sourceReg != 30 || decoded.destination != 29 { + t.Fatalf("decode FMLA/FMLS indexed word %#08x = %+v, ok=%v", word, decoded, ok) + } + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfmlaforms": {Name: "rawfmlaforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-fmla.ll", "arm64-raw-fmla.o", ir) + }) + } +} diff --git a/arm64_lower_word_fmov_test.go b/arm64_lower_word_fmov_test.go new file mode 100644 index 00000000..3ce9d4a5 --- /dev/null +++ b/arm64_lower_word_fmov_test.go @@ -0,0 +1,29 @@ +package plan9asm + +import "testing" + +const arm64RawVectorFMOVImmediate = `TEXT vfmovraw(SB),$0-0 + WORD $0x4f00f785 // FMOV V5.S4, #7.00 + RET +` + +func TestTranslateARM64RawVectorFMOVImmediate(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawVectorFMOVImmediate, true) + file, err := Parse(ArchARM64, arm64RawVectorFMOVImmediate) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{Goarch: "arm64", TargetTriple: triple, Sigs: map[string]FuncSig{"vfmovraw": {Name: "vfmovraw", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vfmov.ll", "arm64-vfmov.o", ir) + }) + } +} diff --git a/arm64_lower_word_fsqrt.go b/arm64_lower_word_fsqrt.go new file mode 100644 index 00000000..44ba3f75 --- /dev/null +++ b/arm64_lower_word_fsqrt.go @@ -0,0 +1,70 @@ +package plan9asm + +import "fmt" + +type arm64RawFSQRT struct { + arrangement arm64VectorArrangement + source int + destination int +} + +func decodeARM64RawFSQRT(word uint32) (arm64RawFSQRT, bool) { + const registers = uint32(31 | 31<<5) + if key := word &^ registers; key == 0x2ef9f800 || key == 0x6ef9f800 { + lanes := 4 + if word&(1<<30) != 0 { + lanes = 8 + } + return arm64RawFSQRT{ + arrangement: arm64VectorArrangement{elementBits: 16, lanes: lanes}, + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true + } + if word&0xbfbffc00 != 0x2ea1f800 { // Ignore Q, size, Rn, and Rd. + return arm64RawFSQRT{}, false + } + elementBits := 32 + if word&(1<<22) != 0 { + elementBits = 64 + } + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + if elementBits == 64 && vectorBits == 64 { + return arm64RawFSQRT{}, false + } + return arm64RawFSQRT{ + arrangement: arm64VectorArrangement{elementBits: elementBits, lanes: vectorBits / elementBits}, + source: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawFSQRT(form arm64RawFSQRT) error { + if form.arrangement.elementBits == 16 { + source, err := c.loadARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.source)), form.arrangement) + if err != nil { + return err + } + result := c.newTmp() + vectorType := fmt.Sprintf("<%d x half>", form.arrangement.lanes) + fmt.Fprintf(c.b, " %%%s = call %s @llvm.sqrt.v%df16(%s %s)\n", result, vectorType, form.arrangement.lanes, vectorType, source) + return c.storeARM64VectorFloat(Reg(fmt.Sprintf("V%d", form.destination)), form.arrangement, "%"+result) + } + arrangement := arm64VectorArrangementName(form.arrangement) + ins := Instr{ + Op: "VFSQRT", + Raw: "decoded ARM64 WORD as VFSQRT", + Args: []Operand{ + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.source, arrangement))}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.destination, arrangement))}, + }, + } + ok, _, err := c.lowerARM64VectorFloatUnary("VFSQRT", ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw VFSQRT decoder reached no semantic lowerer") + } + return err +} diff --git a/arm64_lower_word_fsqrt_test.go b/arm64_lower_word_fsqrt_test.go new file mode 100644 index 00000000..780756a1 --- /dev/null +++ b/arm64_lower_word_fsqrt_test.go @@ -0,0 +1,112 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawFSQRTForms = ` +TEXT rawfsqrtforms(SB),$0-0 + WORD $0x2ef9f820 // FSQRT V1.H4, V0.H4 + WORD $0x6ef9f820 // FSQRT V1.H8, V0.H8 + WORD $0x2ea1f820 // FSQRT V1.S2, V0.S2 + WORD $0x6ea1f820 // FSQRT V1.S4, V0.S4 + WORD $0x6ee1f820 // FSQRT V1.D2, V0.D2 + RET +` + +func TestTranslateARM64RawFSQRTCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawFSQRTForms, true) + file, err := Parse(ArchARM64, arm64RawFSQRTForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfsqrtforms": {Name: "rawfsqrtforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + got := 0 + for _, line := range strings.Split(ll, "\n") { + if strings.Contains(line, " = call ") && strings.Contains(line, "@llvm.sqrt.") { + got++ + } + } + if got != 5 { + t.Fatalf("ARM64 raw FSQRT lowering for %s emitted %d sqrt operations, want 5:\n%s", triple, got, ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-fsqrt.ll", "arm64-raw-fsqrt.o", ll) + }) + } +} + +func TestARM64RawFSQRTRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawfsqrt(SB),$0-16 + MOVD in+0(FP), R0 + MOVD out+8(FP), R1 + VLD1 (R0), [V5.S4] + WORD $0x6ea1f8a5 // FSQRT V5.S4, V5.S4 + VST1 [V5.S4], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawfsqrt": { + Name: "rawfsqrt", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +extern void rawfsqrt(const float *, float *); +int main(void) { + const float in[4] = {4.0f, 9.0f, 16.0f, 25.0f}; + const float want[4] = {2.0f, 3.0f, 4.0f, 5.0f}; + float got[4] = {0}; + rawfsqrt(in, got); + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_fsqrt", triple, ll, mainC, nil) +} + +func TestARM64RawFSQRTDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{0x0ea1d800, 0x1e21c020, 0x2ee1f820} { // SCVTF, scalar FSQRT, reserved D1. + if _, ok := decodeARM64RawFSQRT(word); ok { + t.Fatalf("FSQRT decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} diff --git a/arm64_lower_word_ldnr.go b/arm64_lower_word_ldnr.go new file mode 100644 index 00000000..05a3243b --- /dev/null +++ b/arm64_lower_word_ldnr.go @@ -0,0 +1,78 @@ +package plan9asm + +import "fmt" + +type arm64RawLDnR struct { + count int + post bool + postRegister int + base int + firstRegister int + arrangement arm64VectorArrangement +} + +func decodeARM64RawLDnR(word uint32) (arm64RawLDnR, bool) { + // Advanced SIMD load single structure and replicate to all lanes. Q, the + // structure count bits, post-index bit/register, element size, base, and + // first destination register are all variable. + if word&0xbf40d000 != 0x0d40c000 { + return arm64RawLDnR{}, false + } + post := word&(1<<23) != 0 + postRegister := int(word>>16) & 31 + if !post && postRegister != 0 { + return arm64RawLDnR{}, false + } + count := 1 + (int(word>>21) & 1) + 2*(int(word>>13)&1) + elementBits := 8 << (int(word>>10) & 3) + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + return arm64RawLDnR{ + count: count, + post: post, + postRegister: postRegister, + base: int(word>>5) & 31, + firstRegister: int(word & 31), + arrangement: arm64VectorArrangement{elementBits: elementBits, lanes: vectorBits / elementBits}, + }, true +} + +func (c *arm64Ctx) lowerRawLDnR(form arm64RawLDnR) error { + op := Op(fmt.Sprintf("VLD%dR", form.count)) + rawOp := op + if form.post { + rawOp += ".P" + } + base := Reg(fmt.Sprintf("R%d", form.base)) + if form.base == 31 { + base = SP + } + memory := MemRef{Base: base} + if form.post { + if form.postRegister == 31 { + memory.Off = int64(form.count * form.arrangement.elementBits / 8) + } else { + memory.Index = Reg(fmt.Sprintf("R%d", form.postRegister)) + } + } + arrangement := arm64VectorArrangementName(form.arrangement) + registers := make([]Reg, form.count) + for i := range registers { + registers[i] = Reg(fmt.Sprintf("V%d.%s", (form.firstRegister+i)%32, arrangement)) + } + ins := Instr{ + Op: rawOp, + Raw: fmt.Sprintf("decoded ARM64 WORD as %s", rawOp), + Args: []Operand{ + {Kind: OpMem, Mem: memory}, + {Kind: OpRegList, RegList: registers}, + }, + } + ok, _, err := c.lowerARM64StructureLoadStore(op, form.post, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", rawOp) + } + return err +} diff --git a/arm64_lower_word_ldnr_test.go b/arm64_lower_word_ldnr_test.go new file mode 100644 index 00000000..ff31b6ee --- /dev/null +++ b/arm64_lower_word_ldnr_test.go @@ -0,0 +1,173 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func encodeARM64RawLDnRForTest(count, size int, q, post bool, rm, rn, rt int) uint32 { + word := uint32(0x0d40c000) + if q { + word |= 1 << 30 + } + if post { + word |= 1 << 23 + } + if count&1 == 0 { + word |= 1 << 21 + } + if count >= 3 { + word |= 1 << 13 + } + word |= uint32(size&3) << 10 + word |= uint32(rm&31) << 16 + word |= uint32(rn&31) << 5 + word |= uint32(rt & 31) + return word +} + +func TestTranslateARM64RawLDnRCompleteAdvancedSIMDFormats(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawldnrforms(SB),$0-0\n") + for count := 1; count <= 4; count++ { + for size := 0; size <= 3; size++ { + for _, q := range []bool{false, true} { + for _, addressing := range []struct { + post bool + rm int + }{{false, 0}, {true, 31}, {true, 2}} { + word := encodeARM64RawLDnRForTest(count, size, q, addressing.post, addressing.rm, 0, 28) + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawldnrforms": {Name: "rawldnrforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load i8", "load i16", "load i32", "load i64", "shufflevector", "add i64"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw LDnR lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-ldnr.ll", "arm64-raw-ldnr.o", ll) + }) + } +} + +func TestARM64RawLDnRDecoderCoversEveryFormat(t *testing.T) { + for count := 1; count <= 4; count++ { + for size := 0; size <= 3; size++ { + for _, q := range []bool{false, true} { + for _, addressing := range []struct { + post bool + rm int + }{{false, 0}, {true, 31}, {true, 17}} { + word := encodeARM64RawLDnRForTest(count, size, q, addressing.post, addressing.rm, 9, 30) + form, ok := decodeARM64RawLDnR(word) + if !ok || form.count != count || form.post != addressing.post || form.base != 9 || form.firstRegister != 30 || form.arrangement.elementBits != 8< +#include +extern void rawldnr(const uint32_t *, uint32_t *, uintptr_t *); +int main(void) { + const uint32_t input[4] = {11, 22, 33, 44}; + uint32_t output[16] = {0}; + uintptr_t advanced = 0; + rawldnr(input, output, &advanced); + for (int reg = 0; reg < 4; reg++) + for (int lane = 0; lane < 4; lane++) + if (output[reg*4+lane] != input[reg]) return 1 + reg*4 + lane; + return advanced == (uintptr_t)(input+4) ? 0 : 30; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_ldnr", triple, ll, mainC, nil) +} + +func TestARM64RawLDnRDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x4c407000, // LD1, not LD1R. + encodeARM64RawLDnRForTest(1, 0, true, false, 3, 0, 0), // Rm must be zero without post-indexing. + } { + t.Run(fmt.Sprintf("%08x", word), func(t *testing.T) { + if _, ok := decodeARM64RawLDnR(word); ok { + t.Fatalf("LDnR decoder claimed adjacent/reserved encoding %#08x", word) + } + }) + } +} diff --git a/arm64_lower_word_logical.go b/arm64_lower_word_logical.go new file mode 100644 index 00000000..5c473b56 --- /dev/null +++ b/arm64_lower_word_logical.go @@ -0,0 +1,64 @@ +package plan9asm + +import "fmt" + +type arm64RawLogical struct { + op Op + arrangement arm64VectorArrangement + first int + second int + destination int +} + +func decodeARM64RawLogical(word uint32) (arm64RawLogical, bool) { + var op Op + switch word & 0xbfe0fc00 { // Ignore Q, Rm, Rn, and Rd. + case 0x0e201c00: + op = "VAND" + case 0x0e601c00: + op = "VBIC" + case 0x0ea01c00: + op = "VORR" + case 0x0ee01c00: + op = "VORN" + case 0x2e201c00: + op = "VEOR" + case 0x2e601c00: + op = "VBSL" + case 0x2ea01c00: + op = "VBIT" + case 0x2ee01c00: + op = "VBIF" + default: + return arm64RawLogical{}, false + } + lanes := 8 + if word&(1<<30) != 0 { + lanes = 16 + } + return arm64RawLogical{ + op: op, + arrangement: arm64VectorArrangement{elementBits: 8, lanes: lanes}, + first: int(word>>5) & 31, + second: int(word>>16) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawLogical(form arm64RawLogical) error { + arrangement := arm64VectorArrangementName(form.arrangement) + ins := Instr{ + Op: form.op, + Raw: fmt.Sprintf("decoded ARM64 WORD as %s", form.op), + Args: []Operand{ + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.second, arrangement))}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.first, arrangement))}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.destination, arrangement))}, + }, + } + ok, _, err := c.lowerARM64VectorLogical(form.op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", form.op) + } + return err +} diff --git a/arm64_lower_word_logical_test.go b/arm64_lower_word_logical_test.go new file mode 100644 index 00000000..b3776601 --- /dev/null +++ b/arm64_lower_word_logical_test.go @@ -0,0 +1,133 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64RawLogicalCompleteAdvancedSIMDFormats(t *testing.T) { + bases := []uint32{0x0e201c00, 0x0e601c00, 0x0ea01c00, 0x0ee01c00, 0x2e201c00, 0x2e601c00, 0x2ea01c00, 0x2ee01c00} + var source strings.Builder + source.WriteString("TEXT rawlogicalforms(SB),$0-0\n") + for _, base := range bases { + for _, q := range []uint32{0, 1 << 30} { // B8 and B16. + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|q|1<<16|2<<5|3) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawlogicalforms": {Name: "rawlogicalforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, operation := range []string{"and <", "or <", "xor <"} { + if !strings.Contains(ll, operation) { + t.Fatalf("ARM64 raw logical lowering for %s omitted %q:\n%s", triple, operation, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-logical.ll", "arm64-raw-logical.o", ll) + }) + } +} + +func TestARM64RawLogicalRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawlogical(SB),$0-32 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD initial+16(FP), R2 + MOVD out+24(FP), R3 + VLD1 (R0), [V0.B16] + VLD1 (R1), [V1.B16] + VLD1.P 64(R2), [V2.B16, V3.B16, V4.B16, V5.B16] + VLD1 (R2), [V6.B16, V7.B16, V8.B16, V9.B16] + WORD $0x4e211c02 // AND V2.16B, V0.16B, V1.16B + WORD $0x4e611c03 // BIC V3.16B, V0.16B, V1.16B + WORD $0x4ea11c04 // ORR V4.16B, V0.16B, V1.16B + WORD $0x4ee11c05 // ORN V5.16B, V0.16B, V1.16B + WORD $0x6e211c06 // EOR V6.16B, V0.16B, V1.16B + WORD $0x6e611c07 // BSL V7.16B, V0.16B, V1.16B + WORD $0x6ea11c08 // BIT V8.16B, V0.16B, V1.16B + WORD $0x6ee11c09 // BIF V9.16B, V0.16B, V1.16B + VST1.P [V2.B16, V3.B16, V4.B16, V5.B16], 64(R3) + VST1 [V6.B16, V7.B16, V8.B16, V9.B16], (R3) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawlogical": { + Name: "rawlogical", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawlogical(const uint8_t *, const uint8_t *, const uint8_t *, uint8_t *); +int main(void) { + uint8_t a[16], b[16], initial[128], got[128] = {0}; + for (int i = 0; i < 16; i++) { a[i] = i * 17u; b[i] = 255u - i * 11u; } + for (int i = 0; i < 128; i++) initial[i] = 0xa5u ^ i; + rawlogical(a, b, initial, got); + for (int i = 0; i < 16; i++) { + const uint8_t old_bsl = initial[5*16+i], old_bit = initial[6*16+i], old_bif = initial[7*16+i]; + const uint8_t want[8] = { + a[i]&b[i], a[i]&~b[i], a[i]|b[i], a[i]|~b[i], a[i]^b[i], + (old_bsl&a[i])|(~old_bsl&b[i]), + (old_bit&~b[i])|(a[i]&b[i]), + (old_bif&b[i])|(a[i]&~b[i]), + }; + for (int op = 0; op < 8; op++) if (got[op*16+i] != want[op]) return op*16+i+1; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_logical", triple, ll, mainC, nil) +} + +func TestARM64RawLogicalDecoderRejectsAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{0x0e201800, 0x0e205c00, 0x5e201c00} { + if _, ok := decodeARM64RawLogical(word); ok { + t.Fatalf("logical decoder accepted adjacent/scalar encoding %#08x", word) + } + } +} diff --git a/arm64_lower_word_matrix_multiply.go b/arm64_lower_word_matrix_multiply.go new file mode 100644 index 00000000..47eac1e5 --- /dev/null +++ b/arm64_lower_word_matrix_multiply.go @@ -0,0 +1,92 @@ +package plan9asm + +import "fmt" + +type arm64RawMatrixMultiply struct { + leftSigned bool + rightSigned bool + destination int + left int + right int +} + +func decodeARM64RawMatrixMultiply(word uint32) (arm64RawMatrixMultiply, bool) { + form := arm64RawMatrixMultiply{} + switch word & 0xffe0fc00 { + case 0x4e80a400: // SMMLA. + form.leftSigned, form.rightSigned = true, true + case 0x6e80a400: // UMMLA. + case 0x4e80ac00: // USMMLA. + form.rightSigned = true + default: + return arm64RawMatrixMultiply{}, false + } + form.destination = int(word) & 31 + form.left = int(word>>5) & 31 + form.right = int(word>>16) & 31 + return form, true +} + +func (c *arm64Ctx) lowerRawMatrixMultiply(form arm64RawMatrixMultiply) error { + inputArrangement := arm64VectorArrangement{elementBits: 8, lanes: 16} + accumulatorArrangement := arm64VectorArrangement{elementBits: 32, lanes: 4} + leftReg := Reg(fmt.Sprintf("V%d.B16", form.left)) + rightReg := Reg(fmt.Sprintf("V%d.B16", form.right)) + accumulatorReg := Reg(fmt.Sprintf("V%d.S4", form.destination)) + left, err := c.loadARM64VectorInteger(leftReg, inputArrangement) + if err != nil { + return err + } + right, err := c.loadARM64VectorInteger(rightReg, inputArrangement) + if err != nil { + return err + } + result, err := c.loadARM64VectorInteger(accumulatorReg, accumulatorArrangement) + if err != nil { + return err + } + + widen := func(value string, signed bool) string { + op := "zext" + if signed { + op = "sext" + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s <16 x i8> %s to <16 x i32>\n", wide, op, value) + return "%" + wide + } + wideLeft := widen(left, form.leftSigned) + + for column := 0; column < 2; column++ { + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shufflevector <16 x i8> %s, <16 x i8> poison, <16 x i32> <", selected, right) + for lane := 0; lane < 16; lane++ { + if lane != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", 2*(lane%8)+column) + } + c.b.WriteString(">\n") + wideRight := widen("%"+selected, form.rightSigned) + products := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul <16 x i32> %s, %s\n", products, wideLeft, wideRight) + + for row := 0; row < 2; row++ { + destinationLane := row*2 + column + accumulated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <4 x i32> %s, i32 %d\n", accumulated, result, destinationLane) + value := "%" + accumulated + for k := 0; k < 8; k++ { + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <16 x i32> %%%s, i32 %d\n", product, products, row*8+k) + sum := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %%%s\n", sum, value, product) + value = "%" + sum + } + updated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <4 x i32> %s, i32 %s, i32 %d\n", updated, result, value, destinationLane) + result = "%" + updated + } + } + return c.storeARM64VectorInteger(accumulatorReg, accumulatorArrangement, result) +} diff --git a/arm64_lower_word_matrix_multiply_test.go b/arm64_lower_word_matrix_multiply_test.go new file mode 100644 index 00000000..2d450c32 --- /dev/null +++ b/arm64_lower_word_matrix_multiply_test.go @@ -0,0 +1,141 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawMatrixMultiplyForms = ` +TEXT rawmatrixmultiplyforms(SB),$0-0 + WORD $0x4e9fa7dd // SMMLA V29.4S, V30.16B, V31.16B + WORD $0x6e9fa7dd // UMMLA V29.4S, V30.16B, V31.16B + WORD $0x4e9fafdd // USMMLA V29.4S, V30.16B, V31.16B + RET +` + +func TestTranslateARM64RawMatrixMultiplyCompleteArchitecturalFamily(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawMatrixMultiplyForms, true) + file, err := Parse(ArchARM64, arm64RawMatrixMultiplyForms) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawmatrixmultiplyforms": {Name: "rawmatrixmultiplyforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sext <16 x i8>", "zext <16 x i8>", "mul <16 x i32>", "add i32"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw matrix-multiply family for %s omitted %q:\n%s", triple, want, ir) + } + } + compileLLVMToObject(t, llc, triple, "arm64-raw-matrix-multiply.ll", "arm64-raw-matrix-multiply.o", ir) + }) + } +} + +func TestARM64RawMatrixMultiplyDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x0e80a400, // Q=0 is unallocated for matrix multiply. + 0x4ea0a400, // Reserved bit 21. + 0x4e80a000, // Adjacent opcode field. + 0x4e80a800, // Adjacent opcode field. + 0x6e80ac00, // Unallocated unsigned/mixed-sign combination. + } { + if _, ok := decodeARM64RawMatrixMultiply(word); ok { + t.Fatalf("matrix-multiply decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} + +func TestARM64RawMatrixMultiplyRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawmatrixmultiply(SB),$0-32 + MOVD accumulator+0(FP), R0 + MOVD lhs+8(FP), R1 + MOVD rhs+16(FP), R2 + MOVD output+24(FP), R3 + VLD1 (R1), [V16.B16] + VLD1 (R2), [V18.B16] + VLD1 (R0), [V8.S4] + WORD $0x4e92a608 // SMMLA V8.4S, V16.16B, V18.16B + VST1 [V8.S4], (R3) + ADD $16, R3 + VLD1 (R0), [V8.S4] + WORD $0x6e92a608 // UMMLA V8.4S, V16.16B, V18.16B + VST1 [V8.S4], (R3) + ADD $16, R3 + VLD1 (R0), [V8.S4] + WORD $0x4e92ae08 // USMMLA V8.4S, V16.16B, V18.16B + VST1 [V8.S4], (R3) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawmatrixmultiply": { + Name: "rawmatrixmultiply", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawmatrixmultiply(const int32_t *, const uint8_t *, const uint8_t *, int32_t *); +static void reference(int32_t *out, const int32_t *acc, const uint8_t *lhs, const uint8_t *rhs, int lhs_signed, int rhs_signed) { + for (int row = 0; row < 2; row++) for (int col = 0; col < 2; col++) { + int32_t sum = acc[row * 2 + col]; + for (int k = 0; k < 8; k++) { + int32_t a = lhs_signed ? (int8_t)lhs[row * 8 + k] : lhs[row * 8 + k]; + int32_t b = rhs_signed ? (int8_t)rhs[k * 2 + col] : rhs[k * 2 + col]; + sum += a * b; + } + out[row * 2 + col] = sum; + } +} +int main(void) { + const int32_t accumulator[4] = {10, 20, 30, 40}; + const uint8_t lhs[16] = {255,2,253,4,251,6,249,8, 247,10,245,12,243,14,241,16}; + const uint8_t rhs[16] = {1,254,3,252,5,250,7,248,9,246,11,244,13,242,15,240}; + int32_t got[12] = {0}; + int32_t want[12] = {0}; + rawmatrixmultiply(accumulator, lhs, rhs, got); + reference(want + 0, accumulator, lhs, rhs, 1, 1); + reference(want + 4, accumulator, lhs, rhs, 0, 0); + reference(want + 8, accumulator, lhs, rhs, 0, 1); + for (int i = 0; i < 12; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_matrix_multiply", triple, ir, mainC, nil) +} diff --git a/arm64_lower_word_mla.go b/arm64_lower_word_mla.go new file mode 100644 index 00000000..b18b918f --- /dev/null +++ b/arm64_lower_word_mla.go @@ -0,0 +1,46 @@ +package plan9asm + +func decodeARM64RawMLA(word uint32) (arm64RawMUL, bool) { + form := arm64RawMUL{element: -1} + switch { + case word&0xbf20fc00 == 0x0e209400: // vector, three same + case word&0xbf00f400 == 0x2f000000: // vector, by element + form.byElement = true + default: + return arm64RawMUL{}, false + } + size := int(word>>22) & 3 + if form.byElement { + if size != 1 && size != 2 { + return arm64RawMUL{}, false + } + } else if size > 2 { + return arm64RawMUL{}, false + } + bits := 8 << size + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + form.arrangement = arm64VectorArrangement{elementBits: bits, lanes: vectorBits / bits} + form.destination = int(word & 31) + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + if form.byElement { + form.second &= 15 + l := int(word>>21) & 1 + m := int(word>>20) & 1 + h := int(word>>11) & 1 + if bits == 16 { + form.element = m<<2 | l<<1 | h + } else { + form.second |= m << 4 + form.element = l<<1 | h + } + } + return form, true +} + +func (c *arm64Ctx) lowerRawMLA(form arm64RawMUL) error { + return c.lowerRawMultiplyAccumulate(form, "add") +} diff --git a/arm64_lower_word_mla_test.go b/arm64_lower_word_mla_test.go new file mode 100644 index 00000000..9bc8e3fe --- /dev/null +++ b/arm64_lower_word_mla_test.go @@ -0,0 +1,127 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawMLAForms = ` +TEXT rawmlaforms(SB),$0-0 + WORD $0x0e229420 // MLA V0.8B, V1.8B, V2.8B + WORD $0x4e259483 // MLA V3.16B, V4.16B, V5.16B + WORD $0x0e6894e6 // MLA V6.4H, V7.4H, V8.4H + WORD $0x4e6b9549 // MLA V9.8H, V10.8H, V11.8H + WORD $0x0eae95ac // MLA V12.2S, V13.2S, V14.2S + WORD $0x4eb1960f // MLA V15.4S, V16.4S, V17.4S + WORD $0x2f740a72 // MLA V18.4H, V19.4H, V4.H[7] + WORD $0x6f750ab4 // MLA V20.8H, V21.8H, V5.H[7] + WORD $0x2fb80af6 // MLA V22.2S, V23.2S, V24.S[3] + WORD $0x6fbb0b59 // MLA V25.4S, V26.4S, V27.S[3] + RET +` + +func TestTranslateARM64RawMLACompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawMLAForms, true) + file, err := Parse(ArchARM64, arm64RawMLAForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawmlaforms": {Name: "rawmlaforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "mul <8 x i8>", "mul <16 x i8>", + "mul <4 x i16>", "mul <8 x i16>", + "mul <2 x i32>", "mul <4 x i32>", + "add <8 x i8>", "add <4 x i32>", + "extractelement <8 x i16>", "extractelement <4 x i32>", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw MLA lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-mla.ll", "arm64-raw-mla.o", ll) + }) + } +} + +func TestARM64RawMLARuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawmla(SB),$0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD inout+16(FP), R2 + VLD1 (R0), [V8.H8] + VLD1 (R1), [V7.H8] + VLD1 (R2), [V2.H8] + WORD $0x4e679502 // MLA V2.8H, V8.8H, V7.8H + VST1 [V2.H8], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawmla": { + Name: "rawmla", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawmla(const uint16_t *, const uint16_t *, uint16_t *); +int main(void) { + const uint16_t a[8] = {0,1,65535,32768,2,3,4,5}; + const uint16_t b[8] = {7,65535,3,2,9,10,11,12}; + const uint16_t initial[8] = {9,9,9,9,65000,65000,65000,65000}; + uint16_t got[8]; + for (int i = 0; i < 8; i++) got[i] = initial[i]; + rawmla(a, b, got); + for (int i = 0; i < 8; i++) { + uint16_t want = (uint16_t)(initial[i] + (uint16_t)(a[i] * b[i])); + if (got[i] != want) return i + 1; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_mla", triple, ll, mainC, nil) +} + +func TestARM64RawMLADecoderRejectsAdjacentMLSEncoding(t *testing.T) { + if _, ok := decodeARM64RawMLA(0x2e229420); ok { + t.Fatal("MLA decoder accepted adjacent MLS encoding") + } +} diff --git a/arm64_lower_word_mls.go b/arm64_lower_word_mls.go new file mode 100644 index 00000000..5c975362 --- /dev/null +++ b/arm64_lower_word_mls.go @@ -0,0 +1,73 @@ +package plan9asm + +import "fmt" + +func decodeARM64RawMLS(word uint32) (arm64RawMUL, bool) { + form := arm64RawMUL{element: -1} + switch { + case word&0xbf20fc00 == 0x2e209400: // vector, three same + case word&0xbf00f400 == 0x2f004000: // vector, by element + form.byElement = true + default: + return arm64RawMUL{}, false + } + size := int(word>>22) & 3 + if form.byElement { + if size != 1 && size != 2 { + return arm64RawMUL{}, false + } + } else if size > 2 { + return arm64RawMUL{}, false + } + bits := 8 << size + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + form.arrangement = arm64VectorArrangement{elementBits: bits, lanes: vectorBits / bits} + form.destination = int(word & 31) + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + if form.byElement { + form.second &= 15 + l := int(word>>21) & 1 + m := int(word>>20) & 1 + h := int(word>>11) & 1 + if bits == 16 { + form.element = m<<2 | l<<1 | h + } else { + form.second |= m << 4 + form.element = l<<1 | h + } + } + return form, true +} + +func (c *arm64Ctx) lowerRawMLS(form arm64RawMUL) error { + return c.lowerRawMultiplyAccumulate(form, "sub") +} + +func (c *arm64Ctx) lowerRawMultiplyAccumulate(form arm64RawMUL, operation string) error { + first, err := c.loadRawARM64VectorOperand(form.first, form.arrangement, 0, false) + if err != nil { + return err + } + secondLane := 0 + if form.byElement { + secondLane = form.element + } + second, err := c.loadRawARM64VectorOperand(form.second, form.arrangement, secondLane, form.byElement) + if err != nil { + return err + } + accumulator, err := c.loadRawARM64VectorOperand(form.destination, form.arrangement, 0, false) + if err != nil { + return err + } + vectorType := fmt.Sprintf("<%d x i%d>", form.arrangement.lanes, form.arrangement.elementBits) + product := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul %s %s, %s\n", product, vectorType, first, second) + fmt.Fprintf(c.b, " %%%s = %s %s %s, %%%s\n", result, operation, vectorType, accumulator, product) + return c.storeRawARM64VectorResult(form.destination, form.arrangement, "%"+result, false) +} diff --git a/arm64_lower_word_mls_test.go b/arm64_lower_word_mls_test.go new file mode 100644 index 00000000..ebfab3b6 --- /dev/null +++ b/arm64_lower_word_mls_test.go @@ -0,0 +1,123 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawMLSForms = ` +TEXT rawmlsforms(SB),$0-0 + WORD $0x2e229420 // MLS V0.8B, V1.8B, V2.8B + WORD $0x6e259483 // MLS V3.16B, V4.16B, V5.16B + WORD $0x2e6894e6 // MLS V6.4H, V7.4H, V8.4H + WORD $0x6e6b9549 // MLS V9.8H, V10.8H, V11.8H + WORD $0x2eae95ac // MLS V12.2S, V13.2S, V14.2S + WORD $0x6eb1960f // MLS V15.4S, V16.4S, V17.4S + WORD $0x2f744a72 // MLS V18.4H, V19.4H, V4.H[7] + WORD $0x6f754ab4 // MLS V20.8H, V21.8H, V5.H[7] + WORD $0x2fb84af6 // MLS V22.2S, V23.2S, V24.S[3] + WORD $0x6fbb4b59 // MLS V25.4S, V26.4S, V27.S[3] + RET +` + +func TestTranslateARM64RawMLSCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawMLSForms, true) + file, err := Parse(ArchARM64, arm64RawMLSForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawmlsforms": {Name: "rawmlsforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "mul <8 x i8>", "mul <16 x i8>", + "mul <4 x i16>", "mul <8 x i16>", + "mul <2 x i32>", "mul <4 x i32>", + "sub <8 x i8>", "sub <4 x i32>", + "extractelement <8 x i16>", "extractelement <4 x i32>", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw MLS lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-mls.ll", "arm64-raw-mls.o", ll) + }) + } +} + +func TestARM64RawMLSRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawmls(SB),$0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD inout+16(FP), R2 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V1.S4] + VLD1 (R2), [V2.S4] + WORD $0x6ea19402 // MLS V2.4S, V0.4S, V1.4S + VST1 [V2.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawmls": { + Name: "rawmls", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawmls(const uint32_t *, const uint32_t *, uint32_t *); +int main(void) { + const uint32_t a[4] = {0, 1, 0xffffffffu, 0x80000000u}; + const uint32_t b[4] = {7, 0xffffffffu, 3, 2}; + uint32_t got[4] = {9, 9, 9, 9}; + const uint32_t want[4] = {9, 10, 12, 9}; + rawmls(a, b, got); + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_mls", triple, ll, mainC, nil) +} + +func TestARM64RawMLSDecoderRejectsAdjacentMLAEncoding(t *testing.T) { + if _, ok := decodeARM64RawMLS(0x0e229420); ok { + t.Fatal("MLS decoder accepted adjacent MLA encoding") + } +} diff --git a/arm64_lower_word_modified_immediate.go b/arm64_lower_word_modified_immediate.go new file mode 100644 index 00000000..a2201320 --- /dev/null +++ b/arm64_lower_word_modified_immediate.go @@ -0,0 +1,83 @@ +package plan9asm + +import "fmt" + +type arm64RawModifiedImmediate struct { + op Op + arrangement arm64VectorArrangement + immediate byte + value uint64 + destination int +} + +func decodeARM64RawModifiedImmediate(word uint32) (arm64RawModifiedImmediate, bool) { + // Advanced SIMD modified immediate. Keep the fixed class and o2 bit, while + // allowing Q, op, cmode, imm8, and Rd to be interpreted below. + if word&0x9ff80c00 != 0x0f000400 { + return arm64RawModifiedImmediate{}, false + } + opBit := word&(1<<29) != 0 + cmode := int(word>>12) & 15 + immediate := byte(((word >> 16) & 7 << 5) | ((word >> 5) & 31)) + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + + form := arm64RawModifiedImmediate{op: "VMOVI", immediate: immediate, destination: int(word) & 31} + var value uint64 + switch cmode { + case 0, 2, 4, 6: + form.arrangement = arm64VectorArrangement{elementBits: 32, lanes: vectorBits / 32} + value = uint64(uint32(immediate) << uint(cmode/2*8)) + case 8, 10: + form.arrangement = arm64VectorArrangement{elementBits: 16, lanes: vectorBits / 16} + value = uint64(uint16(immediate) << uint((cmode-8)/2*8)) + case 12: + form.arrangement = arm64VectorArrangement{elementBits: 32, lanes: vectorBits / 32} + value = uint64(uint32(immediate)<<8 | 0xff) + case 13: + form.arrangement = arm64VectorArrangement{elementBits: 32, lanes: vectorBits / 32} + value = uint64(uint32(immediate)<<16 | 0xffff) + case 14: + if !opBit { + form.arrangement = arm64VectorArrangement{elementBits: 8, lanes: vectorBits / 8} + value = uint64(immediate) + break + } + form.arrangement = arm64VectorArrangement{elementBits: 64, lanes: vectorBits / 64} + for bit := 0; bit < 8; bit++ { + if immediate&(1<>5)<<16 | cmode<<12 | uint32(immediate&31)<<5 | uint32(destination) +} + +func TestTranslateARM64RawMOVIMVNICompleteAdvancedSIMDFormats(t *testing.T) { + forms := arm64RawMOVIMVNIForms() + if len(forms) != 36 { + t.Fatalf("MOVI/MVNI format inventory has %d forms, want 36", len(forms)) + } + var source strings.Builder + source.WriteString("TEXT rawmodifiedimmediateforms(SB),$0-0\n") + for i, form := range forms { + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawModifiedImmediate(form.opBit, form.cmode, form.q, 0x92, i%32)) + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawmodifiedimmediateforms": {Name: "rawmodifiedimmediateforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-modified-immediate.ll", "arm64-raw-modified-immediate.o", ll) + }) + } +} + +func TestARM64RawMOVIMVNIDecoderCoversEveryImmediate(t *testing.T) { + for _, form := range arm64RawMOVIMVNIForms() { + for immediate := 0; immediate <= 255; immediate++ { + word := encodeARM64RawModifiedImmediate(form.opBit, form.cmode, form.q, byte(immediate), 17) + got, ok := decodeARM64RawModifiedImmediate(word) + if !ok { + t.Fatalf("decoder rejected %s cmode=%d Q=%d immediate=%#02x word=%#08x", form.op, form.cmode, form.q, immediate, word) + } + if got.op != form.op || got.arrangement != form.arrangement || got.destination != 17 { + t.Fatalf("decoded word %#08x as %+v, want op=%s arrangement=%+v destination=17", word, got, form.op, form.arrangement) + } + } + } +} + +func TestARM64RawMOVIMVNIRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + tests := []struct{ opBit, cmode, q uint32 }{ + {0, 14, 1}, // MOVI B16. + {0, 10, 1}, // MOVI H8, LSL #8. + {0, 6, 1}, // MOVI S4, LSL #24. + {0, 12, 1}, // MOVI S4, MSL #8. + {0, 13, 1}, // MOVI S4, MSL #16. + {1, 10, 1}, // MVNI H8, LSL #8. + {1, 13, 1}, // MVNI S4, MSL #16. + {1, 14, 1}, // MOVI D2 byte mask. + } + var source strings.Builder + source.WriteString("TEXT rawmodifiedimmediate(SB),$0-8\n\tMOVD out+0(FP), R0\n") + for destination, test := range tests { + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawModifiedImmediate(test.opBit, test.cmode, test.q, 0x12, destination)) + } + source.WriteString("\tVST1.P [V0.B16, V1.B16, V2.B16, V3.B16], 64(R0)\n\tVST1 [V4.B16, V5.B16, V6.B16, V7.B16], (R0)\n\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawmodifiedimmediate": { + Name: "rawmodifiedimmediate", Args: []LLVMType{Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawmodifiedimmediate(uint8_t *); +int main(void) { + uint8_t got[128] = {0}; + rawmodifiedimmediate(got); + for (int i = 0; i < 16; i++) { + const uint8_t want[8] = { + 0x12, + (i&1) ? 0x12 : 0x00, + (i&3) == 3 ? 0x12 : 0x00, + (i&3) == 0 ? 0xff : (i&3) == 1 ? 0x12 : 0x00, + (i&3) < 2 ? 0xff : (i&3) == 2 ? 0x12 : 0x00, + (i&1) ? 0xed : 0xff, + (i&3) < 2 ? 0x00 : (i&3) == 2 ? 0xed : 0xff, + (0x12u & (1u << (i&7))) ? 0xff : 0x00, + }; + for (int op = 0; op < 8; op++) if (got[op*16+i] != want[op]) return op*16+i+1; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_modified_immediate", triple, ll, mainC, nil) +} + +func TestARM64RawMOVIMVNIDecoderRejectsNeighboringModifiedImmediateClasses(t *testing.T) { + for _, word := range []uint32{ + encodeARM64RawModifiedImmediate(0, 1, 0, 1, 0), // ORR immediate. + encodeARM64RawModifiedImmediate(1, 11, 1, 1, 0), // BIC immediate. + encodeARM64RawModifiedImmediate(0, 15, 1, 1, 0), // FMOV immediate. + } { + if _, ok := decodeARM64RawModifiedImmediate(word); ok { + t.Fatalf("MOVI/MVNI decoder accepted neighboring encoding %#08x", word) + } + } +} diff --git a/arm64_lower_word_move_wide.go b/arm64_lower_word_move_wide.go new file mode 100644 index 00000000..28cfaaaa --- /dev/null +++ b/arm64_lower_word_move_wide.go @@ -0,0 +1,75 @@ +package plan9asm + +import "fmt" + +type arm64RawMoveWide struct { + op Op + width int + shift int + immediate uint16 + destination int +} + +func decodeARM64RawMoveWide(word uint32) (arm64RawMoveWide, bool) { + if word&0x1f800000 != 0x12800000 { + return arm64RawMoveWide{}, false + } + var op Op + switch (word >> 29) & 3 { + case 0: + op = "MOVN" + case 2: + op = "MOVZ" + case 3: + op = "MOVK" + default: + return arm64RawMoveWide{}, false + } + width := 32 + if word&(1<<31) != 0 { + width = 64 + } + halfword := int(word>>21) & 3 + if width == 32 && halfword > 1 { + return arm64RawMoveWide{}, false + } + return arm64RawMoveWide{ + op: op, + width: width, + shift: halfword * 16, + immediate: uint16(word >> 5), + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawMoveWide(form arm64RawMoveWide) error { + // Rd=31 denotes WZR/XZR for this encoding class. + if form.destination == 31 { + return nil + } + widthMask := uint64(0xffffffff) + if form.width == 64 { + widthMask = ^uint64(0) + } + field := uint64(form.immediate) << form.shift + reg := Reg(fmt.Sprintf("R%d", form.destination)) + switch form.op { + case "MOVZ": + return c.storeReg(reg, fmt.Sprintf("%d", field)) + case "MOVN": + return c.storeReg(reg, fmt.Sprintf("%d", (^field)&widthMask)) + case "MOVK": + old, err := c.loadReg(reg) + if err != nil { + return err + } + preserveMask := widthMask & ^(uint64(0xffff) << form.shift) + preserved := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, %d\n", preserved, old, preserveMask) + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %d\n", result, preserved, field) + return c.storeReg(reg, "%"+result) + default: + return fmt.Errorf("unknown ARM64 raw move-wide operation %s", form.op) + } +} diff --git a/arm64_lower_word_move_wide_test.go b/arm64_lower_word_move_wide_test.go new file mode 100644 index 00000000..efbaa041 --- /dev/null +++ b/arm64_lower_word_move_wide_test.go @@ -0,0 +1,152 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +type arm64RawMoveWideTestForm struct { + op Op + opc uint32 + width int + shift int +} + +func arm64RawMoveWideForms() []arm64RawMoveWideTestForm { + var forms []arm64RawMoveWideTestForm + for _, operation := range []struct { + op Op + opc uint32 + }{{"MOVN", 0}, {"MOVZ", 2}, {"MOVK", 3}} { + for _, width := range []int{32, 64} { + maxShift := width - 16 + for shift := 0; shift <= maxShift; shift += 16 { + forms = append(forms, arm64RawMoveWideTestForm{op: operation.op, opc: operation.opc, width: width, shift: shift}) + } + } + } + return forms +} + +func encodeARM64RawMoveWide(opc uint32, width, shift int, immediate uint16, destination int) uint32 { + word := uint32(0x12800000) | opc<<29 | uint32(shift/16)<<21 | uint32(immediate)<<5 | uint32(destination) + if width == 64 { + word |= 1 << 31 + } + return word +} + +func TestTranslateARM64RawMoveWideCompleteFormats(t *testing.T) { + forms := arm64RawMoveWideForms() + if len(forms) != 18 { + t.Fatalf("move-wide format inventory has %d forms, want 18", len(forms)) + } + var source strings.Builder + source.WriteString("TEXT rawmovewideforms(SB),$0-0\n") + for i, form := range forms { + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawMoveWide(form.opc, form.width, form.shift, 0xa55a, i%31)) + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawmovewideforms": {Name: "rawmovewideforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-move-wide.ll", "arm64-raw-move-wide.o", ll) + }) + } +} + +func TestARM64RawMoveWideDecoderCoversEveryImmediate(t *testing.T) { + for _, form := range arm64RawMoveWideForms() { + for immediate := 0; immediate <= 0xffff; immediate++ { + word := encodeARM64RawMoveWide(form.opc, form.width, form.shift, uint16(immediate), 17) + got, ok := decodeARM64RawMoveWide(word) + if !ok { + t.Fatalf("decoder rejected %s width=%d shift=%d immediate=%#04x", form.op, form.width, form.shift, immediate) + } + if got.op != form.op || got.width != form.width || got.shift != form.shift || got.immediate != uint16(immediate) || got.destination != 17 { + t.Fatalf("decoded word %#08x as %+v, want %+v immediate=%#04x destination=17", word, got, form, immediate) + } + } + } +} + +func TestARM64RawMoveWideRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + var source strings.Builder + source.WriteString("TEXT rawmovewide(SB),$0-16\n\tMOVD out+0(FP), R0\n\tMOVD initial+8(FP), R1\n") + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawMoveWide(2, 64, 32, 0x1234, 2)) // MOVZ X2, #0x1234, LSL #32. + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawMoveWide(0, 32, 16, 0x00ff, 3)) // MOVN W3, #0x00ff, LSL #16. + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawMoveWide(3, 64, 16, 0xabcd, 1)) // MOVK X1, #0xabcd, LSL #16. + source.WriteString("\tMOVD R2, 0(R0)\n\tMOVD R3, 8(R0)\n\tMOVD R1, 16(R0)\n\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawmovewide": { + Name: "rawmovewide", Args: []LLVMType{Ptr, I64}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: I64, Index: 1, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawmovewide(uint64_t *, uint64_t); +int main(void) { + uint64_t got[3] = {0}; + rawmovewide(got, UINT64_C(0x0123456789abcdef)); + if (got[0] != UINT64_C(0x0000123400000000)) return 1; + if (got[1] != UINT64_C(0x00000000ff00ffff)) return 2; + if (got[2] != UINT64_C(0x01234567abcdcdef)) return 3; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_move_wide", triple, ll, mainC, nil) +} + +func TestARM64RawMoveWideDecoderRejectsReservedAndAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{ + encodeARM64RawMoveWide(1, 64, 0, 1, 0), // reserved opc. + encodeARM64RawMoveWide(2, 32, 32, 1, 0), // reserved W shift. + 0x12000000, // AND immediate. + } { + if _, ok := decodeARM64RawMoveWide(word); ok { + t.Fatalf("move-wide decoder accepted reserved/adjacent encoding %#08x", word) + } + } +} diff --git a/arm64_lower_word_mul.go b/arm64_lower_word_mul.go new file mode 100644 index 00000000..153f9d7a --- /dev/null +++ b/arm64_lower_word_mul.go @@ -0,0 +1,73 @@ +package plan9asm + +import "fmt" + +type arm64RawMUL struct { + byElement bool + arrangement arm64VectorArrangement + destination int + first int + second int + element int +} + +func decodeARM64RawMUL(word uint32) (arm64RawMUL, bool) { + form := arm64RawMUL{element: -1} + switch { + case word&0xbf20fc00 == 0x0e209c00: // vector, three same + case word&0xbf00f400 == 0x0f008000: // vector, by element + form.byElement = true + default: + return arm64RawMUL{}, false + } + + size := int(word>>22) & 3 + if form.byElement { + if size != 1 && size != 2 { + return arm64RawMUL{}, false + } + } else if size > 2 { + return arm64RawMUL{}, false + } + bits := 8 << size + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + form.arrangement = arm64VectorArrangement{elementBits: bits, lanes: vectorBits / bits} + form.destination = int(word & 31) + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + if form.byElement { + form.second &= 15 + l := int(word>>21) & 1 + m := int(word>>20) & 1 + h := int(word>>11) & 1 + if bits == 16 { + form.element = m<<2 | l<<1 | h + } else { + form.second |= m << 4 + form.element = l<<1 | h + } + } + return form, true +} + +func (c *arm64Ctx) lowerRawMUL(form arm64RawMUL) error { + first, err := c.loadRawARM64VectorOperand(form.first, form.arrangement, 0, false) + if err != nil { + return err + } + secondLane := 0 + if form.byElement { + secondLane = form.element + } + second, err := c.loadRawARM64VectorOperand(form.second, form.arrangement, secondLane, form.byElement) + if err != nil { + return err + } + vectorType := fmt.Sprintf("<%d x i%d>", form.arrangement.lanes, form.arrangement.elementBits) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul %s %s, %s\n", product, vectorType, first, second) + return c.storeRawARM64VectorResult(form.destination, form.arrangement, "%"+product, false) +} diff --git a/arm64_lower_word_mul_test.go b/arm64_lower_word_mul_test.go new file mode 100644 index 00000000..5c21d6cd --- /dev/null +++ b/arm64_lower_word_mul_test.go @@ -0,0 +1,132 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +// Integer MUL has six same-vector forms and four by-element forms in the +// Advanced SIMD ISA. Go's VMUL mnemonic covers the former; raw WORD users can +// encode both groups, so the raw decoder must cover the complete family. +const arm64RawMULForms = ` +TEXT rawmulforms(SB),$0-0 + WORD $0x0e229c20 // MUL V0.8B, V1.8B, V2.8B + WORD $0x4e259c83 // MUL V3.16B, V4.16B, V5.16B + WORD $0x0e689ce6 // MUL V6.4H, V7.4H, V8.4H + WORD $0x4e6b9d49 // MUL V9.8H, V10.8H, V11.8H + WORD $0x0eae9dac // MUL V12.2S, V13.2S, V14.2S + WORD $0x4eb19e0f // MUL V15.4S, V16.4S, V17.4S + WORD $0x0f748a72 // MUL V18.4H, V19.4H, V4.H[7] + WORD $0x4f758ab4 // MUL V20.8H, V21.8H, V5.H[7] + WORD $0x0fb88af6 // MUL V22.2S, V23.2S, V24.S[3] + WORD $0x4fbb8b59 // MUL V25.4S, V26.4S, V27.S[3] + RET +` + +func TestTranslateARM64RawMULCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawMULForms, true) + file, err := Parse(ArchARM64, arm64RawMULForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawmulforms": {Name: "rawmulforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "mul <8 x i8>", "mul <16 x i8>", + "mul <4 x i16>", "mul <8 x i16>", + "mul <2 x i32>", "mul <4 x i32>", + "extractelement <8 x i16>", "extractelement <4 x i32>", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw MUL lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-mul.ll", "arm64-raw-mul.o", ll) + }) + } +} + +func TestARM64RawMULRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawmul(SB),$0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V1.S4] + WORD $0x4ea19c02 // MUL V2.4S, V0.4S, V1.4S + VST1 [V2.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawmul": { + Name: "rawmul", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawmul(const uint32_t *, const uint32_t *, uint32_t *); +int main(void) { + const uint32_t a[4] = {0, 1, 0xffffffffu, 0x80000000u}; + const uint32_t b[4] = {7, 0xffffffffu, 3, 2}; + uint32_t got[4] = {0}; + const uint32_t want[4] = {0, 0xffffffffu, 0xfffffffdu, 0}; + rawmul(a, b, got); + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_mul", triple, ll, mainC, nil) +} + +func TestARM64RawMULDecoderRejectsAdjacentEncoding(t *testing.T) { + // PMUL shares much of the three-same encoding space but has polynomial, + // rather than integer, multiplication semantics. + if _, ok := decodeARM64RawMUL(0x2e229c20); ok { + t.Fatal("MUL decoder claimed adjacent PMUL encoding") + } +} diff --git a/arm64_lower_word_pairwise_add_long_test.go b/arm64_lower_word_pairwise_add_long_test.go new file mode 100644 index 00000000..3adcd79c --- /dev/null +++ b/arm64_lower_word_pairwise_add_long_test.go @@ -0,0 +1,137 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestTranslateARM64RawPairwiseAddLongCompleteArchitecturalFormats(t *testing.T) { + bases := []uint32{ + 0x0e202800, // SADDLP. + 0x2e202800, // UADDLP. + 0x0e206800, // SADALP. + 0x2e206800, // UADALP. + } + var source strings.Builder + source.WriteString("TEXT rawpairwiseaddlongforms(SB),$0-0\n") + for _, base := range bases { + for size := uint32(0); size < 3; size++ { + for q := uint32(0); q < 2; q++ { + fmt.Fprintf(&source, "\tWORD $%#08x\n", base|size<<22|q<<30|31<<5|30) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawpairwiseaddlongforms": {Name: "rawpairwiseaddlongforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-pairwise-add-long.ll", "arm64-raw-pairwise-add-long.o", ir) + }) + } +} + +func TestARM64RawPairwiseAddLongDecoderRejectsAdjacentAndReservedEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x0ee02800, // SADDLP reserved 64-bit source elements. + 0x2ee02800, // UADDLP reserved 64-bit source elements. + 0x0ee06800, // SADALP reserved 64-bit source elements. + 0x2ee06800, // UADALP reserved 64-bit source elements. + 0x0e202c00, // adjacent opcode bits. + 0x0e203800, // SADDV. + } { + if _, ok := decodeARM64RawPairwiseAddLong(word); ok { + t.Fatalf("pairwise-add-long decoder accepted adjacent/reserved encoding %#08x", word) + } + } +} + +func TestARM64RawPairwiseAddLongRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawpairwiseaddlong(SB),$0-24 + MOVD input+0(FP), R0 + MOVD accumulator+8(FP), R1 + MOVD output+16(FP), R2 + VLD1 (R0), [V0.B16] + VLD1 (R1), [V4.H8] + VLD1 (R1), [V5.H8] + WORD $0x4e202801 // SADDLP V1.8H, V0.16B + WORD $0x6e202802 // UADDLP V2.8H, V0.16B + WORD $0x4e206804 // SADALP V4.8H, V0.16B + WORD $0x6e206805 // UADALP V5.8H, V0.16B + VST1.P [V1.H8], 16(R2) + VST1.P [V2.H8], 16(R2) + VST1.P [V4.H8], 16(R2) + VST1 [V5.H8], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ir, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawpairwiseaddlong": { + Name: "rawpairwiseaddlong", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawpairwiseaddlong(const uint8_t *, const int16_t *, int16_t *); +int main(void) { + const uint8_t input[16] = {255,1,2,3,128,127,254,255,10,20,30,40,50,60,70,80}; + const int16_t accumulator[8] = {100,100,100,100,100,100,100,100}; + const int16_t signed_sum[8] = {0,5,-1,-3,30,70,110,150}; + const int16_t unsigned_sum[8] = {256,5,255,509,30,70,110,150}; + int16_t got[32] = {0}; + rawpairwiseaddlong(input, accumulator, got); + for (int lane = 0; lane < 8; lane++) { + if (got[lane] != signed_sum[lane]) return 1 + lane; + if (got[8 + lane] != unsigned_sum[lane]) return 10 + lane; + if (got[16 + lane] != signed_sum[lane] + 100) return 20 + lane; + if (got[24 + lane] != unsigned_sum[lane] + 100) return 30 + lane; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_pairwise_add_long", triple, ir, mainC, nil) +} diff --git a/arm64_lower_word_shsub.go b/arm64_lower_word_shsub.go new file mode 100644 index 00000000..4a6840e4 --- /dev/null +++ b/arm64_lower_word_shsub.go @@ -0,0 +1,57 @@ +package plan9asm + +import "fmt" + +type arm64RawSHSUB struct { + arrangement arm64VectorArrangement + destination int + first int + second int +} + +func decodeARM64RawSHSUB(word uint32) (arm64RawSHSUB, bool) { + if word&0xbf20fc00 != 0x0e202400 { + return arm64RawSHSUB{}, false + } + size := int(word>>22) & 3 + if size > 2 { + return arm64RawSHSUB{}, false + } + bits := 8 << size + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + return arm64RawSHSUB{ + arrangement: arm64VectorArrangement{elementBits: bits, lanes: vectorBits / bits}, + destination: int(word & 31), + first: int(word>>5) & 31, + second: int(word>>16) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawSHSUB(form arm64RawSHSUB) error { + first, err := c.loadRawARM64VectorOperand(form.first, form.arrangement, 0, false) + if err != nil { + return err + } + second, err := c.loadRawARM64VectorOperand(form.second, form.arrangement, 0, false) + if err != nil { + return err + } + narrow := form.arrangement + wide := arm64VectorArrangement{elementBits: narrow.elementBits * 2, lanes: narrow.lanes} + narrowType := fmt.Sprintf("<%d x i%d>", narrow.lanes, narrow.elementBits) + wideType := fmt.Sprintf("<%d x i%d>", wide.lanes, wide.elementBits) + wideFirst := c.newTmp() + wideSecond := c.newTmp() + difference := c.newTmp() + halved := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", wideFirst, narrowType, first, wideType) + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", wideSecond, narrowType, second, wideType) + fmt.Fprintf(c.b, " %%%s = sub %s %%%s, %%%s\n", difference, wideType, wideFirst, wideSecond) + fmt.Fprintf(c.b, " %%%s = ashr %s %%%s, %s\n", halved, wideType, difference, arm64VectorIntegerSplat(wide, 1)) + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", result, wideType, halved, narrowType) + return c.storeRawARM64VectorResult(form.destination, narrow, "%"+result, false) +} diff --git a/arm64_lower_word_shsub_test.go b/arm64_lower_word_shsub_test.go new file mode 100644 index 00000000..e95717d4 --- /dev/null +++ b/arm64_lower_word_shsub_test.go @@ -0,0 +1,119 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawSHSUBForms = ` +TEXT rawshsubforms(SB),$0-0 + WORD $0x0e222420 // SHSUB V0.8B, V1.8B, V2.8B + WORD $0x4e252483 // SHSUB V3.16B, V4.16B, V5.16B + WORD $0x0e6824e6 // SHSUB V6.4H, V7.4H, V8.4H + WORD $0x4e6b2549 // SHSUB V9.8H, V10.8H, V11.8H + WORD $0x0eae25ac // SHSUB V12.2S, V13.2S, V14.2S + WORD $0x4eb1260f // SHSUB V15.4S, V16.4S, V17.4S + RET +` + +func TestTranslateARM64RawSHSUBCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawSHSUBForms, true) + file, err := Parse(ArchARM64, arm64RawSHSUBForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawshsubforms": {Name: "rawshsubforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "sub <8 x i16>", "sub <16 x i16>", + "sub <4 x i32>", "sub <8 x i32>", + "sub <2 x i64>", "sub <4 x i64>", "ashr <", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw SHSUB lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-shsub.ll", "arm64-raw-shsub.o", ll) + }) + } +} + +func TestARM64RawSHSUBRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawshsub(SB),$0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V1.S4] + WORD $0x4ea12402 // SHSUB V2.4S, V0.4S, V1.4S + VST1 [V2.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawshsub": { + Name: "rawshsub", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void rawshsub(const int32_t *, const int32_t *, int32_t *); +int main(void) { + const int32_t a[4] = {INT32_MIN, INT32_MAX, -3, 4}; + const int32_t b[4] = {INT32_MAX, INT32_MIN, 4, -3}; + const int32_t want[4] = {INT32_MIN, INT32_MAX, -4, 3}; + int32_t got[4] = {0}; + rawshsub(a, b, got); + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_shsub", triple, ll, mainC, nil) +} + +func TestARM64RawSHSUBDecoderRejectsAdjacentUHSUBEncoding(t *testing.T) { + if _, ok := decodeARM64RawSHSUB(0x2e222420); ok { + t.Fatal("SHSUB decoder claimed adjacent UHSUB encoding") + } +} diff --git a/arm64_lower_word_sqdmulh.go b/arm64_lower_word_sqdmulh.go new file mode 100644 index 00000000..98591623 --- /dev/null +++ b/arm64_lower_word_sqdmulh.go @@ -0,0 +1,150 @@ +package plan9asm + +import "fmt" + +// arm64RawSQDMULH describes every Advanced SIMD SQDMULH encoding. Go 1.27 +// exposes only the SVE ZSQDMULH mnemonic, so ecosystem code that needs the +// fixed-width instruction still carries these encodings in WORD directives. +type arm64RawSQDMULH struct { + scalar bool + byElement bool + arrangement arm64VectorArrangement + destination int + first int + second int + element int +} + +func decodeARM64RawSQDMULH(word uint32) (arm64RawSQDMULH, bool) { + form := arm64RawSQDMULH{element: -1} + switch { + case word&0xff20fc00 == 0x5e20b400: // scalar, three same + form.scalar = true + case word&0xbf20fc00 == 0x0e20b400: // vector, three same + case word&0xff00f400 == 0x5f00c000: // scalar, by element + form.scalar = true + form.byElement = true + case word&0xbf00f400 == 0x0f00c000: // vector, by element + form.byElement = true + default: + return arm64RawSQDMULH{}, false + } + + size := int(word>>22) & 3 + if size != 1 && size != 2 { + return arm64RawSQDMULH{}, false + } + bits := 8 << size + lanes := 1 + if !form.scalar { + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + lanes = vectorBits / bits + } + form.arrangement = arm64VectorArrangement{elementBits: bits, lanes: lanes} + form.destination = int(word & 31) + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + if form.byElement { + form.second &= 15 + l := int(word>>21) & 1 + m := int(word>>20) & 1 + h := int(word>>11) & 1 + if bits == 16 { + form.element = m<<2 | l<<1 | h + } else { + form.second |= m << 4 + form.element = l<<1 | h + } + } + return form, true +} + +func (c *arm64Ctx) lowerRawSQDMULH(form arm64RawSQDMULH) error { + return c.lowerRawSaturatingDoublingMultiplyHigh(form, false) +} + +func (c *arm64Ctx) lowerRawSaturatingDoublingMultiplyHigh(form arm64RawSQDMULH, rounding bool) error { + first, err := c.loadRawARM64VectorOperand(form.first, form.arrangement, 0, form.scalar) + if err != nil { + return err + } + secondLane := 0 + if form.byElement { + secondLane = form.element + } + second, err := c.loadRawARM64VectorOperand(form.second, form.arrangement, secondLane, form.scalar || form.byElement) + if err != nil { + return err + } + + narrow := form.arrangement + wide := arm64VectorArrangement{elementBits: narrow.elementBits * 2, lanes: narrow.lanes} + narrowType := fmt.Sprintf("<%d x i%d>", narrow.lanes, narrow.elementBits) + wideType := fmt.Sprintf("<%d x i%d>", wide.lanes, wide.elementBits) + wideFirst := c.newTmp() + wideSecond := c.newTmp() + product := c.newTmp() + productValue := "" + shifted := c.newTmp() + truncated := c.newTmp() + firstMinimum := c.newTmp() + secondMinimum := c.newTmp() + overflow := c.newTmp() + result := c.newTmp() + minimum := -(int64(1) << (narrow.elementBits - 1)) + maximum := (int64(1) << (narrow.elementBits - 1)) - 1 + + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", wideFirst, narrowType, first, wideType) + fmt.Fprintf(c.b, " %%%s = sext %s %s to %s\n", wideSecond, narrowType, second, wideType) + fmt.Fprintf(c.b, " %%%s = mul %s %%%s, %%%s\n", product, wideType, wideFirst, wideSecond) + productValue = "%" + product + if rounding { + rounded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %s\n", rounded, wideType, productValue, arm64VectorIntegerSplat(wide, int64(1)<<(narrow.elementBits-2))) + productValue = "%" + rounded + } + fmt.Fprintf(c.b, " %%%s = ashr %s %s, %s\n", shifted, wideType, productValue, arm64VectorIntegerSplat(wide, int64(narrow.elementBits-1))) + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", truncated, wideType, shifted, narrowType) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, %s\n", firstMinimum, narrowType, first, arm64VectorIntegerSplat(narrow, minimum)) + fmt.Fprintf(c.b, " %%%s = icmp eq %s %s, %s\n", secondMinimum, narrowType, second, arm64VectorIntegerSplat(narrow, minimum)) + fmt.Fprintf(c.b, " %%%s = and <%d x i1> %%%s, %%%s\n", overflow, narrow.lanes, firstMinimum, secondMinimum) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, %s %s, %s %%%s\n", + result, narrow.lanes, overflow, narrowType, arm64VectorIntegerSplat(narrow, maximum), narrowType, truncated) + return c.storeRawARM64VectorResult(form.destination, narrow, "%"+result, form.scalar) +} + +func (c *arm64Ctx) loadRawARM64VectorOperand(index int, arrangement arm64VectorArrangement, lane int, scalarOrLane bool) (string, error) { + reg := Reg(fmt.Sprintf("V%d", index)) + if !scalarOrLane { + return c.loadARM64VectorInteger(Reg(fmt.Sprintf("V%d.%s", index, arm64VectorArrangementName(arrangement))), arrangement) + } + element, err := c.arm64VDUPExtractLane(reg, arrangement.elementBits, lane) + if err != nil { + return "", err + } + if arrangement.lanes == 1 { + seed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <1 x i%d> poison, i%d %s, i32 0\n", seed, arrangement.elementBits, arrangement.elementBits, element) + return "%" + seed, nil + } + return c.arm64VDUPSplat(arrangement, element), nil +} + +func (c *arm64Ctx) storeRawARM64VectorResult(index int, arrangement arm64VectorArrangement, value string, scalar bool) error { + reg := Reg(fmt.Sprintf("V%d", index)) + if !scalar { + return c.storeARM64VectorInteger(Reg(fmt.Sprintf("V%d.%s", index, arm64VectorArrangementName(arrangement))), arrangement, value) + } + element := c.newTmp() + physicalLanes := 128 / arrangement.elementBits + inserted := c.newTmp() + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <1 x i%d> %s, i32 0\n", element, arrangement.elementBits, value) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> zeroinitializer, i%d %%%s, i32 0\n", + inserted, physicalLanes, arrangement.elementBits, arrangement.elementBits, element) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to <16 x i8>\n", bytes, physicalLanes, arrangement.elementBits, inserted) + return c.storeVReg(reg, "%"+bytes) +} diff --git a/arm64_lower_word_sqdmulh_test.go b/arm64_lower_word_sqdmulh_test.go new file mode 100644 index 00000000..4dba80a3 --- /dev/null +++ b/arm64_lower_word_sqdmulh_test.go @@ -0,0 +1,139 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +// These encodings cover every Advanced SIMD SQDMULH format documented by +// LLVM 22's AArch64 assembler: scalar, vector, scalar-by-element, and +// vector-by-element, for every legal H/S arrangement and Q width. +const arm64RawSQDMULHForms = ` +TEXT rawsqdmulhforms(SB),$0-0 + WORD $0x5e62b420 // SQDMULH H0, H1, H2 + WORD $0x5ea5b483 // SQDMULH S3, S4, S5 + WORD $0x0e68b4e6 // SQDMULH V6.4H, V7.4H, V8.4H + WORD $0x4e6bb549 // SQDMULH V9.8H, V10.8H, V11.8H + WORD $0x0eaeb5ac // SQDMULH V12.2S, V13.2S, V14.2S + WORD $0x4eb1b60f // SQDMULH V15.4S, V16.4S, V17.4S + WORD $0x5f74ca72 // SQDMULH H18, H19, V4.H[7] + WORD $0x5fb7cad5 // SQDMULH S21, S22, V23.S[3] + WORD $0x0f7acb38 // SQDMULH V24.4H, V25.4H, V10.H[7] + WORD $0x4f7dcb9b // SQDMULH V27.8H, V28.8H, V13.H[7] + WORD $0x0fa1c81e // SQDMULH V30.2S, V0.2S, V1.S[3] + WORD $0x4fa4c862 // SQDMULH V2.4S, V3.4S, V4.S[3] + RET +` + +func TestTranslateARM64RawSQDMULHCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawSQDMULHForms, true) + file, err := Parse(ArchARM64, arm64RawSQDMULHForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawsqdmulhforms": {Name: "rawsqdmulhforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "mul <4 x i32>", "mul <8 x i32>", + "mul <2 x i64>", "mul <4 x i64>", + "ashr <4 x i32>", "ashr <8 x i32>", + "ashr <2 x i64>", "ashr <4 x i64>", + "select <", "i16 32767", "i32 2147483647", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw SQDMULH lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-sqdmulh.ll", "arm64-raw-sqdmulh.o", ll) + }) + } +} + +func TestARM64RawSQDMULHRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawsqdmulh(SB),$0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V1.S4] + WORD $0x4ea1b402 // SQDMULH V2.4S, V0.4S, V1.4S + VST1 [V2.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawsqdmulh": { + Name: "rawsqdmulh", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void rawsqdmulh(const int32_t *, const int32_t *, int32_t *); +int main(void) { + const int32_t a[4] = {INT32_MIN, INT32_MIN, 1073741824, -1073741824}; + const int32_t b[4] = {INT32_MIN, INT32_MAX, 1073741824, 1073741824}; + int32_t got[4] = {0}; + rawsqdmulh(a, b, got); + const int32_t want[4] = {INT32_MAX, -2147483647, 536870912, -536870912}; + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_sqdmulh", triple, ll, mainC, nil) +} + +func TestARM64RawSQDMULHDecoderRejectsAdjacentEncodings(t *testing.T) { + // SQRDMULH has different rounding semantics and must not be captured by the + // SQDMULH masks merely because the register fields are identical. + const word = uint32(0x6ea1b402) + if _, ok := decodeARM64RawSQDMULH(word); ok { + t.Fatal("SQDMULH decoder accepted adjacent SQRDMULH encoding") + } +} diff --git a/arm64_lower_word_sqrdmulh.go b/arm64_lower_word_sqrdmulh.go new file mode 100644 index 00000000..7388c8e3 --- /dev/null +++ b/arm64_lower_word_sqrdmulh.go @@ -0,0 +1,55 @@ +package plan9asm + +// decodeARM64RawSQRDMULH covers every fixed-width Advanced SIMD SQRDMULH +// encoding. Go 1.27 names only the SVE form, ZSQRDMULH, so fixed-width users +// carry these instructions as WORD directives. +func decodeARM64RawSQRDMULH(word uint32) (arm64RawSQDMULH, bool) { + form := arm64RawSQDMULH{element: -1} + switch { + case word&0xff20fc00 == 0x7e20b400: // scalar, three same + form.scalar = true + case word&0xbf20fc00 == 0x2e20b400: // vector, three same + case word&0xff00f400 == 0x5f00d000: // scalar, by element + form.scalar = true + form.byElement = true + case word&0xbf00f400 == 0x0f00d000: // vector, by element + form.byElement = true + default: + return arm64RawSQDMULH{}, false + } + + size := int(word>>22) & 3 + if size != 1 && size != 2 { + return arm64RawSQDMULH{}, false + } + bits := 8 << size + lanes := 1 + if !form.scalar { + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + lanes = vectorBits / bits + } + form.arrangement = arm64VectorArrangement{elementBits: bits, lanes: lanes} + form.destination = int(word & 31) + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + if form.byElement { + form.second &= 15 + l := int(word>>21) & 1 + m := int(word>>20) & 1 + h := int(word>>11) & 1 + if bits == 16 { + form.element = m<<2 | l<<1 | h + } else { + form.second |= m << 4 + form.element = l<<1 | h + } + } + return form, true +} + +func (c *arm64Ctx) lowerRawSQRDMULH(form arm64RawSQDMULH) error { + return c.lowerRawSaturatingDoublingMultiplyHigh(form, true) +} diff --git a/arm64_lower_word_sqrdmulh_test.go b/arm64_lower_word_sqrdmulh_test.go new file mode 100644 index 00000000..0de7b6b1 --- /dev/null +++ b/arm64_lower_word_sqrdmulh_test.go @@ -0,0 +1,76 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +// LLVM 22's AArch64 assembler was used to enumerate every fixed-width +// Advanced SIMD SQRDMULH form: scalar, vector, scalar-by-element, and +// vector-by-element, for every legal H/S arrangement and Q width. +const arm64RawSQRDMULHForms = ` +TEXT rawsqrdmulhforms(SB),$0-0 + WORD $0x7e62b420 // SQRDMULH H0, H1, H2 + WORD $0x7ea5b483 // SQRDMULH S3, S4, S5 + WORD $0x2e68b4e6 // SQRDMULH V6.4H, V7.4H, V8.4H + WORD $0x6e6bb549 // SQRDMULH V9.8H, V10.8H, V11.8H + WORD $0x2eaeb5ac // SQRDMULH V12.2S, V13.2S, V14.2S + WORD $0x6eb1b60f // SQRDMULH V15.4S, V16.4S, V17.4S + WORD $0x5f74da72 // SQRDMULH H18, H19, V4.H[7] + WORD $0x5fb7dad5 // SQRDMULH S21, S22, V23.S[3] + WORD $0x0f7adb38 // SQRDMULH V24.4H, V25.4H, V10.H[7] + WORD $0x4f7ddb9b // SQRDMULH V27.8H, V28.8H, V13.H[7] + WORD $0x0fa1d81e // SQRDMULH V30.2S, V0.2S, V1.S[3] + WORD $0x4fa4d862 // SQRDMULH V2.4S, V3.4S, V4.S[3] + RET +` + +func TestTranslateARM64RawSQRDMULHCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawSQRDMULHForms, true) + file, err := Parse(ArchARM64, arm64RawSQRDMULHForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawsqrdmulhforms": {Name: "rawsqrdmulhforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "mul <4 x i32>", "mul <8 x i32>", + "mul <2 x i64>", "mul <4 x i64>", + "add <4 x i32>", "add <8 x i32>", + "add <2 x i64>", "add <4 x i64>", + "ashr <", "select <", "i16 32767", "i32 2147483647", + } { + if !strings.Contains(ir, want) { + t.Fatalf("ARM64 raw SQRDMULH lowering for %s omitted %q:\n%s", triple, want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-sqrdmulh.ll", "arm64-raw-sqrdmulh.o", ir) + }) + } +} + +func TestARM64RawSQRDMULHDecoderDoesNotCaptureSQDMULH(t *testing.T) { + if _, ok := decodeARM64RawSQRDMULH(0x4ea1b402); ok { + t.Fatal("SQRDMULH decoder accepted adjacent SQDMULH encoding") + } +} diff --git a/arm64_lower_word_sshr.go b/arm64_lower_word_sshr.go new file mode 100644 index 00000000..b4b0eacb --- /dev/null +++ b/arm64_lower_word_sshr.go @@ -0,0 +1,74 @@ +package plan9asm + +import "fmt" + +type arm64RawSSHR struct { + scalar bool + arrangement arm64VectorArrangement + shift int + source int + destination int +} + +func decodeARM64RawSSHR(word uint32) (arm64RawSSHR, bool) { + form := arm64RawSSHR{} + switch { + case word&0xff80fc00 == 0x5f000400: + form.scalar = true + case word&0xbf80fc00 == 0x0f000400: + default: + return arm64RawSSHR{}, false + } + encodedImmediate := int(word>>16) & 0x7f + bits := 0 + switch { + case encodedImmediate >= 64: + bits = 64 + case encodedImmediate >= 32: + bits = 32 + case encodedImmediate >= 16: + bits = 16 + case encodedImmediate >= 8: + bits = 8 + default: + return arm64RawSSHR{}, false + } + shift := 2*bits - encodedImmediate + if shift < 1 || shift > bits || form.scalar && bits != 64 { + return arm64RawSSHR{}, false + } + vectorBits := 64 + if form.scalar { + form.arrangement = arm64VectorArrangement{elementBits: 64, lanes: 1} + } else { + if word&(1<<30) != 0 { + vectorBits = 128 + } + if bits == 64 && vectorBits != 128 { + return arm64RawSSHR{}, false + } + form.arrangement = arm64VectorArrangement{elementBits: bits, lanes: vectorBits / bits} + } + form.shift = shift + form.source = int(word>>5) & 31 + form.destination = int(word & 31) + return form, true +} + +func (c *arm64Ctx) lowerRawSSHR(form arm64RawSSHR) error { + source, err := c.loadRawARM64VectorOperand(form.source, form.arrangement, 0, form.scalar) + if err != nil { + return err + } + vectorType := fmt.Sprintf("<%d x i%d>", form.arrangement.lanes, form.arrangement.elementBits) + result := c.newTmp() + shift := form.shift + if shift == form.arrangement.elementBits { + // LLVM shifts by the element width are poison. AArch64 SSHR by the + // element width instead replicates the sign bit, which is equivalent to + // an arithmetic shift by width-1. + shift-- + } + fmt.Fprintf(c.b, " %%%s = ashr %s %s, %s\n", result, vectorType, source, arm64VectorIntegerSplat(form.arrangement, int64(shift))) + return c.storeRawARM64VectorResult(form.destination, form.arrangement, "%"+result, form.scalar) +} diff --git a/arm64_lower_word_sshr_test.go b/arm64_lower_word_sshr_test.go new file mode 100644 index 00000000..4699be00 --- /dev/null +++ b/arm64_lower_word_sshr_test.go @@ -0,0 +1,132 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawSSHRForms = ` +TEXT rawsshrforms(SB),$0-0 + WORD $0x0f0f0420 // SSHR V0.8B, V1.8B, #1 + WORD $0x4f080462 // SSHR V2.16B, V3.16B, #8 + WORD $0x0f1f04a4 // SSHR V4.4H, V5.4H, #1 + WORD $0x4f1004e6 // SSHR V6.8H, V7.8H, #16 + WORD $0x0f3f0528 // SSHR V8.2S, V9.2S, #1 + WORD $0x4f20056a // SSHR V10.4S, V11.4S, #32 + WORD $0x4f4005ac // SSHR V12.2D, V13.2D, #64 + WORD $0x5f7f05ee // SSHR D14, D15, #1 + RET +` + +func TestTranslateARM64RawSSHRCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawSSHRForms, true) + file, err := Parse(ArchARM64, arm64RawSSHRForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawsshrforms": {Name: "rawsshrforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "ashr <8 x i8>", "ashr <16 x i8>", + "ashr <4 x i16>", "ashr <8 x i16>", + "ashr <2 x i32>", "ashr <4 x i32>", + "ashr <2 x i64>", "ashr i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw SSHR lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-sshr.ll", "arm64-raw-sshr.o", ll) + }) + } +} + +func TestARM64RawSSHRDecoderCoversEveryImmediate(t *testing.T) { + for _, bits := range []int{8, 16, 32, 64} { + for shift := 1; shift <= bits; shift++ { + encodedImmediate := uint32(2*bits - shift) + word := uint32(0x0f000400) | encodedImmediate<<16 + if bits == 64 { + word |= 1 << 30 + } + form, ok := decodeARM64RawSSHR(word) + if !ok || form.arrangement.elementBits != bits || form.shift != shift { + t.Fatalf("decode SSHR bits=%d shift=%d: form=%#v ok=%v", bits, shift, form, ok) + } + } + } +} + +func TestARM64RawSSHRRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawsshr(SB),$0-16 + MOVD in+0(FP), R0 + MOVD out+8(FP), R1 + VLD1 (R0), [V30.S4] + WORD $0x4f2107de // SSHR V30.4S, V30.4S, #31 + VST1 [V30.S4], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawsshr": { + Name: "rawsshr", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void rawsshr(const int32_t *, int32_t *); +int main(void) { + const int32_t in[4] = {INT32_MIN, -1, 0, INT32_MAX}; + const int32_t want[4] = {-1, -1, 0, 0}; + int32_t got[4] = {0}; + rawsshr(in, got); + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_sshr", triple, ll, mainC, nil) +} + +func TestARM64RawSSHRDecoderRejectsAdjacentUSHR(t *testing.T) { + if _, ok := decodeARM64RawSSHR(0x2f0f0420); ok { + t.Fatal("SSHR decoder claimed adjacent USHR encoding") + } +} diff --git a/arm64_lower_word_structure_lane.go b/arm64_lower_word_structure_lane.go new file mode 100644 index 00000000..da588d11 --- /dev/null +++ b/arm64_lower_word_structure_lane.go @@ -0,0 +1,138 @@ +package plan9asm + +import "fmt" + +// arm64RawStructureLane describes the Advanced SIMD load/store single +// structure encodings. These are the LD1/ST1 through LD4/ST4 forms that move +// one selected lane in each consecutive vector register, rather than the +// whole-register structure forms accepted by Go's named VLDn/VSTn syntax. +type arm64RawStructureLane struct { + load bool + count int + elementBits int + lane int + firstRegister int + base int + post bool + postRegister int // 31 selects the architecture-defined fixed increment. +} + +func decodeARM64RawStructureLane(word uint32) (arm64RawStructureLane, bool) { + // Advanced SIMD load/store single structure. Q, L, R, opcode, S, size, + // Rm, Rn, and Rt are decoded below. Bit 23 distinguishes no-offset from + // post-indexed forms. In the no-offset form Rm is reserved and must be zero. + if word&0xbf000000 != 0x0d000000 { + return arm64RawStructureLane{}, false + } + post := word&(1<<23) != 0 + postRegister := int(word>>16) & 31 + if !post && postRegister != 0 { + return arm64RawStructureLane{}, false + } + + q := int(word>>30) & 1 + s := int(word>>12) & 1 + size := int(word>>10) & 3 + opcode := int(word>>13) & 7 + count := 1 + (int(word>>21) & 1) + 2*(opcode&1) + + elementBits := 0 + lane := 0 + switch opcode >> 1 { + case 0: // B: index = UInt(Q:S:size) + elementBits = 8 + lane = q<<3 | s<<2 | size + case 1: // H: index = UInt(Q:S:size<1>), size<0> is reserved. + if size&1 != 0 { + return arm64RawStructureLane{}, false + } + elementBits = 16 + lane = q<<2 | s<<1 | size>>1 + case 2: // S uses size=00; D uses S=0,size=01. + if size == 0 { + elementBits = 32 + lane = q<<1 | s + } else if size == 1 && s == 0 { + elementBits = 64 + lane = q + } else { + return arm64RawStructureLane{}, false + } + default: + // opcode<2:1> == 11 is the load-and-replicate family. + return arm64RawStructureLane{}, false + } + + return arm64RawStructureLane{ + load: word&(1<<22) != 0, + count: count, + elementBits: elementBits, + lane: lane, + firstRegister: int(word) & 31, + base: int(word>>5) & 31, + post: post, + postRegister: postRegister, + }, true +} + +func (c *arm64Ctx) lowerRawStructureLane(form arm64RawStructureLane) error { + base := Reg(fmt.Sprintf("R%d", form.base)) + if form.base == 31 { + base = SP + } + addr, err := c.loadReg(base) + if err != nil { + return err + } + arrangement := arm64VectorArrangement{ + elementBits: form.elementBits, + lanes: 128 / form.elementBits, + } + elementBytes := form.elementBits / 8 + + for registerOffset := 0; registerOffset < form.count; registerOffset++ { + reg := Reg(fmt.Sprintf("V%d", (form.firstRegister+registerOffset)%32)) + offset := int64(registerOffset * elementBytes) + if form.load { + element, err := c.arm64LoadStructureElement(addr, offset, form.elementBits) + if err != nil { + return err + } + vector, err := c.loadARM64VectorInteger(reg, arrangement) + if err != nil { + return err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> %s, i%d %s, i32 %d\n", + inserted, arrangement.lanes, form.elementBits, vector, + form.elementBits, element, form.lane) + if err := c.storeARM64VectorInteger(reg, arrangement, "%"+inserted); err != nil { + return err + } + continue + } + + vector, err := c.loadARM64VectorInteger(reg, arrangement) + if err != nil { + return err + } + element := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x i%d> %s, i32 %d\n", + element, arrangement.lanes, form.elementBits, vector, form.lane) + if err := c.arm64StoreStructureElement(addr, offset, form.elementBits, "%"+element); err != nil { + return err + } + } + + if !form.post { + return nil + } + increment := c.imm64(int64(form.count * elementBytes)) + if form.postRegister != 31 { + increment, err = c.loadReg(Reg(fmt.Sprintf("R%d", form.postRegister))) + if err != nil { + return err + } + } + return c.arm64UpdatePostIncrement(base, increment) +} diff --git a/arm64_lower_word_sve_count_test.go b/arm64_lower_word_sve_count_test.go new file mode 100644 index 00000000..4b569946 --- /dev/null +++ b/arm64_lower_word_sve_count_test.go @@ -0,0 +1,32 @@ +package plan9asm + +import "testing" + +const arm64RawSVECntForms = `TEXT svecntwords(SB),$0-0 + WORD $0x0420e3ea // CNTB X10 + WORD $0x0460e3ea // CNTH X10 + WORD $0x04a0e3ea // CNTW X10 + WORD $0x04e0e3ea // CNTD X10 + RET +` + +func TestTranslateARM64RawSVECntForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawSVECntForms, true) + file, err := Parse(ArchARM64, arm64RawSVECntForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{Goarch: "arm64", TargetTriple: triple, Sigs: map[string]FuncSig{"svecntwords": {Name: "svecntwords", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-count.ll", "arm64-sve-count.o", ir) + }) + } +} diff --git a/arm64_lower_word_sve_dup_immediate_test.go b/arm64_lower_word_sve_dup_immediate_test.go new file mode 100644 index 00000000..71f10376 --- /dev/null +++ b/arm64_lower_word_sve_dup_immediate_test.go @@ -0,0 +1,174 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64RawSVEDupImmediate(elementBits, immediate, shift, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + return 0x2538c000 | size<<22 | uint32(uint8(int8(immediate)))<<5 | uint32(shift/8)<<13 | uint32(destination) +} + +func TestTranslateARM64SVEDupImmediateCompleteGo127Form(t *testing.T) { + const named = ` +TEXT svedupnamed(SB),$0-0 + ZDUP R0, Z14.B + ZDUP R1, Z15.H + ZDUP R2, Z16.S + ZDUP RSP, Z17.D + ZDUP Z0.B[0], Z18.B + ZDUP Z1.B[15], Z19.B + ZDUP Z2.H[0], Z20.H + ZDUP Z3.H[7], Z21.H + ZDUP Z4.S[0], Z22.S + ZDUP Z5.S[3], Z23.S + ZDUP Z6.D[0], Z24.D + ZDUP Z7.D[1], Z25.D + ZDUP Z8.Q[0], Z26.Q + ZDUP Z9.Q[1], Z27.Q + ZDUP $-128, Z0.B + ZDUP $127, Z1.B + ZDUP $-128, Z2.H + ZDUP $127, Z3.H + ZDUP $-32768, Z4.H + ZDUP $32512, Z5.H + ZDUP $-128, Z6.S + ZDUP $127, Z7.S + ZDUP $-32768, Z8.S + ZDUP $32512, Z9.S + ZDUP $-128, Z10.D + ZDUP $127, Z11.D + ZDUP $-32768, Z12.D + ZDUP $32512, Z13.D + RET +` + requireARM64SVEGoAssemblerResult(t, named, true) + + var raw strings.Builder + raw.WriteString("TEXT svedupraw(SB),$0-0\n") + for _, elementBits := range []int{8, 16, 32, 64} { + for _, shift := range []int{0, 8} { + if elementBits == 8 && shift == 8 { + continue + } + for _, immediate := range []int{-128, 0, 127} { + fmt.Fprintf(&raw, "\tWORD $%#08x\n", encodeARM64RawSVEDupImmediate(elementBits, immediate, shift, (elementBits+shift+immediate)&31)) + } + } + } + raw.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, raw.String(), true) + + for name, source := range map[string]string{"named": named, "raw": raw.String()} { + t.Run(name, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + function := "svedup" + name + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{function: {Name: function, Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`"target-features"=`, "+sve", "", "splat (i"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 SVE DUP immediate lowering for %s/%s omitted %q:\n%s", name, triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-dup-immediate.ll", "arm64-sve-dup-immediate.o", ll) + }) + } + }) + } +} + +func encodeARM64RawSVEDupElement(elementBits, lane, source, destination int) uint32 { + if elementBits == 128 { + return 0x05202000 | 16<<16 | uint32(lane)<<22 | uint32(source)<<5 | uint32(destination) + } + size := map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + imm5 := lane<<(size+1) | 1<", 128/elementBits, floatingType) + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s to %s\n", converted, bytes, vectorType) + return "%" + converted, vectorType, nil +} + +func (c *arm64Ctx) storeRawSVEFloatVector(index, elementBits int, value string, vectorType string) error { + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to \n", bytes, vectorType, value) + return c.storeZReg(index, "%"+bytes) +} + +// decodeARM64RawSVEFloat covers the scalar-vector SVE floating arithmetic +// encodings emitted by Go's generated assembly. The destructive predicated +// forms keep Zd as their first operand; FMLA/FMAD use the two encoded source +// vectors and accumulate into Zd. +func decodeARM64RawSVEFloat(word uint32) (arm64RawSVEFloat, bool) { + form := arm64RawSVEFloat{elementBits: 8 << (int(word>>22) & 3)} + switch { + case word&0xff20fc00 == 0x65000000: + form.kind = arm64RawSVEFloatAdd + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + form.destination = int(word) & 31 + case word&0xff20fc00 == 0x65000400: + form.kind = arm64RawSVEFloatSub + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + form.destination = int(word) & 31 + case word&0xff20fc00 == 0x65000800: + form.kind = arm64RawSVEFloatMul + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + form.destination = int(word) & 31 + case word&0xff20e000 == 0x65008000: + form.kind = arm64RawSVEFloatAdd + form.predicated = true + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + form.predicate = int(word>>10) & 7 + case word&0xff20e000 == 0x65008400: + form.kind = arm64RawSVEFloatSub + form.predicated = true + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + form.predicate = int(word>>10) & 7 + case word&0xff20e000 == 0x65008800: + form.kind = arm64RawSVEFloatMul + form.predicated = true + form.first = int(word>>5) & 31 + form.destination = int(word) & 31 + form.predicate = int(word>>10) & 7 + case word&0xff20e000 == 0x65200000: + form.kind = arm64RawSVEFloatFMLA + form.predicated = true + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + form.destination = int(word) & 31 + form.predicate = int(word>>10) & 7 + case word&0xff20e000 == 0x65208000: + form.kind = arm64RawSVEFloatFMAD + form.predicated = true + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + form.destination = int(word) & 31 + form.predicate = int(word>>10) & 7 + case word&0xff20e000 == 0x65002000: + form.destination = int(word) & 31 + form.predicate = int(word>>10) & 7 + if word&0x001f0000 == 0 { + form.kind = arm64RawSVEFloatFADDV + form.first = form.destination + } else if word&0x001f0000 == 0x00180000 { + form.kind = arm64RawSVEFloatFADDA + form.first = int(word>>5) & 31 + } else { + return arm64RawSVEFloat{}, false + } + default: + return arm64RawSVEFloat{}, false + } + return form, true +} + +func (c *arm64Ctx) lowerRawSVEFloat(form arm64RawSVEFloat) error { + switch form.kind { + case arm64RawSVEFloatFADDV, arm64RawSVEFloatFADDA: + return c.lowerRawSVEFloatReduction(form) + } + _, _, err := arm64SVEVectorType(form.elementBits) + if err != nil { + return err + } + result := c.newTmp() + var vectorType string + if form.kind == arm64RawSVEFloatFMLA || form.kind == arm64RawSVEFloatFMAD { + first, vt, err := c.loadRawSVEFloatVector(form.first, form.elementBits) + if err != nil { + return err + } + vectorType = vt + second, _, err := c.loadRawSVEFloatVector(form.second, form.elementBits) + if err != nil { + return err + } + old, _, err := c.loadRawSVEFloatVector(form.destination, form.elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.fma.nxv%df%d(%s %s, %s %s, %s %s)\n", result, vectorType, 128/form.elementBits, form.elementBits, vectorType, first, vectorType, second, vectorType, old) + } else { + first, vt, err := c.loadRawSVEFloatVector(form.first, form.elementBits) + if err != nil { + return err + } + vectorType = vt + second := first + if !form.predicated { + second, _, err = c.loadRawSVEFloatVector(form.second, form.elementBits) + if err != nil { + return err + } + } + op := map[arm64RawSVEFloatKind]string{ + arm64RawSVEFloatAdd: "fadd", + arm64RawSVEFloatSub: "fsub", + arm64RawSVEFloatMul: "fmul", + }[form.kind] + if form.predicated { + old, _, err := c.loadRawSVEFloatVector(form.destination, form.elementBits) + if err != nil { + return err + } + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", result, op, vectorType, old, second) + } else { + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", result, op, vectorType, first, second) + } + } + value := "%" + result + if form.predicated { + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + old, _, err := c.loadRawSVEFloatVector(form.destination, form.elementBits) + if err != nil { + return err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s %s\n", selected, predicateType, predicate, vectorType, value, vectorType, old) + value = "%" + selected + } + return c.storeRawSVEFloatVector(form.destination, form.elementBits, value, vectorType) +} + +func (c *arm64Ctx) lowerRawSVEFloatReduction(form arm64RawSVEFloat) error { + sourceIndex := form.destination + if form.kind == arm64RawSVEFloatFADDA { + sourceIndex = form.first + } + source, vectorType, err := c.loadZRegElements(sourceIndex, form.elementBits) + if err != nil { + return err + } + predicate, predicateType, err := c.loadPRegElements(form.predicate, form.elementBits) + if err != nil { + return err + } + masked := c.newTmp() + floatingType := map[int]string{16: "half", 32: "float", 64: "double"}[form.elementBits] + if floatingType == "" { + return fmt.Errorf("unsupported ARM64 SVE floating element width %d", form.elementBits) + } + floatingVectorType := fmt.Sprintf("", 128/form.elementBits, floatingType) + if vectorType != floatingVectorType { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", converted, vectorType, source, floatingVectorType) + source = "%" + converted + } + zero := fmt.Sprintf("%s zeroinitializer", floatingVectorType) + fmt.Fprintf(c.b, " %%%s = select %s %s, %s %s, %s\n", masked, predicateType, predicate, floatingVectorType, source, zero) + initial := fmt.Sprintf("0.000000e+00") + if form.kind == arm64RawSVEFloatFADDA { + initial, err = c.loadARM64ScalarFloatReg(Reg(fmt.Sprintf("F%d", form.destination)), form.elementBits) + if err != nil { + return err + } + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.vector.reduce.fadd.nxv%df%d(%s %s, %s %%%s)\n", result, floatingType, 128/form.elementBits, form.elementBits, floatingType, initial, floatingVectorType, masked) + return c.storeARM64ScalarFloatReg(Reg(fmt.Sprintf("F%d", form.destination)), form.elementBits, "%"+result) +} diff --git a/arm64_lower_word_sve_float_test.go b/arm64_lower_word_sve_float_test.go new file mode 100644 index 00000000..71975f7f --- /dev/null +++ b/arm64_lower_word_sve_float_test.go @@ -0,0 +1,44 @@ +package plan9asm + +import "testing" + +const arm64RawSVEFloatForms = `TEXT svefloatwords(SB),$0-0 + WORD $0x65800020 // FADD Z0.S, Z1.S, Z0.S + WORD $0x65850484 // FSUB Z4.S, Z4.S, Z5.S + WORD $0x65810821 // FMUL Z1.S, Z1.S, Z1.S + WORD $0x65808080 // FADD Z0.S, P0/M, Z0.S, Z4.S + WORD $0x65a400a3 // FMLA Z3.S, P0/M, Z5.S, Z4.S + WORD $0x65a48203 // FMAD Z3.S, P0/M, Z16.S, Z4.S + WORD $0x65802063 // FADDV S3, P0, Z3.S + WORD $0x65982020 // FADDA S0, P0, S0, Z1.S + WORD $0x65400020 // FADD Z0.H, Z1.H, Z0.H + WORD $0x65c50484 // FSUB Z4.D, Z4.D, Z5.D + WORD $0x65c10821 // FMUL Z1.D, Z1.D, Z1.D + WORD $0x65c18480 // FSUB Z0.D, P1/M, Z0.D, Z4.D + WORD $0x65428861 // FMUL Z1.H, P2/M, Z1.H, Z3.H + WORD $0x65e400a3 // FMLA Z3.D, P0/M, Z5.D, Z4.D + WORD $0x65c02463 // FADDV D3, P1, Z3.D + WORD $0x65d82820 // FADDA D0, P2, D0, Z1.D + RET +` + +func TestTranslateARM64RawSVEFloatForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawSVEFloatForms, true) + file, err := Parse(ArchARM64, arm64RawSVEFloatForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{Goarch: "arm64", TargetTriple: triple, Sigs: map[string]FuncSig{"svefloatwords": {Name: "svefloatwords", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-float.ll", "arm64-sve-float.o", ir) + }) + } +} diff --git a/arm64_lower_word_sve_ldr_str.go b/arm64_lower_word_sve_ldr_str.go new file mode 100644 index 00000000..61732ecd --- /dev/null +++ b/arm64_lower_word_sve_ldr_str.go @@ -0,0 +1,66 @@ +package plan9asm + +import "fmt" + +type arm64RawSVELoadStore struct { + load bool + immediate int + base int + vector int +} + +// decodeARM64RawSVELoadStore covers the complete unpredicated SVE LDR/STR +// scalar-base format. Its signed imm9 is measured in whole vector lengths. +func decodeARM64RawSVELoadStore(word uint32) (arm64RawSVELoadStore, bool) { + form := arm64RawSVELoadStore{} + switch word & 0xffc0e000 { + case 0x85804000: + form.load = true + case 0xe5804000: + form.load = false + default: + return arm64RawSVELoadStore{}, false + } + imm9 := int(word>>16&0x3f)<<3 | int(word>>10&7) + if imm9&0x100 != 0 { + imm9 -= 0x200 + } + form.immediate = imm9 + form.base = int(word>>5) & 31 + form.vector = int(word) & 31 + return form, true +} + +func (c *arm64Ctx) lowerRawSVELoadStore(form arm64RawSVELoadStore) error { + baseReg := Reg(fmt.Sprintf("R%d", form.base)) + if form.base == 31 { + baseReg = SP + } + base, err := c.loadReg(baseReg) + if err != nil { + return err + } + address := base + if form.immediate != 0 { + vscale := c.newTmp() + offset := c.newTmp() + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.vscale.i64()\n", vscale) + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %d\n", offset, vscale, form.immediate*16) + fmt.Fprintf(c.b, " %%%s = add i64 %s, %%%s\n", adjusted, base, offset) + address = "%" + adjusted + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + if form.load { + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load , ptr %%%s, align 1\n", loaded, pointer) + return c.storeZReg(form.vector, "%"+loaded) + } + value, err := c.loadZReg(form.vector) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store %s, ptr %%%s, align 1\n", value, pointer) + return nil +} diff --git a/arm64_lower_word_sve_ldr_str_test.go b/arm64_lower_word_sve_ldr_str_test.go new file mode 100644 index 00000000..8e2f7d92 --- /dev/null +++ b/arm64_lower_word_sve_ldr_str_test.go @@ -0,0 +1,79 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64RawSVELoadStore(load bool, immediate, base, vector int) uint32 { + word := uint32(0xe5804000) + if load { + word = 0x85804000 + } + imm9 := uint32(immediate) & 0x1ff + return word | (imm9>>3)<<16 | (imm9&7)<<10 | uint32(base)<<5 | uint32(vector) +} + +func TestTranslateARM64RawSVELoadStoreCompleteFormat(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT sveLoadStoreRaw(SB), $0-0\n") + for _, form := range []struct { + load bool + immediate, base, vector int + }{{true, -256, 0, 0}, {true, 255, 31, 31}, {false, -256, 0, 0}, {false, 255, 31, 31}} { + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawSVELoadStore(form.load, form.immediate, form.base, form.vector)) + } + source.WriteString("\tRET\n") + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + ir, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"sveLoadStoreRaw": {Name: "sveLoadStoreRaw", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load ", "store ", "call i64 @llvm.vscale.i64()", `"target-features"="+sve"`} { + if !strings.Contains(ir, want) { + t.Fatalf("%s SVE LDR/STR IR omitted %q:\n%s", triple, want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-ldr-str.ll", "arm64-sve-ldr-str.o", ir) + } +} + +func TestARM64RawSVELoadStoreDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for _, load := range []bool{false, true} { + for immediate := -256; immediate <= 255; immediate++ { + for base := 0; base < 32; base++ { + for vector := 0; vector < 32; vector++ { + word := encodeARM64RawSVELoadStore(load, immediate, base, vector) + got, ok := decodeARM64RawSVELoadStore(word) + if !ok || got.load != load || got.immediate != immediate || got.base != base || got.vector != vector { + t.Fatalf("decoded SVE LDR/STR %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + if count != 2*512*32*32 { + t.Fatalf("covered %d SVE LDR/STR encodings", count) + } +} + +func TestARM64RawSVELoadStoreDecoderRejectsAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{0x85404000, 0xe5404000, 0x85806000} { + if _, ok := decodeARM64RawSVELoadStore(word); ok { + t.Fatalf("SVE LDR/STR decoder accepted adjacent encoding %#08x", word) + } + } +} diff --git a/arm64_lower_word_sve_ldst1d.go b/arm64_lower_word_sve_ldst1d.go new file mode 100644 index 00000000..808e972a --- /dev/null +++ b/arm64_lower_word_sve_ldst1d.go @@ -0,0 +1,113 @@ +package plan9asm + +import "fmt" + +type arm64RawSVELDST1D struct { + load bool + immediate int + registerOffset bool + index int + predicate int + base int + vector int +} + +// decodeARM64RawSVELDST1D recognizes the SVE contiguous, scalar-base, +// signed-imm4 MUL VL forms of LD1D and ST1D. Other SVE addressing classes are +// deliberately left for their own decoders so an adjacent encoding cannot be +// silently assigned the wrong semantics. +func decodeARM64RawSVELDST1D(word uint32) (arm64RawSVELDST1D, bool) { + form := arm64RawSVELDST1D{} + switch word & 0xffe0e000 { + case 0xa5e04000: + form.load = true + form.registerOffset = true + case 0xe5e04000: + form.registerOffset = true + } + if form.registerOffset { + form.index = int(word>>16) & 31 + form.predicate = int(word>>10) & 7 + form.base = int(word>>5) & 31 + form.vector = int(word) & 31 + return form, true + } + switch word & 0xfff0e000 { + case 0xa5e0a000: + form.load = true + case 0xe5e0e000: + form.load = false + default: + return arm64RawSVELDST1D{}, false + } + immediate := int(word>>16) & 15 + if immediate&8 != 0 { + immediate -= 16 + } + form.immediate = immediate + form.predicate = int(word>>10) & 7 + form.base = int(word>>5) & 31 + form.vector = int(word) & 31 + return form, true +} + +func (c *arm64Ctx) lowerRawSVELDST1D(form arm64RawSVELDST1D) error { + predicate, err := c.loadPReg(form.predicate) + if err != nil { + return err + } + narrowPredicate := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %s)\n", narrowPredicate, predicate) + + baseReg := Reg(fmt.Sprintf("R%d", form.base)) + if form.base == 31 { + baseReg = SP + } + base, err := c.loadReg(baseReg) + if err != nil { + return err + } + address := base + if form.registerOffset { + indexReg := ZR + if form.index != 31 { + indexReg = Reg(fmt.Sprintf("R%d", form.index)) + } + index, err := c.loadReg(indexReg) + if err != nil { + return err + } + scaled := c.newTmp() + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i64 %s, 3\n", scaled, index) + fmt.Fprintf(c.b, " %%%s = add i64 %s, %%%s\n", adjusted, base, scaled) + address = "%" + adjusted + } else if form.immediate != 0 { + vscale := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.vscale.i64()\n", vscale) + offset := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %d\n", offset, vscale, form.immediate*16) + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i64 %s, %%%s\n", adjusted, base, offset) + address = "%" + adjusted + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + + if form.load { + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.masked.load.nxv2i64.p0(ptr align 1 %%%s, %%%s, zeroinitializer)\n", loaded, pointer, narrowPredicate) + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %%%s to \n", bytes, loaded) + return c.storeZReg(form.vector, "%"+bytes) + } + + bytes, err := c.loadZReg(form.vector) + if err != nil { + return err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s to \n", value, bytes) + fmt.Fprintf(c.b, " call void @llvm.masked.store.nxv2i64.p0( %%%s, ptr align 1 %%%s, %%%s)\n", value, pointer, narrowPredicate) + return nil +} diff --git a/arm64_lower_word_sve_ldst1d_test.go b/arm64_lower_word_sve_ldst1d_test.go new file mode 100644 index 00000000..0c2ac6c5 --- /dev/null +++ b/arm64_lower_word_sve_ldst1d_test.go @@ -0,0 +1,143 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARM64RawSVELDST1D(load bool, immediate, predicate, base, vector int) uint32 { + opcode := uint32(0xe5e0e000) + if load { + opcode = 0xa5e0a000 + } + return opcode | uint32(immediate&15)<<16 | uint32(predicate)<<10 | uint32(base)<<5 | uint32(vector) +} + +func TestTranslateARM64RawSVELDST1DScalarImmediateCompleteFormats(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawldst1dforms(SB),$0-0\n") + for _, load := range []bool{true, false} { + for immediate := -8; immediate <= 7; immediate++ { + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawSVELDST1D(load, immediate, (immediate+8)%8, 2, 3)) + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawldst1dforms": {Name: "rawldst1dforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.convert.from.svbool.nxv2i1", + "@llvm.masked.load.nxv2i64.p0", " zeroinitializer", + "@llvm.masked.store.nxv2i64.p0", "call i64 @llvm.vscale.i64()", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw SVE LD1D/ST1D lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-sve-ldst1d.ll", "arm64-raw-sve-ldst1d.o", ll) + }) + } +} + +func TestARM64RawSVELDST1DDecoderCoversAllEncodingFields(t *testing.T) { + for _, load := range []bool{true, false} { + for immediate := -8; immediate <= 7; immediate++ { + for predicate := 0; predicate < 8; predicate++ { + for base := 0; base < 32; base++ { + for vector := 0; vector < 32; vector++ { + word := encodeARM64RawSVELDST1D(load, immediate, predicate, base, vector) + got, ok := decodeARM64RawSVELDST1D(word) + if !ok || got.load != load || got.immediate != immediate || got.predicate != predicate || got.base != base || got.vector != vector { + t.Fatalf("decoded SVE LD1D/ST1D word %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } + } +} + +func TestARM64RawSVELDST1DDecoderRejectsAdjacentAddressingClasses(t *testing.T) { + for _, word := range []uint32{0xa5a04000, 0xc5e0c000, 0xe5a0c000} { + if _, ok := decodeARM64RawSVELDST1D(word); ok { + t.Fatalf("SVE LD1D/ST1D decoder accepted adjacent encoding %#08x", word) + } + } +} + +func encodeARM64RawSVELDST1DScalarRegister(load bool, index, predicate, base, vector int) uint32 { + opcode := uint32(0xe5e04000) + if load { + opcode = 0xa5e04000 + } + return opcode | uint32(index)<<16 | uint32(predicate)<<10 | uint32(base)<<5 | uint32(vector) +} + +func TestTranslateARM64RawSVELDST1DScalarRegisterCompleteFormat(t *testing.T) { + const source = `TEXT rawldst1dregister(SB),$0-0 + WORD $0xa5ef40c1 // ld1d {z1.d}, p0/z, [x6,x15,lsl#3] + WORD $0xe5ef40c0 // st1d {z0.d}, p0, [x6,x15,lsl#3] + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{TargetTriple: triple, Goarch: "arm64", Sigs: map[string]FuncSig{"rawldst1dregister": {Name: "rawldst1dregister", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"shl i64", "@llvm.masked.load.nxv2i64.p0", "@llvm.masked.store.nxv2i64.p0", `"target-features"="+sve"`} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw SVE register-offset LD1D/ST1D lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-sve-ldst1d-register.ll", "arm64-raw-sve-ldst1d-register.o", ll) + }) + } +} + +func TestARM64RawSVELDST1DScalarRegisterDecoderCoversAllFields(t *testing.T) { + for _, load := range []bool{false, true} { + for index := 0; index < 32; index++ { + for predicate := 0; predicate < 8; predicate++ { + for base := 0; base < 32; base++ { + for vector := 0; vector < 32; vector++ { + word := encodeARM64RawSVELDST1DScalarRegister(load, index, predicate, base, vector) + got, ok := decodeARM64RawSVELDST1D(word) + if !ok || got.load != load || !got.registerOffset || got.index != index || got.predicate != predicate || got.base != base || got.vector != vector { + t.Fatalf("decoded register-offset SVE LD1D/ST1D %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } + } + } +} diff --git a/arm64_lower_word_sve_ldst1w.go b/arm64_lower_word_sve_ldst1w.go new file mode 100644 index 00000000..5b2a71c8 --- /dev/null +++ b/arm64_lower_word_sve_ldst1w.go @@ -0,0 +1,103 @@ +package plan9asm + +import "fmt" + +type arm64RawSVELDST1W struct { + load bool + immediate int + registerOffset bool + index int + predicate int + base int + vector int +} + +// decodeARM64RawSVELDST1W covers the SVE LD1W/ST1W scalar-base forms used by +// generated Go assembly: predicated zero/merge load-store with either a +// signed MUL VL immediate or a scalar register offset scaled by four bytes. +func decodeARM64RawSVELDST1W(word uint32) (arm64RawSVELDST1W, bool) { + form := arm64RawSVELDST1W{} + switch word & 0xffe0e000 { + case 0xa5404000: + form.load = true + form.registerOffset = true + case 0xe5404000: + form.registerOffset = true + case 0xa540a000: + form.load = true + case 0xe540e000: + default: + return arm64RawSVELDST1W{}, false + } + form.predicate = int(word>>10) & 7 + form.base = int(word>>5) & 31 + form.vector = int(word) & 31 + if form.registerOffset { + form.index = int(word>>16) & 31 + return form, true + } + form.immediate = int(word>>16) & 15 + if form.immediate&8 != 0 { + form.immediate -= 16 + } + return form, true +} + +func (c *arm64Ctx) lowerRawSVELDST1W(form arm64RawSVELDST1W) error { + predicate, err := c.loadPReg(form.predicate) + if err != nil { + return err + } + narrowPredicate := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %s)\n", narrowPredicate, predicate) + + baseReg := Reg(fmt.Sprintf("R%d", form.base)) + if form.base == 31 { + baseReg = SP + } + base, err := c.loadReg(baseReg) + if err != nil { + return err + } + address := base + if form.registerOffset { + indexReg := ZR + if form.index != 31 { + indexReg = Reg(fmt.Sprintf("R%d", form.index)) + } + index, err := c.loadReg(indexReg) + if err != nil { + return err + } + scaled := c.newTmp() + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i64 %s, 2\n", scaled, index) + fmt.Fprintf(c.b, " %%%s = add i64 %s, %%%s\n", adjusted, base, scaled) + address = "%" + adjusted + } else if form.immediate != 0 { + vscale := c.newTmp() + offset := c.newTmp() + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 @llvm.vscale.i64()\n", vscale) + fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %d\n", offset, vscale, form.immediate*16) + fmt.Fprintf(c.b, " %%%s = add i64 %s, %%%s\n", adjusted, base, offset) + address = "%" + adjusted + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i64 %s to ptr\n", pointer, address) + if form.load { + loaded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.masked.load.nxv4i32.p0(ptr align 1 %%%s, %%%s, zeroinitializer)\n", loaded, pointer, narrowPredicate) + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %%%s to \n", bytes, loaded) + return c.storeZReg(form.vector, "%"+bytes) + } + bytes, err := c.loadZReg(form.vector) + if err != nil { + return err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s to \n", value, bytes) + fmt.Fprintf(c.b, " call void @llvm.masked.store.nxv4i32.p0( %%%s, ptr align 1 %%%s, %%%s)\n", value, pointer, narrowPredicate) + return nil +} diff --git a/arm64_lower_word_sve_ldst1w_test.go b/arm64_lower_word_sve_ldst1w_test.go new file mode 100644 index 00000000..681d60d4 --- /dev/null +++ b/arm64_lower_word_sve_ldst1w_test.go @@ -0,0 +1,32 @@ +package plan9asm + +import "testing" + +const arm64RawSVELDST1WForms = `TEXT sveldst1wwords(SB),$0-0 + WORD $0xa54b4003 // LD1W {Z3.S}, P0/Z, [X0, X11, LSL #2] + WORD $0xa540a003 // LD1W {Z3.S}, P0/Z, [X0, #0, MUL VL] + WORD $0xe54b4003 // ST1W {Z3.S}, P0, [X0, X11, LSL #2] + WORD $0xe540e003 // ST1W {Z3.S}, P0, [X0, #0, MUL VL] + RET +` + +func TestTranslateARM64RawSVELDST1WForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawSVELDST1WForms, true) + file, err := Parse(ArchARM64, arm64RawSVELDST1WForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{Goarch: "arm64", TargetTriple: triple, Sigs: map[string]FuncSig{"sveldst1wwords": {Name: "sveldst1wwords", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-sve-ldst1w.ll", "arm64-sve-ldst1w.o", ir) + }) + } +} diff --git a/arm64_lower_word_sve_ptrue.go b/arm64_lower_word_sve_ptrue.go new file mode 100644 index 00000000..3f8baced --- /dev/null +++ b/arm64_lower_word_sve_ptrue.go @@ -0,0 +1,43 @@ +package plan9asm + +import "fmt" + +type arm64RawSVEPTrue struct { + elementBits int + pattern int + destination int +} + +func arm64SVEPTruePatternValid(pattern int) bool { + return (pattern >= 0 && pattern <= 13) || pattern == 29 || pattern == 30 || pattern == 31 +} + +func decodeARM64RawSVEPTrue(word uint32) (arm64RawSVEPTrue, bool) { + if word&0xff3ffc10 != 0x2518e000 { + return arm64RawSVEPTrue{}, false + } + pattern := int(word>>5) & 31 + if !arm64SVEPTruePatternValid(pattern) { + return arm64RawSVEPTrue{}, false + } + return arm64RawSVEPTrue{ + elementBits: 8 << (int(word>>22) & 3), + pattern: pattern, + destination: int(word) & 15, + }, true +} + +func (c *arm64Ctx) lowerRawSVEPTrue(form arm64RawSVEPTrue) error { + lanes := 128 / form.elementBits + predicateType := fmt.Sprintf("", lanes) + predicate := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ptrue.nxv%di1(i32 %d)\n", predicate, predicateType, lanes, form.pattern) + value := "%" + predicate + if form.elementBits != 8 { + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.convert.to.svbool.nxv%di1(%s %s)\n", + converted, lanes, predicateType, value) + value = "%" + converted + } + return c.storePReg(form.destination, value) +} diff --git a/arm64_lower_word_sve_ptrue_test.go b/arm64_lower_word_sve_ptrue_test.go new file mode 100644 index 00000000..3de6badc --- /dev/null +++ b/arm64_lower_word_sve_ptrue_test.go @@ -0,0 +1,87 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +var arm64SVEPTruePatterns = []int{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29, 30, 31} + +func encodeARM64RawSVEPTrue(elementBits, pattern, destination int) uint32 { + size := map[int]uint32{8: 0, 16: 1, 32: 2, 64: 3}[elementBits] + return 0x2518e000 | size<<22 | uint32(pattern)<<5 | uint32(destination) +} + +func TestTranslateARM64RawSVEPTrueCompleteFormats(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawptrueforms(SB),$0-0\n") + destination := 0 + for _, elementBits := range []int{8, 16, 32, 64} { + for _, pattern := range arm64SVEPTruePatterns { + fmt.Fprintf(&source, "\tWORD $%#08x\n", encodeARM64RawSVEPTrue(elementBits, pattern, destination%16)) + destination++ + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawptrueforms": {Name: "rawptrueforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `"target-features"="+sve"`, + "@llvm.aarch64.sve.ptrue.nxv16i1", "@llvm.aarch64.sve.ptrue.nxv8i1", + "@llvm.aarch64.sve.ptrue.nxv4i1", "@llvm.aarch64.sve.ptrue.nxv2i1", + "@llvm.aarch64.sve.convert.to.svbool.nxv2i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw PTRUE lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-sve-ptrue.ll", "arm64-raw-sve-ptrue.o", ll) + }) + } +} + +func TestARM64RawSVEPTrueDecoderCoversArchitecturalDomain(t *testing.T) { + for _, elementBits := range []int{8, 16, 32, 64} { + for _, pattern := range arm64SVEPTruePatterns { + for destination := 0; destination < 16; destination++ { + word := encodeARM64RawSVEPTrue(elementBits, pattern, destination) + got, ok := decodeARM64RawSVEPTrue(word) + if !ok || got.elementBits != elementBits || got.pattern != pattern || got.destination != destination { + t.Fatalf("decoded PTRUE word %#08x as %+v, ok=%v", word, got, ok) + } + } + } + } +} + +func TestARM64RawSVEPTrueDecoderRejectsReservedAndAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{ + encodeARM64RawSVEPTrue(8, 14, 0), + encodeARM64RawSVEPTrue(64, 28, 15), + 0x2518e400, // PFALSE. + } { + if _, ok := decodeARM64RawSVEPTrue(word); ok { + t.Fatalf("PTRUE decoder accepted reserved/adjacent encoding %#08x", word) + } + } +} diff --git a/arm64_lower_word_system_register.go b/arm64_lower_word_system_register.go new file mode 100644 index 00000000..f1017808 --- /dev/null +++ b/arm64_lower_word_system_register.go @@ -0,0 +1,55 @@ +package plan9asm + +import "fmt" + +type arm64RawSystemRegister struct { + read bool + encoding uint16 + reg int +} + +// decodeARM64RawSystemRegister covers the complete MRS/MSR (register) encoding +// fields: both directions, every 15-bit architectural system-register value, +// and every Xt value (including XZR). +func decodeARM64RawSystemRegister(word uint32) (arm64RawSystemRegister, bool) { + fixed := word & 0xfff00000 + if fixed != 0xd5300000 && fixed != 0xd5100000 { + return arm64RawSystemRegister{}, false + } + return arm64RawSystemRegister{ + read: fixed == 0xd5300000, + encoding: uint16((word >> 5) & 0x7fff), + reg: int(word & 31), + }, true +} + +func arm64EncodedSystemRegisterName(encoding uint16) string { + op0 := 2 + int((encoding>>14)&1) + op1 := int((encoding >> 11) & 7) + crn := int((encoding >> 7) & 15) + crm := int((encoding >> 3) & 15) + op2 := int(encoding & 7) + return fmt.Sprintf("S%d_%d_C%d_C%d_%d", op0, op1, crn, crm, op2) +} + +func (c *arm64Ctx) lowerRawSystemRegister(form arm64RawSystemRegister) error { + sysreg := arm64EncodedSystemRegisterName(form.encoding) + if form.read { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i64 asm sideeffect %q, %q()\n", value, "mrs $0, "+sysreg, "=r,~{memory}") + if form.reg == 31 { + return nil + } + return c.storeReg(Reg(fmt.Sprintf("R%d", form.reg)), "%"+value) + } + value := "0" + if form.reg != 31 { + var err error + value, err = c.loadReg(Reg(fmt.Sprintf("R%d", form.reg))) + if err != nil { + return err + } + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(i64 %s)\n", "msr "+sysreg+", $0", "r,~{memory}", value) + return nil +} diff --git a/arm64_lower_word_system_register_test.go b/arm64_lower_word_system_register_test.go new file mode 100644 index 00000000..1fc5393f --- /dev/null +++ b/arm64_lower_word_system_register_test.go @@ -0,0 +1,75 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestDecodeARM64RawSystemRegisterCompleteEncodingFields(t *testing.T) { + for _, direction := range []struct { + base uint32 + read bool + }{{0xd5100000, false}, {0xd5300000, true}} { + for encoding := 0; encoding <= 0x7fff; encoding++ { + for reg := 0; reg < 32; reg++ { + word := direction.base | uint32(encoding)<<5 | uint32(reg) + got, ok := decodeARM64RawSystemRegister(word) + if !ok || got.read != direction.read || got.encoding != uint16(encoding) || got.reg != reg { + t.Fatalf("decode %#08x = %#v, %v", word, got, ok) + } + } + } + } + for _, word := range []uint32{0xd5000000, 0xd5200000, 0xd5400000, 0xd4ffffff} { + if got, ok := decodeARM64RawSystemRegister(word); ok { + t.Fatalf("decodeARM64RawSystemRegister(%#08x) = %#v, true", word, got) + } + } + if got := arm64EncodedSystemRegisterName(0x5e82); got != "S3_3_C13_C0_2" { + t.Fatalf("TPIDR_EL0 encoding name = %q", got) + } +} + +func TestTranslateARM64RawSystemRegisterFamilyLLVM22(t *testing.T) { + const source = `TEXT ·rawSystemRegisters(SB), $0-0 + WORD $0xd53bd040 + WORD $0xd51bd040 + WORD $0xd53bd05f + WORD $0xd51bd05f + RET +` + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "rawSystemRegisters": {Name: "rawSystemRegisters", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{"mrs $0, S3_3_C13_C0_2", "msr S3_3_C13_C0_2, $0"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s raw system-register IR omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, fmt.Sprintf("arm64-raw-system-register-%s.ll", strings.ReplaceAll(triple, "-", "_")), "arm64-raw-system-register.o", ll) + } +} diff --git a/arm64_lower_word_table_lookup.go b/arm64_lower_word_table_lookup.go new file mode 100644 index 00000000..efc74baf --- /dev/null +++ b/arm64_lower_word_table_lookup.go @@ -0,0 +1,62 @@ +package plan9asm + +import "fmt" + +type arm64RawTableLookup struct { + extension bool + lanes int + tableCount int + index int + firstTable int + destination int +} + +func decodeARM64RawTableLookup(word uint32) (arm64RawTableLookup, bool) { + // Advanced SIMD TBL/TBX (vector). Q, len, op and the three register + // fields are variable; every remaining bit is architecturally fixed. + if word&0xbfe08c00 != 0x0e000000 { + return arm64RawTableLookup{}, false + } + lanes := 8 + if word&(1<<30) != 0 { + lanes = 16 + } + return arm64RawTableLookup{ + extension: word&(1<<12) != 0, + lanes: lanes, + tableCount: int(word>>13)&3 + 1, + index: int(word>>16) & 31, + firstTable: int(word>>5) & 31, + destination: int(word) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawTableLookup(form arm64RawTableLookup) error { + arrangement := fmt.Sprintf("B%d", form.lanes) + reg := func(index int) Reg { + return Reg(fmt.Sprintf("V%d.%s", index, arrangement)) + } + tables := make([]Reg, form.tableCount) + for i := range tables { + // Table operands are always full 128-bit vectors, independently of Q. + tables[i] = Reg(fmt.Sprintf("V%d.B16", (form.firstTable+i)%32)) + } + op := Op("VTBL") + if form.extension { + op = "VTBX" + } + ins := Instr{ + Op: op, + Raw: "decoded ARM64 WORD as " + string(op), + Args: []Operand{ + {Kind: OpReg, Reg: reg(form.index)}, + {Kind: OpRegList, RegList: tables}, + {Kind: OpReg, Reg: reg(form.destination)}, + }, + } + ok, _, err := c.lowerARM64VectorTableLookup(op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", op) + } + return err +} diff --git a/arm64_lower_word_table_lookup_test.go b/arm64_lower_word_table_lookup_test.go new file mode 100644 index 00000000..efba7727 --- /dev/null +++ b/arm64_lower_word_table_lookup_test.go @@ -0,0 +1,101 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARM64RawTableLookupCompleteAdvancedSIMDFormats(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawtablelookupforms(SB),$0-0\n") + for _, extension := range []bool{false, true} { + for _, lanes := range []int{8, 16} { + for tableCount := 1; tableCount <= 4; tableCount++ { + word := uint32(0x0e000000 | ((tableCount - 1) << 13) | (3 << 16) | (2 << 5) | 1) + if extension { + word |= 1 << 12 + } + if lanes == 16 { + word |= 1 << 30 + } + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawtablelookupforms": {Name: "rawtablelookupforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"<8 x i8>", "<16 x i8>", "<64 x i8>", "icmp ult i32"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw table lookup lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-table-lookup.ll", "arm64-raw-table-lookup.o", ll) + }) + } +} + +func TestARM64RawTableLookupDecoderCoversAllRegisterFields(t *testing.T) { + for _, extension := range []bool{false, true} { + for _, lanes := range []int{8, 16} { + for tableCount := 1; tableCount <= 4; tableCount++ { + for index := 0; index < 32; index++ { + for firstTable := 0; firstTable < 32; firstTable++ { + for destination := 0; destination < 32; destination++ { + word := uint32(0x0e000000 | ((tableCount - 1) << 13) | (index << 16) | (firstTable << 5) | destination) + if extension { + word |= 1 << 12 + } + if lanes == 16 { + word |= 1 << 30 + } + form, ok := decodeARM64RawTableLookup(word) + if !ok || form.extension != extension || form.lanes != lanes || form.tableCount != tableCount || form.index != index || form.firstTable != firstTable || form.destination != destination { + t.Fatalf("decode %#08x = %#v, %v", word, form, ok) + } + } + } + } + } + } + } +} + +func TestARM64RawTableLookupDecoderRejectsAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{ + 0x2e030042, + 0x0e038042, + 0x0e030442, + 0x0e030c42, + } { + if form, ok := decodeARM64RawTableLookup(word); ok { + t.Fatalf("table lookup decoder accepted adjacent encoding %#08x as %#v", word, form) + } + } +} diff --git a/arm64_lower_word_test.go b/arm64_lower_word_test.go new file mode 100644 index 00000000..7649e56c --- /dev/null +++ b/arm64_lower_word_test.go @@ -0,0 +1,70 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64KnownRawWordsHaveRealSemantics(t *testing.T) { + source := ` +TEXT rawwordforms(SB),$0-0 + WORD $0xea00001f + WORD $0xf1000400 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawwordforms": {Name: "rawwordforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"icmp eq i64", "sub i64"} { + if !strings.Contains(ll, want) { + t.Fatalf("known ARM64 WORD omitted %q semantics:\n%s", want, ll) + } + } +} + +func TestTranslateARM64UnknownRawEncodingFailsExplicitly(t *testing.T) { + // Go accepts arbitrary integer payloads in WORD directives. A reserved + // encoding must remain an explicit error rather than being swallowed by an + // over-broad decoder and reported as successfully translated. + source := "TEXT rawword(SB),$0-0\n\tWORD $0xffffffff\n\tRET\n" + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawword": {Name: "rawword", Ret: Void}}, + }); err == nil || !strings.Contains(err.Error(), "unsupported ARM64 WORD encoding") { + t.Fatalf("unknown ARM64 WORD did not fail explicitly: %v", err) + } +} + +func TestTranslateARM64RawDirectiveRejectsMalformedOrPartialEncoding(t *testing.T) { + for _, instruction := range []string{"WORD", "WORD R0", "WORD $1, $2", "BYTE $0xd5"} { + file, err := Parse(ArchARM64, "TEXT bad(SB),$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate silently accepted raw directive %q", instruction) + } + } +} diff --git a/arm64_lower_word_uabd_test.go b/arm64_lower_word_uabd_test.go new file mode 100644 index 00000000..6890e4c9 --- /dev/null +++ b/arm64_lower_word_uabd_test.go @@ -0,0 +1,33 @@ +package plan9asm + +import "testing" + +const arm64RawVUABDForms = `TEXT vuabdwords(SB),$0-0 + WORD $0x2E207400 // UABD V0.8B, V0.8B, V0.8B + WORD $0x6E30749D // UABD V29.16B, V4.16B, V16.16B + WORD $0x2E607400 // UABD V0.4H, V0.4H, V0.4H + WORD $0x2EA07400 // UABD V0.2S, V0.2S, V0.2S + WORD $0x6EA07400 // UABD V0.4S, V0.4S, V0.4S + RET +` + +func TestTranslateARM64RawVUABDForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawVUABDForms, true) + file, err := Parse(ArchARM64, arm64RawVUABDForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{Goarch: "arm64", TargetTriple: triple, Sigs: map[string]FuncSig{"vuabdwords": {Name: "vuabdwords", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vuabd.ll", "arm64-vuabd.o", ir) + }) + } +} diff --git a/arm64_lower_word_uadalp.go b/arm64_lower_word_uadalp.go new file mode 100644 index 00000000..6ab59ab0 --- /dev/null +++ b/arm64_lower_word_uadalp.go @@ -0,0 +1,103 @@ +package plan9asm + +import "fmt" + +type arm64RawPairwiseAddLong struct { + signed bool + accumulate bool + source arm64VectorArrangement + destination arm64VectorArrangement + sourceReg int + destReg int +} + +func decodeARM64RawPairwiseAddLong(word uint32) (arm64RawPairwiseAddLong, bool) { + form := arm64RawPairwiseAddLong{} + switch word & 0xbf3ffc00 { + case 0x0e202800: // SADDLP. + form.signed = true + case 0x2e202800: // UADDLP. + case 0x0e206800: // SADALP. + form.signed, form.accumulate = true, true + case 0x2e206800: // UADALP. + form.accumulate = true + default: + return arm64RawPairwiseAddLong{}, false + } + size := int(word>>22) & 3 + if size > 2 { + return arm64RawPairwiseAddLong{}, false + } + sourceBits := 8 << size + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + sourceLanes := vectorBits / sourceBits + form.source = arm64VectorArrangement{elementBits: sourceBits, lanes: sourceLanes} + form.destination = arm64VectorArrangement{elementBits: sourceBits * 2, lanes: sourceLanes / 2} + form.sourceReg = int(word>>5) & 31 + form.destReg = int(word & 31) + return form, true +} + +// Keep the instruction-specific entry point for focused compatibility tests. +type arm64RawUADALP = arm64RawPairwiseAddLong + +func decodeARM64RawUADALP(word uint32) (arm64RawUADALP, bool) { + form, ok := decodeARM64RawPairwiseAddLong(word) + if !ok || form.signed || !form.accumulate { + return arm64RawUADALP{}, false + } + return form, true +} + +func (c *arm64Ctx) lowerRawUADALP(form arm64RawUADALP) error { + return c.lowerRawPairwiseAddLong(form) +} + +func (c *arm64Ctx) lowerRawPairwiseAddLong(form arm64RawPairwiseAddLong) error { + source, err := c.loadRawARM64VectorOperand(form.sourceReg, form.source, 0, false) + if err != nil { + return err + } + sourceType := fmt.Sprintf("<%d x i%d>", form.source.lanes, form.source.elementBits) + pairType := fmt.Sprintf("<%d x i%d>", form.destination.lanes, form.source.elementBits) + destType := fmt.Sprintf("<%d x i%d>", form.destination.lanes, form.destination.elementBits) + even := c.newTmp() + odd := c.newTmp() + c.writeRawPairwiseAddLongShuffle(even, sourceType, source, pairType, form.destination.lanes, 0) + c.writeRawPairwiseAddLongShuffle(odd, sourceType, source, pairType, form.destination.lanes, 1) + wideEven := c.newTmp() + wideOdd := c.newTmp() + pairs := c.newTmp() + extension := "zext" + if form.signed { + extension = "sext" + } + fmt.Fprintf(c.b, " %%%s = %s %s %%%s to %s\n", wideEven, extension, pairType, even, destType) + fmt.Fprintf(c.b, " %%%s = %s %s %%%s to %s\n", wideOdd, extension, pairType, odd, destType) + fmt.Fprintf(c.b, " %%%s = add %s %%%s, %%%s\n", pairs, destType, wideEven, wideOdd) + result := "%" + pairs + if form.accumulate { + accumulator, err := c.loadRawARM64VectorOperand(form.destReg, form.destination, 0, false) + if err != nil { + return err + } + added := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add %s %s, %%%s\n", added, destType, accumulator, pairs) + result = "%" + added + } + return c.storeRawARM64VectorResult(form.destReg, form.destination, result, false) +} + +func (c *arm64Ctx) writeRawPairwiseAddLongShuffle(name, sourceType, source, resultType string, lanes, parity int) { + fmt.Fprintf(c.b, " %%%s = shufflevector %s %s, %s poison, <%d x i32> <", name, sourceType, source, sourceType, lanes) + for lane := 0; lane < lanes; lane++ { + if lane != 0 { + c.b.WriteString(", ") + } + fmt.Fprintf(c.b, "i32 %d", lane*2+parity) + } + c.b.WriteString(">\n") +} diff --git a/arm64_lower_word_uadalp_test.go b/arm64_lower_word_uadalp_test.go new file mode 100644 index 00000000..a6515cf5 --- /dev/null +++ b/arm64_lower_word_uadalp_test.go @@ -0,0 +1,113 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawUADALPForms = ` +TEXT rawuadalpforms(SB),$0-0 + WORD $0x2e206820 // UADALP V0.4H, V1.8B + WORD $0x6e206862 // UADALP V2.8H, V3.16B + WORD $0x2e6068a4 // UADALP V4.2S, V5.4H + WORD $0x6e6068e6 // UADALP V6.4S, V7.8H + WORD $0x2ea06928 // UADALP V8.1D, V9.2S + WORD $0x6ea0696a // UADALP V10.2D, V11.4S + RET +` + +func TestTranslateARM64RawUADALPCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawUADALPForms, true) + file, err := Parse(ArchARM64, arm64RawUADALPForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawuadalpforms": {Name: "rawuadalpforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "zext <4 x i8>", "zext <8 x i8>", + "zext <2 x i16>", "zext <4 x i16>", + "zext <1 x i32>", "zext <2 x i32>", "add <", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw UADALP lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-uadalp.ll", "arm64-raw-uadalp.o", ll) + }) + } +} + +func TestARM64RawUADALPRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawuadalp(SB),$0-16 + MOVD in+0(FP), R0 + MOVD inout+8(FP), R1 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V4.D2] + WORD $0x6ea06804 // UADALP V4.2D, V0.4S + VST1 [V4.D2], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawuadalp": { + Name: "rawuadalp", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawuadalp(const uint32_t *, uint64_t *); +int main(void) { + const uint32_t in[4] = {0xffffffffu, 1, 2, 0xfffffffeu}; + uint64_t got[2] = {7, 9}; + const uint64_t want[2] = {UINT64_C(0x100000007), UINT64_C(0x100000009)}; + rawuadalp(in, got); + for (int i = 0; i < 2; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_uadalp", triple, ll, mainC, nil) +} + +func TestARM64RawUADALPDecoderRejectsAdjacentSADALPEncoding(t *testing.T) { + if _, ok := decodeARM64RawUADALP(0x0e206820); ok { + t.Fatal("UADALP decoder claimed adjacent SADALP encoding") + } +} diff --git a/arm64_lower_word_uhadd.go b/arm64_lower_word_uhadd.go new file mode 100644 index 00000000..8e7182fc --- /dev/null +++ b/arm64_lower_word_uhadd.go @@ -0,0 +1,57 @@ +package plan9asm + +import "fmt" + +type arm64RawUHADD struct { + arrangement arm64VectorArrangement + destination int + first int + second int +} + +func decodeARM64RawUHADD(word uint32) (arm64RawUHADD, bool) { + if word&0xbf20fc00 != 0x2e200400 { + return arm64RawUHADD{}, false + } + size := int(word>>22) & 3 + // The Advanced SIMD UHADD encoding has no 64-bit element form. Go's + // assembler currently emits the reserved size=3 encoding if asked for D2, + // so validate the architectural encoding independently of parser acceptance. + if size > 2 { + return arm64RawUHADD{}, false + } + bits := 8 << size + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + return arm64RawUHADD{ + arrangement: arm64VectorArrangement{elementBits: bits, lanes: vectorBits / bits}, + destination: int(word & 31), + first: int(word>>5) & 31, + second: int(word>>16) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawUHADD(form arm64RawUHADD) error { + arrangement := arm64VectorArrangementName(form.arrangement) + reg := func(index int) Operand { + return Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", index, arrangement))} + } + // Plan 9 syntax orders the operands Vm, Vn, Vd, while the raw fields above + // use the architectural Vd, Vn, Vm names. + ins := Instr{ + Op: "VUHADD", + Raw: "decoded ARM64 WORD as VUHADD", + Args: []Operand{ + reg(form.second), + reg(form.first), + reg(form.destination), + }, + } + ok, _, err := c.lowerARM64VectorHalvingAdd("VUHADD", ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw VUHADD decoder reached no semantic lowerer") + } + return err +} diff --git a/arm64_lower_word_uhadd_test.go b/arm64_lower_word_uhadd_test.go new file mode 100644 index 00000000..0b0b4151 --- /dev/null +++ b/arm64_lower_word_uhadd_test.go @@ -0,0 +1,122 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +const arm64RawUHADDForms = ` +TEXT rawuhaddforms(SB),$0-0 + WORD $0x2e220420 // UHADD V0.8B, V1.8B, V2.8B + WORD $0x6e250483 // UHADD V3.16B, V4.16B, V5.16B + WORD $0x2e6804e6 // UHADD V6.4H, V7.4H, V8.4H + WORD $0x6e6b0549 // UHADD V9.8H, V10.8H, V11.8H + WORD $0x2eae05ac // UHADD V12.2S, V13.2S, V14.2S + WORD $0x6eb1060f // UHADD V15.4S, V16.4S, V17.4S + RET +` + +func TestTranslateARM64RawUHADDCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawUHADDForms, true) + file, err := Parse(ArchARM64, arm64RawUHADDForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawuhaddforms": {Name: "rawuhaddforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "lshr <8 x i16>", "lshr <16 x i16>", + "lshr <4 x i32>", "lshr <8 x i32>", + "lshr <2 x i64>", "lshr <4 x i64>", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw UHADD lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-uhadd.ll", "arm64-raw-uhadd.o", ll) + }) + } +} + +func TestARM64RawUHADDRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawuhadd(SB),$0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V1.S4] + WORD $0x6ea10402 // UHADD V2.4S, V0.4S, V1.4S + VST1 [V2.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawuhadd": { + Name: "rawuhadd", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void rawuhadd(const uint32_t *, const uint32_t *, uint32_t *); +int main(void) { + const uint32_t a[4] = {UINT32_MAX, UINT32_MAX, 1, 4}; + const uint32_t b[4] = {UINT32_MAX, 1, 2, 3}; + const uint32_t want[4] = {UINT32_MAX, 2147483648u, 1, 3}; + uint32_t got[4] = {0}; + rawuhadd(a, b, got); + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_uhadd", triple, ll, mainC, nil) +} + +func TestARM64RawUHADDDecoderRejectsAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{0x0e220420, 0x2e221420, 0x6ee20420} { // SHADD, URHADD, reserved D2. + t.Run(fmt.Sprintf("%#08x", word), func(t *testing.T) { + if _, ok := decodeARM64RawUHADD(word); ok { + t.Fatalf("UHADD decoder claimed adjacent/reserved encoding %#08x", word) + } + }) + } +} diff --git a/arm64_lower_word_umlal.go b/arm64_lower_word_umlal.go new file mode 100644 index 00000000..6bfcfc6e --- /dev/null +++ b/arm64_lower_word_umlal.go @@ -0,0 +1,63 @@ +package plan9asm + +import "fmt" + +type arm64RawUMLAL struct { + highHalf bool + source arm64VectorArrangement + destination arm64VectorArrangement + destReg int + first int + second int +} + +func decodeARM64RawUMLAL(word uint32) (arm64RawUMLAL, bool) { + if word&0xbf20fc00 != 0x2e208000 { + return arm64RawUMLAL{}, false + } + size := int(word>>22) & 3 + if size > 2 { + return arm64RawUMLAL{}, false + } + sourceBits := 8 << size + destinationLanes := 128 / (sourceBits * 2) + highHalf := word&(1<<30) != 0 + sourceLanes := destinationLanes + if highHalf { + sourceLanes *= 2 + } + return arm64RawUMLAL{ + highHalf: highHalf, + source: arm64VectorArrangement{elementBits: sourceBits, lanes: sourceLanes}, + destination: arm64VectorArrangement{elementBits: sourceBits * 2, lanes: destinationLanes}, + destReg: int(word & 31), + first: int(word>>5) & 31, + second: int(word>>16) & 31, + }, true +} + +func (c *arm64Ctx) lowerRawUMLAL(form arm64RawUMLAL) error { + op := Op("VUMLAL") + if form.highHalf { + op = "VUMLAL2" + } + sourceArrangement := arm64VectorArrangementName(form.source) + destinationArrangement := arm64VectorArrangementName(form.destination) + sourceReg := func(index int) Operand { + return Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", index, sourceArrangement))} + } + ins := Instr{ + Op: op, + Raw: fmt.Sprintf("decoded ARM64 WORD as %s", op), + Args: []Operand{ + sourceReg(form.second), + sourceReg(form.first), + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.destReg, destinationArrangement))}, + }, + } + ok, _, err := c.lowerARM64VectorWideningMultiply(op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", op) + } + return err +} diff --git a/arm64_lower_word_umlal_test.go b/arm64_lower_word_umlal_test.go new file mode 100644 index 00000000..54330667 --- /dev/null +++ b/arm64_lower_word_umlal_test.go @@ -0,0 +1,130 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +const arm64RawUMLALForms = ` +TEXT rawumlalforms(SB),$0-0 + WORD $0x2e228020 // UMLAL V0.8H, V1.8B, V2.8B + WORD $0x6e258083 // UMLAL2 V3.8H, V4.16B, V5.16B + WORD $0x2e6880e6 // UMLAL V6.4S, V7.4H, V8.4H + WORD $0x6e6b8149 // UMLAL2 V9.4S, V10.8H, V11.8H + WORD $0x2eae81ac // UMLAL V12.2D, V13.2S, V14.2S + WORD $0x6eb1820f // UMLAL2 V15.2D, V16.4S, V17.4S + RET +` + +func TestTranslateARM64RawUMLALCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawUMLALForms, true) + file, err := Parse(ArchARM64, arm64RawUMLALForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawumlalforms": {Name: "rawumlalforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "zext <8 x i8>", "zext <4 x i16>", "zext <2 x i32>", + "mul <8 x i16>", "mul <4 x i32>", "mul <2 x i64>", "add <", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw UMLAL lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-umlal.ll", "arm64-raw-umlal.o", ll) + }) + } +} + +func TestARM64RawUMLALRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawumlal(SB),$0-32 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD accumulator+16(FP), R2 + MOVD out+24(FP), R3 + VLD1 (R0), [V0.B16] + VLD1 (R1), [V1.B16] + VLD1 (R2), [V2.H8, V3.H8] + WORD $0x2e218002 // UMLAL V2.8H, V0.8B, V1.8B + WORD $0x6e218003 // UMLAL2 V3.8H, V0.16B, V1.16B + VST1 [V2.H8, V3.H8], (R3) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawumlal": { + Name: "rawumlal", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawumlal(const uint8_t *, const uint8_t *, const uint16_t *, uint16_t *); +int main(void) { + uint8_t a[16], b[16]; + uint16_t accumulator[16], got[16] = {0}; + for (int i = 0; i < 16; i++) { + a[i] = (uint8_t)(240+i); + b[i] = (uint8_t)(17-i); + accumulator[i] = (uint16_t)(65000+i); + } + rawumlal(a, b, accumulator, got); + for (int i = 0; i < 16; i++) { + uint16_t want = (uint16_t)(accumulator[i] + (uint16_t)a[i] * (uint16_t)b[i]); + if (got[i] != want) return i + 1; + } + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_umlal", triple, ll, mainC, nil) +} + +func TestARM64RawUMLALDecoderRejectsAdjacentEncodings(t *testing.T) { + for _, word := range []uint32{0x0e228020, 0x2e22a020} { // SMLAL, UMLSL. + t.Run(fmt.Sprintf("%#08x", word), func(t *testing.T) { + if _, ok := decodeARM64RawUMLAL(word); ok { + t.Fatalf("UMLAL decoder claimed adjacent encoding %#08x", word) + } + }) + } +} diff --git a/arm64_lower_word_umull.go b/arm64_lower_word_umull.go new file mode 100644 index 00000000..5ac000fa --- /dev/null +++ b/arm64_lower_word_umull.go @@ -0,0 +1,85 @@ +package plan9asm + +import "fmt" + +type arm64RawUMULL struct { + byElement bool + highHalf bool + source arm64VectorArrangement + destination arm64VectorArrangement + destReg int + first int + second int + element int +} + +func decodeARM64RawUMULL(word uint32) (arm64RawUMULL, bool) { + form := arm64RawUMULL{element: -1, highHalf: word&(1<<30) != 0} + switch { + case word&0xbf20fc00 == 0x2e20c000: // vector, three registers + case word&0xbf00f400 == 0x2f00a000: // vector, by element + form.byElement = true + default: + return arm64RawUMULL{}, false + } + size := int(word>>22) & 3 + if size > 2 || form.byElement && size == 0 { + return arm64RawUMULL{}, false + } + sourceBits := 8 << size + destLanes := 128 / (sourceBits * 2) + sourceLanes := destLanes + if form.highHalf { + sourceLanes *= 2 + } + form.source = arm64VectorArrangement{elementBits: sourceBits, lanes: sourceLanes} + form.destination = arm64VectorArrangement{elementBits: sourceBits * 2, lanes: destLanes} + form.destReg = int(word & 31) + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + if form.byElement { + form.second &= 15 + l := int(word>>21) & 1 + m := int(word>>20) & 1 + h := int(word>>11) & 1 + if sourceBits == 16 { + form.element = h<<2 | l<<1 | m + } else { + form.second |= m << 4 + form.element = h<<1 | l + } + } + return form, true +} + +func (c *arm64Ctx) lowerRawUMULL(form arm64RawUMULL) error { + first, err := c.loadRawARM64VectorOperand(form.first, form.source, 0, false) + if err != nil { + return err + } + if form.highHalf { + first = c.selectARM64VectorHighHalf(form.source, form.destination.lanes, first) + } + selected := arm64VectorArrangement{elementBits: form.source.elementBits, lanes: form.destination.lanes} + var second string + if form.byElement { + second, err = c.loadRawARM64VectorOperand(form.second, selected, form.element, true) + } else { + second, err = c.loadRawARM64VectorOperand(form.second, form.source, 0, false) + if err == nil && form.highHalf { + second = c.selectARM64VectorHighHalf(form.source, form.destination.lanes, second) + } + } + if err != nil { + return err + } + narrowType := fmt.Sprintf("<%d x i%d>", selected.lanes, selected.elementBits) + wideType := fmt.Sprintf("<%d x i%d>", form.destination.lanes, form.destination.elementBits) + wideFirst := c.newTmp() + wideSecond := c.newTmp() + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", wideFirst, narrowType, first, wideType) + fmt.Fprintf(c.b, " %%%s = zext %s %s to %s\n", wideSecond, narrowType, second, wideType) + fmt.Fprintf(c.b, " %%%s = mul %s %%%s, %%%s\n", product, wideType, wideFirst, wideSecond) + return c.storeRawARM64VectorResult(form.destReg, form.destination, "%"+product, false) +} diff --git a/arm64_lower_word_umull_test.go b/arm64_lower_word_umull_test.go new file mode 100644 index 00000000..8a3d0159 --- /dev/null +++ b/arm64_lower_word_umull_test.go @@ -0,0 +1,121 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawUMULLForms = ` +TEXT rawumullforms(SB),$0-0 + WORD $0x2e22c020 // UMULL V0.8H, V1.8B, V2.8B + WORD $0x6e25c083 // UMULL2 V3.8H, V4.16B, V5.16B + WORD $0x2e68c0e6 // UMULL V6.4S, V7.4H, V8.4H + WORD $0x6e6bc149 // UMULL2 V9.4S, V10.8H, V11.8H + WORD $0x2eaec1ac // UMULL V12.2D, V13.2S, V14.2S + WORD $0x6eb1c20f // UMULL2 V15.2D, V16.4S, V17.4S + WORD $0x2f74aa72 // UMULL V18.4S, V19.4H, V4.H[7] + WORD $0x6f75aab4 // UMULL2 V20.4S, V21.8H, V5.H[7] + WORD $0x2fb8aaf6 // UMULL V22.2D, V23.2S, V24.S[3] + WORD $0x6fbbab59 // UMULL2 V25.2D, V26.4S, V27.S[3] + RET +` + +func TestTranslateARM64RawUMULLCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawUMULLForms, true) + file, err := Parse(ArchARM64, arm64RawUMULLForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawumullforms": {Name: "rawumullforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "zext <8 x i8>", "zext <4 x i16>", "zext <2 x i32>", + "mul <8 x i16>", "mul <4 x i32>", "mul <2 x i64>", + "extractelement <8 x i16>", "extractelement <4 x i32>", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw UMULL lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-umull.ll", "arm64-raw-umull.o", ll) + }) + } +} + +func TestARM64RawUMULLRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawumull(SB),$0-24 + MOVD a+0(FP), R0 + MOVD b+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V1.S4] + WORD $0x2ea1c01e // UMULL V30.2D, V0.2S, V1.2S + WORD $0x6ea1c01f // UMULL2 V31.2D, V0.4S, V1.4S + VST1 [V30.D2, V31.D2], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawumull": { + Name: "rawumull", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawumull(const uint32_t *, const uint32_t *, uint64_t *); +int main(void) { + const uint32_t a[4] = {0xffffffffu, 2, 3, 0x80000000u}; + const uint32_t b[4] = {2, 0xffffffffu, 7, 2}; + uint64_t got[4] = {0}; + const uint64_t want[4] = {UINT64_C(0x1fffffffe), UINT64_C(0x1fffffffe), 21, UINT64_C(0x100000000)}; + rawumull(a, b, got); + for (int i = 0; i < 4; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_umull", triple, ll, mainC, nil) +} + +func TestARM64RawUMULLDecoderRejectsAdjacentSMULLEncoding(t *testing.T) { + if _, ok := decodeARM64RawUMULL(0x0e22c020); ok { + t.Fatal("UMULL decoder claimed adjacent SMULL encoding") + } +} diff --git a/arm64_lower_word_ushll.go b/arm64_lower_word_ushll.go new file mode 100644 index 00000000..fd46a380 --- /dev/null +++ b/arm64_lower_word_ushll.go @@ -0,0 +1,66 @@ +package plan9asm + +import "fmt" + +type arm64RawUSHLL struct { + highHalf bool + shift int + sourceArrangement arm64VectorArrangement + destinationArrangement arm64VectorArrangement + source int + destination int +} + +func decodeARM64RawUSHLL(word uint32) (arm64RawUSHLL, bool) { + if word&0xbf80fc00 != 0x2f00a400 { + return arm64RawUSHLL{}, false + } + encodedImmediate := int(word>>16) & 0x7f + bits := 0 + switch { + case encodedImmediate >= 32 && encodedImmediate < 64: + bits = 32 + case encodedImmediate >= 16: + bits = 16 + case encodedImmediate >= 8: + bits = 8 + default: + return arm64RawUSHLL{}, false + } + shift := encodedImmediate - bits + destinationLanes := 128 / (bits * 2) + highHalf := word&(1<<30) != 0 + sourceLanes := destinationLanes + if highHalf { + sourceLanes *= 2 + } + return arm64RawUSHLL{ + highHalf: highHalf, + shift: shift, + sourceArrangement: arm64VectorArrangement{elementBits: bits, lanes: sourceLanes}, + destinationArrangement: arm64VectorArrangement{elementBits: bits * 2, lanes: destinationLanes}, + source: int(word>>5) & 31, + destination: int(word & 31), + }, true +} + +func (c *arm64Ctx) lowerRawUSHLL(form arm64RawUSHLL) error { + op := Op("VUSHLL") + if form.highHalf { + op = "VUSHLL2" + } + ins := Instr{ + Op: op, + Raw: fmt.Sprintf("decoded ARM64 WORD as %s", op), + Args: []Operand{ + {Kind: OpImm, Imm: int64(form.shift)}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.source, arm64VectorArrangementName(form.sourceArrangement)))}, + {Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", form.destination, arm64VectorArrangementName(form.destinationArrangement)))}, + }, + } + ok, _, err := c.lowerARM64WideningShift(op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", op) + } + return err +} diff --git a/arm64_lower_word_ushll_test.go b/arm64_lower_word_ushll_test.go new file mode 100644 index 00000000..c50ba3f3 --- /dev/null +++ b/arm64_lower_word_ushll_test.go @@ -0,0 +1,131 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawUSHLLForms = ` +TEXT rawushllforms(SB),$0-0 + WORD $0x2f08a420 // USHLL V0.8H, V1.8B, #0 + WORD $0x2f0fa462 // USHLL V2.8H, V3.8B, #7 + WORD $0x2f10a4a4 // USHLL V4.4S, V5.4H, #0 + WORD $0x2f1fa4e6 // USHLL V6.4S, V7.4H, #15 + WORD $0x2f20a528 // USHLL V8.2D, V9.2S, #0 + WORD $0x2f3fa56a // USHLL V10.2D, V11.2S, #31 + WORD $0x6f08a5ac // USHLL2 V12.8H, V13.16B, #0 + WORD $0x6f0fa5ee // USHLL2 V14.8H, V15.16B, #7 + WORD $0x6f10a630 // USHLL2 V16.4S, V17.8H, #0 + WORD $0x6f1fa672 // USHLL2 V18.4S, V19.8H, #15 + WORD $0x6f20a6b4 // USHLL2 V20.2D, V21.4S, #0 + WORD $0x6f3fa6f6 // USHLL2 V22.2D, V23.4S, #31 + RET +` + +func TestTranslateARM64RawUSHLLCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawUSHLLForms, true) + file, err := Parse(ArchARM64, arm64RawUSHLLForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawushllforms": {Name: "rawushllforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"zext <8 x i8>", "zext <4 x i16>", "zext <2 x i32>", "shl <8 x i16>", "shl <4 x i32>", "shl <2 x i64>"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 raw USHLL lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-ushll.ll", "arm64-raw-ushll.o", ll) + }) + } +} + +func TestARM64RawUSHLLDecoderCoversEveryImmediate(t *testing.T) { + for _, highHalf := range []bool{false, true} { + for _, bits := range []int{8, 16, 32} { + for shift := 0; shift < bits; shift++ { + word := uint32(0x2f00a400) | uint32(bits+shift)<<16 + if highHalf { + word |= 1 << 30 + } + form, ok := decodeARM64RawUSHLL(word) + if !ok || form.sourceArrangement.elementBits != bits || form.shift != shift || form.highHalf != highHalf { + t.Fatalf("decode USHLL high=%v bits=%d shift=%d: form=%#v ok=%v", highHalf, bits, shift, form, ok) + } + } + } + } +} + +func TestARM64RawUSHLLRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawushll(SB),$0-16 + MOVD in+0(FP), R0 + MOVD out+8(FP), R1 + VLD1 (R0), [V11.S2] + WORD $0x2f38a57e // USHLL V30.2D, V11.2S, #24 + VST1 [V30.D2], (R1) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawushll": { + Name: "rawushll", Args: []LLVMType{Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawushll(const uint32_t *, uint64_t *); +int main(void) { + const uint32_t in[2] = {0xffffffffu, 0x12345678u}; + const uint64_t want[2] = {0x00ffffffff000000ull, 0x0012345678000000ull}; + uint64_t got[2] = {0}; + rawushll(in, got); + for (int i = 0; i < 2; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_ushll", triple, ll, mainC, nil) +} + +func TestARM64RawUSHLLDecoderRejectsAdjacentSSHLL(t *testing.T) { + if _, ok := decodeARM64RawUSHLL(0x0f08a420); ok { + t.Fatal("USHLL decoder claimed adjacent SSHLL encoding") + } +} diff --git a/arm64_lower_word_usubl_test.go b/arm64_lower_word_usubl_test.go new file mode 100644 index 00000000..80389dc5 --- /dev/null +++ b/arm64_lower_word_usubl_test.go @@ -0,0 +1,34 @@ +package plan9asm + +import "testing" + +const arm64RawVUSUBLForms = `TEXT vusublwords(SB),$0-0 + WORD $0x2E302094 // USUBL V20.8H, V4.8B, V16.8B + WORD $0x6E302098 // USUBL2 V24.8H, V4.16B, V16.16B + WORD $0x2E602000 // USUBL V0.4S, V0.4H, V0.4H + WORD $0x6E602000 // USUBL2 V0.4S, V0.8H, V0.8H + WORD $0x2EA02000 // USUBL V0.2D, V0.2S, V0.2S + WORD $0x6EA02000 // USUBL2 V0.2D, V0.4S, V0.4S + RET +` + +func TestTranslateARM64RawVUSUBLForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawVUSUBLForms, true) + file, err := Parse(ArchARM64, arm64RawVUSUBLForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{Goarch: "arm64", TargetTriple: triple, Sigs: map[string]FuncSig{"vusublwords": {Name: "vusublwords", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vusubl.ll", "arm64-vusubl.o", ir) + }) + } +} diff --git a/arm64_lower_word_uzp.go b/arm64_lower_word_uzp.go new file mode 100644 index 00000000..2e9acdbe --- /dev/null +++ b/arm64_lower_word_uzp.go @@ -0,0 +1,60 @@ +package plan9asm + +import "fmt" + +type arm64RawUZP struct { + op Op + arrangement arm64VectorArrangement + destination int + first int + second int +} + +func decodeARM64RawUZP(word uint32) (arm64RawUZP, bool) { + form := arm64RawUZP{} + switch word & 0xbf20fc00 { + case 0x0e001800: + form.op = "VUZP1" + case 0x0e005800: + form.op = "VUZP2" + default: + return arm64RawUZP{}, false + } + size := int(word>>22) & 3 + vectorBits := 64 + if word&(1<<30) != 0 { + vectorBits = 128 + } + if size == 3 && vectorBits != 128 { + return arm64RawUZP{}, false + } + bits := 8 << size + form.arrangement = arm64VectorArrangement{elementBits: bits, lanes: vectorBits / bits} + form.destination = int(word & 31) + form.first = int(word>>5) & 31 + form.second = int(word>>16) & 31 + return form, true +} + +func (c *arm64Ctx) lowerRawUZP(form arm64RawUZP) error { + arrangement := arm64VectorArrangementName(form.arrangement) + reg := func(index int) Operand { + return Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("V%d.%s", index, arrangement))} + } + // The existing Plan 9 lowerer takes Vm, Vn, Vd; raw encoding fields are + // named according to the architectural Vd, Vn, Vm order. + ins := Instr{ + Op: form.op, + Raw: fmt.Sprintf("decoded ARM64 WORD as %s", form.op), + Args: []Operand{ + reg(form.second), + reg(form.first), + reg(form.destination), + }, + } + ok, _, err := c.lowerARM64VectorPermute(form.op, ins) + if !ok && err == nil { + return fmt.Errorf("arm64 raw %s decoder reached no semantic lowerer", form.op) + } + return err +} diff --git a/arm64_lower_word_uzp_test.go b/arm64_lower_word_uzp_test.go new file mode 100644 index 00000000..f0f9a037 --- /dev/null +++ b/arm64_lower_word_uzp_test.go @@ -0,0 +1,124 @@ +//go:build !llgo + +package plan9asm + +import ( + "runtime" + "strings" + "testing" +) + +const arm64RawUZPForms = ` +TEXT rawuzpforms(SB),$0-0 + WORD $0x0e021820 // UZP1 V0.8B, V1.8B, V2.8B + WORD $0x4e051883 // UZP1 V3.16B, V4.16B, V5.16B + WORD $0x0e4818e6 // UZP1 V6.4H, V7.4H, V8.4H + WORD $0x4e4b1949 // UZP1 V9.8H, V10.8H, V11.8H + WORD $0x0e8e19ac // UZP1 V12.2S, V13.2S, V14.2S + WORD $0x4e911a0f // UZP1 V15.4S, V16.4S, V17.4S + WORD $0x4ed41a72 // UZP1 V18.2D, V19.2D, V20.2D + WORD $0x0e025820 // UZP2 V0.8B, V1.8B, V2.8B + WORD $0x4e055883 // UZP2 V3.16B, V4.16B, V5.16B + WORD $0x0e4858e6 // UZP2 V6.4H, V7.4H, V8.4H + WORD $0x4e4b5949 // UZP2 V9.8H, V10.8H, V11.8H + WORD $0x0e8e59ac // UZP2 V12.2S, V13.2S, V14.2S + WORD $0x4e915a0f // UZP2 V15.4S, V16.4S, V17.4S + WORD $0x4ed45a72 // UZP2 V18.2D, V19.2D, V20.2D + RET +` + +func TestTranslateARM64RawUZPCompleteAdvancedSIMDFormats(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawUZPForms, true) + file, err := Parse(ArchARM64, arm64RawUZPForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{"rawuzpforms": {Name: "rawuzpforms", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if got := strings.Count(ll, "shufflevector"); got < 14 { + t.Fatalf("raw UZP shuffle count = %d, want at least 14:\n%s", got, ll) + } + for _, want := range []string{"i32 0, i32 2", "i32 1, i32 3"} { + if !strings.Contains(ll, want) { + t.Fatalf("raw UZP forms omitted %q mask:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-uzp.ll", "arm64-raw-uzp.o", ll) + }) + } +} + +func TestARM64RawUZPRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = ` +TEXT rawuzp(SB),$0-24 + MOVD n+0(FP), R0 + MOVD m+8(FP), R1 + MOVD out+16(FP), R2 + VLD1 (R0), [V0.S4] + VLD1 (R1), [V1.S4] + WORD $0x4e811802 // UZP1 V2.4S, V0.4S, V1.4S + WORD $0x4e815803 // UZP2 V3.4S, V0.4S, V1.4S + VST1 [V2.S4, V3.S4], (R2) + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawuzp": { + Name: "rawuzp", Args: []LLVMType{Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + }}, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +extern void rawuzp(const uint32_t *, const uint32_t *, uint32_t *); +int main(void) { + const uint32_t n[4] = {0, 1, 2, 3}; + const uint32_t m[4] = {10, 11, 12, 13}; + const uint32_t want[8] = {0, 2, 10, 12, 1, 3, 11, 13}; + uint32_t got[8] = {0}; + rawuzp(n, m, got); + for (int i = 0; i < 8; i++) if (got[i] != want[i]) return i + 1; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_uzp", triple, ll, mainC, nil) +} + +func TestARM64RawUZPDecoderRejectsAdjacentZIPEncoding(t *testing.T) { + if _, ok := decodeARM64RawUZP(0x4e813802); ok { + t.Fatal("UZP decoder claimed adjacent ZIP encoding") + } +} diff --git a/arm64_lower_word_vnot_test.go b/arm64_lower_word_vnot_test.go new file mode 100644 index 00000000..6a648299 --- /dev/null +++ b/arm64_lower_word_vnot_test.go @@ -0,0 +1,30 @@ +package plan9asm + +import "testing" + +const arm64RawVMVNForms = `TEXT vmvnraw(SB),$0-0 + WORD $0x2E2058E5 // VMVN V7.B8, V5.B8 + WORD $0x6E205A7E // VMVN V19.B16, V30.B16 + RET +` + +func TestTranslateARM64RawVMVNGoAliasForms(t *testing.T) { + requireARM64GoAssemblerResult(t, arm64RawVMVNForms, true) + file, err := Parse(ArchARM64, arm64RawVMVNForms) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{Goarch: "arm64", TargetTriple: triple, Sigs: map[string]FuncSig{"vmvnraw": {Name: "vmvnraw", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-vnot.ll", "arm64-vnot.o", ir) + }) + } +} diff --git a/arm64_lower_word_vrshrn_test.go b/arm64_lower_word_vrshrn_test.go new file mode 100644 index 00000000..38cb2d91 --- /dev/null +++ b/arm64_lower_word_vrshrn_test.go @@ -0,0 +1,88 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64RawVRSHRNCompleteAdvancedSIMDFormats(t *testing.T) { + // x/arch prints the architectural RSHRN/RSHRN2 encodings in Go syntax as + // VRSHRN/VRSHRN2. Go 1.27's assembler table exposes VSHRN/VSHRN2 (the + // non-rounding form), so these are deliberately exercised through WORD. + const source = `TEXT ·rawVRSHRNForms(SB), $0-0 + WORD $0x0F0B8C01 // VRSHRN $5, V0.H8, V1.B8 + WORD $0x0F118C44 // VRSHRN $15, V2.S4, V4.H4 + WORD $0x0F218C57 // VRSHRN $31, V2.D2, V23.S2 + WORD $0x4F088C63 // VRSHRN2 $8, V3.H8, V3.B16 + WORD $0x4F148C85 // VRSHRN2 $12, V4.S4, V5.H8 + WORD $0x4F2C8CA6 // VRSHRN2 $20, V5.D2, V6.S4 + RET +` + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "rawVRSHRNForms": {Name: "rawVRSHRNForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{"ashr <", "add <", "trunc <", "insertelement <"} { + if !strings.Contains(ll, want) { + t.Fatalf("%s VRSHRN IR omitted %q:\n%s", triple, want, ll) + } + } + compileLLVMToObject(t, llc, triple, "arm64-raw-vrshrn.ll", "arm64-raw-vrshrn.o", ll) + } +} + +func TestARM64RawVRSHRNDecoderCoversEveryGoNarrowingFormat(t *testing.T) { + // The raw decoder must retain all register fields and every immediate in + // the same H8->B8, S4->H4, and D2->S2 rows used by Go's AVSHRN optab. + for _, highHalf := range []bool{false, true} { + for _, destinationBits := range []int{8, 16, 32} { + for shift := 1; shift <= destinationBits; shift++ { + encodedImmediate := uint32(2*destinationBits - shift) + for source := 0; source < 32; source++ { + for destination := 0; destination < 32; destination++ { + word := uint32(0x0f008c00) | encodedImmediate<<16 | uint32(source<<5|destination) + if highHalf { + word |= 1 << 30 + } + decoded, err := decodeARM64RawWordInstruction(Instr{ + Op: OpWORD, + Args: []Operand{{Kind: OpImm, Imm: int64(word)}}, + }) + if err != nil { + t.Fatalf("decode VRSHRN high=%v destinationBits=%d shift=%d source=%d destination=%d word=%#08x: %v", highHalf, destinationBits, shift, source, destination, word, err) + } + wantOp := Op("VRSHRN") + if highHalf { + wantOp = "VRSHRN2" + } + if decoded.Op != wantOp || len(decoded.Args) != 3 || decoded.Args[0].Kind != OpImm || decoded.Args[0].Imm != int64(shift) { + t.Fatalf("decode VRSHRN high=%v destinationBits=%d shift=%d source=%d destination=%d: %#v", highHalf, destinationBits, shift, source, destination, decoded) + } + } + } + } + } + } +} diff --git a/arm64_needed.go b/arm64_needed.go index 29da2fe5..91b1100a 100644 --- a/arm64_needed.go +++ b/arm64_needed.go @@ -20,7 +20,7 @@ func funcNeedsARM64CFG(fn Func) bool { } switch Op(op) { // Keep the linear path only for the tiny subset it can currently lower. - case OpTEXT, OpBYTE, OpMRS: + case OpTEXT, OpMRS: continue case OpRET: if len(ins.Args) != 0 { diff --git a/arm64_new_opfamilies_test.go b/arm64_new_opfamilies_test.go index 17f5228f..d37dee9b 100644 --- a/arm64_new_opfamilies_test.go +++ b/arm64_new_opfamilies_test.go @@ -4,10 +4,454 @@ package plan9asm import ( + "fmt" "strings" "testing" ) +func TestTranslateARM64ScalarSquareRootFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 maps both scalar square-root opcodes to the AFCVTSD optab: + // exactly one F-register source and one F-register destination. + src := ` +TEXT scalarsquarerootforms(SB),NOSPLIT,$0-0 + FSQRTS F0, F9 + FSQRTD F14, F27 + RET +` + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "scalarsquarerootforms": {Name: "scalarsquarerootforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, intrinsic := range []string{"@llvm.sqrt.f32", "@llvm.sqrt.f64"} { + if !strings.Contains(ll, intrinsic) { + t.Fatalf("scalar square-root lowering omitted %s:\n%s", intrinsic, ll) + } + } +} + +func TestTranslateARM64ScalarSquareRootFamilyRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "FSQRTS F0", + "FSQRTD F0, F1, F2", + "FSQRTS R0, F1", + "FSQRTD F0, R1", + "FSQRTS.P F0, F1", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidscalarsquareroot(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "invalidscalarsquareroot": {Name: "invalidscalarsquareroot", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's AFCVTSD optab", instruction) + } + }) + } +} + +func TestTranslateARM64ScalarPrecisionConversionCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 maps all six scalar precision conversions to AFCVTSD's single + // C_FREG -> C_FREG optab row; mnemonic letters specify source then result. + src := ` +TEXT scalarprecisionconversionforms(SB),$0-0 + FCVTSD F0, F31 + FCVTDS F30, F1 + FCVTSH F2, F29 + FCVTHS F28, F3 + FCVTDH F4, F27 + FCVTHD F26, F5 + RET +` + requireARM64GoAssemblerResult(t, src, true) + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "scalarprecisionconversionforms": {Name: "scalarprecisionconversionforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "fpext float", "fptrunc double", + "fptrunc float", "to half", "fpext half", "to float", + "fptrunc double", "to half", "fpext half", "to double", + } { + if !strings.Contains(ll, want) { + t.Fatalf("scalar precision conversion for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "scalar-precision-conversion.ll", "scalar-precision-conversion.o", ll) + } +} + +func TestTranslateARM64ScalarPrecisionConversionRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "FCVTSD F0", + "FCVTDS F0, F1, F2", + "FCVTSH F0", + "FCVTHS F0, F1, F2", + "FCVTDH R0, F1", + "FCVTHD F0, R1", + "FCVTSD R0, F1", + "FCVTDS F0, R1", + "FCVTSD.P F0, F1", + } { + src := "TEXT invalidscalarprecisionconversion(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "invalidscalarprecisionconversion": {Name: "invalidscalarprecisionconversion", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's scalar precision-conversion optab", instruction) + } + } +} + +func TestTranslateARM64IntegerToScalarFloatFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 maps these eight opcodes to ASCVTFD's single C_ZREG->C_FREG + // row. The W spellings consume the low i32; the others consume i64. + src := ` +TEXT integerfloatforms(SB),NOSPLIT,$0-0 + SCVTFD R0, F0 + SCVTFS R1, F1 + SCVTFWD R2, F2 + SCVTFWS R3, F3 + UCVTFD R4, F4 + UCVTFS R5, F5 + UCVTFWD R6, F6 + UCVTFWS ZR, F7 + RET +` + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "integerfloatforms": {Name: "integerfloatforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sitofp i64", "sitofp i32", "uitofp i64", "uitofp i32", "to float", "to double"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 integer-to-float family IR omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + triple string + }{ + {"darwin", "arm64-apple-macosx"}, + {"linux", "aarch64-unknown-linux-gnu"}, + {"windows", "aarch64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "integerfloatforms": {Name: "integerfloatforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "integer-float-forms.ll", "integer-float-forms.o", ir) + }) + } +} + +func TestTranslateARM64IntegerToScalarFloatFamilyRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "SCVTFS F0, F1", + "SCVTFD (R0), F1", + "SCVTFWS R0, R1", + "UCVTFS RSP, F0", + "UCVTFD R0, F1, F2", + "UCVTFWS.P R0, F1", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + file, err := Parse(ArchARM64, "TEXT invalidintegerfloat(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "invalidintegerfloat": {Name: "invalidintegerfloat", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ASCVTFD optab family", instruction) + } + }) + } +} + +func TestTranslateARM64ScalarFloatBinaryFamilyCompleteGoAssemblerForms(t *testing.T) { + // All eighteen opcodes share AFADDS's two C_FREG optab rows. Exercise both + // destructive two-register and explicit three-register forms for each one. + ops := []string{ + "FADDS", "FADDD", "FSUBS", "FSUBD", "FMULS", "FMULD", + "FNMULS", "FNMULD", "FDIVS", "FDIVD", + "FMAXS", "FMAXD", "FMINS", "FMIND", + "FMAXNMS", "FMAXNMD", "FMINNMS", "FMINNMD", + } + var src strings.Builder + src.WriteString("TEXT scalarfloatbinaryforms(SB),NOSPLIT,$0-0\n") + for _, op := range ops { + fmt.Fprintf(&src, "\t%s F0, F1\n", op) + fmt.Fprintf(&src, "\t%s F2, F3, F4\n", op) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchARM64, src.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "scalarfloatbinaryforms": {Name: "scalarfloatbinaryforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "fadd float", "fadd double", "fsub float", "fmul float", "fneg float", "fdiv float", + "@llvm.maximum.f32", "@llvm.minimum.f64", "@llvm.maxnum.f32", "@llvm.minnum.f64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM64 scalar binary floating family IR omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + for _, target := range []struct { + name string + triple string + }{ + {"darwin", "arm64-apple-macosx"}, + {"linux", "aarch64-unknown-linux-gnu"}, + {"windows", "aarch64-pc-windows-msvc"}, + } { + t.Run(target.name, func(t *testing.T) { + file, err := Parse(ArchARM64, src.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: target.triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "scalarfloatbinaryforms": {Name: "scalarfloatbinaryforms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, target.triple, "scalar-float-binary-forms.ll", "scalar-float-binary-forms.o", ir) + }) + } +} + +func TestTranslateARM64ScalarFloatBinaryFamilyRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{ + "FMULS F0", + "FMULD F0, F1, F2, F3", + "FMAXS R0, F1", + "FMIND F0, R1", + "FMAXNMS $1, F0", + "FMINNMD (R0), F1", + "FNMULS.P F0, F1", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + file, err := Parse(ArchARM64, "TEXT invalidfloatbinary(SB),NOSPLIT,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "invalidfloatbinary": {Name: "invalidfloatbinary", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's AFADDS optab family", instruction) + } + }) + } +} + +func TestTranslateARM64ScalarFloatMoveFamilyCompleteGoAssemblerForms(t *testing.T) { + // Go 1.27 gives FMOVS and FMOVD the same complete shape family: floating + // constant, F<->F, R/ZR<->F, and F<->memory through stack, symbol, + // immediate-offset, register-offset, post-index, and pre-index addresses. + src := ` +TEXT scalarfloatmoveforms(SB),NOSPLIT,$0-32 + FMOVS $(4.0), F0 + FMOVS F0, F1 + FMOVS R2, F2 + FMOVS ZR, F3 + FMOVS F2, R3 + FMOVS F3, ZR + FMOVS (R4), F4 + FMOVS F4, 4(R4) + FMOVS scalar(SB), F5 + FMOVS F5, scalar(SB) + FMOVS input32+0(FP), F6 + FMOVS F6, result32+16(FP) + FMOVS.P 4(R7), F7 + FMOVS.P F7, 4(R7) + FMOVS.W 4(R8), F8 + FMOVS.W F8, 4(R8) + FMOVS (R9)(R10), F9 + FMOVS F9, (R9)(R10<<2) + FMOVD $(28.0), F10 + FMOVD F10, F11 + FMOVD R12, F12 + FMOVD ZR, F13 + FMOVD F12, R13 + FMOVD F13, ZR + FMOVD (R14), F14 + FMOVD F14, 8(R14) + FMOVD scalar(SB), F15 + FMOVD F15, scalar(SB) + FMOVD input64+8(FP), F16 + FMOVD F16, result64+24(FP) + FMOVD.P 8(R17), F17 + FMOVD.P F17, 8(R17) + FMOVD.W 8(R18), F18 + FMOVD.W F18, 8(R18) + FMOVD (R19)(R20), F19 + FMOVD F19, (R19)(R20<<3) + RET +` + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + ResolveSym: func(sym string) string { return strings.TrimPrefix(sym, "·") }, + Sigs: map[string]FuncSig{ + "scalarfloatmoveforms": { + Name: "scalarfloatmoveforms", + Args: []LLVMType{LLVMType("float"), LLVMType("double")}, + Ret: LLVMType("{ float, double }"), + Frame: FrameLayout{ + Params: []FrameSlot{ + {Offset: 0, Type: LLVMType("float"), Index: 0, Field: -1}, + {Offset: 8, Type: LLVMType("double"), Index: 1, Field: -1}, + }, + Results: []FrameSlot{ + {Offset: 16, Type: LLVMType("float"), Index: 0, Field: -1}, + {Offset: 24, Type: LLVMType("double"), Index: 1, Field: -1}, + }, + }, + }, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load i32", "store i32", "load i64", "store i64", "bitcast float", "bitcast double"} { + if !strings.Contains(ll, want) { + t.Fatalf("complete scalar float-move lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "aarch64-unknown-linux-gnu", "scalar-float-moves.ll", "scalar-float-moves.o", ll) +} + +func TestTranslateARM64ScalarFloatMoveFamilyRejectsFormsOutsideGoOptabs(t *testing.T) { + for _, instruction := range []string{ + "FMOVS F0", + "FMOVD F0, F1, F2", + "FMOVS (R0), R1", + "FMOVD R0, (R1)", + "FMOVS $(1.0), R1", + "FMOVD.P F0, F1", + "FMOVS.Z F0, F1", + "FMOVS (R0)(R1<<3), F0", + "FMOVD F0, (R0)(R1<<2)", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + src := "TEXT invalidscalarfloatmove(SB),NOSPLIT,$0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchARM64, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "invalidscalarfloatmove": {Name: "invalidscalarfloatmove", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate accepted %q, which is absent from Go 1.27's FMOVS/FMOVD optabs", instruction) + } + }) + } +} + func TestTranslateARM64BranchMinus(t *testing.T) { src := ` TEXT branchminus(SB),NOSPLIT,$0-0 diff --git a/arm64_official_directive_test.go b/arm64_official_directive_test.go new file mode 100644 index 00000000..3dc197e4 --- /dev/null +++ b/arm64_official_directive_test.go @@ -0,0 +1,37 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARM64OfficialNoopAndEnd(t *testing.T) { + const source = `TEXT officialNoopEnd(SB),$0-0 + NOOP + RET + END +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"officialNoopEnd": {Name: "officialNoopEnd", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ll, "hint #0") { + t.Fatalf("ARM64 NOOP did not retain its architectural hint encoding:\n%s", ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, arm64LinuxGNUTriple, "arm64-official-noop-end.ll", "arm64-official-noop-end.o", ll) +} diff --git a/arm64_privileged_probe_test.go b/arm64_privileged_probe_test.go new file mode 100644 index 00000000..e56736a8 --- /dev/null +++ b/arm64_privileged_probe_test.go @@ -0,0 +1,47 @@ +//go:build !llgo + +package plan9asm + +import ( + "errors" + "testing" +) + +func TestProbeARM64PrivilegedOfficialFormsRequireExecutionContext(t *testing.T) { + for _, instruction := range []string{ + "TLBI VMALLE1IS", + "TLBI VAE1IS, R0", + "TLBI VAE3IS, ZR", + "SYS $32768", + "SYS $32768, R1", + "SYSL $285440, R12", + "DCPS1 $11378", + "DCPS2 $10699", + "DCPS3 $24415", + "DRPS", + "ERET", + "HLT $65509", + "HVC $61428", + "SMC $37977", + } { + t.Run(instruction, func(t *testing.T) { + source := "TEXT privileged(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + probeErr := ProbeInstruction(ArchARM64, "arm64", file.Funcs[0].Instrs[1]) + if !errors.Is(probeErr, ErrProbeNeedsContext) { + t.Fatalf("ProbeInstruction(%q) error = %v, want ErrProbeNeedsContext", instruction, probeErr) + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"privileged": {Name: "privileged", Ret: Void}}, + }); err == nil { + t.Fatalf("full translation of privileged instruction %q must not report portable success", instruction) + } + }) + } +} diff --git a/arm64_probe_context_test.go b/arm64_probe_context_test.go new file mode 100644 index 00000000..76c5e741 --- /dev/null +++ b/arm64_probe_context_test.go @@ -0,0 +1,25 @@ +//go:build !llgo + +package plan9asm + +import ( + "errors" + "testing" +) + +func TestProbeARM64PCRelativeAddressRequiresFunctionContext(t *testing.T) { + file, err := Parse(ArchARM64, "TEXT probe(SB),$0-0\n\tADR target, R1\ntarget:\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if err := ProbeInstruction(ArchARM64, "arm64", file.Funcs[0].Instrs[1]); !errors.Is(err, ErrProbeNeedsContext) { + t.Fatalf("ProbeInstruction(ADR) error = %v, want ErrProbeNeedsContext", err) + } + if _, err := Translate(file, Options{ + TargetTriple: arm64LinuxGNUTriple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"probe": {Name: "probe", Ret: Void}}, + }); err != nil { + t.Fatalf("full-function ADR translation failed: %v", err) + } +} diff --git a/arm64_raw_decode.go b/arm64_raw_decode.go new file mode 100644 index 00000000..a6d222a1 --- /dev/null +++ b/arm64_raw_decode.go @@ -0,0 +1,139 @@ +package plan9asm + +import ( + "encoding/binary" + "fmt" + "strings" + + "golang.org/x/arch/arm64/arm64asm" +) + +// decodeARM64RawWordInstruction uses Go's architecture decoder to recover a +// Plan 9 instruction from a WORD that is not covered by a specialized decoder. +// The caller must run the returned instruction through the regular semantic +// lowerers; decoding by itself never counts as supported. +func decodeARM64RawWordInstruction(ins Instr) (Instr, error) { + return decodeARM64RawWordInstructionTarget(ins, "") +} + +// decodeARM64RawWordInstructionTarget decodes one raw instruction. When the +// instruction contains a PC-relative operand, target must be the exact source +// label established by normalizeARM64RawPCRelative. Keeping the layout proof +// out of this context-free decoder prevents guessed control-flow edges. +func decodeARM64RawWordInstructionTarget(ins Instr, target string) (Instr, error) { + if len(ins.Args) != 1 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return Instr{}, fmt.Errorf("arm64 WORD expects exactly one resolved integer constant: %q", ins.Raw) + } + word := uint32(ins.Args[0].Imm) + var code [4]byte + binary.LittleEndian.PutUint32(code[:], word) + decoded, err := arm64asm.Decode(code[:]) + if err != nil { + return Instr{}, fmt.Errorf("decode ARM64 WORD %#08x: %w", word, err) + } + pcRelative := 0 + for _, arg := range decoded.Args { + if arg == nil { + break + } + if _, ok := arg.(arm64asm.PCRel); ok { + pcRelative++ + } + } + if pcRelative != 0 && target == "" { + return Instr{}, fmt.Errorf("ARM64 WORD %#08x is PC-relative and cannot be mapped safely to source labels: %q", word, ins.Raw) + } + if pcRelative > 1 { + return Instr{}, fmt.Errorf("ARM64 WORD %#08x has %d PC-relative operands: %q", word, pcRelative, ins.Raw) + } + syntax := decodedARM64GoSyntax(decoded) + file, err := Parse(ArchARM64, "TEXT decoded(SB), $0-0\n"+syntax+"\n") + if err != nil { + return Instr{}, fmt.Errorf("parse decoded ARM64 WORD %#08x as %q: %w", word, syntax, err) + } + if len(file.Funcs) != 1 || len(file.Funcs[0].Instrs) != 2 { + return Instr{}, fmt.Errorf("decoded ARM64 WORD %#08x produced an invalid instruction sequence %q", word, syntax) + } + result := file.Funcs[0].Instrs[1] + if pcRelative != 0 { + replaced := 0 + for i := range result.Args { + if result.Args[i].Kind == OpMem && result.Args[i].Mem.Base == PC { + result.Args[i] = Operand{Kind: OpIdent, Ident: target} + replaced++ + } + } + if replaced != pcRelative { + return Instr{}, fmt.Errorf("decoded ARM64 WORD %#08x as %q but replaced %d/%d PC-relative operands", word, syntax, replaced, pcRelative) + } + } + result.Raw = fmt.Sprintf("%s /* decoded from %s */", result.Raw, ins.Raw) + return result, nil +} + +func decodedARM64GoSyntax(inst arm64asm.Inst) string { + syntax := arm64asm.GoSyntax(inst, 0, nil, nil) + op, rest, hasArgs := strings.Cut(syntax, " ") + if !hasArgs { + rest = "" + } + if op == "NOOP" { + return "NOP" + } + // x/arch v0.14 predates cmd/asm spellings for the unscaled signed-offset + // load aliases and prints names such as LDURBW. Canonicalize the complete + // integer family to the same MOV forms used for the corresponding LDR + // instructions so the regular width/sign-aware lowerers provide semantics. + switch inst.Op { + case arm64asm.MVN: + // x/arch calls the Advanced SIMD bitwise-not alias MVN and + // prints it as VMVN. Go's assembler names this form VNOT. + // Keep the scalar integer MVN spelling untouched. + if strings.HasPrefix(rest, "V") { + op = "VNOT" + } + case arm64asm.LDURB: + op = "MOVBU" + case arm64asm.LDURH: + op = "MOVHU" + case arm64asm.LDURSB: + op = "MOVB" + if arm64DecodedDestinationIsWord(inst) { + op = "MOVBW" + } + case arm64asm.LDURSH: + op = "MOVH" + if arm64DecodedDestinationIsWord(inst) { + op = "MOVHW" + } + case arm64asm.LDURSW: + op = "MOVW" + } + // x/arch v0.12 is the last decoder usable by this module's Go 1.20 + // baseline. Its Plan 9 printer omits the V prefix for these Advanced SIMD + // forms; the operand arrangement tells them apart from their scalar forms. + if strings.HasPrefix(rest, "V") { + switch op { + case "FABS", "FNEG", "FSQRT", "FRINTN", "FRINTP", "FRINTM", "FRINTZ", "FRINTA", "FRINTX", "FRINTI", + "FCVTZS", "FCVTZU", "SCVTF", "UCVTF", "FMAXV", "FMINV", "FMAXNMV", "FMINNMV": + op = "V" + op + } + } + // Go's named reduction syntax spells the scalar destination as a bare V + // register, while the architecture decoder prints the aliased F register. + // Canonicalize raw reductions through the exact named-form lowerer. + if op == "VFMAXV" || op == "VFMINV" || op == "VFMAXNMV" || op == "VFMINNMV" { + if separator := strings.LastIndex(rest, ", F"); separator >= 0 { + rest = rest[:separator] + ", V" + rest[separator+3:] + } + } + if rest == "" { + return op + } + return op + " " + rest +} + +func arm64DecodedDestinationIsWord(inst arm64asm.Inst) bool { + reg, ok := inst.Args[0].(arm64asm.Reg) + return ok && reg >= arm64asm.W0 && reg <= arm64asm.WZR +} diff --git a/arm64_raw_decode_test.go b/arm64_raw_decode_test.go new file mode 100644 index 00000000..301aec0b --- /dev/null +++ b/arm64_raw_decode_test.go @@ -0,0 +1,329 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +func TestARM64RawWordsUseOfficialDecoderAndSemanticLowering(t *testing.T) { + const source = `TEXT rawDecoded(SB), $0-0 + MOVD $9, R0 + MOVD $3, R16 + WORD $0x9ad00800 // UDIV R16, R0, R0 + WORD $0x2e211402 // VURHADD V1.B8, V0.B8, V2.B8 + WORD $0x4ee0f8e7 // VFABS V7.D2, V7.D2 + RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{ + Goarch: "arm64", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "rawDecoded": {Name: "rawDecoded", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("Translate() error = %v", err) + } + for _, want := range []string{"udiv i64", "lshr <8 x i16>", "@llvm.fabs.v2f64"} { + if !strings.Contains(ir, want) { + t.Fatalf("decoded semantics omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-decoded.ll", "arm64-raw-decoded.o", ir) + }) + } +} + +func TestARM64RawPCRelativeInstructionFailsClosed(t *testing.T) { + for _, test := range []struct { + name string + word uint32 + }{ + {name: "ADR without proven boundary", word: 0x100000a0}, + {name: "ADRP nonzero page delta", word: 0xb0000000}, + } { + t.Run(test.name, func(t *testing.T) { + source := "TEXT rawADR(SB), $0-0\n\tWORD $" + fmt.Sprintf("%#08x", test.word) + "\n\tRET\n" + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + _, err = Translate(file, Options{ + Goarch: "arm64", + TargetTriple: "aarch64-unknown-linux-gnu", + Sigs: map[string]FuncSig{ + "rawADR": {Name: "rawADR", Ret: Void}, + }, + }) + if err == nil || !strings.Contains(err.Error(), "PC-relative") { + t.Fatalf("Translate() error = %v, want explicit PC-relative raw-instruction rejection", err) + } + }) + } +} + +func TestARM64RawZeroPageADRPResolvesAtExactInstructionBoundary(t *testing.T) { + const source = `TEXT rawADRPPage(SB), $0-8 + WORD $0x90000000 // ADRP current page, R0 + MOVD R0, ret+0(FP) + RET +` + requireARM64GoAssemblerResult(t, source, true) + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "arm64", + TargetTriple: triple, + Sigs: map[string]FuncSig{"rawADRPPage": { + Name: "rawADRPPage", Ret: I64, + Frame: FrameLayout{Results: []FrameSlot{{Offset: 0, Type: I64, Index: 0, Field: -1}}}, + }}, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "blockaddress(@rawADRPPage") || !strings.Contains(ir, "and i64") || !strings.Contains(ir, ", -4096") { + t.Fatalf("zero-page ADRP semantics missing:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-zero-adrp.ll", "arm64-raw-zero-adrp.o", ir) + if triple != "aarch64-apple-darwin" || runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + return + } + clang := findLLVM22Tool("clang") + if clang == "" { + t.Fatal("LLVM 22 clang not found") + } + const mainC = ` +#include +extern uintptr_t rawADRPPage(void); +int main(void) { + uintptr_t got = rawADRPPage(); + uintptr_t want = ((uintptr_t)&rawADRPPage) & ~(uintptr_t)4095; + return got == want ? 0 : 1; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_zero_adrp", triple, ir, mainC, nil) + }) + } +} + +func TestARM64RawPCRelativeWordsResolveExactInstructionBoundaries(t *testing.T) { + const source = `TEXT rawPCRelative(SB), $16-0 + WORD $0x100000a0 // ADR +20, R0; crosses the framed RET expansion + MOVD R0, R1 + RET +target: + WORD $0x14000002 // B +8 + WORD $0x91000400 // ADD $1, R0, R0 +done: + WORD $0xd65f03c0 // RET +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + ir, err := Translate(file, Options{ + Goarch: "arm64", + TargetTriple: "aarch64-unknown-linux-gnu", + Sigs: map[string]FuncSig{ + "rawPCRelative": {Name: "rawPCRelative", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("Translate() error = %v", err) + } + for _, want := range []string{ + "blockaddress(@rawPCRelative, %target)", + "br label %done", + } { + if !strings.Contains(ir, want) { + t.Fatalf("raw PC-relative lowering omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "aarch64-unknown-linux-gnu", "arm64-raw-pcrel.ll", "arm64-raw-pcrel.o", ir) +} + +func TestARM64RawPCRelativeLayoutMatchesFramedEntryWrapper(t *testing.T) { + const source = `TEXT rawEntry(SB), $16 + NO_LOCAL_POINTERS + WORD $0x100000a0 + MOVD R0, ret(FP) + RET +rawBody: + WORD $0xd65f03c0 +` + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + if len(file.Funcs) != 1 { + t.Fatalf("Parse() funcs = %d, want 1", len(file.Funcs)) + } + if _, err := normalizeARM64RawPCRelative(file.Funcs[0]); err != nil { + for i, ins := range file.Funcs[0].Instrs { + t.Logf("instruction %d: op=%s args=%#v raw=%q", i, ins.Op, ins.Args, ins.Raw) + } + t.Fatalf("normalizeARM64RawPCRelative() error = %v", err) + } +} + +func TestARM64RawPCRelativeSeparatesEmbeddedCodeAndConstantPools(t *testing.T) { + const source = `TEXT rawEmbedded(SB), $16-0 + WORD $0x100000a0 // ADR +20, R0: entry wrapper returns embedded code + MOVD R0, R1 + RET +code: + WORD $0x10000042 // ADR +8, R2: embedded code addresses its constant pool + WORD $0xd65f03c0 // RET +data: + WORD $0x04030201 +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + ir, err := Translate(file, Options{ + Goarch: "arm64", + TargetTriple: "aarch64-unknown-linux-gnu", + Sigs: map[string]FuncSig{ + "rawEmbedded": {Name: "rawEmbedded", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("Translate() error = %v", err) + } + for _, want := range []string{ + `@rawEmbedded.data.raw_data = private constant [4 x i8] c"\01\02\03\04"`, + "blockaddress(@rawEmbedded, %code)", + "ptrtoint ptr @rawEmbedded.data.raw_data to i64", + } { + if !strings.Contains(ir, want) { + t.Fatalf("embedded raw-data lowering omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "aarch64-unknown-linux-gnu", "arm64-raw-data.ll", "arm64-raw-data.o", ir) +} + +func TestARM64RawPCRelativeCrossesCompleteFixedWidthJumpFamily(t *testing.T) { + for _, jump := range []string{ + "B branchTarget", + "JMP branchTarget", + "JMP 1(PC)", + "JMP (R11)", + "BL branchTarget", + "BL 1(PC)", + "BL R3", + "BL (R4)", + "BL global(SB)", + "CALL R5", + "CALL (R6)", + "CALL global(SB)", + } { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(jump), func(t *testing.T) { + source := "TEXT rawJumpFamily(SB), $0-0\n\tWORD $0x1000005e // ADR +8, R30\n\t" + jump + "\n\tMOVD R0, R0\nbranchTarget:\n\tRET\n" + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := normalizeARM64RawPCRelative(file.Funcs[0]); err != nil { + t.Fatalf("fixed-width %q broke raw PC-relative layout: %v", jump, err) + } + }) + } +} + +func TestARM64RawTrailingUnreferencedWordsBecomeDataAfterTerminator(t *testing.T) { + const source = `TEXT rawTrailingData(SB), $0-0 + WORD $0xd65f03c0 // RET +mask: + WORD $0x00000002 +` + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawTrailingData": {Name: "rawTrailingData", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, `@rawTrailingData.mask.raw_data = private constant [4 x i8] c"\02\00\00\00"`) { + t.Fatalf("trailing raw data was not separated from code:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "aarch64-unknown-linux-gnu", "arm64-raw-trailing-data.ll", "arm64-raw-trailing-data.o", ir) +} + +func TestARM64RawReachableInvalidWordDoesNotBecomeData(t *testing.T) { + const source = `TEXT rawReachableInvalid(SB), $0-0 + WORD $0xd503201f // NOP falls through +reachable: + WORD $0x00000002 + RET +` + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + _, err = Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawReachableInvalid": {Name: "rawReachableInvalid", Ret: Void}, + }, + }) + if err == nil || !strings.Contains(err.Error(), "unsupported ARM64 WORD encoding") { + t.Fatalf("reachable invalid WORD error = %v, want fail-closed rejection", err) + } +} diff --git a/arm64_raw_pc_relative.go b/arm64_raw_pc_relative.go new file mode 100644 index 00000000..175e735d --- /dev/null +++ b/arm64_raw_pc_relative.go @@ -0,0 +1,453 @@ +package plan9asm + +import ( + "encoding/binary" + "fmt" + "sort" + "strings" + + "golang.org/x/arch/arm64/arm64asm" +) + +type arm64RawLayoutPoint struct { + segment int + offset int64 +} + +type arm64RawDataBlob struct { + label string + bytes []byte +} + +const arm64RawDataOp Op = "ARM64_RAW_DATA" + +// normalizeARM64RawPCRelative replaces raw ARM64 PC-relative instructions +// with decoded instructions that name exact source labels. It deliberately +// models only source spans whose cmd/asm widths are known. An unknown-width +// pseudo instruction starts a new segment, so a raw displacement can never be +// guessed across it. +func normalizeARM64RawPCRelative(fn Func) (Func, error) { + result, _, err := prepareARM64RawPCRelative(fn) + return result, err +} + +func prepareARM64RawPCRelative(fn Func) (Func, []arm64RawDataBlob, error) { + points := make([]arm64RawLayoutPoint, len(fn.Instrs)) + boundaries := make(map[arm64RawLayoutPoint]int) + labels := make(map[arm64RawLayoutPoint]string) + labelIndices := make(map[string]int) + knownLabels := make(map[string]bool) + + segment := 0 + offset := int64(0) + for i, ins := range fn.Instrs { + point := arm64RawLayoutPoint{segment: segment, offset: offset} + points[i] = point + if ins.Op == OpLABEL && len(ins.Args) == 1 && ins.Args[0].Kind == OpLabel { + if _, exists := labels[point]; !exists { + labels[point] = ins.Args[0].Sym + } + knownLabels[ins.Args[0].Sym] = true + labelIndices[ins.Args[0].Sym] = i + continue + } + + width, known := arm64RawKnownSourceWidth(fn, ins) + if !known { + segment++ + offset = 0 + continue + } + if width != 0 { + if _, exists := boundaries[point]; !exists { + boundaries[point] = i + } + offset += width + } + } + end := arm64RawLayoutPoint{segment: segment, offset: offset} + if _, exists := boundaries[end]; !exists { + boundaries[end] = len(fn.Instrs) + } + + dataWords, dataBlobs, err := identifyARM64RawData(fn, points, boundaries, labels, labelIndices) + if err != nil { + return Func{}, nil, err + } + + replacements := make(map[int]Instr) + insertions := make(map[int]string) + for i, ins := range fn.Instrs { + if dataWords[i] { + continue + } + displacement, op, pcRelative, err := arm64RawPCRelativeDisplacement(ins) + if err != nil { + return Func{}, nil, err + } + if !pcRelative { + continue + } + switch op { + case "ADR", "B", "BL", "CBZ", "CBNZ", "TBZ", "TBNZ": + // These encodings define their displacement relative to the current + // instruction address. + case "ADRP": + // A zero displacement always denotes the page containing this exact + // instruction, independent of source layout and final link placement. + // Insert a boundary label at the instruction and let the ordinary ADRP + // lowerer page-align its blockaddress. Nonzero raw page deltas remain + // unsafe because source layout cannot prove their link-time target page. + if displacement != 0 { + return Func{}, nil, fmt.Errorf("ARM64 WORD PC-relative ADRP page delta %+d is not source-layout safe: %q", displacement, ins.Raw) + } + default: + return Func{}, nil, fmt.Errorf("ARM64 WORD PC-relative %s is not source-layout safe: %q", op, ins.Raw) + } + + targetPoint := arm64RawLayoutPoint{ + segment: points[i].segment, + offset: points[i].offset + displacement, + } + target, ok := labels[targetPoint] + if !ok { + at, boundaryOK := boundaries[targetPoint] + if !boundaryOK { + return Func{}, nil, fmt.Errorf("ARM64 WORD PC-relative %s target %+d does not land on a proven instruction boundary: %q", op, displacement, ins.Raw) + } + if existing, exists := insertions[at]; exists { + target = existing + } else { + target = arm64UniqueRawTargetLabel(knownLabels, targetPoint) + knownLabels[target] = true + insertions[at] = target + } + } + decoded, err := decodeARM64RawWordInstructionTarget(ins, target) + if err != nil { + return Func{}, nil, err + } + replacements[i] = decoded + } + + if len(replacements) == 0 && len(dataWords) == 0 { + return fn, dataBlobs, nil + } + result := fn + result.Instrs = make([]Instr, 0, len(fn.Instrs)+len(insertions)) + for i, ins := range fn.Instrs { + if label, ok := insertions[i]; ok { + result.Instrs = append(result.Instrs, Instr{ + Op: OpLABEL, + Args: []Operand{{Kind: OpLabel, Sym: label}}, + Raw: label + ":", + }) + } + if dataWords[i] { + ins.Op = arm64RawDataOp + } else if replacement, ok := replacements[i]; ok { + ins = replacement + } + result.Instrs = append(result.Instrs, ins) + } + if label, ok := insertions[len(fn.Instrs)]; ok { + result.Instrs = append(result.Instrs, Instr{ + Op: OpLABEL, + Args: []Operand{{Kind: OpLabel, Sym: label}}, + Raw: label + ":", + }) + } + return result, dataBlobs, nil +} + +// identifyARM64RawData recognizes generator-emitted local constant pools. The +// characteristic form is ADR label followed later by a label and one or more +// WORD directives. The one ADR before the first source RET is excluded: that +// is the generated entry wrapper returning a pointer to the embedded code. +func identifyARM64RawData(fn Func, points []arm64RawLayoutPoint, boundaries map[arm64RawLayoutPoint]int, labels map[arm64RawLayoutPoint]string, labelIndices map[string]int) (map[int]bool, []arm64RawDataBlob, error) { + firstReturn := len(fn.Instrs) + for i, ins := range fn.Instrs { + if ins.Op == OpRET { + firstReturn = i + break + } + } + + starts := make(map[int]string) + codeLabels := make(map[string]bool) + for i, ins := range fn.Instrs { + displacement, op, pcRelative, err := arm64RawPCRelativeDisplacement(ins) + if err != nil { + return nil, nil, err + } + if !pcRelative { + continue + } + targetPoint := arm64RawLayoutPoint{segment: points[i].segment, offset: points[i].offset + displacement} + label, hasLabel := labels[targetPoint] + targetIndex, hasBoundary := boundaries[targetPoint] + if !hasLabel || !hasBoundary { + continue + } + if op != "ADR" { + codeLabels[label] = true + continue + } + // Generated entry wrappers return a pointer to the embedded routine. + // That ADR appears before the first source RET and points beyond it. + if i < firstReturn && targetIndex > firstReturn { + codeLabels[label] = true + continue + } + starts[targetIndex] = label + } + // Preserve every explicitly referenced local label as code. Raw embedded + // routines use PC-relative encodings handled above; source-level wrappers + // may use ordinary Plan 9 branch operands. + for _, ins := range fn.Instrs { + if ins.Op == OpWORD || ins.Op == OpLABEL { + continue + } + for _, operand := range ins.Args { + var label string + switch operand.Kind { + case OpIdent: + label = operand.Ident + case OpSym: + label = strings.TrimSuffix(strings.TrimSuffix(operand.Sym, "(SB)"), "<>") + } + if _, exists := labelIndices[label]; exists { + codeLabels[label] = true + } + } + } + + // Some generators append unreferenced metadata words (for example a mask + // discriminator) immediately after an unconditional terminator and before + // ADR-addressed tables. Classify only all-WORD label regions that cannot be + // reached by control flow. Once such a region starts, adjacent all-WORD + // labels remain data. Reachable invalid WORDs therefore still fail closed. + type labelRegion struct { + label string + labelIndex int + start, end int + allRawWords bool + } + regions := make([]labelRegion, 0, len(labelIndices)) + for label, labelIndex := range labelIndices { + start := labelIndex + 1 + for start < len(fn.Instrs) && fn.Instrs[start].Op == OpLABEL { + start++ + } + end := len(fn.Instrs) + for i := start; i < len(fn.Instrs); i++ { + if fn.Instrs[i].Op == OpLABEL { + end = i + break + } + } + allRawWords := start < end + for i := start; i < end && allRawWords; i++ { + ins := fn.Instrs[i] + allRawWords = ins.Op == OpWORD && len(ins.Args) == 1 && ins.Args[0].Kind == OpImm && ins.Args[0].ImmRaw == "" + } + regions = append(regions, labelRegion{label: label, labelIndex: labelIndex, start: start, end: end, allRawWords: allRawWords}) + } + sort.Slice(regions, func(i, j int) bool { return regions[i].labelIndex < regions[j].labelIndex }) + previousDataEnd := -1 + for _, region := range regions { + if !region.allRawWords || codeLabels[region.label] { + previousDataEnd = -1 + continue + } + _, alreadyData := starts[region.start] + followsData := previousDataEnd == region.labelIndex + followsTerminator := false + for i := region.labelIndex - 1; i >= 0; i-- { + if fn.Instrs[i].Op == OpLABEL { + continue + } + followsTerminator = arm64RawIsNonFallthroughTerminator(fn.Instrs[i]) + break + } + if !alreadyData && !followsData && !followsTerminator { + previousDataEnd = -1 + continue + } + starts[region.start] = region.label + previousDataEnd = region.end + } + + dataWords := make(map[int]bool) + blobs := make([]arm64RawDataBlob, 0, len(starts)) + startIndices := make([]int, 0, len(starts)) + for start := range starts { + startIndices = append(startIndices, start) + } + sort.Ints(startIndices) + for _, start := range startIndices { + label := starts[start] + labelIndex := labelIndices[label] + end := len(fn.Instrs) + for i := labelIndex + 1; i < len(fn.Instrs); i++ { + if fn.Instrs[i].Op == OpLABEL { + end = i + break + } + } + buf := make([]byte, 0, (end-start)*4) + for i := start; i < end; i++ { + ins := fn.Instrs[i] + if ins.Op != OpWORD || len(ins.Args) != 1 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return nil, nil, fmt.Errorf("ARM64 raw data label %q contains a non-WORD directive: %q", label, ins.Raw) + } + word := uint32(ins.Args[0].Imm) + buf = append(buf, byte(word), byte(word>>8), byte(word>>16), byte(word>>24)) + dataWords[i] = true + } + if len(buf) != 0 { + blobs = append(blobs, arm64RawDataBlob{label: label, bytes: buf}) + } + } + return dataWords, blobs, nil +} + +func arm64RawIsNonFallthroughTerminator(ins Instr) bool { + op := strings.ToUpper(string(ins.Op)) + if dot := strings.IndexByte(op, '.'); dot >= 0 { + op = op[:dot] + } + if op == "RET" || op == "B" || op == "JMP" || op == "BR" { + return true + } + if ins.Op != OpWORD || len(ins.Args) != 1 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return false + } + var code [4]byte + binary.LittleEndian.PutUint32(code[:], uint32(ins.Args[0].Imm)) + decoded, err := arm64asm.Decode(code[:]) + if err != nil { + return false + } + switch decoded.Op.String() { + case "B", "BR", "RET", "ERET", "DRPS": + return true + default: + return false + } +} + +func arm64RawPCRelativeDisplacement(ins Instr) (displacement int64, op string, pcRelative bool, err error) { + if ins.Op != OpWORD || len(ins.Args) != 1 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return 0, "", false, nil + } + word := uint32(ins.Args[0].Imm) + var code [4]byte + binary.LittleEndian.PutUint32(code[:], word) + decoded, decodeErr := arm64asm.Decode(code[:]) + if decodeErr != nil { + return 0, "", false, nil + } + count := 0 + for _, arg := range decoded.Args { + if arg == nil { + break + } + if relative, ok := arg.(arm64asm.PCRel); ok { + displacement = int64(relative) + count++ + } + } + if count == 0 { + return 0, decoded.Op.String(), false, nil + } + if count != 1 { + return 0, decoded.Op.String(), true, fmt.Errorf("ARM64 WORD %#08x has %d PC-relative operands: %q", word, count, ins.Raw) + } + return displacement, decoded.Op.String(), true, nil +} + +func arm64RawKnownSourceWidth(fn Func, ins Instr) (int64, bool) { + switch ins.Op { + case OpTEXT, OpLABEL, "NO_LOCAL_POINTERS", "PCDATA", "FUNCDATA": + return 0, true + case OpWORD: + return 4, true + case OpRET: + if len(ins.Args) != 0 { + return 0, false + } + if fn.FrameSize == 0 { + return 4, true + } + // cmd/asm emits restore-FP, restore-SP, RET for ordinary framed + // functions whose rounded frame fits ARM64's immediate ADD. + if fn.FrameSize > 0 && fn.FrameSize <= 4080 { + return 12, true + } + return 0, false + case "B", OpJMP: + if arm64RawFixedWidthJumpOperand(ins, false) { + return 4, true + } + return 0, false + case "BL", OpCALL: + if arm64RawFixedWidthJumpOperand(ins, true) { + return 4, true + } + return 0, false + case OpMOVD: + if len(ins.Args) != 2 { + return 0, false + } + for _, arg := range ins.Args { + switch arg.Kind { + case OpReg, OpFP, OpMem: + default: + return 0, false + } + } + return 4, true + default: + return 0, false + } +} + +// arm64RawFixedWidthJumpOperand mirrors Go 1.27's complete AB/ABL optab: +// C_SBRA and C_ZOREG for B/JMP, plus C_ZREG for BL/CALL. Every accepted form +// occupies one AArch64 instruction. Keeping this validation local prevents an +// invalid or expanding pseudo-op from being guessed as four bytes. +func arm64RawFixedWidthJumpOperand(ins Instr, link bool) bool { + if len(ins.Args) != 1 { + return false + } + operand := ins.Args[0] + switch operand.Kind { + case OpIdent, OpSym: + return true // C_SBRA: local or relocated branch target. + case OpReg: + return link && isARM64GeneralOrZeroReg(operand.Reg) // C_ZREG. + case OpMem: + if operand.Mem.Base == PC { + return operand.Mem.Index == "" // instruction-relative C_SBRA. + } + return operand.Mem.Off == 0 && operand.Mem.OffRaw == "" && operand.Mem.Index == "" && + isARM64GeneralOrZeroReg(operand.Mem.Base) // C_ZOREG. + default: + return false + } +} + +func arm64UniqueRawTargetLabel(known map[string]bool, point arm64RawLayoutPoint) string { + base := fmt.Sprintf("raw_pc_%d_%x", point.segment, point.offset) + base = strings.ReplaceAll(base, "-", "neg_") + for suffix := 0; ; suffix++ { + candidate := base + if suffix != 0 { + candidate = fmt.Sprintf("%s_%d", base, suffix) + } + if !known[candidate] { + return candidate + } + } +} diff --git a/arm64_raw_structure_lane_test.go b/arm64_raw_structure_lane_test.go new file mode 100644 index 00000000..9a555b95 --- /dev/null +++ b/arm64_raw_structure_lane_test.go @@ -0,0 +1,280 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "runtime" + "strings" + "testing" +) + +type arm64RawStructureLanePost int + +const ( + arm64RawStructureLaneNoPost arm64RawStructureLanePost = iota + arm64RawStructureLaneFixedPost + arm64RawStructureLaneRegisterPost +) + +func encodeARM64RawStructureLane(load bool, count, elementBits, lane int, post arm64RawStructureLanePost, postRegister, base, firstRegister int) uint32 { + word := uint32(0x0d000000 | base<<5 | firstRegister) + if load { + word |= 1 << 22 + } + if count%2 == 0 { + word |= 1 << 21 + } + if count >= 3 { + word |= 1 << 13 + } + if post != arm64RawStructureLaneNoPost { + word |= 1 << 23 + if post == arm64RawStructureLaneFixedPost { + postRegister = 31 + } + word |= uint32(postRegister) << 16 + } + switch elementBits { + case 8: + word |= uint32(lane>>3) << 30 + word |= uint32(lane&7) << 10 + case 16: + word |= 1 << 14 + word |= uint32(lane>>2) << 30 + word |= uint32(lane&3) << 11 + case 32: + word |= 1 << 15 + word |= uint32(lane>>1) << 30 + word |= uint32(lane&1) << 12 + case 64: + word |= 1 << 15 + word |= 1 << 10 + word |= uint32(lane) << 30 + default: + panic("invalid ARM64 structure-lane element width") + } + return word +} + +func TestTranslateARM64RawStructureLaneReportedEncoding(t *testing.T) { + const source = `TEXT rawStructureLane(SB),$0-0 + WORD $0x0da14010 // ST2 {V16.H, V17.H}[0], [R0], R1 + RET +` + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "aarch64-unknown-linux-gnu", + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawStructureLane": {Name: "rawStructureLane", Ret: Void}, + }, + }); err != nil { + t.Fatal(err) + } +} + +func TestARM64RawStructureLaneDecoderCoversCompleteArchitectureFamily(t *testing.T) { + for _, load := range []bool{false, true} { + for count := 1; count <= 4; count++ { + for _, elementBits := range []int{8, 16, 32, 64} { + for lane := 0; lane < 128/elementBits; lane++ { + for _, post := range []arm64RawStructureLanePost{ + arm64RawStructureLaneNoPost, + arm64RawStructureLaneFixedPost, + arm64RawStructureLaneRegisterPost, + } { + word := encodeARM64RawStructureLane(load, count, elementBits, lane, post, 17, 31, 31) + form, ok := decodeARM64RawStructureLane(word) + wantPostRegister := 0 + if post == arm64RawStructureLaneFixedPost { + wantPostRegister = 31 + } else if post == arm64RawStructureLaneRegisterPost { + wantPostRegister = 17 + } + if !ok || form.load != load || form.count != count || form.elementBits != elementBits || + form.lane != lane || form.firstRegister != 31 || form.base != 31 || + form.post != (post != arm64RawStructureLaneNoPost) || form.postRegister != wantPostRegister { + t.Fatalf("decode load=%v count=%d bits=%d lane=%d post=%d word=%#08x: form=%#v ok=%v", + load, count, elementBits, lane, post, word, form, ok) + } + decoded, err := decodeARM64RawWordInstruction(Instr{Op: OpWORD, Args: []Operand{{Kind: OpImm, Imm: int64(word)}}}) + if err != nil { + t.Fatalf("architecture decoder rejected %#08x: %v", word, err) + } + wantPrefix := map[bool]string{false: "ST", true: "LD"}[load] + if count == 1 { + wantPrefix = "V" + wantPrefix + } + wantOp := fmt.Sprintf("%s%d", wantPrefix, count) + if strings.TrimSuffix(string(decoded.Op), ".P") != wantOp { + t.Fatalf("architecture decoder decoded %#08x as %s, want %s", word, decoded.Op, wantOp) + } + } + } + } + } + } +} + +func TestARM64RawStructureLaneDecoderRejectsAdjacentEncodings(t *testing.T) { + validB := encodeARM64RawStructureLane(true, 1, 8, 0, arm64RawStructureLaneNoPost, 0, 0, 0) + validH := encodeARM64RawStructureLane(true, 2, 16, 0, arm64RawStructureLaneNoPost, 0, 0, 0) + validS := encodeARM64RawStructureLane(false, 3, 32, 0, arm64RawStructureLaneNoPost, 0, 0, 0) + validD := encodeARM64RawStructureLane(false, 4, 64, 0, arm64RawStructureLaneNoPost, 0, 0, 0) + for _, word := range []uint32{ + validB | 3<<14, // load-and-replicate opcode space + validH | 1<<10, + validS | 1<<11, + validD | 1<<12, + validB | 1<<16, // Rm is reserved without post-indexing + validB | 1<<29, + } { + if form, ok := decodeARM64RawStructureLane(word); ok { + t.Fatalf("decoded reserved or adjacent encoding %#08x as %#v", word, form) + } + } +} + +func TestTranslateARM64RawStructureLaneCompleteArchitectureFamily(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT rawStructureLaneArchitectureForms(SB),$0-0\n") + for _, load := range []bool{false, true} { + for count := 1; count <= 4; count++ { + for _, elementBits := range []int{8, 16, 32, 64} { + for _, lane := range []int{0, 128/elementBits - 1} { + for _, post := range []arm64RawStructureLanePost{ + arm64RawStructureLaneNoPost, + arm64RawStructureLaneFixedPost, + arm64RawStructureLaneRegisterPost, + } { + word := encodeARM64RawStructureLane(load, count, elementBits, lane, post, 21, 20, 31) + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + } + } + } + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + for _, triple := range []string{ + "aarch64-apple-darwin", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + } { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawStructureLaneArchitectureForms": {Name: "rawStructureLaneArchitectureForms", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, operation := range []string{"load i", "store i", "insertelement", "extractelement", "add i64"} { + if !strings.Contains(ll, operation) { + t.Fatalf("%s omitted %s semantics:\n%s", triple, operation, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-structure-lane.ll", "arm64-raw-structure-lane.o", ll) + }) + } +} + +func TestARM64RawStructureLaneRuntimeSemantics(t *testing.T) { + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Skip("runtime execution test requires a Darwin arm64 host") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + load4H := encodeARM64RawStructureLane(true, 4, 16, 3, arm64RawStructureLaneNoPost, 0, 0, 8) + store4HPost := encodeARM64RawStructureLane(false, 4, 16, 3, arm64RawStructureLaneFixedPost, 0, 4, 8) + load3SPost := encodeARM64RawStructureLane(true, 3, 32, 2, arm64RawStructureLaneRegisterPost, 5, 0, 12) + source := fmt.Sprintf(`TEXT rawStructureLaneSemantics(SB),$0-32 + MOVD input+0(FP), R0 + MOVD initial+8(FP), R1 + MOVD output+16(FP), R2 + MOVD updates+24(FP), R3 + VLD1.P 64(R1), [V8.B16, V9.B16, V10.B16, V11.B16] + VLD1.P 48(R1), [V12.B16, V13.B16, V14.B16] + WORD $%#08x + VST1 [V8.B16, V9.B16, V10.B16, V11.B16], (R2) + ADD $64, R2, R4 + WORD $%#08x + MOVD R4, 0(R3) + MOVD $12, R5 + WORD $%#08x + MOVD R0, 8(R3) + ADD $80, R2, R6 + VST1.P [V12.B16, V13.B16, V14.B16], 48(R6) + RET +`, load4H, store4HPost, load3SPost) + requireARM64GoAssemblerResult(t, source, true) + file, err := Parse(ArchARM64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{"rawStructureLaneSemantics": { + Name: "rawStructureLaneSemantics", Args: []LLVMType{Ptr, Ptr, Ptr, Ptr}, Ret: Void, + Frame: FrameLayout{Params: []FrameSlot{ + {Offset: 0, Type: Ptr, Index: 0, Field: -1}, + {Offset: 8, Type: Ptr, Index: 1, Field: -1}, + {Offset: 16, Type: Ptr, Index: 2, Field: -1}, + {Offset: 24, Type: Ptr, Index: 3, Field: -1}, + }}, + }}, + }) + if err != nil { + t.Fatal(err) + } + const mainC = ` +#include +#include +extern void rawStructureLaneSemantics(const uint8_t *, const uint8_t *, uint8_t *, uintptr_t *); +int main(void) { + uint8_t input[32], initial[112], output[128] = {0}; + uintptr_t updates[2] = {0}; + for (int i = 0; i < 32; i++) input[i] = (uint8_t)(i * 7u + 3u); + for (int i = 0; i < 112; i++) initial[i] = (uint8_t)(i * 11u + 5u); + rawStructureLaneSemantics(input, initial, output, updates); + for (int reg = 0; reg < 4; reg++) { + for (int byte = 0; byte < 16; byte++) { + uint8_t want = initial[reg * 16 + byte]; + if (byte == 6 || byte == 7) want = input[reg * 2 + byte - 6]; + if (output[reg * 16 + byte] != want) return 1 + reg * 16 + byte; + } + } + if (memcmp(output + 64, input, 8) != 0) return 70; + for (int reg = 0; reg < 3; reg++) { + for (int byte = 0; byte < 16; byte++) { + uint8_t want = initial[64 + reg * 16 + byte]; + if (byte >= 8 && byte < 12) want = input[reg * 4 + byte - 8]; + if (output[80 + reg * 16 + byte] != want) return 80 + reg * 16 + byte; + } + } + if (updates[0] != (uintptr_t)(output + 72)) return 201; + if (updates[1] != (uintptr_t)(input + 12)) return 202; + return 0; +} +` + compileAndRunRuntimeTestForTarget(t, llc, clang, "arm64_raw_structure_lane", triple, ll, mainC, nil) +} diff --git a/arm64_raw_unscaled_memory_test.go b/arm64_raw_unscaled_memory_test.go new file mode 100644 index 00000000..deaaecdd --- /dev/null +++ b/arm64_raw_unscaled_memory_test.go @@ -0,0 +1,84 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestARM64RawUnscaledMemoryCompleteArchitecturalFamily(t *testing.T) { + forms := []struct { + word uint32 + op Op + }{ + {0xb84bf1a1, "MOVWU"}, // LDUR W1, [X13,#191] + {0xf85c42c3, "MOVD"}, // LDUR X3, [X22,#-60] + {0x3850122e, "MOVBU"}, // LDURB W14, [X17,#-255] + {0x78480026, "MOVHU"}, // LDURH W6, [X1,#128] + {0x38cde3c3, "MOVBW"}, // LDURSB W3, [X30,#222] + {0x38896127, "MOVB"}, // LDURSB X7, [X9,#150] + {0x78db717c, "MOVHW"}, // LDURSH W28, [X11,#-73] + {0x789e101d, "MOVH"}, // LDURSH X29, [X0,#-31] + {0xb88480d4, "MOVW"}, // LDURSW X20, [X6,#72] + {0xb8022015, "MOVW"}, // STUR W21, [X0,#34] + {0xf8177239, "MOVD"}, // STUR X25, [X17,#-137] + {0x3801328f, "MOVB"}, // STURB W15, [X20,#19] + {0x781b02eb, "MOVH"}, // STURH W11, [X23,#-80] + {0x3c5df1b8, "FMOVB"}, // LDUR B24, [X13,#-33] + {0x7c5c6395, "FMOVH"}, // LDUR H21, [X28,#-58] + {0xbc46d027, "FMOVS"}, // LDUR S7, [X1,#109] + {0xfc4e6221, "FMOVD"}, // LDUR D1, [X17,#230] + {0x3cd8d26d, "FMOVQ"}, // LDUR Q13, [X19,#-115] + {0x3c0ab0a7, "FMOVB"}, // STUR B7, [X5,#171] + {0x7c10e340, "FMOVH"}, // STUR H0, [X26,#-242] + {0xbc1f9118, "FMOVS"}, // STUR S24, [X8,#-7] + {0xfc07c0fc, "FMOVD"}, // STUR D28, [X7,#124] + {0x3c8912db, "FMOVQ"}, // STUR Q27, [X22,#145] + } + + var source strings.Builder + source.WriteString("TEXT rawUnscaledMemory(SB), $0-0\n") + for _, form := range forms { + ins := Instr{Op: OpWORD, Args: []Operand{{Kind: OpImm, Imm: int64(form.word)}}, Raw: fmt.Sprintf("WORD $%#08x", form.word)} + decoded, err := decodeARM64RawWordInstruction(ins) + if err != nil { + t.Fatalf("decode %#08x: %v", form.word, err) + } + if decoded.Op != form.op { + t.Fatalf("decode %#08x op = %s, want %s (%q)", form.word, decoded.Op, form.op, decoded.Raw) + } + fmt.Fprintf(&source, "\tWORD $%#08x\n", form.word) + } + source.WriteString("\tRET\n") + requireARM64GoAssemblerResult(t, source.String(), true) + file, err := Parse(ArchARM64, source.String()) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"aarch64-apple-darwin", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ll, err := Translate(file, Options{ + TargetTriple: triple, + Goarch: "arm64", + Sigs: map[string]FuncSig{ + "rawUnscaledMemory": {Name: "rawUnscaledMemory", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load i8", "load i16", "load i32", "load i64", "load <16 x i8>", "store i8", "store i16", "store i32", "store i64", "store <16 x i8>"} { + if !strings.Contains(ll, want) { + t.Fatalf("unscaled memory lowering for %s omitted %q:\n%s", triple, want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm64-raw-unscaled-memory.ll", "arm64-raw-unscaled-memory.o", ll) + }) + } +} diff --git a/arm64_sve_state.go b/arm64_sve_state.go new file mode 100644 index 00000000..1b0f7673 --- /dev/null +++ b/arm64_sve_state.go @@ -0,0 +1,176 @@ +package plan9asm + +import "fmt" + +func (c *arm64Ctx) loadZReg(index int) (string, error) { + slot := c.zRegSlot[index] + if slot == "" { + return "", fmt.Errorf("arm64 SVE Z%d was not allocated", index) + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load , ptr %s\n", value, slot) + return "%" + value, nil +} + +func (c *arm64Ctx) storeZReg(index int, value string) error { + slot := c.zRegSlot[index] + if slot == "" { + return fmt.Errorf("arm64 SVE Z%d was not allocated", index) + } + fmt.Fprintf(c.b, " store %s, ptr %s\n", value, slot) + return nil +} + +func (c *arm64Ctx) loadPReg(index int) (string, error) { + slot := c.pRegSlot[index] + if slot == "" { + return "", fmt.Errorf("arm64 SVE P%d was not allocated", index) + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load , ptr %s\n", value, slot) + return "%" + value, nil +} + +func (c *arm64Ctx) storePReg(index int, value string) error { + slot := c.pRegSlot[index] + if slot == "" { + return fmt.Errorf("arm64 SVE P%d was not allocated", index) + } + fmt.Fprintf(c.b, " store %s, ptr %s\n", value, slot) + return nil +} + +func (c *arm64Ctx) loadPNReg(index int) (string, error) { + slot := c.pnRegSlot[index] + if slot == "" { + return "", fmt.Errorf("arm64 SVE PN%d was not allocated", index) + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load target(\"aarch64.svcount\"), ptr %s\n", value, slot) + return "%" + value, nil +} + +func (c *arm64Ctx) storePNReg(index int, value string) error { + slot := c.pnRegSlot[index] + if slot == "" { + return fmt.Errorf("arm64 SVE PN%d was not allocated", index) + } + fmt.Fprintf(c.b, " store target(\"aarch64.svcount\") %s, ptr %s\n", value, slot) + return nil +} + +func (c *arm64Ctx) storePRegElements(index, elementBits int, value string) error { + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return err + } + if elementBits == 8 { + return c.storePReg(index, value) + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call @llvm.aarch64.sve.convert.to.svbool.nxv%di1( %s)\n", converted, lanes, lanes, value) + return c.storePReg(index, "%"+converted) +} + +func arm64SVEVectorType(elementBits int) (string, int, error) { + if elementBits != 8 && elementBits != 16 && elementBits != 32 && elementBits != 64 { + return "", 0, fmt.Errorf("unsupported ARM64 SVE element width %d", elementBits) + } + lanes := 128 / elementBits + return fmt.Sprintf("", lanes, elementBits), lanes, nil +} + +func (c *arm64Ctx) loadZRegElements(index, elementBits int) (value, vectorType string, err error) { + bytes, err := c.loadZReg(index) + if err != nil { + return "", "", err + } + vectorType, _, err = arm64SVEVectorType(elementBits) + if err != nil { + return "", "", err + } + if elementBits == 8 { + return bytes, vectorType, nil + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s to %s\n", converted, bytes, vectorType) + return "%" + converted, vectorType, nil +} + +func (c *arm64Ctx) storeZRegElements(index, elementBits int, value string) error { + vectorType, _, err := arm64SVEVectorType(elementBits) + if err != nil { + return err + } + if elementBits == 8 { + return c.storeZReg(index, value) + } + bytes := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to \n", bytes, vectorType, value) + return c.storeZReg(index, "%"+bytes) +} + +func (c *arm64Ctx) loadPRegElements(index, elementBits int) (value, predicateType string, err error) { + predicate, err := c.loadPReg(index) + if err != nil { + return "", "", err + } + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return "", "", err + } + predicateType = fmt.Sprintf("", lanes) + if elementBits == 8 { + return predicate, predicateType, nil + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.convert.from.svbool.nxv%di1( %s)\n", + converted, predicateType, lanes, predicate) + return "%" + converted, predicateType, nil +} + +func (c *arm64Ctx) allTruePRegElements(elementBits int) (value, predicateType string, err error) { + _, lanes, err := arm64SVEVectorType(elementBits) + if err != nil { + return "", "", err + } + predicateType = fmt.Sprintf("", lanes) + valueName := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call %s @llvm.aarch64.sve.ptrue.nxv%di1(i32 31)\n", valueName, predicateType, lanes) + return "%" + valueName, predicateType, nil +} + +func (c *arm64Ctx) setSVEPredicateFlags(governing, result, predicateType string, lanes int) { + c.setSVEPredicateSequenceFlags(governing, []string{result}, predicateType, lanes) +} + +func (c *arm64Ctx) setSVEPredicateSequenceFlags(governing string, results []string, predicateType string, lanes int) { + if len(results) == 0 { + return + } + negative := c.newTmp() + zero := c.newTmp() + last := c.newTmp() + carry := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i1 @llvm.aarch64.sve.ptest.first.nxv%di1(%s %s, %s %s)\n", negative, lanes, predicateType, governing, predicateType, results[0]) + anyValues := make([]string, 0, len(results)) + for _, result := range results { + any := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i1 @llvm.aarch64.sve.ptest.any.nxv%di1(%s %s, %s %s)\n", any, lanes, predicateType, governing, predicateType, result) + anyValues = append(anyValues, "%"+any) + } + anyValue := anyValues[0] + for _, value := range anyValues[1:] { + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %s, %s\n", combined, anyValue, value) + anyValue = "%" + combined + } + fmt.Fprintf(c.b, " %%%s = xor i1 %s, true\n", zero, anyValue) + fmt.Fprintf(c.b, " %%%s = call i1 @llvm.aarch64.sve.ptest.last.nxv%di1(%s %s, %s %s)\n", last, lanes, predicateType, governing, predicateType, results[len(results)-1]) + fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", carry, last) + c.flagsWritten = true + c.storeFlag(c.flagsNSlot, "%"+negative) + c.storeFlag(c.flagsZSlot, "%"+zero) + c.storeFlag(c.flagsCSlot, "%"+carry) + c.storeFlag(c.flagsVSlot, "false") +} diff --git a/arm64_translate.go b/arm64_translate.go index cfa69899..10360da5 100644 --- a/arm64_translate.go +++ b/arm64_translate.go @@ -12,9 +12,771 @@ func emitARM64Prelude(b *strings.Builder) { b.WriteString("declare i64 @syscall(i64, i64, i64, i64, i64, i64, i64)\n") b.WriteString("declare i32 @cliteErrno()\n") b.WriteString("declare i64 @llvm.bitreverse.i64(i64)\n") + b.WriteString("declare i32 @llvm.bitreverse.i32(i32)\n") + b.WriteString("declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>)\n") + b.WriteString("declare <16 x i8> @llvm.bitreverse.v16i8(<16 x i8>)\n") b.WriteString("declare i64 @llvm.ctlz.i64(i64, i1)\n") + b.WriteString("declare i32 @llvm.ctlz.i32(i32, i1)\n") b.WriteString("declare i64 @llvm.bswap.i64(i64)\n") b.WriteString("declare i32 @llvm.bswap.i32(i32)\n") + b.WriteString("declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>)\n") + b.WriteString("declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)\n") + for _, intrinsic := range []string{"smmla", "ummla", "usmmla"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv4i32(, , )\n", intrinsic) + } + b.WriteString("declare @llvm.aarch64.sve.bfmmla(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fmmla.nxv4f32(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fmmla.nxv2f64(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(, , )\n") + for _, vector := range []struct{ lanes, bits int }{{8, 8}, {16, 8}, {4, 16}, {8, 16}, {2, 32}, {4, 32}} { + fmt.Fprintf(b, "declare <%d x i%d> @llvm.ctlz.v%di%d(<%d x i%d>, i1)\n", vector.lanes, vector.bits, vector.lanes, vector.bits, vector.lanes, vector.bits) + } + b.WriteString("declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>)\n") + b.WriteString("declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)\n") + for _, vector := range []struct{ lanes, bits int }{{8, 8}, {16, 8}, {4, 16}, {8, 16}, {2, 32}, {4, 32}, {2, 64}} { + vectorType := fmt.Sprintf("<%d x i%d>", vector.lanes, vector.bits) + for _, intrinsic := range []string{"sshl", "srshl", "ushl", "urshl", "sqshl", "uqshl"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.neon.%s.v%di%d(%s, %s)\n", vectorType, intrinsic, vector.lanes, vector.bits, vectorType, vectorType) + } + } + for _, intrinsic := range []string{"sshl", "srshl", "ushl", "urshl"} { + fmt.Fprintf(b, "declare i64 @llvm.aarch64.neon.%s.i64(i64, i64)\n", intrinsic) + } + b.WriteString("declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8>, <16 x i8>)\n") + b.WriteString("declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8>, <16 x i8>)\n") + b.WriteString("declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8>)\n") + b.WriteString("declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8>)\n") + b.WriteString("declare <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32>, i32, <4 x i32>)\n") + b.WriteString("declare <4 x i32> @llvm.aarch64.crypto.sha1p(<4 x i32>, i32, <4 x i32>)\n") + b.WriteString("declare <4 x i32> @llvm.aarch64.crypto.sha1m(<4 x i32>, i32, <4 x i32>)\n") + b.WriteString("declare i32 @llvm.aarch64.crypto.sha1h(i32)\n") + b.WriteString("declare <4 x i32> @llvm.aarch64.crypto.sha1su0(<4 x i32>, <4 x i32>, <4 x i32>)\n") + b.WriteString("declare <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32>, <4 x i32>)\n") + b.WriteString("declare <4 x i32> @llvm.aarch64.crypto.sha256h(<4 x i32>, <4 x i32>, <4 x i32>)\n") + b.WriteString("declare <4 x i32> @llvm.aarch64.crypto.sha256h2(<4 x i32>, <4 x i32>, <4 x i32>)\n") + b.WriteString("declare <4 x i32> @llvm.aarch64.crypto.sha256su0(<4 x i32>, <4 x i32>)\n") + b.WriteString("declare <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32>, <4 x i32>, <4 x i32>)\n") + b.WriteString("declare <2 x i64> @llvm.aarch64.crypto.sha512h(<2 x i64>, <2 x i64>, <2 x i64>)\n") + b.WriteString("declare <2 x i64> @llvm.aarch64.crypto.sha512h2(<2 x i64>, <2 x i64>, <2 x i64>)\n") + b.WriteString("declare <2 x i64> @llvm.aarch64.crypto.sha512su0(<2 x i64>, <2 x i64>)\n") + b.WriteString("declare <2 x i64> @llvm.aarch64.crypto.sha512su1(<2 x i64>, <2 x i64>, <2 x i64>)\n") + b.WriteString("declare i64 @llvm.vscale.i64()\n") + b.WriteString("declare @llvm.masked.load.nxv2i64.p0(ptr, , )\n") + b.WriteString("declare void @llvm.masked.store.nxv2i64.p0(, ptr, )\n") + for _, bits := range []int{8, 16, 32, 64} { + lanes := 128 / bits + vectorType := fmt.Sprintf("", lanes, bits) + for _, intrinsic := range []string{"eorbt", "eortb"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s, %s)\n", vectorType, intrinsic, lanes, bits, vectorType, vectorType, vectorType) + } + predicateType := fmt.Sprintf("", lanes) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ld1ro.nxv%di%d(%s, ptr)\n", vectorType, lanes, bits, predicateType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ld1rq.nxv%di%d(%s, ptr)\n", vectorType, lanes, bits, predicateType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ldnt1.nxv%di%d(%s, ptr)\n", vectorType, lanes, bits, predicateType) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.stnt1.nxv%di%d(%s, %s, ptr)\n", lanes, bits, vectorType, predicateType) + fmt.Fprintf(b, "declare { %s, %s } @llvm.aarch64.sve.ldnt1.pn.x2.nxv%di%d(target(\"aarch64.svcount\"), ptr)\n", vectorType, vectorType, lanes, bits) + fmt.Fprintf(b, "declare { %s, %s, %s, %s } @llvm.aarch64.sve.ldnt1.pn.x4.nxv%di%d(target(\"aarch64.svcount\"), ptr)\n", vectorType, vectorType, vectorType, vectorType, lanes, bits) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.stnt1.pn.x2.nxv%di%d(%s, %s, target(\"aarch64.svcount\"), ptr)\n", lanes, bits, vectorType, vectorType) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.stnt1.pn.x4.nxv%di%d(%s, %s, %s, %s, target(\"aarch64.svcount\"), ptr)\n", lanes, bits, vectorType, vectorType, vectorType, vectorType) + } + for _, destinationBits := range []int{32, 64} { + lanes := 128 / destinationBits + baseType := fmt.Sprintf("", lanes, destinationBits) + predicateType := fmt.Sprintf("", lanes) + for _, memoryBits := range []int{8, 16, 32, 64} { + if memoryBits > destinationBits { + continue + } + memoryType := fmt.Sprintf("", lanes, memoryBits) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv%di%d.nxv%di%d(%s, %s, i64)\n", memoryType, lanes, memoryBits, lanes, destinationBits, predicateType, baseType) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv%di%d.nxv%di%d(%s, %s, %s, i64)\n", lanes, memoryBits, lanes, destinationBits, memoryType, predicateType, baseType) + } + } + for _, destinationBits := range []int{8, 16, 32, 64} { + lanes := 128 / destinationBits + indexType := fmt.Sprintf("", lanes, destinationBits) + predicateType := fmt.Sprintf("", lanes) + for _, memoryBits := range []int{8, 16, 32, 64} { + if memoryBits > destinationBits { + continue + } + memoryType := fmt.Sprintf("", lanes, memoryBits) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ldff1.nxv%di%d(%s, ptr)\n", memoryType, lanes, memoryBits, predicateType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ldnf1.nxv%di%d(%s, ptr)\n", memoryType, lanes, memoryBits, predicateType) + if destinationBits != 32 && destinationBits != 64 { + continue + } + suffixes := []string{"", ".index"} + if destinationBits == 32 { + suffixes = append(suffixes, ".uxtw", ".uxtw.index", ".sxtw", ".sxtw.index") + } + for _, suffix := range suffixes { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ldff1.gather%s.nxv%di%d(%s, ptr, %s)\n", memoryType, suffix, lanes, memoryBits, predicateType, indexType) + } + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv%di%d.nxv%di%d(%s, %s, i64)\n", + memoryType, lanes, memoryBits, lanes, destinationBits, predicateType, indexType) + } + } + for _, destinationBits := range []int{8, 16, 32, 64} { + lanes := 128 / destinationBits + indexType := fmt.Sprintf("", lanes, destinationBits) + predicateType := fmt.Sprintf("", lanes) + for _, memoryBits := range []int{8, 16, 32, 64} { + if memoryBits > destinationBits { + continue + } + memoryType := fmt.Sprintf("", lanes, memoryBits) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ld1.nxv%di%d(%s, ptr)\n", memoryType, lanes, memoryBits, predicateType) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.st1.nxv%di%d(%s, %s, ptr)\n", lanes, memoryBits, memoryType, predicateType) + if destinationBits != 32 && destinationBits != 64 { + continue + } + suffixes := []string{"", ".index"} + if destinationBits == 32 { + suffixes = append(suffixes, ".uxtw", ".uxtw.index", ".sxtw", ".sxtw.index") + } + for _, suffix := range suffixes { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ld1.gather%s.nxv%di%d(%s, ptr, %s)\n", memoryType, suffix, lanes, memoryBits, predicateType, indexType) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.st1.scatter%s.nxv%di%d(%s, %s, ptr, %s)\n", suffix, lanes, memoryBits, memoryType, predicateType, indexType) + } + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv%di%d.nxv%di%d(%s, %s, i64)\n", + memoryType, lanes, memoryBits, lanes, destinationBits, predicateType, indexType) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv%di%d.nxv%di%d(%s, %s, %s, i64)\n", + lanes, memoryBits, lanes, destinationBits, memoryType, predicateType, indexType) + } + } + for _, bits := range []int{8, 16, 32, 64} { + lanes := 128 / bits + vectorType := fmt.Sprintf("", lanes, bits) + fmt.Fprintf(b, "declare { %s, %s } @llvm.aarch64.sve.ld1.pn.x2.nxv%di%d(target(\"aarch64.svcount\"), ptr)\n", vectorType, vectorType, lanes, bits) + fmt.Fprintf(b, "declare { %s, %s, %s, %s } @llvm.aarch64.sve.ld1.pn.x4.nxv%di%d(target(\"aarch64.svcount\"), ptr)\n", vectorType, vectorType, vectorType, vectorType, lanes, bits) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.st1.pn.x2.nxv%di%d(%s, %s, target(\"aarch64.svcount\"), ptr)\n", lanes, bits, vectorType, vectorType) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.st1.pn.x4.nxv%di%d(%s, %s, %s, %s, target(\"aarch64.svcount\"), ptr)\n", lanes, bits, vectorType, vectorType, vectorType, vectorType) + } + b.WriteString("declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1()\n") + b.WriteString("declare @llvm.aarch64.sve.ld1uwq.nxv4i32(, ptr)\n") + b.WriteString("declare @llvm.aarch64.sve.ld1udq.nxv2i64(, ptr)\n") + b.WriteString("declare void @llvm.aarch64.sve.st1wq.nxv4i32(, , ptr)\n") + b.WriteString("declare void @llvm.aarch64.sve.st1dq.nxv2i64(, , ptr)\n") + b.WriteString("declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(, , i64)\n") + b.WriteString("declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(, , , i64)\n") + for _, count := range []int{2, 3, 4} { + for _, bits := range []int{8, 16, 32, 64} { + lanes := 128 / bits + vectorType := fmt.Sprintf("", lanes, bits) + predicateType := fmt.Sprintf("", lanes) + aggregateType := arm64SVEAggregateType(vectorType, count) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ld%d.sret.nxv%di%d(%s, ptr)\n", aggregateType, count, lanes, bits, predicateType) + values := make([]string, count) + for i := range values { + values[i] = vectorType + } + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.st%d.nxv%di%d(%s, %s, ptr)\n", count, lanes, bits, strings.Join(values, ", "), predicateType) + } + vectorType := "" + predicateType := "" + aggregateType := arm64SVEAggregateType(vectorType, count) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ld%dq.sret.nxv2i64(%s, ptr)\n", aggregateType, count, predicateType) + values := make([]string, count) + for i := range values { + values[i] = vectorType + } + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.st%dq.nxv2i64(%s, %s, ptr)\n", count, strings.Join(values, ", "), predicateType) + } + for _, elementBits := range []int{8, 16, 32, 64} { + fmt.Fprintf(b, "declare target(\"aarch64.svcount\") @llvm.aarch64.sve.ptrue.c%d()\n", elementBits) + fmt.Fprintf(b, "declare i64 @llvm.aarch64.sve.cntp.c%d(target(\"aarch64.svcount\"), i32 immarg)\n", elementBits) + lanes := 128 / elementBits + fmt.Fprintf(b, "declare i64 @llvm.aarch64.sve.cntp.nxv%di1(, )\n", lanes, lanes, lanes) + predicateType := fmt.Sprintf("", lanes) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.pext.nxv%di1(target(\"aarch64.svcount\"), i32 immarg)\n", predicateType, lanes) + fmt.Fprintf(b, "declare { %s, %s } @llvm.aarch64.sve.pext.x2.nxv%di1(target(\"aarch64.svcount\"), i32 immarg)\n", predicateType, predicateType, lanes) + for _, condition := range []string{"whilege", "whilegt", "whilehi", "whilehs", "whilele", "whilelo", "whilels", "whilelt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di1.i64(i64, i64)\n", predicateType, condition, lanes) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di1.i32(i32, i32)\n", predicateType, condition, lanes) + fmt.Fprintf(b, "declare { %s, %s } @llvm.aarch64.sve.%s.x2.nxv%di1(i64, i64)\n", predicateType, predicateType, condition, lanes) + fmt.Fprintf(b, "declare target(\"aarch64.svcount\") @llvm.aarch64.sve.%s.c%d(i64, i64, i32 immarg)\n", condition, elementBits) + } + letter := strings.ToLower(map[int]string{8: "B", 16: "H", 32: "S", 64: "D"}[elementBits]) + for _, condition := range []string{"whilerw", "whilewr"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.%s.nxv%di1.p0(ptr, ptr)\n", predicateType, condition, letter, lanes) + } + for _, intrinsic := range []string{"sqdecp", "sqincp", "uqdecp", "uqincp"} { + fmt.Fprintf(b, "declare i32 @llvm.aarch64.sve.%s.n32.nxv%di1(i32, %s)\n", intrinsic, lanes, predicateType) + fmt.Fprintf(b, "declare i64 @llvm.aarch64.sve.%s.n64.nxv%di1(i64, %s)\n", intrinsic, lanes, predicateType) + } + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.prf.nxv%di1(%s, ptr, i32 immarg)\n", lanes, predicateType) + vectorType := fmt.Sprintf("", lanes, elementBits) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.index.nxv%di%d(i%d, i%d)\n", vectorType, lanes, elementBits, elementBits, elementBits) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.insr.nxv%di%d(%s, i%d)\n", vectorType, lanes, elementBits, vectorType, elementBits) + for _, intrinsic := range []string{"lasta", "lastb"} { + fmt.Fprintf(b, "declare i%d @llvm.aarch64.sve.%s.nxv%di%d(%s, %s)\n", elementBits, intrinsic, lanes, elementBits, predicateType, vectorType) + } + for _, intrinsic := range []string{"clasta", "clastb"} { + fmt.Fprintf(b, "declare i%d @llvm.aarch64.sve.%s.n.nxv%di%d(%s, i%d, %s)\n", elementBits, intrinsic, lanes, elementBits, predicateType, elementBits, vectorType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s, %s)\n", vectorType, intrinsic, lanes, elementBits, predicateType, vectorType, vectorType) + } + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.compact.nxv%di%d(%s, %s)\n", vectorType, lanes, elementBits, predicateType, vectorType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.expand.nxv%di%d(%s, %s)\n", vectorType, lanes, elementBits, predicateType, vectorType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.splice.nxv%di%d(%s, %s, %s)\n", vectorType, lanes, elementBits, predicateType, vectorType, vectorType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv%di%d(%s)\n", predicateType, lanes, elementBits, vectorType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.pmov.to.pred.lane.nxv%di%d(%s, i32 immarg)\n", predicateType, lanes, elementBits, vectorType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv%di%d(%s)\n", vectorType, lanes, elementBits, predicateType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv%di%d(%s, %s, i32 immarg)\n", vectorType, lanes, elementBits, vectorType, predicateType) + } + for _, destinationBits := range []int{16, 32, 64} { + destinationLanes := 128 / destinationBits + sourceBits := destinationBits / 2 + sourceLanes := 128 / sourceBits + destinationType := fmt.Sprintf("", destinationLanes, destinationBits) + sourceType := fmt.Sprintf("", sourceLanes, sourceBits) + for _, intrinsic := range []string{"saddlb", "saddlbt", "saddlt", "ssublb", "ssublbt", "ssublt", "ssubltb", "uaddlb", "uaddlt", "usublb", "usublt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s)\n", destinationType, intrinsic, destinationLanes, destinationBits, sourceType, sourceType) + } + for _, intrinsic := range []string{"sshllb", "sshllt", "ushllb", "ushllt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, i32 immarg)\n", destinationType, intrinsic, destinationLanes, destinationBits, sourceType) + } + for _, intrinsic := range []string{"saddwb", "saddwt", "ssubwb", "ssubwt", "uaddwb", "uaddwt", "usubwb", "usubwt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s)\n", destinationType, intrinsic, destinationLanes, destinationBits, destinationType, sourceType) + } + for _, intrinsic := range []string{"sabdlb", "sabdlt", "uabdlb", "uabdlt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s)\n", destinationType, intrinsic, destinationLanes, destinationBits, sourceType, sourceType) + } + for _, intrinsic := range []string{"sabalb", "sabalt", "uabalb", "uabalt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s, %s)\n", destinationType, intrinsic, destinationLanes, destinationBits, destinationType, sourceType, sourceType) + } + for _, intrinsic := range []string{"sadalp", "uadalp"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(, %s, %s)\n", destinationType, intrinsic, destinationLanes, destinationBits, destinationLanes, destinationType, sourceType) + } + } + for _, sourceBits := range []int{16, 32, 64} { + sourceLanes := 128 / sourceBits + destinationBits := sourceBits / 2 + destinationLanes := 128 / destinationBits + sourceType := fmt.Sprintf("", sourceLanes, sourceBits) + destinationType := fmt.Sprintf("", destinationLanes, destinationBits) + for _, intrinsic := range []string{"addhnb", "raddhnb", "rsubhnb", "subhnb"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s)\n", destinationType, intrinsic, sourceLanes, sourceBits, sourceType, sourceType) + } + for _, intrinsic := range []string{"addhnt", "raddhnt", "rsubhnt", "subhnt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s, %s)\n", destinationType, intrinsic, sourceLanes, sourceBits, destinationType, sourceType, sourceType) + } + } + for _, intrinsic := range []string{"bcax", "bsl", "bsl1n", "bsl2n", "eor3", "nbsl"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv2i64(, , )\n", intrinsic) + } + for _, bits := range []int{8, 16, 32, 64} { + lanes := 128 / bits + vectorType := fmt.Sprintf("", lanes, bits) + for _, intrinsic := range []string{"bdep.x", "bext.x", "bgrp.x"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s)\n", vectorType, intrinsic, lanes, bits, vectorType, vectorType) + } + } + for _, bits := range []int{32, 64} { + lanes := 128 / bits + vectorType := fmt.Sprintf("", lanes, bits) + for _, intrinsic := range []string{"adclb", "adclt", "sbclb", "sbclt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s, %s)\n", vectorType, intrinsic, lanes, bits, vectorType, vectorType, vectorType) + } + } + for _, bits := range []int{8, 16, 32, 64} { + lanes := 128 / bits + vectorType := fmt.Sprintf("", lanes, bits) + for _, intrinsic := range []string{"sclamp", "uclamp"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s, %s)\n", vectorType, intrinsic, lanes, bits, vectorType, vectorType, vectorType) + } + } + for _, bits := range []int{16, 32, 64} { + _, vectorType, lanes, _ := arm64SVEFloatType(bits) + suffix := map[int]string{16: "f16", 32: "f32", 64: "f64"}[bits] + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.fclamp.nxv%d%s(%s, %s, %s)\n", vectorType, lanes, suffix, vectorType, vectorType, vectorType) + } + b.WriteString("declare @llvm.aarch64.sve.fclamp.nxv8bf16(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.bfdot(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.bfdot.lane.v2(, , , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.fp8.fdot.nxv8f16(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(, , , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.fp8.fdot.nxv4f32(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(, , , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.fdot.x2.nxv4f32(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(, , , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.cdot.nxv4i32(, , , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.cdot.lane.nxv4i32(, , , i32 immarg, i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.cdot.nxv2i64(, , , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.cdot.lane.nxv2i64(, , , i32 immarg, i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.luti2.lane.nxv16i8(, , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.luti2.lane.nxv8i16(, , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.luti4.lane.nxv16i8(, , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.luti4.lane.nxv8i16(, , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.luti4.lane.x2.nxv8i16(, , , i32 immarg)\n") + for _, intrinsic := range []string{"fmlalb", "fmlalt", "fmlslb", "fmlslt"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv4f32(, , )\n", intrinsic) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.lane.nxv4f32(, , , i32 immarg)\n", intrinsic) + } + for _, intrinsic := range []string{"fmlalb", "fmlalt"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.fp8.%s.nxv8f16(, , )\n", intrinsic) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.fp8.%s.lane.nxv8f16(, , , i32 immarg)\n", intrinsic) + } + for _, intrinsic := range []string{"fmlallbb", "fmlallbt", "fmlalltb", "fmlalltt"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.fp8.%s.nxv4f32(, , )\n", intrinsic) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.fp8.%s.lane.nxv4f32(, , , i32 immarg)\n", intrinsic) + } + for _, intrinsic := range []string{"sqcvtn", "sqcvtun", "uqcvtn"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.x2.nxv4i32(, )\n", intrinsic) + } + for _, intrinsic := range []string{"sqrshrn", "sqrshrun", "uqrshrn"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.x2.nxv4i32(, , i32 immarg)\n", intrinsic) + } + b.WriteString("declare @llvm.vector.interleave2.nxv16i8(, )\n") + b.WriteString("declare @llvm.aarch64.sve.aesimc()\n") + b.WriteString("declare @llvm.aarch64.sve.aesmc()\n") + b.WriteString("declare @llvm.aarch64.sve.aesd(, )\n") + b.WriteString("declare @llvm.aarch64.sve.aese(, )\n") + b.WriteString("declare @llvm.aarch64.sve.rax1(, )\n") + b.WriteString("declare @llvm.aarch64.sve.sm4e(, )\n") + b.WriteString("declare @llvm.aarch64.sve.sm4ekey(, )\n") + for _, count := range []int{2, 4} { + types := make([]string, count) + arguments := make([]string, count+2) + for i := 0; i < count; i++ { + types[i] = "" + arguments[i] = "" + } + arguments[count] = "" + arguments[count+1] = "i32 immarg" + aggregateType := "{ " + strings.Join(types, ", ") + " }" + for _, intrinsic := range []string{"aesd", "aesdimc", "aese", "aesemc"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.lane.x%d(%s)\n", aggregateType, intrinsic, count, strings.Join(arguments, ", ")) + } + } + b.WriteString("declare @llvm.aarch64.sve.revd.nxv2i64(, , )\n") + b.WriteString("declare @llvm.aarch64.sve.pmul.nxv16i8(, )\n") + for _, bits := range []int{8, 32, 64} { + lanes := 128 / bits + vectorType := fmt.Sprintf("", lanes, bits) + for _, intrinsic := range []string{"pmullb.pair", "pmullt.pair"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s)\n", vectorType, intrinsic, lanes, bits, vectorType, vectorType) + } + } + b.WriteString("declare { , } @llvm.aarch64.sve.pmull.pair.x2(, )\n") + b.WriteString("declare { , } @llvm.aarch64.sve.pmlal.pair.x2(, , , )\n") + for _, form := range []struct{ destinationBits, sourceBits int }{{16, 8}, {32, 16}, {32, 8}, {64, 16}} { + destinationLanes := 128 / form.destinationBits + sourceLanes := 128 / form.sourceBits + destinationType := fmt.Sprintf("", destinationLanes, form.destinationBits) + sourceType := fmt.Sprintf("", sourceLanes, form.sourceBits) + x2 := "" + if form.destinationBits == form.sourceBits*2 { + x2 = ".x2" + } + for _, intrinsic := range []string{"sdot", "udot"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s%s.nxv%di%d(%s, %s, %s)\n", destinationType, intrinsic, x2, destinationLanes, form.destinationBits, destinationType, sourceType, sourceType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.lane%s.nxv%di%d(%s, %s, %s, i32 immarg)\n", destinationType, intrinsic, x2, destinationLanes, form.destinationBits, destinationType, sourceType, sourceType) + } + } + for _, intrinsic := range []string{"usdot", "usdot.lane", "sudot.lane"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv4i32(, , ", intrinsic) + if strings.Contains(intrinsic, ".lane") { + b.WriteString(", i32 immarg") + } + b.WriteString(")\n") + } + for _, sourceBits := range []int{8, 16, 32} { + destinationBits := sourceBits * 2 + sourceLanes := 128 / sourceBits + destinationLanes := 128 / destinationBits + sourceType := fmt.Sprintf("", sourceLanes, sourceBits) + destinationType := fmt.Sprintf("", destinationLanes, destinationBits) + for _, intrinsic := range []string{"sunpkhi", "sunpklo", "uunpkhi", "uunpklo"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s)\n", destinationType, intrinsic, destinationLanes, destinationBits, sourceType) + } + } + for _, sourceBits := range []int{16, 32, 64} { + destinationBits := sourceBits / 2 + sourceLanes := 128 / sourceBits + destinationLanes := 128 / destinationBits + sourceType := fmt.Sprintf("", sourceLanes, sourceBits) + destinationType := fmt.Sprintf("", destinationLanes, destinationBits) + for _, intrinsic := range []string{"sqxtnb", "sqxtunb", "uqxtnb"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s)\n", destinationType, intrinsic, sourceLanes, sourceBits, sourceType) + } + for _, intrinsic := range []string{"sqxtnt", "sqxtunt", "uqxtnt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s)\n", destinationType, intrinsic, sourceLanes, sourceBits, destinationType, sourceType) + } + } + for _, sourceBits := range []int{16, 32, 64} { + destinationBits := sourceBits / 2 + sourceLanes := 128 / sourceBits + destinationLanes := 128 / destinationBits + sourceType := fmt.Sprintf("", sourceLanes, sourceBits) + destinationType := fmt.Sprintf("", destinationLanes, destinationBits) + for _, intrinsic := range []string{"shrnb", "rshrnb"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, i32 immarg)\n", destinationType, intrinsic, sourceLanes, sourceBits, sourceType) + } + for _, intrinsic := range []string{"shrnt", "rshrnt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s, i32 immarg)\n", destinationType, intrinsic, sourceLanes, sourceBits, destinationType, sourceType) + } + } + for _, sourceBits := range []int{16, 32, 64} { + destinationBits := sourceBits / 2 + sourceLanes := 128 / sourceBits + destinationLanes := 128 / destinationBits + sourceType := fmt.Sprintf("", sourceLanes, sourceBits) + destinationType := fmt.Sprintf("", destinationLanes, destinationBits) + for _, intrinsic := range []string{"sqshrnb", "sqrshrnb", "sqshrunb", "sqrshrunb", "uqshrnb", "uqrshrnb"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, i32 immarg)\n", destinationType, intrinsic, sourceLanes, sourceBits, sourceType) + } + for _, intrinsic := range []string{"sqshrnt", "sqrshrnt", "sqshrunt", "sqrshrunt", "uqshrnt", "uqrshrnt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s, i32 immarg)\n", destinationType, intrinsic, sourceLanes, sourceBits, destinationType, sourceType) + } + } + b.WriteString("declare @llvm.aarch64.sve.ext.nxv16i8(, , i32 immarg)\n") + b.WriteString("declare @llvm.aarch64.sve.extq.nxv16i8(, , i32 immarg)\n") + emitARM64SVEConvertDeclarations(b) + emitARM64SVEFloatNarrowConversionDeclarations(b) + emitARM64SVEBFloatArithmeticDeclarations(b) + emitARM64SVEBFloatMLADeclarations(b) + for _, elementBits := range []int{16, 32, 64} { + _, vectorType, lanes, _ := arm64SVEFloatType(elementBits) + code := map[int]string{16: "f16", 32: "f32", 64: "f64"}[elementBits] + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.fmul.lane.nxv%d%s(%s, %s, i32 immarg)\n", vectorType, lanes, code, vectorType, vectorType) + predicateType := fmt.Sprintf("", lanes) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.fmulx.nxv%d%s(%s, %s, %s)\n", vectorType, lanes, code, predicateType, vectorType, vectorType) + for _, intrinsic := range []string{"ftsmul", "ftssel"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.x.nxv%d%s(%s, )\n", vectorType, intrinsic, lanes, code, vectorType, lanes, elementBits) + } + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.ftmad.x.nxv%d%s(%s, %s, i32 immarg)\n", vectorType, lanes, code, vectorType, vectorType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.fcmla.nxv%d%s(%s, %s, %s, %s, i32 immarg)\n", vectorType, lanes, code, predicateType, vectorType, vectorType, vectorType) + if elementBits != 64 { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.fcmla.lane.nxv%d%s(%s, %s, %s, i32 immarg, i32 immarg)\n", vectorType, lanes, code, vectorType, vectorType, vectorType) + } + for _, intrinsic := range []string{"fmla", "fmls", "fmad", "fmsb", "fnmla", "fnmls", "fnmad", "fnmsb"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%d%s(%s, %s, %s, %s)\n", vectorType, intrinsic, lanes, code, predicateType, vectorType, vectorType, vectorType) + } + for _, intrinsic := range []string{"fmla", "fmls"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.lane.nxv%d%s(%s, %s, %s, i32 immarg)\n", vectorType, intrinsic, lanes, code, vectorType, vectorType, vectorType) + } + } + for _, vectorBits := range []int{32, 64} { + lanes := 128 / vectorBits + predicateType := fmt.Sprintf("", lanes) + vectorType := fmt.Sprintf("", lanes, vectorBits) + for _, letter := range []string{"b", "h", "w", "d"} { + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.prf%s.gather.index.nxv%di%d(%s, ptr, %s, i32 immarg)\n", letter, lanes, vectorBits, predicateType, vectorType) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.prf%s.gather.uxtw.index.nxv%di%d(%s, ptr, %s, i32 immarg)\n", letter, lanes, vectorBits, predicateType, vectorType) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.prf%s.gather.sxtw.index.nxv%di%d(%s, ptr, %s, i32 immarg)\n", letter, lanes, vectorBits, predicateType, vectorType) + fmt.Fprintf(b, "declare void @llvm.aarch64.sve.prf%s.gather.scalar.offset.nxv%di%d(%s, %s, i64, i32 immarg)\n", letter, lanes, vectorBits, predicateType, vectorType) + } + } + for _, lanes := range []int{16, 8, 4, 2} { + for _, intrinsic := range []string{"any", "first", "last"} { + fmt.Fprintf(b, "declare i1 @llvm.aarch64.sve.ptest.%s.nxv%di1(, )\n", intrinsic, lanes, lanes, lanes) + } + } + b.WriteString("declare @llvm.aarch64.sve.rdffr()\n") + b.WriteString("declare @llvm.aarch64.sve.rdffr.z()\n") + b.WriteString("declare void @llvm.aarch64.sve.setffr()\n") + b.WriteString("declare void @llvm.aarch64.sve.wrffr()\n") + for _, intrinsic := range []string{"brka", "brkb"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv16i1(, , )\n", intrinsic) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.z.nxv16i1(, )\n", intrinsic) + } + for _, intrinsic := range []string{"brkn.z", "brkpa.z", "brkpb.z"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv16i1(, , )\n", intrinsic) + } + b.WriteString("declare @llvm.vector.reverse.nxv16i1()\n") + for _, elementBits := range []int{16, 32, 64} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.rev.b%d()\n", elementBits) + } + for _, intrinsic := range []string{"trn1", "trn2", "uzp1", "uzp2", "zip1", "zip2"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv16i1(, )\n", intrinsic) + for _, elementBits := range []int{16, 32, 64} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.b%d(, )\n", intrinsic, elementBits) + } + } + for _, intrinsic := range []string{"punpkhi", "punpklo"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv16i1()\n", intrinsic) + } + b.WriteString("declare @llvm.aarch64.sve.pfirst.nxv16i1(, )\n") + for _, lanes := range []int{16, 8, 4, 2} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.pnext.nxv%di1(, )\n", lanes, lanes, lanes, lanes) + for _, intrinsic := range []string{"firstp", "lastp"} { + fmt.Fprintf(b, "declare i64 @llvm.aarch64.sve.%s.nxv%di1(, )\n", intrinsic, lanes, lanes, lanes) + } + } + for _, lanes := range []int{16, 8, 4, 2} { + bits := 128 / lanes + fmt.Fprintf(b, "declare @llvm.aarch64.sve.ptrue.nxv%di1(i32 immarg)\n", lanes, lanes) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.dupq.lane.nxv%di%d(, i64)\n", lanes, bits, lanes, bits, lanes, bits) + for _, intrinsic := range []string{"asr", "lsl", "lsr"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"suqadd", "usqadd"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits, lanes, bits) + } + fmt.Fprintf(b, "declare @llvm.aarch64.sve.addp.nxv%di%d(, , )\n", lanes, bits, lanes, bits, lanes, lanes, bits, lanes, bits) + if bits != 8 { + for _, intrinsic := range []string{"sqdecp", "sqincp", "uqdecp", "uqincp"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, )\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes) + } + } + for _, intrinsic := range []string{"asrd", "sqshlu", "srshr", "urshr"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , i32 immarg)\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits) + } + for _, intrinsic := range []string{"sli", "sri", "srsra", "ssra", "ursra", "usra"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , i32 immarg)\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits) + } + fmt.Fprintf(b, "declare @llvm.aarch64.sve.mul.nxv%di%d(, , )\n", lanes, bits, lanes, bits, lanes, lanes, bits, lanes, bits) + for _, intrinsic := range []string{"mad", "mla", "mls", "msb"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , , )\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"smulh", "smulh.u", "umulh", "umulh.u"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"sqshl", "uqshl", "sqrshl", "uqrshl", "srshl", "urshl"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"sqdmulh", "sqrdmulh"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, )\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"saba", "uaba"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"sabd", "uabd"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"shadd", "shsub", "shsubr", "srhadd", "uhadd", "uhsub", "uhsubr", "urhadd"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits, lanes, bits) + } + if bits >= 32 { + for _, intrinsic := range []string{"sdiv", "sdivr", "udiv", "udivr"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits, lanes, bits) + } + } + for _, intrinsic := range []string{"cmla", "sqrdcmlah"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.x.nxv%di%d(, , , i32 immarg)\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"sqrdmlah", "sqrdmlsh"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"smax", "smin", "umax", "umin", "smaxp", "sminp", "umaxp", "uminp"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"cadd.x", "sqcadd.x"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , i32 immarg)\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits) + } + fmt.Fprintf(b, "declare @llvm.aarch64.sve.xar.nxv%di%d(, , i32 immarg)\n", lanes, bits, lanes, bits, lanes, bits, lanes, bits) + if bits == 8 || bits == 16 { + for _, intrinsic := range []string{"match", "nmatch"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, intrinsic, lanes, bits, lanes, lanes, bits, lanes, bits) + } + } + if bits == 8 { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.histseg.nxv16i8(, )\n") + } + if bits == 32 || bits == 64 { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.histcnt.nxv%di%d(, , )\n", lanes, bits, lanes, bits, lanes, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"abs", "cls", "clz", "cnot", "cnt", "neg", "not", "rbit", "revb", "revh", "revw", "sqabs", "sqneg", "sxtb", "sxth", "sxtw", "uxtb", "uxth", "uxtw", "urecpe", "ursqrte"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, lanes, bits) + } + fmt.Fprintf(b, "declare @llvm.vector.reverse.nxv%di%d()\n", lanes, bits, lanes, bits, lanes, bits) + for _, intrinsic := range []string{"andv", "eorv", "orv", "smaxv", "sminv", "umaxv", "uminv"} { + fmt.Fprintf(b, "declare i%d @llvm.aarch64.sve.%s.nxv%di%d(, )\n", bits, intrinsic, lanes, bits, lanes, lanes, bits) + } + for _, intrinsic := range []string{"saddv", "uaddv"} { + fmt.Fprintf(b, "declare i64 @llvm.aarch64.sve.%s.nxv%di%d(, )\n", intrinsic, lanes, bits, lanes, lanes, bits) + } + for _, intrinsic := range []string{"addqv", "andqv", "eorqv", "orqv", "smaxqv", "sminqv", "umaxqv", "uminqv"} { + fmt.Fprintf(b, "declare <%d x i%d> @llvm.aarch64.sve.%s.v%di%d.nxv%di%d(, )\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, lanes, bits) + } + fmt.Fprintf(b, "declare @llvm.aarch64.sve.tbl.nxv%di%d(, )\n", lanes, bits, lanes, bits, lanes, bits, lanes, bits) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.tbl2.nxv%di%d(, , )\n", lanes, bits, lanes, bits, lanes, bits, lanes, bits, lanes, bits) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.tblq.nxv%di%d(, )\n", lanes, bits, lanes, bits, lanes, bits, lanes, bits) + for _, intrinsic := range []string{"tbx", "tbxq"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits, lanes, bits) + } + if bits != 8 { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.mul.lane.nxv%di%d(, , i32 immarg)\n", lanes, bits, lanes, bits, lanes, bits, lanes, bits) + for _, intrinsic := range []string{"mla", "mls"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.lane.nxv%di%d(, , , i32 immarg)\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits, lanes, bits) + } + for _, intrinsic := range []string{"sqdmulh", "sqrdmulh"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.lane.nxv%di%d(, , i32 immarg)\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits) + } + if bits != 64 { + for _, intrinsic := range []string{"cmla", "sqrdcmlah"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.lane.x.nxv%di%d(, , , i32 immarg, i32 immarg)\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits, lanes, bits) + } + } + for _, intrinsic := range []string{"sqrdmlah", "sqrdmlsh"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.lane.nxv%di%d(, , , i32 immarg)\n", lanes, bits, intrinsic, lanes, bits, lanes, bits, lanes, bits, lanes, bits) + } + } + if bits != 64 { + for _, intrinsic := range []string{"asr", "lsl", "lsr"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.wide.nxv%di%d(, , )\n", lanes, bits, intrinsic, lanes, bits, lanes, lanes, bits) + } + } + if bits != 64 { + for _, intrinsic := range []string{"cmpeq", "cmpge", "cmpgt", "cmphi", "cmphs", "cmpne"} { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.wide.nxv%di%d(, , )\n", lanes, intrinsic, lanes, bits, lanes, lanes, bits) + } + } + if lanes != 16 { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.convert.to.svbool.nxv%di1()\n", lanes, lanes) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.convert.from.svbool.nxv%di1()\n", lanes, lanes) + } + } + for _, sourceBits := range []int{8, 16, 32} { + sourceLanes := 128 / sourceBits + destinationBits := sourceBits * 2 + destinationLanes := 128 / destinationBits + for _, op := range arm64SVEMultiplyLongOps { + spec := arm64SVEMultiplyLongSpecs[op] + if spec.accumulate { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", destinationLanes, destinationBits, spec.intrinsic, destinationLanes, destinationBits, destinationLanes, destinationBits, sourceLanes, sourceBits, sourceLanes, sourceBits) + } else { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, )\n", destinationLanes, destinationBits, spec.intrinsic, destinationLanes, destinationBits, sourceLanes, sourceBits, sourceLanes, sourceBits) + } + } + for _, op := range arm64SVEMultiplyAccumulateLongOpsBySelector { + intrinsic := arm64SVEMultiplyAccumulateLongIntrinsics[op] + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, , )\n", destinationLanes, destinationBits, intrinsic, destinationLanes, destinationBits, destinationLanes, destinationBits, sourceLanes, sourceBits, sourceLanes, sourceBits) + } + if sourceBits != 8 { + for _, op := range arm64SVEMultiplyLongOps { + spec := arm64SVEMultiplyLongSpecs[op] + if spec.laneHBase == 0 { + continue + } + if spec.accumulate { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.lane.nxv%di%d(, , , i32 immarg)\n", destinationLanes, destinationBits, spec.intrinsic, destinationLanes, destinationBits, destinationLanes, destinationBits, sourceLanes, sourceBits, sourceLanes, sourceBits) + } else { + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.lane.nxv%di%d(, , i32 immarg)\n", destinationLanes, destinationBits, spec.intrinsic, destinationLanes, destinationBits, sourceLanes, sourceBits, sourceLanes, sourceBits) + } + } + for _, op := range arm64SVEMultiplyAccumulateLongOpsBySelector { + intrinsic := arm64SVEMultiplyAccumulateLongIntrinsics[op] + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.lane.nxv%di%d(, , , i32 immarg)\n", destinationLanes, destinationBits, intrinsic, destinationLanes, destinationBits, destinationLanes, destinationBits, sourceLanes, sourceBits, sourceLanes, sourceBits) + } + } + } + for _, elementBits := range []int{8, 16, 32, 64} { + lanes := 128 / elementBits + for _, op := range arm64SVEPermuteOpsByIndex { + intrinsic := arm64SVEPermuteIntrinsics[op] + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, )\n", lanes, elementBits, intrinsic, lanes, elementBits, lanes, elementBits, lanes, elementBits) + } + for _, op := range arm64SVEQPermuteOpsByIndex { + intrinsic := arm64SVEPermuteIntrinsics[op] + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv%di%d(, )\n", lanes, elementBits, intrinsic, lanes, elementBits, lanes, elementBits, lanes, elementBits) + } + } + for _, elementBits := range []int{16, 32, 64} { + lanes := 128 / elementBits + scalarType := map[int]string{16: "half", 32: "float", 64: "double"}[elementBits] + vectorType := fmt.Sprintf("", lanes, scalarType) + predicateType := fmt.Sprintf("", lanes) + mangle := fmt.Sprintf("nxv%d%s", lanes, map[int]string{16: "f16", 32: "f32", 64: "f64"}[elementBits]) + for _, intrinsic := range []string{"fabd", "faddp", "famax", "famin", "fmax", "fmin", "fmaxnm", "fminnm", "fmaxp", "fminp", "fmaxnmp", "fminnmp"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.%s(%s, %s, %s)\n", vectorType, intrinsic, mangle, predicateType, vectorType, vectorType) + } + for _, intrinsic := range []string{"fmaxv", "fminv", "fmaxnmv", "fminnmv"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.%s(%s, %s)\n", scalarType, intrinsic, mangle, predicateType, vectorType) + } + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.fadda.%s(%s, %s, %s)\n", scalarType, mangle, predicateType, scalarType, vectorType) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.faddv.%s(%s, %s)\n", scalarType, mangle, predicateType, vectorType) + for _, intrinsic := range []string{"faddqv", "fmaxqv", "fminqv", "fmaxnmqv", "fminnmqv"} { + fmt.Fprintf(b, "declare <%d x %s> @llvm.aarch64.sve.%s.v%d%s.%s(%s, %s)\n", lanes, scalarType, intrinsic, lanes, map[int]string{16: "f16", 32: "f32", 64: "f64"}[elementBits], mangle, predicateType, vectorType) + } + for _, intrinsic := range []string{"fabs", "fneg", "frecpx", "frint32x", "frint32z", "frint64x", "frint64z", "frinta", "frinti", "frintm", "frintn", "frintp", "frintx", "frintz", "fsqrt"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.%s(%s, %s, %s)\n", vectorType, intrinsic, mangle, vectorType, predicateType, vectorType) + } + for _, intrinsic := range []string{"frecpe.x", "frsqrte.x"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.%s(%s)\n", vectorType, intrinsic, mangle, vectorType) + } + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.fexpa.x.%s()\n", vectorType, mangle, lanes, elementBits) + fmt.Fprintf(b, "declare @llvm.aarch64.sve.flogb.%s(, %s, %s)\n", lanes, elementBits, mangle, lanes, elementBits, predicateType, vectorType) + for _, intrinsic := range []string{"fdiv", "fdivr"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.%s(%s, %s, %s)\n", vectorType, intrinsic, mangle, predicateType, vectorType, vectorType) + } + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.fscale.%s(%s, %s, )\n", vectorType, mangle, predicateType, vectorType, lanes, elementBits) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.fcadd.%s(%s, %s, %s, i32 immarg)\n", vectorType, mangle, predicateType, vectorType, vectorType) + for _, intrinsic := range []string{"frecps.x", "frsqrts.x"} { + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.%s(%s, %s)\n", vectorType, intrinsic, mangle, vectorType, vectorType) + } + for _, intrinsic := range []string{"rint", "trunc"} { + fmt.Fprintf(b, "declare %s @llvm.%s.%s(%s)\n", vectorType, intrinsic, mangle, vectorType) + } + if elementBits != 16 { + for _, integerBits := range []int{32, 64} { + fmt.Fprintf(b, "declare @llvm.fptosi.sat.nxv%di%d.%s(%s)\n", lanes, integerBits, lanes, integerBits, mangle, vectorType) + } + } + } + for _, op := range arm64SVEPermuteOpsByIndex { + intrinsic := arm64SVEPermuteIntrinsics[op] + "q" + fmt.Fprintf(b, "declare @llvm.aarch64.sve.%s.nxv2i64(, )\n", intrinsic) + } + b.WriteString("declare float @llvm.sqrt.f32(float)\n") + b.WriteString("declare double @llvm.sqrt.f64(double)\n") + b.WriteString("declare float @llvm.fma.f32(float, float, float)\n") + b.WriteString("declare double @llvm.fma.f64(double, double, double)\n") + b.WriteString("declare half @llvm.fma.f16(half, half, half)\n") + for _, intrinsic := range []string{"fabs", "roundeven", "ceil", "floor", "trunc", "round", "rint", "nearbyint"} { + b.WriteString("declare float @llvm." + intrinsic + ".f32(float)\n") + b.WriteString("declare double @llvm." + intrinsic + ".f64(double)\n") + } + b.WriteString("declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)\n") + b.WriteString("declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)\n") + b.WriteString("declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)\n") + b.WriteString("declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)\n") + b.WriteString("declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)\n") + for _, intrinsic := range []string{"fabs", "sqrt", "roundeven", "round", "rint", "nearbyint", "ceil", "floor", "trunc"} { + b.WriteString("declare <4 x half> @llvm." + intrinsic + ".v4f16(<4 x half>)\n") + b.WriteString("declare <8 x half> @llvm." + intrinsic + ".v8f16(<8 x half>)\n") + b.WriteString("declare <2 x float> @llvm." + intrinsic + ".v2f32(<2 x float>)\n") + b.WriteString("declare <4 x float> @llvm." + intrinsic + ".v4f32(<4 x float>)\n") + b.WriteString("declare <2 x double> @llvm." + intrinsic + ".v2f64(<2 x double>)\n") + } + for _, intrinsic := range []string{"fptosi.sat", "fptoui.sat"} { + for _, destination := range []string{"i32", "i64"} { + b.WriteString("declare " + destination + " @llvm." + intrinsic + "." + destination + ".f32(float)\n") + b.WriteString("declare " + destination + " @llvm." + intrinsic + "." + destination + ".f64(double)\n") + } + b.WriteString("declare <2 x i32> @llvm." + intrinsic + ".v2i32.v2f32(<2 x float>)\n") + b.WriteString("declare <4 x i32> @llvm." + intrinsic + ".v4i32.v4f32(<4 x float>)\n") + b.WriteString("declare <2 x i64> @llvm." + intrinsic + ".v2i64.v2f64(<2 x double>)\n") + } + for _, intrinsic := range []string{"maximum", "minimum", "maxnum", "minnum"} { + b.WriteString("declare half @llvm." + intrinsic + ".f16(half, half)\n") + b.WriteString("declare float @llvm." + intrinsic + ".f32(float, float)\n") + b.WriteString("declare double @llvm." + intrinsic + ".f64(double, double)\n") + b.WriteString("declare <4 x half> @llvm." + intrinsic + ".v4f16(<4 x half>, <4 x half>)\n") + b.WriteString("declare <8 x half> @llvm." + intrinsic + ".v8f16(<8 x half>, <8 x half>)\n") + b.WriteString("declare <2 x float> @llvm." + intrinsic + ".v2f32(<2 x float>, <2 x float>)\n") + b.WriteString("declare <4 x float> @llvm." + intrinsic + ".v4f32(<4 x float>, <4 x float>)\n") + b.WriteString("declare <2 x double> @llvm." + intrinsic + ".v2f64(<2 x double>, <2 x double>)\n") + } + for _, intrinsic := range []string{"sadd.sat", "uadd.sat", "ssub.sat", "usub.sat"} { + for _, vector := range []struct { + lanes int + bits int + }{ + {8, 8}, {16, 8}, {4, 16}, {8, 16}, {2, 32}, {4, 32}, {2, 64}, + } { + vectorType := fmt.Sprintf("<%d x i%d>", vector.lanes, vector.bits) + fmt.Fprintf(b, "declare %s @llvm.%s.v%di%d(%s, %s)\n", vectorType, intrinsic, vector.lanes, vector.bits, vectorType, vectorType) + } + } + for _, intrinsic := range []string{"sqadd.x", "uqadd.x", "sqsub.x", "uqsub.x"} { + for _, bits := range []int{8, 16, 32, 64} { + lanes := 128 / bits + vectorType := fmt.Sprintf("", lanes, bits) + fmt.Fprintf(b, "declare %s @llvm.aarch64.sve.%s.nxv%di%d(%s, %s)\n", vectorType, intrinsic, lanes, bits, vectorType, vectorType) + } + } // AArch64 CRC32 and CRC32C intrinsics. // Note: B/H forms take the data operand as i32 (low bits used). b.WriteString("declare i32 @llvm.aarch64.crc32b(i32, i32)\n") @@ -32,6 +794,21 @@ func emitARM64Prelude(b *strings.Builder) { } func translateFuncARM64(b *strings.Builder, fn Func, sig FuncSig, resolve func(string) string, sigs map[string]FuncSig, annotateSource bool) error { + var err error + var rawData []arm64RawDataBlob + fn, rawData, err = prepareARM64RawPCRelative(fn) + if err != nil { + return err + } + rawDataGlobals := make(map[string]string, len(rawData)) + for _, data := range rawData { + name := sig.Name + "." + data.label + ".raw_data" + rawDataGlobals[data.label] = name + fmt.Fprintf(b, "%s = private constant [%d x i8] %s, align %d\n", llvmGlobal(name), len(data.bytes), llvmI8ArrayInit(data.bytes), bestAlign(int64(len(data.bytes)))) + } + if len(rawData) != 0 { + b.WriteString("\n") + } fmt.Fprintf(b, "define %s %s(", sig.Ret, llvmGlobal(sig.Name)) for i, t := range sig.Args { if i > 0 { @@ -46,9 +823,11 @@ func translateFuncARM64(b *strings.Builder, fn Func, sig FuncSig, resolve func(s b.WriteString(" {\n") c := newARM64Ctx(b, fn, sig, resolve, sigs, annotateSource) + c.rawDataGlobals = rawDataGlobals if err := c.emitEntryAllocasAndArgInit(); err != nil { return err } + fmt.Fprintf(b, " br label %%%s\n", arm64LLVMBlockName(c.blocks[0].name)) if err := c.lowerBlocks(); err != nil { return err } @@ -72,9 +851,7 @@ func (c *arm64Ctx) lowerBlocks() error { for bi := 0; bi < len(c.blocks); bi++ { blk := c.blocks[bi] - if bi != 0 { - fmt.Fprintf(c.b, "\n%s:\n", arm64LLVMBlockName(blk.name)) - } + fmt.Fprintf(c.b, "\n%s:\n", arm64LLVMBlockName(blk.name)) terminated := false for _, ins := range blk.instrs { @@ -111,16 +888,11 @@ func (c *arm64Ctx) lowerInstr(bi int, ins Instr, emitBr arm64EmitBr, emitCondBr baseOp = baseOp[:dot] } op := Op(baseOp) - if strings.HasPrefix(rawOp, "SAVE_R19_TO_R28(") || - strings.HasPrefix(rawOp, "RESTORE_R19_TO_R28(") || - strings.HasPrefix(rawOp, "SAVE_F8_TO_F15(") || - strings.HasPrefix(rawOp, "RESTORE_F8_TO_F15(") { - return false, nil - } - switch op { - case OpTEXT, OpBYTE: + case OpTEXT: return false, nil + case OpBYTE: + return false, fmt.Errorf("arm64 BYTE cannot be lowered safely as a partial machine instruction: %q", ins.Raw) case OpRET: if len(ins.Args) == 1 && ins.Args[0].Kind == OpSym && strings.HasSuffix(ins.Args[0].Sym, "(SB)") { return true, c.tailCallAndRet(ins.Args[0]) @@ -130,15 +902,401 @@ func (c *arm64Ctx) lowerInstr(bi int, ins Instr, emitBr arm64EmitBr, emitCondBr } return true, c.lowerRET() case OpWORD: - return false, c.lowerRawWord(ins) - case "PCALIGN", "NO_LOCAL_POINTERS", "PCDATA", "FUNCDATA", "DMB", "DSB", "ISB", "DC", "PRFM", - "BREAK", "BRK", "UNDEF", "#UNDEF", "YIELD", "NOP", - "FLDPD", "FSTPD", "FMOVS", "STY", - "P256ADDINLINE", "P256MULBY2INLINE", "MOV", - "#IFDEF", "#ELSE", "#ENDIF": + rawErr := c.lowerRawWord(ins) + if rawErr == nil { + return false, nil + } else if !strings.Contains(rawErr.Error(), "unsupported ARM64 WORD encoding") { + return false, rawErr + } + decoded, err := decodeARM64RawWordInstruction(ins) + if err != nil { + if strings.Contains(err.Error(), "PC-relative") { + return false, err + } + return false, rawErr + } + return c.lowerInstr(bi, decoded, emitBr, emitCondBr) + case arm64RawDataOp: + return false, nil + case "END": + // Go's assembler end-of-file directive emits no instruction. return false, nil + case "PCALIGN", "NO_LOCAL_POINTERS", "PCDATA", "FUNCDATA": + return false, nil + } + if ok, term, err := c.lowerARM64Barrier(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64CacheMaintenance(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64Prefetch(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64Exception(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64Hint(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEAddress(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEAddressGeneration(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVECnt(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEDupImmediate(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEAdd(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEAddSub(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatAddSub(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatMultiply(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatMultiplyExtended(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatTrigMultiply(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatTrigMultiplyAdd(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatComplexMultiplyAccumulate(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatMultiplyAccumulate(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMultiplyAccumulate(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMADMSB(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEBFDOT(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEIntegerDot(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEAESMix(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEAESRound(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEOptionalCrypto(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVERevd(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPMUL(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPMULL(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPMULLPair(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVESaturatingMultiplyHigh(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEComplexMultiplyAccumulate(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEComplexAdd(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEXAR(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVESaturatingRoundingMultiplyAccumulateHigh(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatMinMax(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatPredicatedPairwise(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatReciprocalStep(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatExponent(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatImmediate(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatDivideScale(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMixedSaturatingAdd(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatComplexAdd(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEDupW(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEDupQ(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEDupM(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFDOT(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVECDOT(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVELUTI(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEWideningFloatMLA(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMultiNarrow(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatNarrowConversion(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEBFloatArithmetic(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEBFloatMLA(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFloatUnary(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEIntegerUnary(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicateLogical(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicateBreak(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicatePermute(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicateSelect(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicateState(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicateIterate(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicatePosition(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicateCounter(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicateWhile(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicateIncDec(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPredicateMemory(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEWholeVectorMemory(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEVectorPrefetch(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVENonTemporalMemory(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEOrdinaryMemory(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEStructuredMemory(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEFirstFaultMemory(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVENonFaultingMemory(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEReplicateMemory(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64CTERM(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPMOV(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEIndex(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEInsert(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVELast(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVECLast(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVECompact(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEExpand(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMOVPRFX(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEEXT(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVESplice(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVECopy(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEConvert(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVECompare(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVECharacterMatch(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEHistogram(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMinMax(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEIntegerReduction(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEAddReduction(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEWideningAddSub(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEShiftLong(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEAbsoluteDifference(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEHalvingAddSub(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEDivide(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVETernaryBitwise(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEEORInterleave(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEBitPermute(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVECarryLong(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEClamp(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEUnpack(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVESaturatingNarrow(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEShiftNarrow(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVESaturatingShiftNarrow(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVELSR(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEExtraShift(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMatrixMultiply(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPairwiseTail(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMultiplyAddTail(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEVectorPredicateIncDec(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVESelect(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMultiply(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMultiplyHigh(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVESaturatingShift(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEEOR(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVETable(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVETableExtension(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEUMULLB(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEMultiplyAccumulateLong(op, ins); ok { + return term, err + } + if ok, term, err := c.lowerARM64SVEPermute(op, ins); ok { + return term, err } + if ok, term, err := c.lowerPCRelativeAddress(bi, op, ins); ok { + return term, err + } if ok, term, err := c.lowerData(op, postInc, ins); ok { return term, err } @@ -170,32 +1328,38 @@ func (c *arm64Ctx) lowerRET() error { // Prefer classic Go asm return slots if present; many stdlib asm functions // never materialize the return value in R0 and only store to ret+off(FP). if len(c.fpResults) == 0 { - r0, err := c.loadReg(Reg("R0")) + if c.sig.Ret == Void { + c.b.WriteString(" ret void\n") + return nil + } + cursor := arm64ABIRegisterCursor{} + if fields, aggregate := parseLiteralStructFields(c.sig.Ret); aggregate { + result := "undef" + for fieldIndex, fieldType := range fields { + reg, err := cursor.next(fieldType) + if err != nil { + return fmt.Errorf("arm64 RET result field %d: %w", fieldIndex, err) + } + value, err := c.loadABIRegisterValue(reg, fieldType) + if err != nil { + return err + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertvalue %s %s, %s %s, %d\n", inserted, c.sig.Ret, result, fieldType, value, fieldIndex) + result = "%" + inserted + } + fmt.Fprintf(c.b, " ret %s %s\n", c.sig.Ret, result) + return nil + } + reg, err := cursor.next(c.sig.Ret) if err != nil { - return err + return fmt.Errorf("arm64 RET unsupported register result type %s", c.sig.Ret) } - switch c.sig.Ret { - case Void: - c.b.WriteString(" ret void\n") - case I1: - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i1\n", t, r0) - fmt.Fprintf(c.b, " ret i1 %%%s\n", t) - case I8: - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i8\n", t, r0) - fmt.Fprintf(c.b, " ret i8 %%%s\n", t) - case I16: - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i16\n", t, r0) - fmt.Fprintf(c.b, " ret i16 %%%s\n", t) - case I32: - t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", t, r0) - fmt.Fprintf(c.b, " ret i32 %%%s\n", t) - default: - fmt.Fprintf(c.b, " ret %s %s\n", c.sig.Ret, r0) + value, err := c.loadABIRegisterValue(reg, c.sig.Ret) + if err != nil { + return err } + fmt.Fprintf(c.b, " ret %s %s\n", c.sig.Ret, value) return nil } diff --git a/arm_blocks.go b/arm_blocks.go index ff67347d..b4d44682 100644 --- a/arm_blocks.go +++ b/arm_blocks.go @@ -161,7 +161,7 @@ func armDecodeOp(raw string) (base string, cond string, postInc bool, setFlags b base = parts[0] for _, p := range parts[1:] { switch p { - case "P": + case "P", "PW", "WP": postInc = true case "S": setFlags = true diff --git a/arm_caller_sp_test.go b/arm_caller_sp_test.go new file mode 100644 index 00000000..4648d016 --- /dev/null +++ b/arm_caller_sp_test.go @@ -0,0 +1,52 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARMCallerSPPseudoAddress(t *testing.T) { + src := `TEXT callerSP(SB),NOSPLIT,$8-0 + MOVW $sp-4(FP), R7 + RET +` + file, err := Parse(ArchARM, src) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "arm", + TargetTriple: "armv5te-unknown-linux-gnueabi", + Sigs: map[string]FuncSig{ + "callerSP": {Name: "callerSP", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "store i32 0, ptr %reg_R7") { + t.Fatalf("caller-SP context placeholder was not written to R7:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv5te-unknown-linux-gnueabi", "arm-caller-sp.ll", "arm-caller-sp.o", ir) +} + +func TestTranslateARMCallerSPPseudoAddressRejectsOtherOffsets(t *testing.T) { + src := "TEXT callerSP(SB),NOSPLIT,$8-0\n\tMOVW $sp-8(FP), R7\n\tRET\n" + file, err := Parse(ArchARM, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + Goarch: "arm", + TargetTriple: "armv5te-unknown-linux-gnueabi", + Sigs: map[string]FuncSig{ + "callerSP": {Name: "callerSP", Ret: Void}, + }, + }); err == nil { + t.Fatal("Translate unexpectedly accepted an unknown caller-SP offset") + } +} diff --git a/arm_ctx.go b/arm_ctx.go index 650be718..2aef7969 100644 --- a/arm_ctx.go +++ b/arm_ctx.go @@ -114,6 +114,118 @@ func (c *armCtx) scanUsedRegs() { } for _, blk := range c.blocks { for _, ins := range blk.instrs { + if ins.Op == OpWORD && len(ins.Args) == 1 && ins.Args[0].Kind == OpImm { + if move, ok := decodeARMRawVFPMove(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(move.source, move.bits)) + markReg(armRawVFPBackingReg(move.destination, move.bits)) + } + if pairwise, ok := decodeARMRawNEONPairwiseMinMax(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(pairwise.lhs, 64)) + markReg(armRawVFPBackingReg(pairwise.rhs, 64)) + markReg(armRawVFPBackingReg(pairwise.destination, 64)) + } + if minmax, ok := decodeARMRawNEONMinMax(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(minmax.lhs, 64)) + markReg(armRawVFPBackingReg(minmax.rhs, 64)) + markReg(armRawVFPBackingReg(minmax.destination, 64)) + if minmax.quad { + markReg(armRawVFPBackingReg(minmax.lhs+1, 64)) + markReg(armRawVFPBackingReg(minmax.rhs+1, 64)) + markReg(armRawVFPBackingReg(minmax.destination+1, 64)) + } + } + if status, ok := decodeARMRawVFPStatusTransfer(uint32(ins.Args[0].Imm)); ok && !status.toFlags { + markReg(Reg(fmt.Sprintf("R%d", status.core))) + } + if arithmetic, ok := decodeARMRawVFPScalarArithmetic(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(arithmetic.lhs, arithmetic.bits)) + markReg(armRawVFPBackingReg(arithmetic.rhs, arithmetic.bits)) + markReg(armRawVFPBackingReg(arithmetic.destination, arithmetic.bits)) + } + if multiply, ok := decodeARMRawNEONMultiplyLane(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(multiply.scalar, 64)) + markReg(armRawVFPBackingReg(multiply.lhs, 64)) + markReg(armRawVFPBackingReg(multiply.destination, 64)) + if multiply.quad { + markReg(armRawVFPBackingReg(multiply.lhs+1, 64)) + markReg(armRawVFPBackingReg(multiply.destination+1, 64)) + } + } + if conversion, ok := decodeARMRawNEONConvertFloat32(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(conversion.source, 64)) + markReg(armRawVFPBackingReg(conversion.destination, 64)) + if conversion.quad { + markReg(armRawVFPBackingReg(conversion.source+1, 64)) + markReg(armRawVFPBackingReg(conversion.destination+1, 64)) + } + } + if moveLong, ok := decodeARMRawNEONMoveLong(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(moveLong.source, 64)) + markReg(armRawVFPBackingReg(moveLong.destination, 64)) + markReg(armRawVFPBackingReg(moveLong.destination+1, 64)) + } + if widening, ok := decodeARMRawNEONWideningSubtract(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(widening.lhs, 64)) + markReg(armRawVFPBackingReg(widening.rhs, 64)) + markReg(armRawVFPBackingReg(widening.destination, 64)) + markReg(armRawVFPBackingReg(widening.destination+1, 64)) + } + if duplicate, ok := decodeARMRawNEONDup(uint32(ins.Args[0].Imm)); ok { + markReg(Reg(fmt.Sprintf("R%d", duplicate.core))) + markReg(armRawVFPBackingReg(duplicate.destination, 64)) + if duplicate.quad { + markReg(armRawVFPBackingReg(duplicate.destination+1, 64)) + } + } + if immediate, ok := decodeARMRawVFPImmediate(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(immediate.destination, immediate.bits)) + } + if decoded, err := decodeARMRawWordInstruction(ins); err == nil { + for _, op := range decoded.Args { + markOp(op) + if single, ok := armSingleOperandNumber(op); ok { + markReg(armRawVFPBackingReg(single, 32)) + } + } + } + if compare, ok := decodeARMRawVFPCompare(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(compare.lhs, compare.bits)) + if !compare.zeroRHS { + markReg(armRawVFPBackingReg(compare.rhs, compare.bits)) + } + } + if pair, ok := decodeARMRawVMOVPair(uint32(ins.Args[0].Imm)); ok { + markReg(Reg(fmt.Sprintf("R%d", pair.firstCore))) + markReg(Reg(fmt.Sprintf("R%d", pair.secondCore))) + markReg(armRawVFPBackingReg(pair.firstSingle, 32)) + markReg(armRawVFPBackingReg(pair.firstSingle+1, 32)) + } + if multiple, ok := decodeARMRawVFPMultiple(uint32(ins.Args[0].Imm)); ok { + markReg(Reg(fmt.Sprintf("R%d", multiple.base))) + for register := multiple.first; register < multiple.first+multiple.count; register++ { + markReg(armRawVFPBackingReg(register, multiple.bits)) + } + } + if structure, ok := decodeARMRawNEONStructureOne(uint32(ins.Args[0].Imm)); ok { + markReg(Reg(fmt.Sprintf("R%d", structure.base))) + if structure.offset != 13 && structure.offset != 15 { + markReg(Reg(fmt.Sprintf("R%d", structure.offset))) + } + for register := structure.first; register < structure.first+structure.count; register++ { + markReg(armRawVFPBackingReg(register, 64)) + } + } + if logical, ok := decodeARMRawNEONEOR(uint32(ins.Args[0].Imm)); ok { + markReg(armRawVFPBackingReg(logical.lhs, 64)) + markReg(armRawVFPBackingReg(logical.rhs, 64)) + markReg(armRawVFPBackingReg(logical.destination, 64)) + if logical.quad { + markReg(armRawVFPBackingReg(logical.lhs+1, 64)) + markReg(armRawVFPBackingReg(logical.rhs+1, 64)) + markReg(armRawVFPBackingReg(logical.destination+1, 64)) + } + } + } for _, op := range ins.Args { markOp(op) } @@ -194,9 +306,9 @@ func (c *armCtx) emitEntryAllocasAndArgInit() error { return fmt.Errorf("arm: FP param slot +%d(FP) invalid arg index %d", p.Offset, p.Index) } value := fmt.Sprintf("%%arg%d", p.Index) - if p.Field >= 0 { + if fields := frameSlotFields(p); len(fields) != 0 { extracted := c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", extracted, c.sig.Args[p.Index], value, p.Field) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %s%s\n", extracted, c.sig.Args[p.Index], value, frameSlotExtractSuffix(p)) value = "%" + extracted } name := fmt.Sprintf("%%fp_arg_%d", p.Offset) diff --git a/arm_deep_coverage_test.go b/arm_deep_coverage_test.go index 598d3f23..222da1b7 100644 --- a/arm_deep_coverage_test.go +++ b/arm_deep_coverage_test.go @@ -360,7 +360,7 @@ func TestARMArithCoverageDeep(t *testing.T) { if err := c.lowerARMMULAWT("", Instr{Raw: "MULAWT R0, R1, R2", Args: []Operand{{Kind: OpReg, Reg: "R0"}, {Kind: OpReg, Reg: "R1"}, {Kind: OpReg, Reg: "R2"}}}); err == nil { t.Fatalf("lowerARMMULAWT(invalid) unexpectedly succeeded") } - if err := c.lowerARMDIVUHW("", Instr{Raw: "DIVUHW R0, R1", Args: []Operand{{Kind: OpReg, Reg: "R0"}, {Kind: OpReg, Reg: "R1"}}}); err == nil { + if err := c.lowerARMDIVUHW("", Instr{Raw: "DIVUHW R0", Args: []Operand{{Kind: OpReg, Reg: "R0"}}}); err == nil { t.Fatalf("lowerARMDIVUHW(invalid) unexpectedly succeeded") } if err := c.lowerARMCLZ("", Instr{Raw: "CLZ R0, $1", Args: []Operand{{Kind: OpReg, Reg: "R0"}, {Kind: OpImm, Imm: 1}}}); err == nil { @@ -443,10 +443,10 @@ func TestARMBranchMovmAndSyscallCoverage(t *testing.T) { } c2, _ := newARMCtxForTest(t, FuncSig{Name: "example.callers", Ret: I32}, map[string]FuncSig{ - "example.ret32": {Name: "example.ret32", Ret: I32}, - "example.retVoid": {Name: "example.retVoid", Ret: Void}, - "example.retBad": {Name: "example.retBad", Ret: LLVMType("vector")}, - "example.tail64": {Name: "example.tail64", Ret: I64}, + "example.ret32": {Name: "example.ret32", Ret: I32}, + "example.retVoid": {Name: "example.retVoid", Ret: Void}, + "example.retBad": {Name: "example.retBad", Ret: LLVMType("vector")}, + "example.tailFloat": {Name: "example.tailFloat", Ret: LLVMType("double")}, }) if err := c2.callSym(Operand{Kind: OpSym, Sym: "ret32(SB)"}); err != nil { t.Fatalf("callSym(ret32) error = %v", err) @@ -472,7 +472,7 @@ func TestARMBranchMovmAndSyscallCoverage(t *testing.T) { if err := c2.tailCallAndRet(Operand{Kind: OpSym, Sym: "missing(SB)"}); err != nil { t.Fatalf("tailCallAndRet(missing sig) error = %v", err) } - if err := c2.tailCallAndRet(Operand{Kind: OpSym, Sym: "tail64(SB)"}); err == nil { + if err := c2.tailCallAndRet(Operand{Kind: OpSym, Sym: "tailFloat(SB)"}); err == nil { t.Fatalf("tailCallAndRet(mismatch) unexpectedly succeeded") } @@ -496,6 +496,17 @@ func TestARMBranchMovmAndSyscallCoverage(t *testing.T) { t.Fatalf("tailCallAndRet(ptr -> i32) output:\n%s", got) } + floatSig := FuncSig{Name: "example.floatcaller", Args: []LLVMType{LLVMType("float")}, Ret: LLVMType("float")} + cTailFloat, bTailFloat := newARMCtxForTest(t, floatSig, map[string]FuncSig{ + "example.floatcallee": {Name: "example.floatcallee", Args: []LLVMType{LLVMType("float")}, Ret: LLVMType("float")}, + }) + if err := cTailFloat.tailCallAndRet(Operand{Kind: OpSym, Sym: "floatcallee(SB)"}); err != nil { + t.Fatalf("tailCallAndRet(identical float signature) error = %v", err) + } + if got := bTailFloat.String(); !strings.Contains(got, `call float @"example.floatcallee"(float %arg0)`) || !strings.Contains(got, "ret float") { + t.Fatalf("tailCallAndRet(identical float signature) output:\n%s", got) + } + out := b.String() for _, want := range []string{ `call void @"example.tail"()`, @@ -510,7 +521,7 @@ func TestARMBranchMovmAndSyscallCoverage(t *testing.T) { } } -func TestTranslateARMLinearCoverageDeep(t *testing.T) { +func TestTranslateARMStraightLineCoverageDeep(t *testing.T) { ll := translateARMForTest(t, `TEXT ·linear(SB),NOSPLIT,$0-0 MOVB $1, R1 MOVBU $2, R2 @@ -531,9 +542,9 @@ func TestTranslateARMLinearCoverageDeep(t *testing.T) { }, }) for _, want := range []string{ - "trunc i64 1 to i8", - "zext i8", - "add i32 %arg0, %arg1", + "store i32 1", + "store i32 2", + "add i32", "sub i32", "and i32", "or i32", diff --git a/arm_ecosystem_test.go b/arm_ecosystem_test.go new file mode 100644 index 00000000..b4534959 --- /dev/null +++ b/arm_ecosystem_test.go @@ -0,0 +1,584 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func translateARMCompleteForms(t *testing.T, src string, sigs map[string]FuncSig) string { + t.Helper() + file, err := Parse(ArchARM, src) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: sigs, + }) + if err != nil { + t.Fatal(err) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-complete-forms.ll", "arm-complete-forms.o", ll) + return ll +} + +func rejectARMFormsOutsideGo127Optabs(t *testing.T, instructions []string) { + t.Helper() + for _, instruction := range instructions { + t.Run(strings.NewReplacer(" ", "_", "(", "_", ")", "_").Replace(instruction), func(t *testing.T) { + file, err := Parse(ArchARM, "TEXT bad(SB),0,$0-0\n\t"+instruction+"\n\tRET\n") + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM optabs", instruction) + } + }) + } +} + +func TestTranslateARMScalarFloatMoveFamilyCompleteGo127Forms(t *testing.T) { + ll := translateARMCompleteForms(t, ` +TEXT floatmoves(SB),0,$0-0 + CMP R0, R0 + MOVF F0, F1 + MOVD F1, F2 + MOVF $0.5, F3 + MOVD $0.5, F4 + MOVF F0, 4(R1) + MOVF 4(R1), F0 + MOVD F1, 8(R1) + MOVD 8(R1), F1 + MOVF F0, 8192(R1) + MOVF 8192(R1), F0 + MOVD F1, 8192(R1) + MOVD 8192(R1), F1 + MOVF F0, float32global(SB) + MOVF float32global(SB), F0 + MOVD F1, float64global(SB) + MOVD float64global(SB), F1 + MOVF.EQ F0, F1 + MOVD.NE F1, F2 + MOVF.P F0, 4(R1) + MOVD.W 8(R1), F0 + MOVF.PW F0, 4(R1) + MOVD.U 8(R1), F0 + RET + +TEXT floatframe(SB),0,$0-8 + MOVF x+0(FP), F0 + MOVF F0, ret+4(FP) + RET + +TEXT doubleframe(SB),0,$0-16 + MOVD x+0(FP), F0 + MOVD F0, ret+8(FP) + RET +`, map[string]FuncSig{ + "floatmoves": {Name: "floatmoves", Ret: Void}, + "floatframe": { + Name: "floatframe", Args: []LLVMType{LLVMType("float")}, Ret: LLVMType("float"), + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: LLVMType("float"), Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 4, Type: LLVMType("float"), Index: 0, Field: -1}}, + }, + }, + "doubleframe": { + Name: "doubleframe", Args: []LLVMType{LLVMType("double")}, Ret: LLVMType("double"), + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: LLVMType("double"), Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 8, Type: LLVMType("double"), Index: 0, Field: -1}}, + }, + }, + }) + for _, want := range []string{ + "load i32", "store i32", "load i64", "store i64", "add i32", + "load i32, ptr %fp_arg_0", "load i64, ptr %fp_arg_0", "br i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM float-move family IR missing %q:\n%s", want, ll) + } + } +} + +func TestTranslateARMScalarFloatMoveFamilyRejectsFormsOutsideGo127Optabs(t *testing.T) { + rejectARMFormsOutsideGo127Optabs(t, []string{ + "MOVF R0, F0", + "MOVD F0, R0", + "MOVF (R0), (R1)", + "MOVD $0.5, (R0)", + "MOVF F0", + "MOVD.S F0, F1", + "MOVF.P F0, F1", + }) +} + +func TestTranslateARMFloatUnaryAndConvertFamilyCompleteGo127Forms(t *testing.T) { + ll := translateARMCompleteForms(t, ` +TEXT floatunary(SB),0,$0-0 + CMP R0, R0 + NEGF F0, F1 + NEGD.EQ F1, F2 + ABSF F2, F3 + ABSD.NE F3, F4 + SQRTF F4, F5 + SQRTD F5, F6 + MOVFD F6, F7 + MOVDF F7, F0 + RET +`, map[string]FuncSig{"floatunary": {Name: "floatunary", Ret: Void}}) + for _, want := range []string{ + "fneg float", "fneg double", "@llvm.fabs.f32", "@llvm.fabs.f64", + "@llvm.sqrt.f32", "@llvm.sqrt.f64", "fpext float", "fptrunc double", "br i1", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM float unary/convert family IR missing %q:\n%s", want, ll) + } + } +} + +func TestTranslateARMFloatUnaryAndConvertFamilyRejectsFormsOutsideGo127Optabs(t *testing.T) { + rejectARMFormsOutsideGo127Optabs(t, []string{ + "SQRTD F0", + "SQRTF F0, R1", + "ABSD (R0), F1", + "ABSF F0, (R1)", + "NEGD F0, F1, F2", + "MOVFD.S F0, F1", + "MOVDF.P F0, F1", + }) +} + +func TestTranslateARMScalarFloatArithmeticFamilyCompleteGo127Forms(t *testing.T) { + // Go 1.27 routes this whole family through AADDF's two optab rows. Plain + // arithmetic permits both Fsrc,Fdst and Fsrc1,Fsrc2,Fdst; accumulating + // variants require the explicit three-register form. + ll := translateARMCompleteForms(t, ` +TEXT floatarithmetic(SB),0,$0-0 + CMP R0, R0 + ADDF F0, F1 + ADDD.EQ F0, F1, F2 + SUBF F0, F1 + SUBD.NE F0, F1, F2 + MULF F0, F1 + MULD F0, F1, F2 + NMULF F0, F1 + NMULD F0, F1, F2 + DIVF F0, F1 + DIVD F0, F1, F2 + MULAF F0, F1, F2 + MULAD F0, F1, F2 + MULSF F0, F1, F2 + MULSD F0, F1, F2 + NMULAF F0, F1, F2 + NMULAD F0, F1, F2 + NMULSF F0, F1, F2 + NMULSD F0, F1, F2 + FMULAF F0, F1, F2 + FMULAD F0, F1, F2 + FMULSF F0, F1, F2 + FMULSD F0, F1, F2 + FNMULAF F0, F1, F2 + FNMULAD F0, F1, F2 + FNMULSF F0, F1, F2 + FNMULSD F0, F1, F2 + RET +`, map[string]FuncSig{"floatarithmetic": {Name: "floatarithmetic", Ret: Void}}) + for _, want := range []string{"fadd float", "fadd double", "fsub float", "fmul float", "fdiv float", "fneg float", "br i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM scalar float-arithmetic family IR missing %q:\n%s", want, ll) + } + } +} + +func TestTranslateARMScalarFloatArithmeticFamilyRejectsFormsOutsideGo127Optabs(t *testing.T) { + rejectARMFormsOutsideGo127Optabs(t, []string{ + "ADDF F0", + "ADDF R0, F1", + "ADDD F0, R1", + "SUBF F0, F1, F2, F3", + "MULAF F0, F1", + "NMULSD F0, F1", + "FMULAF F0, F1", + "FNMULSD F0, F1", + "DIVF F0, (R1)", + "ADDF.S F0, F1", + }) +} + +func TestTranslateARMWordFloatConversionFamilyCompleteGo127Forms(t *testing.T) { + // MOV{W}{F,D} converts signed/unsigned 32-bit integers to floating point; + // MOV{F,D}W truncates floating point to signed/unsigned 32-bit integers. + // Go's optab permits the integer bits to live in either an R or F register. + ll := translateARMCompleteForms(t, ` +TEXT wordfloatconversions(SB),0,$0-0 + CMP R0, R0 + MOVWF R0, F0 + MOVWF F0, F1 + MOVWF.U R1, F2 + MOVWF.EQ F2, F3 + MOVWD R2, F4 + MOVWD F4, F5 + MOVWD.U R3, F6 + MOVWD.NE F6, F7 + MOVFW F0, R4 + MOVFW F1, F2 + MOVFW.U F2, R5 + MOVFW.EQ F3, F4 + MOVDW F4, R6 + MOVDW F5, F6 + MOVDW.U F6, R7 + MOVDW.NE F7, F8 + RET +`, map[string]FuncSig{"wordfloatconversions": {Name: "wordfloatconversions", Ret: Void}}) + for _, want := range []string{"sitofp i32", "uitofp i32", "fptosi float", "fptoui float", "fptosi double", "br i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM word/float conversion family IR missing %q:\n%s", want, ll) + } + } +} + +func TestTranslateARMWordFloatConversionFamilyRejectsFormsOutsideGo127Optabs(t *testing.T) { + rejectARMFormsOutsideGo127Optabs(t, []string{ + "MOVWF R0", + "MOVWF (R0), F0", + "MOVWF R0, R1", + "MOVWD F0, R0", + "MOVFW R0, F0", + "MOVFW F0, (R1)", + "MOVDW F0, F1, F2", + "MOVFW.P F0, R0", + "MOVWD.S R0, F0", + }) +} + +func TestTranslateARMWordRegisterBitTransferSubfamilyCompleteGo127Forms(t *testing.T) { + ll := translateARMCompleteForms(t, ` +TEXT wordregisterbittransfers(SB),0,$0-0 + CMP R0, R0 + MOVW R0, F0 + MOVW F0, R1 + MOVW.EQ R2, F3 + MOVW.NE F3, R4 + RET +`, map[string]FuncSig{"wordregisterbittransfers": {Name: "wordregisterbittransfers", Ret: Void}}) + for _, want := range []string{"trunc i64", "zext i32", "br i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM MOVW R/F bit-transfer IR missing %q:\n%s", want, ll) + } + } +} + +func TestTranslateARMWordRegisterBitTransferSubfamilyRejectsNonGoForms(t *testing.T) { + rejectARMFormsOutsideGo127Optabs(t, []string{ + "MOVW $1, F0", + "MOVW (R0), F0", + "MOVW F0, (R1)", + "MOVW F0, F1", + "MOVW.S R0, F0", + }) +} + +func TestTranslateARMPreloadFamilyCompleteGo127Forms(t *testing.T) { + ll := translateARMCompleteForms(t, ` +TEXT preloadforms(SB),0,$0-0 + CMP R0, R0 + PLD (R0) + PLD 4095(R1) + PLD -4095(R2) + PLD (2*64)(R3) + PLD.EQ 64(R4) + RET +`, map[string]FuncSig{"preloadforms": {Name: "preloadforms", Ret: Void}}) + if !strings.Contains(ll, "@llvm.prefetch.p0") || !strings.Contains(ll, "br i1") { + t.Fatalf("ARM PLD family IR is incomplete:\n%s", ll) + } +} + +func TestTranslateARMPreloadFamilyRejectsFormsOutsideGo127Optabs(t *testing.T) { + rejectARMFormsOutsideGo127Optabs(t, []string{ + "PLD", + "PLD R0", + "PLD 4096(R0)", + "PLD -4096(R0)", + "PLD (R0)(R1)", + "PLD source(SB)", + "PLD.P (R0)", + "PLD.W (R0)", + "PLD.U (R0)", + "PLD.S (R0)", + }) +} + +func TestTranslateARMScalarFloatCompareFamilyCompleteGo127Forms(t *testing.T) { + ll := translateARMCompleteForms(t, ` +TEXT floatcompareforms(SB),0,$0-0 + CMP R0, R0 + CMPF F0 + BGT compare1 +compare1: + CMPF F0, F1 + BLT compare2 +compare2: + CMPD F2 + BEQ compare3 +compare3: + CMPD.EQ F2, F3 + BVS done +done: + RET +`, map[string]FuncSig{"floatcompareforms": {Name: "floatcompareforms", Ret: Void}}) + for _, want := range []string{"fcmp oeq float", "fcmp olt float", "fcmp uge float", "fcmp uno float", "fcmp oeq double"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM scalar float-compare family IR missing %q:\n%s", want, ll) + } + } +} + +func TestTranslateARMScalarFloatCompareFamilyRejectsFormsOutsideGo127Optabs(t *testing.T) { + rejectARMFormsOutsideGo127Optabs(t, []string{ + "CMPF", + "CMPF R0", + "CMPF F0, R1", + "CMPD (R0)", + "CMPD F0, F1, F2", + "CMPF.S F0, F1", + }) +} + +func TestTranslateARMRawVFPCompareAndVMRSFamily(t *testing.T) { + ll := translateARMCompleteForms(t, ` +TEXT rawvfpcompare(SB),0,$0-0 + WORD $0xeeb56ac0 // VCMPE.F32 F6, #0 + WORD $0xeef1fa10 // VMRS APSR_nzcv, FPSCR + BGT rawgreater +rawgreater: + WORD $0xeeb42ac0 // VCMPE.F32 F2, F0 + WORD $0xeef1fa10 + BLT done + WORD $0xeeb41ac4 // VCMPE.F32 S2, S8 (Go F1, F4) + WORD $0xeef1fa10 + MOVF.GT F1, F4 +done: + RET +`, map[string]FuncSig{"rawvfpcompare": {Name: "rawvfpcompare", Ret: Void}}) + if !strings.Contains(ll, "fcmp") || !strings.Contains(ll, "br i1") { + t.Fatalf("raw ARM VFP compare/VMRS sequence was not modeled:\n%s", ll) + } +} + +func TestDecodeARMRawVFPCompareFamily(t *testing.T) { + tests := []struct { + name string + word uint32 + bits int + zeroRHS bool + }{ + {"vcmp-f32-register", 0xeeb40a40, 32, false}, + {"vcmpe-f32-register", 0xeeb40ac0, 32, false}, + {"vcmp-f32-zero", 0xeeb50a40, 32, true}, + {"vcmpe-f32-zero", 0xeeb50ac0, 32, true}, + {"vcmp-f64-register", 0xeeb40b40, 64, false}, + {"vcmpe-f64-register", 0xeeb40bc0, 64, false}, + {"vcmp-f64-zero", 0xeeb50b40, 64, true}, + {"vcmpe-f64-zero", 0xeeb50bc0, 64, true}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + word := test.word | 3<<12 + if !test.zeroRHS { + word |= 2 + } + decoded, ok := decodeARMRawVFPCompare(word) + if !ok { + t.Fatalf("decodeARMRawVFPCompare(%#08x) failed", test.word) + } + wantLHS := 6 + if test.bits == 64 { + wantLHS = 3 + } + if decoded.bits != test.bits || decoded.zeroRHS != test.zeroRHS || decoded.lhs != wantLHS { + t.Fatalf("decodeARMRawVFPCompare(%#08x) = %#v", test.word, decoded) + } + if test.zeroRHS && decoded.rhs != 0 { + t.Fatalf("zero comparison rhs = %d, want zero encoding", decoded.rhs) + } + }) + } + for _, word := range []uint32{ + 0xeeb50a41, // zero form must encode Vm=0. + 0xeeb50a60, // zero form must also have M=0. + 0xfeb40a40, // unconditional/reserved condition field. + } { + if decoded, ok := decodeARMRawVFPCompare(word); ok { + t.Fatalf("decodeARMRawVFPCompare(%#08x) = %#v, want rejected", word, decoded) + } + } +} + +func TestTranslateARMDivModFamilyCompleteGo127Forms(t *testing.T) { + ll := translateARMCompleteForms(t, ` +TEXT divmod(SB),0,$0-0 + CMP R0, R0 + DIV R0, R1 + DIV R0, R1, R2 + DIVU R0, R1 + DIVU.EQ R0, R1, R2 + MOD R0, R1 + MOD.NE R0, R1, R2 + MODU R0, R1 + MODU R0, R1, R2 + RET +`, map[string]FuncSig{"divmod": {Name: "divmod", Ret: Void}}) + for _, want := range []string{"sdiv i32", "udiv i32", "srem i32", "urem i32", "select i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM div/mod family IR missing %q:\n%s", want, ll) + } + } +} + +func TestTranslateARMDivModFamilyRejectsFormsOutsideGo127Optabs(t *testing.T) { + rejectARMFormsOutsideGo127Optabs(t, []string{ + "DIV $2, R1", + "DIV (R0), R1", + "DIV R0, (R1)", + "DIV R0, R1, (R2)", + "DIVU R0", + "MODU R0, R1, R2, R3", + "MOD.S R0, R1", + }) +} + +func TestTranslateARMFrameAddressIncludesParametersAndInteriorOffsets(t *testing.T) { + ll := translateARMCompleteForms(t, ` +TEXT frameaddr(SB),0,$0-12 + MOVW $word+0(FP), R0 + MOVW $wordhi+4(FP), R1 + MOVW $ret+8(FP), R2 + RET +`, map[string]FuncSig{ + "frameaddr": { + Name: "frameaddr", Args: []LLVMType{I64}, Ret: I32, + Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: I64, Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 8, Type: I32, Index: 0, Field: -1}}, + }, + }, + }) + for _, want := range []string{"ptrtoint ptr %fp_arg_0 to i32", "getelementptr i8, ptr %fp_arg_0, i32 4", "ptrtoint ptr %fp_ret_0 to i32"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM frame-address IR missing %q:\n%s", want, ll) + } + } +} + +func TestTranslateARMExplicitShiftFamily(t *testing.T) { + file, err := Parse(ArchARM, ` +TEXT shifts(SB),NOSPLIT,$0-0 + CMP $0, R0 + SLL $3, R0 + SLL $5, R0, R1 + SLL R2, R1 + SLL R2, R1, R3 + SRL $3, R3 + SRL $5, R3, R4 + SRL R2, R4 + SRL R2, R4, R5 + SRA $3, R5 + SRA $5, R5, R6 + SRA R2, R6 + SRA.EQ.S R2, R6, R7 + RET +`) + if err != nil { + t.Fatal(err) + } + ll, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"shifts": {Name: "shifts", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"shl i32", "lshr i32", "ashr i32", "and i32", "icmp ugt i32", "select i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("shift-family IR missing %q:\n%s", want, ll) + } + } +} + +func TestTranslateARMExplicitShiftFamilyRejectsNonGoForms(t *testing.T) { + for _, instruction := range []string{ + "SLL R0", + "SRL $257, R0", + "SRA $1, $2, R0", + "SLL $1, R0, 0(R1)", + "SRL R0, R1, R2, R3", + } { + file, err := Parse(ArchARM, "TEXT bad(SB),NOSPLIT,$0-0\n"+instruction+"\nRET\n") + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate(%q) unexpectedly succeeded", instruction) + } + } +} + +func TestTranslateARMFallbackI64Return(t *testing.T) { + file, err := Parse(ArchARM, ` +TEXT helper(SB),NOSPLIT,$0-0 + MOVW $1, R0 + MOVW $2, R1 + B done +done: + RET +`) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{ + "helper": {Name: "helper", Ret: I64}, + }, + }); err != nil { + t.Fatal(err) + } +} + +func TestTranslateARMRawTSTFeedsConditionalInstruction(t *testing.T) { + file, err := Parse(ArchARM, ` +TEXT rawtst(SB),NOSPLIT,$0-0 + WORD $0xe1180008 + MOVW.EQ $1, R0 + WORD $0xe31e0003 + MOVW.NE $2, R0 + RET +`) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"rawtst": {Name: "rawtst", Ret: Void}}, + }); err != nil { + t.Fatal(err) + } +} diff --git a/arm_eval.go b/arm_eval.go index e5d6db33..260a7054 100644 --- a/arm_eval.go +++ b/arm_eval.go @@ -218,7 +218,7 @@ func (c *armCtx) evalFPValue32(op Operand) (string, error) { slot, ok := c.fpParams[op.FPOffset] if !ok { for base, candidate := range c.fpParams { - if candidate.Type != I64 || op.FPOffset != base+4 { + if candidate.Type != I64 && candidate.Type != LLVMType("double") || op.FPOffset != base+4 { continue } p := c.fpParamAlloca[base] @@ -226,10 +226,16 @@ func (c *armCtx) evalFPValue32(op Operand) (string, error) { return "", fmt.Errorf("arm: missing FP param alloca for +%d(FP)", base) } full := c.newTmp() + fullValue := "%" + full hi := c.newTmp() word := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i64, ptr %s\n", full, p) - fmt.Fprintf(c.b, " %%%s = lshr i64 %%%s, 32\n", hi, full) + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s\n", full, candidate.Type, p) + if candidate.Type == LLVMType("double") { + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", bits, fullValue) + fullValue = "%" + bits + } + fmt.Fprintf(c.b, " %%%s = lshr i64 %s, 32\n", hi, fullValue) fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", word, hi) return "%" + word, nil } @@ -243,10 +249,10 @@ func (c *armCtx) evalFPValue32(op Operand) (string, error) { t := c.newTmp() fmt.Fprintf(c.b, " %%%s = load %s, ptr %s\n", t, slot.Type, p) arg = "%" + t - } else if slot.Field >= 0 { + } else if fields := frameSlotFields(slot); len(fields) != 0 { aggTy := c.sig.Args[slot.Index] t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = extractvalue %s %s, %d\n", t, aggTy, arg, slot.Field) + fmt.Fprintf(c.b, " %%%s = extractvalue %s %s%s\n", t, aggTy, arg, frameSlotExtractSuffix(slot)) arg = "%" + t } switch slot.Type { @@ -272,16 +278,25 @@ func (c *armCtx) evalFPValue32(op Operand) (string, error) { t := c.newTmp() fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", t, arg) return "%" + t, nil + case LLVMType("double"): + bits := c.newTmp() + word := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", bits, arg) + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", word, bits) + return "%" + word, nil default: return "", fmt.Errorf("arm: unsupported FP slot type %q", slot.Type) } } func (c *armCtx) evalFPAddr32(op Operand) (string, error) { - if slot, ok := c.fpResAllocaOff[op.FPOffset]; ok { - c.markFPResultAddrTaken(op.FPOffset) + ptr, resultOffset, isResult, ok := c.armFramePointer(op.FPOffset, 0) + if ok { + if isResult { + c.markFPResultAddrTaken(resultOffset) + } t := c.newTmp() - fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %s to i32\n", t, slot) + fmt.Fprintf(c.b, " %%%s = ptrtoint ptr %s to i32\n", t, ptr) return "%" + t, nil } if op.FPName == "argframe" { @@ -292,5 +307,97 @@ func (c *armCtx) evalFPAddr32(op Operand) (string, error) { // for using only addressable, modeled slots. return "0", nil } + if strings.EqualFold(op.FPName, "sp") && op.FPOffset == -4 { + // runtime.vdsoCall spells the caller's stack pointer as $sp-4(FP). + // An ordinary LLVM function signature does not expose that caller-owned + // address. Match the explicit argframe context fallback above so corpus + // and object lowering remain possible; executable ABI coverage must not + // treat this placeholder as an addressable modeled frame slot. + return "0", nil + } return "", fmt.Errorf("arm: unsupported FP addr slot: %s", op.String()) } + +func armFrameTypeSize(typ LLVMType) int64 { + switch typ { + case I1, I8: + return 1 + case I16: + return 2 + case I32, Ptr, LLVMType("float"): + return 4 + case I64, LLVMType("double"): + return 8 + default: + // Frame slots are normally scalar leaves. Preserve the established + // conservative aggregate fallback used by the x86 classic-frame model. + return 16 + } +} + +// armFramePointer resolves exact and interior classic-frame offsets to the +// backing alloca. accessBytes == 0 forms an address; positive sizes additionally +// prove that the requested load/store remains inside that modeled slot. +func (c *armCtx) armFramePointer(off, accessBytes int64) (ptr string, base int64, isResult, ok bool) { + type candidate struct { + slot FrameSlot + ptr string + isResult bool + } + candidates := make([]candidate, 0, len(c.sig.Frame.Params)+len(c.fpResults)) + for _, slot := range c.sig.Frame.Params { + if p := c.fpParamAlloca[slot.Offset]; p != "" { + candidates = append(candidates, candidate{slot: slot, ptr: p}) + } + } + for _, slot := range c.fpResults { + if p := c.fpResAllocaIdx[slot.Index]; p != "" { + candidates = append(candidates, candidate{slot: slot, ptr: p, isResult: true}) + } + } + // Prefer an exact slot when one starts at the same offset as the end of an + // earlier slot. + for pass := 0; pass < 2; pass++ { + for _, candidate := range candidates { + size := armFrameTypeSize(candidate.slot.Type) + exact := off == candidate.slot.Offset + inside := off >= candidate.slot.Offset && off < candidate.slot.Offset+size + if (pass == 0 && !exact) || (pass == 1 && exact) || !inside { + continue + } + if accessBytes > 0 && off+accessBytes > candidate.slot.Offset+size { + continue + } + resolved := candidate.ptr + if delta := off - candidate.slot.Offset; delta != 0 { + t := c.newTmp() + fmt.Fprintf(c.b, " %%%s = getelementptr i8, ptr %s, i32 %d\n", t, resolved, delta) + resolved = "%" + t + } + return resolved, candidate.slot.Offset, candidate.isResult, true + } + } + return "", 0, false, false +} + +func (c *armCtx) loadARMFrameBits(off int64, bits int) (string, error) { + ptr, _, _, ok := c.armFramePointer(off, int64(bits/8)) + if !ok { + return "", fmt.Errorf("arm: unsupported %d-bit FP frame load at +%d(FP)", bits, off) + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i%d, ptr %s\n", value, bits, ptr) + return "%" + value, nil +} + +func (c *armCtx) storeARMFrameBits(off int64, bits int, value string) error { + ptr, resultOffset, isResult, ok := c.armFramePointer(off, int64(bits/8)) + if !ok { + return fmt.Errorf("arm: unsupported %d-bit FP frame store at +%d(FP)", bits, off) + } + fmt.Fprintf(c.b, " store i%d %s, ptr %s\n", bits, value, ptr) + if isResult { + c.markFPResultWritten(resultOffset) + } + return nil +} diff --git a/arm_fp.go b/arm_fp.go index 441bfb2e..e8aeede0 100644 --- a/arm_fp.go +++ b/arm_fp.go @@ -25,7 +25,7 @@ func (c *armCtx) markFPResultAddrTaken(off int64) { func (c *armCtx) storeFPResult32(off int64, v32 string) error { for _, meta := range c.fpResults { - if meta.Type != I64 || (off != meta.Offset && off != meta.Offset+4) { + if meta.Type != I64 && meta.Type != LLVMType("double") || (off != meta.Offset && off != meta.Offset+4) { continue } slot := c.fpResAllocaIdx[meta.Index] @@ -33,22 +33,34 @@ func (c *armCtx) storeFPResult32(off int64, v32 string) error { return fmt.Errorf("arm: missing FP result alloca for index %d", meta.Index) } old := c.newTmp() + oldBits := "%" + old word := c.newTmp() cleared := c.newTmp() - fmt.Fprintf(c.b, " %%%s = load i64, ptr %s\n", old, slot) + fmt.Fprintf(c.b, " %%%s = load %s, ptr %s\n", old, meta.Type, slot) + if meta.Type == LLVMType("double") { + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", bits, oldBits) + oldBits = "%" + bits + } fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", word, v32) inserted := "%" + word if off == meta.Offset { - fmt.Fprintf(c.b, " %%%s = and i64 %%%s, -4294967296\n", cleared, old) + fmt.Fprintf(c.b, " %%%s = and i64 %s, -4294967296\n", cleared, oldBits) } else { - fmt.Fprintf(c.b, " %%%s = and i64 %%%s, 4294967295\n", cleared, old) + fmt.Fprintf(c.b, " %%%s = and i64 %s, 4294967295\n", cleared, oldBits) shifted := c.newTmp() fmt.Fprintf(c.b, " %%%s = shl i64 %%%s, 32\n", shifted, word) inserted = "%" + shifted } merged := c.newTmp() fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %s\n", merged, cleared, inserted) - fmt.Fprintf(c.b, " store i64 %%%s, ptr %s\n", merged, slot) + stored := "%" + merged + if meta.Type == LLVMType("double") { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to double\n", value, stored) + stored = "%" + value + } + fmt.Fprintf(c.b, " store %s %s, ptr %s\n", meta.Type, stored, slot) c.fpResWritten[meta.Index] = true return nil } diff --git a/arm_lower_arith.go b/arm_lower_arith.go index b2f88431..534dfa48 100644 --- a/arm_lower_arith.go +++ b/arm_lower_arith.go @@ -2,6 +2,7 @@ package plan9asm import ( "fmt" + "math/bits" "strings" ) @@ -11,30 +12,310 @@ func (c *armCtx) lowerArith(op, cond string, setFlags bool, ins Instr) (ok bool, return true, false, c.lowerARMALU(op, cond, setFlags, ins) case "MVN": return true, false, c.lowerARMMVN(cond, setFlags, ins) - case "ADC", "SBC": + case "ADC", "SBC", "RSC": return true, false, c.lowerARMADCSBC(op, cond, setFlags, ins) case "MUL", "MULU": return true, false, c.lowerARMMUL(cond, ins) case "MULLU": return true, false, c.lowerARMMULLU(cond, ins) + case "MULL", "MMUL", "MMULA", "MMULS", "MULABB", "MULAWB", "MULBB", "MULS", "MULWB", "MULWT": + return true, false, c.lowerARMSignedMultiply(op, cond, setFlags, ins) case "MULA": return true, false, c.lowerARMMULA(cond, ins) case "MULAL", "MULALU": return true, false, c.lowerARMMULAL(cond, ins) case "MULAWT": - return true, false, c.lowerARMMULAWT(cond, ins) - case "DIVUHW": - return true, false, c.lowerARMDIVUHW(cond, ins) + return true, false, c.lowerARMSignedMultiply(op, cond, setFlags, ins) + case "DIV", "DIVU", "MOD", "MODU", "DIVHW", "DIVUHW": + return true, false, c.lowerARMDivMod(op, cond, setFlags, ins) case "CLZ": return true, false, c.lowerARMCLZ(cond, ins) + case "REV", "REV16", "REVSH", "RBIT": + return true, false, c.lowerARMReverseBits(op, cond, ins) + case "BFC", "BFI", "BFX", "BFXU": + return true, false, c.lowerARMBitfield(op, cond, ins) + case "XTAB", "XTABU", "XTAH", "XTAHU": + return true, false, c.lowerARMExtendAdd(op, cond, ins) + case "SWPW", "SWPBU": + return true, false, c.lowerARMAtomicSwap(op, cond, ins) + case "UADD8", "USUB8": + return true, false, c.lowerARMUnsignedParallelByteAddSub(op, cond, setFlags, ins) + case "SLL", "SRL", "SRA": + return true, false, c.lowerARMShift(op, cond, setFlags, ins) case "MRC": return true, false, c.lowerARMMRC(ins) + case "MCR": + return true, false, c.lowerARMMCR(ins) case "CMP", "CMN", "TST", "TEQ": return true, false, c.lowerARMCompare(op, ins) } return false, false, nil } +func (c *armCtx) lowerARMDivMod(op, cond string, setFlags bool, ins Instr) error { + if err := armRequireConditionOnlySuffix(ins); err != nil { + return err + } + if setFlags { + return fmt.Errorf("arm %s does not accept the .S suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return fmt.Errorf("arm %s expects divisor, dst or divisor, numerator, dst: %q", op, ins.Raw) + } + for _, operand := range ins.Args { + if operand.Kind != OpReg || !isARMGeneralReg(operand.Reg) { + return fmt.Errorf("arm %s accepts only general registers: %q", op, ins.Raw) + } + } + + divisor, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return err + } + numeratorOperand := ins.Args[len(ins.Args)-2] + destination := ins.Args[len(ins.Args)-1].Reg + numerator, err := c.loadReg(numeratorOperand.Reg) + if err != nil { + return err + } + + zero := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 0\n", zero, divisor) + safeDivisor := divisor + overflow := "false" + if op == "DIV" || op == "MOD" || op == "DIVHW" { + isMin := c.newTmp() + isMinusOne := c.newTmp() + overflowTmp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, -2147483648\n", isMin, numerator) + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, -1\n", isMinusOne, divisor) + fmt.Fprintf(c.b, " %%%s = and i1 %%%s, %%%s\n", overflowTmp, isMin, isMinusOne) + overflow = "%" + overflowTmp + invalid := c.newTmp() + fmt.Fprintf(c.b, " %%%s = or i1 %%%s, %s\n", invalid, zero, overflow) + safe := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 1, i32 %s\n", safe, invalid, divisor) + safeDivisor = "%" + safe + } else { + safe := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 1, i32 %s\n", safe, zero, divisor) + safeDivisor = "%" + safe + } + + calculated := c.newTmp() + switch op { + case "DIV", "DIVHW": + fmt.Fprintf(c.b, " %%%s = sdiv i32 %s, %s\n", calculated, numerator, safeDivisor) + case "DIVU", "DIVUHW": + fmt.Fprintf(c.b, " %%%s = udiv i32 %s, %s\n", calculated, numerator, safeDivisor) + case "MOD": + fmt.Fprintf(c.b, " %%%s = srem i32 %s, %s\n", calculated, numerator, safeDivisor) + case "MODU": + fmt.Fprintf(c.b, " %%%s = urem i32 %s, %s\n", calculated, numerator, safeDivisor) + } + result := "%" + calculated + if op == "DIV" || op == "DIVHW" { + wrapped := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i32 -2147483648, i32 %s\n", wrapped, overflow, result) + result = "%" + wrapped + } else if op == "MOD" { + wrapped := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i32 0, i32 %s\n", wrapped, overflow, result) + result = "%" + wrapped + } + zeroResult := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 0, i32 %s\n", zeroResult, zero, result) + return c.selectRegWrite(destination, cond, "%"+zeroResult) +} + +func armRotatedImmediateEncodable(value uint32) bool { + for i := 0; i < 16; i++ { + if value&^uint32(0xff) == 0 { + return true + } + value = bits.RotateLeft32(value, 2) + } + return false +} + +func (c *armCtx) lowerARMShift(op, cond string, setFlags bool, ins Instr) error { + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return fmt.Errorf("arm %s expects shift, dstReg or shift, srcReg, dstReg: %q", op, ins.Raw) + } + shift := ins.Args[0] + var src, dst Operand + if len(ins.Args) == 2 { + src, dst = ins.Args[1], ins.Args[1] + } else { + src, dst = ins.Args[1], ins.Args[2] + } + if src.Kind != OpReg || dst.Kind != OpReg { + return fmt.Errorf("arm %s source and destination must be registers: %q", op, ins.Raw) + } + srcValue, err := c.loadReg(src.Reg) + if err != nil { + return err + } + if _, err := c.loadReg(dst.Reg); err != nil { + return err + } + + execute := "true" + if cond != "" && !strings.EqualFold(cond, "AL") { + execute, err = c.condValue(cond) + if err != nil { + return err + } + } + + var result, carry string + switch shift.Kind { + case OpImm: + if shift.Imm < 0 || uint64(shift.Imm) > uint64(^uint32(0)) || !armRotatedImmediateEncodable(uint32(shift.Imm)) { + return fmt.Errorf("arm %s immediate is not a Go ARM rotated immediate: %q", op, ins.Raw) + } + result, carry = c.emitARMImmediateShift(op, srcValue, uint32(shift.Imm)&31) + case OpReg: + shiftValue, loadErr := c.loadReg(shift.Reg) + if loadErr != nil { + return loadErr + } + result, carry = c.emitARMRegisterShift(op, srcValue, shiftValue) + default: + return fmt.Errorf("arm %s shift must be an immediate or register: %q", op, ins.Raw) + } + if err := c.selectRegWrite(dst.Reg, cond, result); err != nil { + return err + } + if setFlags { + return c.setARMShiftFlags(execute, result, carry) + } + return nil +} + +func (c *armCtx) emitARMImmediateShift(op, value string, encodedAmount uint32) (result, carry string) { + amount := encodedAmount + if (op == "SRL" || op == "SRA") && amount == 0 { + amount = 32 + } + switch op { + case "SLL": + if amount == 0 { + result = value + carry = c.loadFlagValue(c.flagsCSlot) + return result, carry + } + result = c.emitARMConstantShift("shl", value, amount) + carry = c.emitARMShiftBit(value, 32-amount) + case "SRL": + if amount == 32 { + result = "0" + } else { + result = c.emitARMConstantShift("lshr", value, amount) + } + carry = c.emitARMShiftBit(value, amount-1) + case "SRA": + if amount == 32 { + result = c.emitARMConstantShift("ashr", value, 31) + } else { + result = c.emitARMConstantShift("ashr", value, amount) + } + carry = c.emitARMShiftBit(value, amount-1) + } + return result, carry +} + +func (c *armCtx) emitARMRegisterShift(op, value, rawAmount string) (result, carry string) { + amount := c.newTmp() + safeAmount := c.newTmp() + isZero := c.newTmp() + isAbove32 := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i32 %s, 255\n", amount, rawAmount) + fmt.Fprintf(c.b, " %%%s = and i32 %%%s, 31\n", safeAmount, amount) + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %%%s, 0\n", isZero, amount) + fmt.Fprintf(c.b, " %%%s = icmp ugt i32 %%%s, 32\n", isAbove32, amount) + + shifted := c.newTmp() + llvmOp := map[string]string{"SLL": "shl", "SRL": "lshr", "SRA": "ashr"}[op] + fmt.Fprintf(c.b, " %%%s = %s i32 %s, %%%s\n", shifted, llvmOp, value, safeAmount) + overflowResult := "0" + if op == "SRA" { + overflowResult = c.emitARMConstantShift("ashr", value, 31) + } + overflowSelected := c.newTmp() + zeroSelected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %s, i32 %%%s\n", overflowSelected, isAbove32, overflowResult, shifted) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 %s, i32 %%%s\n", zeroSelected, isZero, value, overflowSelected) + result = "%" + zeroSelected + + position := c.newTmp() + if op == "SLL" { + fmt.Fprintf(c.b, " %%%s = sub i32 32, %%%s\n", position, amount) + } else { + fmt.Fprintf(c.b, " %%%s = sub i32 %%%s, 1\n", position, amount) + } + safePosition := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i32 %%%s, 31\n", safePosition, position) + candidateCarry := c.emitARMVariableShiftBit(value, "%"+safePosition) + overflowCarry := "false" + if op == "SRA" { + overflowCarry = c.emitARMShiftBit(value, 31) + } + overflowCarrySelected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i1 %s, i1 %s\n", overflowCarrySelected, isAbove32, overflowCarry, candidateCarry) + oldCarry := c.loadFlagValue(c.flagsCSlot) + zeroCarrySelected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i1 %s, i1 %%%s\n", zeroCarrySelected, isZero, oldCarry, overflowCarrySelected) + return result, "%" + zeroCarrySelected +} + +func (c *armCtx) emitARMConstantShift(op, value string, amount uint32) string { + tmp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s i32 %s, %d\n", tmp, op, value, amount) + return "%" + tmp +} + +func (c *armCtx) emitARMShiftBit(value string, position uint32) string { + return c.emitARMVariableShiftBit(value, fmt.Sprintf("%d", position)) +} + +func (c *armCtx) emitARMVariableShiftBit(value, position string) string { + shifted := c.newTmp() + bit := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i32 %s, %s\n", shifted, value, position) + fmt.Fprintf(c.b, " %%%s = trunc i32 %%%s to i1\n", bit, shifted) + return "%" + bit +} + +func (c *armCtx) loadFlagValue(slot string) string { + tmp := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i1, ptr %s\n", tmp, slot) + return "%" + tmp +} + +func (c *armCtx) setARMShiftFlags(execute, result, carry string) error { + c.flagsWritten = true + zero := c.newTmp() + negative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 0\n", zero, result) + fmt.Fprintf(c.b, " %%%s = icmp slt i32 %s, 0\n", negative, result) + c.storeFlagPredicate(c.flagsZSlot, "%"+zero, execute) + c.storeFlagPredicate(c.flagsNSlot, "%"+negative, execute) + c.storeFlagPredicate(c.flagsCSlot, carry, execute) + return nil +} + +func (c *armCtx) storeFlagPredicate(slot, value, execute string) { + if execute == "true" { + c.storeFlag(slot, value) + return + } + old := c.loadFlagValue(slot) + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i1 %s, i1 %s\n", selected, execute, value, old) + c.storeFlag(slot, "%"+selected) +} + func (c *armCtx) lowerARMALU(op, cond string, setFlags bool, ins Instr) error { if len(ins.Args) != 2 && len(ins.Args) != 3 { return fmt.Errorf("arm %s expects 2 or 3 operands: %q", op, ins.Raw) @@ -184,6 +465,20 @@ func (c *armCtx) lowerARMADCSBC(op, cond string, setFlags bool, ins Instr) error if len(ins.Args) != 2 && len(ins.Args) != 3 { return fmt.Errorf("arm %s expects 2 or 3 operands: %q", op, ins.Raw) } + if op == "RSC" { + source := ins.Args[0] + sourceOK := source.Kind == OpImm || + source.Kind == OpReg && isARMGeneralReg(source.Reg) || + source.Kind == OpRegShift && isARMGeneralReg(source.Reg) + if !sourceOK { + return fmt.Errorf("arm RSC source must be an immediate, general register, or shifted general register: %q", ins.Raw) + } + for _, operand := range ins.Args[1:] { + if operand.Kind != OpReg || !isARMGeneralReg(operand.Reg) { + return fmt.Errorf("arm RSC input and destination must be general registers: %q", ins.Raw) + } + } + } var src, lhs string dst := Operand{} var err error @@ -217,7 +512,7 @@ func (c *armCtx) lowerARMADCSBC(op, cond string, setFlags bool, ins Instr) error cf := c.newTmp() fmt.Fprintf(c.b, " %%%s = load i1, ptr %s\n", cf, c.flagsCSlot) cin := c.newTmp() - if op == "SBC" { + if op == "SBC" || op == "RSC" { ncf := c.newTmp() fmt.Fprintf(c.b, " %%%s = xor i1 %%%s, true\n", ncf, cf) fmt.Fprintf(c.b, " %%%s = zext i1 %%%s to i32\n", cin, ncf) @@ -227,11 +522,13 @@ func (c *armCtx) lowerARMADCSBC(op, cond string, setFlags bool, ins Instr) error t0 := c.newTmp() if op == "SBC" { fmt.Fprintf(c.b, " %%%s = sub i32 %s, %s\n", t0, lhs, src) + } else if op == "RSC" { + fmt.Fprintf(c.b, " %%%s = sub i32 %s, %s\n", t0, src, lhs) } else { fmt.Fprintf(c.b, " %%%s = add i32 %s, %s\n", t0, lhs, src) } res := c.newTmp() - if op == "SBC" { + if op == "SBC" || op == "RSC" { fmt.Fprintf(c.b, " %%%s = sub i32 %%%s, %%%s\n", res, t0, cin) } else { fmt.Fprintf(c.b, " %%%s = add i32 %%%s, %%%s\n", res, t0, cin) @@ -260,17 +557,21 @@ func (c *armCtx) lowerARMADCSBC(op, cond string, setFlags bool, ins Instr) error return err } } else { + minuend, subtrahend := lhs, src + if op == "RSC" { + minuend, subtrahend = src, lhs + } l64 := c.newTmp() s64 := c.newTmp() b64 := c.newTmp() subtr := c.newTmp() borrow := c.newTmp() - fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", l64, lhs) - fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", s64, src) + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", l64, minuend) + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", s64, subtrahend) fmt.Fprintf(c.b, " %%%s = zext i32 %%%s to i64\n", b64, cin) fmt.Fprintf(c.b, " %%%s = add i64 %%%s, %%%s\n", subtr, s64, b64) fmt.Fprintf(c.b, " %%%s = icmp ult i64 %%%s, %%%s\n", borrow, l64, subtr) - if err := c.setFlagsSub(cond, lhs, src, "%"+res); err != nil { + if err := c.setFlagsSub(cond, minuend, subtrahend, "%"+res); err != nil { return err } nb := c.newTmp() @@ -441,55 +742,11 @@ func (c *armCtx) lowerARMMULAL(cond string, ins Instr) error { } func (c *armCtx) lowerARMMULAWT(cond string, ins Instr) error { - if len(ins.Args) != 4 || ins.Args[3].Kind != OpReg { - return fmt.Errorf("arm MULAWT expects a, b, acc, dst: %q", ins.Raw) - } - a, err := c.eval32(ins.Args[0], false) - if err != nil { - return err - } - b, err := c.eval32(ins.Args[1], false) - if err != nil { - return err - } - acc, err := c.eval32(ins.Args[2], false) - if err != nil { - return err - } - a64 := c.newTmp() - b64 := c.newTmp() - prod := c.newTmp() - hiShift := c.newTmp() - hi := c.newTmp() - res := c.newTmp() - fmt.Fprintf(c.b, " %%%s = sext i32 %s to i64\n", a64, a) - fmt.Fprintf(c.b, " %%%s = sext i32 %s to i64\n", b64, b) - fmt.Fprintf(c.b, " %%%s = mul i64 %%%s, %%%s\n", prod, a64, b64) - fmt.Fprintf(c.b, " %%%s = ashr i64 %%%s, 32\n", hiShift, prod) - fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", hi, hiShift) - fmt.Fprintf(c.b, " %%%s = add i32 %%%s, %s\n", res, hi, acc) - return c.selectRegWrite(ins.Args[3].Reg, cond, "%"+res) + return c.lowerARMSignedMultiply("MULAWT", cond, false, ins) } func (c *armCtx) lowerARMDIVUHW(cond string, ins Instr) error { - if len(ins.Args) != 3 || ins.Args[2].Kind != OpReg { - return fmt.Errorf("arm DIVUHW expects divisor, numerator, dst: %q", ins.Raw) - } - divisor, err := c.eval32(ins.Args[0], false) - if err != nil { - return err - } - numer, err := c.eval32(ins.Args[1], false) - if err != nil { - return err - } - zero := c.newTmp() - fmt.Fprintf(c.b, " %%%s = icmp eq i32 %s, 0\n", zero, divisor) - div := c.newTmp() - fmt.Fprintf(c.b, " %%%s = udiv i32 %s, %s\n", div, numer, divisor) - sel := c.newTmp() - fmt.Fprintf(c.b, " %%%s = select i1 %%%s, i32 0, i32 %%%s\n", sel, zero, div) - return c.selectRegWrite(ins.Args[2].Reg, cond, "%"+sel) + return c.lowerARMDivMod("DIVUHW", cond, false, ins) } func (c *armCtx) lowerARMCLZ(cond string, ins Instr) error { @@ -519,3 +776,26 @@ func (c *armCtx) lowerARMMRC(ins Instr) error { fmt.Fprintf(c.b, " %%%s = call i32 asm sideeffect %q, %q()\n", t, asm, "=r,~{memory}") return c.storeReg(ins.Args[2].Reg, "%"+t) } + +func (c *armCtx) lowerARMMCR(ins Instr) error { + if len(ins.Args) != 6 || ins.Args[2].Kind != OpReg || !isARMGeneralReg(ins.Args[2].Reg) { + return fmt.Errorf("arm MCR expects coprocessor, operation, source register, CRn, CRm, information: %q", ins.Raw) + } + for _, suffix := range armInstructionSuffixes(ins) { + if suffix != "" && suffix != "S" && !armCondCodes[suffix] { + return fmt.Errorf("arm MCR suffix %q is absent from the Go 1.27 optab: %q", suffix, ins.Raw) + } + } + part := func(op Operand) string { + s := strings.ToLower(strings.TrimSpace(op.String())) + s = strings.TrimPrefix(s, "$") + return strings.TrimPrefix(s, "c") + } + value, err := c.loadReg(ins.Args[2].Reg) + if err != nil { + return err + } + asm := fmt.Sprintf("mcr p%s, #%s, $0, c%s, c%s, #%s", part(ins.Args[0]), part(ins.Args[1]), part(ins.Args[3]), part(ins.Args[4]), part(ins.Args[5])) + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(i32 %s)\n", asm, "r,~{memory}", value) + return nil +} diff --git a/arm_lower_atomic.go b/arm_lower_atomic.go index 245a3eb6..69697a82 100644 --- a/arm_lower_atomic.go +++ b/arm_lower_atomic.go @@ -97,14 +97,34 @@ func (c *armCtx) lowerAtomic(op string, ins Instr) (ok bool, terminated bool, er return true, false, c.storeReg(ins.Args[1].Reg, v) case "LDREXD": - if len(ins.Args) != 2 || ins.Args[0].Kind != OpMem || ins.Args[1].Kind != OpReg { - return true, false, fmt.Errorf("arm LDREXD expects mem, regLo: %q", ins.Raw) + var mem Operand + var loReg, hiReg Reg + switch { + case len(ins.Args) == 2 && ins.Args[0].Kind == OpMem && ins.Args[1].Kind == OpReg: + mem, loReg = ins.Args[0], ins.Args[1].Reg + case len(ins.Args) == 3 && ins.Args[0].Kind == OpMem && ins.Args[1].Kind == OpReg && ins.Args[2].Kind == OpReg: + // x/arch's raw ARM syntax prints the implicit pair explicitly as + // mem, regHi, regLo; Go source syntax prints mem, regLo. + mem, hiReg, loReg = ins.Args[0], ins.Args[1].Reg, ins.Args[2].Reg + default: + return true, false, fmt.Errorf("arm LDREXD expects mem, regLo (or decoded mem, regHi, regLo): %q", ins.Raw) } - hiReg, err := armNextReg(ins.Args[1].Reg) - if err != nil { - return true, false, err + if hiReg == "" { + var err error + hiReg, err = armNextReg(loReg) + if err != nil { + return true, false, err + } + } else { + wantHi, err := armNextReg(loReg) + if err != nil || hiReg != wantHi { + return true, false, fmt.Errorf("arm LDREXD register pair must be consecutive: %q", ins.Raw) + } } - ptr, err := c.atomicMemPtr(ins.Args[0].Mem) + if loReg == "" { + return true, false, fmt.Errorf("arm LDREXD missing low register: %q", ins.Raw) + } + ptr, err := c.atomicMemPtr(mem.Mem) if err != nil { return true, false, err } @@ -120,7 +140,7 @@ func (c *armCtx) lowerAtomic(op string, ins Instr) (ok bool, terminated bool, er fmt.Fprintf(c.b, " store ptr %s, ptr %s\n", ptr, c.exclusivePtrSlot) fmt.Fprintf(c.b, " store i8 8, ptr %s\n", c.exclusiveSizeSlot) fmt.Fprintf(c.b, " store i64 %%%s, ptr %s\n", ld, c.exclusiveValueSlot) - if err := c.storeReg(ins.Args[1].Reg, "%"+lo); err != nil { + if err := c.storeReg(loReg, "%"+lo); err != nil { return true, false, err } return true, false, c.storeReg(hiReg, "%"+hi) @@ -152,14 +172,30 @@ func (c *armCtx) lowerAtomic(op string, ins Instr) (ok bool, terminated bool, er return true, false, c.storeReg(ins.Args[2].Reg, status) case "STREXD": - if len(ins.Args) != 3 || ins.Args[0].Kind != OpReg || ins.Args[1].Kind != OpMem || ins.Args[2].Kind != OpReg { - return true, false, fmt.Errorf("arm STREXD expects srcLoReg, mem, statusReg: %q", ins.Raw) + var loReg, hiReg, statusReg Reg + var mem Operand + switch { + case len(ins.Args) == 3 && ins.Args[0].Kind == OpReg && ins.Args[1].Kind == OpMem && ins.Args[2].Kind == OpReg: + loReg, mem, statusReg = ins.Args[0].Reg, ins.Args[1], ins.Args[2].Reg + case len(ins.Args) == 4 && ins.Args[0].Kind == OpMem && ins.Args[1].Kind == OpReg && ins.Args[2].Kind == OpReg && ins.Args[3].Kind == OpReg: + // x/arch's raw ARM syntax prints mem, regHi, regLo, status. + mem, hiReg, loReg, statusReg = ins.Args[0], ins.Args[1].Reg, ins.Args[2].Reg, ins.Args[3].Reg + default: + return true, false, fmt.Errorf("arm STREXD expects srcLoReg, mem, statusReg (or decoded mem, regHi, regLo, statusReg): %q", ins.Raw) + } + var err error + if hiReg == "" { + hiReg, err = armNextReg(loReg) + } else { + wantHi, pairErr := armNextReg(loReg) + if pairErr != nil || hiReg != wantHi { + err = fmt.Errorf("arm STREXD register pair must be consecutive: %q", ins.Raw) + } } - hiReg, err := armNextReg(ins.Args[0].Reg) if err != nil { return true, false, err } - lo, err := c.loadReg(ins.Args[0].Reg) + lo, err := c.loadReg(loReg) if err != nil { return true, false, err } @@ -173,7 +209,7 @@ func (c *armCtx) lowerAtomic(op string, ins Instr) (ok bool, terminated bool, er new64 := c.newTmp() fmt.Fprintf(c.b, " %%%s = shl i64 %s, 32\n", hiShift, hi64) fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %s\n", new64, hiShift, lo64) - ptr, err := c.atomicMemPtr(ins.Args[1].Mem) + ptr, err := c.atomicMemPtr(mem.Mem) if err != nil { return true, false, err } @@ -181,7 +217,7 @@ func (c *armCtx) lowerAtomic(op string, ins Instr) (ok bool, terminated bool, er if err != nil { return true, false, err } - return true, false, c.storeReg(ins.Args[2].Reg, status) + return true, false, c.storeReg(statusReg, status) } return false, false, nil } diff --git a/arm_lower_atomic_swap.go b/arm_lower_atomic_swap.go new file mode 100644 index 00000000..a7d6e0d5 --- /dev/null +++ b/arm_lower_atomic_swap.go @@ -0,0 +1,43 @@ +package plan9asm + +import "fmt" + +func (c *armCtx) lowerARMAtomicSwap(op, cond string, ins Instr) error { + if err := armRequireConditionOnlySuffix(ins); err != nil { + return err + } + if len(ins.Args) != 3 || + ins.Args[0].Kind != OpReg || !isARMGeneralReg(ins.Args[0].Reg) || + ins.Args[1].Kind != OpMem || ins.Args[1].Mem.Base == "" || ins.Args[1].Mem.Off != 0 || + ins.Args[1].Mem.OffRaw != "" || ins.Args[1].Mem.Index != "" || ins.Args[1].Mem.Sym != "" || + ins.Args[2].Kind != OpReg || !isARMGeneralReg(ins.Args[2].Reg) { + return fmt.Errorf("arm %s expects source register, (base register), destination register: %q", op, ins.Raw) + } + if cond != "" { + return c.emitConditionalEffect(cond, func() error { + return c.lowerARMAtomicSwap(op, "", ins) + }) + } + source, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return err + } + address, _, _, err := c.addrI32(ins.Args[1].Mem, false) + if err != nil { + return err + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i32 %s to ptr\n", pointer, address) + if op == "SWPW" { + old := c.newTmp() + fmt.Fprintf(c.b, " %%%s = atomicrmw xchg ptr %%%s, i32 %s seq_cst\n", old, pointer, source) + return c.storeReg(ins.Args[2].Reg, "%"+old) + } + narrowed := c.newTmp() + old := c.newTmp() + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i32 %s to i8\n", narrowed, source) + fmt.Fprintf(c.b, " %%%s = atomicrmw xchg ptr %%%s, i8 %%%s seq_cst\n", old, pointer, narrowed) + fmt.Fprintf(c.b, " %%%s = zext i8 %%%s to i32\n", extended, old) + return c.storeReg(ins.Args[2].Reg, "%"+extended) +} diff --git a/arm_lower_atomic_swap_test.go b/arm_lower_atomic_swap_test.go new file mode 100644 index 00000000..ef90a266 --- /dev/null +++ b/arm_lower_atomic_swap_test.go @@ -0,0 +1,49 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +const armAtomicSwapForms = `TEXT atomicSwapForms(SB),$0-0 + SWPW R3, (R7), R9 + SWPBU R4, (R2), R8 + RET +` + +func TestTranslateARMAtomicSwapCompleteFormats(t *testing.T) { + requireARMGoAssemblerResult(t, armAtomicSwapForms, true) + ll := translateARMForTest(t, armAtomicSwapForms, map[string]FuncSig{ + "example.atomicSwapForms": {Name: "example.atomicSwapForms", Ret: Void}, + }) + for _, want := range []string{"atomicrmw xchg ptr", "i32", "i8", "zext i8"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM atomic swap lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-atomic-swap.ll", "arm-atomic-swap.o", ll) +} + +func TestTranslateARMAtomicSwapRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"SWPW R0, 4(R1), R2", "SWPBU R0, (R1)"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARMGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM atomic-swap optab", instruction) + } + } +} diff --git a/arm_lower_bitfield.go b/arm_lower_bitfield.go new file mode 100644 index 00000000..d8dc8dcd --- /dev/null +++ b/arm_lower_bitfield.go @@ -0,0 +1,79 @@ +package plan9asm + +import "fmt" + +func (c *armCtx) lowerARMBitfield(op, cond string, ins Instr) error { + if err := armRequireConditionOnlySuffix(ins); err != nil { + return err + } + if len(ins.Args) != 3 && len(ins.Args) != 4 { + return fmt.Errorf("arm %s expects width, lsb, dst or width, lsb, src, dst: %q", op, ins.Raw) + } + if op == "BFC" && len(ins.Args) != 3 { + return fmt.Errorf("arm BFC expects width, lsb, dst: %q", ins.Raw) + } + if ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" || + ins.Args[1].Kind != OpImm || ins.Args[1].ImmRaw != "" { + return fmt.Errorf("arm %s width and lsb must be resolved integer constants: %q", op, ins.Raw) + } + width, lsb := ins.Args[0].Imm, ins.Args[1].Imm + if width <= 0 || width > 32 || lsb < 0 || lsb >= 32 || width+lsb > 32 { + return fmt.Errorf("arm %s requires 1 <= width <= 32 and 0 <= lsb with width+lsb <= 32: %q", op, ins.Raw) + } + sourceOperand := ins.Args[len(ins.Args)-1] + if len(ins.Args) == 4 { + sourceOperand = ins.Args[2] + } + destination := ins.Args[len(ins.Args)-1] + if sourceOperand.Kind != OpReg || !isARMGeneralReg(sourceOperand.Reg) || + destination.Kind != OpReg || !isARMGeneralReg(destination.Reg) { + return fmt.Errorf("arm %s source and destination must be general registers: %q", op, ins.Raw) + } + source, err := c.loadReg(sourceOperand.Reg) + if err != nil { + return err + } + fieldMask := ^uint32(0) + if width < 32 { + fieldMask = uint32(1)< callerBits: + fmt.Fprintf(c.b, " %%%s = trunc %s %%%s to %s\n", conv, csig.Ret, t, c.sig.Ret) + case calleeInteger && callerInteger && calleeBits < callerBits: + fmt.Fprintf(c.b, " %%%s = zext %s %%%s to %s\n", conv, csig.Ret, t, c.sig.Ret) case csig.Ret == I32 && (c.sig.Ret == I1 || c.sig.Ret == I8 || c.sig.Ret == I16): fmt.Fprintf(c.b, " %%%s = trunc i32 %%%s to %s\n", conv, t, c.sig.Ret) case (csig.Ret == I1 || csig.Ret == I8 || csig.Ret == I16) && c.sig.Ret == I32: @@ -200,6 +226,23 @@ func (c *armCtx) tailCallAndRet(symOp Operand) error { return nil } +func armIntegerTypeWidth(typ LLVMType) (int, bool) { + switch typ { + case I1: + return 1, true + case I8: + return 8, true + case I16: + return 16, true + case I32: + return 32, true + case I64: + return 64, true + default: + return 0, false + } +} + func (c *armCtx) callSym(symOp Operand) error { if symOp.Kind != OpSym { return fmt.Errorf("arm call expects sym operand, got %s", symOp.String()) diff --git a/arm_lower_branch_exchange_test.go b/arm_lower_branch_exchange_test.go new file mode 100644 index 00000000..abdac97c --- /dev/null +++ b/arm_lower_branch_exchange_test.go @@ -0,0 +1,40 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARMBranchExchangeCompleteFormat(t *testing.T) { + const source = "TEXT branchExchange(SB),$0-0\n\tBX (R0)\n" + requireARMGoAssemblerResult(t, source, true) + ll := translateARMForTest(t, source, map[string]FuncSig{ + "example.branchExchange": {Name: "example.branchExchange", Ret: Void}, + }) + if !strings.Contains(ll, `asm sideeffect "bx $0"`) { + t.Fatalf("ARM BX lowering omitted indirect branch exchange:\n%s", ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-bx.ll", "arm-bx.o", ll) +} + +func TestTranslateARMBranchExchangeRejectsFormsOutsideGoOptab(t *testing.T) { + const source = "TEXT bad(SB),$0-0\n\tBX R0\n" + requireARMGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM, source) + if err != nil { + return + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatal("Translate accepted BX R0 outside Go 1.27's ARM BX optab") + } +} diff --git a/arm_lower_coprocessor_write_test.go b/arm_lower_coprocessor_write_test.go new file mode 100644 index 00000000..734aa30b --- /dev/null +++ b/arm_lower_coprocessor_write_test.go @@ -0,0 +1,42 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARMCoprocessorWriteCompleteFormat(t *testing.T) { + const source = "TEXT coprocessorWrite(SB),$0-0\n\tMCR.S 4, 6, R1, C2, C3, 7\n\tRET\n" + requireARMGoAssemblerResult(t, source, true) + ll := translateARMForTest(t, source, map[string]FuncSig{ + "example.coprocessorWrite": {Name: "example.coprocessorWrite", Ret: Void}, + }) + if !strings.Contains(ll, `asm sideeffect "mcr p4, #6, $0, c2, c3, #7"`) { + t.Fatalf("ARM MCR lowering omitted coprocessor write:\n%s", ll) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-mcr.ll", "arm-mcr.o", ll) +} + +func TestTranslateARMCoprocessorWriteRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"MCR.S 4, 6, R1, C2, C3", "MCR.S 4, 6, (R1), C2, C3, 7"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARMGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM MCR optab", instruction) + } + } +} diff --git a/arm_lower_data.go b/arm_lower_data.go index 7a1c5807..b13a2293 100644 --- a/arm_lower_data.go +++ b/arm_lower_data.go @@ -7,38 +7,46 @@ import ( func (c *armCtx) lowerData(op, cond string, postInc bool, ins Instr) (ok bool, terminated bool, err error) { switch op { - case "MOVD": + case "MOVF", "MOVD": + return c.lowerARMFloatMove(op, cond, ins) + case "MOVW": if len(ins.Args) != 2 { - return true, false, fmt.Errorf("arm MOVD expects 2 operands: %q", ins.Raw) + return true, false, fmt.Errorf("arm MOVW expects 2 operands: %q", ins.Raw) } src, dst := ins.Args[0], ins.Args[1] - switch { - case src.Kind == OpReg && strings.HasPrefix(string(src.Reg), "F") && dst.Kind == OpMem: - v, err := c.loadFReg(src.Reg) - if err != nil { + srcF := src.Kind == OpReg && isARMFReg(src.Reg) + dstF := dst.Kind == OpReg && isARMFReg(dst.Reg) + if srcF || dstF { + if err := armRequireConditionOnlySuffix(ins); err != nil { return true, false, err } - return true, false, c.storeMem(dst.Mem, 64, postInc, v) - case src.Kind == OpMem && dst.Kind == OpReg && strings.HasPrefix(string(dst.Reg), "F"): - v, err := c.loadMem(src.Mem, 64, postInc, false) - if err != nil { - return true, false, err + srcR := src.Kind == OpReg && isARMGeneralReg(src.Reg) && !srcF + dstR := dst.Kind == OpReg && isARMGeneralReg(dst.Reg) && !dstF + if (!srcR || !dstF) && (!srcF || !dstR) { + return true, false, fmt.Errorf("arm MOVW R/F bit transfer expects Rsrc,Fdst or Fsrc,Rdst: %q", ins.Raw) } - return true, false, c.storeFReg(dst.Reg, v) - case src.Kind == OpReg && strings.HasPrefix(string(src.Reg), "F") && dst.Kind == OpReg && strings.HasPrefix(string(dst.Reg), "F"): - v, err := c.loadFReg(src.Reg) - if err != nil { + if cond != "" && !strings.EqualFold(cond, "AL") { + err := c.emitConditionalEffect(cond, func() error { + _, _, innerErr := c.lowerData(op, "", postInc, ins) + return innerErr + }) return true, false, err } - return true, false, c.storeFReg(dst.Reg, v) - default: - return true, false, fmt.Errorf("arm MOVD unsupported operands: %q", ins.Raw) - } - case "MOVW": - if len(ins.Args) != 2 { - return true, false, fmt.Errorf("arm MOVW expects 2 operands: %q", ins.Raw) + if srcR { + value, loadErr := c.loadReg(src.Reg) + if loadErr != nil { + return true, false, loadErr + } + return true, false, c.selectFRegWrite(dst.Reg, "", c.normalizeARMFloatBits(value, 32)) + } + value, loadErr := c.loadFReg(src.Reg) + if loadErr != nil { + return true, false, loadErr + } + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", narrow, value) + return true, false, c.storeReg(dst.Reg, "%"+narrow) } - src, dst := ins.Args[0], ins.Args[1] if cond != "" && (dst.Kind == OpMem || dst.Kind == OpFP || dst.Kind == OpSym || dst.Kind == OpIdent) { err := c.emitConditionalEffect(cond, func() error { _, _, err := c.lowerData(op, "", postInc, ins) @@ -56,7 +64,7 @@ func (c *armCtx) lowerData(op, cond string, postInc bool, ins Instr) (ok bool, t return true, false, err } return true, false, c.storeARMValue(dst, v, 32, cond, postInc, ins.Raw) - case "MOVB", "MOVBU", "MOVH", "MOVHU": + case "MOVB", "MOVBS", "MOVBU", "MOVH", "MOVHS", "MOVHU": if len(ins.Args) != 2 { return true, false, fmt.Errorf("arm %s expects 2 operands: %q", op, ins.Raw) } @@ -70,13 +78,20 @@ func (c *armCtx) lowerData(op, cond string, postInc bool, ins Instr) (ok bool, t } v := "" bits := 8 - if op == "MOVH" || op == "MOVHU" { + if op == "MOVH" || op == "MOVHS" || op == "MOVHU" { bits = 16 } if src.Kind == OpMem { - v, err = c.loadMem(src.Mem, bits, postInc, op == "MOVB" || op == "MOVH") + v, err = c.loadMem(src.Mem, bits, postInc, op == "MOVB" || op == "MOVBS" || op == "MOVH" || op == "MOVHS") } else { v, err = c.eval32(src, false) + if err == nil && (op == "MOVBS" || op == "MOVHS") { + narrow := c.newTmp() + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i32 %s to i%d\n", narrow, v, bits) + fmt.Fprintf(c.b, " %%%s = sext i%d %%%s to i32\n", extended, bits, narrow) + v = "%" + extended + } } if err != nil { return true, false, err diff --git a/arm_lower_extend_add.go b/arm_lower_extend_add.go new file mode 100644 index 00000000..6b5a77aa --- /dev/null +++ b/arm_lower_extend_add.go @@ -0,0 +1,50 @@ +package plan9asm + +import "fmt" + +func (c *armCtx) lowerARMExtendAdd(op, cond string, ins Instr) error { + if err := armRequireConditionOnlySuffix(ins); err != nil { + return err + } + if len(ins.Args) != 2 && len(ins.Args) != 3 { + return fmt.Errorf("arm %s expects rotated source, dst or rotated source, accumulator, dst: %q", op, ins.Raw) + } + sourceOperand := ins.Args[0] + if sourceOperand.Kind != OpRegShift || sourceOperand.ShiftOp != ShiftRotate || sourceOperand.ShiftReg != "" || + !isARMGeneralReg(sourceOperand.Reg) || + (sourceOperand.ShiftAmount != 0 && sourceOperand.ShiftAmount != 8 && sourceOperand.ShiftAmount != 16 && sourceOperand.ShiftAmount != 24) { + return fmt.Errorf("arm %s source must be a general register rotated right by 0, 8, 16, or 24: %q", op, ins.Raw) + } + accumulatorOperand := ins.Args[len(ins.Args)-1] + if len(ins.Args) == 3 { + accumulatorOperand = ins.Args[1] + } + destination := ins.Args[len(ins.Args)-1] + if accumulatorOperand.Kind != OpReg || !isARMGeneralReg(accumulatorOperand.Reg) || + destination.Kind != OpReg || !isARMGeneralReg(destination.Reg) { + return fmt.Errorf("arm %s accumulator and destination must be general registers: %q", op, ins.Raw) + } + rotated, err := c.evalShift(sourceOperand) + if err != nil { + return err + } + bits := 8 + if op == "XTAH" || op == "XTAHU" { + bits = 16 + } + narrowed := c.newTmp() + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i32 %s to i%d\n", narrowed, rotated, bits) + if op == "XTAB" || op == "XTAH" { + fmt.Fprintf(c.b, " %%%s = sext i%d %%%s to i32\n", extended, bits, narrowed) + } else { + fmt.Fprintf(c.b, " %%%s = zext i%d %%%s to i32\n", extended, bits, narrowed) + } + accumulator, err := c.loadReg(accumulatorOperand.Reg) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %%%s\n", result, accumulator, extended) + return c.selectRegWrite(destination.Reg, cond, "%"+result) +} diff --git a/arm_lower_extend_add_test.go b/arm_lower_extend_add_test.go new file mode 100644 index 00000000..fb040f65 --- /dev/null +++ b/arm_lower_extend_add_test.go @@ -0,0 +1,81 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +const armExtendAddForms = `TEXT extendAddForms(SB),$0-0 + XTAB R2@>0, R8 + XTAB R2@>8, R8 + XTAB R2@>16, R8 + XTAB R2@>24, R8 + XTAB R2@>0, R4, R8 + XTAB R2@>8, R4, R8 + XTAB R2@>16, R4, R8 + XTAB R2@>24, R4, R8 + XTAH R3@>0, R9 + XTAH R3@>8, R9 + XTAH R3@>16, R9 + XTAH R3@>24, R9 + XTAH R3@>0, R4, R9 + XTAH R3@>8, R4, R9 + XTAH R3@>16, R4, R9 + XTAH R3@>24, R4, R9 + XTABU R4@>0, R7 + XTABU R4@>8, R7 + XTABU R4@>16, R7 + XTABU R4@>24, R7 + XTABU R4@>0, R0, R7 + XTABU R4@>8, R0, R7 + XTABU R4@>16, R0, R7 + XTABU R4@>24, R0, R7 + XTAHU R5@>0, R1 + XTAHU R5@>8, R1 + XTAHU R5@>16, R1 + XTAHU R5@>24, R1 + XTAHU R5@>0, R9, R1 + XTAHU R5@>8, R9, R1 + XTAHU R5@>16, R9, R1 + XTAHU R5@>24, R9, R1 + RET +` + +func TestTranslateARMExtendAddCompleteFormats(t *testing.T) { + requireARMGoAssemblerResult(t, armExtendAddForms, true) + ll := translateARMForTest(t, armExtendAddForms, map[string]FuncSig{ + "example.extendAddForms": {Name: "example.extendAddForms", Ret: Void}, + }) + for _, want := range []string{ + "call i32 @llvm.fshr.i32", "trunc i32", "sext i8", "sext i16", "zext i8", "zext i16", "add i32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM extend-and-add lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-extend-add.ll", "arm-extend-add.o", ll) +} + +func TestTranslateARMExtendAddRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"XTAB R0<<8, R1", "XTAHU R0@>4, R1", "XTABU R0@>8, (R1)"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARMGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM extend-and-add optab", instruction) + } + } +} diff --git a/arm_lower_float.go b/arm_lower_float.go new file mode 100644 index 00000000..4cdcb696 --- /dev/null +++ b/arm_lower_float.go @@ -0,0 +1,677 @@ +package plan9asm + +import ( + "fmt" + "math" + "strconv" + "strings" +) + +func isARMFReg(r Reg) bool { + s := strings.ToUpper(strings.TrimSpace(string(r))) + if !strings.HasPrefix(s, "F") { + return false + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "F")) + return err == nil && n >= 0 && n <= 15 +} + +func armSingleRegisterNumber(r Reg) (int, bool) { + s := strings.ToUpper(strings.TrimSpace(string(r))) + if !strings.HasPrefix(s, "S") { + return 0, false + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "S")) + return n, err == nil && n >= 0 && n <= 31 +} + +func armSingleOperandNumber(op Operand) (int, bool) { + switch op.Kind { + case OpReg: + return armSingleRegisterNumber(op.Reg) + case OpIdent: + return armSingleRegisterNumber(Reg(op.Ident)) + default: + return 0, false + } +} + +func isARMGeneralReg(r Reg) bool { + s := strings.ToUpper(strings.TrimSpace(string(r))) + if s == "SP" || s == "PC" { + return true + } + if !strings.HasPrefix(s, "R") { + return false + } + n, err := strconv.Atoi(strings.TrimPrefix(s, "R")) + return err == nil && n >= 0 && n <= 15 +} + +func armInstructionSuffixes(ins Instr) []string { + parts := strings.Split(strings.ToUpper(strings.TrimSpace(string(ins.Op))), ".") + if len(parts) < 2 { + return nil + } + return parts[1:] +} + +func armRequireConditionOnlySuffix(ins Instr) error { + for _, suffix := range armInstructionSuffixes(ins) { + if suffix != "" && !armCondCodes[suffix] { + return fmt.Errorf("arm %s suffix %q is absent from the Go 1.27 optab: %q", ins.Op, suffix, ins.Raw) + } + } + return nil +} + +func armFloatMoveModifiers(ins Instr) (postIndex, writeback, up bool, err error) { + for _, suffix := range armInstructionSuffixes(ins) { + switch suffix { + case "", "AL": + case "P": + postIndex = true + case "W": + writeback = true + case "U": + up = true + case "PW", "WP": + postIndex = true + writeback = true + default: + if !armCondCodes[suffix] { + return false, false, false, fmt.Errorf("arm %s suffix %q is absent from the Go 1.27 MOVF/MOVD optab: %q", ins.Op, suffix, ins.Raw) + } + } + } + return postIndex, writeback, up, nil +} + +func armRawOperands(ins Instr) []string { + raw := strings.TrimSpace(ins.Raw) + separator := strings.IndexAny(raw, " \t") + if separator < 0 { + return nil + } + return splitTopLevelCSV(strings.TrimSpace(raw[separator+1:])) +} + +func armFloatImmediateBits(ins Instr, bits int) (string, error) { + operands := armRawOperands(ins) + if len(operands) == 0 { + return "", fmt.Errorf("arm floating move cannot recover its source spelling: %q", ins.Raw) + } + source := strings.TrimSpace(strings.TrimPrefix(strings.TrimSpace(operands[0]), "$")) + // The Go ARM parser classifies integer constants as C_*CON, none of which + // occur in MOVF/MOVD's rows. Require a floating token rather than silently + // accepting forms such as MOVD $1, F0. + if !strings.ContainsAny(source, ".eEpP") { + return "", fmt.Errorf("arm MOVF/MOVD immediate must be a Go floating constant: %q", ins.Raw) + } + if ins.Args[0].ImmRaw != "" { + return "", fmt.Errorf("arm unresolved floating immediate %q", ins.Args[0].ImmRaw) + } + value := math.Float64frombits(uint64(ins.Args[0].Imm)) + if bits == 32 { + return strconv.FormatUint(uint64(math.Float32bits(float32(value))), 10), nil + } + return strconv.FormatUint(math.Float64bits(value), 10), nil +} + +func (c *armCtx) selectFRegWrite(dst Reg, cond, value string) error { + if cond == "" || strings.EqualFold(cond, "AL") { + return c.storeFReg(dst, value) + } + condition, err := c.condValue(cond) + if err != nil { + return err + } + old, err := c.loadFReg(dst) + if err != nil { + return err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i64 %s, i64 %s\n", selected, condition, value, old) + return c.storeFReg(dst, "%"+selected) +} + +func (c *armCtx) normalizeARMFloatBits(value string, bits int) string { + if bits == 64 { + return value + } + wide := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", wide, value) + return "%" + wide +} + +func (c *armCtx) loadARMFloatMemoryBits(op Operand, bits int, postIndex, writeback bool) (string, error) { + switch op.Kind { + case OpFP: + return c.loadARMFrameBits(op.FPOffset, bits) + case OpSym: + ptr, err := c.ptrFromSB(op.Sym) + if err != nil { + return "", err + } + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i%d, ptr %s, align 1\n", value, bits, ptr) + return "%" + value, nil + case OpMem: + value, err := c.loadMem(op.Mem, bits, postIndex, false) + if err != nil { + return "", err + } + if writeback && !postIndex { + if err := c.updatePostInc(op.Mem.Base, op.Mem.Off); err != nil { + return "", err + } + } + return value, nil + default: + return "", fmt.Errorf("arm floating load has unsupported operand %s", op.String()) + } +} + +func (c *armCtx) storeARMFloatMemoryBits(op Operand, bits int, postIndex, writeback bool, value string) error { + switch op.Kind { + case OpFP: + return c.storeARMFrameBits(op.FPOffset, bits, value) + case OpSym: + ptr, err := c.ptrFromSB(op.Sym) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store i%d %s, ptr %s, align 1\n", bits, value, ptr) + return nil + case OpMem: + if err := c.storeMem(op.Mem, bits, postIndex, value); err != nil { + return err + } + if writeback && !postIndex { + return c.updatePostInc(op.Mem.Base, op.Mem.Off) + } + return nil + default: + return fmt.Errorf("arm floating store has unsupported operand %s", op.String()) + } +} + +func isARMFloatMemory(op Operand) bool { + return op.Kind == OpFP || op.Kind == OpMem || (op.Kind == OpSym && !strings.HasPrefix(strings.TrimSpace(op.Sym), "$")) +} + +func (c *armCtx) lowerARMFloatMove(op, cond string, ins Instr) (ok bool, terminated bool, err error) { + bits := 32 + if op == "MOVD" { + bits = 64 + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm %s expects exactly 2 operands: %q", op, ins.Raw) + } + postIndex, writeback, up, err := armFloatMoveModifiers(ins) + if err != nil { + return true, false, err + } + src, dst := ins.Args[0], ins.Args[1] + srcF := src.Kind == OpReg && isARMFReg(src.Reg) + dstF := dst.Kind == OpReg && isARMFReg(dst.Reg) + srcMemory := isARMFloatMemory(src) + dstMemory := isARMFloatMemory(dst) + valid := (srcF && (dstF || dstMemory)) || (srcMemory && dstF) || (src.Kind == OpImm && dstF) + if !valid { + return true, false, fmt.Errorf("arm %s operands are absent from the Go 1.27 optab: %q", op, ins.Raw) + } + if (postIndex || writeback || up) && !srcMemory && !dstMemory { + return true, false, fmt.Errorf("arm %s addressing suffix requires a memory operand: %q", op, ins.Raw) + } + memory := src + if dstMemory { + memory = dst + } + if up && memory.Kind == OpMem && memory.Mem.Off < 0 { + return true, false, fmt.Errorf("arm %s .U cannot be used with a negative offset: %q", op, ins.Raw) + } + if cond != "" && !strings.EqualFold(cond, "AL") { + err := c.emitConditionalEffect(cond, func() error { + _, _, innerErr := c.lowerARMFloatMove(op, "", ins) + return innerErr + }) + return true, false, err + } + + var value string + switch { + case src.Kind == OpImm: + value, err = armFloatImmediateBits(ins, bits) + case srcF: + value, err = c.loadFReg(src.Reg) + if err == nil && bits == 32 { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", narrow, value) + value = "%" + narrow + } + case srcMemory: + value, err = c.loadARMFloatMemoryBits(src, bits, postIndex, writeback) + } + if err != nil { + return true, false, err + } + if dstF { + return true, false, c.selectFRegWrite(dst.Reg, "", c.normalizeARMFloatBits(value, bits)) + } + return true, false, c.storeARMFloatMemoryBits(dst, bits, postIndex, writeback, value) +} + +func (c *armCtx) loadARMFloatRegValue(reg Reg, bits int) (string, error) { + value, err := c.loadFReg(reg) + if err != nil { + return "", err + } + integerType := "i64" + floatType := "double" + if bits == 32 { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", narrow, value) + value = "%" + narrow + integerType = "i32" + floatType = "float" + } + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", converted, integerType, value, floatType) + return "%" + converted, nil +} + +func (c *armCtx) storeARMFloatRegValue(reg Reg, cond string, bits int, value string) error { + floatType := "double" + integerType := "i64" + if bits == 32 { + floatType = "float" + integerType = "i32" + } + encoded := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast %s %s to %s\n", encoded, floatType, value, integerType) + bitsValue := "%" + encoded + if bits == 32 { + bitsValue = c.normalizeARMFloatBits(bitsValue, bits) + } + return c.selectFRegWrite(reg, cond, bitsValue) +} + +func (c *armCtx) setARMFloatCompareFlags(lhs, rhs, floatType, cond string) error { + if cond != "" && !strings.EqualFold(cond, "AL") { + return c.emitConditionalEffect(cond, func() error { + return c.setARMFloatCompareFlags(lhs, rhs, floatType, "") + }) + } + comparisons := []struct { + predicate string + slot string + }{ + {"olt", c.flagsNSlot}, + {"oeq", c.flagsZSlot}, + // ARM VFP compare sets C for greater, equal, and unordered. + {"uge", c.flagsCSlot}, + {"uno", c.flagsVSlot}, + } + for _, comparison := range comparisons { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fcmp %s %s %s, %s\n", value, comparison.predicate, floatType, lhs, rhs) + c.storeFlag(comparison.slot, "%"+value) + } + c.flagsWritten = true + return nil +} + +func (c *armCtx) lowerARMFloatCompare(op, cond string, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "CMPF", "CMPD": + default: + return false, false, nil + } + if err := armRequireConditionOnlySuffix(ins); err != nil { + return true, false, err + } + if len(ins.Args) < 1 || len(ins.Args) > 2 { + return true, false, fmt.Errorf("arm %s expects Fsrc or Fsrc1,Fsrc2: %q", op, ins.Raw) + } + for _, arg := range ins.Args { + if arg.Kind != OpReg || !isARMFReg(arg.Reg) { + return true, false, fmt.Errorf("arm %s accepts only floating registers: %q", op, ins.Raw) + } + } + bits := 32 + floatType := "float" + if op == "CMPD" { + bits = 64 + floatType = "double" + } + // obj/arm encodes p.From as Vm and p.Reg as Vd. With one operand Vd is + // compared against zero; with two, Plan 9 order is Vm,Vd. + rhs := "0.000000e+00" + lhsIndex := 0 + if len(ins.Args) == 2 { + lhsIndex = 1 + var loadErr error + rhs, loadErr = c.loadARMFloatRegValue(ins.Args[0].Reg, bits) + if loadErr != nil { + return true, false, loadErr + } + } + lhs, err := c.loadARMFloatRegValue(ins.Args[lhsIndex].Reg, bits) + if err != nil { + return true, false, err + } + return true, false, c.setARMFloatCompareFlags(lhs, rhs, floatType, cond) +} + +func armWordFloatConversionUnsigned(ins Instr) (bool, error) { + unsigned := false + for _, suffix := range armInstructionSuffixes(ins) { + switch { + case suffix == "", suffix == "AL", armCondCodes[suffix]: + case suffix == "U": + unsigned = true + default: + return false, fmt.Errorf("arm %s suffix %q is absent from the Go 1.27 conversion optab: %q", ins.Op, suffix, ins.Raw) + } + } + return unsigned, nil +} + +func (c *armCtx) lowerARMWordFloatConversion(op, cond string, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "MOVWF", "MOVWD", "MOVFW", "MOVDW": + default: + return false, false, nil + } + unsigned, err := armWordFloatConversionUnsigned(ins) + if err != nil { + return true, false, err + } + if len(ins.Args) != 2 { + return true, false, fmt.Errorf("arm %s expects exactly 2 operands: %q", op, ins.Raw) + } + wordToFloat := strings.HasPrefix(op, "MOVW") + floatBits := 32 + if strings.Contains(op, "D") { + floatBits = 64 + } + src, dst := ins.Args[0], ins.Args[1] + srcF := src.Kind == OpReg && isARMFReg(src.Reg) + dstF := dst.Kind == OpReg && isARMFReg(dst.Reg) + srcSNumber, srcS := armSingleOperandNumber(src) + dstSNumber, dstS := armSingleOperandNumber(dst) + // S-register spellings are produced by the architectural decoder for raw + // VCVT encodings. They are not part of the source-level Go optab, whose + // floating register class is F0..F15. + rawSingleRegisters := strings.Contains(ins.Raw, "decoded from WORD") && floatBits == 32 + if !rawSingleRegisters { + srcS = false + dstS = false + } + srcR := src.Kind == OpReg && isARMGeneralReg(src.Reg) && !isARMFReg(src.Reg) + dstR := dst.Kind == OpReg && isARMGeneralReg(dst.Reg) && !isARMFReg(dst.Reg) + if wordToFloat { + if (!srcF && !srcS && !srcR) || (!dstF && !dstS) { + return true, false, fmt.Errorf("arm %s expects R/F word source and F destination: %q", op, ins.Raw) + } + } else if (!srcF && !srcS) || (!dstF && !dstS && !dstR) { + return true, false, fmt.Errorf("arm %s expects F source and R/F word destination: %q", op, ins.Raw) + } + if cond != "" && !strings.EqualFold(cond, "AL") { + err := c.emitConditionalEffect(cond, func() error { + _, _, innerErr := c.lowerARMWordFloatConversion(op, "", ins) + return innerErr + }) + return true, false, err + } + + floatType := "float" + if floatBits == 64 { + floatType = "double" + } + if wordToFloat { + var integer string + switch { + case srcR: + integer, err = c.loadReg(src.Reg) + case srcS: + integer, err = c.loadARMRawSingleBits(srcSNumber) + default: + var wide string + wide, err = c.loadFReg(src.Reg) + if err == nil { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", narrow, wide) + integer = "%" + narrow + } + } + if err != nil { + return true, false, err + } + converted := c.newTmp() + conversion := "sitofp" + if unsigned { + conversion = "uitofp" + } + fmt.Fprintf(c.b, " %%%s = %s i32 %s to %s\n", converted, conversion, integer, floatType) + if dstS { + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast float %%%s to i32\n", bits, converted) + return true, false, c.storeARMRawSingleBits(dstSNumber, "%"+bits, "") + } + return true, false, c.storeARMFloatRegValue(dst.Reg, "", floatBits, "%"+converted) + } + + var floating string + if srcS { + floating, err = c.loadARMRawVFPRegValue(srcSNumber, 32) + } else { + floating, err = c.loadARMFloatRegValue(src.Reg, floatBits) + } + if err != nil { + return true, false, err + } + converted := c.newTmp() + conversion := "fptosi" + if unsigned { + conversion = "fptoui" + } + fmt.Fprintf(c.b, " %%%s = %s %s %s to i32\n", converted, conversion, floatType, floating) + integer := "%" + converted + if dstR { + return true, false, c.storeReg(dst.Reg, integer) + } + if dstS { + return true, false, c.storeARMRawSingleBits(dstSNumber, integer, "") + } + return true, false, c.selectFRegWrite(dst.Reg, "", c.normalizeARMFloatBits(integer, 32)) +} + +func armScalarFloatArithmeticKind(op string) (kind string, bits int, accumulating bool, ok bool) { + bits = 32 + if strings.HasSuffix(op, "D") { + bits = 64 + } + switch op { + case "ADDF", "ADDD": + return "add", bits, false, true + case "SUBF", "SUBD": + return "sub", bits, false, true + case "MULF", "MULD": + return "mul", bits, false, true + case "NMULF", "NMULD": + return "nmul", bits, false, true + case "DIVF", "DIVD": + return "div", bits, false, true + case "MULAF", "MULAD", "FMULAF", "FMULAD": + return "madd", bits, true, true + case "MULSF", "MULSD", "FMULSF", "FMULSD": + return "msub", bits, true, true + case "NMULAF", "NMULAD", "FNMULAF", "FNMULAD": + return "nmadd", bits, true, true + case "NMULSF", "NMULSD", "FNMULSF", "FNMULSD": + return "nmsub", bits, true, true + default: + return "", 0, false, false + } +} + +func (c *armCtx) lowerARMScalarFloatArithmetic(op, cond string, ins Instr) (ok bool, terminated bool, err error) { + kind, bits, accumulating, handled := armScalarFloatArithmeticKind(op) + if !handled { + return false, false, nil + } + if err := armRequireConditionOnlySuffix(ins); err != nil { + return true, false, err + } + wantMin := 2 + if accumulating { + wantMin = 3 + } + if len(ins.Args) < wantMin || len(ins.Args) > 3 { + if accumulating { + return true, false, fmt.Errorf("arm %s expects Fsrc1, Fsrc2, Faccumulator: %q", op, ins.Raw) + } + return true, false, fmt.Errorf("arm %s expects Fsrc,Fdst or Fsrc1,Fsrc2,Fdst: %q", op, ins.Raw) + } + for _, arg := range ins.Args { + if arg.Kind != OpReg || !isARMFReg(arg.Reg) { + return true, false, fmt.Errorf("arm %s accepts only floating registers: %q", op, ins.Raw) + } + } + if cond != "" && !strings.EqualFold(cond, "AL") { + err := c.emitConditionalEffect(cond, func() error { + _, _, innerErr := c.lowerARMScalarFloatArithmetic(op, "", ins) + return innerErr + }) + return true, false, err + } + + // obj/arm encodes p.From as Vm and p.Reg (or p.To for two-operand + // instructions) as Vn. Plan 9 order is therefore Vm,Vn,Vd and subtraction + // and division must compute Vn op Vm. + rhs, err := c.loadARMFloatRegValue(ins.Args[0].Reg, bits) + if err != nil { + return true, false, err + } + lhsIndex := 1 + dstIndex := len(ins.Args) - 1 + lhs, err := c.loadARMFloatRegValue(ins.Args[lhsIndex].Reg, bits) + if err != nil { + return true, false, err + } + floatType := "float" + if bits == 64 { + floatType = "double" + } + emitBinary := func(operation, left, right string) string { + name := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", name, operation, floatType, left, right) + return "%" + name + } + emitNeg := func(value string) string { + name := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", name, floatType, value) + return "%" + name + } + + var result string + switch kind { + case "add": + result = emitBinary("fadd", lhs, rhs) + case "sub": + result = emitBinary("fsub", lhs, rhs) + case "mul": + result = emitBinary("fmul", lhs, rhs) + case "nmul": + result = emitNeg(emitBinary("fmul", lhs, rhs)) + case "div": + result = emitBinary("fdiv", lhs, rhs) + default: + product := emitBinary("fmul", lhs, rhs) + accumulator, loadErr := c.loadARMFloatRegValue(ins.Args[dstIndex].Reg, bits) + if loadErr != nil { + return true, false, loadErr + } + switch kind { + case "madd": + result = emitBinary("fadd", accumulator, product) + case "msub": + result = emitBinary("fsub", accumulator, product) + case "nmadd": + result = emitNeg(emitBinary("fadd", accumulator, product)) + case "nmsub": + result = emitBinary("fsub", product, accumulator) + } + } + return true, false, c.storeARMFloatRegValue(ins.Args[dstIndex].Reg, "", bits, result) +} + +func (c *armCtx) lowerFloat(op, cond string, ins Instr) (ok bool, terminated bool, err error) { + if ok, terminated, err := c.lowerARMFloatCompare(op, cond, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARMWordFloatConversion(op, cond, ins); ok { + return ok, terminated, err + } + if ok, terminated, err := c.lowerARMScalarFloatArithmetic(op, cond, ins); ok { + return ok, terminated, err + } + switch op { + case "NEGF", "NEGD", "ABSF", "ABSD", "SQRTF", "SQRTD", "MOVFD", "MOVDF": + default: + return false, false, nil + } + if err := armRequireConditionOnlySuffix(ins); err != nil { + return true, false, err + } + if len(ins.Args) != 2 || ins.Args[0].Kind != OpReg || !isARMFReg(ins.Args[0].Reg) || ins.Args[1].Kind != OpReg || !isARMFReg(ins.Args[1].Reg) { + return true, false, fmt.Errorf("arm %s expects Fsrc, Fdst: %q", op, ins.Raw) + } + if cond != "" && !strings.EqualFold(cond, "AL") { + err := c.emitConditionalEffect(cond, func() error { + _, _, innerErr := c.lowerFloat(op, "", ins) + return innerErr + }) + return true, false, err + } + + sourceBits, destinationBits := 32, 32 + if strings.HasSuffix(op, "D") { + sourceBits, destinationBits = 64, 64 + } + if op == "MOVFD" { + sourceBits, destinationBits = 32, 64 + } else if op == "MOVDF" { + sourceBits, destinationBits = 64, 32 + } + source, err := c.loadARMFloatRegValue(ins.Args[0].Reg, sourceBits) + if err != nil { + return true, false, err + } + result := source + resultName := c.newTmp() + floatType := "float" + if sourceBits == 64 { + floatType = "double" + } + switch { + case strings.HasPrefix(op, "NEG"): + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", resultName, floatType, source) + result = "%" + resultName + case strings.HasPrefix(op, "ABS"): + fmt.Fprintf(c.b, " %%%s = call %s @llvm.fabs.f%d(%s %s)\n", resultName, floatType, sourceBits, floatType, source) + result = "%" + resultName + case strings.HasPrefix(op, "SQRT"): + fmt.Fprintf(c.b, " %%%s = call %s @llvm.sqrt.f%d(%s %s)\n", resultName, floatType, sourceBits, floatType, source) + result = "%" + resultName + case op == "MOVFD": + fmt.Fprintf(c.b, " %%%s = fpext float %s to double\n", resultName, source) + result = "%" + resultName + case op == "MOVDF": + fmt.Fprintf(c.b, " %%%s = fptrunc double %s to float\n", resultName, source) + result = "%" + resultName + } + return true, false, c.storeARMFloatRegValue(ins.Args[1].Reg, "", destinationBits, result) +} diff --git a/arm_lower_hardware_divide_test.go b/arm_lower_hardware_divide_test.go new file mode 100644 index 00000000..1cea84ac --- /dev/null +++ b/arm_lower_hardware_divide_test.go @@ -0,0 +1,51 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +const armHardwareDivideForms = `TEXT hardwareDivide(SB),$0-0 + DIVHW R0, R1, R2 + DIVUHW R0, R1, R2 + DIVHW R0, R1 + DIVUHW R0, R1 + RET +` + +func TestTranslateARMHardwareDivideCompleteFormats(t *testing.T) { + requireARMGoAssemblerResult(t, armHardwareDivideForms, true) + ll := translateARMForTest(t, armHardwareDivideForms, map[string]FuncSig{ + "example.hardwareDivide": {Name: "example.hardwareDivide", Ret: Void}, + }) + for _, want := range []string{"sdiv i32", "udiv i32", "icmp eq i32", "select i1"} { + if !strings.Contains(ll, want) { + t.Fatalf("ARM hardware divide lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-hardware-divide.ll", "arm-hardware-divide.o", ll) +} + +func TestTranslateARMHardwareDivideRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"DIVHW R0", "DIVUHW (R0), R1"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARMGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM hardware-divide optab", instruction) + } + } +} diff --git a/arm_lower_parallel_byte.go b/arm_lower_parallel_byte.go new file mode 100644 index 00000000..f05fc7a5 --- /dev/null +++ b/arm_lower_parallel_byte.go @@ -0,0 +1,53 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +// lowerARMUnsignedParallelByteAddSub implements the complete three-register +// UADD8/USUB8 result family decoded by Go's vendored ARM instruction table. +// The four packed byte lanes deliberately wrap independently, matching the +// architectural data result rather than carrying between adjacent lanes. +func (c *armCtx) lowerARMUnsignedParallelByteAddSub(op, cond string, setFlags bool, ins Instr) error { + if err := armRequireConditionOnlySuffix(ins); err != nil { + return err + } + if setFlags { + return fmt.Errorf("arm %s does not accept the .S suffix: %q", op, ins.Raw) + } + if len(ins.Args) != 3 { + return fmt.Errorf("arm %s expects Rm, Rn, Rd: %q", op, ins.Raw) + } + for _, operand := range ins.Args { + if operand.Kind != OpReg || !isARMParallelDataReg(operand.Reg) { + return fmt.Errorf("arm %s accepts only R0-R14 registers: %q", op, ins.Raw) + } + } + rm, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return err + } + rn, err := c.loadReg(ins.Args[1].Reg) + if err != nil { + return err + } + rmBytes := c.newTmp() + rnBytes := c.newTmp() + resultBytes := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i32 %s to <4 x i8>\n", rmBytes, rm) + fmt.Fprintf(c.b, " %%%s = bitcast i32 %s to <4 x i8>\n", rnBytes, rn) + operation := "add" + if op == "USUB8" { + operation = "sub" + } + fmt.Fprintf(c.b, " %%%s = %s <4 x i8> %%%s, %%%s\n", resultBytes, operation, rnBytes, rmBytes) + fmt.Fprintf(c.b, " %%%s = bitcast <4 x i8> %%%s to i32\n", result, resultBytes) + return c.selectRegWrite(ins.Args[2].Reg, cond, "%"+result) +} + +func isARMParallelDataReg(reg Reg) bool { + s := strings.ToUpper(strings.TrimSpace(string(reg))) + return isARMGeneralReg(reg) && s != "PC" && s != "R15" +} diff --git a/arm_lower_parallel_byte_test.go b/arm_lower_parallel_byte_test.go new file mode 100644 index 00000000..2e347b32 --- /dev/null +++ b/arm_lower_parallel_byte_test.go @@ -0,0 +1,94 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestARMUnsignedParallelByteAddSubCompleteDecodedForms(t *testing.T) { + var source strings.Builder + source.WriteString("TEXT parallelBytes(SB), $0-0\n\tCMP R0, R0\n") + for condition := uint32(0); condition <= 14; condition++ { + for _, base := range []uint32{0x06500f90, 0x06500ff0} { + // Rd=R2, Rn=R3, Rm=R4. The decoder table defines one + // three-register form for each of ARM's 15 executable conditions. + word := condition<<28 | base | 3<<16 | 2<<12 | 4 + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + } + source.WriteString("\tRET\n") + file, err := Parse(ArchARM, source.String()) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + ir, err := Translate(file, Options{ + Goarch: "arm", + TargetTriple: "armv7-unknown-linux-gnueabihf", + Sigs: map[string]FuncSig{ + "parallelBytes": {Name: "parallelBytes", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("Translate() error = %v", err) + } + for _, want := range []string{"add <4 x i8>", "sub <4 x i8>"} { + if !strings.Contains(ir, want) { + t.Fatalf("parallel byte semantics omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-parallel-byte.ll", "arm-parallel-byte.o", ir) +} + +func TestARMUnsignedParallelByteAddSubRejectsNonExecutableCondition(t *testing.T) { + for _, word := range []uint32{0xf6500f91, 0xf6500ff1} { + t.Run(fmt.Sprintf("%#08x", word), func(t *testing.T) { + source := fmt.Sprintf("TEXT invalid(SB), $0-0\n\tWORD $%#08x\n\tRET\n", word) + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + if _, err := Translate(file, Options{ + Goarch: "arm", + TargetTriple: "armv7-unknown-linux-gnueabihf", + Sigs: map[string]FuncSig{ + "invalid": {Name: "invalid", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate() accepted reserved encoding %#08x", word) + } + }) + } +} + +func TestARMUnsignedParallelByteAddSubRejectsNamedFormsOutsideDecoderShape(t *testing.T) { + for _, instruction := range []string{ + "UADD8 R0, R1", + "USUB8 $1, R0, R1", + "UADD8.S R0, R1, R2", + "USUB8 R0, R1, R2, R3", + } { + t.Run(strings.ReplaceAll(instruction, " ", "_"), func(t *testing.T) { + source := "TEXT invalid(SB), $0-0\n\t" + instruction + "\n\tRET\n" + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatalf("Parse() error = %v", err) + } + if _, err := Translate(file, Options{ + Goarch: "arm", + TargetTriple: "armv7-unknown-linux-gnueabihf", + Sigs: map[string]FuncSig{ + "invalid": {Name: "invalid", Ret: Void}, + }, + }); err == nil { + t.Fatalf("Translate() accepted invalid form %q", instruction) + } + }) + } +} diff --git a/arm_lower_prefetch.go b/arm_lower_prefetch.go new file mode 100644 index 00000000..8686ec46 --- /dev/null +++ b/arm_lower_prefetch.go @@ -0,0 +1,39 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *armCtx) lowerPreload(op, cond string, ins Instr) (ok bool, terminated bool, err error) { + switch op { + case "PLD": + default: + return false, false, nil + } + if err := armRequireConditionOnlySuffix(ins); err != nil { + return true, false, err + } + if len(ins.Args) != 1 || ins.Args[0].Kind != OpMem { + return true, false, fmt.Errorf("arm PLD expects one register-relative memory operand: %q", ins.Raw) + } + mem := ins.Args[0].Mem + if !isARMGeneralReg(mem.Base) || mem.Index != "" || mem.Sym != "" || mem.Off < -4095 || mem.Off > 4095 { + return true, false, fmt.Errorf("arm PLD operand is absent from Go 1.27's C_SOREG optab row: %q", ins.Raw) + } + if cond != "" && !strings.EqualFold(cond, "AL") { + err := c.emitConditionalEffect(cond, func() error { + _, _, innerErr := c.lowerPreload(op, "", ins) + return innerErr + }) + return true, false, err + } + addr, _, _, err := c.addrI32(mem, false) + if err != nil { + return true, false, err + } + ptr := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i32 %s to ptr\n", ptr, addr) + fmt.Fprintf(c.b, " call void @llvm.prefetch.p0(ptr %%%s, i32 0, i32 3, i32 1)\n", ptr) + return true, false, nil +} diff --git a/arm_lower_reverse_bits.go b/arm_lower_reverse_bits.go new file mode 100644 index 00000000..a6b9af19 --- /dev/null +++ b/arm_lower_reverse_bits.go @@ -0,0 +1,52 @@ +package plan9asm + +import "fmt" + +func (c *armCtx) lowerARMReverseBits(op, cond string, ins Instr) error { + if err := armRequireConditionOnlySuffix(ins); err != nil { + return err + } + if len(ins.Args) != 2 || + ins.Args[0].Kind != OpReg || !isARMGeneralReg(ins.Args[0].Reg) || + ins.Args[1].Kind != OpReg || !isARMGeneralReg(ins.Args[1].Reg) { + return fmt.Errorf("arm %s expects two general registers: %q", op, ins.Raw) + } + source, err := c.loadReg(ins.Args[0].Reg) + if err != nil { + return err + } + result := "" + switch op { + case "REV": + reversed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.bswap.i32(i32 %s)\n", reversed, source) + result = "%" + reversed + case "RBIT": + reversed := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.bitreverse.i32(i32 %s)\n", reversed, source) + result = "%" + reversed + case "REV16": + low := c.newTmp() + high := c.newTmp() + lowShifted := c.newTmp() + highShifted := c.newTmp() + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i32 %s, 16711935\n", low, source) + fmt.Fprintf(c.b, " %%%s = and i32 %s, -16711936\n", high, source) + fmt.Fprintf(c.b, " %%%s = shl i32 %%%s, 8\n", lowShifted, low) + fmt.Fprintf(c.b, " %%%s = lshr i32 %%%s, 8\n", highShifted, high) + fmt.Fprintf(c.b, " %%%s = or i32 %%%s, %%%s\n", combined, lowShifted, highShifted) + result = "%" + combined + case "REVSH": + narrowed := c.newTmp() + reversed := c.newTmp() + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i32 %s to i16\n", narrowed, source) + fmt.Fprintf(c.b, " %%%s = call i16 @llvm.bswap.i16(i16 %%%s)\n", reversed, narrowed) + fmt.Fprintf(c.b, " %%%s = sext i16 %%%s to i32\n", extended, reversed) + result = "%" + extended + default: + return fmt.Errorf("arm: unsupported reverse instruction %s", op) + } + return c.selectRegWrite(ins.Args[1].Reg, cond, result) +} diff --git a/arm_lower_reverse_bits_test.go b/arm_lower_reverse_bits_test.go new file mode 100644 index 00000000..48daa00d --- /dev/null +++ b/arm_lower_reverse_bits_test.go @@ -0,0 +1,53 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +const armReverseBitsForms = `TEXT reverseBits(SB),$0-0 + REV R1, R2 + REV16 R2, R3 + REVSH R3, R4 + RBIT R4, R5 + RET +` + +func TestTranslateARMReverseBitsCompleteFormats(t *testing.T) { + requireARMGoAssemblerResult(t, armReverseBitsForms, true) + ll := translateARMForTest(t, armReverseBitsForms, map[string]FuncSig{ + "example.reverseBits": {Name: "example.reverseBits", Ret: Void}, + }) + for _, want := range []string{ + "call i32 @llvm.bswap.i32", "call i32 @llvm.bitreverse.i32", "sext i16", "and i32", "shl i32", "lshr i32", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM reverse-bit/byte lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-reverse-bits.ll", "arm-reverse-bits.o", ll) +} + +func TestTranslateARMReverseBitsRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"REV (R0), R1", "RBIT R0, R1, R2"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARMGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM reverse-bit/byte optab", instruction) + } + } +} diff --git a/arm_lower_reverse_subtract_carry_test.go b/arm_lower_reverse_subtract_carry_test.go new file mode 100644 index 00000000..e9da4a30 --- /dev/null +++ b/arm_lower_reverse_subtract_carry_test.go @@ -0,0 +1,89 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +const armReverseSubtractCarryForms = `TEXT reverseSubtractCarry(SB),$0-0 + RSC $255, R0, R1 + RSC.S $255, R0, R1 + RSC $255, R0 + RSC.S $255, R0 + RSC R0, R1, R2 + RSC.S R0, R1, R2 + RSC R0, R1 + RSC.S R0, R1 + RSC R0>>28, R1, R2 + RSC R0<<28, R1, R2 + RSC R0->28, R1, R2 + RSC R0@>28, R1, R2 + RSC.S R0>>28, R1, R2 + RSC.S R0<<28, R1, R2 + RSC.S R0->28, R1, R2 + RSC.S R0@>28, R1, R2 + RSC R0<<28, R1 + RSC R0>>28, R1 + RSC R0->28, R1 + RSC R0@>28, R1 + RSC.S R0<<28, R1 + RSC.S R0>>28, R1 + RSC.S R0->28, R1 + RSC.S R0@>28, R1 + RSC R0<>R1, R2, R3 + RSC R0->R1, R2, R3 + RSC R0@>R1, R2, R3 + RSC.S R0<>R1, R2, R3 + RSC.S R0->R1, R2, R3 + RSC.S R0@>R1, R2, R3 + RSC R0<>R1, R2 + RSC R0->R1, R2 + RSC R0@>R1, R2 + RSC.S R0<>R1, R2 + RSC.S R0->R1, R2 + RSC.S R0@>R1, R2 + RET +` + +func TestTranslateARMReverseSubtractCarryCompleteFormats(t *testing.T) { + requireARMGoAssemblerResult(t, armReverseSubtractCarryForms, true) + ll := translateARMForTest(t, armReverseSubtractCarryForms, map[string]FuncSig{ + "example.reverseSubtractCarry": {Name: "example.reverseSubtractCarry", Ret: Void}, + }) + for _, want := range []string{ + "call i32 @llvm.fshr.i32", "sub i32", "load i1", "xor i1", "icmp ult i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("RSC lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-rsc.ll", "arm-rsc.o", ll) +} + +func TestTranslateARMReverseSubtractCarryRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"RSC R0", "RSC (R0), R1"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARMGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM RSC optab", instruction) + } + } +} diff --git a/arm_lower_signed_move_alias_test.go b/arm_lower_signed_move_alias_test.go new file mode 100644 index 00000000..5db02f2b --- /dev/null +++ b/arm_lower_signed_move_alias_test.go @@ -0,0 +1,94 @@ +//go:build !llgo + +package plan9asm + +import ( + "os" + "os/exec" + "path/filepath" + "runtime" + "strings" + "testing" +) + +const armSignedMoveAliasForms = `TEXT signedMoveAliases(SB),$0-0 + MOVBS R5, R6 + MOVBS R1, (R2) + MOVBS.P R1, (R2) + MOVBS.W R1, 32(R2) + MOVBS (R2), R1 + MOVBS.P 32(R2), R1 + MOVBS.W -32(R2), R1 + MOVBS R0, math·Exp(SB) + MOVBS math·Exp(SB), R0 + MOVBS R2@>0, R8 + MOVHS R5, R6 + MOVHS R4, (R3) + MOVHS.P R4, (R3) + MOVHS.W R3, 32(R4) + MOVHS (R9), R8 + MOVHS.P 34(R9), R8 + MOVHS.W -36(R9), R8 + MOVHS R0, math·Exp(SB) + MOVHS math·Exp(SB), R0 + MOVHS R3@>8, R9 + RET +` + +func requireARMGoAssemblerResult(t *testing.T, src string, wantSuccess bool) { + t.Helper() + if !goToolchainAtLeast(runtime.Version(), 1, 27) { + return + } + dir := t.TempDir() + asm := filepath.Join(dir, "forms.s") + if err := os.WriteFile(asm, []byte(src), 0o600); err != nil { + t.Fatal(err) + } + cmd := exec.Command("go", "tool", "asm", "-p", "example.com/forms", "-o", filepath.Join(dir, "forms.o"), asm) + cmd.Env = append(os.Environ(), "GOOS=linux", "GOARCH=arm") + out, err := cmd.CombinedOutput() + if wantSuccess && err != nil { + t.Fatalf("Go 1.27 ARM assembler rejected accepted forms: %v\n%s", err, out) + } + if !wantSuccess && err == nil { + t.Fatalf("Go 1.27 ARM assembler accepted a form expected outside the optab:\n%s", src) + } +} + +func TestTranslateARMSignedMoveAliasCompleteFormats(t *testing.T) { + requireARMGoAssemblerResult(t, armSignedMoveAliasForms, true) + ll := translateARMForTest(t, armSignedMoveAliasForms, map[string]FuncSig{ + "example.signedMoveAliases": {Name: "example.signedMoveAliases", Ret: Void}, + }) + for _, want := range []string{ + "sext i8", "sext i16", "trunc i32", "llvm.fshr.i32", "@math.Exp", + } { + if !strings.Contains(ll, want) { + t.Fatalf("signed move alias lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-signed-move-alias.ll", "arm-signed-move-alias.o", ll) +} + +func TestTranslateARMSignedMoveAliasRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"MOVBS R1", "MOVHS R1, R2, R3"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARMGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM MOVBS/MOVHS optab", instruction) + } + } +} diff --git a/arm_lower_signed_multiply.go b/arm_lower_signed_multiply.go new file mode 100644 index 00000000..baab8eb1 --- /dev/null +++ b/arm_lower_signed_multiply.go @@ -0,0 +1,163 @@ +package plan9asm + +import ( + "fmt" + "strings" +) + +func (c *armCtx) lowerARMSignedMultiply(op, cond string, setFlags bool, ins Instr) error { + for _, suffix := range armInstructionSuffixes(ins) { + if suffix == "" || armCondCodes[suffix] || suffix == "S" && op == "MULL" { + continue + } + return fmt.Errorf("arm %s suffix %q is absent from the Go 1.27 optab: %q", op, suffix, ins.Raw) + } + if setFlags && op != "MULL" { + return fmt.Errorf("arm %s does not accept the .S suffix: %q", op, ins.Raw) + } + loadRegOperand := func(operand Operand) (string, error) { + if operand.Kind != OpReg || !isARMGeneralReg(operand.Reg) { + return "", fmt.Errorf("arm %s accepts only general-register operands: %q", op, ins.Raw) + } + return c.loadReg(operand.Reg) + } + signed64 := func(value string) string { + name := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sext i32 %s to i64\n", name, value) + return "%" + name + } + signedHalf := func(value string, top bool) string { + if top { + name := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ashr i32 %s, 16\n", name, value) + return "%" + name + } + narrow := c.newTmp() + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i32 %s to i16\n", narrow, value) + fmt.Fprintf(c.b, " %%%s = sext i16 %%%s to i32\n", extended, narrow) + return "%" + extended + } + multiply64 := func(first, second string) string { + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i64 %s, %s\n", product, signed64(first), signed64(second)) + return "%" + product + } + highWord := func(product string) string { + shifted := c.newTmp() + word := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ashr i64 %s, 32\n", shifted, product) + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", word, shifted) + return "%" + word + } + + if op == "MULL" { + if len(ins.Args) != 3 || ins.Args[2].Kind != OpRegList || len(ins.Args[2].RegList) != 2 || + !armRegListAllGPR(ins.Args[2].RegList) { + return fmt.Errorf("arm MULL expects src, src, (hi,lo): %q", ins.Raw) + } + first, err := loadRegOperand(ins.Args[0]) + if err != nil { + return err + } + second, err := loadRegOperand(ins.Args[1]) + if err != nil { + return err + } + product := multiply64(first, second) + low := c.newTmp() + highShifted := c.newTmp() + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", low, product) + fmt.Fprintf(c.b, " %%%s = lshr i64 %s, 32\n", highShifted, product) + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", high, highShifted) + if err := c.selectRegPairWrite(ins.Args[2].RegList[0], ins.Args[2].RegList[1], cond, "%"+high, "%"+low); err != nil { + return err + } + if setFlags { + execute := "true" + if cond != "" && !strings.EqualFold(cond, "AL") { + execute, err = c.condValue(cond) + if err != nil { + return err + } + } + zero := c.newTmp() + negative := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp eq i64 %s, 0\n", zero, product) + fmt.Fprintf(c.b, " %%%s = icmp slt i64 %s, 0\n", negative, product) + c.storeFlagPredicate(c.flagsZSlot, "%"+zero, execute) + c.storeFlagPredicate(c.flagsNSlot, "%"+negative, execute) + c.flagsWritten = true + } + return nil + } + + wantArgs := 3 + if op == "MMULA" || op == "MMULS" || op == "MULABB" || op == "MULAWB" || op == "MULAWT" || op == "MULS" { + wantArgs = 4 + } + if len(ins.Args) != wantArgs { + return fmt.Errorf("arm %s expects %d general-register operands: %q", op, wantArgs, ins.Raw) + } + values := make([]string, len(ins.Args)) + for i, operand := range ins.Args { + value, err := loadRegOperand(operand) + if err != nil { + return err + } + values[i] = value + } + result := "" + switch op { + case "MMUL", "MMULA", "MMULS": + high := highWord(multiply64(values[0], values[1])) + if op == "MMUL" { + result = high + } else { + combined := c.newTmp() + llvmOp := "add" + if op == "MMULS" { + llvmOp = "sub" + fmt.Fprintf(c.b, " %%%s = sub i32 %s, %s\n", combined, values[2], high) + } else { + fmt.Fprintf(c.b, " %%%s = %s i32 %s, %s\n", combined, llvmOp, high, values[2]) + } + result = "%" + combined + } + case "MULBB", "MULABB": + first := signedHalf(values[0], false) + second := signedHalf(values[1], false) + product := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i32 %s, %s\n", product, first, second) + result = "%" + product + if op == "MULABB" { + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %s\n", combined, result, values[2]) + result = "%" + combined + } + case "MULWB", "MULWT", "MULAWB", "MULAWT": + top := op == "MULWT" || op == "MULAWT" + half := signedHalf(values[0], top) + product := multiply64(half, values[1]) + shifted := c.newTmp() + word := c.newTmp() + fmt.Fprintf(c.b, " %%%s = ashr i64 %s, 16\n", shifted, product) + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", word, shifted) + result = "%" + word + if op == "MULAWB" || op == "MULAWT" { + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %s\n", combined, result, values[2]) + result = "%" + combined + } + case "MULS": + product := c.newTmp() + combined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = mul i32 %s, %s\n", product, values[0], values[1]) + fmt.Fprintf(c.b, " %%%s = sub i32 %s, %%%s\n", combined, values[2], product) + result = "%" + combined + default: + return fmt.Errorf("arm: unsupported signed multiply instruction %s", op) + } + return c.selectRegWrite(ins.Args[len(ins.Args)-1].Reg, cond, result) +} diff --git a/arm_lower_signed_multiply_test.go b/arm_lower_signed_multiply_test.go new file mode 100644 index 00000000..b32568df --- /dev/null +++ b/arm_lower_signed_multiply_test.go @@ -0,0 +1,61 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +const armSignedMultiplyForms = `TEXT signedMultiplyForms(SB),$0-0 + MULAWT R1, R2, R3, R4 + MULAWB R1, R2, R3, R4 + MULS R1, R2, R3, R4 + MMULA R1, R2, R3, R4 + MMULS R1, R2, R3, R4 + MULABB R1, R2, R3, R4 + MULL R1, R2, (R4, R3) + MULL.S R1, R2, (R4, R3) + MMUL R1, R2, R3 + MULBB R1, R2, R3 + MULWB R1, R2, R3 + MULWT R1, R2, R3 + RET +` + +func TestTranslateARMSignedMultiplyCompleteFormats(t *testing.T) { + requireARMGoAssemblerResult(t, armSignedMultiplyForms, true) + ll := translateARMForTest(t, armSignedMultiplyForms, map[string]FuncSig{ + "example.signedMultiplyForms": {Name: "example.signedMultiplyForms", Ret: Void}, + }) + for _, want := range []string{ + "sext i16", "sext i32", "mul i64", "ashr i64", "add i32", "sub i32", "icmp eq i64", "icmp slt i64", + } { + if !strings.Contains(ll, want) { + t.Fatalf("ARM signed multiply lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-signed-multiply.ll", "arm-signed-multiply.o", ll) +} + +func TestTranslateARMSignedMultiplyRejectsFormsOutsideGoOptab(t *testing.T) { + for _, instruction := range []string{"MMUL R0, R1", "MULBB (R0), R1, R2", "MULL R0, R1, R2"} { + source := "TEXT bad(SB),$0-0\n\t" + instruction + "\n\tRET\n" + requireARMGoAssemblerResult(t, source, false) + file, err := Parse(ArchARM, source) + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "armv7-unknown-linux-gnueabihf", + Goarch: "arm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted %q outside Go 1.27's ARM signed-multiply optab", instruction) + } + } +} diff --git a/arm_lower_word.go b/arm_lower_word.go new file mode 100644 index 00000000..5b8c164c --- /dev/null +++ b/arm_lower_word.go @@ -0,0 +1,145 @@ +package plan9asm + +import ( + "fmt" + "math/bits" +) + +type armRawVFPCompare struct { + lhs int + rhs int + zeroRHS bool + bits int + condition string +} + +func decodeARMRawVFPCompare(word uint32) (armRawVFPCompare, bool) { + // VCMP/VCMPE.{F32,F64} Vd,Vm and Vd,#0 share this encoding shape. + // E (quiet/signaling), precision, Vd, Vm, D/M extension bits, zero, and the + // ARM condition field are the variable bits. For F32, D/M select the odd + // half of a D register; for F64 they extend D0..D15 to D16..D31. + const variable = uint32(0xf0000000 | 0x00400000 | 0x00010000 | 0x0000f000 | 0x00000100 | 0x00000080 | 0x00000020 | 0x0000000f) + const base = uint32(0x0eb40a40) + if word&^variable != base { + return armRawVFPCompare{}, false + } + zero := word&(1<<16) != 0 + if zero && word&0x2f != 0 { + return armRawVFPCompare{}, false + } + condition, ok := armRawCondition(word >> 28) + if !ok { + return armRawVFPCompare{}, false + } + bits := 32 + if word&(1<<8) != 0 { + bits = 64 + } + lhs := int((word >> 12) & 0xf) + rhs := int(word & 0xf) + if bits == 32 { + lhs = lhs*2 + int((word>>22)&1) + rhs = rhs*2 + int((word>>5)&1) + } else { + lhs += int((word>>22)&1) * 16 + rhs += int((word>>5)&1) * 16 + } + return armRawVFPCompare{ + lhs: lhs, + rhs: rhs, + zeroRHS: zero, + bits: bits, + condition: condition, + }, true +} + +func armRawVFPBackingReg(number, bits int) Reg { + if bits == 32 { + number /= 2 + } + return Reg(fmt.Sprintf("F%d", number)) +} + +func (c *armCtx) loadARMRawVFPRegValue(number, bits int) (string, error) { + reg := armRawVFPBackingReg(number, bits) + if bits == 64 || number%2 == 0 { + return c.loadARMFloatRegValue(reg, bits) + } + wide, err := c.loadFReg(reg) + if err != nil { + return "", err + } + shifted := c.newTmp() + narrow := c.newTmp() + converted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i64 %s, 32\n", shifted, wide) + fmt.Fprintf(c.b, " %%%s = trunc i64 %%%s to i32\n", narrow, shifted) + fmt.Fprintf(c.b, " %%%s = bitcast i32 %%%s to float\n", converted, narrow) + return "%" + converted, nil +} + +func armRawCondition(value uint32) (string, bool) { + conditions := []string{"EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "AL"} + if value >= uint32(len(conditions)) { + return "", false + } + return conditions[value], true +} + +// lowerRawWord recognizes ARM instructions that older assembly used as raw +// encodings because the contemporary Go assembler could not spell them. Keep +// the decoder deliberately narrow: an unknown word remains an opaque directive. +func (c *armCtx) lowerRawWord(ins Instr) (bool, error) { + if len(ins.Args) != 1 || ins.Args[0].Kind != OpImm { + return false, nil + } + word := uint32(ins.Args[0].Imm) + switch word { + case 0xe320f001: // YIELD, encoded explicitly so it remains a NOP before ARMv6K. + c.b.WriteString(" call void asm sideeffect \".long 0xe320f001\", \"~{memory}\"()\n") + return true, nil + } + if immediate, ok := decodeARMRawVFPImmediate(word); ok { + return true, c.lowerRawVFPImmediate(immediate) + } + if compare, ok := decodeARMRawVFPCompare(word); ok { + lhs, err := c.loadARMRawVFPRegValue(compare.lhs, compare.bits) + if err != nil { + return true, err + } + rhs := "0.000000e+00" + if !compare.zeroRHS { + rhs, err = c.loadARMRawVFPRegValue(compare.rhs, compare.bits) + if err != nil { + return true, err + } + } + floatType := "float" + if compare.bits == 64 { + floatType = "double" + } + return true, c.setARMFloatCompareFlags(lhs, rhs, floatType, compare.condition) + } + if word>>28 != 0xe || word&(3<<26) != 0 || (word>>21)&0xf != 8 || word&(1<<20) == 0 { + return false, nil + } + rn := Reg(fmt.Sprintf("R%d", (word>>16)&0xf)) + operand2 := word & 0xfff + var src Operand + if word&(1<<25) != 0 { + rotate := int(((operand2 >> 8) & 0xf) * 2) + value := bits.RotateLeft32(operand2&0xff, -rotate) + src = Operand{Kind: OpImm, Imm: int64(value)} + } else { + if operand2&0xff0 != 0 { + return false, nil + } + src = Operand{Kind: OpReg, Reg: Reg(fmt.Sprintf("R%d", operand2&0xf))} + } + decoded := Instr{ + Op: "TST", + Args: []Operand{src, {Kind: OpReg, Reg: rn}}, + Raw: ins.Raw, + } + return true, c.lowerARMCompare("TST", decoded) +} diff --git a/arm_lower_word_extend.go b/arm_lower_word_extend.go new file mode 100644 index 00000000..4bd3061d --- /dev/null +++ b/arm_lower_word_extend.go @@ -0,0 +1,49 @@ +package plan9asm + +import "fmt" + +type armRawSXTB struct { + condition string + rotation int + source int + destination int +} + +func armConditionName(code int) string { + return [...]string{"EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "AL"}[code] +} + +// decodeARMRawSXTB covers every A32 SXTB Rd, Rm{, ROR #8|16|24} +// encoding: all four rotations, every register field, and the 15 executable +// conditions. Condition 0xf belongs to the unconditional instruction space. +func decodeARMRawSXTB(word uint32) (armRawSXTB, bool) { + if word&0x0fff03f0 != 0x06af0070 || word>>28 == 0xf { + return armRawSXTB{}, false + } + return armRawSXTB{ + condition: armConditionName(int(word >> 28)), + rotation: int(word>>10&3) * 8, + source: int(word) & 15, + destination: int(word>>12) & 15, + }, true +} + +func (c *armCtx) lowerRawSXTB(form armRawSXTB) error { + if form.source == 15 || form.destination == 15 { + return fmt.Errorf("arm SXTB cannot safely use PC") + } + source, err := c.loadReg(Reg(fmt.Sprintf("R%d", form.source))) + if err != nil { + return err + } + if form.rotation != 0 { + rotated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 @llvm.fshr.i32(i32 %s, i32 %s, i32 %d)\n", rotated, source, source, form.rotation) + source = "%" + rotated + } + narrowed := c.newTmp() + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i32 %s to i8\n", narrowed, source) + fmt.Fprintf(c.b, " %%%s = sext i8 %%%s to i32\n", extended, narrowed) + return c.selectRegWrite(Reg(fmt.Sprintf("R%d", form.destination)), form.condition, "%"+extended) +} diff --git a/arm_lower_word_ldrexd_test.go b/arm_lower_word_ldrexd_test.go new file mode 100644 index 00000000..dc83e859 --- /dev/null +++ b/arm_lower_word_ldrexd_test.go @@ -0,0 +1,25 @@ +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARMRawLDREXDDecoderFormat(t *testing.T) { + ll := translateARMForTest(t, `TEXT ·rawLDREXD(SB),NOSPLIT,$0-0 + WORD $0xe1bd0f9f // LDREXD [SP], R1, R0 + WORD $0xe1a90f98 // STREXD [R9], R9, R8, R0 + WORD $0xf57ff01f // CLREX + RET +`, map[string]FuncSig{"example.rawLDREXD": {Name: "example.rawLDREXD", Ret: Void}}) + for _, want := range []string{"load atomic i64", "cmpxchg ptr", "store i32", "exclusive_valid", `asm sideeffect "clrex"`} { + if !strings.Contains(ll, want) { + t.Fatalf("raw LDREXD lowering omitted %q:\n%s", want, ll) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-ldrexd.ll", "arm-raw-ldrexd.o", ll) +} diff --git a/arm_lower_word_neon_convert_float32.go b/arm_lower_word_neon_convert_float32.go new file mode 100644 index 00000000..aaf1f78e --- /dev/null +++ b/arm_lower_word_neon_convert_float32.go @@ -0,0 +1,63 @@ +package plan9asm + +import "fmt" + +type armRawNEONConvertFloat32 struct { + toFloat bool + unsigned bool + quad bool + destination int + source int +} + +// decodeARMRawNEONConvertFloat32 covers all eight classic A32 NEON VCVT +// integer/float32 forms: signed or unsigned, both directions, and D or Q +// vectors. Fixed-point, FP16, and ARMv8 directed-rounding encodings are +// separate architectural families. +func decodeARMRawNEONConvertFloat32(word uint32) (armRawNEONConvertFloat32, bool) { + if word&0xffbf0010 != 0xf3bb0000 { + return armRawNEONConvertFloat32{}, false + } + op := int(word>>7) & 31 + if op < 0b01100 || op > 0b01111 { + return armRawNEONConvertFloat32{}, false + } + quad := word>>6&1 != 0 + destination := int(word>>12)&15 | int(word>>22&1)*16 + source := int(word)&15 | int(word>>5&1)*16 + if quad && (destination&1 != 0 || source&1 != 0) { + return armRawNEONConvertFloat32{}, false + } + return armRawNEONConvertFloat32{ + toFloat: op == 0b01100 || op == 0b01101, + unsigned: op == 0b01101 || op == 0b01111, + quad: quad, + destination: destination, + source: source, + }, true +} + +func (c *armCtx) lowerRawNEONConvertFloat32(form armRawNEONConvertFloat32) error { + sourceType := "i32" + destinationType := "float" + operation := "sitofp" + if form.toFloat { + if form.unsigned { + operation = "uitofp" + } + } else { + sourceType = "float" + destinationType = "i32" + operation = "fptosi" + if form.unsigned { + operation = "fptoui" + } + } + source, lanes, err := c.loadARMRawNEONVector(form.source, 32, form.quad, sourceType) + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s <%d x %s> %s to <%d x %s>\n", result, operation, lanes, sourceType, source, lanes, destinationType) + return c.storeARMRawNEONVector(form.destination, 32, form.quad, destinationType, "%"+result) +} diff --git a/arm_lower_word_neon_convert_float32_test.go b/arm_lower_word_neon_convert_float32_test.go new file mode 100644 index 00000000..abc44891 --- /dev/null +++ b/arm_lower_word_neon_convert_float32_test.go @@ -0,0 +1,125 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARMRawNEONConvertFloat32(toFloat, unsigned, quad bool, destination, source int) uint32 { + op := 0b01100 + if !toFloat { + op = 0b01110 + } + if unsigned { + op++ + } + word := uint32(0xf3bb0000 | (destination&15)<<12 | op<<7 | source&15) + word |= uint32(destination/16) << 22 + word |= uint32(source/16) << 5 + if quad { + word |= 1 << 6 + } + return word +} + +func TestTranslateARMRawNEONVCVTFloat32GoDSPRegression(t *testing.T) { + const source = `TEXT rawConvertFloat32(SB), $0-0 + WORD $0xf3bb2642 // vcvt.f32.s32 q1, q1 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawConvertFloat32": {Name: "rawConvertFloat32", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sitofp <4 x i32>", `"target-features"="+neon"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON VCVT IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-vcvt.ll", "arm-raw-neon-vcvt.o", ir) +} + +func TestARMRawNEONVCVTFloat32DecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for _, toFloat := range []bool{false, true} { + for _, unsigned := range []bool{false, true} { + for _, quad := range []bool{false, true} { + step := 1 + if quad { + step = 2 + } + for destination := 0; destination < 32; destination += step { + for source := 0; source < 32; source += step { + word := encodeARMRawNEONConvertFloat32(toFloat, unsigned, quad, destination, source) + got, ok := decodeARMRawNEONConvertFloat32(word) + if !ok || got.toFloat != toFloat || got.unsigned != unsigned || got.quad != quad || got.destination != destination || got.source != source { + t.Fatalf("decoded NEON VCVT %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + } + if count != 5120 { + t.Fatalf("covered %d NEON VCVT encodings, want 5120", count) + } +} + +func TestTranslateARMRawNEONVCVTFloat32AllOperations(t *testing.T) { + source := "TEXT rawConvertFloat32All(SB), $0-0\n" + for _, test := range []struct { + toFloat bool + unsigned bool + quad bool + }{ + {true, false, false}, {true, true, false}, {false, false, false}, {false, true, false}, + {true, false, true}, {true, true, true}, {false, false, true}, {false, true, true}, + } { + word := encodeARMRawNEONConvertFloat32(test.toFloat, test.unsigned, test.quad, 0, 2) + source += fmt.Sprintf("\tWORD $%#08x\n", word) + } + source += "\tRET\n" + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawConvertFloat32All": {Name: "rawConvertFloat32All", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sitofp <2 x i32>", "uitofp <4 x i32>", "fptosi <2 x float>", "fptoui <4 x float>"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON VCVT all operations omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-vcvt-all.ll", "arm-raw-neon-vcvt-all.o", ir) +} + +func TestARMRawNEONVCVTFloat32RejectsReservedForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawNEONConvertFloat32(true, false, false, 0, 0) &^ (uint32(31) << 7), + encodeARMRawNEONConvertFloat32(true, false, true, 0, 0) | 1<<12, + encodeARMRawNEONConvertFloat32(true, false, true, 0, 0) | 1, + encodeARMRawNEONConvertFloat32(true, false, false, 0, 0) | 1<<4, + } { + if _, ok := decodeARMRawNEONConvertFloat32(word); ok { + t.Fatalf("NEON VCVT decoder accepted reserved encoding %#08x", word) + } + } +} diff --git a/arm_lower_word_neon_dup.go b/arm_lower_word_neon_dup.go new file mode 100644 index 00000000..9541ba66 --- /dev/null +++ b/arm_lower_word_neon_dup.go @@ -0,0 +1,83 @@ +package plan9asm + +import "fmt" + +type armRawNEONDup struct { + condition string + elementBits int + destination int + core int + quad bool +} + +// decodeARMRawNEONDup covers the complete A32 VDUP (ARM core register) +// family for 8-, 16-, and 32-bit elements and both D and Q destinations. +func decodeARMRawNEONDup(word uint32) (armRawNEONDup, bool) { + if word&0x0f900f5f != 0x0e800b10 { + return armRawNEONDup{}, false + } + condition, ok := armRawCondition(word >> 28) + if !ok { + return armRawNEONDup{}, false + } + bit8 := word>>22&1 != 0 + bit16 := word>>5&1 != 0 + if bit8 && bit16 { + return armRawNEONDup{}, false + } + elementBits := 32 + if bit8 { + elementBits = 8 + } else if bit16 { + elementBits = 16 + } + destination := int(word>>16)&15 | int(word>>7&1)*16 + quad := word>>21&1 != 0 + if quad && destination&1 != 0 { + return armRawNEONDup{}, false + } + return armRawNEONDup{ + condition: condition, + elementBits: elementBits, + destination: destination, + core: int(word>>12) & 15, + quad: quad, + }, true +} + +func (c *armCtx) lowerRawNEONDup(form armRawNEONDup) error { + if form.core == 15 { + return fmt.Errorf("arm NEON VDUP cannot safely use PC") + } + if form.condition != "" && form.condition != "AL" { + condition := form.condition + form.condition = "AL" + return c.emitConditionalEffect(condition, func() error { + return c.lowerRawNEONDup(form) + }) + } + source, err := c.loadReg(Reg(fmt.Sprintf("R%d", form.core))) + if err != nil { + return err + } + element := source + if form.elementBits != 32 { + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i32 %s to i%d\n", narrow, source, form.elementBits) + element = "%" + narrow + } + lanes := 64 / form.elementBits + inserted := c.newTmp() + broadcast := c.newTmp() + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x i%d> poison, i%d %s, i32 0\n", inserted, lanes, form.elementBits, form.elementBits, element) + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x i%d> %%%s, <%d x i%d> poison, <%d x i32> zeroinitializer\n", broadcast, lanes, form.elementBits, inserted, lanes, form.elementBits, lanes) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to i64\n", bits, lanes, form.elementBits, broadcast) + if err := c.storeFReg(armRawVFPBackingReg(form.destination, 64), "%"+bits); err != nil { + return err + } + if form.quad { + return c.storeFReg(armRawVFPBackingReg(form.destination+1, 64), "%"+bits) + } + return nil +} diff --git a/arm_lower_word_neon_dup_test.go b/arm_lower_word_neon_dup_test.go new file mode 100644 index 00000000..101c901f --- /dev/null +++ b/arm_lower_word_neon_dup_test.go @@ -0,0 +1,100 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARMRawNEONDup(condition, elementBits, destination, core int, quad bool) uint32 { + word := uint32(condition)<<28 | 0x0e800b10 | uint32(destination&15)<<16 | uint32(core)<<12 | uint32(destination/16)<<7 + if quad { + word |= 1 << 21 + } + switch elementBits { + case 8: + word |= 1 << 22 + case 16: + word |= 1 << 5 + } + return word +} + +func TestTranslateARMRawNEONDupCompleteForms(t *testing.T) { + const source = `TEXT rawDup(SB), $0-0 + WORD $0xeec00b10 // vdup.8 d0, r0 + WORD $0xeee00b10 // vdup.8 q0, r0 + WORD $0xee834b30 // vdup.16 d3, r4 + WORD $0xeea64b30 // vdup.16 q3, r4 + WORD $0xee8feb10 // vdup.32 d15, r14 + WORD $0xeeaeeb10 // vdup.32 q7, r14 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawDup": {Name: "rawDup", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"shufflevector <8 x i8>", "shufflevector <4 x i16>", "shufflevector <2 x i32>", `"target-features"="+neon"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON VDUP IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-dup.ll", "arm-raw-neon-dup.o", ir) +} + +func TestARMRawNEONDupDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for condition := 0; condition < 15; condition++ { + for _, elementBits := range []int{8, 16, 32} { + for _, quad := range []bool{false, true} { + step := 1 + if quad { + step = 2 + } + for destination := 0; destination < 32; destination += step { + for core := 0; core < 16; core++ { + word := encodeARMRawNEONDup(condition, elementBits, destination, core, quad) + got, ok := decodeARMRawNEONDup(word) + if !ok || got.condition != armConditionName(condition) || got.elementBits != elementBits || got.destination != destination || got.core != core || got.quad != quad { + t.Fatalf("decoded NEON VDUP %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + } + if count == 0 { + t.Fatal("covered no NEON VDUP encodings") + } +} + +func TestARMRawNEONDupRejectsReservedAndUnsafeForms(t *testing.T) { + reserved := encodeARMRawNEONDup(14, 8, 0, 0, false) | 1<<5 + if _, ok := decodeARMRawNEONDup(reserved); ok { + t.Fatal("NEON VDUP decoder accepted reserved size encoding") + } + for _, word := range []uint32{encodeARMRawNEONDup(15, 8, 0, 0, false), encodeARMRawNEONDup(14, 8, 1, 0, true)} { + if _, ok := decodeARMRawNEONDup(word); ok { + t.Fatalf("NEON VDUP decoder accepted reserved encoding %#08x", word) + } + } + word := encodeARMRawNEONDup(14, 8, 0, 15, false) + file, err := Parse(ArchARM, fmt.Sprintf("TEXT badDup(SB), $0-0\n\tWORD $%#08x\n\tRET\n", word)) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"badDup": {Name: "badDup", Ret: Void}}}); err == nil { + t.Fatal("Translate accepted PC as NEON VDUP source") + } +} diff --git a/arm_lower_word_neon_eor.go b/arm_lower_word_neon_eor.go new file mode 100644 index 00000000..c25daf66 --- /dev/null +++ b/arm_lower_word_neon_eor.go @@ -0,0 +1,48 @@ +package plan9asm + +import "fmt" + +type armRawNEONEOR struct { + quad bool + destination int + lhs int + rhs int +} + +// decodeARMRawNEONEOR covers the complete classic A32 Advanced SIMD VEOR +// (register) family for both 64-bit D registers and 128-bit Q registers. +func decodeARMRawNEONEOR(word uint32) (armRawNEONEOR, bool) { + const variable = uint32(0x00400000 | 0x000f0000 | 0x0000f000 | 0x00000080 | 0x00000040 | 0x00000020 | 0x0000000f) + const base = uint32(0xf3000110) + if word&^variable != base { + return armRawNEONEOR{}, false + } + + quad := word>>6&1 != 0 + destination := int(word>>12)&15 | int(word>>22&1)*16 + lhs := int(word>>16)&15 | int(word>>7&1)*16 + rhs := int(word)&15 | int(word>>5&1)*16 + if quad && (destination&1 != 0 || lhs&1 != 0 || rhs&1 != 0) { + return armRawNEONEOR{}, false + } + return armRawNEONEOR{ + quad: quad, + destination: destination, + lhs: lhs, + rhs: rhs, + }, true +} + +func (c *armCtx) lowerRawNEONEOR(form armRawNEONEOR) error { + lhs, lanes, err := c.loadARMRawNEONVector(form.lhs, 64, form.quad, "i64") + if err != nil { + return err + } + rhs, _, err := c.loadARMRawNEONVector(form.rhs, 64, form.quad, "i64") + if err != nil { + return err + } + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = xor <%d x i64> %s, %s\n", result, lanes, lhs, rhs) + return c.storeARMRawNEONVector(form.destination, 64, form.quad, "i64", "%"+result) +} diff --git a/arm_lower_word_neon_eor_test.go b/arm_lower_word_neon_eor_test.go new file mode 100644 index 00000000..906f6992 --- /dev/null +++ b/arm_lower_word_neon_eor_test.go @@ -0,0 +1,86 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARMRawNEONEOR(quad bool, destination, lhs, rhs int) uint32 { + word := uint32(0xf3000110 | (destination&15)<<12 | (lhs&15)<<16 | rhs&15) + word |= uint32(destination/16) << 22 + word |= uint32(lhs/16) << 7 + word |= uint32(rhs/16) << 5 + if quad { + word |= 1 << 6 + } + return word +} + +func TestTranslateARMRawNEONVEORPionTransportRegression(t *testing.T) { + const source = `TEXT rawXor(SB), $0-0 + WORD $0xF3004154 // veor q2, q0, q2 + WORD $0xF3026156 // veor q3, q1, q3 + WORD $0xF3002152 // veor q1, q0, q1 + WORD $0xF3001111 // veor d1, d0, d1 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawXor": {Name: "rawXor", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"xor <2 x i64>", "xor <1 x i64>", `"target-features"="+neon"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON VEOR IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-veor.ll", "arm-raw-neon-veor.o", ir) +} + +func TestARMRawNEONVEORDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for _, quad := range []bool{false, true} { + step := 1 + if quad { + step = 2 + } + for destination := 0; destination < 32; destination += step { + for lhs := 0; lhs < 32; lhs += step { + for rhs := 0; rhs < 32; rhs += step { + word := encodeARMRawNEONEOR(quad, destination, lhs, rhs) + got, ok := decodeARMRawNEONEOR(word) + if !ok || got.quad != quad || got.destination != destination || got.lhs != lhs || got.rhs != rhs { + t.Fatalf("decoded NEON VEOR %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + if count != 36864 { + t.Fatalf("covered %d NEON VEOR encodings, want 36864", count) + } +} + +func TestARMRawNEONVEORRejectsReservedForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawNEONEOR(true, 0, 0, 0) | 1<<12, + encodeARMRawNEONEOR(true, 0, 0, 0) | 1<<16, + encodeARMRawNEONEOR(true, 0, 0, 0) | 1, + encodeARMRawNEONEOR(false, 0, 0, 0) ^ 1<<8, + } { + if got, ok := decodeARMRawNEONEOR(word); ok { + t.Fatalf("NEON VEOR decoder accepted reserved encoding %#08x as %s", word, fmt.Sprint(got)) + } + } +} diff --git a/arm_lower_word_neon_helpers.go b/arm_lower_word_neon_helpers.go new file mode 100644 index 00000000..aa22347a --- /dev/null +++ b/arm_lower_word_neon_helpers.go @@ -0,0 +1,59 @@ +package plan9asm + +import "fmt" + +// loadARMRawNEONVector reads a D register or the consecutive D-register pair +// that encodes a Q register and views the bits as an LLVM vector. +func (c *armCtx) loadARMRawNEONVector(first, elementBits int, quad bool, elementType string) (string, int, error) { + lanes := 64 / elementBits + low, err := c.loadFReg(armRawVFPBackingReg(first, 64)) + if err != nil { + return "", 0, err + } + bits := low + totalBits := 64 + if quad { + lanes *= 2 + totalBits = 128 + high, err := c.loadFReg(armRawVFPBackingReg(first+1, 64)) + if err != nil { + return "", 0, err + } + lowWide := c.newTmp() + highWide := c.newTmp() + highShifted := c.newTmp() + joined := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i64 %s to i128\n", lowWide, low) + fmt.Fprintf(c.b, " %%%s = zext i64 %s to i128\n", highWide, high) + fmt.Fprintf(c.b, " %%%s = shl i128 %%%s, 64\n", highShifted, highWide) + fmt.Fprintf(c.b, " %%%s = or i128 %%%s, %%%s\n", joined, lowWide, highShifted) + bits = "%" + joined + } + vector := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast i%d %s to <%d x %s>\n", vector, totalBits, bits, lanes, elementType) + return "%" + vector, lanes, nil +} + +func (c *armCtx) storeARMRawNEONVector(first, elementBits int, quad bool, elementType, value string) error { + lanes := 64 / elementBits + totalBits := 64 + if quad { + lanes *= 2 + totalBits = 128 + } + bits := c.newTmp() + fmt.Fprintf(c.b, " %%%s = bitcast <%d x %s> %s to i%d\n", bits, lanes, elementType, value, totalBits) + if !quad { + return c.storeFReg(armRawVFPBackingReg(first, 64), "%"+bits) + } + low := c.newTmp() + highWide := c.newTmp() + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", low, bits) + fmt.Fprintf(c.b, " %%%s = lshr i128 %%%s, 64\n", highWide, bits) + fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", high, highWide) + if err := c.storeFReg(armRawVFPBackingReg(first, 64), "%"+low); err != nil { + return err + } + return c.storeFReg(armRawVFPBackingReg(first+1, 64), "%"+high) +} diff --git a/arm_lower_word_neon_minmax.go b/arm_lower_word_neon_minmax.go new file mode 100644 index 00000000..c572091d --- /dev/null +++ b/arm_lower_word_neon_minmax.go @@ -0,0 +1,112 @@ +package plan9asm + +import "fmt" + +type armRawNEONMinMax struct { + minimum bool + floating bool + unsigned bool + quad bool + elementBits int + destination int + lhs int + rhs int +} + +// decodeARMRawNEONMinMax covers the complete classic A32 Advanced SIMD +// VMAX/VMIN family described by LLVM 22's ARMInstrNEON.td: signed and +// unsigned 8/16/32-bit integers plus 16/32-bit floating point, for both D and +// Q vectors. ARMv8 VMAXNM/VMINNM encodings are a separate instruction family. +func decodeARMRawNEONMinMax(word uint32) (armRawNEONMinMax, bool) { + // N3V fixes 31:25=1111001 and bit 23=0. + if word&0xfe800000 != 0xf2000000 { + return armRawNEONMinMax{}, false + } + op := int(word>>8) & 15 + size := int(word>>20) & 3 + minimum := false + floating := false + unsigned := false + elementBits := 0 + switch op { + case 0b0110: + if size == 3 { + return armRawNEONMinMax{}, false + } + minimum = word>>4&1 != 0 + unsigned = word>>24&1 != 0 + elementBits = 8 << size + case 0b1111: + if word>>24&1 != 0 || word>>4&1 != 0 { + return armRawNEONMinMax{}, false + } + floating = true + minimum = size >= 2 + if size&1 == 0 { + elementBits = 32 + } else { + elementBits = 16 + } + default: + return armRawNEONMinMax{}, false + } + + quad := word>>6&1 != 0 + destination := int(word>>12)&15 | int(word>>22&1)*16 + lhs := int(word>>16)&15 | int(word>>7&1)*16 + rhs := int(word)&15 | int(word>>5&1)*16 + if quad && (destination&1 != 0 || lhs&1 != 0 || rhs&1 != 0) { + return armRawNEONMinMax{}, false + } + return armRawNEONMinMax{ + minimum: minimum, + floating: floating, + unsigned: unsigned, + quad: quad, + elementBits: elementBits, + destination: destination, + lhs: lhs, + rhs: rhs, + }, true +} + +func (c *armCtx) lowerRawNEONMinMax(form armRawNEONMinMax) error { + elementType := fmt.Sprintf("i%d", form.elementBits) + if form.floating { + elementType = "half" + if form.elementBits == 32 { + elementType = "float" + } + } + lhs, lanes, err := c.loadARMRawNEONVector(form.lhs, form.elementBits, form.quad, elementType) + if err != nil { + return err + } + rhs, _, err := c.loadARMRawNEONVector(form.rhs, form.elementBits, form.quad, elementType) + if err != nil { + return err + } + result := c.newTmp() + if form.floating { + operation := "maximum" + if form.minimum { + operation = "minimum" + } + fmt.Fprintf(c.b, " %%%s = call <%d x %s> @llvm.%s.v%df%d(<%d x %s> %s, <%d x %s> %s)\n", result, lanes, elementType, operation, lanes, form.elementBits, lanes, elementType, lhs, lanes, elementType, rhs) + } else { + predicate := "sgt" + if form.unsigned { + predicate = "ugt" + } + if form.minimum { + predicate = "slt" + if form.unsigned { + predicate = "ult" + } + } + condition := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %s <%d x %s> %s, %s\n", condition, predicate, lanes, elementType, lhs, rhs) + fmt.Fprintf(c.b, " %%%s = select <%d x i1> %%%s, <%d x %s> %s, <%d x %s> %s\n", result, lanes, condition, lanes, elementType, lhs, lanes, elementType, rhs) + } + return c.storeARMRawNEONVector(form.destination, form.elementBits, form.quad, elementType, "%"+result) +} diff --git a/arm_lower_word_neon_minmax_test.go b/arm_lower_word_neon_minmax_test.go new file mode 100644 index 00000000..53ddfb35 --- /dev/null +++ b/arm_lower_word_neon_minmax_test.go @@ -0,0 +1,154 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARMRawNEONVMAXGoDSPRegression(t *testing.T) { + const source = `TEXT rawMaximum(SB), $0-0 + WORD $0xf2088f42 // vmax.f32 q4, q4, q1 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawMaximum": {Name: "rawMaximum", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "@llvm.maximum.v4f32") { + t.Fatalf("raw NEON VMAX.F32 IR omitted maximum intrinsic:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-vmax.ll", "arm-raw-neon-vmax.o", ir) +} + +func encodeARMRawNEONMinMax(minimum, floating, unsigned, quad bool, elementBits, destination, lhs, rhs int) uint32 { + word := uint32(0xf2000000 | (destination&15)<<12 | (lhs&15)<<16 | rhs&15) + word |= uint32(destination/16) << 22 + word |= uint32(lhs/16) << 7 + word |= uint32(rhs/16) << 5 + if quad { + word |= 1 << 6 + } + if floating { + word |= 0b1111 << 8 + size := 0 + if elementBits == 16 { + size = 1 + } + if minimum { + size += 2 + } + word |= uint32(size) << 20 + } else { + word |= 0b0110 << 8 + word |= uint32(map[int]int{8: 0, 16: 1, 32: 2}[elementBits]) << 20 + if unsigned { + word |= 1 << 24 + } + if minimum { + word |= 1 << 4 + } + } + return word +} + +func TestARMRawNEONMinMaxDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for _, floating := range []bool{false, true} { + for _, minimum := range []bool{false, true} { + unsignedValues := []bool{false, true} + elementSizes := []int{8, 16, 32} + if floating { + unsignedValues = []bool{false} + elementSizes = []int{16, 32} + } + for _, unsigned := range unsignedValues { + for _, quad := range []bool{false, true} { + step := 1 + if quad { + step = 2 + } + for _, elementBits := range elementSizes { + for destination := 0; destination < 32; destination += step { + for lhs := 0; lhs < 32; lhs += step { + for rhs := 0; rhs < 32; rhs += step { + word := encodeARMRawNEONMinMax(minimum, floating, unsigned, quad, elementBits, destination, lhs, rhs) + got, ok := decodeARMRawNEONMinMax(word) + if !ok || got.minimum != minimum || got.floating != floating || got.unsigned != unsigned || got.quad != quad || got.elementBits != elementBits || got.destination != destination || got.lhs != lhs || got.rhs != rhs { + t.Fatalf("decoded NEON min/max %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + } + } + } + } + if count != 589824 { + t.Fatalf("covered %d NEON min/max encodings, want 589824", count) + } +} + +func TestTranslateARMRawNEONMinMaxAllFormats(t *testing.T) { + source := "TEXT rawMinMaxAll(SB), $0-0\n" + for _, minimum := range []bool{false, true} { + for _, unsigned := range []bool{false, true} { + for _, quad := range []bool{false, true} { + for _, bits := range []int{8, 16, 32} { + source += fmt.Sprintf("\tWORD $%#08x\n", encodeARMRawNEONMinMax(minimum, false, unsigned, quad, bits, 0, 2, 4)) + } + } + } + for _, quad := range []bool{false, true} { + for _, bits := range []int{16, 32} { + source += fmt.Sprintf("\tWORD $%#08x\n", encodeARMRawNEONMinMax(minimum, true, false, quad, bits, 0, 2, 4)) + } + } + } + source += "\tRET\n" + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawMinMaxAll": {Name: "rawMinMaxAll", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"icmp sgt <8 x i8>", "icmp ugt <16 x i8>", "icmp slt <2 x i32>", "icmp ult <4 x i32>", "@llvm.maximum.v4f16", "@llvm.maximum.v4f32", "@llvm.minimum.v8f16", "@llvm.minimum.v2f32", "+fullfp16", "+neon"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON min/max formats omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-minmax-all.ll", "arm-raw-neon-minmax-all.o", ir) +} + +func TestARMRawNEONMinMaxRejectsReservedForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawNEONMinMax(false, false, false, false, 8, 0, 0, 0) | 3<<20, + encodeARMRawNEONMinMax(false, true, false, false, 32, 0, 0, 0) | 1<<24, + encodeARMRawNEONMinMax(false, true, false, false, 32, 0, 0, 0) | 1<<4, + encodeARMRawNEONMinMax(false, false, false, true, 8, 0, 0, 0) | 1<<12, + encodeARMRawNEONMinMax(false, false, false, true, 8, 0, 0, 0) | 1<<16, + encodeARMRawNEONMinMax(false, false, false, true, 8, 0, 0, 0) | 1, + } { + if _, ok := decodeARMRawNEONMinMax(word); ok { + t.Fatalf("NEON min/max decoder accepted reserved encoding %#08x", word) + } + } +} diff --git a/arm_lower_word_neon_move_long.go b/arm_lower_word_neon_move_long.go new file mode 100644 index 00000000..38be0cff --- /dev/null +++ b/arm_lower_word_neon_move_long.go @@ -0,0 +1,69 @@ +package plan9asm + +import "fmt" + +type armRawNEONMoveLong struct { + unsigned bool + elementBits int + destination int + source int +} + +// decodeARMRawNEONMoveLong covers the complete A32 VMOVL family: signed and +// unsigned widening from 8-, 16-, or 32-bit lanes in a D register to a Q +// register. +func decodeARMRawNEONMoveLong(word uint32) (armRawNEONMoveLong, bool) { + if word&0xfe800fd0 != 0xf2800a10 { + return armRawNEONMoveLong{}, false + } + var elementBits int + switch word >> 16 & 0x3f { + case 0b001000: + elementBits = 8 + case 0b010000: + elementBits = 16 + case 0b100000: + elementBits = 32 + default: + return armRawNEONMoveLong{}, false + } + destination := int(word>>12)&15 | int(word>>22&1)*16 + if destination&1 != 0 { + return armRawNEONMoveLong{}, false + } + return armRawNEONMoveLong{ + unsigned: word>>24&1 != 0, + elementBits: elementBits, + destination: destination, + source: int(word)&15 | int(word>>5&1)*16, + }, true +} + +func (c *armCtx) lowerRawNEONMoveLong(form armRawNEONMoveLong) error { + sourceBits, err := c.loadFReg(armRawVFPBackingReg(form.source, 64)) + if err != nil { + return err + } + lanes := 64 / form.elementBits + wideBits := form.elementBits * 2 + source := c.newTmp() + result := c.newTmp() + resultBits := c.newTmp() + extend := "sext" + if form.unsigned { + extend = "zext" + } + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to <%d x i%d>\n", source, sourceBits, lanes, form.elementBits) + fmt.Fprintf(c.b, " %%%s = %s <%d x i%d> %%%s to <%d x i%d>\n", result, extend, lanes, form.elementBits, source, lanes, wideBits) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to i128\n", resultBits, lanes, wideBits, result) + low := c.newTmp() + highWide := c.newTmp() + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", low, resultBits) + fmt.Fprintf(c.b, " %%%s = lshr i128 %%%s, 64\n", highWide, resultBits) + fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", high, highWide) + if err := c.storeFReg(armRawVFPBackingReg(form.destination, 64), "%"+low); err != nil { + return err + } + return c.storeFReg(armRawVFPBackingReg(form.destination+1, 64), "%"+high) +} diff --git a/arm_lower_word_neon_move_long_test.go b/arm_lower_word_neon_move_long_test.go new file mode 100644 index 00000000..e80e3485 --- /dev/null +++ b/arm_lower_word_neon_move_long_test.go @@ -0,0 +1,93 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func encodeARMRawNEONMoveLong(unsigned bool, elementBits, destination, source int) uint32 { + word := uint32(0xf2800a10 | (destination&15)<<12 | source&15) + if unsigned { + word |= 1 << 24 + } + word |= uint32(destination/16) << 22 + word |= uint32(map[int]int{8: 0b001000, 16: 0b010000, 32: 0b100000}[elementBits]) << 16 + word |= uint32(source/16) << 5 + return word +} + +func TestTranslateARMRawNEONVMOVLGoDSPRegression(t *testing.T) { + const source = `TEXT rawMoveLong(SB), $0-0 + WORD $0xf2902a34 // vmovl.s16 q1, d20 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawMoveLong": {Name: "rawMoveLong", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sext <4 x i16>", `"target-features"="+neon"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON VMOVL IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-vmovl.ll", "arm-raw-neon-vmovl.o", ir) +} + +func TestARMRawNEONVMOVLDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for _, unsigned := range []bool{false, true} { + for _, elementBits := range []int{8, 16, 32} { + for destination := 0; destination < 32; destination += 2 { + for source := 0; source < 32; source++ { + word := encodeARMRawNEONMoveLong(unsigned, elementBits, destination, source) + got, ok := decodeARMRawNEONMoveLong(word) + if !ok || got.unsigned != unsigned || got.elementBits != elementBits || got.destination != destination || got.source != source { + t.Fatalf("decoded NEON VMOVL %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + if count != 3072 { + t.Fatalf("covered %d NEON VMOVL encodings, want 3072", count) + } +} + +func TestARMRawNEONVMOVLRejectsReservedForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawNEONMoveLong(false, 8, 0, 0) &^ (uint32(0x3f) << 16), + encodeARMRawNEONMoveLong(false, 8, 0, 0) | 1<<12, + encodeARMRawNEONMoveLong(false, 8, 0, 0) | 1<<6, + } { + if _, ok := decodeARMRawNEONMoveLong(word); ok { + t.Fatalf("NEON VMOVL decoder accepted reserved encoding %#08x", word) + } + } + + const unsignedSource = `TEXT rawUnsignedMoveLong(SB), $0-0 + WORD $0xf3880a10 // vmovl.u8 q0, d0 + RET +` + file, err := Parse(ArchARM, unsignedSource) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawUnsignedMoveLong": {Name: "rawUnsignedMoveLong", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "zext <8 x i8>") { + t.Fatalf("unsigned NEON VMOVL omitted zero extension:\n%s", ir) + } +} diff --git a/arm_lower_word_neon_multiply_lane.go b/arm_lower_word_neon_multiply_lane.go new file mode 100644 index 00000000..f66d4b1e --- /dev/null +++ b/arm_lower_word_neon_multiply_lane.go @@ -0,0 +1,82 @@ +package plan9asm + +import "fmt" + +type armRawNEONMultiplyLane struct { + floating bool + quad bool + elementBits int + destination int + lhs int + scalar int + lane int +} + +// decodeARMRawNEONMultiplyLane covers every LLVM 22 ARMInstrNEON VMUL scalar +// lane form: integer i16/i32 and floating f16/f32, D and Q destinations. The +// 16-bit encoding addresses D0..D7 with four lanes; the 32-bit encoding +// addresses D0..D15 with two lanes. +func decodeARMRawNEONMultiplyLane(word uint32) (armRawNEONMultiplyLane, bool) { + if word&0xfe800e50 != 0xf2800840 { + return armRawNEONMultiplyLane{}, false + } + elementBits := 0 + switch word >> 20 & 3 { + case 1: + elementBits = 16 + case 2: + elementBits = 32 + default: + return armRawNEONMultiplyLane{}, false + } + quad := word>>24&1 != 0 + destination := int(word>>12)&15 | int(word>>22&1)*16 + lhs := int(word>>16)&15 | int(word>>7&1)*16 + if quad && (destination&1 != 0 || lhs&1 != 0) { + return armRawNEONMultiplyLane{}, false + } + scalar := int(word) & 15 + lane := int(word>>5) & 1 + if elementBits == 16 { + scalar &= 7 + lane = int(word>>3)&1 | int(word>>5&1)*2 + } + return armRawNEONMultiplyLane{ + floating: word>>8&1 != 0, + quad: quad, + elementBits: elementBits, + destination: destination, + lhs: lhs, + scalar: scalar, + lane: lane, + }, true +} + +func (c *armCtx) lowerRawNEONMultiplyLane(form armRawNEONMultiplyLane) error { + elementType := fmt.Sprintf("i%d", form.elementBits) + operation := "mul" + if form.floating { + elementType = "half" + if form.elementBits == 32 { + elementType = "float" + } + operation = "fmul" + } + lhs, lanes, err := c.loadARMRawNEONVector(form.lhs, form.elementBits, form.quad, elementType) + if err != nil { + return err + } + scalars, scalarLanes, err := c.loadARMRawNEONVector(form.scalar, form.elementBits, false, elementType) + if err != nil { + return err + } + scalar := c.newTmp() + inserted := c.newTmp() + broadcast := c.newTmp() + result := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %s, i32 %d\n", scalar, scalarLanes, elementType, scalars, form.lane) + fmt.Fprintf(c.b, " %%%s = insertelement <%d x %s> poison, %s %%%s, i32 0\n", inserted, lanes, elementType, elementType, scalar) + fmt.Fprintf(c.b, " %%%s = shufflevector <%d x %s> %%%s, <%d x %s> poison, <%d x i32> zeroinitializer\n", broadcast, lanes, elementType, inserted, lanes, elementType, lanes) + fmt.Fprintf(c.b, " %%%s = %s <%d x %s> %s, %%%s\n", result, operation, lanes, elementType, lhs, broadcast) + return c.storeARMRawNEONVector(form.destination, form.elementBits, form.quad, elementType, "%"+result) +} diff --git a/arm_lower_word_neon_multiply_lane_test.go b/arm_lower_word_neon_multiply_lane_test.go new file mode 100644 index 00000000..fee4da2c --- /dev/null +++ b/arm_lower_word_neon_multiply_lane_test.go @@ -0,0 +1,140 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARMRawNEONMultiplyLane(floating, quad bool, elementBits, destination, lhs, scalar, lane int) uint32 { + word := uint32(0xf2800840 | (destination&15)<<12 | (lhs&15)<<16) + if floating { + word |= 1 << 8 + } + if quad { + word |= 1 << 24 + } + word |= uint32(map[int]int{16: 1, 32: 2}[elementBits]) << 20 + word |= uint32(destination/16) << 22 + word |= uint32(lhs/16) << 7 + if elementBits == 16 { + word |= uint32(scalar & 7) + word |= uint32(lane&1) << 3 + word |= uint32(lane/2) << 5 + } else { + word |= uint32(scalar & 15) + word |= uint32(lane) << 5 + } + return word +} + +func TestTranslateARMRawNEONVMULLaneGoDSPRegression(t *testing.T) { + const source = `TEXT rawMultiplyLane(SB), $0-0 + WORD $0xf3a22940 // vmul.f32 q1, q1, d0[0] + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawMultiplyLane": {Name: "rawMultiplyLane", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"extractelement <2 x float>", "fmul <4 x float>", `"target-features"="+neon"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON VMUL-by-lane IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-vmul-lane.ll", "arm-raw-neon-vmul-lane.o", ir) +} + +func TestARMRawNEONVMULLaneDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for _, floating := range []bool{false, true} { + for _, quad := range []bool{false, true} { + step := 1 + if quad { + step = 2 + } + for _, elementBits := range []int{16, 32} { + scalarRegisters := 8 + lanes := 4 + if elementBits == 32 { + scalarRegisters = 16 + lanes = 2 + } + for destination := 0; destination < 32; destination += step { + for lhs := 0; lhs < 32; lhs += step { + for scalar := 0; scalar < scalarRegisters; scalar++ { + for lane := 0; lane < lanes; lane++ { + word := encodeARMRawNEONMultiplyLane(floating, quad, elementBits, destination, lhs, scalar, lane) + got, ok := decodeARMRawNEONMultiplyLane(word) + if !ok || got.floating != floating || got.quad != quad || got.elementBits != elementBits || got.destination != destination || got.lhs != lhs || got.scalar != scalar || got.lane != lane { + t.Fatalf("decoded NEON VMUL-by-lane %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + } + } + } + if count != 163840 { + t.Fatalf("covered %d NEON VMUL-by-lane encodings, want 163840", count) + } +} + +func TestTranslateARMRawNEONVMULLaneAllFormats(t *testing.T) { + source := "TEXT rawMultiplyLaneAll(SB), $0-0\n" + for _, test := range []struct { + floating bool + quad bool + elementBits int + }{ + {false, false, 16}, {false, true, 16}, {false, false, 32}, {false, true, 32}, + {true, false, 16}, {true, true, 16}, {true, false, 32}, {true, true, 32}, + } { + word := encodeARMRawNEONMultiplyLane(test.floating, test.quad, test.elementBits, 0, 2, 1, 1) + source += fmt.Sprintf("\tWORD $%#08x\n", word) + } + source += "\tRET\n" + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawMultiplyLaneAll": {Name: "rawMultiplyLaneAll", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"mul <4 x i16>", "mul <4 x i32>", "fmul <4 x half>", "fmul <4 x float>", "+fullfp16", "+neon"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON VMUL-by-lane formats omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-vmul-lane-all.ll", "arm-raw-neon-vmul-lane-all.o", ir) +} + +func TestARMRawNEONVMULLaneRejectsReservedForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawNEONMultiplyLane(false, false, 16, 0, 0, 0, 0) &^ (uint32(3) << 20), + encodeARMRawNEONMultiplyLane(false, true, 16, 0, 0, 0, 0) | 1<<12, + encodeARMRawNEONMultiplyLane(false, true, 16, 0, 0, 0, 0) | 1<<16, + encodeARMRawNEONMultiplyLane(false, false, 16, 0, 0, 0, 0) | 1<<4, + } { + if _, ok := decodeARMRawNEONMultiplyLane(word); ok { + t.Fatalf("NEON VMUL-by-lane decoder accepted reserved encoding %#08x", word) + } + } +} diff --git a/arm_lower_word_neon_pairwise_minmax.go b/arm_lower_word_neon_pairwise_minmax.go new file mode 100644 index 00000000..e1a2b95f --- /dev/null +++ b/arm_lower_word_neon_pairwise_minmax.go @@ -0,0 +1,117 @@ +package plan9asm + +import "fmt" + +type armRawNEONPairwiseMinMax struct { + minimum bool + floating bool + unsigned bool + elementBits int + destination int + lhs int + rhs int +} + +// decodeARMRawNEONPairwiseMinMax covers every classic A32 VPMAX/VPMIN form +// in LLVM 22's ARMInstrNEON.td: signed and unsigned 8/16/32-bit integers plus +// 16/32-bit floating point. Pairwise forms operate only on D registers. +func decodeARMRawNEONPairwiseMinMax(word uint32) (armRawNEONPairwiseMinMax, bool) { + // N3VDInt fixes 31:25=1111001, bit 23=0, and bit 6=0. + if word&0xfe800040 != 0xf2000000 { + return armRawNEONPairwiseMinMax{}, false + } + op := int(word>>8) & 15 + size := int(word>>20) & 3 + minimum := false + floating := false + unsigned := false + elementBits := 0 + switch op { + case 0b1010: + if size == 3 { + return armRawNEONPairwiseMinMax{}, false + } + minimum = word>>4&1 != 0 + unsigned = word>>24&1 != 0 + elementBits = 8 << size + case 0b1111: + if word>>24&1 == 0 || word>>4&1 != 0 { + return armRawNEONPairwiseMinMax{}, false + } + floating = true + minimum = size >= 2 + if size&1 == 0 { + elementBits = 32 + } else { + elementBits = 16 + } + default: + return armRawNEONPairwiseMinMax{}, false + } + return armRawNEONPairwiseMinMax{ + minimum: minimum, + floating: floating, + unsigned: unsigned, + elementBits: elementBits, + destination: int(word>>12)&15 | int(word>>22&1)*16, + lhs: int(word>>16)&15 | int(word>>7&1)*16, + rhs: int(word)&15 | int(word>>5&1)*16, + }, true +} + +func (c *armCtx) lowerRawNEONPairwiseMinMax(form armRawNEONPairwiseMinMax) error { + elementType := fmt.Sprintf("i%d", form.elementBits) + if form.floating { + elementType = "half" + if form.elementBits == 32 { + elementType = "float" + } + } + lhs, lanes, err := c.loadARMRawNEONVector(form.lhs, form.elementBits, false, elementType) + if err != nil { + return err + } + rhs, _, err := c.loadARMRawNEONVector(form.rhs, form.elementBits, false, elementType) + if err != nil { + return err + } + result := "poison" + for destinationLane := 0; destinationLane < lanes; destinationLane++ { + source := lhs + sourceLane := destinationLane * 2 + if destinationLane >= lanes/2 { + source = rhs + sourceLane = (destinationLane - lanes/2) * 2 + } + first := c.newTmp() + second := c.newTmp() + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %s, i32 %d\n", first, lanes, elementType, source, sourceLane) + fmt.Fprintf(c.b, " %%%s = extractelement <%d x %s> %s, i32 %d\n", second, lanes, elementType, source, sourceLane+1) + selected := c.newTmp() + if form.floating { + operation := "maximum" + if form.minimum { + operation = "minimum" + } + fmt.Fprintf(c.b, " %%%s = call %s @llvm.%s.f%d(%s %%%s, %s %%%s)\n", selected, elementType, operation, form.elementBits, elementType, first, elementType, second) + } else { + predicate := "sgt" + if form.unsigned { + predicate = "ugt" + } + if form.minimum { + predicate = "slt" + if form.unsigned { + predicate = "ult" + } + } + condition := c.newTmp() + fmt.Fprintf(c.b, " %%%s = icmp %s %s %%%s, %%%s\n", condition, predicate, elementType, first, second) + fmt.Fprintf(c.b, " %%%s = select i1 %%%s, %s %%%s, %s %%%s\n", selected, condition, elementType, first, elementType, second) + } + inserted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = insertelement <%d x %s> %s, %s %%%s, i32 %d\n", inserted, lanes, elementType, result, elementType, selected, destinationLane) + result = "%" + inserted + } + return c.storeARMRawNEONVector(form.destination, form.elementBits, false, elementType, result) +} diff --git a/arm_lower_word_neon_pairwise_minmax_test.go b/arm_lower_word_neon_pairwise_minmax_test.go new file mode 100644 index 00000000..b6249fca --- /dev/null +++ b/arm_lower_word_neon_pairwise_minmax_test.go @@ -0,0 +1,140 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARMRawNEONVPMAXGoDSPRegression(t *testing.T) { + const source = `TEXT rawPairwiseMaximum(SB), $0-0 + WORD $0xf3004f01 // vpmax.f32 d4, d0, d1 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawPairwiseMaximum": {Name: "rawPairwiseMaximum", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "@llvm.maximum.f32") { + t.Fatalf("raw NEON VPMAX.F32 IR omitted maximum intrinsic:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-vpmax.ll", "arm-raw-neon-vpmax.o", ir) +} + +func encodeARMRawNEONPairwiseMinMax(minimum, floating, unsigned bool, elementBits, destination, lhs, rhs int) uint32 { + word := uint32(0xf2000000 | (destination&15)<<12 | (lhs&15)<<16 | rhs&15) + word |= uint32(destination/16) << 22 + word |= uint32(lhs/16) << 7 + word |= uint32(rhs/16) << 5 + if floating { + word |= 1 << 24 + word |= 0b1111 << 8 + size := 0 + if elementBits == 16 { + size = 1 + } + if minimum { + size += 2 + } + word |= uint32(size) << 20 + } else { + word |= 0b1010 << 8 + word |= uint32(map[int]int{8: 0, 16: 1, 32: 2}[elementBits]) << 20 + if unsigned { + word |= 1 << 24 + } + if minimum { + word |= 1 << 4 + } + } + return word +} + +func TestARMRawNEONPairwiseMinMaxDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for _, floating := range []bool{false, true} { + for _, minimum := range []bool{false, true} { + unsignedValues := []bool{false, true} + elementSizes := []int{8, 16, 32} + if floating { + unsignedValues = []bool{false} + elementSizes = []int{16, 32} + } + for _, unsigned := range unsignedValues { + for _, elementBits := range elementSizes { + for destination := 0; destination < 32; destination++ { + for lhs := 0; lhs < 32; lhs++ { + for rhs := 0; rhs < 32; rhs++ { + word := encodeARMRawNEONPairwiseMinMax(minimum, floating, unsigned, elementBits, destination, lhs, rhs) + got, ok := decodeARMRawNEONPairwiseMinMax(word) + if !ok || got.minimum != minimum || got.floating != floating || got.unsigned != unsigned || got.elementBits != elementBits || got.destination != destination || got.lhs != lhs || got.rhs != rhs { + t.Fatalf("decoded NEON pairwise min/max %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + } + } + } + if count != 524288 { + t.Fatalf("covered %d NEON pairwise min/max encodings, want 524288", count) + } +} + +func TestTranslateARMRawNEONPairwiseMinMaxAllFormats(t *testing.T) { + source := "TEXT rawPairwiseMinMaxAll(SB), $0-0\n" + for _, minimum := range []bool{false, true} { + for _, unsigned := range []bool{false, true} { + for _, bits := range []int{8, 16, 32} { + source += fmt.Sprintf("\tWORD $%#08x\n", encodeARMRawNEONPairwiseMinMax(minimum, false, unsigned, bits, 0, 1, 2)) + } + } + for _, bits := range []int{16, 32} { + source += fmt.Sprintf("\tWORD $%#08x\n", encodeARMRawNEONPairwiseMinMax(minimum, true, false, bits, 0, 1, 2)) + } + } + source += "\tRET\n" + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawPairwiseMinMaxAll": {Name: "rawPairwiseMinMaxAll", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"icmp sgt i8", "icmp ugt i16", "icmp slt i32", "icmp ult i8", "@llvm.maximum.f16", "@llvm.maximum.f32", "@llvm.minimum.f16", "@llvm.minimum.f32", "+fullfp16", "+neon"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON pairwise min/max formats omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-pairwise-minmax-all.ll", "arm-raw-neon-pairwise-minmax-all.o", ir) +} + +func TestARMRawNEONPairwiseMinMaxRejectsReservedForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawNEONPairwiseMinMax(false, false, false, 8, 0, 0, 0) | 3<<20, + encodeARMRawNEONPairwiseMinMax(false, true, false, 32, 0, 0, 0) &^ (1 << 24), + encodeARMRawNEONPairwiseMinMax(false, true, false, 32, 0, 0, 0) | 1<<4, + encodeARMRawNEONPairwiseMinMax(false, false, false, 8, 0, 0, 0) | 1<<6, + } { + if _, ok := decodeARMRawNEONPairwiseMinMax(word); ok { + t.Fatalf("NEON pairwise min/max decoder accepted reserved encoding %#08x", word) + } + } +} diff --git a/arm_lower_word_neon_structure.go b/arm_lower_word_neon_structure.go new file mode 100644 index 00000000..3257e100 --- /dev/null +++ b/arm_lower_word_neon_structure.go @@ -0,0 +1,125 @@ +package plan9asm + +import "fmt" + +// armRawNEONStructureOne describes the A32 Advanced SIMD VLD1/VST1 +// "multiple single elements" encoding. Each transfer moves one to four +// consecutive 64-bit D registers without interleaving their elements. +type armRawNEONStructureOne struct { + load bool + base int + offset int + first int + count int + elementBits int + alignment int +} + +// decodeARMRawNEONStructureOne covers every VLD1/VST1 multiple-single-element +// form described by LLVM's ARMInstrNEON.td VLD1D/VLD1Q/VLD1D3/VLD1D4 and the +// corresponding VST1 classes. offset 15 means no writeback; offset 13 selects +// fixed writeback by the transfer size; every other value is a register +// post-index. +func decodeARMRawNEONStructureOne(word uint32) (armRawNEONStructureOne, bool) { + // 11110100 D L 0 Rn Vd type size align Rm + if word&0xff900000 != 0xf4000000 { + return armRawNEONStructureOne{}, false + } + + typeField := int(word>>8) & 15 + count := 0 + maxAlignmentCode := 0 + switch typeField { + case 0b0111: + count = 1 + maxAlignmentCode = 1 // omitted or 64-bit + case 0b1010: + count = 2 + maxAlignmentCode = 2 // omitted, 64-bit, or 128-bit + case 0b0110: + count = 3 + maxAlignmentCode = 1 // omitted or 64-bit + case 0b0010: + count = 4 + maxAlignmentCode = 3 // omitted, 64-, 128-, or 256-bit + default: + return armRawNEONStructureOne{}, false + } + + alignmentCode := int(word>>4) & 3 + if alignmentCode > maxAlignmentCode { + return armRawNEONStructureOne{}, false + } + first := int(word>>12)&15 | int(word>>22&1)*16 + if first+count > 32 { + return armRawNEONStructureOne{}, false + } + alignment := 0 + if alignmentCode != 0 { + alignment = 4 << alignmentCode // 1,2,3 encode 8,16,32 bytes. + } + return armRawNEONStructureOne{ + load: word>>21&1 != 0, + base: int(word>>16) & 15, + offset: int(word) & 15, + first: first, + count: count, + elementBits: 8 << (word >> 6 & 3), + alignment: alignment, + }, true +} + +func (c *armCtx) lowerRawNEONStructureOne(form armRawNEONStructureOne) error { + if form.base == 15 { + return fmt.Errorf("arm NEON VLD1/VST1 cannot safely use PC as its base") + } + baseReg := Reg(fmt.Sprintf("R%d", form.base)) + base, err := c.loadReg(baseReg) + if err != nil { + return err + } + alignment := form.alignment + if alignment == 0 { + alignment = 1 + } + for i := 0; i < form.count; i++ { + address := base + if offset := i * 8; offset != 0 { + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %d\n", adjusted, base, offset) + address = "%" + adjusted + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i32 %s to ptr\n", pointer, address) + register := armRawVFPBackingReg(form.first+i, 64) + if form.load { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i64, ptr %%%s, align %d\n", value, pointer, alignment) + if err := c.storeFReg(register, "%"+value); err != nil { + return err + } + continue + } + value, err := c.loadFReg(register) + if err != nil { + return err + } + fmt.Fprintf(c.b, " store i64 %s, ptr %%%s, align %d\n", value, pointer, alignment) + } + + if form.offset == 15 { + return nil + } + increment := "" + if form.offset == 13 { + increment = fmt.Sprintf("%d", form.count*8) + } else { + increment, err = c.loadReg(Reg(fmt.Sprintf("R%d", form.offset))) + if err != nil { + return err + } + } + updated := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %s\n", updated, base, increment) + return c.storeReg(baseReg, "%"+updated) +} diff --git a/arm_lower_word_neon_structure_test.go b/arm_lower_word_neon_structure_test.go new file mode 100644 index 00000000..9441f1a9 --- /dev/null +++ b/arm_lower_word_neon_structure_test.go @@ -0,0 +1,132 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARMRawNEONStructureOne(load bool, base, offset, first, count, elementBits, alignment int) uint32 { + typeField := map[int]int{1: 0b0111, 2: 0b1010, 3: 0b0110, 4: 0b0010}[count] + word := uint32(0xf4000000 | base<<16 | (first&15)<<12 | typeField<<8 | offset) + if load { + word |= 1 << 21 + } + word |= uint32(first/16) << 22 + word |= uint32(map[int]int{8: 0, 16: 1, 32: 2, 64: 3}[elementBits]) << 6 + word |= uint32(map[int]int{0: 0, 8: 1, 16: 2, 32: 3}[alignment]) << 4 + return word +} + +func TestTranslateARMRawNEONVLD1VST1PionTransportRegression(t *testing.T) { + const source = `TEXT rawStructure(SB), $0-0 + WORD $0xF421020D // vld1.u8 {q0, q1}, [r1]! + WORD $0xF422420D // vld1.u8 {q2, q3}, [r2]! + WORD $0xF400420D // vst1.u8 {q2, q3}, [r0]! + WORD $0xF4210A0D // vld1.u8 q0, [r1]! + WORD $0xF4002A0D // vst1.u8 q1, [r0]! + WORD $0xF421070D // vld1.u8 d0, [r1]! + WORD $0xF400170D // vst1.u8 d1, [r0]! + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawStructure": {Name: "rawStructure", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load i64, ptr", "store i64", `"target-features"="+neon"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON VLD1/VST1 IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-structure.ll", "arm-raw-neon-structure.o", ir) +} + +func TestARMRawNEONVLD1VST1DecoderCoversEveryEncodingField(t *testing.T) { + countForms := 0 + alignmentsByCount := map[int][]int{1: {0, 8}, 2: {0, 8, 16}, 3: {0, 8}, 4: {0, 8, 16, 32}} + for _, load := range []bool{false, true} { + for count := 1; count <= 4; count++ { + for _, elementBits := range []int{8, 16, 32, 64} { + for _, alignment := range alignmentsByCount[count] { + for first := 0; first+count <= 32; first++ { + for base := 0; base < 16; base++ { + for offset := 0; offset < 16; offset++ { + word := encodeARMRawNEONStructureOne(load, base, offset, first, count, elementBits, alignment) + got, ok := decodeARMRawNEONStructureOne(word) + if !ok || got.load != load || got.base != base || got.offset != offset || got.first != first || got.count != count || got.elementBits != elementBits || got.alignment != alignment { + t.Fatalf("decoded NEON VLD1/VST1 %#08x as %+v, ok=%v", word, got, ok) + } + countForms++ + } + } + } + } + } + } + } + if countForms != 681984 { + t.Fatalf("covered %d NEON VLD1/VST1 encodings, want 681984", countForms) + } +} + +func TestARMRawNEONVLD1VST1RejectsReservedAndUnsafeForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawNEONStructureOne(true, 0, 15, 31, 1, 32, 0) &^ (uint32(15) << 8), + encodeARMRawNEONStructureOne(true, 0, 15, 0, 1, 32, 0) | 2<<4, + encodeARMRawNEONStructureOne(true, 0, 15, 31, 4, 32, 0), + } { + if _, ok := decodeARMRawNEONStructureOne(word); ok { + t.Fatalf("NEON VLD1/VST1 decoder accepted reserved encoding %#08x", word) + } + } + + word := encodeARMRawNEONStructureOne(true, 15, 13, 0, 4, 32, 0) + file, err := Parse(ArchARM, fmt.Sprintf("TEXT badStructure(SB), $0-0\n\tWORD $%#08x\n\tRET\n", word)) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"badStructure": {Name: "badStructure", Ret: Void}}}); err == nil { + t.Fatal("Translate accepted PC as NEON VLD1/VST1 base") + } +} + +func TestTranslateARMRawNEONVLD1VST1AddressingModes(t *testing.T) { + source := "TEXT rawStructureModes(SB), $0-0\n" + for _, word := range []uint32{ + encodeARMRawNEONStructureOne(true, 0, 15, 0, 1, 8, 8), + encodeARMRawNEONStructureOne(true, 1, 13, 1, 2, 16, 16), + encodeARMRawNEONStructureOne(false, 2, 4, 3, 3, 32, 8), + encodeARMRawNEONStructureOne(false, 3, 13, 6, 4, 64, 32), + } { + source += fmt.Sprintf("\tWORD $%#08x\n", word) + } + source += "\tRET\n" + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawStructureModes": {Name: "rawStructureModes", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"align 8", "align 16", "align 32", "add i32", `"target-features"="+neon"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON VLD1/VST1 addressing IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-structure-modes.ll", "arm-raw-neon-structure-modes.o", ir) +} diff --git a/arm_lower_word_neon_widening_subtract.go b/arm_lower_word_neon_widening_subtract.go new file mode 100644 index 00000000..0f3f547a --- /dev/null +++ b/arm_lower_word_neon_widening_subtract.go @@ -0,0 +1,75 @@ +package plan9asm + +import "fmt" + +type armRawNEONWideningSubtract struct { + unsigned bool + elementBits int + destination int + lhs int + rhs int +} + +// decodeARMRawNEONWideningSubtract covers the complete A32 VSUBL signed and +// unsigned family: 8-, 16-, and 32-bit D-register lanes widened into a Q +// destination before subtraction. +func decodeARMRawNEONWideningSubtract(word uint32) (armRawNEONWideningSubtract, bool) { + if word&0xfe800f50 != 0xf2800200 { + return armRawNEONWideningSubtract{}, false + } + size := int(word>>20) & 3 + if size == 3 { + return armRawNEONWideningSubtract{}, false + } + destination := int(word>>12)&15 | int(word>>22&1)*16 + // A Q register is encoded as its even-numbered first D register. + if destination&1 != 0 { + return armRawNEONWideningSubtract{}, false + } + return armRawNEONWideningSubtract{ + unsigned: word>>24&1 != 0, + elementBits: 8 << size, + destination: destination, + lhs: int(word>>16)&15 | int(word>>7&1)*16, + rhs: int(word)&15 | int(word>>5&1)*16, + }, true +} + +func (c *armCtx) lowerRawNEONWideningSubtract(form armRawNEONWideningSubtract) error { + lhsBits, err := c.loadFReg(armRawVFPBackingReg(form.lhs, 64)) + if err != nil { + return err + } + rhsBits, err := c.loadFReg(armRawVFPBackingReg(form.rhs, 64)) + if err != nil { + return err + } + lanes := 64 / form.elementBits + wideBits := form.elementBits * 2 + lhsVector := c.newTmp() + rhsVector := c.newTmp() + lhsWide := c.newTmp() + rhsWide := c.newTmp() + result := c.newTmp() + resultBits := c.newTmp() + extend := "sext" + if form.unsigned { + extend = "zext" + } + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to <%d x i%d>\n", lhsVector, lhsBits, lanes, form.elementBits) + fmt.Fprintf(c.b, " %%%s = bitcast i64 %s to <%d x i%d>\n", rhsVector, rhsBits, lanes, form.elementBits) + fmt.Fprintf(c.b, " %%%s = %s <%d x i%d> %%%s to <%d x i%d>\n", lhsWide, extend, lanes, form.elementBits, lhsVector, lanes, wideBits) + fmt.Fprintf(c.b, " %%%s = %s <%d x i%d> %%%s to <%d x i%d>\n", rhsWide, extend, lanes, form.elementBits, rhsVector, lanes, wideBits) + fmt.Fprintf(c.b, " %%%s = sub <%d x i%d> %%%s, %%%s\n", result, lanes, wideBits, lhsWide, rhsWide) + fmt.Fprintf(c.b, " %%%s = bitcast <%d x i%d> %%%s to i128\n", resultBits, lanes, wideBits, result) + low := c.newTmp() + highWide := c.newTmp() + high := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", low, resultBits) + fmt.Fprintf(c.b, " %%%s = lshr i128 %%%s, 64\n", highWide, resultBits) + fmt.Fprintf(c.b, " %%%s = trunc i128 %%%s to i64\n", high, highWide) + if err := c.storeFReg(armRawVFPBackingReg(form.destination, 64), "%"+low); err != nil { + return err + } + return c.storeFReg(armRawVFPBackingReg(form.destination+1, 64), "%"+high) +} diff --git a/arm_lower_word_neon_widening_subtract_test.go b/arm_lower_word_neon_widening_subtract_test.go new file mode 100644 index 00000000..cf1fcef4 --- /dev/null +++ b/arm_lower_word_neon_widening_subtract_test.go @@ -0,0 +1,99 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func encodeARMRawNEONWideningSubtract(unsigned bool, elementBits, destination, lhs, rhs int) uint32 { + word := uint32(0xf2800200 | (destination&15)<<12 | (lhs&15)<<16 | rhs&15) + if unsigned { + word |= 1 << 24 + } + word |= uint32(destination/16) << 22 + word |= uint32(map[int]int{8: 0, 16: 1, 32: 2}[elementBits]) << 20 + word |= uint32(lhs/16) << 7 + word |= uint32(rhs/16) << 5 + return word +} + +func TestTranslateARMRawNEONVSUBLGoDSPRegression(t *testing.T) { + const source = `TEXT rawWideningSubtract(SB), $0-0 + WORD $0xf3cc4280 // vsubl.u8 q10, d28, d0 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawWideningSubtract": {Name: "rawWideningSubtract", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"zext <8 x i8>", "sub <8 x i16>", `"target-features"="+neon"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw NEON VSUBL IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-neon-vsubl.ll", "arm-raw-neon-vsubl.o", ir) +} + +func TestARMRawNEONVSUBLDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for _, unsigned := range []bool{false, true} { + for _, elementBits := range []int{8, 16, 32} { + for destination := 0; destination < 32; destination += 2 { + for lhs := 0; lhs < 32; lhs++ { + for rhs := 0; rhs < 32; rhs++ { + word := encodeARMRawNEONWideningSubtract(unsigned, elementBits, destination, lhs, rhs) + got, ok := decodeARMRawNEONWideningSubtract(word) + if !ok || got.unsigned != unsigned || got.elementBits != elementBits || got.destination != destination || got.lhs != lhs || got.rhs != rhs { + t.Fatalf("decoded NEON VSUBL %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + } + if count != 98304 { + t.Fatalf("covered %d NEON VSUBL encodings, want 98304", count) + } +} + +func TestARMRawNEONVSUBLRejectsReservedForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawNEONWideningSubtract(false, 8, 0, 0, 0) | 3<<20, + encodeARMRawNEONWideningSubtract(false, 8, 0, 0, 0) | 1<<12, + encodeARMRawNEONWideningSubtract(false, 8, 0, 0, 0) | 1<<6, + } { + if _, ok := decodeARMRawNEONWideningSubtract(word); ok { + t.Fatalf("NEON VSUBL decoder accepted reserved encoding %#08x", word) + } + } + if _, ok := decodeARMRawNEONWideningSubtract(encodeARMRawNEONWideningSubtract(true, 32, 30, 31, 31)); !ok { + t.Fatal("NEON VSUBL decoder rejected last valid registers") + } + + const signedSource = `TEXT rawSignedWideningSubtract(SB), $0-0 + WORD $0xf28c4280 // vsubl.s8 q2, d28, d0 + RET +` + file, err := Parse(ArchARM, signedSource) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawSignedWideningSubtract": {Name: "rawSignedWideningSubtract", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "sext <8 x i8>") { + t.Fatalf("signed NEON VSUBL omitted sign extension:\n%s", ir) + } +} diff --git a/arm_lower_word_vfp_immediate.go b/arm_lower_word_vfp_immediate.go new file mode 100644 index 00000000..348f882e --- /dev/null +++ b/arm_lower_word_vfp_immediate.go @@ -0,0 +1,94 @@ +package plan9asm + +import ( + "fmt" + "strconv" +) + +type armRawVFPImmediate struct { + condition string + bits int + destination int + immediate uint8 +} + +// decodeARMRawVFPImmediate covers the complete A32 VMOV (immediate) family: +// every ordinary ARM condition, both F32/F64 widths, all S0..S31/D0..D31 +// destinations, and all 256 encodable floating constants. +func decodeARMRawVFPImmediate(word uint32) (armRawVFPImmediate, bool) { + const mask = uint32(0x0fb00ef0) + const base = uint32(0x0eb00a00) + if word&mask != base { + return armRawVFPImmediate{}, false + } + condition, ok := armRawCondition(word >> 28) + if !ok { + return armRawVFPImmediate{}, false + } + width := 32 + destination := int(word>>12) & 15 + if word>>8&1 != 0 { + width = 64 + destination += int(word>>22&1) * 16 + } else { + destination = destination*2 + int(word>>22&1) + } + immediate := uint8(word>>16&15)<<4 | uint8(word&15) + return armRawVFPImmediate{ + condition: condition, + bits: width, + destination: destination, + immediate: immediate, + }, true +} + +// expandARMVFPImmediate implements the VFPExpandImm operation from the ARM +// architecture. Returning the IEEE bits avoids rounding the encoded constant +// through a host floating-point parser. +func expandARMVFPImmediate(immediate uint8, width int) uint64 { + exponentBits, fractionBits := 8, 23 + if width == 64 { + exponentBits, fractionBits = 11, 52 + } + repeated := uint64(immediate>>6) & 1 + exponent := (repeated ^ 1) << (exponentBits - 1) + if repeated != 0 { + exponent |= ((uint64(1) << (exponentBits - 3)) - 1) << 2 + } + exponent |= uint64(immediate>>4) & 3 + fraction := uint64(immediate&15) << (fractionBits - 4) + sign := uint64(immediate>>7) << (width - 1) + return sign | exponent<>4) << 16 + word |= uint32(immediate & 15) + if bits == 32 { + word |= uint32(destination&1) << 22 + word |= uint32(destination>>1) << 12 + } else { + word |= 1 << 8 + word |= uint32(destination>>4) << 22 + word |= uint32(destination&15) << 12 + } + return word +} + +func TestARMRawVFPImmediateDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for condition := 0; condition < 15; condition++ { + for _, width := range []int{32, 64} { + for destination := 0; destination < 32; destination++ { + for immediate := 0; immediate < 256; immediate++ { + word := encodeARMRawVFPImmediate(condition, width, destination, immediate) + got, ok := decodeARMRawVFPImmediate(word) + if !ok { + t.Fatalf("decodeARMRawVFPImmediate(%#08x) failed", word) + } + if got.bits != width || got.destination != destination || got.immediate != uint8(immediate) { + t.Fatalf("decodeARMRawVFPImmediate(%#08x) = %+v", word, got) + } + count++ + } + } + } + } + if count != 15*2*32*256 { + t.Fatalf("covered %d VFP immediate encodings", count) + } +} + +func TestARMRawVFPImmediateExpansion(t *testing.T) { + for _, test := range []struct { + immediate uint8 + bits int + want uint64 + }{ + {immediate: 0x70, bits: 32, want: 0x3f800000}, + {immediate: 0x70, bits: 64, want: 0x3ff0000000000000}, + {immediate: 0xf0, bits: 32, want: 0xbf800000}, + {immediate: 0xf0, bits: 64, want: 0xbff0000000000000}, + {immediate: 0x00, bits: 32, want: 0x40000000}, + {immediate: 0x0f, bits: 64, want: 0x400f000000000000}, + } { + if got := expandARMVFPImmediate(test.immediate, test.bits); got != test.want { + t.Fatalf("expandARMVFPImmediate(%#x, %d) = %#x, want %#x", test.immediate, test.bits, got, test.want) + } + } +} + +func TestTranslateARMRawVFPImmediateFamilyThroughLLVM22(t *testing.T) { + words := []uint32{ + encodeARMRawVFPImmediate(14, 64, 0, 0x70), + encodeARMRawVFPImmediate(14, 32, 30, 0x70), + encodeARMRawVFPImmediate(14, 32, 31, 0xf0), + encodeARMRawVFPImmediate(14, 64, 16, 0x00), + } + var source strings.Builder + source.WriteString("TEXT rawVFPImmediate(SB), $0-0\n") + for _, word := range words { + fmt.Fprintf(&source, "\tWORD $%#08x\n", word) + } + source.WriteString("\tRET\n") + file, err := Parse(ArchARM, source.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", + Sigs: map[string]FuncSig{"rawVFPImmediate": {Name: "rawVFPImmediate", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"1065353216", "-4647714815446351872", "4611686018427387904", `"target-features"="+vfp2"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw VFP immediate family omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-vfp-immediate.ll", "arm-vfp-immediate.o", ir) +} + +func TestARMRawVFPImmediateRejectsReservedAndDifferentForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawVFPImmediate(15, 64, 0, 0x70), + encodeARMRawVFPImmediate(14, 64, 0, 0x70) | 1<<6, + 0xeeb00b40, // VMOV.F64 D0,D0. + } { + if got, ok := decodeARMRawVFPImmediate(word); ok { + t.Fatalf("decoded reserved/different form %#08x as %+v", word, got) + } + } +} diff --git a/arm_lower_word_vfp_move.go b/arm_lower_word_vfp_move.go new file mode 100644 index 00000000..901a1f3b --- /dev/null +++ b/arm_lower_word_vfp_move.go @@ -0,0 +1,64 @@ +package plan9asm + +type armRawVFPMove struct { + condition string + bits int + destination int + source int +} + +// decodeARMRawVFPMove covers the complete A32 scalar VMOV (register) family: +// every condition and all S0..S31 and D0..D31 source/destination fields. Raw +// single-register moves need a dedicated path because x/arch's Go syntax uses +// F for even S registers and S for odd ones, while source-level Go F +// registers represent a different register view. +func decodeARMRawVFPMove(word uint32) (armRawVFPMove, bool) { + const mask = uint32(0x0fbf0ed0) + const base = uint32(0x0eb00a40) + if word&mask != base { + return armRawVFPMove{}, false + } + condition, ok := armRawCondition(word >> 28) + if !ok { + return armRawVFPMove{}, false + } + bits := 32 + destination := int(word>>12) & 15 + source := int(word) & 15 + if word>>8&1 != 0 { + bits = 64 + destination += int(word>>22&1) * 16 + source += int(word>>5&1) * 16 + } else { + destination = destination*2 + int(word>>22&1) + source = source*2 + int(word>>5&1) + } + return armRawVFPMove{ + condition: condition, + bits: bits, + destination: destination, + source: source, + }, true +} + +func (c *armCtx) lowerRawVFPMove(form armRawVFPMove) error { + if form.condition != "" && form.condition != "AL" { + condition := form.condition + form.condition = "AL" + return c.emitConditionalEffect(condition, func() error { + return c.lowerRawVFPMove(form) + }) + } + if form.bits == 32 { + value, err := c.loadARMRawSingleBits(form.source) + if err != nil { + return err + } + return c.storeARMRawSingleBits(form.destination, value, "") + } + value, err := c.loadFReg(armRawVFPBackingReg(form.source, 64)) + if err != nil { + return err + } + return c.storeFReg(armRawVFPBackingReg(form.destination, 64), value) +} diff --git a/arm_lower_word_vfp_move_test.go b/arm_lower_word_vfp_move_test.go new file mode 100644 index 00000000..8ab8168f --- /dev/null +++ b/arm_lower_word_vfp_move_test.go @@ -0,0 +1,117 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARMRawVFPConditionalMoveGoDSPRegression(t *testing.T) { + const source = `TEXT rawConditionalMove(SB), $0-0 + CMP R0, R1 + WORD $0xceb04a60 // vmovgt.f32 s8, s1 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawConditionalMove": {Name: "rawConditionalMove", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"lshr i64", "trunc i64", "cond_effect_taken", `"target-features"="+vfp2"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw conditional VFP move IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-vfp-move.ll", "arm-raw-vfp-move.o", ir) +} + +func encodeARMRawVFPMove(condition, bits, destination, source int) uint32 { + word := uint32(condition)<<28 | 0x0eb00a40 + if bits == 32 { + word |= uint32(destination/2) << 12 + word |= uint32(destination&1) << 22 + word |= uint32(source / 2) + word |= uint32(source&1) << 5 + } else { + word |= 1 << 8 + word |= uint32(destination&15) << 12 + word |= uint32(destination/16) << 22 + word |= uint32(source & 15) + word |= uint32(source/16) << 5 + } + return word +} + +func TestARMRawVFPMoveDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for condition := 0; condition < 15; condition++ { + for _, bits := range []int{32, 64} { + for destination := 0; destination < 32; destination++ { + for source := 0; source < 32; source++ { + word := encodeARMRawVFPMove(condition, bits, destination, source) + got, ok := decodeARMRawVFPMove(word) + if !ok || got.condition != armConditionName(condition) || got.bits != bits || got.destination != destination || got.source != source { + t.Fatalf("decoded VFP VMOV %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + if count != 30720 { + t.Fatalf("covered %d scalar VFP VMOV encodings, want 30720", count) + } +} + +func TestTranslateARMRawVFPMoveCompleteFormats(t *testing.T) { + source := "TEXT rawMoveAll(SB), $0-0\n\tCMP R0, R1\n" + for condition := 0; condition < 15; condition++ { + for _, test := range []struct { + bits int + destination int + source int + }{{32, 0, 31}, {32, 31, 0}, {64, 0, 31}, {64, 31, 0}} { + source += fmt.Sprintf("\tWORD $%#08x\n", encodeARMRawVFPMove(condition, test.bits, test.destination, test.source)) + } + } + source += "\tRET\n" + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawMoveAll": {Name: "rawMoveAll", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"lshr i64", "shl i64", "cond_effect_taken", `"target-features"="+vfp2"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw VFP VMOV complete formats omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-vfp-move-all.ll", "arm-raw-vfp-move-all.o", ir) +} + +func TestARMRawVFPMoveRejectsReservedConditionAndDifferentFamilies(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawVFPMove(15, 32, 0, 0), + encodeARMRawVFPMove(14, 32, 0, 0) | 1<<16, + encodeARMRawVFPMove(14, 32, 0, 0) | 1<<4, + } { + if _, ok := decodeARMRawVFPMove(word); ok { + t.Fatalf("scalar VFP VMOV decoder accepted reserved encoding %#08x", word) + } + } +} diff --git a/arm_lower_word_vfp_multiple.go b/arm_lower_word_vfp_multiple.go new file mode 100644 index 00000000..d694a869 --- /dev/null +++ b/arm_lower_word_vfp_multiple.go @@ -0,0 +1,133 @@ +package plan9asm + +import "fmt" + +type armRawVFPMultiple struct { + load bool + decrement bool + writeback bool + condition string + base int + bits int + first int + count int +} + +// decodeARMRawVFPMultiple covers the complete A32 VLDM/VSTM IA and DB +// encoding family for contiguous S0..S31 and D0..D31 register lists. DB is +// architecturally a writeback form; encodings without W are rejected. +func decodeARMRawVFPMultiple(word uint32) (armRawVFPMultiple, bool) { + if word&0x0e000e00 != 0x0c000a00 { + return armRawVFPMultiple{}, false + } + condition, ok := armRawCondition(word >> 28) + if !ok { + return armRawVFPMultiple{}, false + } + p := word>>24&1 != 0 + u := word>>23&1 != 0 + if p == u || p && word>>21&1 == 0 { + return armRawVFPMultiple{}, false + } + bits := 32 + if word>>8&1 != 0 { + bits = 64 + } + first := int(word>>12) & 15 + if bits == 32 { + first = first*2 + int(word>>22&1) + } else { + first += int(word>>22&1) * 16 + } + encodedCount := int(word & 0xff) + if encodedCount == 0 || bits == 64 && encodedCount&1 != 0 { + return armRawVFPMultiple{}, false + } + count := encodedCount + if bits == 64 { + count /= 2 + } + if first+count > 32 { + return armRawVFPMultiple{}, false + } + return armRawVFPMultiple{ + load: word>>20&1 != 0, + decrement: p, + writeback: word>>21&1 != 0, + condition: condition, + base: int(word>>16) & 15, + bits: bits, + first: first, + count: count, + }, true +} + +func (c *armCtx) lowerRawVFPMultiple(form armRawVFPMultiple) error { + if form.base == 15 { + return fmt.Errorf("arm VFP multiple transfer cannot safely use PC as its base") + } + if form.condition != "" && form.condition != "AL" { + condition := form.condition + form.condition = "AL" + return c.emitConditionalEffect(condition, func() error { + return c.lowerRawVFPMultiple(form) + }) + } + + baseReg := Reg(fmt.Sprintf("R%d", form.base)) + base, err := c.loadReg(baseReg) + if err != nil { + return err + } + bytes := form.count * (form.bits / 8) + address := base + if form.decrement { + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = sub i32 %s, %d\n", adjusted, base, bytes) + address = "%" + adjusted + } + for i := 0; i < form.count; i++ { + itemAddress := address + if offset := i * (form.bits / 8); offset != 0 { + adjusted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = add i32 %s, %d\n", adjusted, address, offset) + itemAddress = "%" + adjusted + } + pointer := c.newTmp() + fmt.Fprintf(c.b, " %%%s = inttoptr i32 %s to ptr\n", pointer, itemAddress) + register := form.first + i + if form.load { + value := c.newTmp() + fmt.Fprintf(c.b, " %%%s = load i%d, ptr %%%s, align 1\n", value, form.bits, pointer) + if form.bits == 32 { + if err := c.storeARMRawSingleBits(register, "%"+value, ""); err != nil { + return err + } + } else if err := c.storeFReg(armRawVFPBackingReg(register, 64), "%"+value); err != nil { + return err + } + continue + } + + var value string + if form.bits == 32 { + value, err = c.loadARMRawSingleBits(register) + } else { + value, err = c.loadFReg(armRawVFPBackingReg(register, 64)) + } + if err != nil { + return err + } + fmt.Fprintf(c.b, " store i%d %s, ptr %%%s, align 1\n", form.bits, value, pointer) + } + if form.writeback { + updated := c.newTmp() + operation := "add" + if form.decrement { + operation = "sub" + } + fmt.Fprintf(c.b, " %%%s = %s i32 %s, %d\n", updated, operation, base, bytes) + return c.storeReg(baseReg, "%"+updated) + } + return nil +} diff --git a/arm_lower_word_vfp_multiple_test.go b/arm_lower_word_vfp_multiple_test.go new file mode 100644 index 00000000..3be2854b --- /dev/null +++ b/arm_lower_word_vfp_multiple_test.go @@ -0,0 +1,117 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARMRawVFPMultiple(load, decrement, writeback bool, condition, base, bits, first, count int) uint32 { + word := uint32(condition)<<28 | 0x0c000a00 | uint32(base)<<16 + if decrement { + word |= 1 << 24 + } else { + word |= 1 << 23 + } + if writeback { + word |= 1 << 21 + } + if load { + word |= 1 << 20 + } + if bits == 32 { + word |= uint32(first/2) << 12 + word |= uint32(first&1) << 22 + word |= uint32(count) + } else { + word |= 1 << 8 + word |= uint32(first&15) << 12 + word |= uint32(first/16) << 22 + word |= uint32(count * 2) + } + return word +} + +func TestTranslateARMRawVFPMultipleCompleteModes(t *testing.T) { + const source = `TEXT rawMultiple(SB), $0-0 + WORD $0xeca30a04 // vstmia r3!, {s0-s3} + WORD $0xecb11a04 // vldmia r1!, {s2-s5} + WORD $0xecb02b10 // vldmia r0!, {d2-d9} + WORD $0xeca12b10 // vstmia r1!, {d2-d9} + WORD $0xed324a04 // vldmdb r2!, {s8-s11} + WORD $0xed630b20 // vstmdb r3!, {d16-d31} + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawMultiple": {Name: "rawMultiple", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"load i32, ptr", "load i64, ptr", "store i32", "store i64", "sub i32", `"target-features"="+vfp2"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw VFP multiple IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-vfp-multiple.ll", "arm-raw-vfp-multiple.o", ir) +} + +func TestARMRawVFPMultipleDecoderCoversEveryValidField(t *testing.T) { + count := 0 + for condition := 0; condition < 15; condition++ { + for _, load := range []bool{false, true} { + for _, decrement := range []bool{false, true} { + for _, writeback := range []bool{false, true} { + if decrement && !writeback { + continue + } + for base := 0; base < 16; base++ { + for _, bits := range []int{32, 64} { + for first := 0; first < 32; first++ { + for registers := 1; registers <= 32-first; registers++ { + word := encodeARMRawVFPMultiple(load, decrement, writeback, condition, base, bits, first, registers) + got, ok := decodeARMRawVFPMultiple(word) + if !ok || got.load != load || got.decrement != decrement || got.writeback != writeback || got.condition != armConditionName(condition) || got.base != base || got.bits != bits || got.first != first || got.count != registers { + t.Fatalf("decoded VFP multiple %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + } + } + } + } + if count == 0 { + t.Fatal("covered no VFP multiple encodings") + } +} + +func TestARMRawVFPMultipleRejectsReservedAndUnsafeForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawVFPMultiple(true, false, true, 15, 0, 32, 0, 1), + encodeARMRawVFPMultiple(true, true, false, 14, 0, 32, 0, 1), + encodeARMRawVFPMultiple(true, false, true, 14, 0, 32, 31, 2), + } { + if _, ok := decodeARMRawVFPMultiple(word); ok { + t.Fatalf("VFP multiple decoder accepted reserved encoding %#08x", word) + } + } + word := encodeARMRawVFPMultiple(true, false, true, 14, 15, 32, 0, 1) + file, err := Parse(ArchARM, fmt.Sprintf("TEXT badMultiple(SB), $0-0\n\tWORD $%#08x\n\tRET\n", word)) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"badMultiple": {Name: "badMultiple", Ret: Void}}}); err == nil { + t.Fatal("Translate accepted PC as VFP multiple base") + } +} diff --git a/arm_lower_word_vfp_scalar_arithmetic.go b/arm_lower_word_vfp_scalar_arithmetic.go new file mode 100644 index 00000000..2fd9e270 --- /dev/null +++ b/arm_lower_word_vfp_scalar_arithmetic.go @@ -0,0 +1,142 @@ +package plan9asm + +import "fmt" + +type armRawVFPScalarArithmetic struct { + kind string + condition string + bits int + destination int + lhs int + rhs int +} + +// decodeARMRawVFPScalarArithmetic covers the complete classic A32 scalar VFP +// arithmetic family: add, subtract, multiply, negative multiply, divide, and +// the four accumulating multiply forms, for F32/F64 and every executable +// condition and register field. +func decodeARMRawVFPScalarArithmetic(word uint32) (armRawVFPScalarArithmetic, bool) { + const variable = uint32(0xf0000000 | 0x00400000 | 0x000f0000 | 0x0000f000 | 0x00000100 | 0x00000080 | 0x00000020 | 0x0000000f) + var kind string + switch word &^ variable { + case 0x0e300a00: + kind = "add" + case 0x0e300a40: + kind = "sub" + case 0x0e200a00: + kind = "mul" + case 0x0e200a40: + kind = "nmul" + case 0x0e800a00: + kind = "div" + case 0x0e000a00: + kind = "madd" + case 0x0e000a40: + kind = "msub" + case 0x0e100a40: + kind = "nmadd" + case 0x0e100a00: + kind = "nmsub" + default: + return armRawVFPScalarArithmetic{}, false + } + condition, ok := armRawCondition(word >> 28) + if !ok { + return armRawVFPScalarArithmetic{}, false + } + bits := 32 + destination := int(word>>12) & 15 + lhs := int(word>>16) & 15 + rhs := int(word) & 15 + if word>>8&1 != 0 { + bits = 64 + destination += int(word>>22&1) * 16 + lhs += int(word>>7&1) * 16 + rhs += int(word>>5&1) * 16 + } else { + destination = destination*2 + int(word>>22&1) + lhs = lhs*2 + int(word>>7&1) + rhs = rhs*2 + int(word>>5&1) + } + return armRawVFPScalarArithmetic{ + kind: kind, + condition: condition, + bits: bits, + destination: destination, + lhs: lhs, + rhs: rhs, + }, true +} + +func (c *armCtx) storeARMRawVFPRegValue(number, bits int, value string) error { + encoded := c.newTmp() + if bits == 32 { + fmt.Fprintf(c.b, " %%%s = bitcast float %s to i32\n", encoded, value) + return c.storeARMRawSingleBits(number, "%"+encoded, "") + } + fmt.Fprintf(c.b, " %%%s = bitcast double %s to i64\n", encoded, value) + return c.storeFReg(armRawVFPBackingReg(number, 64), "%"+encoded) +} + +func (c *armCtx) lowerRawVFPScalarArithmetic(form armRawVFPScalarArithmetic) error { + if form.condition != "" && form.condition != "AL" { + condition := form.condition + form.condition = "AL" + return c.emitConditionalEffect(condition, func() error { + return c.lowerRawVFPScalarArithmetic(form) + }) + } + lhs, err := c.loadARMRawVFPRegValue(form.lhs, form.bits) + if err != nil { + return err + } + rhs, err := c.loadARMRawVFPRegValue(form.rhs, form.bits) + if err != nil { + return err + } + floatType := "float" + if form.bits == 64 { + floatType = "double" + } + emitBinary := func(operation, left, right string) string { + name := c.newTmp() + fmt.Fprintf(c.b, " %%%s = %s %s %s, %s\n", name, operation, floatType, left, right) + return "%" + name + } + emitNeg := func(value string) string { + name := c.newTmp() + fmt.Fprintf(c.b, " %%%s = fneg %s %s\n", name, floatType, value) + return "%" + name + } + + var result string + switch form.kind { + case "add": + result = emitBinary("fadd", lhs, rhs) + case "sub": + result = emitBinary("fsub", lhs, rhs) + case "mul": + result = emitBinary("fmul", lhs, rhs) + case "nmul": + result = emitNeg(emitBinary("fmul", lhs, rhs)) + case "div": + result = emitBinary("fdiv", lhs, rhs) + default: + accumulator, loadErr := c.loadARMRawVFPRegValue(form.destination, form.bits) + if loadErr != nil { + return loadErr + } + product := emitBinary("fmul", lhs, rhs) + switch form.kind { + case "madd": + result = emitBinary("fadd", accumulator, product) + case "msub": + result = emitBinary("fsub", accumulator, product) + case "nmadd": + result = emitNeg(emitBinary("fadd", accumulator, product)) + case "nmsub": + result = emitBinary("fsub", product, accumulator) + } + } + return c.storeARMRawVFPRegValue(form.destination, form.bits, result) +} diff --git a/arm_lower_word_vfp_scalar_arithmetic_test.go b/arm_lower_word_vfp_scalar_arithmetic_test.go new file mode 100644 index 00000000..23fe1d3a --- /dev/null +++ b/arm_lower_word_vfp_scalar_arithmetic_test.go @@ -0,0 +1,134 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +var armRawVFPScalarArithmeticTestBases = map[string]uint32{ + "add": 0x0e300a00, + "sub": 0x0e300a40, + "mul": 0x0e200a00, + "nmul": 0x0e200a40, + "div": 0x0e800a00, + "madd": 0x0e000a00, + "msub": 0x0e000a40, + "nmadd": 0x0e100a40, + "nmsub": 0x0e100a00, +} + +func encodeARMRawVFPScalarArithmetic(kind string, condition, bits, destination, lhs, rhs int) uint32 { + word := uint32(condition)<<28 | armRawVFPScalarArithmeticTestBases[kind] + if bits == 64 { + word |= 1 << 8 + word |= uint32(destination&15) << 12 + word |= uint32(destination/16) << 22 + word |= uint32(lhs&15) << 16 + word |= uint32(lhs/16) << 7 + word |= uint32(rhs & 15) + word |= uint32(rhs/16) << 5 + return word + } + word |= uint32(destination/2) << 12 + word |= uint32(destination&1) << 22 + word |= uint32(lhs/2) << 16 + word |= uint32(lhs&1) << 7 + word |= uint32(rhs / 2) + word |= uint32(rhs&1) << 5 + return word +} + +func TestTranslateARMRawVFPScalarArithmeticGoDSPRegression(t *testing.T) { + const source = `TEXT rawScalarArithmetic(SB), $0-0 + WORD $0xee611a80 // vmul.f32 s3, s3, s0 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawScalarArithmetic": {Name: "rawScalarArithmetic", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"fmul float", "lshr i64", "and i64", `"target-features"="+vfp2"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw VFP scalar arithmetic omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-vfp-scalar-arithmetic.ll", "arm-raw-vfp-scalar-arithmetic.o", ir) +} + +func TestARMRawVFPScalarArithmeticDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for kind := range armRawVFPScalarArithmeticTestBases { + for condition := 0; condition < 15; condition++ { + for _, bits := range []int{32, 64} { + for destination := 0; destination < 32; destination++ { + for lhs := 0; lhs < 32; lhs++ { + for rhs := 0; rhs < 32; rhs++ { + word := encodeARMRawVFPScalarArithmetic(kind, condition, bits, destination, lhs, rhs) + got, ok := decodeARMRawVFPScalarArithmetic(word) + if !ok || got.kind != kind || got.condition != armConditionName(condition) || got.bits != bits || got.destination != destination || got.lhs != lhs || got.rhs != rhs { + t.Fatalf("decoded scalar VFP arithmetic %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + } + } + if count != 8847360 { + t.Fatalf("covered %d scalar VFP arithmetic encodings, want 8847360", count) + } +} + +func TestTranslateARMRawVFPScalarArithmeticAllOperations(t *testing.T) { + source := "TEXT rawScalarArithmeticAll(SB), $0-0\n\tCMP R0, R1\n" + for kind := range armRawVFPScalarArithmeticTestBases { + for _, bits := range []int{32, 64} { + for _, condition := range []int{1, 14} { + word := encodeARMRawVFPScalarArithmetic(kind, condition, bits, 3, 5, 7) + source += fmt.Sprintf("\tWORD $%#08x\n", word) + } + } + } + source += "\tRET\n" + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawScalarArithmeticAll": {Name: "rawScalarArithmeticAll", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"fadd float", "fsub double", "fmul float", "fdiv double", "fneg float", "cond_effect_taken", `"target-features"="+vfp2"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw VFP scalar arithmetic family omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-vfp-scalar-arithmetic-all.ll", "arm-raw-vfp-scalar-arithmetic-all.o", ir) +} + +func TestARMRawVFPScalarArithmeticRejectsReservedForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawVFPScalarArithmetic("mul", 15, 32, 0, 0, 0), + encodeARMRawVFPScalarArithmetic("mul", 14, 32, 0, 0, 0) ^ 1<<9, + } { + if _, ok := decodeARMRawVFPScalarArithmetic(word); ok { + t.Fatalf("scalar VFP arithmetic decoder accepted reserved encoding %#08x", word) + } + } +} diff --git a/arm_lower_word_vfp_status.go b/arm_lower_word_vfp_status.go new file mode 100644 index 00000000..776808f8 --- /dev/null +++ b/arm_lower_word_vfp_status.go @@ -0,0 +1,68 @@ +package plan9asm + +import "fmt" + +type armRawVFPStatusTransfer struct { + toCore bool + toFlags bool + condition string + core int +} + +// decodeARMRawVFPStatusTransfer covers VMRS Rt,FPSCR, VMSR FPSCR,Rt, and the +// VMRS APSR_nzcv,FPSCR form for every executable A32 condition. PC is reserved +// as a VMSR source and denotes APSR_nzcv only in the VMRS direction. +func decodeARMRawVFPStatusTransfer(word uint32) (armRawVFPStatusTransfer, bool) { + const mask = uint32(0x0fff0fff) + key := word & mask + toCore := false + switch key { + case 0x0ee10a10: + case 0x0ef10a10: + toCore = true + default: + return armRawVFPStatusTransfer{}, false + } + condition, ok := armRawCondition(word >> 28) + if !ok { + return armRawVFPStatusTransfer{}, false + } + core := int(word>>12) & 15 + if !toCore && core == 15 { + return armRawVFPStatusTransfer{}, false + } + return armRawVFPStatusTransfer{ + toCore: toCore, + toFlags: toCore && core == 15, + condition: condition, + core: core, + }, true +} + +func (c *armCtx) lowerRawVFPStatusTransfer(form armRawVFPStatusTransfer) error { + if form.condition != "" && form.condition != "AL" { + condition := form.condition + form.condition = "AL" + return c.emitConditionalEffect(condition, func() error { + return c.lowerRawVFPStatusTransfer(form) + }) + } + if form.toFlags { + if !c.flagsWritten { + return fmt.Errorf("%w: raw VMRS has no preceding modeled VFP flag write", ErrProbeNeedsContext) + } + return nil + } + core := Reg(fmt.Sprintf("R%d", form.core)) + if form.toCore { + status := c.newTmp() + fmt.Fprintf(c.b, " %%%s = call i32 asm sideeffect %q, %q()\n", status, "vmrs $0, fpscr", "=r,~{memory}") + return c.storeReg(core, "%"+status) + } + status, err := c.loadReg(core) + if err != nil { + return err + } + fmt.Fprintf(c.b, " call void asm sideeffect %q, %q(i32 %s)\n", "vmsr fpscr, $0", "r,~{memory}", status) + return nil +} diff --git a/arm_lower_word_vfp_status_test.go b/arm_lower_word_vfp_status_test.go new file mode 100644 index 00000000..c9666d90 --- /dev/null +++ b/arm_lower_word_vfp_status_test.go @@ -0,0 +1,89 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARMRawVFPStatusTransfer(toCore bool, condition, core int) uint32 { + word := uint32(condition)<<28 | 0x0ee10a10 | uint32(core)<<12 + if toCore { + word |= 1 << 20 + } + return word +} + +func TestTranslateARMRawVFPStatusGoDSPRegression(t *testing.T) { + const source = `TEXT rawStatus(SB), $0-0 + WORD $0xeef13a10 // vmrs r3, fpscr + WORD $0xeee13a10 // vmsr fpscr, r3 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawStatus": {Name: "rawStatus", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"vmrs $0, fpscr", "vmsr fpscr, $0", `"target-features"="+vfp2"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw VFP status transfer omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-vfp-status.ll", "arm-raw-vfp-status.o", ir) +} + +func TestARMRawVFPStatusDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for condition := 0; condition < 15; condition++ { + for core := 0; core < 15; core++ { + for _, toCore := range []bool{false, true} { + word := encodeARMRawVFPStatusTransfer(toCore, condition, core) + got, ok := decodeARMRawVFPStatusTransfer(word) + if !ok || got.toCore != toCore || got.toFlags || got.condition != armConditionName(condition) || got.core != core { + t.Fatalf("decoded VFP status transfer %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + word := encodeARMRawVFPStatusTransfer(true, condition, 15) + got, ok := decodeARMRawVFPStatusTransfer(word) + if !ok || !got.toCore || !got.toFlags || got.condition != armConditionName(condition) { + t.Fatalf("decoded VFP flag transfer %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + if count != 465 { + t.Fatalf("covered %d VFP status transfers, want 465", count) + } +} + +func TestARMRawVFPStatusRejectsReservedForms(t *testing.T) { + for _, word := range []uint32{ + encodeARMRawVFPStatusTransfer(false, 14, 15), + encodeARMRawVFPStatusTransfer(true, 15, 0), + encodeARMRawVFPStatusTransfer(true, 14, 0) ^ 1<<8, + } { + if got, ok := decodeARMRawVFPStatusTransfer(word); ok { + t.Fatalf("VFP status decoder accepted reserved encoding %#08x as %+v", word, got) + } + } + + word := encodeARMRawVFPStatusTransfer(true, 14, 15) + file, err := Parse(ArchARM, fmt.Sprintf("TEXT missingCompare(SB), $0-0\n\tWORD $%#08x\n\tRET\n", word)) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"missingCompare": {Name: "missingCompare", Ret: Void}}}); err == nil || !strings.Contains(err.Error(), ErrProbeNeedsContext.Error()) { + t.Fatalf("flag transfer without comparison returned %v, want context error", err) + } +} diff --git a/arm_lower_word_vmov_pair.go b/arm_lower_word_vmov_pair.go new file mode 100644 index 00000000..b799507e --- /dev/null +++ b/arm_lower_word_vmov_pair.go @@ -0,0 +1,130 @@ +package plan9asm + +import "fmt" + +type armRawVMOVPair struct { + toFloat bool + condition string + firstCore int + secondCore int + firstSingle int +} + +// decodeARMRawVMOVPair covers both A32 directions between a pair of core +// registers and two adjacent single-precision registers, across every +// executable condition and encoded register field. +func decodeARMRawVMOVPair(word uint32) (armRawVMOVPair, bool) { + const mask = uint32(0x0ff00fd0) + const toFloatBase = uint32(0x0c400a10) + const fromFloatBase = uint32(0x0c500a10) + + toFloat := false + switch word & mask { + case toFloatBase: + toFloat = true + case fromFloatBase: + default: + return armRawVMOVPair{}, false + } + condition, ok := armRawCondition(word >> 28) + if !ok { + return armRawVMOVPair{}, false + } + firstSingle := int(word&0xf)*2 + int(word>>5&1) + if firstSingle >= 31 { + return armRawVMOVPair{}, false + } + return armRawVMOVPair{ + toFloat: toFloat, + condition: condition, + firstCore: int(word>>12) & 15, + secondCore: int(word>>16) & 15, + firstSingle: firstSingle, + }, true +} + +func (c *armCtx) loadARMRawSingleBits(number int) (string, error) { + wide, err := c.loadFReg(armRawVFPBackingReg(number, 32)) + if err != nil { + return "", err + } + if number&1 != 0 { + shifted := c.newTmp() + fmt.Fprintf(c.b, " %%%s = lshr i64 %s, 32\n", shifted, wide) + wide = "%" + shifted + } + narrow := c.newTmp() + fmt.Fprintf(c.b, " %%%s = trunc i64 %s to i32\n", narrow, wide) + return "%" + narrow, nil +} + +func (c *armCtx) storeARMRawSingleBits(number int, value, condition string) error { + reg := armRawVFPBackingReg(number, 32) + old, err := c.loadFReg(reg) + if err != nil { + return err + } + extended := c.newTmp() + fmt.Fprintf(c.b, " %%%s = zext i32 %s to i64\n", extended, value) + newBits := "%" + extended + if number&1 != 0 { + shifted := c.newTmp() + kept := c.newTmp() + merged := c.newTmp() + fmt.Fprintf(c.b, " %%%s = shl i64 %s, 32\n", shifted, newBits) + fmt.Fprintf(c.b, " %%%s = and i64 %s, 4294967295\n", kept, old) + fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %%%s\n", merged, kept, shifted) + newBits = "%" + merged + } else { + kept := c.newTmp() + merged := c.newTmp() + fmt.Fprintf(c.b, " %%%s = and i64 %s, -4294967296\n", kept, old) + fmt.Fprintf(c.b, " %%%s = or i64 %%%s, %s\n", merged, kept, newBits) + newBits = "%" + merged + } + if condition != "" && condition != "AL" { + conditionValue, err := c.condValue(condition) + if err != nil { + return err + } + selected := c.newTmp() + fmt.Fprintf(c.b, " %%%s = select i1 %s, i64 %s, i64 %s\n", selected, conditionValue, newBits, old) + newBits = "%" + selected + } + return c.storeFReg(reg, newBits) +} + +func (c *armCtx) lowerRawVMOVPair(form armRawVMOVPair) error { + if form.firstCore == 15 || form.secondCore == 15 { + return fmt.Errorf("arm VMOV register pair cannot safely use PC") + } + firstCore := Reg(fmt.Sprintf("R%d", form.firstCore)) + secondCore := Reg(fmt.Sprintf("R%d", form.secondCore)) + if form.toFloat { + first, err := c.loadReg(firstCore) + if err != nil { + return err + } + second, err := c.loadReg(secondCore) + if err != nil { + return err + } + if err := c.storeARMRawSingleBits(form.firstSingle, first, form.condition); err != nil { + return err + } + return c.storeARMRawSingleBits(form.firstSingle+1, second, form.condition) + } + + first, err := c.loadARMRawSingleBits(form.firstSingle) + if err != nil { + return err + } + second, err := c.loadARMRawSingleBits(form.firstSingle + 1) + if err != nil { + return err + } + if err := c.selectRegWrite(firstCore, form.condition, first); err != nil { + return err + } + return c.selectRegWrite(secondCore, form.condition, second) +} diff --git a/arm_lower_word_vmov_pair_test.go b/arm_lower_word_vmov_pair_test.go new file mode 100644 index 00000000..97c5dc65 --- /dev/null +++ b/arm_lower_word_vmov_pair_test.go @@ -0,0 +1,86 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func encodeARMRawVMOVPair(toFloat bool, condition, firstCore, secondCore, firstSingle int) uint32 { + word := uint32(condition)<<28 | 0x0c400a10 | uint32(secondCore)<<16 | uint32(firstCore)<<12 | uint32(firstSingle/2) + if !toFloat { + word |= 1 << 20 + } + if firstSingle&1 != 0 { + word |= 1 << 5 + } + return word +} + +func TestTranslateARMRawVMOVPairCompleteDirections(t *testing.T) { + const source = `TEXT rawVMOVPair(SB), $0-0 + WORD $0xec454a1e // vmov s28, s29, r4, r5 + WORD $0xec476a1f // vmov s30, s31, r6, r7 + WORD $0xec540a11 // vmov r0, r4, s2, s3 + WORD $0xec5b8a12 // vmov r8, r11, s4, s5 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawVMOVPair": {Name: "rawVMOVPair", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"zext i32", "trunc i64", `"target-features"="+vfp2"`} { + if !strings.Contains(ir, want) { + t.Fatalf("VMOV pair IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-vmov-pair.ll", "arm-raw-vmov-pair.o", ir) +} + +func TestARMRawVMOVPairDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for _, toFloat := range []bool{false, true} { + for condition := 0; condition < 15; condition++ { + for firstCore := 0; firstCore < 16; firstCore++ { + for secondCore := 0; secondCore < 16; secondCore++ { + for firstSingle := 0; firstSingle < 31; firstSingle++ { + word := encodeARMRawVMOVPair(toFloat, condition, firstCore, secondCore, firstSingle) + got, ok := decodeARMRawVMOVPair(word) + if !ok || got.toFloat != toFloat || got.condition != armConditionName(condition) || got.firstCore != firstCore || got.secondCore != secondCore || got.firstSingle != firstSingle { + t.Fatalf("decoded VMOV pair %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + } + if count != 2*15*16*16*31 { + t.Fatalf("covered %d VMOV pair encodings", count) + } +} + +func TestARMRawVMOVPairRejectsReservedAndUnsafeForms(t *testing.T) { + if _, ok := decodeARMRawVMOVPair(encodeARMRawVMOVPair(true, 15, 0, 1, 0)); ok { + t.Fatal("VMOV pair decoder accepted condition 0xf") + } + for _, word := range []uint32{encodeARMRawVMOVPair(true, 14, 15, 1, 0), encodeARMRawVMOVPair(false, 14, 0, 15, 0)} { + file, err := Parse(ArchARM, fmt.Sprintf("TEXT badVMOVPair(SB), $0-0\n\tWORD $%#08x\n\tRET\n", word)) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"badVMOVPair": {Name: "badVMOVPair", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted PC in VMOV pair %#08x", word) + } + } +} diff --git a/arm_more_test.go b/arm_more_test.go index 04f80bb5..1fe769fc 100644 --- a/arm_more_test.go +++ b/arm_more_test.go @@ -348,7 +348,8 @@ TEXT ·tail(SB),NOSPLIT,$0-0 "lshr i32", "ashr i32", "call i32 @llvm.fshr.i32", - "ret i16 0", + "trunc i32", + "ret i16", } { if !strings.Contains(ll, want) { t.Fatalf("missing %q in output:\n%s", want, ll) @@ -356,6 +357,21 @@ TEXT ·tail(SB),NOSPLIT,$0-0 } } +func TestTranslateARMTailCallAdaptsIntegerReturnWidths(t *testing.T) { + ll := translateARMForTest(t, `TEXT ·boolTail(SB),NOSPLIT,$0-0 + B ·wide(SB) + +TEXT ·wide(SB),NOSPLIT,$0-0 + RET +`, map[string]FuncSig{ + "example.boolTail": {Name: "example.boolTail", Ret: I1}, + "example.wide": {Name: "example.wide", Ret: I64}, + }) + if !strings.Contains(ll, "trunc i64 %") || !strings.Contains(ll, " to i1") { + t.Fatalf("ARM integer tailcall did not adapt i64 to i1:\n%s", ll) + } +} + func TestTranslateARMAdditionalAtomicForms(t *testing.T) { ll := translateARMForTest(t, `TEXT ·atomics(SB),NOSPLIT,$0-0 LDREXB (R1), R0 diff --git a/arm_needed.go b/arm_needed.go index 7b49b954..9147578a 100644 --- a/arm_needed.go +++ b/arm_needed.go @@ -2,8 +2,9 @@ package plan9asm import "strings" -// funcNeedsARMCFG decides whether ARM lowering needs the CFG-based path. -// The linear prototype only handles straight-line arithmetic/data movement. +// funcNeedsARMCFG is retained for focused classifier tests and historical +// callers. Translate now always selects the CFG path for supported ARM code so +// straight-line functions cannot bypass architecture-specific form checks. func funcNeedsARMCFG(fn Func) bool { for _, ins := range fn.Instrs { if ins.Op == OpLABEL { @@ -28,7 +29,7 @@ func funcNeedsARMCFG(fn Func) bool { return true } for _, arg := range ins.Args { - if arg.Kind == OpIdent { + if arg.Kind == OpIdent || arg.Kind == OpFPAddr { return true } } diff --git a/arm_official_directive_test.go b/arm_official_directive_test.go new file mode 100644 index 00000000..5a987629 --- /dev/null +++ b/arm_official_directive_test.go @@ -0,0 +1,58 @@ +//go:build !llgo + +package plan9asm + +import ( + "errors" + "strings" + "testing" +) + +func TestTranslateARMEndDirective(t *testing.T) { + const source = "TEXT endDirective(SB),$0-0\n\tRET\n\tEND\n" + requireARMGoAssemblerResult(t, source, true) + ll := translateARMForTest(t, source, map[string]FuncSig{ + "example.endDirective": {Name: "example.endDirective", Ret: Void}, + }) + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-end.ll", "arm-end.o", ll) +} + +func TestTranslateARMEndDirectiveIgnoresTrailingOperandsLikeGo(t *testing.T) { + const source = "TEXT endWithIgnoredOperand(SB),$0-0\n\tRET\n\tEND R0\n" + requireARMGoAssemblerResult(t, source, true) + translateARMForTest(t, source, map[string]FuncSig{ + "example.endWithIgnoredOperand": {Name: "example.endWithIgnoredOperand", Ret: Void}, + }) +} + +func TestProbeARMContextDependentOfficialDirectives(t *testing.T) { + cases := []struct { + name string + source string + }{ + {name: "return-from-exception", source: "RFE"}, + {name: "undefined-raw-word", source: "WORD $4294967295"}, + {name: "pc-relative-raw-word", source: "WORD $2863311530"}, + {name: "stateful-raw-word", source: "WORD $1431655765"}, + } + for _, test := range cases { + t.Run(test.name, func(t *testing.T) { + file, err := Parse(ArchARM, "TEXT probe(SB),$0-0\n\t"+test.source+"\n") + if err != nil { + t.Fatal(err) + } + instruction := file.Funcs[0].Instrs[1] + err = ProbeInstruction(ArchARM, "arm", instruction) + if !errors.Is(err, ErrProbeNeedsContext) { + t.Fatalf("ProbeInstruction(%s) error = %v, want ErrProbeNeedsContext", test.source, err) + } + if !strings.Contains(err.Error(), test.source) { + t.Fatalf("context error %q does not identify %q", err, test.source) + } + }) + } +} diff --git a/arm_raw_decode.go b/arm_raw_decode.go new file mode 100644 index 00000000..5ae986b0 --- /dev/null +++ b/arm_raw_decode.go @@ -0,0 +1,62 @@ +package plan9asm + +import ( + "encoding/binary" + "fmt" + "strings" + + "golang.org/x/arch/arm/armasm" +) + +// decodeARMRawWordInstruction recovers the Go assembler spelling for an ARM +// WORD using Go's architecture decoder. The returned instruction is not +// considered supported until the ordinary ARM semantic lowerer accepts it. +func decodeARMRawWordInstruction(ins Instr) (Instr, error) { + if len(ins.Args) != 1 || ins.Args[0].Kind != OpImm || ins.Args[0].ImmRaw != "" { + return Instr{}, fmt.Errorf("arm WORD expects exactly one resolved integer constant: %q", ins.Raw) + } + word := uint32(ins.Args[0].Imm) + // runtime/asm_arm.s deliberately uses this permanently undefined ARM + // encoding as a GDB-recognized software breakpoint. x/arch does not decode + // it, but it has the same terminating semantics as Go's operand-free UNDEF. + if word == 0xe7f001f0 { + return Instr{Op: "UNDEF", Raw: fmt.Sprintf("UNDEF /* decoded from %s */", ins.Raw)}, nil + } + var code [4]byte + binary.LittleEndian.PutUint32(code[:], word) + decoded, err := armasm.Decode(code[:], armasm.ModeARM) + if err != nil { + return Instr{}, fmt.Errorf("decode ARM WORD %#08x: %w", word, err) + } + for _, arg := range decoded.Args { + if arg == nil { + break + } + if _, ok := arg.(armasm.PCRel); ok { + return Instr{}, fmt.Errorf("ARM WORD %#08x is PC-relative and cannot be mapped safely to source labels: %q", word, ins.Raw) + } + } + syntax := armasm.GoSyntax(decoded, 0, nil, nil) + if op, rest, ok := strings.Cut(syntax, " "); ok && strings.HasPrefix(op, "BLX") { + condition := strings.TrimPrefix(op, "BLX") + if condition != "" && !strings.HasPrefix(condition, ".") { + condition = "." + condition + } + syntax = "BL" + condition + " (" + rest + ")" + } + // x/arch uses ARM architectural brackets for memory operands, while the + // Go assembler source grammar spells the same operand with parentheses. + // Convert them before parsing; otherwise [SP] is mistaken for a register + // list and raw LDREXD/STREXD forms lose their memory operand class. + syntax = strings.NewReplacer("[", "(", "]", ")").Replace(syntax) + file, err := Parse(ArchARM, "TEXT decoded(SB), $0-0\n"+syntax+"\n") + if err != nil { + return Instr{}, fmt.Errorf("parse decoded ARM WORD %#08x as %q: %w", word, syntax, err) + } + if len(file.Funcs) != 1 || len(file.Funcs[0].Instrs) != 2 { + return Instr{}, fmt.Errorf("decoded ARM WORD %#08x produced an invalid instruction sequence %q", word, syntax) + } + result := file.Funcs[0].Instrs[1] + result.Raw = fmt.Sprintf("%s /* decoded from %s */", result.Raw, ins.Raw) + return result, nil +} diff --git a/arm_raw_float_conversion_test.go b/arm_raw_float_conversion_test.go new file mode 100644 index 00000000..d3a75a75 --- /dev/null +++ b/arm_raw_float_conversion_test.go @@ -0,0 +1,38 @@ +//go:build !llgo + +package plan9asm + +import ( + "strings" + "testing" +) + +func TestTranslateARMRawSingleRegisterConversionCompleteFamily(t *testing.T) { + // These words cover both directions, signed and unsigned integer modes, + // even/odd single-register halves, and the S0/S31 register boundaries. + const source = `TEXT rawConversions(SB), $0-0 + WORD $0xeef80aee // vcvt.f32.s32 s1, s29 + WORD $0xeeb81a4f // vcvt.f32.u32 s2, s30 + WORD $0xeefd1aef // vcvt.s32.f32 s3, s31 + WORD $0xeebc2ac0 // vcvt.u32.f32 s4, s0 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawConversions": {Name: "rawConversions", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{"sitofp i32", "uitofp i32", "fptosi float", "fptoui float", `"target-features"="+vfp2"`} { + if !strings.Contains(ir, want) { + t.Fatalf("raw VCVT family IR omitted %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-vcvt.ll", "arm-raw-vcvt.o", ir) +} diff --git a/arm_raw_sxtb_test.go b/arm_raw_sxtb_test.go new file mode 100644 index 00000000..43b26332 --- /dev/null +++ b/arm_raw_sxtb_test.go @@ -0,0 +1,74 @@ +//go:build !llgo + +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestARMRawSXTBRotationFamilyUsesSemanticLowering(t *testing.T) { + const source = `TEXT rawSXTB(SB), $0-0 + WORD $0xe6af4074 // sxtb r4, r4 + WORD $0xe6af5474 // sxtb r5, r4, ror #8 + WORD $0xe6af6874 // sxtb r6, r4, ror #16 + WORD $0xe6af7c74 // sxtb r7, r4, ror #24 + RET +` + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"rawSXTB": {Name: "rawSXTB", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if strings.Count(ir, "sext i8") != 4 || strings.Count(ir, "= call i32 @llvm.fshr.i32") != 3 { + t.Fatalf("raw SXTB family did not retain rotate and signed-extension semantics:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-sxtb.ll", "arm-raw-sxtb.o", ir) +} + +func TestARMRawSXTBDecoderCoversEveryEncodingField(t *testing.T) { + count := 0 + for condition := 0; condition < 15; condition++ { + for rotation := 0; rotation < 4; rotation++ { + for source := 0; source < 16; source++ { + for destination := 0; destination < 16; destination++ { + word := uint32(condition)<<28 | 0x06af0070 | uint32(destination)<<12 | uint32(rotation)<<10 | uint32(source) + got, ok := decodeARMRawSXTB(word) + if !ok || got.condition != armConditionName(condition) || got.rotation != rotation*8 || got.source != source || got.destination != destination { + t.Fatalf("decoded ARM SXTB %#08x as %+v, ok=%v", word, got, ok) + } + count++ + } + } + } + } + if count != 15*4*16*16 { + t.Fatalf("covered %d SXTB encodings, want %d", count, 15*4*16*16) + } +} + +func TestARMRawSXTBRejectsReservedAndUnsafeForms(t *testing.T) { + if _, ok := decodeARMRawSXTB(0xf6af0070); ok { + t.Fatal("SXTB decoder accepted condition 0xf from the unconditional instruction space") + } + // 0xe6bf0070 is the official SXTH R0, R0 encoding, not a reserved + // SXTB-adjacent slot. The 0x69 variant is absent from the architectural + // signed/unsigned extend family (0x68, 0x6a-0x6c, and 0x6e-0x6f). + for _, word := range []uint32{0xe69f0070, 0xe6af047f} { + file, err := Parse(ArchARM, fmt.Sprintf("TEXT badSXTB(SB), $0-0\n\tWORD $%#08x\n\tRET\n", word)) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{Goarch: "arm", TargetTriple: "armv7-unknown-linux-gnueabihf", Sigs: map[string]FuncSig{"badSXTB": {Name: "badSXTB", Ret: Void}}}); err == nil { + t.Fatalf("Translate accepted reserved/unsafe SXTB-adjacent encoding %#08x", word) + } + } +} diff --git a/arm_raw_undef_test.go b/arm_raw_undef_test.go new file mode 100644 index 00000000..2ba89b2c --- /dev/null +++ b/arm_raw_undef_test.go @@ -0,0 +1,122 @@ +package plan9asm + +import ( + "fmt" + "strings" + "testing" +) + +func TestTranslateARMRawUndefinedInstructionEncodings(t *testing.T) { + for _, word := range []uint32{ + 0xe7f001f0, // Runtime's GDB-recognized software breakpoint. + 0xf7fabcfd, // Encoding emitted by Go 1.27 for named UNDEF. + } { + t.Run(fmt.Sprintf("%08x", word), func(t *testing.T) { + src := fmt.Sprintf("TEXT rawundef(SB),NOSPLIT,$0-0\n\tWORD $%#08x\n", word) + file, err := Parse(ArchARM, src) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + Goarch: "arm", + TargetTriple: "armv7-unknown-linux-gnueabihf", + Sigs: map[string]FuncSig{ + "rawundef": {Name: "rawundef", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{`asm sideeffect "udf #0"`, "unreachable"} { + if !strings.Contains(ir, want) { + t.Fatalf("raw UNDEF IR missing %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "armv7-unknown-linux-gnueabihf", "arm-raw-undef.ll", "arm-raw-undef.o", ir) + }) + } +} + +func TestTranslateARMRawUndefinedRejectsUnrelatedWord(t *testing.T) { + src := "TEXT rawunknown(SB),NOSPLIT,$0-0\n\tWORD $0xffffffff\n\tRET\n" + file, err := Parse(ArchARM, src) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{ + Goarch: "arm", + TargetTriple: "armv7-unknown-linux-gnueabihf", + Sigs: map[string]FuncSig{ + "rawunknown": {Name: "rawunknown", Ret: Void}, + }, + }); err == nil { + t.Fatal("Translate unexpectedly accepted an unrelated ARM WORD") + } +} + +func TestTranslateARMRawFPSCRTransferPair(t *testing.T) { + src := `TEXT fpscr(SB),NOSPLIT,$0-0 + WORD $0xeef1ba10 + BIC $(1<<24), R11 + WORD $0xeee1ba10 + RET +` + file, err := Parse(ArchARM, src) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"armv5te-unknown-linux-gnueabi", "armv7-unknown-linux-gnueabihf"} { + ir, err := Translate(file, Options{ + Goarch: "arm", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "fpscr": {Name: "fpscr", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + for _, want := range []string{`vmrs $0, fpscr`, `vmsr fpscr, $0`} { + if !strings.Contains(ir, want) { + t.Fatalf("%s raw FPSCR IR missing %q:\n%s", triple, want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm-raw-fpscr.ll", "arm-raw-fpscr.o", ir) + } +} + +func TestTranslateARMRawYieldHint(t *testing.T) { + src := "TEXT yieldhint(SB),NOSPLIT,$0-0\n\tWORD $0xe320f001\n\tRET\n" + file, err := Parse(ArchARM, src) + if err != nil { + t.Fatal(err) + } + for _, triple := range []string{"armv5te-unknown-linux-gnueabi", "armv7-unknown-linux-gnueabihf"} { + ir, err := Translate(file, Options{ + Goarch: "arm", + TargetTriple: triple, + Sigs: map[string]FuncSig{ + "yieldhint": {Name: "yieldhint", Ret: Void}, + }, + }) + if err != nil { + t.Fatalf("%s: %v", triple, err) + } + if !strings.Contains(ir, `.long 0xe320f001`) { + t.Fatalf("%s raw YIELD encoding was not preserved:\n%s", triple, ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, triple, "arm-raw-yield.ll", "arm-raw-yield.o", ir) + } +} diff --git a/arm_register_expression_test.go b/arm_register_expression_test.go new file mode 100644 index 00000000..d167839f --- /dev/null +++ b/arm_register_expression_test.go @@ -0,0 +1,44 @@ +package plan9asm + +import "testing" + +func TestNormalizeARMParenthesizedRegistersMatchesGoPrefixTables(t *testing.T) { + for _, tc := range []struct { + arch Arch + in string + want string + }{ + {ArchARM, "12(R(1))", "12(R1)"}, + {ArchARM, "R0>>R(1)", "R0>>R1"}, + {ArchARM, "R(1)<<2(R(3))", "R1<<2(R3)"}, + {ArchARM, "[R(0)-R(7)]", "[R0-R7]"}, + {ArchARM, "F(15)", "F15"}, + {ArchARM, "R(16)", "R(16)"}, + {ArchARM64, "R(30)", "R30"}, + {ArchARM64, "R(31)", "R(31)"}, + {ArchARM64, "F(31), V(31).B16, Z(31).D2, P(15).B, PN(15).D", "F31, V31.B16, Z31.D2, P15.B, PN15.D"}, + {ArchARM64, "P(16), PN(16)", "P(16), PN(16)"}, + {ArchARM64, "SPR(269)", "SPR(269)"}, + } { + if got := normalizeARMParenthesizedRegisters(tc.arch, tc.in); got != tc.want { + t.Errorf("normalizeARMParenthesizedRegisters(%v, %q) = %q, want %q", tc.arch, tc.in, got, tc.want) + } + } +} + +func TestParseARMNumericRegisterExpressionsFromOfficialAssemblerCorpus(t *testing.T) { + file, err := Parse(ArchARM, "TEXT probe(SB),NOSPLIT,$0-0\nADD R(1)< 32 { + return nil, fmt.Errorf("assembly include depth exceeds 32 at %s", file) + } + if active[file] { + return nil, fmt.Errorf("assembly include cycle at %s", file) + } + src, err := os.ReadFile(file) + if err != nil { + return nil, err + } + active[file] = true + defer delete(active, file) + + var out strings.Builder + for _, line := range strings.SplitAfter(string(src), "\n") { + trimmed := strings.TrimSpace(strings.TrimSuffix(line, "\n")) + match := quotedGoAssemblyIncludeRE.FindStringSubmatch(trimmed) + if match == nil || filepath.IsAbs(match[1]) { + out.WriteString(line) + continue + } + + includedPath := filepath.Clean(filepath.Join(filepath.Dir(file), filepath.FromSlash(match[1]))) + localAllowed := goAssemblyPathWithinRoot(sourceRoot, includedPath) + var included []byte + var includeErr error + if localAllowed { + resolvedPath, err := evalGoAssemblyPath(includedPath) + if err == nil { + if !goAssemblyPathWithinRoot(sourceRoot, resolvedPath) { + return nil, fmt.Errorf("assembly include %q escapes source root %s through symlink %s", match[1], sourceRoot, resolvedPath) + } + includedPath = resolvedPath + } else if !os.IsNotExist(err) { + return nil, fmt.Errorf("resolve assembly include %q from %s: %w", match[1], file, err) + } + included, includeErr = expandGoAssemblyIncludes(includedPath, sourceRoot, active, depth+1) + } + if !localAllowed || os.IsNotExist(includeErr) { + goRoot, err := evalGoAssemblyPath(filepath.Clean(runtime.GOROOT())) + if err != nil { + return nil, fmt.Errorf("resolve GOROOT symlinks: %w", err) + } + goIncludeRoot := filepath.Join(goRoot, "pkg", "include") + goIncludedPath := filepath.Clean(filepath.Join(goIncludeRoot, filepath.FromSlash(match[1]))) + if goAssemblyPathWithinRoot(goRoot, goIncludedPath) { + resolvedPath, err := evalGoAssemblyPath(goIncludedPath) + if err == nil { + if !goAssemblyPathWithinRoot(goRoot, resolvedPath) { + return nil, fmt.Errorf("assembly include %q escapes GOROOT %s through symlink %s", match[1], goRoot, resolvedPath) + } + goIncludedPath = resolvedPath + } else if !os.IsNotExist(err) { + return nil, fmt.Errorf("resolve Go assembly include %q: %w", match[1], err) + } + included, includeErr = expandGoAssemblyIncludes(goIncludedPath, goRoot, active, depth+1) + } else if !localAllowed { + return nil, fmt.Errorf("assembly include %q escapes source root %s and GOROOT %s", match[1], sourceRoot, goRoot) + } + if os.IsNotExist(includeErr) { + if !localAllowed { + return nil, fmt.Errorf("assembly include %q escapes source root %s", match[1], sourceRoot) + } + out.WriteString(line) + continue + } + } + if includeErr != nil { + return nil, fmt.Errorf("expand assembly include %q from %s: %w", match[1], file, includeErr) + } + out.Write(included) + if strings.HasSuffix(line, "\n") && len(included) != 0 && included[len(included)-1] != '\n' { + out.WriteByte('\n') + } + } + return []byte(out.String()), nil +} + +// evalGoAssemblyPath canonicalizes symlinks before containment checks. The +// Windows hosted toolcache exposes GOROOT through a cross-volume directory +// link which filepath.EvalSymlinks cannot always traverse even though the path +// is readable. In that one trusted tree, retain the absolute path after proving +// it exists; module and arbitrary source roots still require full resolution. +func evalGoAssemblyPath(path string) (string, error) { + return evalGoAssemblyPathForOS(path, runtime.GOOS, runtime.GOROOT(), filepath.EvalSymlinks) +} + +func evalGoAssemblyPathForOS(path, goos, goRoot string, eval func(string) (string, error)) (string, error) { + resolved, err := eval(path) + if err == nil || goos != "windows" { + return resolved, err + } + absPath, absErr := filepath.Abs(path) + if absErr != nil { + return "", err + } + absRoot, absErr := filepath.Abs(goRoot) + if absErr != nil || !goAssemblyPathWithinRoot(filepath.Clean(absRoot), filepath.Clean(absPath)) { + return "", err + } + if _, statErr := os.Stat(absPath); statErr != nil { + return "", err + } + return filepath.Clean(absPath), nil +} + +func goAssemblyPathWithinRoot(root, candidate string) bool { + rel, err := filepath.Rel(root, candidate) + return err == nil && rel != ".." && !strings.HasPrefix(rel, ".."+string(filepath.Separator)) +} diff --git a/assembly_include_symlink_test.go b/assembly_include_symlink_test.go new file mode 100644 index 00000000..4d730313 --- /dev/null +++ b/assembly_include_symlink_test.go @@ -0,0 +1,34 @@ +//go:build !windows && !llgo + +package plan9asm + +import ( + "os" + "path/filepath" + "strings" + "testing" +) + +func TestReadGoAssemblySourceRejectsSymlinkIncludeOutsideRoot(t *testing.T) { + sandbox := t.TempDir() + sourceRoot := filepath.Join(sandbox, "module") + if err := os.Mkdir(sourceRoot, 0o700); err != nil { + t.Fatal(err) + } + outside := filepath.Join(sandbox, "outside.h") + if err := os.WriteFile(outside, []byte("#define OUTSIDE 1\n"), 0o600); err != nil { + t.Fatal(err) + } + if err := os.Symlink(outside, filepath.Join(sourceRoot, "escape.h")); err != nil { + t.Fatal(err) + } + asm := filepath.Join(sourceRoot, "entry_amd64.s") + if err := os.WriteFile(asm, []byte("#include \"escape.h\"\nTEXT ·entry(SB),$0-0\nRET\n"), 0o600); err != nil { + t.Fatal(err) + } + + _, err := ReadGoAssemblySource(asm, sourceRoot) + if err == nil || !strings.Contains(err.Error(), "escapes source root") { + t.Fatalf("ReadGoAssemblySource symlink escape error = %v, want source-root rejection", err) + } +} diff --git a/assembly_include_test.go b/assembly_include_test.go new file mode 100644 index 00000000..20020243 --- /dev/null +++ b/assembly_include_test.go @@ -0,0 +1,67 @@ +//go:build !llgo + +package plan9asm + +import ( + "errors" + "os" + "path/filepath" + "strings" + "testing" +) + +func TestEvalGoAssemblyPathWindowsGOROOTLinkFallback(t *testing.T) { + goRoot := t.TempDir() + file := filepath.Join(goRoot, "src", "runtime", "asm.s") + if err := os.MkdirAll(filepath.Dir(file), 0o700); err != nil { + t.Fatal(err) + } + if err := os.WriteFile(file, []byte("RET\n"), 0o600); err != nil { + t.Fatal(err) + } + evalErr := errors.New("cross-volume link cannot be evaluated") + failingEval := func(string) (string, error) { return "", evalErr } + got, err := evalGoAssemblyPathForOS(file, "windows", goRoot, failingEval) + if err != nil { + t.Fatalf("trusted existing GOROOT path fallback error = %v", err) + } + want, err := filepath.Abs(file) + if err != nil { + t.Fatal(err) + } + if got != filepath.Clean(want) { + t.Fatalf("trusted existing GOROOT path fallback = %q, want %q", got, want) + } + + outside := filepath.Join(t.TempDir(), "outside.s") + if err := os.WriteFile(outside, []byte("RET\n"), 0o600); err != nil { + t.Fatal(err) + } + if _, err := evalGoAssemblyPathForOS(outside, "windows", goRoot, failingEval); !errors.Is(err, evalErr) { + t.Fatalf("outside-GOROOT fallback error = %v, want %v", err, evalErr) + } +} + +func TestReadGoAssemblySourceExpandsNestedLocalHeaders(t *testing.T) { + dir := t.TempDir() + write := func(name, content string) { + t.Helper() + if err := os.WriteFile(filepath.Join(dir, name), []byte(content), 0o600); err != nil { + t.Fatal(err) + } + } + write("ops.h", "#define SAVE(offset) MOVD R19, offset(RSP)\n") + write("abi.h", "#include \"ops.h\"\n") + write("entry_arm64.s", "#include \"abi.h\"\nTEXT entry(SB),$0-0\nSAVE(8)\nRET\n") + + src, err := ReadGoAssemblySource(filepath.Join(dir, "entry_arm64.s"), dir) + if err != nil { + t.Fatal(err) + } + if strings.Contains(string(src), `#include "abi.h"`) || !strings.Contains(string(src), "#define SAVE") { + t.Fatalf("nested header was not expanded:\n%s", src) + } + if _, err := ParseWithDefines(ArchARM64, string(src), GoAssemblerDefines("linux", "arm64")); err != nil { + t.Fatalf("expanded assembly did not parse: %v\n%s", err, src) + } +} diff --git a/cmd/plan9asm/go.mod b/cmd/plan9asm/go.mod index 5809e299..ef8358bd 100644 --- a/cmd/plan9asm/go.mod +++ b/cmd/plan9asm/go.mod @@ -9,6 +9,7 @@ require ( require ( github.com/xgo-dev/llvm v0.9.9 // indirect + golang.org/x/arch v0.14.0 // indirect golang.org/x/mod v0.33.0 // indirect golang.org/x/sync v0.19.0 // indirect ) diff --git a/cmd/plan9asm/go.sum b/cmd/plan9asm/go.sum index 59f00a20..3d4f7ea0 100644 --- a/cmd/plan9asm/go.sum +++ b/cmd/plan9asm/go.sum @@ -2,6 +2,8 @@ github.com/google/go-cmp v0.6.0 h1:ofyhxvXcZhMsU5ulbFiLKl/XBFqE1GSq7atu8tAmTRI= github.com/google/go-cmp v0.6.0/go.mod h1:17dUlkBOakJ0+DkrSSNjCkIjxS6bF9zb3elmeNGIjoY= github.com/xgo-dev/llvm v0.9.9 h1:u4RZvy0vxu8nNt4oTrhttyMSyscYtmiy9geP+Kl/RYg= github.com/xgo-dev/llvm v0.9.9/go.mod h1:42vav2/cI5BAIcL543DZSMO9do8/aCK2z7JERH+AE+M= +golang.org/x/arch v0.14.0 h1:z9JUEZWr8x4rR0OU6c4/4t6E6jOZ8/QBS2bBYBm4tx4= +golang.org/x/arch v0.14.0/go.mod h1:FEVrYAQjsQXMVJ1nsMoVVXPZg6p2JE2mx8psSWTDQys= golang.org/x/mod v0.33.0 h1:tHFzIWbBifEmbwtGz65eaWyGiGZatSrT9prnU8DbVL8= golang.org/x/mod v0.33.0/go.mod h1:swjeQEj+6r7fODbD2cqrnje9PnziFuw4bmLbBZFrQ5w= golang.org/x/sync v0.19.0 h1:vV+1eWNmZ5geRlYjzm2adRgW2/mcpevXNg50YZtPCE4= diff --git a/cmd/plan9asm/main.go b/cmd/plan9asm/main.go index e352473e..3690f3dc 100644 --- a/cmd/plan9asm/main.go +++ b/cmd/plan9asm/main.go @@ -19,6 +19,7 @@ import ( "strings" "github.com/xgo-dev/plan9asm" + "github.com/xgo-dev/plan9asm/internal/asmsig" "golang.org/x/tools/go/packages" ) @@ -343,15 +344,30 @@ func transpileSingleFileMode(inFile, outFile, goos, goarch string, annotate bool } func translateAsmForPackage(pkg *packages.Package, asmPath, goos, goarch string, annotate bool) (translation, bool, error) { - src, err := os.ReadFile(asmPath) + sourceRoot := filepath.Dir(asmPath) + if pkg != nil && pkg.Module != nil && pkg.Module.Dir != "" { + sourceRoot = pkg.Module.Dir + } + src, err := plan9asm.ReadGoAssemblySource(asmPath, sourceRoot) if err != nil { return translation{}, false, err } + imports := make(map[string]*types.Package, len(pkg.Imports)) + for path, imported := range pkg.Imports { + if imported != nil && imported.Types != nil { + imports[path] = imported.Types + } + } + src = plan9asm.ExpandGoAssemblySource(plan9asm.GoPackage{ + Path: pkg.PkgPath, + Types: pkg.Types, + Imports: imports, + }, src, goarch) arch, err := toPlan9Arch(goarch) if err != nil { return translation{}, false, err } - file, err := plan9asm.Parse(arch, string(src)) + file, err := plan9asm.ParseWithDefines(arch, string(src), plan9asm.GoAssemblerDefines(goos, goarch)) if err != nil { if strings.Contains(err.Error(), "no TEXT directive found") { return translation{}, false, nil @@ -368,12 +384,6 @@ func translateAsmForPackage(pkg *packages.Package, asmPath, goos, goarch string, if goos == "js" || goos == "wasip1" { wasmABI = plan9asm.WASMABIGo } - imports := make(map[string]*types.Package, len(pkg.Imports)) - for path, imported := range pkg.Imports { - if imported != nil && imported.Types != nil { - imports[path] = imported.Types - } - } tr, err := plan9asm.TranslateGoModule(plan9asm.GoPackage{ Path: pkg.PkgPath, Types: pkg.Types, @@ -786,15 +796,21 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str if pkg == nil || pkg.Types == nil || pkg.Types.Scope() == nil { for _, fn := range file.Funcs { fs := fallbackSigForAsmFunc(fn, resolve(stripABISuffix(fn.Sym)), goarch) - if goarch == "wasm" && strings.HasSuffix(fn.Sym, "<>") { - var err error - fs, err = plan9asm.InferWASMAssemblyFuncSig(fn, fs.Name) - if err != nil { - return nil, err + if goarch == "wasm" { + if native, ok := plan9asm.LookupGoWASMNativeFuncSig(fs.Name); ok { + fs = native + } else if strings.HasSuffix(stripABISuffix(fn.Sym), "<>") && plan9asm.WASMAssemblyUsesNativeReturn(fn) { + var err error + fs, err = plan9asm.InferWASMAssemblyFuncSig(fn, fs.Name) + if err != nil { + return nil, err + } + fs.WASMNative = true } } sigs[fs.Name] = fs } + asmsig.RefineTailForwarders(file, sigs, resolve, nil) return sigs, nil } @@ -829,14 +845,19 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str } if goarch == "wasm" { for _, fn := range file.Funcs { - if !strings.HasSuffix(fn.Sym, "<>") { - continue - } resolved := resolve(stripABISuffix(fn.Sym)) - fs, err := plan9asm.InferWASMAssemblyFuncSig(fn, resolved) - if err != nil { - return nil, err + fs, ok := plan9asm.LookupGoWASMNativeFuncSig(resolved) + if !ok { + if !strings.HasSuffix(stripABISuffix(fn.Sym), "<>") || !plan9asm.WASMAssemblyUsesNativeReturn(fn) { + continue + } + var err error + fs, err = plan9asm.InferWASMAssemblyFuncSig(fn, resolved) + if err != nil { + return nil, err + } } + fs.WASMNative = true sigs[resolved] = fs } } @@ -857,7 +878,7 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str // result slots agree with the declared caller. Local helpers share the // caller's physical frame, so a byte result may otherwise remain an i32 // fallback slot underneath an i1 function signature. - if tail && caller.Name != "" && !declaredSigs[resolved] { + if tail && declaredSigs[caller.Name] && !declaredSigs[resolved] { existing.Ret = caller.Ret if len(existing.Frame.Results) == len(caller.Frame.Results) { for i := range existing.Frame.Results { @@ -873,6 +894,12 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str } return } + if goarch == "wasm" { + if fs, ok := plan9asm.LookupGoWASMNativeFuncSig(resolved); ok { + sigs[resolved] = fs + return + } + } fs, ok, err := tryDeclSig(scope, asmDeclLookupSym(pkg, sym), resolved, linknames, goarch, sz) if err == nil && ok { sigs[resolved] = fs @@ -893,8 +920,8 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str caller := sigs[callerName] for _, ins := range fn.Instrs { op := strings.ToUpper(string(ins.Op)) - tail := op == "JMP" || op == "B" - if !(tail || op == "CALL" || op == "BL") { + tail := op == "JMP" || op == "B" || (op == "RET" && len(ins.Args) == 1) + if !(tail || op == "CALL" || op == "CALLNORESUME" || op == "WASMCALL" || op == "BL") { continue } if len(ins.Args) != 1 || ins.Args[0].Kind != plan9asm.OpSym { @@ -927,6 +954,7 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str } } + asmsig.RefineTailForwarders(file, sigs, resolve, declaredSigs) return sigs, nil } @@ -948,7 +976,7 @@ func fallbackSigForAsmFunc(fn plan9asm.Func, resolved, goarch string) plan9asm.F for _, ins := range fn.Instrs { op := strings.ToUpper(string(ins.Op)) for i, a := range ins.Args { - if a.Kind != plan9asm.OpFP { + if a.Kind != plan9asm.OpFP && a.Kind != plan9asm.OpFPAddr { continue } if isLikelyResultSlot(op, i, len(ins.Args), a.FPName) { @@ -981,7 +1009,12 @@ func fallbackSigForAsmFunc(fn plan9asm.Func, resolved, goarch string) plan9asm.F ret := plan9asm.Void switch len(results) { case 0: - ret = word + // A fallback with FP parameters follows ABI0, whose results also live + // in explicit FP slots. No result slot therefore means void. Keep the + // conservative word return only for register-only assembly helpers. + if len(params) == 0 { + ret = word + } case 1: ret = word default: diff --git a/cmd/plan9asm/main_test.go b/cmd/plan9asm/main_test.go index 3a7c8f13..085b61be 100644 --- a/cmd/plan9asm/main_test.go +++ b/cmd/plan9asm/main_test.go @@ -1,12 +1,14 @@ package main import ( + "go/constant" "go/token" "go/types" "os" "path/filepath" "reflect" "runtime" + "strings" "testing" "github.com/xgo-dev/plan9asm" @@ -35,6 +37,65 @@ func TestPackageSFilesAbsFiltersNonPlan9Asm(t *testing.T) { } } +func TestTranslateAsmForPackageExpandsRuntimeStyleFunctionMacro(t *testing.T) { + dir := t.TempDir() + header := filepath.Join(dir, "abi.h") + asm := filepath.Join(dir, "entry_arm64.s") + if err := os.WriteFile(header, []byte("#ifdef GOOS_linux\n#define SAVE(offset) MOVD R19, offset(RSP)\n#else\n#define SAVE(offset) UNKNOWN_TARGET\n#endif\n"), 0o600); err != nil { + t.Fatal(err) + } + if err := os.WriteFile(asm, []byte("#include \"abi.h\"\nTEXT ·entry(SB),NOSPLIT,$0-0\nSAVE(8)\nRET\n"), 0o600); err != nil { + t.Fatal(err) + } + + pkgTypes := types.NewPackage("example.com/m/p", "p") + pkgTypes.Scope().Insert(types.NewFunc(token.NoPos, pkgTypes, "entry", types.NewSignature(nil, nil, nil, false))) + pkg := &packages.Package{ + PkgPath: pkgTypes.Path(), + Types: pkgTypes, + TypesSizes: types.SizesFor("gc", "arm64"), + Module: &packages.Module{Path: "example.com/m", Dir: dir}, + } + tr, ok, err := translateAsmForPackage(pkg, asm, "linux", "arm64", false) + if err != nil { + t.Fatal(err) + } + if !ok || !strings.Contains(tr.LLVMIR, "store i64") { + t.Fatalf("included SAVE macro was not translated:\n%s", tr.LLVMIR) + } +} + +func TestTranslateAsmForPackageExpandsGeneratedGoAsmConstants(t *testing.T) { + dir := t.TempDir() + asm := filepath.Join(dir, "asm_amd64.s") + if err := os.WriteFile(asm, []byte(`#include "go_asm.h" +#ifdef GOOS_windows +GLOBL zeroTLS<>(SB),RODATA,$const_tlsSize +#endif +TEXT ·entry(SB),NOSPLIT,$0-0 +RET +`), 0o600); err != nil { + t.Fatal(err) + } + + pkgTypes := types.NewPackage("runtime", "runtime") + pkgTypes.Scope().Insert(types.NewConst(token.NoPos, pkgTypes, "tlsSize", types.Typ[types.Int], constant.MakeInt64(48))) + pkgTypes.Scope().Insert(types.NewFunc(token.NoPos, pkgTypes, "entry", types.NewSignature(nil, nil, nil, false))) + pkg := &packages.Package{ + PkgPath: pkgTypes.Path(), + Types: pkgTypes, + TypesSizes: types.SizesFor("gc", "amd64"), + Module: &packages.Module{Path: "runtime", Dir: dir}, + } + tr, ok, err := translateAsmForPackage(pkg, asm, "windows", "amd64", false) + if err != nil { + t.Fatal(err) + } + if !ok || !strings.Contains(tr.LLVMIR, `@"runtime.zeroTLS$local" = constant [48 x i8]`) { + t.Fatalf("generated const_tlsSize was not expanded:\n%s", tr.LLVMIR) + } +} + func TestFallbackSigUsesTargetWordSize(t *testing.T) { fn := plan9asm.Func{Instrs: []plan9asm.Instr{{ Op: "MOVW", @@ -62,6 +123,20 @@ func TestFallbackSigUsesTargetWordSize(t *testing.T) { } } +func TestFallbackSigTreatsAddressedFrameWithoutResultAsVoid(t *testing.T) { + fn := plan9asm.Func{Instrs: []plan9asm.Instr{{ + Op: "LEAL", + Args: []plan9asm.Operand{ + {Kind: plan9asm.OpFPAddr, FPName: "arg", FPOffset: 0}, + {Kind: plan9asm.OpReg, Reg: "AX"}, + }, + }}} + got := fallbackSigForAsmFunc(fn, "example.helper$local", "386") + if len(got.Args) != 1 || got.Args[0] != plan9asm.I32 || got.Ret != plan9asm.Void { + t.Fatalf("fallback signature = %#v, want (i32) -> void", got) + } +} + func TestLikelyResultSlotUsesExplicitResultPrefix(t *testing.T) { if !isLikelyResultSlot("MOVW", 0, 2, "ret0") { t.Fatal("ret-prefixed FP slot was not classified as a result") @@ -204,6 +279,74 @@ TEXT runtime·rt0_go(SB),NOSPLIT,$0 } } +func TestUndeclaredPureForwarderInheritsABI0Frame(t *testing.T) { + file, err := plan9asm.Parse(plan9asm.ArchAMD64, "TEXT forward(SB),$0-8\nJMP body(SB)\nTEXT body(SB),$0-8\nMOVQ arg+0(FP), AX\nRET\n") + if err != nil { + t.Fatal(err) + } + for _, pkg := range []*packages.Package{nil, {Types: types.NewPackage("example", "example"), TypesSizes: types.SizesFor("gc", "amd64")}} { + sigs, err := sigsForAsmFile(pkg, file, resolveSymFunc("example"), "amd64") + if err != nil { + t.Fatal(err) + } + got := sigs["forward"] + if got.Ret != plan9asm.Void || len(got.Args) != 1 || len(got.Frame.Params) != 1 { + t.Fatalf("forward ABI = %#v", got) + } + } +} + +func TestSigsForAsmFileDiscoversWasmCallOpcodes(t *testing.T) { + for _, op := range []string{"Call", "CALLNORESUME"} { + t.Run(op, func(t *testing.T) { + file, err := plan9asm.Parse(plan9asm.ArchWASM, "TEXT ·caller(SB),NOSPLIT,$0-0\n\t"+op+" ·target(SB)\n\tRET\n") + if err != nil { + t.Fatal(err) + } + pkgTypes := types.NewPackage("example", "example") + voidSig := types.NewSignature(nil, nil, nil, false) + pkgTypes.Scope().Insert(types.NewFunc(token.NoPos, pkgTypes, "caller", voidSig)) + pkgTypes.Scope().Insert(types.NewFunc(token.NoPos, pkgTypes, "target", voidSig)) + pkg := &packages.Package{Types: pkgTypes, TypesSizes: types.SizesFor("gc", "wasm")} + sigs, err := sigsForAsmFile(pkg, file, resolveSymFunc("example"), "wasm") + if err != nil { + t.Fatal(err) + } + if got, ok := sigs["example.target"]; !ok || got.Ret != plan9asm.Void { + t.Fatalf("%s target signature = %#v, present=%v; want void", op, got, ok) + } + }) + } +} + +func TestSigsForAsmFileUsesGoWasmNativeSignatures(t *testing.T) { + file, err := plan9asm.Parse(plan9asm.ArchWASM, `TEXT wasm_export_run(SB),NOSPLIT,$0 + Call wasm_pc_f_loop(SB) + Return + +TEXT gcWriteBarrier<>(SB),NOSPLIT,$0 + Get R0 + I64Const $8 + I64Add + Return +`) + if err != nil { + t.Fatal(err) + } + pkgTypes := types.NewPackage("runtime", "runtime") + pkg := &packages.Package{Types: pkgTypes, TypesSizes: types.SizesFor("gc", "wasm")} + sigs, err := sigsForAsmFile(pkg, file, resolveSymFunc("runtime"), "wasm") + if err != nil { + t.Fatal(err) + } + if got := sigs["wasm_pc_f_loop"]; len(got.Args) != 0 || got.Ret != plan9asm.Void || !got.WASMNative { + t.Fatalf("wasm_pc_f_loop signature = %#v; want native () -> void", got) + } + if got := sigs["runtime.gcWriteBarrier$local"]; !reflect.DeepEqual(got.Args, []plan9asm.LLVMType{plan9asm.I64}) || got.Ret != plan9asm.I64 || !got.WASMNative { + t.Fatalf("gcWriteBarrier signature = %#v; want native (i64) -> i64", got) + } +} + func TestLLVMTypeForGoPointerLikeValues(t *testing.T) { for name, typ := range map[string]types.Type{ "func": types.NewSignature(nil, nil, nil, false), diff --git a/cmd/plan9asmcorpus/discovery.go b/cmd/plan9asmcorpus/discovery.go new file mode 100644 index 00000000..93f0444d --- /dev/null +++ b/cmd/plan9asmcorpus/discovery.go @@ -0,0 +1,1935 @@ +package main + +import ( + "archive/zip" + "bufio" + "bytes" + "context" + "crypto/sha256" + "encoding/binary" + "encoding/json" + "errors" + "fmt" + "go/build" + "go/build/constraint" + "go/parser" + "go/token" + "io" + "math/bits" + "os" + "os/exec" + "path" + "path/filepath" + "runtime" + "sort" + "strings" + "time" + + "github.com/xgo-dev/plan9asm/internal/discoverymeta" + "golang.org/x/mod/modfile" + "golang.org/x/mod/module" +) + +const discoveryReportSchema = 2 + +const ( + discoveryStatusPassed = "passed" + discoveryStatusFailed = "failed" + discoveryStatusNotApplicable = "not_applicable" +) + +type discoveryRecord struct { + Kind string `json:"kind"` + Module string `json:"module"` + Version string `json:"version"` + Architectures []string `json:"architectures,omitempty"` + AsmFiles []string `json:"asm_files,omitempty"` +} + +type discoveryCandidate struct { + Module string `json:"module"` + Version string `json:"version"` + Architectures []string `json:"architectures"` + AsmFiles []string `json:"asm_files"` +} + +func (c discoveryCandidate) exactKey() string { + return c.Module + "@" + c.Version +} + +type discoveryCorpusConfig struct { + LedgerPath string + RepoRoot string + Translator string + LLC string + Targets []string + FilterTargets bool + ShardIndex int + ShardCount int + CandidateTimeout time.Duration + ReportPath string +} + +type discoveryExecutionPlan struct { + ModulePath string + Patterns []string + GoMod string +} + +type discoveryBuildConfiguration struct { + BuildTags []string `json:"build_tags,omitempty"` + Targets []string `json:"targets"` + AsmFiles []string `json:"asm_files"` +} + +type discoveryPackageGroup struct { + Pattern string + AsmFiles []string +} + +const ( + discoverySourceNotApplicableGoAssembler = "go_assembler_rejected_all_supported_targets" + discoverySourceNotApplicableNoGoPackage = "no_current_go_package" + discoverySourceNotApplicableGoBuild = "go_build_rejected_package_target" + discoverySourceNotApplicableAsmDecl = "go_vet_asmdecl_rejected_target" +) + +type discoverySourceNotApplicableItem struct { + AsmFile string `json:"asm_file,omitempty"` + AsmFiles []string `json:"asm_files,omitempty"` + Targets []string `json:"targets"` + Kind string `json:"kind"` + Reason string `json:"reason"` +} + +type moduleDownloadInfo struct { + Path string `json:"Path"` + Version string `json:"Version"` + Dir string `json:"Dir"` + GoMod string `json:"GoMod"` + Zip string `json:"Zip"` + Error string `json:"Error"` +} + +type discoveryCorpusResult struct { + Module string `json:"module"` + Version string `json:"version"` + Status string `json:"status"` + DiscoveredAsmFiles []string `json:"discovered_asm_files"` + ApplicableAsmFiles []string `json:"applicable_asm_files"` + BuildConfigurations []discoveryBuildConfiguration `json:"build_configurations,omitempty"` + Patterns []string `json:"patterns,omitempty"` + Translations int `json:"translations"` + NotApplicableTranslations int `json:"not_applicable_translations,omitempty"` + NotApplicableItems []matrixTargetNotApplicableItem `json:"not_applicable_items,omitempty"` + SourceNotApplicableItems []discoverySourceNotApplicableItem `json:"source_not_applicable_items,omitempty"` + NotApplicableReason string `json:"not_applicable_reason,omitempty"` + Error string `json:"error,omitempty"` +} + +type discoveryCorpusReport struct { + SchemaVersion int `json:"schema_version"` + Targets []string `json:"targets,omitempty"` + TargetFiltered bool `json:"target_filtered,omitempty"` + ShardIndex int `json:"shard_index"` + ShardCount int `json:"shard_count"` + CandidateTotal int `json:"candidate_total"` + EligibleCandidates int `json:"eligible_candidates"` + Selected int `json:"selected"` + Passed int `json:"passed"` + Failed int `json:"failed"` + NotApplicable int `json:"not_applicable"` + Translations int `json:"translations"` + NotApplicableTranslations int `json:"not_applicable_translations"` + Results []discoveryCorpusResult `json:"results"` +} + +func loadDiscoveryCandidates(root string) ([]discoveryCandidate, error) { + info, err := os.Stat(root) + if err != nil { + return nil, fmt.Errorf("stat discovery ledger: %w", err) + } + var files []string + if !info.IsDir() { + files = []string{root} + } else { + files, err = filepath.Glob(filepath.Join(root, "records", "*.jsonl")) + if err != nil { + return nil, fmt.Errorf("list discovery ledger records: %w", err) + } + } + if len(files) == 0 { + return nil, fmt.Errorf("discovery ledger %q contains no JSONL records", root) + } + sort.Strings(files) + type candidateSets struct { + candidate discoveryCandidate + arches map[string]bool + asmFiles map[string]bool + } + merged := make(map[string]*candidateSets) + for _, filePath := range files { + file, err := os.Open(filePath) + if err != nil { + return nil, fmt.Errorf("open discovery records %s: %w", filePath, err) + } + scanner := bufio.NewScanner(file) + scanner.Buffer(make([]byte, 64<<10), 32<<20) + line := 0 + for scanner.Scan() { + line++ + if len(bytes.TrimSpace(scanner.Bytes())) == 0 { + continue + } + var record discoveryRecord + if err := json.Unmarshal(scanner.Bytes(), &record); err != nil { + file.Close() + return nil, fmt.Errorf("decode discovery record %s:%d: %w", filePath, line, err) + } + if record.Kind != "matched" { + continue + } + if err := validateDiscoveryRecord(record); err != nil { + file.Close() + return nil, fmt.Errorf("invalid discovery record %s:%d: %w", filePath, line, err) + } + key := record.Module + "@" + record.Version + item := merged[key] + if item == nil { + item = &candidateSets{ + candidate: discoveryCandidate{Module: record.Module, Version: record.Version}, + arches: make(map[string]bool), + asmFiles: make(map[string]bool), + } + merged[key] = item + } + for _, arch := range record.Architectures { + item.arches[arch] = true + } + for _, asmFile := range record.AsmFiles { + item.asmFiles[asmFile] = true + } + } + if err := scanner.Err(); err != nil { + file.Close() + return nil, fmt.Errorf("read discovery records %s: %w", filePath, err) + } + if err := file.Close(); err != nil { + return nil, fmt.Errorf("close discovery records %s: %w", filePath, err) + } + } + candidates := make([]discoveryCandidate, 0, len(merged)) + for _, item := range merged { + for arch := range item.arches { + item.candidate.Architectures = append(item.candidate.Architectures, arch) + } + for asmFile := range item.asmFiles { + item.candidate.AsmFiles = append(item.candidate.AsmFiles, asmFile) + } + sort.Strings(item.candidate.Architectures) + sort.Strings(item.candidate.AsmFiles) + candidates = append(candidates, item.candidate) + } + sort.Slice(candidates, func(i, j int) bool { + if candidates[i].Module != candidates[j].Module { + return candidates[i].Module < candidates[j].Module + } + return candidates[i].Version < candidates[j].Version + }) + return candidates, nil +} + +func validateDiscoveryRecord(record discoveryRecord) error { + if record.Module == "" || strings.TrimSpace(record.Module) != record.Module || strings.ContainsAny(record.Module, "\r\n\t ") { + return fmt.Errorf("invalid module %q", record.Module) + } + if record.Version == "" || strings.TrimSpace(record.Version) != record.Version || strings.ContainsAny(record.Version, "\r\n\t ") { + return fmt.Errorf("invalid version %q", record.Version) + } + if len(record.AsmFiles) == 0 { + return fmt.Errorf("%s@%s has no assembly files", record.Module, record.Version) + } + for _, asmFile := range record.AsmFiles { + if asmFile == "" || strings.Contains(asmFile, "\\") || path.IsAbs(asmFile) || path.Clean(asmFile) != asmFile || strings.HasPrefix(asmFile, "../") || !strings.HasSuffix(asmFile, ".s") { + return fmt.Errorf("%s@%s has unsafe assembly path %q", record.Module, record.Version, asmFile) + } + } + return nil +} + +func selectDiscoveryShard(candidates []discoveryCandidate, shardIndex, shardCount int) []discoveryCandidate { + if shardCount <= 0 || shardIndex < 0 || shardIndex >= shardCount { + return nil + } + selected := make([]discoveryCandidate, 0, len(candidates)/shardCount+1) + for _, candidate := range candidates { + if discoveryCandidateShard(candidate, shardCount) == shardIndex { + selected = append(selected, candidate) + } + } + return selected +} + +func discoveryCandidateShard(candidate discoveryCandidate, shardCount int) int { + if shardCount <= 0 { + return -1 + } + sum := sha256.Sum256([]byte(candidate.exactKey())) + return int(binary.BigEndian.Uint64(sum[:8]) % uint64(shardCount)) +} + +func verifyDiscoveryCorpusReports(ledgerPath, reportsPath string, expectedTargets []string) error { + candidates, err := loadDiscoveryCandidates(ledgerPath) + if err != nil { + return err + } + expected := make(map[string]discoveryCandidate, len(candidates)) + for _, candidate := range candidates { + expected[candidate.exactKey()] = candidate + } + files, err := discoveryCorpusReportFiles(reportsPath) + if err != nil { + return err + } + if len(files) == 0 { + return fmt.Errorf("no discovery shard reports found in %q", reportsPath) + } + seenShards := make(map[int]string) + seenCandidates := make(map[string]string, len(candidates)) + shardCount := 0 + for _, filePath := range files { + report, err := readDiscoveryCorpusReport(filePath) + if err != nil { + return err + } + if report.SchemaVersion != discoveryReportSchema { + return fmt.Errorf("%s: unsupported discovery report schema %d", filePath, report.SchemaVersion) + } + if err := validateDiscoveryCorpusAccounting(report); err != nil { + return fmt.Errorf("%s: %w", filePath, err) + } + if report.TargetFiltered { + return fmt.Errorf("%s: target-filtered report cannot prove complete ledger coverage", filePath) + } + if !equalDiscoveryStrings(report.Targets, expectedTargets) { + return fmt.Errorf("%s: targets %v do not match required matrix %v", filePath, report.Targets, expectedTargets) + } + if report.CandidateTotal != len(candidates) || report.EligibleCandidates != len(candidates) { + return fmt.Errorf("%s: candidate totals are total=%d eligible=%d, want %d ledger matches", filePath, report.CandidateTotal, report.EligibleCandidates, len(candidates)) + } + if report.ShardCount <= 0 || report.ShardIndex < 0 || report.ShardIndex >= report.ShardCount { + return fmt.Errorf("%s: invalid shard %d/%d", filePath, report.ShardIndex, report.ShardCount) + } + if shardCount == 0 { + shardCount = report.ShardCount + } else if report.ShardCount != shardCount { + return fmt.Errorf("%s: shard_count %d does not match %d", filePath, report.ShardCount, shardCount) + } + if previous, ok := seenShards[report.ShardIndex]; ok { + return fmt.Errorf("duplicate discovery shard %d in %s and %s", report.ShardIndex, previous, filePath) + } + seenShards[report.ShardIndex] = filePath + if len(report.Results) != report.Selected { + return fmt.Errorf("%s: selected=%d but contains %d auditable results", filePath, report.Selected, len(report.Results)) + } + if report.Failed != 0 { + return fmt.Errorf("%s: discovery shard has %d failed candidates", filePath, report.Failed) + } + for _, result := range report.Results { + key := result.Module + "@" + result.Version + candidate, ok := expected[key] + if !ok { + return fmt.Errorf("%s: result %s is not a current ledger match", filePath, key) + } + if want := discoveryCandidateShard(candidate, report.ShardCount); want != report.ShardIndex { + return fmt.Errorf("%s: result %s belongs to shard %d/%d, not %d", filePath, key, want, report.ShardCount, report.ShardIndex) + } + if previous, ok := seenCandidates[key]; ok { + return fmt.Errorf("duplicate discovery result %s in %s and %s", key, previous, filePath) + } + if !equalDiscoveryStrings(result.DiscoveredAsmFiles, candidate.AsmFiles) { + return fmt.Errorf("%s: result %s assembly inventory %v does not match ledger %v", filePath, key, result.DiscoveredAsmFiles, candidate.AsmFiles) + } + if result.Status != discoveryStatusPassed && result.Status != discoveryStatusNotApplicable { + return fmt.Errorf("%s: result %s has non-passing status %q", filePath, key, result.Status) + } + seenCandidates[key] = filePath + } + } + if shardCount == 0 || len(seenShards) != shardCount { + return fmt.Errorf("found %d discovery shard reports, want exactly %d", len(seenShards), shardCount) + } + if len(seenCandidates) != len(candidates) { + var missing []string + for key := range expected { + if _, ok := seenCandidates[key]; !ok { + missing = append(missing, key) + } + } + sort.Strings(missing) + return fmt.Errorf("discovery reports cover %d/%d ledger matches; missing %v", len(seenCandidates), len(candidates), missing) + } + return nil +} + +func discoveryCorpusReportFiles(reportPath string) ([]string, error) { + info, err := os.Stat(reportPath) + if err != nil { + return nil, fmt.Errorf("stat discovery reports: %w", err) + } + if !info.IsDir() { + return []string{reportPath}, nil + } + var files []string + err = filepath.WalkDir(reportPath, func(name string, entry os.DirEntry, err error) error { + if err != nil { + return err + } + if !entry.IsDir() && strings.HasPrefix(entry.Name(), "shard-") && strings.HasSuffix(entry.Name(), ".json") { + files = append(files, name) + } + return nil + }) + if err != nil { + return nil, fmt.Errorf("list discovery reports: %w", err) + } + sort.Strings(files) + return files, nil +} + +func readDiscoveryCorpusReport(reportPath string) (discoveryCorpusReport, error) { + file, err := os.Open(reportPath) + if err != nil { + return discoveryCorpusReport{}, fmt.Errorf("open discovery report %s: %w", reportPath, err) + } + defer file.Close() + decoder := json.NewDecoder(file) + decoder.DisallowUnknownFields() + var report discoveryCorpusReport + if err := decoder.Decode(&report); err != nil { + return discoveryCorpusReport{}, fmt.Errorf("decode discovery report %s: %w", reportPath, err) + } + if err := ensureJSONEOF(decoder); err != nil { + return discoveryCorpusReport{}, fmt.Errorf("decode discovery report %s: %w", reportPath, err) + } + return report, nil +} + +func equalDiscoveryStrings(a, b []string) bool { + if len(a) != len(b) { + return false + } + for i := range a { + if a[i] != b[i] { + return false + } + } + return true +} + +func filterDiscoveryCandidatesForTargets(candidates []discoveryCandidate, targets []string) ([]discoveryCandidate, error) { + filtered := make([]discoveryCandidate, 0, len(candidates)) + for _, candidate := range candidates { + files, err := discoverymeta.FilterAssemblyFiles(candidate.AsmFiles, targets) + if err != nil { + return nil, err + } + if len(files) == 0 { + continue + } + candidate.AsmFiles = files + candidate.Architectures = discoverymeta.ArchitectureHints(files) + filtered = append(filtered, candidate) + } + return filtered, nil +} + +func discoveryPackagePatterns(candidate discoveryCandidate) []string { + return discoveryPackagePatternsForModule(candidate, candidate.Module) +} + +func discoveryPackagePatternsForModule(candidate discoveryCandidate, modulePath string) []string { + groups := discoveryPackageGroupsForModule(candidate, modulePath) + out := make([]string, 0, len(groups)) + for _, group := range groups { + out = append(out, group.Pattern) + } + return out +} + +func discoveryPackageGroupsForModule(candidate discoveryCandidate, modulePath string) []discoveryPackageGroup { + filesByPattern := make(map[string][]string) + for _, asmFile := range candidate.AsmFiles { + dir := path.Dir(asmFile) + pattern := modulePath + if dir != "." { + pattern += "/" + dir + } + filesByPattern[pattern] = append(filesByPattern[pattern], asmFile) + } + patterns := make([]string, 0, len(filesByPattern)) + for pattern := range filesByPattern { + patterns = append(patterns, pattern) + } + sort.Strings(patterns) + groups := make([]discoveryPackageGroup, 0, len(patterns)) + for _, pattern := range patterns { + groups = append(groups, discoveryPackageGroup{ + Pattern: pattern, + AsmFiles: uniqueSortedDiscoveryStrings(filesByPattern[pattern]), + }) + } + return groups +} + +func makeDiscoveryExecutionPlan(candidate discoveryCandidate, declaredModule string) (discoveryExecutionPlan, error) { + if declaredModule == "" { + declaredModule = candidate.Module + } + if strings.TrimSpace(declaredModule) != declaredModule || strings.ContainsAny(declaredModule, "\r\n\t ") { + return discoveryExecutionPlan{}, fmt.Errorf("invalid declared module path %q", declaredModule) + } + goMod := fmt.Sprintf("module plan9asm.local/discovery\n\ngo 1.27\n\nrequire %s %s\n", declaredModule, candidate.Version) + if declaredModule != candidate.Module { + goMod += fmt.Sprintf("\nreplace %s => %s %s\n", declaredModule, candidate.Module, candidate.Version) + } + return discoveryExecutionPlan{ + ModulePath: declaredModule, + Patterns: discoveryPackagePatternsForModule(candidate, declaredModule), + GoMod: goMod, + }, nil +} + +func parseDeclaredModulePath(contents []byte) (string, error) { + scanner := bufio.NewScanner(bytes.NewReader(contents)) + for scanner.Scan() { + line := strings.TrimSpace(scanner.Text()) + if !strings.HasPrefix(line, "module") || (len(line) > len("module") && line[len("module")] != ' ' && line[len("module")] != '\t') { + continue + } + rest := strings.TrimSpace(strings.TrimPrefix(line, "module")) + if rest == "" { + return "", fmt.Errorf("empty module directive") + } + var modulePath string + if rest[0] == '"' || rest[0] == '`' { + if _, err := fmt.Sscanf(rest, "%q", &modulePath); err != nil { + return "", fmt.Errorf("parse module directive %q: %w", line, err) + } + } else { + modulePath = strings.Fields(rest)[0] + } + if modulePath == "" || strings.ContainsAny(modulePath, "\r\n\t ") { + return "", fmt.Errorf("invalid module directive path %q", modulePath) + } + return modulePath, nil + } + if err := scanner.Err(); err != nil { + return "", err + } + return "", fmt.Errorf("go.mod has no module directive") +} + +func applicableDiscoveryAssemblyFiles(candidate discoveryCandidate, moduleDir string, targets []string) ([]string, error) { + configs, err := discoveryBuildConfigurations(candidate, moduleDir, targets) + if err != nil { + return nil, err + } + var applicable []string + for _, config := range configs { + applicable = append(applicable, config.AsmFiles...) + } + sort.Strings(applicable) + return applicable, nil +} + +func discoveryBuildConfigurations(candidate discoveryCandidate, moduleDir string, targets []string) ([]discoveryBuildConfiguration, error) { + return discoveryBuildConfigurationsWithEvidence(candidate, moduleDir, targets, nil) +} + +func discoveryBuildConfigurationsWithEvidence(candidate discoveryCandidate, moduleDir string, targets []string, sourceNotApplicable *[]discoverySourceNotApplicableItem) ([]discoveryBuildConfiguration, error) { + if moduleDir == "" { + return nil, fmt.Errorf("%s: downloaded module has no directory", candidate.exactKey()) + } + contexts := make([]build.Context, 0, len(targets)) + for _, target := range targets { + goos, goarch, ok := strings.Cut(target, "/") + if !ok || goos == "" || goarch == "" { + return nil, fmt.Errorf("invalid discovery target %q", target) + } + ctx := build.Default + ctx.GOOS = goos + ctx.GOARCH = goarch + ctx.Compiler = "gc" + ctx.CgoEnabled = false + contexts = append(contexts, ctx) + } + + goFilesByDir := make(map[string][]string) + invalidGoFilesByDir := make(map[string][]string) + constraintTagsByFile := make(map[string][]string) + configsByTargetAndTags := make(map[string]*discoveryBuildConfiguration) + for _, asmFile := range candidate.AsmFiles { + dirRel := path.Dir(asmFile) + if discoveryDirIsIgnored(dirRel) { + continue + } + nested, err := discoveryDirIsNestedModule(moduleDir, dirRel) + if err != nil { + return nil, err + } + if nested { + continue + } + dir := filepath.Join(moduleDir, filepath.FromSlash(dirRel)) + goFiles, ok := goFilesByDir[dir] + if !ok { + entries, err := os.ReadDir(dir) + if err != nil { + return nil, fmt.Errorf("read assembly package directory %s: %w", dir, err) + } + for _, entry := range entries { + name := entry.Name() + if entry.IsDir() || !strings.HasSuffix(name, ".go") || strings.HasSuffix(name, "_test.go") || strings.HasPrefix(name, ".") || strings.HasPrefix(name, "_") { + continue + } + if _, parseErr := parser.ParseFile(token.NewFileSet(), filepath.Join(dir, name), nil, parser.PackageClauseOnly); parseErr != nil { + invalidGoFilesByDir[dir] = append(invalidGoFilesByDir[dir], name) + continue + } + goFiles = append(goFiles, name) + } + goFilesByDir[dir] = goFiles + } + if len(goFiles) == 0 { + if sourceNotApplicable != nil { + invalid := uniqueSortedDiscoveryStrings(invalidGoFilesByDir[dir]) + reason := "assembly directory contains no non-test Go source accepted by Go 1.27" + if len(invalid) != 0 { + reason += "; invalid .go files: " + strings.Join(invalid, ", ") + } + *sourceNotApplicable = append(*sourceNotApplicable, discoverySourceNotApplicableItem{ + AsmFile: asmFile, + Targets: uniqueSortedDiscoveryStrings(targets), + Kind: discoverySourceNotApplicableNoGoPackage, + Reason: reason, + }) + } + continue + } + fileNames := append([]string(nil), goFiles...) + fileNames = append(fileNames, path.Base(asmFile)) + var customTags []string + for _, fileName := range fileNames { + fullPath := filepath.Join(dir, fileName) + tags, ok := constraintTagsByFile[fullPath] + if !ok { + var err error + tags, err = discoveryConstraintTags(fullPath) + if err != nil { + return nil, err + } + constraintTagsByFile[fullPath] = tags + } + customTags = append(customTags, tags...) + } + customTags = uniqueDiscoveryCustomTags(customTags, contexts) + if len(customTags) > 16 { + return nil, fmt.Errorf("%s: assembly package %s has %d custom build tags; refusing to leave the satisfiability search incomplete", candidate.exactKey(), dirRel, len(customTags)) + } + type contextMatch struct { + context build.Context + target string + buildTags []string + } + matches := make([]contextMatch, 0, len(contexts)) + for i := range contexts { + target := contexts[i].GOOS + "/" + contexts[i].GOARCH + buildTags, ok, err := findDiscoveryBuildTags(contexts[i], dir, path.Base(asmFile), goFiles, customTags) + if err != nil { + return nil, fmt.Errorf("classify assembly %s: %w", asmFile, err) + } + if !ok { + continue + } + matches = append(matches, contextMatch{context: contexts[i], target: target, buildTags: buildTags}) + } + matchedContexts := make([]build.Context, 0, len(matches)) + for _, match := range matches { + matchedContexts = append(matchedContexts, match.context) + } + sourceTargets, restrictBySource, reason, err := inferUnsuffixedAssemblyTargetsDetailed(filepath.Join(moduleDir, filepath.FromSlash(asmFile)), matchedContexts) + if err != nil { + return nil, fmt.Errorf("classify assembly source %s: %w", asmFile, err) + } + if reason != "" && sourceNotApplicable != nil { + var sourceTargetNames []string + for _, match := range matches { + sourceTargetNames = append(sourceTargetNames, match.target) + } + *sourceNotApplicable = append(*sourceNotApplicable, discoverySourceNotApplicableItem{ + AsmFile: asmFile, + Targets: uniqueSortedDiscoveryStrings(sourceTargetNames), + Kind: discoverySourceNotApplicableGoAssembler, + Reason: reason, + }) + } + for _, match := range matches { + if restrictBySource && !sourceTargets[match.target] { + continue + } + key := match.target + "\x00" + strings.Join(match.buildTags, ",") + config := configsByTargetAndTags[key] + if config == nil { + config = &discoveryBuildConfiguration{ + BuildTags: append([]string(nil), match.buildTags...), + Targets: []string{match.target}, + } + configsByTargetAndTags[key] = config + } + config.AsmFiles = append(config.AsmFiles, asmFile) + } + } + // Targets can share one translator invocation only when both their build + // tags and exact source-inferred assembly allowlist are identical. + configsByShape := make(map[string]*discoveryBuildConfiguration) + for _, config := range configsByTargetAndTags { + config.AsmFiles = uniqueSortedDiscoveryStrings(config.AsmFiles) + shape := strings.Join(config.BuildTags, ",") + "\x00" + strings.Join(config.AsmFiles, "\x00") + group := configsByShape[shape] + if group == nil { + group = &discoveryBuildConfiguration{ + BuildTags: append([]string(nil), config.BuildTags...), + AsmFiles: append([]string(nil), config.AsmFiles...), + } + configsByShape[shape] = group + } + group.Targets = append(group.Targets, config.Targets...) + } + keys := make([]string, 0, len(configsByShape)) + for key := range configsByShape { + keys = append(keys, key) + } + sort.Strings(keys) + configs := make([]discoveryBuildConfiguration, 0, len(keys)) + for _, key := range keys { + config := configsByShape[key] + config.Targets = uniqueSortedDiscoveryStrings(config.Targets) + configs = append(configs, *config) + } + return configs, nil +} + +// inferUnsuffixedAssemblyTargets adds a source-level check only when Go's +// filename convention does not already identify an architecture. Go itself +// selects files by name and build tags; external packages sometimes omit both +// while containing unmistakably architecture-specific assembly. Asking the +// same Go assembler that will build the package prevents such x86 sources from +// being sent to ARM or Wasm translators without maintaining a second opcode +// taxonomy here. +func inferUnsuffixedAssemblyTargets(filePath string, contexts []build.Context) (map[string]bool, bool, error) { + eligible, restrict, _, err := inferUnsuffixedAssemblyTargetsDetailed(filePath, contexts) + return eligible, restrict, err +} + +func inferUnsuffixedAssemblyTargetsDetailed(filePath string, contexts []build.Context) (map[string]bool, bool, string, error) { + if explicitAssemblyFilenameArchitecture(path.Base(filePath)) != "" { + return nil, false, "", nil + } + eligible := make(map[string]bool, len(contexts)) + probed := make(map[string]struct { + accepted bool + conclusive bool + }) + acceptedAny := false + conclusiveAny := false + for _, ctx := range contexts { + key := ctx.GOOS + "/" + ctx.GOARCH + result, ok := probed[key] + if !ok { + accepted, conclusive := probeAssemblySourceForTarget(filePath, ctx.GOOS, ctx.GOARCH) + result = struct { + accepted bool + conclusive bool + }{accepted: accepted, conclusive: conclusive} + probed[key] = result + } + if result.accepted || !result.conclusive { + eligible[key] = true + } + acceptedAny = acceptedAny || result.accepted + conclusiveAny = conclusiveAny || result.conclusive + } + if !acceptedAny && conclusiveAny && len(eligible) == 0 { + // The source is a fixture, generated artifact, or assembly for a target + // outside this repository's supported matrix. The current Go assembler + // supplies stronger applicability evidence than an opcode guess: keep an + // explicit empty allowlist instead of failing translation or silently + // treating it as cross-architecture source. + var rejectedTargets []string + for target := range probed { + rejectedTargets = append(rejectedTargets, target) + } + sort.Strings(rejectedTargets) + return eligible, true, fmt.Sprintf("current Go assembler rejected unsuffixed source for every selected target: %s", strings.Join(rejectedTargets, ", ")), nil + } + if !conclusiveAny { + // Usually a generated go_asm.h (or another build-generated include) was + // unavailable. Keep every target visible instead of silently excluding it. + return nil, false, "", nil + } + return eligible, true, "", nil +} + +func explicitAssemblyFilenameArchitecture(name string) string { + base := strings.TrimSuffix(name, filepath.Ext(name)) + for _, arch := range []string{ + "386", "amd64", "amd64p32", "arm", "arm64", "armbe", "arm64be", + "loong64", "mips", "mipsle", "mips64", "mips64le", "mips64p32", + "mips64p32le", "ppc", "ppc64", "ppc64le", "riscv", "riscv64", + "s390", "s390x", "sparc", "sparc64", "wasm", + } { + if strings.HasSuffix(base, "_"+arch) { + return arch + } + } + return "" +} + +func probeAssemblySourceForTarget(filePath, goos, goarch string) (accepted, conclusive bool) { + run := func(extraInclude string) ([]byte, error) { + args := []string{"tool", "asm"} + if extraInclude != "" { + args = append(args, "-I", extraInclude) + } + args = append(args, "-I", filepath.Dir(filePath), "-I", filepath.Join(runtime.GOROOT(), "pkg", "include"), "-o", os.DevNull, filePath) + cmd := exec.Command("go", args...) + cmd.Env = replaceEnv(os.Environ(), map[string]string{ + "GOOS": goos, + "GOARCH": goarch, + "GOTOOLCHAIN": "local", + "GOWORK": "off", + }) + return cmd.CombinedOutput() + } + output, err := run("") + if err == nil { + return true, true + } + message := strings.ToLower(string(output)) + if missingGoAsmHeader(message) { + stubDir, stubErr := os.MkdirTemp("", "plan9asm-go-asm-header-") + if stubErr != nil { + return false, false + } + defer os.RemoveAll(stubDir) + if stubErr := os.WriteFile(filepath.Join(stubDir, "go_asm.h"), nil, 0o600); stubErr != nil { + return false, false + } + output, err = run(stubDir) + if err == nil { + return true, true + } + message = strings.ToLower(string(output)) + } + for _, fragment := range []string{"no such file or directory", "cannot find", "could not find"} { + if strings.Contains(message, fragment) { + return false, false + } + } + return false, true +} + +func missingGoAsmHeader(message string) bool { + message = strings.ToLower(message) + if !strings.Contains(message, "go_asm.h") { + return false + } + for _, fragment := range []string{"no such file or directory", "cannot find", "could not find"} { + if strings.Contains(message, fragment) { + return true + } + } + return false +} + +func discoveryConstraintTags(filePath string) ([]string, error) { + if strings.HasSuffix(filePath, ".go") { + return discoveryGoConstraintTags(filePath) + } + file, err := os.Open(filePath) + if err != nil { + return nil, fmt.Errorf("open build constraints %s: %w", filePath, err) + } + defer file.Close() + set := make(map[string]bool) + scanner := bufio.NewScanner(file) + scanner.Buffer(make([]byte, 64<<10), 4<<20) + inBlockComment := false + for scanner.Scan() { + line := strings.TrimSpace(scanner.Text()) + if inBlockComment { + if strings.Contains(line, "*/") { + inBlockComment = false + } + continue + } + if line == "" { + continue + } + if strings.HasPrefix(line, "/*") { + inBlockComment = !strings.Contains(line, "*/") + continue + } + if !strings.HasPrefix(line, "//") { + break + } + if !strings.HasPrefix(line, "//go:build ") && !strings.HasPrefix(line, "// +build ") { + continue + } + expr, err := constraint.Parse(line) + if err != nil { + return nil, fmt.Errorf("parse build constraint %s: %w", filePath, err) + } + collectDiscoveryConstraintTags(expr, set) + } + if err := scanner.Err(); err != nil { + return nil, fmt.Errorf("read build constraints %s: %w", filePath, err) + } + tags := make([]string, 0, len(set)) + for tag := range set { + tags = append(tags, tag) + } + sort.Strings(tags) + return tags, nil +} + +func discoveryGoConstraintTags(filePath string) ([]string, error) { + parsed, err := parser.ParseFile(token.NewFileSet(), filePath, nil, parser.PackageClauseOnly|parser.ParseComments) + if err != nil { + return nil, fmt.Errorf("parse Go build constraints %s: %w", filePath, err) + } + set := make(map[string]bool) + for _, group := range parsed.Comments { + for _, comment := range group.List { + line := strings.TrimSpace(comment.Text) + if !strings.HasPrefix(line, "//go:build ") && !strings.HasPrefix(line, "// +build ") { + continue + } + expr, err := constraint.Parse(line) + if err != nil { + return nil, fmt.Errorf("parse build constraint %s: %w", filePath, err) + } + collectDiscoveryConstraintTags(expr, set) + } + } + tags := make([]string, 0, len(set)) + for tag := range set { + tags = append(tags, tag) + } + sort.Strings(tags) + return tags, nil +} + +func collectDiscoveryConstraintTags(expr constraint.Expr, tags map[string]bool) { + switch expr := expr.(type) { + case *constraint.TagExpr: + tags[expr.Tag] = true + case *constraint.NotExpr: + collectDiscoveryConstraintTags(expr.X, tags) + case *constraint.AndExpr: + collectDiscoveryConstraintTags(expr.X, tags) + collectDiscoveryConstraintTags(expr.Y, tags) + case *constraint.OrExpr: + collectDiscoveryConstraintTags(expr.X, tags) + collectDiscoveryConstraintTags(expr.Y, tags) + } +} + +func uniqueDiscoveryCustomTags(tags []string, contexts []build.Context) []string { + reserved := map[string]bool{ + // "ignore" conventionally marks generator inputs and other files that + // are not part of any build. Enabling it globally also selects Go's own + // ignored generator programs and produces packages that cannot compile. + "ignore": true, + "aix": true, "android": true, "darwin": true, "dragonfly": true, + "freebsd": true, "hurd": true, "illumos": true, "ios": true, + "js": true, "linux": true, "netbsd": true, "openbsd": true, + "plan9": true, "solaris": true, "unix": true, "wasip1": true, + "windows": true, "zos": true, + "386": true, "amd64": true, "amd64p32": true, "arm": true, + "armbe": true, "arm64": true, "arm64be": true, "loong64": true, + "mips": true, "mipsle": true, "mips64": true, "mips64le": true, + "mips64p32": true, "mips64p32le": true, "ppc": true, "ppc64": true, + "ppc64le": true, "riscv": true, "riscv64": true, "s390": true, + "s390x": true, "sparc": true, "sparc64": true, "wasm": true, + "cgo": true, "gc": true, "gccgo": true, + } + for _, ctx := range contexts { + reserved[ctx.GOOS] = true + reserved[ctx.GOARCH] = true + reserved[ctx.Compiler] = true + for _, tag := range ctx.ReleaseTags { + reserved[tag] = true + } + for _, tag := range ctx.ToolTags { + reserved[tag] = true + } + } + set := make(map[string]bool) + for _, tag := range tags { + if tag != "" && !reserved[tag] { + set[tag] = true + } + } + out := make([]string, 0, len(set)) + for tag := range set { + out = append(out, tag) + } + sort.Strings(out) + return out +} + +func findDiscoveryBuildTags(ctx build.Context, dir, asmFile string, goFiles, customTags []string) ([]string, bool, error) { + assignments := 1 << len(customTags) + for wantedCount := 0; wantedCount <= len(customTags); wantedCount++ { + for mask := 0; mask < assignments; mask++ { + if bits.OnesCount(uint(mask)) != wantedCount { + continue + } + buildTags := make([]string, 0, wantedCount) + for i, tag := range customTags { + if mask&(1<= cfg.ShardCount { + return fmt.Errorf("invalid discovery shard %d/%d", cfg.ShardIndex, cfg.ShardCount) + } + if cfg.CandidateTimeout <= 0 { + return fmt.Errorf("candidate timeout must be positive") + } + allCandidates, err := loadDiscoveryCandidates(cfg.LedgerPath) + if err != nil { + return err + } + candidates := allCandidates + if cfg.FilterTargets { + candidates, err = filterDiscoveryCandidatesForTargets(allCandidates, cfg.Targets) + if err != nil { + return err + } + } + selected := selectDiscoveryShard(candidates, cfg.ShardIndex, cfg.ShardCount) + report := discoveryCorpusReport{ + SchemaVersion: discoveryReportSchema, + Targets: append([]string(nil), cfg.Targets...), + TargetFiltered: cfg.FilterTargets, + ShardIndex: cfg.ShardIndex, + ShardCount: cfg.ShardCount, + CandidateTotal: len(allCandidates), + EligibleCandidates: len(candidates), + Selected: len(selected), + Results: make([]discoveryCorpusResult, 0, len(selected)), + } + tmpRoot, err := os.MkdirTemp("", fmt.Sprintf("plan9asm-discovery-%02d-", cfg.ShardIndex)) + if err != nil { + return err + } + defer os.RemoveAll(tmpRoot) + for i, candidate := range selected { + fmt.Printf("[%d/%d] %s\n", i+1, len(selected), candidate.exactKey()) + result := discoveryCorpusResult{ + Module: candidate.Module, + Version: candidate.Version, + DiscoveredAsmFiles: append([]string(nil), candidate.AsmFiles...), + } + candidateDir := filepath.Join(tmpRoot, fmt.Sprintf("candidate-%04d", i)) + matrix, patterns, buildConfigurations, runErr := runDiscoveryCandidate(cfg, candidate, candidateDir) + applicableAsmFiles := discoveryConfigurationAsmFiles(buildConfigurations) + result.Patterns = patterns + result.ApplicableAsmFiles = applicableAsmFiles + result.BuildConfigurations = buildConfigurations + result.NotApplicableItems = append(result.NotApplicableItems, matrix.NotApplicableItems...) + result.SourceNotApplicableItems = append(result.SourceNotApplicableItems, matrix.SourceNotApplicableItems...) + if runErr != nil { + result.Status = discoveryStatusFailed + result.Error = runErr.Error() + report.Failed++ + fmt.Fprintf(os.Stderr, "FAIL %s: %v\n", candidate.exactKey(), runErr) + } else if len(applicableAsmFiles) == 0 || matrix.Success == 0 { + result.Status = discoveryStatusNotApplicable + if len(applicableAsmFiles) == 0 { + result.NotApplicableReason = "no discovered assembly file belongs to a buildable Go package on the supported target matrix" + } else { + result.NotApplicableReason = "every target-selected assembly source has evidence-backed current-Go source or ABI incompatibility" + } + result.NotApplicableTranslations = matrix.NotApplicable + report.NotApplicableTranslations += matrix.NotApplicable + report.NotApplicable++ + fmt.Printf("NOT_APPLICABLE %s: discovered_files=%d\n", candidate.exactKey(), len(candidate.AsmFiles)) + } else { + result.Status = discoveryStatusPassed + result.Translations = matrix.Success + result.NotApplicableTranslations = matrix.NotApplicable + report.Passed++ + report.Translations += matrix.Success + report.NotApplicableTranslations += matrix.NotApplicable + fmt.Printf("PASS %s: applicable_files=%d translations=%d not_applicable_translations=%d targets=%d\n", candidate.exactKey(), len(applicableAsmFiles), matrix.Success, matrix.NotApplicable, matrix.TotalTargets) + } + report.Results = append(report.Results, result) + } + if err := validateDiscoveryCorpusAccounting(report); err != nil { + return err + } + if err := writeDiscoveryCorpusReport(cfg.ReportPath, report); err != nil { + return err + } + if report.Failed != 0 { + return fmt.Errorf("discovery shard %d/%d failed: passed=%d failed=%d selected=%d", cfg.ShardIndex, cfg.ShardCount, report.Passed, report.Failed, report.Selected) + } + fmt.Printf("discovery shard %d/%d passed: applicable=%d not_applicable=%d translations=%d not_applicable_translations=%d\n", cfg.ShardIndex, cfg.ShardCount, report.Passed, report.NotApplicable, report.Translations, report.NotApplicableTranslations) + return nil +} + +func validateDiscoveryCorpusAccounting(report discoveryCorpusReport) error { + if report.Selected != report.Passed+report.Failed+report.NotApplicable { + return fmt.Errorf("discovery report accounting mismatch: selected=%d passed=%d failed=%d not_applicable=%d", report.Selected, report.Passed, report.Failed, report.NotApplicable) + } + if len(report.Results) != 0 && len(report.Results) != report.Selected { + return fmt.Errorf("discovery report result count mismatch: selected=%d results=%d", report.Selected, len(report.Results)) + } + var passed, failed, notApplicable, translations, notApplicableTranslations int + for _, result := range report.Results { + switch result.Status { + case discoveryStatusPassed: + passed++ + case discoveryStatusFailed: + failed++ + case discoveryStatusNotApplicable: + notApplicable++ + default: + return fmt.Errorf("%s@%s: invalid discovery result status %q", result.Module, result.Version, result.Status) + } + translations += result.Translations + notApplicableTranslations += result.NotApplicableTranslations + if err := validateDiscoverySourceNotApplicableEvidence(result); err != nil { + return fmt.Errorf("%s@%s: %w", result.Module, result.Version, err) + } + } + if len(report.Results) != 0 && (passed != report.Passed || failed != report.Failed || notApplicable != report.NotApplicable) { + return fmt.Errorf("discovery report result status counts are passed=%d failed=%d not_applicable=%d, summary is passed=%d failed=%d not_applicable=%d", passed, failed, notApplicable, report.Passed, report.Failed, report.NotApplicable) + } + if len(report.Results) != 0 && (translations != report.Translations || notApplicableTranslations != report.NotApplicableTranslations) { + return fmt.Errorf("discovery report result translation counts are translations=%d not_applicable=%d, summary is translations=%d not_applicable=%d", translations, notApplicableTranslations, report.Translations, report.NotApplicableTranslations) + } + return nil +} + +func validateDiscoverySourceNotApplicableEvidence(result discoveryCorpusResult) error { + discovered := make(map[string]bool, len(result.DiscoveredAsmFiles)) + for _, asmFile := range result.DiscoveredAsmFiles { + discovered[asmFile] = true + } + allowedKinds := map[string]bool{ + discoverySourceNotApplicableGoAssembler: true, + discoverySourceNotApplicableNoGoPackage: true, + discoverySourceNotApplicableGoBuild: true, + discoverySourceNotApplicableAsmDecl: true, + } + for _, item := range result.SourceNotApplicableItems { + files := append([]string(nil), item.AsmFiles...) + if item.AsmFile != "" { + files = append(files, item.AsmFile) + } + files = uniqueSortedDiscoveryStrings(files) + valid := allowedKinds[item.Kind] && len(files) != 0 && len(item.Targets) != 0 && item.Reason != "" + for _, asmFile := range files { + valid = valid && discovered[asmFile] + } + for _, target := range item.Targets { + goos, goarch, ok := strings.Cut(target, "/") + valid = valid && ok && goos != "" && goarch != "" + } + if !valid { + return fmt.Errorf("invalid source not-applicable evidence: kind=%q files=%v targets=%v", item.Kind, files, item.Targets) + } + } + return nil +} + +func discoveryConfigurationAsmFiles(configs []discoveryBuildConfiguration) []string { + var files []string + for _, config := range configs { + files = append(files, config.AsmFiles...) + } + return uniqueSortedDiscoveryStrings(files) +} + +func runDiscoveryCandidate(cfg discoveryCorpusConfig, candidate discoveryCandidate, workDir string) (matrixReport, []string, []discoveryBuildConfiguration, error) { + if err := os.MkdirAll(workDir, 0755); err != nil { + return matrixReport{}, nil, nil, err + } + if err := os.WriteFile(filepath.Join(workDir, "go.mod"), []byte("module plan9asm.local/discovery\n\ngo 1.27\n"), 0644); err != nil { + return matrixReport{}, nil, nil, fmt.Errorf("write temporary go.mod: %w", err) + } + env := discoveryCommandEnvironment(os.Environ()) + ctx, cancel := context.WithTimeout(context.Background(), cfg.CandidateTimeout) + defer cancel() + downloadJSON, commandErr := runCapturedCommandOutput(ctx, workDir, env, "go", "mod", "download", "-json", candidate.Module+"@"+candidate.Version) + download, err := resolveModuleDownload(downloadJSON, commandErr, filepath.Join(workDir, "module-source")) + if err != nil { + return matrixReport{}, nil, nil, fmt.Errorf("download module: %w", err) + } + var sourceNotApplicable []discoverySourceNotApplicableItem + buildConfigurations, err := discoveryBuildConfigurationsWithEvidence(candidate, download.Dir, cfg.Targets, &sourceNotApplicable) + if err != nil { + return matrixReport{}, nil, nil, fmt.Errorf("classify discovered assembly: %w", err) + } + if len(buildConfigurations) == 0 { + return matrixReport{SourceNotApplicableItems: sourceNotApplicable}, nil, buildConfigurations, nil + } + declaredModule := candidate.Module + if download.GoMod != "" { + goModContents, err := os.ReadFile(download.GoMod) + if err != nil { + return matrixReport{}, nil, buildConfigurations, fmt.Errorf("read downloaded go.mod: %w", err) + } + declaredModule, err = parseDeclaredModulePath(goModContents) + if err != nil { + return matrixReport{}, nil, buildConfigurations, fmt.Errorf("read declared module path: %w", err) + } + } + patternSet := make(map[string]bool) + aggregate := matrixReport{SourceNotApplicableItems: sourceNotApplicable} + runTargets := make(map[string]bool) + executedBuildConfigurations := make([]discoveryBuildConfiguration, 0, len(buildConfigurations)) + invocationIndex := 0 + for _, buildConfiguration := range buildConfigurations { + applicableCandidate := candidate + applicableCandidate.AsmFiles = buildConfiguration.AsmFiles + plan, err := makeDiscoveryExecutionPlan(applicableCandidate, declaredModule) + if err != nil { + return matrixReport{}, nil, buildConfigurations, err + } + if err := os.WriteFile(filepath.Join(workDir, "go.mod"), []byte(plan.GoMod), 0644); err != nil { + return matrixReport{}, nil, buildConfigurations, fmt.Errorf("write exact module mapping: %w", err) + } + packageGroups := discoveryPackageGroupsForModule(applicableCandidate, plan.ModulePath) + for _, target := range buildConfiguration.Targets { + var targetAsmFiles, targetPatterns []string + for _, group := range packageGroups { + if err := runDiscoveryGoBuild(ctx, workDir, env, target, buildConfiguration.BuildTags, group.Pattern); err != nil { + if isDiscoveryGoBuildInfrastructureFailure(err.Error()) { + return matrixReport{}, sortedDiscoverySet(patternSet), executedBuildConfigurations, fmt.Errorf("verify current Go package %s for %s with build tags %v: %w", group.Pattern, target, buildConfiguration.BuildTags, err) + } + aggregate.SourceNotApplicableItems = append(aggregate.SourceNotApplicableItems, discoverySourceNotApplicableItem{ + AsmFiles: append([]string(nil), group.AsmFiles...), + Targets: []string{target}, + Kind: discoverySourceNotApplicableGoBuild, + Reason: limitDiscoveryEvidence(err.Error(), 8192), + }) + continue + } + validAsmFiles := append([]string(nil), group.AsmFiles...) + if err := runDiscoveryAsmDecl(ctx, workDir, env, target, buildConfiguration.BuildTags, []string{group.Pattern}); err != nil { + rejected := discoveryAsmDeclRejectedFiles(validAsmFiles, err.Error()) + if len(rejected) == 0 { + rejected = append(rejected, validAsmFiles...) + } + aggregate.SourceNotApplicableItems = append(aggregate.SourceNotApplicableItems, discoverySourceNotApplicableItem{ + AsmFiles: append([]string(nil), rejected...), + Targets: []string{target}, + Kind: discoverySourceNotApplicableAsmDecl, + Reason: limitDiscoveryEvidence(err.Error(), 8192), + }) + validAsmFiles = subtractDiscoveryStrings(validAsmFiles, rejected) + } + if len(validAsmFiles) == 0 { + continue + } + targetAsmFiles = append(targetAsmFiles, validAsmFiles...) + targetPatterns = append(targetPatterns, group.Pattern) + } + if len(targetAsmFiles) == 0 { + continue + } + targetAsmFiles = uniqueSortedDiscoveryStrings(targetAsmFiles) + targetPatterns = uniqueSortedDiscoveryStrings(targetPatterns) + for _, pattern := range targetPatterns { + patternSet[pattern] = true + } + targetCandidate := candidate + targetCandidate.AsmFiles = targetAsmFiles + executed := discoveryBuildConfiguration{ + BuildTags: append([]string(nil), buildConfiguration.BuildTags...), + Targets: []string{target}, + AsmFiles: append([]string(nil), targetAsmFiles...), + } + executedBuildConfigurations = append(executedBuildConfigurations, executed) + reportPath := filepath.Join(workDir, fmt.Sprintf("matrix-report-%04d.json", invocationIndex)) + invocation := makeTranslatorInvocationForTargetsAndTags( + workDir, + plan.ModulePath, + targetPatterns, + buildConfiguration.BuildTags, + []string{target}, + targetAsmFiles, + filepath.Join(workDir, "out", fmt.Sprintf("config-%04d", invocationIndex)), + cfg.RepoRoot, + cfg.LLC, + reportPath, + ) + invocationIndex++ + if err := runCapturedCommand(ctx, invocation.Dir, env, cfg.Translator, invocation.Args...); err != nil { + return matrixReport{}, sortedDiscoverySet(patternSet), executedBuildConfigurations, fmt.Errorf("translate and compile target %s with build tags %v: %w", target, buildConfiguration.BuildTags, err) + } + report, err := loadReport(reportPath) + if err != nil { + return matrixReport{}, sortedDiscoverySet(patternSet), executedBuildConfigurations, err + } + if err := validateDiscoveryReport([]string{target}, targetCandidate, report); err != nil { + return matrixReport{}, sortedDiscoverySet(patternSet), executedBuildConfigurations, fmt.Errorf("target %s build tags %v: %w", target, buildConfiguration.BuildTags, err) + } + runTargets[target] = true + aggregate.TotalAsm += report.TotalAsm + aggregate.Success += report.Success + aggregate.NotApplicable += report.NotApplicable + aggregate.Failed += report.Failed + aggregate.NotApplicableItems = append(aggregate.NotApplicableItems, collectMatrixNotApplicableItems(report)...) + } + } + aggregate.TotalTargets = len(runTargets) + return aggregate, sortedDiscoverySet(patternSet), executedBuildConfigurations, nil +} + +func discoveryCommandEnvironment(base []string) []string { + return replaceEnv(base, map[string]string{ + "CGO_ENABLED": "0", + "GOFLAGS": "-mod=mod", + "GOTOOLCHAIN": "local", + "GOWORK": "off", + }) +} + +func resolveModuleDownload(downloadJSON []byte, commandErr error, extractDir string) (moduleDownloadInfo, error) { + var download moduleDownloadInfo + if err := json.Unmarshal(downloadJSON, &download); err != nil { + if commandErr != nil { + return moduleDownloadInfo{}, commandErr + } + return moduleDownloadInfo{}, fmt.Errorf("decode module download metadata: %w", err) + } + if download.Dir != "" { + if info, err := os.Stat(download.Dir); err == nil && info.IsDir() { + return download, nil + } + } + if download.Zip != "" { + if err := extractModuleZip(download.Zip, extractDir, download.Path, download.Version); err == nil { + download.Dir = extractDir + if download.GoMod == "" { + download.GoMod = filepath.Join(extractDir, "go.mod") + } + return download, nil + } else if commandErr == nil && download.Error == "" { + return moduleDownloadInfo{}, fmt.Errorf("extract cached module ZIP: %w", err) + } + } + if download.Error != "" { + return moduleDownloadInfo{}, errors.New(download.Error) + } + if commandErr != nil { + return moduleDownloadInfo{}, commandErr + } + return moduleDownloadInfo{}, errors.New("module download metadata contains neither a directory nor a usable ZIP") +} + +func extractModuleZip(zipPath, destination, modulePath, version string) error { + if err := module.Check(modulePath, version); err != nil { + return fmt.Errorf("validate module version: %w", err) + } + // Module cache file names escape uppercase letters (for example, Upper + // becomes !upper), but paths inside a module ZIP retain the canonical, + // unescaped module path and version. + prefix := modulePath + "@" + version + "/" + reader, err := zip.OpenReader(zipPath) + if err != nil { + return err + } + defer reader.Close() + if err := os.MkdirAll(destination, 0755); err != nil { + return err + } + for _, file := range reader.File { + name := filepath.ToSlash(file.Name) + if !strings.HasPrefix(name, prefix) { + return fmt.Errorf("module ZIP entry %q is outside expected prefix %q", file.Name, prefix) + } + relative := strings.TrimPrefix(name, prefix) + if relative == "" { + continue + } + clean := path.Clean(relative) + if clean == "." || clean == ".." || strings.HasPrefix(clean, "../") || path.IsAbs(clean) { + return fmt.Errorf("unsafe module ZIP path %q", file.Name) + } + target := filepath.Join(destination, filepath.FromSlash(clean)) + rel, err := filepath.Rel(destination, target) + if err != nil || rel == ".." || strings.HasPrefix(rel, ".."+string(filepath.Separator)) { + return fmt.Errorf("unsafe module ZIP path %q", file.Name) + } + if file.FileInfo().IsDir() { + if err := os.MkdirAll(target, 0755); err != nil { + return err + } + continue + } + if !file.Mode().IsRegular() { + return fmt.Errorf("unsupported non-regular module ZIP entry %q", file.Name) + } + if err := os.MkdirAll(filepath.Dir(target), 0755); err != nil { + return err + } + source, err := file.Open() + if err != nil { + return err + } + output, err := os.OpenFile(target, os.O_WRONLY|os.O_CREATE|os.O_EXCL, 0644) + if err == nil { + _, err = io.Copy(output, source) + } + closeOutputErr := error(nil) + if output != nil { + closeOutputErr = output.Close() + } + closeSourceErr := source.Close() + if err != nil { + return err + } + if closeOutputErr != nil { + return closeOutputErr + } + if closeSourceErr != nil { + return closeSourceErr + } + } + return nil +} + +func runDiscoveryGoBuild(ctx context.Context, dir string, env []string, target string, buildTags []string, pattern string) error { + goos, goarch, ok := strings.Cut(target, "/") + if !ok || goos == "" || goarch == "" { + return fmt.Errorf("invalid discovery target %q", target) + } + args := []string{"build"} + if len(buildTags) != 0 { + args = append(args, "-tags="+strings.Join(buildTags, ",")) + } + args = append(args, pattern) + targetEnv := replaceEnv(env, map[string]string{ + "CGO_ENABLED": "0", + "GOOS": goos, + "GOARCH": goarch, + }) + return runCapturedCommand(ctx, dir, targetEnv, "go", args...) +} + +func isDiscoveryGoBuildInfrastructureFailure(diagnostic string) bool { + diagnostic = strings.ToLower(diagnostic) + // "unexpected EOF" is also the Go assembler's deterministic diagnostic + // for a truncated source file. Do not retain that source failure as a + // transient network retry merely because proxies use the same phrase. + if strings.Contains(diagnostic, "unexpected eof") && + strings.Contains(diagnostic, ".s:") && + strings.Contains(diagnostic, "asm: assembly of") { + return false + } + for _, marker := range []string{ + "context deadline exceeded", + "i/o timeout", + "tls handshake timeout", + "temporary failure", + "no such host", + "connection refused", + "connection reset", + "network is unreachable", + "proxyconnect", + "unexpected eof", + "bad gateway", + "service unavailable", + "gateway timeout", + "no space left on device", + "signal: killed", + } { + if strings.Contains(diagnostic, marker) { + return true + } + } + return false +} + +func runDiscoveryAsmDecl(ctx context.Context, dir string, env []string, target string, buildTags, patterns []string) error { + goos, goarch, ok := strings.Cut(target, "/") + if !ok || goos == "" || goarch == "" { + return fmt.Errorf("invalid discovery target %q", target) + } + args := []string{"vet", "-asmdecl"} + if len(buildTags) != 0 { + args = append(args, "-tags="+strings.Join(buildTags, ",")) + } + args = append(args, patterns...) + targetEnv := replaceEnv(env, map[string]string{ + "CGO_ENABLED": "0", + "GOOS": goos, + "GOARCH": goarch, + }) + _, err := runCapturedCommandOutput(ctx, dir, targetEnv, "go", args...) + if err == nil { + return nil + } + if ctx.Err() != nil { + return err + } + if isDiscoveryAsmDeclABIMismatch(err.Error()) { + return err + } + // go vet type-checks package tests before running asmdecl. Old modules can + // have tests that no longer compile even though their production package + // builds; retry against temporary module copies with only *_test.go files + // emptied so unrelated diagnostics cannot hide an assembly ABI mismatch. + // Go forbids overlays beneath GOMODCACHE, hence the explicit module copies. + retryErr := runDiscoveryAsmDeclWithTestlessModuleCopies(ctx, dir, targetEnv, args, buildTags, patterns) + if ctxErr := ctx.Err(); ctxErr != nil { + if retryErr != nil { + return retryErr + } + return fmt.Errorf("go vet -asmdecl: %w", ctxErr) + } + if retryErr != nil && isDiscoveryAsmDeclABIMismatch(retryErr.Error()) { + return retryErr + } + return nil +} + +type discoveryGoListPackage struct { + Dir string + TestGoFiles []string + XTestGoFiles []string + Module *struct { + Path string + Dir string + GoMod string + } +} + +func runDiscoveryAsmDeclWithTestlessModuleCopies(ctx context.Context, dir string, env, vetArgs, buildTags, patterns []string) error { + listArgs := []string{"list", "-json"} + if len(buildTags) != 0 { + listArgs = append(listArgs, "-tags="+strings.Join(buildTags, ",")) + } + listArgs = append(listArgs, patterns...) + output, err := runCapturedCommandOutput(ctx, dir, env, "go", listArgs...) + if err != nil { + return err + } + + goModPath := filepath.Join(dir, "go.mod") + goModData, err := os.ReadFile(goModPath) + if err != nil { + return err + } + parsedGoMod, err := modfile.Parse(goModPath, goModData, nil) + if err != nil { + return err + } + + decoder := json.NewDecoder(bytes.NewReader(output)) + packages := make([]discoveryGoListPackage, 0) + for { + var pkg discoveryGoListPackage + if err := decoder.Decode(&pkg); err != nil { + if err == io.EOF { + break + } + return err + } + packages = append(packages, pkg) + } + + stages := make(map[string]string) + hasTests := false + for _, pkg := range packages { + if len(pkg.TestGoFiles)+len(pkg.XTestGoFiles) == 0 { + continue + } + hasTests = true + if pkg.Module == nil || pkg.Module.Path == "" || pkg.Module.Dir == "" { + return fmt.Errorf("cannot create testless asmdecl copy for package %s without module metadata", pkg.Dir) + } + stage := stages[pkg.Module.Dir] + if stage == "" { + stage, err = os.MkdirTemp("", "plan9asm-vet-module-") + if err != nil { + return err + } + defer os.RemoveAll(stage) + if err := copyDiscoveryModuleTree(pkg.Module.Dir, stage); err != nil { + return err + } + stagedGoMod := filepath.Join(stage, "go.mod") + if _, err := os.Stat(stagedGoMod); os.IsNotExist(err) { + moduleGoMod, readErr := os.ReadFile(pkg.Module.GoMod) + if readErr != nil { + return readErr + } + if err := os.WriteFile(stagedGoMod, moduleGoMod, 0644); err != nil { + return err + } + } else if err != nil { + return err + } + if err := parsedGoMod.AddReplace(pkg.Module.Path, "", stage, ""); err != nil { + return err + } + stages[pkg.Module.Dir] = stage + } + for _, fileName := range append(append([]string(nil), pkg.TestGoFiles...), pkg.XTestGoFiles...) { + sourcePath := filepath.Join(pkg.Dir, fileName) + relativePath, err := filepath.Rel(pkg.Module.Dir, sourcePath) + if err != nil || relativePath == ".." || strings.HasPrefix(relativePath, ".."+string(filepath.Separator)) { + return fmt.Errorf("test file %s is outside module %s", sourcePath, pkg.Module.Dir) + } + parsed, err := parser.ParseFile(token.NewFileSet(), sourcePath, nil, parser.PackageClauseOnly) + if err != nil { + return err + } + if err := os.WriteFile(filepath.Join(stage, relativePath), []byte("package "+parsed.Name.Name+"\n"), 0644); err != nil { + return err + } + } + } + if !hasTests { + return nil + } + formattedGoMod, err := parsedGoMod.Format() + if err != nil { + return err + } + modfilePath := filepath.Join(dir, ".plan9asm-vet.mod") + if err := os.WriteFile(modfilePath, formattedGoMod, 0644); err != nil { + return err + } + args := append([]string{"vet", "-modfile=" + modfilePath}, vetArgs[1:]...) + _, err = runCapturedCommandOutput(ctx, dir, env, "go", args...) + return err +} + +func copyDiscoveryModuleTree(source, destination string) error { + return filepath.Walk(source, func(sourcePath string, info os.FileInfo, walkErr error) error { + if walkErr != nil { + return walkErr + } + relativePath, err := filepath.Rel(source, sourcePath) + if err != nil { + return err + } + destinationPath := filepath.Join(destination, relativePath) + if info.IsDir() { + return os.MkdirAll(destinationPath, info.Mode().Perm()|0700) + } + if !info.Mode().IsRegular() { + return fmt.Errorf("unsupported non-regular module file %s", sourcePath) + } + contents, err := os.ReadFile(sourcePath) + if err != nil { + return err + } + return os.WriteFile(destinationPath, contents, info.Mode().Perm()|0600) + }) +} + +func isDiscoveryAsmDeclABIMismatch(diagnostic string) bool { + diagnostic = strings.ToLower(diagnostic) + if strings.Contains(diagnostic, "wrong argument size") || strings.Contains(diagnostic, "invalid offset") { + return true + } + // asmdecl reports an invalid load/store width against an FP operand when + // the declared Go parameter or result has a different ABI width. Keep the + // FP requirement so generic assembler, dependency, and source diagnostics + // continue into translation instead of being hidden as not applicable. + return strings.Contains(diagnostic, ": invalid ") && strings.Contains(diagnostic, "(fp)") +} + +func discoveryAsmDeclRejectedFiles(asmFiles []string, diagnostic string) []string { + diagnostic = filepath.ToSlash(diagnostic) + var rejected []string + for _, asmFile := range asmFiles { + asmFile = filepath.ToSlash(asmFile) + if strings.Contains(diagnostic, asmFile+":") || strings.Contains(diagnostic, "/"+asmFile+":") { + rejected = append(rejected, asmFile) + continue + } + // The Go command sometimes shortens diagnostics to a package-local + // basename. Only use that fallback when it identifies this file. + if strings.Contains(diagnostic, path.Base(asmFile)+":") { + rejected = append(rejected, asmFile) + } + } + return uniqueSortedDiscoveryStrings(rejected) +} + +func subtractDiscoveryStrings(values, removed []string) []string { + removeSet := make(map[string]bool, len(removed)) + for _, value := range removed { + removeSet[value] = true + } + out := make([]string, 0, len(values)) + for _, value := range values { + if !removeSet[value] { + out = append(out, value) + } + } + return out +} + +func limitDiscoveryEvidence(message string, maxBytes int) string { + message = strings.TrimSpace(message) + if maxBytes <= 0 || len(message) <= maxBytes { + return message + } + return message[:maxBytes] + "\n... evidence truncated ..." +} + +func collectMatrixNotApplicableItems(report matrixReport) []matrixTargetNotApplicableItem { + var items []matrixTargetNotApplicableItem + for _, target := range report.Targets { + targetName := target.Goos + "/" + target.Goarch + for _, item := range target.NotApplicableItems { + items = append(items, matrixTargetNotApplicableItem{Target: targetName, targetNotApplicableItem: item}) + } + } + return items +} + +func sortedDiscoverySet(set map[string]bool) []string { + values := make([]string, 0, len(set)) + for value := range set { + values = append(values, value) + } + sort.Strings(values) + return values +} + +func runCapturedCommand(ctx context.Context, dir string, env []string, name string, args ...string) error { + _, err := runCapturedCommandOutput(ctx, dir, env, name, args...) + return err +} + +func runCapturedCommandOutput(ctx context.Context, dir string, env []string, name string, args ...string) ([]byte, error) { + cmd := exec.CommandContext(ctx, name, args...) + cmd.Dir = dir + cmd.Env = env + var output bytes.Buffer + cmd.Stdout = &output + cmd.Stderr = &output + err := cmd.Run() + if ctx.Err() != nil { + return nil, fmt.Errorf("%s: %w", strings.Join(append([]string{name}, args...), " "), ctx.Err()) + } + if err == nil { + return output.Bytes(), nil + } + message := strings.TrimSpace(output.String()) + if len(message) > 64<<10 { + message = "... output truncated ...\n" + message[len(message)-(64<<10):] + } + if message == "" { + return nil, fmt.Errorf("%s: %w", strings.Join(append([]string{name}, args...), " "), err) + } + return output.Bytes(), fmt.Errorf("%s: %w\n%s", strings.Join(append([]string{name}, args...), " "), err, message) +} + +func replaceEnv(base []string, replacements map[string]string) []string { + out := make([]string, 0, len(base)+len(replacements)) + for _, item := range base { + key, _, ok := strings.Cut(item, "=") + if ok { + if _, replace := replacements[key]; replace { + continue + } + } + out = append(out, item) + } + keys := make([]string, 0, len(replacements)) + for key := range replacements { + keys = append(keys, key) + } + sort.Strings(keys) + for _, key := range keys { + out = append(out, key+"="+replacements[key]) + } + return out +} + +func validateDiscoveryReport(targets []string, candidate discoveryCandidate, report matrixReport) error { + if report.TotalTargets != len(targets) || len(report.Targets) != len(targets) { + return fmt.Errorf("%s: target coverage changed: got total=%d reports=%d, want %d", candidate.exactKey(), report.TotalTargets, len(report.Targets), len(targets)) + } + seen := make(map[string]bool, len(targets)) + totalAsm := 0 + totalSuccess := 0 + totalNotApplicable := 0 + for _, actual := range report.Targets { + target := actual.Goos + "/" + actual.Goarch + if seen[target] { + return fmt.Errorf("%s: duplicate target report %s", candidate.exactKey(), target) + } + seen[target] = true + if actual.Failed != 0 || actual.Success+actual.NotApplicable != actual.TotalAsm { + return fmt.Errorf("%s: %s failed: success=%d not_applicable=%d failed=%d total=%d", candidate.exactKey(), target, actual.Success, actual.NotApplicable, actual.Failed, actual.TotalAsm) + } + if err := validateTargetNotApplicableEvidence(actual); err != nil { + return fmt.Errorf("%s: %s: %w", candidate.exactKey(), target, err) + } + totalAsm += actual.TotalAsm + totalSuccess += actual.Success + totalNotApplicable += actual.NotApplicable + } + for _, target := range targets { + if !seen[target] { + return fmt.Errorf("%s: target %s was silently skipped", candidate.exactKey(), target) + } + } + if totalAsm == 0 { + return fmt.Errorf("%s: no assembly entered translation on the target matrix", candidate.exactKey()) + } + observed := make(map[string]bool) + for _, target := range report.Targets { + for _, actualPath := range target.AsmFiles { + actualPath = filepath.ToSlash(actualPath) + for _, expectedPath := range candidate.AsmFiles { + if actualPath == expectedPath || strings.HasSuffix(actualPath, "/"+expectedPath) { + observed[expectedPath] = true + } + } + } + } + var missing []string + for _, expectedPath := range candidate.AsmFiles { + if !observed[expectedPath] { + missing = append(missing, expectedPath) + } + } + if len(missing) != 0 { + return fmt.Errorf("%s: %d supported assembly files were not exercised: %v", candidate.exactKey(), len(missing), missing) + } + if report.TotalAsm != totalAsm || report.Success != totalSuccess || report.NotApplicable != totalNotApplicable || report.Failed != 0 || report.Success+report.NotApplicable != report.TotalAsm { + return fmt.Errorf("%s: inconsistent matrix totals: success=%d not_applicable=%d failed=%d total=%d", candidate.exactKey(), report.Success, report.NotApplicable, report.Failed, report.TotalAsm) + } + return nil +} + +func validateTargetNotApplicableEvidence(report targetReport) error { + if report.NotApplicable != len(report.NotApplicableItems) { + return fmt.Errorf("not-applicable accounting mismatch: count=%d items=%d", report.NotApplicable, len(report.NotApplicableItems)) + } + asmFiles := make(map[string]bool, len(report.AsmFiles)) + for _, asmFile := range report.AsmFiles { + asmFiles[asmFile] = true + } + for _, item := range report.NotApplicableItems { + if item.Kind != targetNotApplicableGoTextArgSize || item.PkgPath == "" || item.AsmFile == "" || !asmFiles[item.AsmFile] || item.Symbol == "" || item.DeclaredArgSize == item.ExpectedArgSize || item.Reason == "" { + return fmt.Errorf("invalid not-applicable evidence for %q: kind=%q symbol=%q declared=%d expected=%d", item.AsmFile, item.Kind, item.Symbol, item.DeclaredArgSize, item.ExpectedArgSize) + } + } + return nil +} + +func writeDiscoveryCorpusReport(reportPath string, report discoveryCorpusReport) error { + if reportPath == "" { + return nil + } + data, err := json.MarshalIndent(report, "", " ") + if err != nil { + return fmt.Errorf("encode discovery corpus report: %w", err) + } + data = append(data, '\n') + if err := os.MkdirAll(filepath.Dir(reportPath), 0755); err != nil { + return fmt.Errorf("create discovery report directory: %w", err) + } + if err := os.WriteFile(reportPath, data, 0644); err != nil { + return fmt.Errorf("write discovery corpus report: %w", err) + } + return nil +} diff --git a/cmd/plan9asmcorpus/discovery_test.go b/cmd/plan9asmcorpus/discovery_test.go new file mode 100644 index 00000000..f396def0 --- /dev/null +++ b/cmd/plan9asmcorpus/discovery_test.go @@ -0,0 +1,857 @@ +package main + +import ( + "archive/zip" + "context" + "encoding/json" + "errors" + "fmt" + "go/build" + "os" + "path/filepath" + "reflect" + "strings" + "testing" +) + +func TestResolveModuleDownloadUsesCachedZipAfterToolchainVersionRejection(t *testing.T) { + root := t.TempDir() + zipPath := filepath.Join(root, "module.zip") + zipFile, err := os.Create(zipPath) + if err != nil { + t.Fatal(err) + } + writer := zip.NewWriter(zipFile) + for name, contents := range map[string]string{ + "example.com/Upper/Lib@v1.0.0/go.mod": "module example.com/Upper/Lib\n\ngo 1.27.1\n", + "example.com/Upper/Lib@v1.0.0/asm_amd64.s": "TEXT ·f(SB),NOSPLIT,$0-0\nRET\n", + } { + entry, err := writer.Create(name) + if err != nil { + t.Fatal(err) + } + if _, err := entry.Write([]byte(contents)); err != nil { + t.Fatal(err) + } + } + if err := writer.Close(); err != nil { + t.Fatal(err) + } + if err := zipFile.Close(); err != nil { + t.Fatal(err) + } + downloadJSON, err := json.Marshal(moduleDownloadInfo{ + Path: "example.com/Upper/Lib", + Version: "v1.0.0", + GoMod: filepath.Join(root, "cache.mod"), + Zip: zipPath, + Error: "example.com/lib@v1.0.0 requires go >= 1.27.1 (running go 1.27.0; GOTOOLCHAIN=local)", + }) + if err != nil { + t.Fatal(err) + } + download, err := resolveModuleDownload(downloadJSON, errors.New("exit status 1"), filepath.Join(root, "work")) + if err != nil { + t.Fatal(err) + } + contents, err := os.ReadFile(filepath.Join(download.Dir, "asm_amd64.s")) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(string(contents), "TEXT ·f") { + t.Fatalf("extracted assembly = %q", contents) + } +} + +func TestRunDiscoveryAsmDeclUsesCurrentGoTargetABI(t *testing.T) { + dir := t.TempDir() + writeTestFile(t, filepath.Join(dir, "go.mod"), "module example.com/asmdecl\n\ngo 1.20\n") + writeTestFile(t, filepath.Join(dir, "decl.go"), "package asmdecl\n\nfunc f(x int64)\n") + asm := filepath.Join(dir, "decl_amd64.s") + writeTestFile(t, asm, "TEXT ·f(SB), $0-1\nRET\n") + env := replaceEnv(os.Environ(), map[string]string{"GOFLAGS": "-mod=mod", "GOWORK": "off"}) + if err := runDiscoveryAsmDecl(context.Background(), dir, env, "linux/amd64", nil, []string{"example.com/asmdecl"}); err == nil { + t.Fatal("runDiscoveryAsmDecl() succeeded for a wrong TEXT argument size") + } + writeTestFile(t, asm, "TEXT ·f(SB), $0-8\nRET\n") + if err := runDiscoveryAsmDecl(context.Background(), dir, env, "linux/amd64", nil, []string{"example.com/asmdecl"}); err != nil { + t.Fatalf("runDiscoveryAsmDecl() valid source error = %v", err) + } +} + +func TestRunDiscoveryAsmDeclStillFindsABIMismatchWhenTestsDoNotCompile(t *testing.T) { + root := t.TempDir() + dir := filepath.Join(root, "work") + dependency := filepath.Join(root, "dependency") + if err := os.MkdirAll(dir, 0755); err != nil { + t.Fatal(err) + } + if err := os.MkdirAll(dependency, 0755); err != nil { + t.Fatal(err) + } + writeTestFile(t, filepath.Join(dir, "go.mod"), "module plan9asm.local/probe\n\ngo 1.20\n\nrequire example.com/asmdeclbroken v0.0.0\nreplace example.com/asmdeclbroken => ../dependency\n") + writeTestFile(t, filepath.Join(dependency, "go.mod"), "module example.com/asmdeclbroken\n\ngo 1.20\n") + writeTestFile(t, filepath.Join(dependency, "decl.go"), "package asmdeclbroken\n\nfunc f() uint32\n") + writeTestFile(t, filepath.Join(dependency, "decl_386.s"), "TEXT ·f(SB), $0-4\nMOVL AX, ret+4(FP)\nRET\n") + writeTestFile(t, filepath.Join(dependency, "decl_test.go"), "package asmdeclbroken\n\nvar _ uint32 = int64(1)\n") + env := replaceEnv(os.Environ(), map[string]string{"GOFLAGS": "-mod=mod", "GOWORK": "off"}) + err := runDiscoveryAsmDecl(context.Background(), dir, env, "linux/386", nil, []string{"example.com/asmdeclbroken"}) + if err == nil || !isDiscoveryAsmDeclABIMismatch(err.Error()) { + t.Fatalf("runDiscoveryAsmDecl() error = %v, want assembly ABI mismatch despite broken tests", err) + } +} + +func TestRunDiscoveryAsmDeclPropagatesExpiredContext(t *testing.T) { + dir := t.TempDir() + writeTestFile(t, filepath.Join(dir, "go.mod"), "module example.com/asmdecltimeout\n\ngo 1.20\n") + writeTestFile(t, filepath.Join(dir, "decl.go"), "package asmdecltimeout\n\nfunc f()\n") + writeTestFile(t, filepath.Join(dir, "decl_386.s"), "TEXT ·f(SB), $0-0\nRET\n") + env := replaceEnv(os.Environ(), map[string]string{"GOFLAGS": "-mod=mod", "GOWORK": "off"}) + ctx, cancel := context.WithCancel(context.Background()) + cancel() + err := runDiscoveryAsmDecl(ctx, dir, env, "linux/386", nil, []string{"example.com/asmdecltimeout"}) + if !errors.Is(err, context.Canceled) { + t.Fatalf("runDiscoveryAsmDecl() error = %v, want context.Canceled", err) + } +} + +func TestRunDiscoveryGoBuildChecksExactCurrentPackage(t *testing.T) { + dir := t.TempDir() + writeTestFile(t, filepath.Join(dir, "go.mod"), "module example.com/buildable\n\ngo 1.20\n") + writeTestFile(t, filepath.Join(dir, "decl.go"), "package buildable\n\nfunc f()\n") + writeTestFile(t, filepath.Join(dir, "decl_amd64.s"), "TEXT ·f(SB), $0-0\nRET\n") + env := replaceEnv(os.Environ(), map[string]string{"GOFLAGS": "-mod=mod", "GOWORK": "off"}) + if err := runDiscoveryGoBuild(context.Background(), dir, env, "linux/amd64", nil, "example.com/buildable"); err != nil { + t.Fatalf("runDiscoveryGoBuild() valid package error = %v", err) + } + writeTestFile(t, filepath.Join(dir, "decl.go"), "package buildable\n\nvar broken = missingIdentifier\n") + if err := runDiscoveryGoBuild(context.Background(), dir, env, "linux/amd64", nil, "example.com/buildable"); err == nil { + t.Fatal("runDiscoveryGoBuild() accepted source rejected by the current Go compiler") + } +} + +func TestDiscoveryGoBuildInfrastructureFailuresAreNotSourceNotApplicable(t *testing.T) { + for _, diagnostic := range []string{ + "go build example.com/pkg: context deadline exceeded", + "dial tcp: lookup proxy.golang.org: no such host", + "Get https://proxy.golang.org: net/http: TLS handshake timeout", + "write /tmp/go-build/object.o: no space left on device", + "go build example.com/pkg: signal: killed", + } { + if !isDiscoveryGoBuildInfrastructureFailure(diagnostic) { + t.Fatalf("infrastructure diagnostic was classified as source incompatibility: %q", diagnostic) + } + } + for _, diagnostic := range []string{ + "pkg/file.go:12:2: undefined: removedSymbol", + "use of internal package runtime/internal/sys not allowed", + "package example.com/old imports C: build constraints exclude all Go files", + "pkg/goid_386.s:13: unexpected EOF\nasm: assembly of pkg/goid_386.s failed", + } { + if isDiscoveryGoBuildInfrastructureFailure(diagnostic) { + t.Fatalf("source diagnostic was classified as infrastructure failure: %q", diagnostic) + } + } +} + +func TestDiscoveryAsmDeclOnlyClassifiesConcreteABIMismatches(t *testing.T) { + for _, diagnostic := range []string{ + "file.s:1: [386] f: wrong argument size 0; expected $...-12", + "file.s:2: [386] f: invalid offset ret+4(FP); expected ret+8(FP)", + "file.s:3: [386] f: invalid MOVL of x+0(FP); uint64 is 8-byte value", + } { + if !isDiscoveryAsmDeclABIMismatch(diagnostic) { + t.Fatalf("concrete ABI diagnostic was not classified: %q", diagnostic) + } + } + for _, diagnostic := range []string{ + "file.s:1: [arm] f: unknown variable unnamed_lo; offset 36 is ret1_lo+36(FP)", + "file.s:1: [amd64] f+0: function f+0 missing Go declaration", + "package dependency is missing", + } { + if isDiscoveryAsmDeclABIMismatch(diagnostic) { + t.Fatalf("non-ABI diagnostic was classified as N/A: %q", diagnostic) + } + } +} + +func TestDiscoveryConstraintTagsReadsOnlyTheSourceHeader(t *testing.T) { + file := filepath.Join(t.TempDir(), "generated.go") + contents := "//go:build realtag\n\npackage generated\n\nvar template = `\n//go:build invalid%template\n`\n" + strings.Repeat("x", 128<<10) + writeTestFile(t, file, contents) + tags, err := discoveryConstraintTags(file) + if err != nil { + t.Fatal(err) + } + if want := []string{"realtag"}; !reflect.DeepEqual(tags, want) { + t.Fatalf("constraint tags = %#v, want %#v", tags, want) + } +} + +func TestDiscoveryBuildConfigurationsRecordsDirectoryWithoutCurrentGoPackage(t *testing.T) { + dir := t.TempDir() + writeTestFile(t, filepath.Join(dir, "misnamed.go"), ".LCPI0_0:\n .byte 1\n") + writeTestFile(t, filepath.Join(dir, "routine.s"), "TEXT ·routine(SB), $0-0\nRET\n") + candidate := discoveryCandidate{Module: "example.com/broken", Version: "v1.0.0", AsmFiles: []string{"routine.s"}} + var evidence []discoverySourceNotApplicableItem + configs, err := discoveryBuildConfigurationsWithEvidence(candidate, dir, []string{"linux/amd64"}, &evidence) + if err != nil { + t.Fatal(err) + } + if len(configs) != 0 || len(evidence) != 1 || evidence[0].Kind != discoverySourceNotApplicableNoGoPackage || !strings.Contains(evidence[0].Reason, "misnamed.go") { + t.Fatalf("configs = %#v, evidence = %#v", configs, evidence) + } +} + +func TestInferUnsuffixedAssemblyTargetsTreatsCurrentGoRejectedSourceAsInapplicable(t *testing.T) { + file := filepath.Join(t.TempDir(), "fixture.s") + writeTestFile(t, file, "this is deliberately not current Go assembly\n") + contexts := []build.Context{build.Default, build.Default} + contexts[0].GOOS, contexts[0].GOARCH = "linux", "amd64" + contexts[1].GOOS, contexts[1].GOARCH = "linux", "arm64" + eligible, restricted, reason, err := inferUnsuffixedAssemblyTargetsDetailed(file, contexts) + if err != nil { + t.Fatal(err) + } + if !restricted || len(eligible) != 0 { + t.Fatalf("eligible = %#v, restricted = %v; want explicit empty target set", eligible, restricted) + } + if !strings.Contains(reason, "rejected") || !strings.Contains(reason, "linux/amd64") || !strings.Contains(reason, "linux/arm64") { + t.Fatalf("reason = %q, want rejected targets", reason) + } +} + +func TestInferUnsuffixedAssemblyTargetsUsesEmptyGeneratedHeaderForArchitectureProbe(t *testing.T) { + file := filepath.Join(t.TempDir(), "x86.s") + writeTestFile(t, file, "#include \"go_asm.h\"\nTEXT ·x(SB), $0-0\nMOVQ AX, AX\nRET\n") + contexts := []build.Context{build.Default, build.Default} + contexts[0].GOOS, contexts[0].GOARCH = "linux", "amd64" + contexts[1].GOOS, contexts[1].GOARCH = "linux", "arm64" + eligible, restricted, err := inferUnsuffixedAssemblyTargets(file, contexts) + if err != nil { + t.Fatal(err) + } + if !restricted || !eligible["linux/amd64"] || eligible["linux/arm64"] || len(eligible) != 1 { + t.Fatalf("eligible = %#v, restricted = %v; want only linux/amd64", eligible, restricted) + } +} + +func TestMissingGoAsmHeaderRecognizesHostDiagnostics(t *testing.T) { + for _, message := range []string{ + `fatal error: go_asm.h: No such file or directory`, + `open go_asm.h: The system cannot find the file specified.`, + `could not find included file "go_asm.h"`, + } { + if !missingGoAsmHeader(message) { + t.Errorf("missingGoAsmHeader(%q) = false, want true", message) + } + } + if missingGoAsmHeader("missing unrelated.h: no such file or directory") { + t.Fatal("missingGoAsmHeader accepted an unrelated missing include") + } +} + +func TestLoadDiscoveryCandidatesDeduplicatesAndMergesMatchedRecords(t *testing.T) { + dir := t.TempDir() + records := filepath.Join(dir, "records") + if err := os.Mkdir(records, 0755); err != nil { + t.Fatal(err) + } + writeTestFile(t, filepath.Join(records, "01.jsonl"), strings.Join([]string{ + `{"kind":"scanned","module":"example.com/noasm","version":"v1.0.0"}`, + `{"kind":"matched","module":"example.com/asm","version":"v1.2.3","architectures":["amd64"],"asm_files":["root_amd64.s"]}`, + }, "\n")+"\n") + writeTestFile(t, filepath.Join(records, "02.jsonl"), strings.Join([]string{ + `{"kind":"failure","module":"example.com/fail","version":"@latest","error":"404"}`, + `{"kind":"matched","module":"example.com/asm","version":"v1.2.3","architectures":["unknown","arm64","amd64"],"asm_files":["sub/future_riscv64.s","sub/asm_arm64.s","root_amd64.s"]}`, + }, "\n")+"\n") + // A previous per-run layout must not silently expand the active corpus. + legacy := filepath.Join(dir, "runs", "old", "records") + if err := os.MkdirAll(legacy, 0755); err != nil { + t.Fatal(err) + } + writeTestFile(t, filepath.Join(legacy, "03.jsonl"), + `{"kind":"matched","module":"example.com/legacy","version":"v9.9.9","asm_files":["legacy_amd64.s"]}`+"\n") + + got, err := loadDiscoveryCandidates(dir) + if err != nil { + t.Fatal(err) + } + want := []discoveryCandidate{{ + Module: "example.com/asm", + Version: "v1.2.3", + Architectures: []string{"amd64", "arm64", "unknown"}, + AsmFiles: []string{"root_amd64.s", "sub/asm_arm64.s", "sub/future_riscv64.s"}, + }} + if !reflect.DeepEqual(got, want) { + t.Fatalf("candidates = %#v, want %#v", got, want) + } +} + +func TestLoadDiscoveryCandidatesRejectsUnsafeAssemblyPath(t *testing.T) { + path := filepath.Join(t.TempDir(), "records.jsonl") + writeTestFile(t, path, `{"kind":"matched","module":"example.com/asm","version":"v1.0.0","asm_files":["../escape_amd64.s"]}`+"\n") + if _, err := loadDiscoveryCandidates(path); err == nil || !strings.Contains(err.Error(), "unsafe assembly path") { + t.Fatalf("loadDiscoveryCandidates() error = %v, want unsafe path failure", err) + } +} + +func TestDiscoveryShardCoversEveryCandidateExactlyOnce(t *testing.T) { + candidates := make([]discoveryCandidate, 97) + for i := range candidates { + candidates[i] = discoveryCandidate{Module: fmt.Sprintf("example.com/module-%03d", i), Version: "v1.0.0"} + } + seen := make(map[string]int, len(candidates)) + for shard := 0; shard < 13; shard++ { + for _, candidate := range selectDiscoveryShard(candidates, shard, 13) { + seen[candidate.exactKey()]++ + } + } + for _, candidate := range candidates { + if seen[candidate.exactKey()] != 1 { + t.Fatalf("candidate %s occurred in %d shards, want exactly one", candidate.exactKey(), seen[candidate.exactKey()]) + } + } +} + +func TestFilterDiscoveryCandidatesForTargetsUsesRecordedAssemblyPaths(t *testing.T) { + candidates := []discoveryCandidate{ + { + Module: "example.com/mixed", + Version: "v1.0.0", + AsmFiles: []string{"asm_amd64.s", "asm_linux_riscv64.s", "asm_plan9_riscv64.s", "portable.s"}, + }, + { + Module: "example.com/amd64-only", + Version: "v1.0.0", + AsmFiles: []string{"asm_amd64.s"}, + }, + } + got, err := filterDiscoveryCandidatesForTargets(candidates, []string{"linux/riscv64"}) + if err != nil { + t.Fatal(err) + } + want := []discoveryCandidate{{ + Module: "example.com/mixed", + Version: "v1.0.0", + Architectures: []string{"riscv64", "unknown"}, + AsmFiles: []string{"asm_linux_riscv64.s", "portable.s"}, + }} + if !reflect.DeepEqual(got, want) { + t.Fatalf("target candidates = %#v, want %#v", got, want) + } +} + +func TestFilterDiscoveryCandidatesForTargetsKeepsUnknownSuffixesConservatively(t *testing.T) { + candidates := []discoveryCandidate{{ + Module: "example.com/generated", + Version: "v1.0.0", + AsmFiles: []string{"asm_amd64x.s", "asm_linux.s", "asm_windows.s"}, + }} + got, err := filterDiscoveryCandidatesForTargets(candidates, []string{"linux/riscv64"}) + if err != nil { + t.Fatal(err) + } + wantFiles := []string{"asm_amd64x.s", "asm_linux.s"} + if len(got) != 1 || !reflect.DeepEqual(got[0].AsmFiles, wantFiles) { + t.Fatalf("target candidates = %#v, want files %#v", got, wantFiles) + } +} + +func TestDiscoveryPackagePatternsUseOnlyAssemblyDirectories(t *testing.T) { + candidate := discoveryCandidate{ + Module: "example.com/root", + Version: "v1.0.0", + AsmFiles: []string{"root_amd64.s", "internal/a_amd64.s", "internal/sub/b_arm64.s"}, + } + want := []string{"example.com/root", "example.com/root/internal", "example.com/root/internal/sub"} + if got := discoveryPackagePatterns(candidate); !reflect.DeepEqual(got, want) { + t.Fatalf("patterns = %#v, want %#v", got, want) + } +} + +func TestDiscoveryExecutionPlanUsesDeclaredModulePathAndExactForkContent(t *testing.T) { + candidate := discoveryCandidate{ + Module: "example.com/fork", + Version: "v1.2.3", + AsmFiles: []string{"crypto/hash_amd64.s"}, + } + plan, err := makeDiscoveryExecutionPlan(candidate, "example.com/upstream") + if err != nil { + t.Fatal(err) + } + if plan.ModulePath != "example.com/upstream" { + t.Fatalf("module path = %q, want declared path", plan.ModulePath) + } + if want := []string{"example.com/upstream/crypto"}; !reflect.DeepEqual(plan.Patterns, want) { + t.Fatalf("patterns = %#v, want %#v", plan.Patterns, want) + } + for _, want := range []string{ + "require example.com/upstream v1.2.3", + "replace example.com/upstream => example.com/fork v1.2.3", + } { + if !strings.Contains(plan.GoMod, want) { + t.Fatalf("go.mod missing %q:\n%s", want, plan.GoMod) + } + } +} + +func TestParseDeclaredModulePath(t *testing.T) { + for _, test := range []struct { + contents string + want string + }{ + {contents: "module example.com/plain\n", want: "example.com/plain"}, + {contents: "// generated\nmodule \"example.com/quoted\" // comment\n", want: "example.com/quoted"}, + } { + got, err := parseDeclaredModulePath([]byte(test.contents)) + if err != nil { + t.Fatal(err) + } + if got != test.want { + t.Fatalf("declared module = %q, want %q", got, test.want) + } + } +} + +func TestApplicableDiscoveryAssemblyFilesUsesExactTargetBuildRules(t *testing.T) { + dir := t.TempDir() + write := func(name, contents string) { + t.Helper() + fullPath := filepath.Join(dir, filepath.FromSlash(name)) + if err := os.MkdirAll(filepath.Dir(fullPath), 0o755); err != nil { + t.Fatal(err) + } + writeTestFile(t, fullPath, contents) + } + write("pkg.go", "package pkg\n") + write("asm_linux_amd64.s", "TEXT ·amd64(SB),0,$0-0\nRET\n") + write("asm_freebsd_amd64.s", "TEXT ·freebsd(SB),0,$0-0\nRET\n") + write("tagged.s", "//go:build linux && arm64\n\nTEXT ·arm64(SB),0,$0-0\nRET\n") + write("_hidden/hidden.go", "package hidden\n") + write("_hidden/hidden_amd64.s", "TEXT ·hidden(SB),0,$0-0\nRET\n") + write("nested/go.mod", "module example.com/nested\n\ngo 1.27\n") + write("nested/nested.go", "package nested\n") + write("nested/nested_amd64.s", "TEXT ·nested(SB),0,$0-0\nRET\n") + + candidate := discoveryCandidate{AsmFiles: []string{ + "_hidden/hidden_amd64.s", + "asm_freebsd_amd64.s", + "asm_linux_amd64.s", + "nested/nested_amd64.s", + "tagged.s", + }} + got, err := applicableDiscoveryAssemblyFiles(candidate, dir, []string{"linux/amd64", "linux/arm64"}) + if err != nil { + t.Fatal(err) + } + want := []string{"asm_linux_amd64.s", "tagged.s"} + if !reflect.DeepEqual(got, want) { + t.Fatalf("applicable assembly = %#v, want %#v", got, want) + } +} + +func TestDiscoveryBuildConfigurationsCoverMutuallyExclusiveCustomTags(t *testing.T) { + dir := t.TempDir() + writeTestFile(t, filepath.Join(dir, "pkg.go"), "package pkg\n") + writeTestFile(t, filepath.Join(dir, "default.s"), "//go:build !special\n\nTEXT ·defaultImpl(SB),0,$0-0\nRET\n") + writeTestFile(t, filepath.Join(dir, "special.s"), "//go:build special\n\nTEXT ·specialImpl(SB),0,$0-0\nRET\n") + candidate := discoveryCandidate{ + Module: "example.com/customtags", + Version: "v1.0.0", + AsmFiles: []string{"default.s", "special.s"}, + } + got, err := discoveryBuildConfigurations(candidate, dir, []string{"linux/amd64"}) + if err != nil { + t.Fatal(err) + } + want := []discoveryBuildConfiguration{ + {Targets: []string{"linux/amd64"}, AsmFiles: []string{"default.s"}}, + {BuildTags: []string{"special"}, Targets: []string{"linux/amd64"}, AsmFiles: []string{"special.s"}}, + } + if !reflect.DeepEqual(got, want) { + t.Fatalf("build configurations = %#v, want %#v", got, want) + } +} + +func TestDiscoveryBuildConfigurationsCoverTargetSpecificTagAssignments(t *testing.T) { + dir := t.TempDir() + writeTestFile(t, filepath.Join(dir, "pkg.go"), "package pkg\n") + writeTestFile(t, filepath.Join(dir, "hybrid.s"), "//go:build (amd64 && avx) || (arm64 && neon)\n\nTEXT ·hybrid(SB),0,$0-0\nRET\n") + candidate := discoveryCandidate{ + Module: "example.com/targettags", + Version: "v1.0.0", + AsmFiles: []string{"hybrid.s"}, + } + got, err := discoveryBuildConfigurations(candidate, dir, []string{"linux/amd64", "linux/arm64"}) + if err != nil { + t.Fatal(err) + } + want := []discoveryBuildConfiguration{ + {BuildTags: []string{"avx"}, Targets: []string{"linux/amd64"}, AsmFiles: []string{"hybrid.s"}}, + {BuildTags: []string{"neon"}, Targets: []string{"linux/arm64"}, AsmFiles: []string{"hybrid.s"}}, + } + if !reflect.DeepEqual(got, want) { + t.Fatalf("build configurations = %#v, want %#v", got, want) + } +} + +func TestDiscoveryBuildConfigurationsDoNotEnableIgnoredGeneratorSources(t *testing.T) { + dir := t.TempDir() + writeTestFile(t, filepath.Join(dir, "pkg.go"), "package pkg\n") + writeTestFile(t, filepath.Join(dir, "generated.s"), "//go:build ignore\n\nTEXT ·generated(SB),0,$0-0\nRET\n") + candidate := discoveryCandidate{ + Module: "example.com/generator", + Version: "v1.0.0", + AsmFiles: []string{"generated.s"}, + } + got, err := discoveryBuildConfigurations(candidate, dir, []string{"linux/amd64"}) + if err != nil { + t.Fatal(err) + } + if len(got) != 0 { + t.Fatalf("build configurations = %#v, want ignored generator assembly to remain inapplicable", got) + } +} + +func TestDiscoveryBuildConfigurationsInferUnsuffixedAssemblyFromGoAssembler(t *testing.T) { + dir := t.TempDir() + writeTestFile(t, filepath.Join(dir, "pkg.go"), "package pkg\n") + writeTestFile(t, filepath.Join(dir, "goid.s"), "TEXT ·goid(SB),0,$0-0\nMOVQ AX, BX\nLEAQ (BX), CX\nRET\n") + candidate := discoveryCandidate{ + Module: "example.com/goid", + Version: "v1.0.0", + AsmFiles: []string{"goid.s"}, + } + got, err := discoveryBuildConfigurations(candidate, dir, []string{"linux/386", "linux/amd64", "linux/arm64", "js/wasm"}) + if err != nil { + t.Fatal(err) + } + want := []discoveryBuildConfiguration{{Targets: []string{"linux/amd64"}, AsmFiles: []string{"goid.s"}}} + if !reflect.DeepEqual(got, want) { + t.Fatalf("build configurations = %#v, want %#v", got, want) + } +} + +func TestDiscoveryBuildConfigurationsKeepTrulyCrossArchUnsuffixedAssembly(t *testing.T) { + dir := t.TempDir() + writeTestFile(t, filepath.Join(dir, "pkg.go"), "package pkg\n") + writeTestFile(t, filepath.Join(dir, "return.s"), "TEXT ·returnOnly(SB),0,$0-0\nRET\n") + candidate := discoveryCandidate{ + Module: "example.com/returnonly", + Version: "v1.0.0", + AsmFiles: []string{"return.s"}, + } + got, err := discoveryBuildConfigurations(candidate, dir, []string{"linux/386", "linux/amd64", "linux/arm", "linux/arm64"}) + if err != nil { + t.Fatal(err) + } + want := []discoveryBuildConfiguration{{Targets: []string{"linux/386", "linux/amd64", "linux/arm", "linux/arm64"}, AsmFiles: []string{"return.s"}}} + if !reflect.DeepEqual(got, want) { + t.Fatalf("build configurations = %#v, want %#v", got, want) + } +} + +func TestValidateDiscoveryReportRejectsZeroAssemblyAndSkippedTargets(t *testing.T) { + candidate := discoveryCandidate{Module: "example.com/root", Version: "v1.0.0", AsmFiles: []string{"root_amd64.s"}} + report := matrixReport{ + Targets: []targetReport{{Goos: "linux", Goarch: "amd64"}}, + TotalTargets: 1, + } + err := validateDiscoveryReport([]string{"linux/amd64"}, candidate, report) + if err == nil || !strings.Contains(err.Error(), "no assembly") { + t.Fatalf("validateDiscoveryReport() error = %v, want no assembly failure", err) + } + + report.Targets[0].TotalAsm = 1 + report.Targets[0].Success = 1 + report.TotalAsm = 1 + report.Success = 1 + err = validateDiscoveryReport([]string{"linux/amd64", "windows/amd64"}, candidate, report) + if err == nil || !strings.Contains(err.Error(), "target coverage changed") { + t.Fatalf("validateDiscoveryReport() error = %v, want target coverage failure", err) + } +} + +func TestValidateDiscoveryReportRejectsEveryUnobservedApplicableAssemblyFile(t *testing.T) { + candidate := discoveryCandidate{ + Module: "example.com/root", + Version: "v1.0.0", + AsmFiles: []string{"root_amd64.s", "asm_s390x.s"}, + } + report := matrixReport{ + Targets: []targetReport{{ + Goos: "linux", + Goarch: "amd64", + AsmFiles: []string{"/go/pkg/mod/example.com/root@v1.0.0/different_amd64.s"}, + TotalAsm: 1, + Success: 1, + }}, + TotalTargets: 1, + TotalAsm: 1, + Success: 1, + } + err := validateDiscoveryReport([]string{"linux/amd64"}, candidate, report) + if err == nil || !strings.Contains(err.Error(), "assembly files were not exercised") { + t.Fatalf("validateDiscoveryReport() error = %v, want unobserved file failure", err) + } + + report.Targets[0].AsmFiles = []string{"/go/pkg/mod/example.com/root@v1.0.0/root_amd64.s"} + if err := validateDiscoveryReport([]string{"linux/amd64"}, candidate, report); err == nil || !strings.Contains(err.Error(), "asm_s390x.s") { + t.Fatalf("validateDiscoveryReport() error = %v, want every candidate file required", err) + } + + filtered := candidate + filtered.AsmFiles = []string{"root_amd64.s"} + if err := validateDiscoveryReport([]string{"linux/amd64"}, filtered, report); err != nil { + t.Fatalf("validateDiscoveryReport() with prefiltered candidate error = %v", err) + } +} + +func TestValidateDiscoveryReportAcceptsOnlyEvidenceBackedTargetNotApplicable(t *testing.T) { + candidate := discoveryCandidate{ + Module: "example.com/root", + Version: "v1.0.0", + AsmFiles: []string{"cross_arch.s"}, + } + report := matrixReport{ + Targets: []targetReport{ + { + Goos: "linux", + Goarch: "amd64", + AsmFiles: []string{"/go/pkg/mod/example.com/root@v1.0.0/cross_arch.s"}, + TotalAsm: 1, + Success: 1, + }, + { + Goos: "linux", + Goarch: "386", + AsmFiles: []string{"/go/pkg/mod/example.com/root@v1.0.0/cross_arch.s"}, + TotalAsm: 1, + NotApplicable: 1, + NotApplicableItems: []targetNotApplicableItem{{ + PkgPath: "example.com/root", + AsmFile: "/go/pkg/mod/example.com/root@v1.0.0/cross_arch.s", + Kind: targetNotApplicableGoTextArgSize, + Symbol: "example.com/root.StructFieldB", + DeclaredArgSize: 25, + ExpectedArgSize: 17, + Reason: "TEXT argument size is incompatible with the Go declaration on 386", + }}, + }, + }, + TotalTargets: 2, + TotalAsm: 2, + Success: 1, + NotApplicable: 1, + } + if err := validateDiscoveryReport([]string{"linux/amd64", "linux/386"}, candidate, report); err != nil { + t.Fatalf("validateDiscoveryReport() error = %v", err) + } + details := collectMatrixNotApplicableItems(report) + if len(details) != 1 || details[0].Target != "linux/386" || details[0].Symbol != "example.com/root.StructFieldB" { + t.Fatalf("not-applicable details = %#v", details) + } + + report.Targets[1].NotApplicableItems[0].Kind = "unsupported_instruction" + if err := validateDiscoveryReport([]string{"linux/amd64", "linux/386"}, candidate, report); err == nil || !strings.Contains(err.Error(), "invalid not-applicable evidence") { + t.Fatalf("validateDiscoveryReport() error = %v, want evidence rejection", err) + } +} + +func TestDiscoveryCorpusReportAccountsForEverySelectedCandidate(t *testing.T) { + report := discoveryCorpusReport{Selected: 7, Passed: 3, Failed: 2, NotApplicable: 2} + if err := validateDiscoveryCorpusAccounting(report); err != nil { + t.Fatal(err) + } + report.NotApplicable-- + if err := validateDiscoveryCorpusAccounting(report); err == nil || !strings.Contains(err.Error(), "accounting mismatch") { + t.Fatalf("validateDiscoveryCorpusAccounting() error = %v, want accounting mismatch", err) + } +} + +func TestDiscoveryCorpusReportAccountingMatchesAuditableResults(t *testing.T) { + report := discoveryCorpusReport{ + Selected: 2, + Passed: 2, + Translations: 3, + Results: []discoveryCorpusResult{ + {Module: "example.com/a", Version: "v1.0.0", Status: discoveryStatusPassed, Translations: 1}, + {Module: "example.com/b", Version: "v1.0.0", Status: discoveryStatusFailed, Translations: 2}, + }, + } + if err := validateDiscoveryCorpusAccounting(report); err == nil || !strings.Contains(err.Error(), "result status counts") { + t.Fatalf("validateDiscoveryCorpusAccounting() error = %v, want status count mismatch", err) + } + + report.Passed = 1 + report.Failed = 1 + report.Translations = 2 + if err := validateDiscoveryCorpusAccounting(report); err == nil || !strings.Contains(err.Error(), "translation counts") { + t.Fatalf("validateDiscoveryCorpusAccounting() error = %v, want translation count mismatch", err) + } +} + +func TestVerifyDiscoveryCorpusReportsRequiresExactLedgerCoverage(t *testing.T) { + ledger := filepath.Join(t.TempDir(), "ledger") + records := filepath.Join(ledger, "records") + if err := os.MkdirAll(records, 0755); err != nil { + t.Fatal(err) + } + candidates := []discoveryCandidate{ + {Module: "example.com/a", Version: "v1.0.0", Architectures: []string{"amd64"}, AsmFiles: []string{"a_amd64.s"}}, + {Module: "example.com/b", Version: "v2.0.0", Architectures: []string{"arm64"}, AsmFiles: []string{"b_arm64.s"}}, + } + for i, candidate := range candidates { + record := discoveryRecord{Kind: "matched", Module: candidate.Module, Version: candidate.Version, Architectures: candidate.Architectures, AsmFiles: candidate.AsmFiles} + data, err := json.Marshal(record) + if err != nil { + t.Fatal(err) + } + writeTestFile(t, filepath.Join(records, fmt.Sprintf("%02d.jsonl", i)), string(data)+"\n") + } + reports := filepath.Join(t.TempDir(), "reports") + if err := os.MkdirAll(reports, 0755); err != nil { + t.Fatal(err) + } + const shardCount = 2 + for shard := 0; shard < shardCount; shard++ { + selected := selectDiscoveryShard(candidates, shard, shardCount) + report := discoveryCorpusReport{ + SchemaVersion: discoveryReportSchema, + Targets: []string{"linux/amd64", "linux/arm64"}, + ShardIndex: shard, + ShardCount: shardCount, + CandidateTotal: len(candidates), + EligibleCandidates: len(candidates), + Selected: len(selected), + Passed: len(selected), + } + for _, candidate := range selected { + report.Results = append(report.Results, discoveryCorpusResult{ + Module: candidate.Module, Version: candidate.Version, Status: discoveryStatusPassed, + DiscoveredAsmFiles: candidate.AsmFiles, Translations: 1, + }) + report.Translations++ + } + data, err := json.Marshal(report) + if err != nil { + t.Fatal(err) + } + writeTestFile(t, filepath.Join(reports, fmt.Sprintf("shard-%d.json", shard)), string(data)+"\n") + } + if err := verifyDiscoveryCorpusReports(ledger, reports, []string{"linux/amd64", "linux/arm64"}); err != nil { + t.Fatalf("complete reports failed verification: %v", err) + } + if err := os.Remove(filepath.Join(reports, "shard-1.json")); err != nil { + t.Fatal(err) + } + if err := verifyDiscoveryCorpusReports(ledger, reports, []string{"linux/amd64", "linux/arm64"}); err == nil || !strings.Contains(err.Error(), "shard reports") { + t.Fatalf("missing shard verification error = %v", err) + } +} + +func TestDiscoveryConfigurationAsmFilesDeduplicatesTargets(t *testing.T) { + configs := []discoveryBuildConfiguration{ + {Targets: []string{"linux/amd64"}, AsmFiles: []string{"pkg/a_amd64.s", "pkg/b.s"}}, + {Targets: []string{"windows/amd64"}, AsmFiles: []string{"pkg/a_amd64.s"}}, + {Targets: []string{"linux/386"}, AsmFiles: []string{"pkg/b.s"}}, + } + want := []string{"pkg/a_amd64.s", "pkg/b.s"} + if got := discoveryConfigurationAsmFiles(configs); !reflect.DeepEqual(got, want) { + t.Fatalf("applicable assembly files = %#v, want %#v", got, want) + } +} + +func TestDiscoveryCorpusReportValidatesSourceNotApplicableEvidence(t *testing.T) { + result := discoveryCorpusResult{ + Module: "example.com/root", + Version: "v1.0.0", + Status: discoveryStatusNotApplicable, + DiscoveredAsmFiles: []string{"pkg/a_amd64.s", "pkg/b.s"}, + SourceNotApplicableItems: []discoverySourceNotApplicableItem{ + {AsmFile: "pkg/a_amd64.s", Targets: []string{"linux/amd64"}, Kind: discoverySourceNotApplicableGoAssembler, Reason: "current Go assembler rejected the source"}, + {AsmFiles: []string{"pkg/b.s"}, Targets: []string{"windows/amd64"}, Kind: discoverySourceNotApplicableGoBuild, Reason: "current Go compiler rejected the exact package"}, + }, + } + report := discoveryCorpusReport{Selected: 1, NotApplicable: 1, Results: []discoveryCorpusResult{result}} + if err := validateDiscoveryCorpusAccounting(report); err != nil { + t.Fatalf("valid source N/A evidence error = %v", err) + } + + invalid := report + invalid.Results = append([]discoveryCorpusResult(nil), report.Results...) + invalid.Results[0].SourceNotApplicableItems = append([]discoverySourceNotApplicableItem(nil), result.SourceNotApplicableItems...) + invalid.Results[0].SourceNotApplicableItems[1].AsmFiles = []string{"pkg/not-discovered.s"} + if err := validateDiscoveryCorpusAccounting(invalid); err == nil || !strings.Contains(err.Error(), "invalid source not-applicable evidence") { + t.Fatalf("validateDiscoveryCorpusAccounting() error = %v, want invalid source evidence", err) + } + + invalid.Results[0].SourceNotApplicableItems[1] = discoverySourceNotApplicableItem{ + AsmFiles: []string{"pkg/b.s"}, Targets: []string{"linux/amd64"}, Kind: "unsupported_instruction", Reason: "not valid N/A evidence", + } + if err := validateDiscoveryCorpusAccounting(invalid); err == nil || !strings.Contains(err.Error(), "invalid source not-applicable evidence") { + t.Fatalf("validateDiscoveryCorpusAccounting() error = %v, want invalid kind rejection", err) + } +} + +func TestTranslatorInvocationAcceptsExactPatterns(t *testing.T) { + invocation := makeTranslatorInvocationForTargetsAndTags( + "/corpus", + "example.com/root", + []string{"example.com/root/internal/...", "example.com/root"}, + []string{"avx", "sse"}, + []string{"linux/amd64", "windows/amd64"}, + []string{"internal/fast.s", "root_amd64.s"}, + "/tmp/out", + "/repo", + "/bin/llc-22", + "/tmp/report.json", + ) + if !containsString(invocation.Args, "-patterns=example.com/root/internal/...,example.com/root") { + t.Fatalf("translator args = %#v, want exact package patterns", invocation.Args) + } + if containsString(invocation.Args, "-strict-load") { + t.Fatalf("discovery translator args = %#v, must tolerate unrelated Go package errors", invocation.Args) + } + if !containsString(invocation.Args, "-tags=avx,sse") { + t.Fatalf("discovery translator args = %#v, want explicit custom build tags", invocation.Args) + } + if !containsString(invocation.Args, "-targets=linux/amd64,windows/amd64") || containsString(invocation.Args, "-all-targets") { + t.Fatalf("discovery translator args = %#v, want only applicable targets", invocation.Args) + } + if !containsString(invocation.Args, "-asm-files=internal/fast.s,root_amd64.s") { + t.Fatalf("discovery translator args = %#v, want exact assembly allowlist", invocation.Args) + } +} + +func TestDiscoveryCommandEnvironmentMatchesCgoDisabledApplicability(t *testing.T) { + env := discoveryCommandEnvironment([]string{ + "CGO_ENABLED=1", + "GOFLAGS=-mod=vendor", + "GOTOOLCHAIN=auto", + "GOWORK=/tmp/work", + }) + want := map[string]string{ + "CGO_ENABLED": "0", + "GOFLAGS": "-mod=mod", + "GOTOOLCHAIN": "local", + "GOWORK": "off", + } + for _, entry := range env { + key, value, ok := strings.Cut(entry, "=") + if ok && want[key] == value { + delete(want, key) + } + } + if len(want) != 0 { + t.Fatalf("discovery command environment omitted required overrides: %v; env=%v", want, env) + } +} + +func writeTestFile(t *testing.T, path, contents string) { + t.Helper() + if err := os.WriteFile(path, []byte(contents), 0644); err != nil { + t.Fatal(err) + } +} diff --git a/cmd/plan9asmcorpus/main.go b/cmd/plan9asmcorpus/main.go index 47dd6f17..c6963843 100644 --- a/cmd/plan9asmcorpus/main.go +++ b/cmd/plan9asmcorpus/main.go @@ -13,6 +13,7 @@ import ( "regexp" "sort" "strings" + "time" ) type corpusManifest struct { @@ -46,21 +47,44 @@ type commandInvocation struct { } type matrixReport struct { - Targets []targetReport `json:"targets"` - TotalTargets int `json:"total_targets"` - TotalAsm int `json:"total_asm"` - Success int `json:"success"` - Failed int `json:"failed"` + Targets []targetReport `json:"targets"` + TotalTargets int `json:"total_targets"` + TotalAsm int `json:"total_asm"` + Success int `json:"success"` + NotApplicable int `json:"not_applicable"` + Failed int `json:"failed"` + NotApplicableItems []matrixTargetNotApplicableItem `json:"not_applicable_items,omitempty"` + SourceNotApplicableItems []discoverySourceNotApplicableItem `json:"source_not_applicable_items,omitempty"` +} + +const targetNotApplicableGoTextArgSize = "go_text_arg_size_mismatch" + +type targetNotApplicableItem struct { + PkgPath string `json:"pkg_path"` + AsmFile string `json:"asm_file"` + Kind string `json:"kind"` + Symbol string `json:"symbol"` + DeclaredArgSize int64 `json:"declared_arg_size"` + ExpectedArgSize int64 `json:"expected_arg_size"` + Reason string `json:"reason"` +} + +type matrixTargetNotApplicableItem struct { + Target string `json:"target"` + targetNotApplicableItem } type targetReport struct { - Goos string `json:"goos"` - Goarch string `json:"goarch"` - TotalPkgs int `json:"total_pkgs"` - AsmPackages []string `json:"asm_packages"` - TotalAsm int `json:"total_asm"` - Success int `json:"success"` - Failed int `json:"failed"` + Goos string `json:"goos"` + Goarch string `json:"goarch"` + TotalPkgs int `json:"total_pkgs"` + AsmPackages []string `json:"asm_packages"` + AsmFiles []string `json:"asm_files"` + TotalAsm int `json:"total_asm"` + Success int `json:"success"` + NotApplicable int `json:"not_applicable"` + Failed int `json:"failed"` + NotApplicableItems []targetNotApplicableItem `json:"not_applicable_items,omitempty"` } var ( @@ -71,6 +95,12 @@ var ( const ( originLLGoIssue = "llgo-issue" originEcosystemScan = "ecosystem-scan" + + // The deadline covers the complete candidate lifecycle: download, current-Go + // build and asmdecl checks, plus every applicable OS/architecture translation. + // Large generated corpora such as reflectx legitimately need more than 15 + // minutes on the shared Linux CI runners. + defaultDiscoveryCandidateTimeout = 60 * time.Minute ) func main() { @@ -82,6 +112,13 @@ func main() { suite := flag.String("suite", "all", "suite id to run, or all") checkLatest := flag.Bool("check-latest", true, "require each pinned module version to equal @latest") list := flag.Bool("list", false, "list suite ids as a JSON array and exit") + discoveryLedger := flag.String("discovery-ledger", "", "run every matched module@version in a discovery ledger instead of the curated manifest") + discoveryTargets := flag.String("discovery-targets", "", "comma-separated target subset for replaying matching discovery records") + discoveryShardIndex := flag.Int("discovery-shard-index", 0, "zero-based discovery candidate shard") + discoveryShardCount := flag.Int("discovery-shard-count", 1, "number of stable discovery candidate shards") + discoveryTimeout := flag.Duration("candidate-timeout", defaultDiscoveryCandidateTimeout, "download, translation, and compilation timeout per discovery candidate") + discoveryReport := flag.String("discovery-report", "", "write the discovery shard result as JSON") + verifyDiscoveryReports := flag.String("verify-discovery-reports", "", "verify a complete directory of discovery shard reports against -discovery-ledger") flag.Parse() manifest, err := loadManifest(*manifestPath) @@ -94,12 +131,42 @@ func main() { check(json.NewEncoder(os.Stdout).Encode(ids)) return } + if *verifyDiscoveryReports != "" { + if *discoveryLedger == "" { + check(errors.New("-verify-discovery-reports requires -discovery-ledger")) + } + check(verifyDiscoveryCorpusReports(*discoveryLedger, *verifyDiscoveryReports, manifest.Targets)) + fmt.Printf("verified discovery corpus reports against %s\n", *discoveryLedger) + return + } if *translator == "" { check(errors.New("-translator is required")) } if *llc == "" { check(errors.New("-llc is required")) } + if *discoveryLedger != "" { + targets := manifest.Targets + filterTargets := false + if *discoveryTargets != "" { + targets, err = parseDiscoveryTargets(*discoveryTargets) + check(err) + filterTargets = true + } + check(runDiscoveryCorpus(discoveryCorpusConfig{ + LedgerPath: *discoveryLedger, + RepoRoot: *repoRoot, + Translator: *translator, + LLC: *llc, + Targets: targets, + FilterTargets: filterTargets, + ShardIndex: *discoveryShardIndex, + ShardCount: *discoveryShardCount, + CandidateTimeout: *discoveryTimeout, + ReportPath: *discoveryReport, + })) + return + } libraries, err := selectLibraries(manifest.Libraries, *suite) check(err) @@ -108,6 +175,29 @@ func main() { } } +func parseDiscoveryTargets(value string) ([]string, error) { + var targets []string + seen := make(map[string]bool) + for _, target := range strings.Split(value, ",") { + target = strings.TrimSpace(target) + if target == "" { + return nil, errors.New("-discovery-targets contains an empty target") + } + if err := validateTarget(target); err != nil { + return nil, err + } + if seen[target] { + return nil, fmt.Errorf("duplicate discovery target %q", target) + } + seen[target] = true + targets = append(targets, target) + } + if len(targets) == 0 { + return nil, errors.New("-discovery-targets must not be empty") + } + return targets, nil +} + func check(err error) { if err != nil { fmt.Fprintln(os.Stderr, err) @@ -300,22 +390,48 @@ func runLibrary(manifest corpusManifest, library libraryManifest, corpusDir, rep if err := validateReport(manifest.Targets, library, report); err != nil { return err } - fmt.Printf("%s: all %d assembly translations passed across %d targets\n", library.ID, report.TotalAsm, report.TotalTargets) + fmt.Printf("%s: all %d assembly translations passed or were evidence-backed N/A across %d targets\n", library.ID, report.TotalAsm, report.TotalTargets) return nil } func makeTranslatorInvocation(corpusDir, modulePath, outDir, repoRoot, llc, reportPath string) commandInvocation { - return commandInvocation{Dir: corpusDir, Args: []string{ - "-all-targets", - "-patterns=" + modulePath + "/...", + invocation := makeTranslatorInvocationForPatterns(corpusDir, modulePath, []string{modulePath + "/..."}, outDir, repoRoot, llc, reportPath) + invocation.Args = append(invocation.Args, "-strict-load") + return invocation +} + +func makeTranslatorInvocationForPatterns(corpusDir, modulePath string, patterns []string, outDir, repoRoot, llc, reportPath string) commandInvocation { + return makeTranslatorInvocationForPatternsAndTags(corpusDir, modulePath, patterns, nil, outDir, repoRoot, llc, reportPath) +} + +func makeTranslatorInvocationForPatternsAndTags(corpusDir, modulePath string, patterns, buildTags []string, outDir, repoRoot, llc, reportPath string) commandInvocation { + return makeTranslatorInvocationForTargetsAndTags(corpusDir, modulePath, patterns, buildTags, nil, nil, outDir, repoRoot, llc, reportPath) +} + +func makeTranslatorInvocationForTargetsAndTags(corpusDir, modulePath string, patterns, buildTags, targets, asmFiles []string, outDir, repoRoot, llc, reportPath string) commandInvocation { + args := []string{ + "-patterns=" + strings.Join(patterns, ","), "-module-path=" + modulePath, - "-out=" + outDir, + } + if len(targets) == 0 { + args = append([]string{"-all-targets"}, args...) + } else { + args = append([]string{"-targets=" + strings.Join(targets, ",")}, args...) + } + if len(buildTags) != 0 { + args = append(args, "-tags="+strings.Join(buildTags, ",")) + } + if len(asmFiles) != 0 { + args = append(args, "-asm-files="+strings.Join(asmFiles, ",")) + } + args = append(args, + "-out="+outDir, "-compile", - "-llc=" + llc, - "-report=" + reportPath, - "-repo-root=" + repoRoot, - "-strict-load", - }} + "-llc="+llc, + "-report="+reportPath, + "-repo-root="+repoRoot, + ) + return commandInvocation{Dir: corpusDir, Args: args} } func queryModule(dir, query string) (moduleInfo, error) { @@ -361,6 +477,7 @@ func validateReport(targets []string, library libraryManifest, report matrixRepo seen := make(map[string]bool, len(targets)) totalAsm := 0 totalSuccess := 0 + totalNotApplicable := 0 for _, actual := range report.Targets { target := actual.Goos + "/" + actual.Goarch if seen[target] { @@ -376,19 +493,23 @@ func validateReport(targets []string, library libraryManifest, report matrixRepo if actual.TotalPkgs != len(actual.AsmPackages) { return fmt.Errorf("%s: %s inconsistent package count: total_pkgs=%d asm_packages=%v", library.ID, target, actual.TotalPkgs, actual.AsmPackages) } - if actual.Failed != 0 || actual.Success != actual.TotalAsm { - return fmt.Errorf("%s: %s failed: success=%d failed=%d total=%d", library.ID, target, actual.Success, actual.Failed, actual.TotalAsm) + if actual.Failed != 0 || actual.Success+actual.NotApplicable != actual.TotalAsm { + return fmt.Errorf("%s: %s failed: success=%d not_applicable=%d failed=%d total=%d", library.ID, target, actual.Success, actual.NotApplicable, actual.Failed, actual.TotalAsm) + } + if err := validateTargetNotApplicableEvidence(actual); err != nil { + return fmt.Errorf("%s: %s: %w", library.ID, target, err) } totalAsm += actual.TotalAsm totalSuccess += actual.Success + totalNotApplicable += actual.NotApplicable } for _, target := range targets { if !seen[target] { return fmt.Errorf("%s: target %s was silently skipped", library.ID, target) } } - if report.TotalAsm != totalAsm || report.Success != totalSuccess || report.Failed != 0 || report.Success != report.TotalAsm { - return fmt.Errorf("%s: inconsistent matrix totals: success=%d failed=%d total=%d", library.ID, report.Success, report.Failed, report.TotalAsm) + if report.TotalAsm != totalAsm || report.Success != totalSuccess || report.NotApplicable != totalNotApplicable || report.Failed != 0 || report.Success+report.NotApplicable != report.TotalAsm { + return fmt.Errorf("%s: inconsistent matrix totals: success=%d not_applicable=%d failed=%d total=%d", library.ID, report.Success, report.NotApplicable, report.Failed, report.TotalAsm) } return nil } diff --git a/cmd/plan9asmcorpus/main_test.go b/cmd/plan9asmcorpus/main_test.go index 1815a31c..9d1ec134 100644 --- a/cmd/plan9asmcorpus/main_test.go +++ b/cmd/plan9asmcorpus/main_test.go @@ -7,6 +7,22 @@ import ( "testing" ) +func TestParseDiscoveryTargets(t *testing.T) { + got, err := parseDiscoveryTargets("linux/amd64, windows/arm64") + if err != nil { + t.Fatal(err) + } + want := []string{"linux/amd64", "windows/arm64"} + if !reflect.DeepEqual(got, want) { + t.Fatalf("parseDiscoveryTargets() = %#v, want %#v", got, want) + } + for _, value := range []string{"linux/amd64,linux/amd64", "linux/amd64,", "linux/riscv64"} { + if _, err := parseDiscoveryTargets(value); err == nil { + t.Errorf("parseDiscoveryTargets(%q) succeeded, want error", value) + } + } +} + func TestRepositoryManifestTracksReportedAssemblyFailures(t *testing.T) { manifest, err := loadManifest(filepath.Join("..", "..", "testdata", "corpus", "reported-libraries.json")) if err != nil { @@ -50,20 +66,24 @@ func TestRepositoryManifestTracksEcosystemDiscoveries(t *testing.T) { t.Fatal(err) } want := map[string]bool{ + "aead-siphash": true, "anacrolix-mmsg": true, "btcsuite-fastsha256": true, "cespare-xxhash-v1": true, "cespare-xxhash-v2": true, + "chain-txvm": true, "dchest-siphash": true, "dgryski-go-bits": true, "dgryski-go-marvin32": true, "golang-snappy": true, "klauspost-cpuid-v1": true, "klauspost-cpuid-v2": true, + "klauspost-crc32": true, "klauspost-reedsolomon": true, "modern-go-gls": true, "minio-highwayhash": true, "pierrec-lz4-v4": true, + "phuslu-log": true, "roaring-bitmap": true, "stevvooe-resumable": true, "tmthrgd-go-bitwise": true, @@ -142,3 +162,43 @@ func TestValidateReportRejectsInventoryDrift(t *testing.T) { t.Fatalf("validateReport() error = %v, want inventory failure", err) } } + +func TestValidateReportAcceptsOnlyEvidenceBackedNotApplicableAssembly(t *testing.T) { + library := libraryManifest{ + ID: "example", + Inventory: map[string]expectedInventory{ + "linux/386": {AsmFiles: 1, Packages: []string{"example.com/lib"}}, + }, + } + report := matrixReport{ + Targets: []targetReport{{ + Goos: "linux", + Goarch: "386", + TotalPkgs: 1, + AsmPackages: []string{"example.com/lib"}, + AsmFiles: []string{"/go/pkg/mod/example.com/lib@v1.0.0/asm_386.s"}, + TotalAsm: 1, + NotApplicable: 1, + NotApplicableItems: []targetNotApplicableItem{{ + PkgPath: "example.com/lib", + AsmFile: "/go/pkg/mod/example.com/lib@v1.0.0/asm_386.s", + Kind: targetNotApplicableGoTextArgSize, + Symbol: "example.com/lib.Block", + DeclaredArgSize: 12, + ExpectedArgSize: 16, + Reason: "TEXT argument size is incompatible with the Go declaration on 386", + }}, + }}, + TotalTargets: 1, + TotalAsm: 1, + NotApplicable: 1, + } + if err := validateReport([]string{"linux/386"}, library, report); err != nil { + t.Fatalf("validateReport() evidence-backed N/A error = %v", err) + } + + report.Targets[0].NotApplicableItems[0].Kind = "unsupported_instruction" + if err := validateReport([]string{"linux/386"}, library, report); err == nil || !strings.Contains(err.Error(), "invalid not-applicable evidence") { + t.Fatalf("validateReport() error = %v, want invalid evidence failure", err) + } +} diff --git a/cmd/plan9asmdiscover/main.go b/cmd/plan9asmdiscover/main.go index eb96ced1..c8bbfd7d 100644 --- a/cmd/plan9asmdiscover/main.go +++ b/cmd/plan9asmdiscover/main.go @@ -7,7 +7,10 @@ import ( "archive/zip" "bufio" "bytes" + "compress/gzip" "context" + "crypto/sha256" + "encoding/binary" "encoding/json" "errors" "flag" @@ -17,25 +20,42 @@ import ( "net/url" "os" "path" + "path/filepath" "sort" + "strconv" "strings" "sync" "time" + + "github.com/xgo-dev/plan9asm/internal/discoverymeta" + "golang.org/x/mod/module" + "golang.org/x/mod/semver" ) const ( defaultIndexURL = "https://index.golang.org/index" defaultProxyURL = "https://proxy.golang.org/cached-only" discoverySchema = 2 + shardedFormat = "plan9asmdiscover-jsonl-v1" indexPageLimit = 2000 defaultScanLimit = 2000 defaultMaxZipSize = 2 << 30 defaultHTTPTimeout = 60 * time.Second - zipDirectoryTail = 8 << 20 - maxAsmProbeSize = 8 << 20 - zipReadAhead = 1 << 20 - httpAttempts = 3 - httpRetryDelay = 100 * time.Millisecond + // ZIP readers need the final 65,557 bytes to locate the end record when + // the archive uses the maximum-length comment. Earlier directory data is + // fetched lazily through ReaderAt. + zipEOCDSize = 22 + zipMaxEOCDSearch = 65_557 + zipSmallWholeLimit = 64 << 10 + maxAsmProbeSize = 8 << 20 + zipReadAhead = 64 << 10 + httpAttempts = 3 + httpRetryDelay = 100 * time.Millisecond + indexEpoch = "2019-04-10T00:00:00Z" + reversePageTarget = indexPageLimit - 1 + scanModeHistory = "history" + scanModeIncremental = "incremental" + scanModeRetry = "retry" ) type indexEntry struct { @@ -53,6 +73,91 @@ type moduleVersion struct { Version string `json:"version"` } +type moduleCheckpoint struct { + Path string + Version string +} + +type scanWindow struct { + Before string + After string +} + +type trafficBucket struct { + Requests int `json:"requests"` + BodyBytes int64 `json:"body_bytes"` +} + +type moduleTraffic struct { + Module string `json:"module"` + IndexedVersion string `json:"indexed_version,omitempty"` + ResolvedVersion string `json:"resolved_version,omitempty"` + Outcome string `json:"outcome,omitempty"` + Latest trafficBucket `json:"latest"` + ZIPHead trafficBucket `json:"zip_head"` + ZIPRange trafficBucket `json:"zip_range"` + ZIPFull trafficBucket `json:"zip_full"` + AdvertisedZIPBytes int64 `json:"advertised_zip_bytes,omitempty"` + TotalRequests int `json:"total_requests"` + TotalBodyBytes int64 `json:"total_body_bytes"` +} + +type trafficReport struct { + SchemaVersion int `json:"schema_version"` + GeneratedAt time.Time `json:"generated_at"` + ByteDefinition string `json:"byte_definition"` + ScanMode string `json:"scan_mode"` + IndexRanges []indexRange `json:"index_ranges,omitempty"` + IndexEntries int `json:"index_entries"` + UniqueModules int `json:"unique_modules"` + Skipped int `json:"skipped"` + Scanned int `json:"scanned"` + Matched int `json:"matched"` + Failures int `json:"failures"` + Index trafficBucket `json:"index"` + Modules []moduleTraffic `json:"modules"` + TotalRequests int `json:"total_requests"` + TotalBodyBytes int64 `json:"total_body_bytes"` +} + +type ledgerSummary struct { + SchemaVersion int `json:"schema_version"` + HistoryBefore string `json:"history_before"` + IncrementalSince string `json:"incremental_since"` + HistoryComplete bool `json:"history_complete"` + IndexRanges int `json:"index_ranges"` + IndexEntries int `json:"index_entries"` + UniqueModules int `json:"unique_modules"` + ScannedRecords int `json:"scanned_records"` + MatchedRecords int `json:"matched_records"` + AssemblyFiles int `json:"assembly_files"` + FailureRecords int `json:"failure_records"` +} + +type trafficCollector struct { + mu sync.Mutex + index trafficBucket + modules map[string]*moduleTraffic +} + +type trafficCollectorContextKey struct{} +type trafficModuleContextKey struct{} + +type trafficReadCloser struct { + io.ReadCloser + collector *trafficCollector + module string + phase string +} + +func (r *trafficReadCloser) Read(p []byte) (int, error) { + n, err := r.ReadCloser.Read(p) + if n > 0 { + r.collector.addBodyBytes(r.module, r.phase, int64(n)) + } + return n, err +} + type candidate struct { Module string `json:"module"` Version string `json:"version"` @@ -66,11 +171,36 @@ type scanFailure struct { Error string `json:"error"` } +type indexRange struct { + Since string `json:"since"` + Before string `json:"before"` + IndexEntries int `json:"index_entries"` +} + +type seenResult struct { + Match candidate +} + +type sourceInspectionFlight struct { + done chan struct{} +} + +type sourceInspectionCache struct { + mu sync.Mutex + completed map[string]seenResult + inFlight map[string]*sourceInspectionFlight +} + type discoveryReport struct { - SchemaVersion int `json:"schema_version"` - GeneratedAt time.Time `json:"generated_at"` + SchemaVersion int `json:"schema_version"` + GeneratedAt time.Time `json:"generated_at"` + // Since, NextSince, and NextBefore are retained only for importing legacy + // reports. Current bidirectional cursors are derived from IndexRanges. Since string `json:"since,omitempty"` NextSince string `json:"next_since,omitempty"` + ScanDirection string `json:"scan_direction,omitempty"` + NextBefore string `json:"next_before,omitempty"` + IndexRanges []indexRange `json:"index_ranges,omitempty"` IndexEntries int `json:"index_entries"` UniqueModules int `json:"unique_modules"` Skipped int `json:"skipped_previously_scanned,omitempty"` @@ -79,188 +209,1627 @@ type discoveryReport struct { Failures []scanFailure `json:"failures,omitempty"` } +type shardedManifest struct { + SchemaVersion int `json:"schema_version"` + Format string `json:"format"` + GeneratedAt time.Time `json:"generated_at"` + Since string `json:"since,omitempty"` + NextSince string `json:"next_since,omitempty"` + ScanDirection string `json:"scan_direction,omitempty"` + NextBefore string `json:"next_before,omitempty"` + IndexRanges []indexRange `json:"index_ranges,omitempty"` + IndexEntries int `json:"index_entries"` + UniqueModules int `json:"unique_modules"` + Skipped int `json:"skipped_previously_scanned,omitempty"` + Scanned int `json:"scanned_records"` + Matched int `json:"matched_records"` + Failures int `json:"failure_records"` + ShardKey string `json:"shard_key"` +} + +type shardedRecord struct { + Kind string `json:"kind"` + Module string `json:"module"` + Version string `json:"version"` + Architectures []string `json:"architectures,omitempty"` + AsmFiles []string `json:"asm_files,omitempty"` + Error string `json:"error,omitempty"` +} + type config struct { - indexURL string - proxyURL string - since string - limit int - workers int - maxZipSize int64 - httpTimeout time.Duration - seen map[string]struct{} + indexURL string + proxyURL string + scanMode string + before string + after string + indexSpanHint time.Duration + limit int + workers int + maxZipSize int64 + httpTimeout time.Duration + seen map[string]seenResult + sourceSeen map[string]seenResult + checkpoints map[string]moduleCheckpoint } type pathListFlag []string +func newTrafficCollector() *trafficCollector { + return &trafficCollector{modules: make(map[string]*moduleTraffic)} +} + +func newSourceInspectionCache(existing map[string]seenResult) *sourceInspectionCache { + completed := make(map[string]seenResult, len(existing)) + for key, result := range existing { + completed[key] = result + } + return &sourceInspectionCache{ + completed: completed, + inFlight: make(map[string]*sourceInspectionFlight), + } +} + +func (c *sourceInspectionCache) inspect(ctx context.Context, key string, inspect func() (candidate, error)) (candidate, bool, error) { + if key == "" { + item, err := inspect() + return item, false, err + } + for { + c.mu.Lock() + if previous, ok := c.completed[key]; ok { + c.mu.Unlock() + return previous.Match, true, nil + } + if flight, ok := c.inFlight[key]; ok { + c.mu.Unlock() + select { + case <-ctx.Done(): + return candidate{}, false, ctx.Err() + case <-flight.done: + } + continue + } + flight := &sourceInspectionFlight{done: make(chan struct{})} + c.inFlight[key] = flight + c.mu.Unlock() + + item, err := inspect() + c.mu.Lock() + if err == nil { + c.completed[key] = seenResult{Match: item} + } + delete(c.inFlight, key) + close(flight.done) + c.mu.Unlock() + return item, false, err + } +} + +func withTrafficModule(ctx context.Context, modulePath string) context.Context { + return context.WithValue(ctx, trafficModuleContextKey{}, modulePath) +} + +func trafficContext(ctx context.Context) (*trafficCollector, string) { + collector, _ := ctx.Value(trafficCollectorContextKey{}).(*trafficCollector) + modulePath, _ := ctx.Value(trafficModuleContextKey{}).(string) + return collector, modulePath +} + +func trafficPhase(modulePath, method, endpoint string, headers http.Header) string { + if modulePath == "" { + return "index" + } + if method == http.MethodHead { + return "zip_head" + } + if strings.HasSuffix(endpoint, "/@latest") { + return "latest" + } + if headers.Get("Range") != "" { + return "zip_range" + } + return "zip_full" +} + +func (c *trafficCollector) bucket(modulePath, phase string) *trafficBucket { + if phase == "index" { + return &c.index + } + item := c.modules[modulePath] + if item == nil { + item = &moduleTraffic{Module: modulePath} + c.modules[modulePath] = item + } + switch phase { + case "latest": + return &item.Latest + case "zip_head": + return &item.ZIPHead + case "zip_range": + return &item.ZIPRange + case "zip_full": + return &item.ZIPFull + default: + panic("unknown discovery traffic phase: " + phase) + } +} + +func (c *trafficCollector) addRequest(modulePath, phase string) { + c.mu.Lock() + defer c.mu.Unlock() + c.bucket(modulePath, phase).Requests++ +} + +func (c *trafficCollector) addBodyBytes(modulePath, phase string, count int64) { + c.mu.Lock() + defer c.mu.Unlock() + c.bucket(modulePath, phase).BodyBytes += count +} + +func (c *trafficCollector) setAdvertisedZIPBytes(modulePath string, size int64) { + c.mu.Lock() + defer c.mu.Unlock() + item := c.modules[modulePath] + if item == nil { + item = &moduleTraffic{Module: modulePath} + c.modules[modulePath] = item + } + if size > item.AdvertisedZIPBytes { + item.AdvertisedZIPBytes = size + } +} + +func (c *trafficCollector) setModuleScan(modulePath, indexedVersion, resolvedVersion, outcome string) { + c.mu.Lock() + defer c.mu.Unlock() + item := c.modules[modulePath] + if item == nil { + item = &moduleTraffic{Module: modulePath} + c.modules[modulePath] = item + } + if indexedVersion != "" { + item.IndexedVersion = indexedVersion + } + if resolvedVersion != "" && resolvedVersion != "@latest" { + item.ResolvedVersion = resolvedVersion + } + if outcome != "" { + item.Outcome = outcome + } +} + +func (c *trafficCollector) snapshot(generatedAt time.Time, scanMode string, discovery discoveryReport) trafficReport { + c.mu.Lock() + defer c.mu.Unlock() + report := trafficReport{ + SchemaVersion: 1, + GeneratedAt: generatedAt, + ByteDefinition: "HTTP response entity bytes read with Accept-Encoding: identity; excludes headers, TLS, and IP overhead", + ScanMode: scanMode, + IndexRanges: append([]indexRange(nil), discovery.IndexRanges...), + IndexEntries: discovery.IndexEntries, + UniqueModules: discovery.UniqueModules, + Skipped: discovery.Skipped, + Scanned: len(discovery.Scanned), + Matched: len(discovery.Matched), + Failures: len(discovery.Failures), + Index: c.index, + } + for _, current := range c.modules { + item := *current + item.TotalRequests = item.Latest.Requests + item.ZIPHead.Requests + item.ZIPRange.Requests + item.ZIPFull.Requests + item.TotalBodyBytes = item.Latest.BodyBytes + item.ZIPHead.BodyBytes + item.ZIPRange.BodyBytes + item.ZIPFull.BodyBytes + report.Modules = append(report.Modules, item) + report.TotalRequests += item.TotalRequests + report.TotalBodyBytes += item.TotalBodyBytes + } + sort.Slice(report.Modules, func(i, j int) bool { return report.Modules[i].Module < report.Modules[j].Module }) + report.TotalRequests += report.Index.Requests + report.TotalBodyBytes += report.Index.BodyBytes + return report +} + +func writeTrafficReport(name string, report trafficReport) error { + if name == "" { + return nil + } + if err := os.MkdirAll(filepath.Dir(name), 0o755); err != nil { + return fmt.Errorf("create traffic report directory: %w", err) + } + file, err := os.CreateTemp(filepath.Dir(name), ".plan9asm-traffic-*.json") + if err != nil { + return fmt.Errorf("create traffic report: %w", err) + } + temporary := file.Name() + defer os.Remove(temporary) + encoder := json.NewEncoder(file) + encoder.SetIndent("", " ") + if err := encoder.Encode(report); err != nil { + file.Close() + return fmt.Errorf("write traffic report: %w", err) + } + if err := file.Close(); err != nil { + return fmt.Errorf("close traffic report: %w", err) + } + if err := os.Rename(temporary, name); err != nil { + return fmt.Errorf("publish traffic report %q: %w", name, err) + } + return nil +} + func (f *pathListFlag) String() string { return strings.Join(*f, ",") } func (f *pathListFlag) Set(value string) error { if strings.TrimSpace(value) == "" { return errors.New("seen report path must not be empty") } - *f = append(*f, value) - return nil + *f = append(*f, value) + return nil +} + +func main() { + indexURL := flag.String("index-url", defaultIndexURL, "Go module index endpoint") + proxyURL := flag.String("proxy-url", defaultProxyURL, "Go module proxy endpoint") + scanMode := flag.String("scan-mode", scanModeHistory, "scan mode: history, incremental, or retry") + before := flag.String("before", "", "optional exclusive upper bound (RFC3339); normally omit so the ledger derives it") + limit := flag.Int("limit", defaultScanLimit, "approximate history records to inspect backwards; timestamp groups are never split; 0 scans history to 2019; ignored for incremental scans") + workers := flag.Int("workers", 8, "concurrent module ZIP inspections") + maxZipSize := flag.Int64("max-zip-bytes", defaultMaxZipSize, "maximum remote module ZIP size considered") + httpTimeout := flag.Duration("http-timeout", defaultHTTPTimeout, "timeout for each index or proxy request") + out := flag.String("out", "", "write JSON to this file instead of stdout") + outDir := flag.String("out-dir", "", "create or update a diff-friendly sharded JSONL ledger directory") + trafficReportPath := flag.String("traffic-report", "", "write per-module HTTP payload accounting JSON") + statusOnly := flag.Bool("status", false, "validate -out-dir and print its derived cursors and record counts without scanning") + convertReport := flag.String("convert-report", "", "convert an existing JSON, JSON.gz, or sharded report into -out-dir") + var seenReports pathListFlag + flag.Var(&seenReports, "seen-report", "prior discovery JSON, JSON.gz, or sharded report directory to skip (repeatable)") + flag.Parse() + if *out != "" && *outDir != "" { + fatal(errors.New("-out and -out-dir are mutually exclusive")) + } + if *statusOnly && (*outDir == "" || *convertReport != "" || *out != "") { + fatal(errors.New("-status requires only an existing -out-dir")) + } + if *convertReport != "" { + if *outDir == "" { + fatal(errors.New("-convert-report requires -out-dir")) + } + report, err := readSeenReport(*convertReport) + if err != nil { + fatal(err) + } + if err := writeShardedReport(*outDir, report); err != nil { + fatal(err) + } + return + } + var existing *discoveryReport + if *outDir != "" { + if info, err := os.Stat(*outDir); err == nil { + if !info.IsDir() { + fatal(fmt.Errorf("-out-dir %q is not a directory", *outDir)) + } + report, err := readShardedReport(*outDir) + if err != nil { + fatal(fmt.Errorf("read -out-dir %q: %w", *outDir, err)) + } + existing = &report + seenReports = append(seenReports, *outDir) + } else if !errors.Is(err, os.ErrNotExist) { + fatal(fmt.Errorf("read -out-dir %q: %w", *outDir, err)) + } + } + if *statusOnly { + if existing == nil { + fatal(fmt.Errorf("-status requires existing -out-dir %q", *outDir)) + } + if err := writeLedgerSummary(os.Stdout, summarizeLedger(*existing)); err != nil { + fatal(err) + } + return + } + var window scanWindow + if *scanMode == scanModeRetry { + if existing == nil { + fatal(errors.New("failure retry requires an existing -out-dir discovery ledger")) + } + } else { + var err error + window, err = resolveScanWindow(existing, *scanMode, *before, time.Now().UTC()) + if err != nil { + fatal(err) + } + } + seen, sourceSeen, err := loadSeenState(seenReports) + if err != nil { + fatal(err) + } + checkpoints, err := loadModuleCheckpoints(seenReports) + if err != nil { + fatal(err) + } + + cfg := config{ + indexURL: *indexURL, + proxyURL: strings.TrimRight(*proxyURL, "/"), + scanMode: *scanMode, + before: window.Before, + after: window.After, + indexSpanHint: reverseIndexSpanHint(existing, window), + limit: scanLimit(*scanMode, *limit), + workers: *workers, + maxZipSize: *maxZipSize, + httpTimeout: *httpTimeout, + seen: seen, + sourceSeen: sourceSeen, + checkpoints: checkpoints, + } + if err := validateConfig(cfg); err != nil { + fatal(err) + } + + ctx := context.Background() + var traffic *trafficCollector + if *trafficReportPath != "" { + traffic = newTrafficCollector() + ctx = context.WithValue(ctx, trafficCollectorContextKey{}, traffic) + } + client := &http.Client{Timeout: cfg.httpTimeout} + var report discoveryReport + if cfg.scanMode == scanModeRetry { + report = retryFailures(ctx, client, cfg, *existing) + } else { + report, err = discover(ctx, client, cfg) + } + if err != nil { + fatal(err) + } + if traffic != nil { + if err := writeTrafficReport(*trafficReportPath, traffic.snapshot(time.Now().UTC(), cfg.scanMode, report)); err != nil { + fatal(err) + } + } + if *outDir != "" { + if err := writeShardedReport(*outDir, report); err != nil { + fatal(err) + } + persisted, err := readShardedReport(*outDir) + if err != nil { + fatal(fmt.Errorf("verify persisted discovery ledger: %w", err)) + } + if err := writeLedgerSummary(os.Stdout, summarizeLedger(persisted)); err != nil { + fatal(err) + } + return + } + var writer io.Writer = os.Stdout + if *out != "" { + file, err := os.Create(*out) + if err != nil { + fatal(err) + } + defer file.Close() + writer = file + } + enc := json.NewEncoder(writer) + enc.SetIndent("", " ") + if err := enc.Encode(report); err != nil { + fatal(err) + } +} + +func summarizeLedger(report discoveryReport) ledgerSummary { + assemblyFiles := 0 + for _, item := range report.Matched { + assemblyFiles += len(item.AsmFiles) + } + historyBefore := earliestIndexRangeLower(report.IndexRanges) + historyTime, historyErr := time.Parse(time.RFC3339Nano, historyBefore) + epoch, epochErr := time.Parse(time.RFC3339Nano, indexEpoch) + return ledgerSummary{ + SchemaVersion: report.SchemaVersion, + HistoryBefore: historyBefore, + IncrementalSince: latestIndexRangeUpper(report.IndexRanges), + HistoryComplete: historyBefore != "" && historyErr == nil && epochErr == nil && !historyTime.After(epoch), + IndexRanges: len(report.IndexRanges), + IndexEntries: report.IndexEntries, + UniqueModules: report.UniqueModules, + ScannedRecords: len(report.Scanned), + MatchedRecords: len(report.Matched), + AssemblyFiles: assemblyFiles, + FailureRecords: len(report.Failures), + } +} + +func writeLedgerSummary(w io.Writer, summary ledgerSummary) error { + encoder := json.NewEncoder(w) + encoder.SetIndent("", " ") + if err := encoder.Encode(summary); err != nil { + return fmt.Errorf("write discovery ledger summary: %w", err) + } + return nil +} + +func fatal(err error) { + fmt.Fprintln(os.Stderr, err) + os.Exit(1) +} + +func validateConfig(cfg config) error { + if _, err := url.ParseRequestURI(cfg.indexURL); err != nil { + return fmt.Errorf("invalid index URL: %w", err) + } + if _, err := url.ParseRequestURI(cfg.proxyURL); err != nil { + return fmt.Errorf("invalid proxy URL: %w", err) + } + if cfg.scanMode != scanModeHistory && cfg.scanMode != scanModeIncremental && cfg.scanMode != scanModeRetry { + return fmt.Errorf("invalid -scan-mode %q: want %s, %s, or %s", cfg.scanMode, scanModeHistory, scanModeIncremental, scanModeRetry) + } + if cfg.scanMode != scanModeRetry { + if _, err := time.Parse(time.RFC3339Nano, cfg.before); err != nil { + return fmt.Errorf("invalid -before timestamp: %w", err) + } + after, err := time.Parse(time.RFC3339Nano, cfg.after) + if err != nil { + return fmt.Errorf("invalid lower index bound: %w", err) + } + before, _ := time.Parse(time.RFC3339Nano, cfg.before) + if before.Before(after) { + return errors.New("index upper bound must not precede its lower bound") + } + } + if cfg.limit < 0 { + return errors.New("-limit must be nonnegative") + } + if cfg.workers <= 0 { + return errors.New("-workers must be positive") + } + if cfg.maxZipSize <= 0 { + return errors.New("-max-zip-bytes must be positive") + } + if cfg.httpTimeout <= 0 { + return errors.New("-http-timeout must be positive") + } + return nil +} + +func scanLimit(mode string, requested int) int { + if mode == scanModeIncremental { + return 0 + } + return requested +} + +func resolveScanWindow(existing *discoveryReport, mode, requestedBefore string, now time.Time) (scanWindow, error) { + if mode != scanModeHistory && mode != scanModeIncremental { + return scanWindow{}, fmt.Errorf("invalid -scan-mode %q: want %s or %s", mode, scanModeHistory, scanModeIncremental) + } + if mode == scanModeHistory { + derived := "" + if existing != nil { + derived = earliestIndexRangeLower(existing.IndexRanges) + if derived == "" { + derived = existing.NextBefore + } + } + if requestedBefore != "" && derived != "" && requestedBefore != derived { + return scanWindow{}, fmt.Errorf("-before %q does not match derived history cursor %q; omit -before to continue without a gap", requestedBefore, derived) + } + before := requestedBefore + if before == "" { + before = derived + } + if before == "" { + before = now.UTC().Format(time.RFC3339Nano) + } + return scanWindow{Before: before, After: indexEpoch}, nil + } + after := "" + if existing != nil { + after = latestIndexRangeUpper(existing.IndexRanges) + if after == "" && !existing.GeneratedAt.IsZero() { + after = existing.GeneratedAt.UTC().Format(time.RFC3339Nano) + } + } + if after == "" { + after = now.UTC().Format(time.RFC3339Nano) + } + before := requestedBefore + if before == "" { + before = now.UTC().Format(time.RFC3339Nano) + } + return scanWindow{Before: before, After: after}, nil +} + +func retryFailures(ctx context.Context, client *http.Client, cfg config, existing discoveryReport) discoveryReport { + modules := modulesForFailureRetry(existing) + matched, failures, scanned, skipped := inspectModules( + ctx, client, cfg.proxyURL, modules, cfg.seen, cfg.sourceSeen, cfg.workers, cfg.maxZipSize, + ) + return discoveryReport{ + SchemaVersion: discoverySchema, + GeneratedAt: time.Now().UTC(), + UniqueModules: len(modules), + Skipped: skipped, + Scanned: scanned, + Matched: matched, + Failures: failures, + } +} + +func modulesForFailureRetry(report discoveryReport) []moduleVersion { + checkpoints := make(map[string]moduleCheckpoint) + for _, item := range report.Failures { + chooseModuleCheckpoint(checkpoints, item.Module, item.Version) + } + modules := make([]moduleVersion, 0, len(checkpoints)) + for _, item := range checkpoints { + modules = append(modules, moduleVersion{Path: item.Path, Version: item.Version}) + } + sort.Slice(modules, func(i, j int) bool { return modules[i].Path < modules[j].Path }) + return modules +} + +func latestIndexRangeUpper(ranges []indexRange) string { + var latest string + for _, item := range ranges { + if latest == "" || timestampBefore(latest, item.Before) { + latest = item.Before + } + } + return latest +} + +func earliestIndexRangeLower(ranges []indexRange) string { + var earliest string + for _, item := range ranges { + if earliest == "" || timestampBefore(item.Since, earliest) { + earliest = item.Since + } + } + return earliest +} + +func reverseIndexSpanHint(existing *discoveryReport, window scanWindow) time.Duration { + if existing == nil { + return time.Hour + } + for _, item := range existing.IndexRanges { + if item.IndexEntries <= 0 || item.Since != window.Before && item.Before != window.After { + continue + } + since, sinceErr := time.Parse(time.RFC3339Nano, item.Since) + before, beforeErr := time.Parse(time.RFC3339Nano, item.Before) + if sinceErr != nil || beforeErr != nil || !before.After(since) { + continue + } + hint := time.Duration(float64(before.Sub(since)) * float64(reversePageTarget) / float64(item.IndexEntries)) + if hint > 0 { + return hint + } + } + return time.Hour +} + +func discover(ctx context.Context, client *http.Client, cfg config) (discoveryReport, error) { + entries, nextBefore, err := readIndexBackwardsFromWithHint(ctx, client, cfg.indexURL, cfg.before, cfg.after, cfg.limit, cfg.indexSpanHint) + if err != nil { + return discoveryReport{}, err + } + if err := validateFetchedIndexWindow(entries, nextBefore, cfg.before, cfg.after); err != nil { + return discoveryReport{}, err + } + modules, skippedModules := modulesNeedingInspection(entries, cfg.checkpoints) + uniqueModules := len(modules) + skippedModules + + matched, failures, scanned, skipped := inspectModules(ctx, client, cfg.proxyURL, modules, cfg.seen, cfg.sourceSeen, cfg.workers, cfg.maxZipSize) + report := discoveryReport{ + SchemaVersion: discoverySchema, + GeneratedAt: time.Now().UTC(), + ScanDirection: cfg.scanMode, + IndexEntries: len(entries), + UniqueModules: uniqueModules, + Skipped: skippedModules + skipped, + Scanned: scanned, + Matched: matched, + Failures: failures, + } + report.IndexRanges = []indexRange{{ + Since: nextBefore, Before: cfg.before, IndexEntries: len(entries), + }} + return report, nil +} + +func validateFetchedIndexWindow(entries []indexEntry, nextBefore, before, after string) error { + nextTime, err := time.Parse(time.RFC3339Nano, nextBefore) + if err != nil { + return fmt.Errorf("invalid returned index cursor %q: %w", nextBefore, err) + } + beforeTime, err := time.Parse(time.RFC3339Nano, before) + if err != nil { + return fmt.Errorf("invalid index upper bound %q: %w", before, err) + } + afterTime, err := time.Parse(time.RFC3339Nano, after) + if err != nil { + return fmt.Errorf("invalid index lower bound %q: %w", after, err) + } + if nextTime.Before(afterTime) || nextTime.After(beforeTime) { + return fmt.Errorf("returned index cursor %s is outside requested interval [%s,%s)", nextBefore, after, before) + } + if len(entries) == 0 { + if !nextTime.Equal(afterTime) { + return fmt.Errorf("empty index result stopped at %s instead of lower bound %s", nextBefore, after) + } + return nil + } + if !entries[0].Timestamp.Equal(nextTime) { + return fmt.Errorf("returned index cursor %s does not equal first complete timestamp group %s", nextBefore, entries[0].Timestamp.Format(time.RFC3339Nano)) + } + for i, entry := range entries { + if entry.Timestamp.Before(nextTime) || !entry.Timestamp.Before(beforeTime) { + return fmt.Errorf("index entry %s@%s timestamp %s is outside committed interval [%s,%s)", entry.Path, entry.Version, entry.Timestamp.Format(time.RFC3339Nano), nextBefore, before) + } + if i > 0 && entry.Timestamp.Before(entries[i-1].Timestamp) { + return fmt.Errorf("index result is not ordered at %s@%s", entry.Path, entry.Version) + } + } + return nil +} + +func modulesNeedingInspection(entries []indexEntry, checkpoints map[string]moduleCheckpoint) ([]moduleVersion, int) { + moduleSet := make(map[string]string, len(entries)) + for _, entry := range entries { + // Module-path major has priority across a family; within one exact path, + // retain the greatest Go semantic version regardless of index arrival + // order. The index entry only triggers a fresh @latest resolution. + if previous, ok := moduleSet[entry.Path]; !ok || compareModuleVersions(previous, entry.Version) < 0 { + moduleSet[entry.Path] = entry.Version + } + } + families := make(map[string]moduleVersion, len(moduleSet)) + for modulePath, indexedVersion := range moduleSet { + item := moduleVersion{Path: modulePath, Version: indexedVersion} + family := moduleFamily(modulePath) + if previous, ok := families[family]; !ok || compareModuleCandidates(previous, item) < 0 { + families[family] = item + } + } + modules := make([]moduleVersion, 0, len(families)) + skipped := len(moduleSet) - len(families) + for family, item := range families { + checkpoint, ok := checkpoints[family] + if ok && !indexedVersionMayBeNewer(item, checkpoint) { + skipped++ + continue + } + modules = append(modules, item) + } + sort.Slice(modules, func(i, j int) bool { return modules[i].Path < modules[j].Path }) + return modules, skipped +} + +func indexedVersionMayBeNewer(indexed moduleVersion, checkpoint moduleCheckpoint) bool { + if checkpoint.Version == "@latest" && indexed.Path == checkpoint.Path { + return false + } + return compareModuleCandidates( + moduleVersion{Path: checkpoint.Path, Version: checkpoint.Version}, + indexed, + ) < 0 +} + +func loadSeenReports(paths []string) (map[string]seenResult, error) { + seen, _, err := loadSeenState(paths) + return seen, err +} + +func loadSeenState(paths []string) (map[string]seenResult, map[string]seenResult, error) { + seen := make(map[string]seenResult) + sourceSeen := make(map[string]seenResult) + for _, reportPath := range paths { + report, err := readSeenReport(reportPath) + if err != nil { + return nil, nil, err + } + for _, item := range report.Scanned { + if item.Path == "" || item.Version == "" { + return nil, nil, fmt.Errorf("seen report %q contains an incomplete scanned version", reportPath) + } + rememberSeenResult(seen, scanKey(item), seenResult{}) + rememberSeenResult(sourceSeen, sourceScanKey(item), seenResult{}) + } + // Older reports did not contain the complete scanned set, but their + // successful matches are still safe to reuse. + for _, item := range report.Matched { + if item.Module != "" && item.Version != "" { + version := moduleVersion{Path: item.Module, Version: item.Version} + result := seenResult{Match: item} + rememberSeenResult(seen, scanKey(version), result) + rememberSeenResult(sourceSeen, sourceScanKey(version), result) + } + } + } + return seen, sourceSeen, nil +} + +func rememberSeenResult(seen map[string]seenResult, key string, result seenResult) { + if key == "" { + return + } + previous, ok := seen[key] + if !ok || previous.Match.Module == "" || result.Match.Module != "" { + seen[key] = result + } +} + +func sourceScanKey(item moduleVersion) string { + if !module.IsPseudoVersion(item.Version) { + return "" + } + revision, err := module.PseudoVersionRev(item.Version) + if err != nil || revision == "" { + return "" + } + parts := strings.Split(item.Path, "/") + if len(parts) < 3 || !strings.EqualFold(parts[0], "github.com") { + return "" + } + canonical := "github.com/" + strings.ToLower(parts[1]) + "/" + strings.ToLower(parts[2]) + if len(parts) > 3 { + canonical += "/" + strings.Join(parts[3:], "/") + } + return "source\x00" + canonical + "\x00" + revision +} + +func loadModuleCheckpoints(paths []string) (map[string]moduleCheckpoint, error) { + checkpoints := make(map[string]moduleCheckpoint) + for _, reportPath := range paths { + report, err := readSeenReport(reportPath) + if err != nil { + return nil, err + } + for _, checkpoint := range moduleCheckpoints(report) { + chooseModuleCheckpoint(checkpoints, checkpoint.Path, checkpoint.Version) + } + } + return checkpoints, nil +} + +func moduleCheckpoints(report discoveryReport) map[string]moduleCheckpoint { + checkpoints := make(map[string]moduleCheckpoint) + for _, item := range report.Scanned { + chooseModuleCheckpoint(checkpoints, item.Path, item.Version) + } + for _, item := range report.Matched { + chooseModuleCheckpoint(checkpoints, item.Module, item.Version) + } + for _, item := range report.Failures { + chooseModuleCheckpoint(checkpoints, item.Module, item.Version) + } + return checkpoints +} + +func chooseModuleCheckpoint(checkpoints map[string]moduleCheckpoint, modulePath, version string) { + if modulePath == "" || version == "" { + return + } + family := moduleFamily(modulePath) + candidate := moduleCheckpoint{Path: modulePath, Version: version} + previous, ok := checkpoints[family] + if !ok || compareModuleCheckpoints(previous, candidate) < 0 { + checkpoints[family] = candidate + } +} + +func moduleFamily(modulePath string) string { + prefix, _, ok := module.SplitPathVersion(modulePath) + if ok { + return prefix + } + return modulePath +} + +func compareModuleCandidates(a, b moduleVersion) int { + return compareModuleCheckpoints( + moduleCheckpoint{Path: a.Path, Version: a.Version}, + moduleCheckpoint{Path: b.Path, Version: b.Version}, + ) +} + +func compareModuleCheckpoints(a, b moduleCheckpoint) int { + if a.Path == b.Path && (a.Version == "@latest" || b.Version == "@latest") { + if a.Version == b.Version { + return 0 + } + if a.Version == "@latest" { + return 1 + } + return -1 + } + aMajor := moduleMajor(a.Path, a.Version) + bMajor := moduleMajor(b.Path, b.Version) + if aMajor != bMajor { + if aMajor < bMajor { + return -1 + } + return 1 + } + if a.Version == "@latest" || b.Version == "@latest" { + if a.Version == b.Version { + return strings.Compare(a.Path, b.Path) + } + if a.Version == "@latest" { + return 1 + } + return -1 + } + if compared := compareModuleVersions(a.Version, b.Version); compared != 0 { + return compared + } + return strings.Compare(a.Path, b.Path) +} + +func moduleMajor(modulePath, version string) int { + _, pathMajor, ok := module.SplitPathVersion(modulePath) + if ok && pathMajor != "" { + raw := strings.TrimPrefix(strings.TrimPrefix(pathMajor, "/v"), ".v") + if major, err := strconv.Atoi(raw); err == nil { + return major + } + } + major := strings.TrimPrefix(semver.Major(version), "v") + parsed, _ := strconv.Atoi(major) + return parsed +} + +func readSeenReport(reportPath string) (discoveryReport, error) { + info, err := os.Stat(reportPath) + if err != nil { + return discoveryReport{}, fmt.Errorf("read seen report %q: %w", reportPath, err) + } + if info.IsDir() { + return readShardedReports(reportPath) + } + data, err := os.ReadFile(reportPath) + if err != nil { + return discoveryReport{}, fmt.Errorf("read seen report %q: %w", reportPath, err) + } + if bytes.HasPrefix(data, []byte{0x1f, 0x8b}) { + reader, err := gzip.NewReader(bytes.NewReader(data)) + if err != nil { + return discoveryReport{}, fmt.Errorf("decompress seen report %q: %w", reportPath, err) + } + data, err = io.ReadAll(reader) + _ = reader.Close() + if err != nil { + return discoveryReport{}, fmt.Errorf("decompress seen report %q: %w", reportPath, err) + } + } + var report discoveryReport + if err := json.Unmarshal(data, &report); err != nil { + return discoveryReport{}, fmt.Errorf("decode seen report %q: %w", reportPath, err) + } + return report, nil +} + +func writeShardedReport(reportPath string, report discoveryReport) (returnErr error) { + release, err := acquireLedgerLock(reportPath) + if err != nil { + return err + } + defer func() { + if err := release(); returnErr == nil && err != nil { + returnErr = err + } + }() + + exists := false + if info, err := os.Stat(reportPath); err == nil { + if !info.IsDir() { + return fmt.Errorf("write sharded report %q: path already exists and is not a directory", reportPath) + } + existing, err := readShardedReport(reportPath) + if err != nil { + return fmt.Errorf("update sharded report %q: %w", reportPath, err) + } + report, err = mergeDiscoveryReports(existing, report) + if err != nil { + return fmt.Errorf("update sharded report %q: %w", reportPath, err) + } + exists = true + } else if !errors.Is(err, os.ErrNotExist) { + return fmt.Errorf("write sharded report %q: %w", reportPath, err) + } else { + var mergeErr error + report, mergeErr = mergeDiscoveryReports(discoveryReport{}, report) + if mergeErr != nil { + return fmt.Errorf("write sharded report %q: %w", reportPath, mergeErr) + } + } + + parent := filepath.Dir(reportPath) + if err := os.MkdirAll(parent, 0o755); err != nil { + return fmt.Errorf("create sharded report parent %q: %w", parent, err) + } + temporary, err := os.MkdirTemp(parent, ".plan9asmdiscover-*") + if err != nil { + return fmt.Errorf("create temporary sharded report: %w", err) + } + defer os.RemoveAll(temporary) + + records := make(map[byte][]shardedRecord) + add := func(record shardedRecord) { + hash := sha256.Sum256([]byte(record.Module)) + records[hash[0]] = append(records[hash[0]], record) + } + for _, item := range report.Scanned { + add(shardedRecord{Kind: "scanned", Module: item.Path, Version: item.Version}) + } + for _, item := range report.Matched { + add(shardedRecord{ + Kind: "matched", + Module: item.Module, + Version: item.Version, + Architectures: item.Architectures, + AsmFiles: item.AsmFiles, + }) + } + for _, item := range report.Failures { + add(shardedRecord{Kind: "failure", Module: item.Module, Version: item.Version, Error: item.Error}) + } + + recordsDir := filepath.Join(temporary, "records") + if err := os.Mkdir(recordsDir, 0o755); err != nil { + return fmt.Errorf("create record shard directory: %w", err) + } + shards := make([]int, 0, len(records)) + for shard := range records { + shards = append(shards, int(shard)) + } + sort.Ints(shards) + for _, shard := range shards { + items := records[byte(shard)] + sort.Slice(items, func(i, j int) bool { + return compareShardedRecords(items[i], items[j]) < 0 + }) + name := filepath.Join(recordsDir, fmt.Sprintf("%02x.jsonl", shard)) + file, err := os.OpenFile(name, os.O_CREATE|os.O_EXCL|os.O_WRONLY, 0o644) + if err != nil { + return fmt.Errorf("create record shard %q: %w", name, err) + } + encoder := json.NewEncoder(file) + for _, item := range items { + if err := encoder.Encode(item); err != nil { + file.Close() + return fmt.Errorf("write record shard %q: %w", name, err) + } + } + if err := file.Close(); err != nil { + return fmt.Errorf("close record shard %q: %w", name, err) + } + } + + manifest := shardedManifest{ + SchemaVersion: report.SchemaVersion, + Format: shardedFormat, + GeneratedAt: report.GeneratedAt, + Since: report.Since, + NextSince: report.NextSince, + ScanDirection: report.ScanDirection, + NextBefore: report.NextBefore, + IndexRanges: report.IndexRanges, + IndexEntries: report.IndexEntries, + UniqueModules: report.UniqueModules, + Skipped: report.Skipped, + Scanned: len(report.Scanned), + Matched: len(report.Matched), + Failures: len(report.Failures), + ShardKey: "sha256(module)[0]", + } + manifestFile, err := os.OpenFile(filepath.Join(temporary, "manifest.json"), os.O_CREATE|os.O_EXCL|os.O_WRONLY, 0o644) + if err != nil { + return fmt.Errorf("create sharded report manifest: %w", err) + } + encoder := json.NewEncoder(manifestFile) + encoder.SetIndent("", " ") + if err := encoder.Encode(manifest); err != nil { + manifestFile.Close() + return fmt.Errorf("write sharded report manifest: %w", err) + } + if err := manifestFile.Close(); err != nil { + return fmt.Errorf("close sharded report manifest: %w", err) + } + if !exists { + if err := os.Rename(temporary, reportPath); err != nil { + return fmt.Errorf("publish sharded report %q: %w", reportPath, err) + } + return nil + } + backup := temporary + "-previous" + if err := os.Rename(reportPath, backup); err != nil { + return fmt.Errorf("replace sharded report %q: preserve previous ledger: %w", reportPath, err) + } + if err := os.Rename(temporary, reportPath); err != nil { + if restoreErr := os.Rename(backup, reportPath); restoreErr != nil { + return fmt.Errorf("replace sharded report %q: %v (also failed to restore previous ledger: %v)", reportPath, err, restoreErr) + } + return fmt.Errorf("replace sharded report %q: %w", reportPath, err) + } + if err := os.RemoveAll(backup); err != nil { + return fmt.Errorf("remove previous sharded report %q after replacement: %w", backup, err) + } + return nil +} + +func acquireLedgerLock(reportPath string) (func() error, error) { + parent := filepath.Dir(reportPath) + if err := os.MkdirAll(parent, 0o755); err != nil { + return nil, fmt.Errorf("create ledger parent %q: %w", parent, err) + } + lockPath := filepath.Join(parent, "."+filepath.Base(reportPath)+".writer-lock") + if err := os.Mkdir(lockPath, 0o700); err != nil { + if errors.Is(err, os.ErrExist) { + return nil, fmt.Errorf("another discovery writer holds %q; do not update one ledger concurrently", lockPath) + } + return nil, fmt.Errorf("lock discovery ledger %q: %w", reportPath, err) + } + return func() error { + if err := os.Remove(lockPath); err != nil { + return fmt.Errorf("unlock discovery ledger %q: %w", reportPath, err) + } + return nil + }, nil +} + +func upgradeDiscoveryReport(report discoveryReport) (discoveryReport, error) { + switch report.SchemaVersion { + case 0: + report.SchemaVersion = discoverySchema + case discoverySchema: + default: + return discoveryReport{}, fmt.Errorf("unsupported discovery schema %d", report.SchemaVersion) + } + if len(report.IndexRanges) == 0 { + report.SchemaVersion = discoverySchema + return report, nil + } + ranges, err := mergeIndexRanges(report.IndexRanges) + if err != nil { + return discoveryReport{}, err + } + report.IndexRanges = ranges + report.Since = "" + report.NextSince = "" + report.NextBefore = "" + report.ScanDirection = "bidirectional" + if err := validateIndexCoverage(report.IndexRanges); err != nil { + return discoveryReport{}, err + } + return report, nil +} + +func validateIndexCoverage(ranges []indexRange) error { + for i := 1; i < len(ranges); i++ { + if timestampBefore(ranges[i].Since, ranges[i-1].Since) { + return fmt.Errorf("index ranges are not in chronological order at [%s,%s)", ranges[i].Since, ranges[i].Before) + } + if ranges[i-1].Before != ranges[i].Since { + return fmt.Errorf("index ranges [%s,%s) and [%s,%s) leave an unverified gap", ranges[i-1].Since, ranges[i-1].Before, ranges[i].Since, ranges[i].Before) + } + } + return nil +} + +func mergeDiscoveryReports(base, update discoveryReport) (discoveryReport, error) { + var err error + base, err = upgradeDiscoveryReport(base) + if err != nil { + return discoveryReport{}, fmt.Errorf("upgrade base discovery report: %w", err) + } + update, err = upgradeDiscoveryReport(update) + if err != nil { + return discoveryReport{}, fmt.Errorf("upgrade update discovery report: %w", err) + } + merged := discoveryReport{SchemaVersion: discoverySchema} + merged.GeneratedAt = base.GeneratedAt + if update.GeneratedAt.After(merged.GeneratedAt) { + merged.GeneratedAt = update.GeneratedAt + } + merged.Since = earlierTimestamp(base.Since, update.Since) + merged.NextSince = laterTimestamp(base.NextSince, update.NextSince) + merged.ScanDirection = base.ScanDirection + if update.ScanDirection != "" { + merged.ScanDirection = update.ScanDirection + } + merged.IndexRanges, err = mergeIndexRanges(base.IndexRanges, update.IndexRanges) + if err != nil { + return discoveryReport{}, err + } + if len(merged.IndexRanges) > 0 { + merged.ScanDirection = "bidirectional" + merged.Since = "" + merged.NextSince = "" + merged.NextBefore = "" + if err := validateIndexCoverage(merged.IndexRanges); err != nil { + return discoveryReport{}, err + } + for _, item := range merged.IndexRanges { + merged.IndexEntries += item.IndexEntries + } + } else { + overlaps := discoveryRangesOverlap(base.Since, base.NextSince, update.Since, update.NextSince) + merged.IndexEntries = mergeRunCount(base.IndexEntries, update.IndexEntries, overlaps) + } + overlaps := discoveryRangesOverlap(base.Since, base.NextSince, update.Since, update.NextSince) || + indexRangeSetsOverlap(base.IndexRanges, update.IndexRanges) + if len(merged.IndexRanges) > 0 && len(base.IndexRanges) == 0 && len(update.IndexRanges) > 0 { + // The first reverse range replaces the unprovable aggregate statistics + // from legacy forward windows. + merged.Skipped = update.Skipped + } else { + merged.Skipped = mergeRunCount(base.Skipped, update.Skipped, overlaps) + } + + scanned := make(map[string]moduleVersion, len(base.Scanned)+len(update.Scanned)+len(base.Matched)+len(update.Matched)) + failures := make(map[string]scanFailure, len(base.Failures)+len(update.Failures)) + type candidateSets struct { + candidate candidate + arches map[string]bool + asmFiles map[string]bool + } + // The active record for a module family is selected by module-path major + // first and Go semantic version second, across both sides of the merge. + // This is deliberately monotonic while history is scanned backwards: an + // older index window may introduce /v3 after /v2 was already inspected, + // but a still older /v2 record can never displace that /v3 checkpoint. + // Exact failures participate too, keeping the highest version retryable. + authoritative := make(map[string]moduleCheckpoint) + for _, report := range []discoveryReport{base, update} { + for _, item := range report.Scanned { + chooseAuthoritativeVersion(authoritative, item.Path, item.Version) + } + for _, item := range report.Matched { + chooseAuthoritativeVersion(authoritative, item.Module, item.Version) + } + for _, item := range report.Failures { + chooseAuthoritativeVersion(authoritative, item.Module, item.Version) + } + } + resolvedByUpdate := make(map[string]bool) + markResolvedByUpdate := func(modulePath, version string) { + if !semver.IsValid(version) { + return + } + family := moduleFamily(modulePath) + latest := authoritative[family] + if latest.Path == modulePath && latest.Version == version { + resolvedByUpdate[family] = true + } + } + for _, item := range update.Scanned { + markResolvedByUpdate(item.Path, item.Version) + } + for _, item := range update.Matched { + markResolvedByUpdate(item.Module, item.Version) + } + for _, item := range update.Failures { + markResolvedByUpdate(item.Module, item.Version) + } + keep := func(isUpdate bool, modulePath, version string) bool { + latest, ok := authoritative[moduleFamily(modulePath)] + if version == "@latest" { + // A current resolution failure remains retryable alongside the last + // known exact result. Only an authoritative exact resolution in this + // update removes it; unrelated history batches must preserve it. + return isUpdate || !resolvedByUpdate[moduleFamily(modulePath)] + } + return !ok || modulePath == latest.Path && version == latest.Version + } + matched := make(map[string]*candidateSets, len(base.Matched)+len(update.Matched)) + addCandidate := func(item candidate) { + key := scanKey(moduleVersion{Path: item.Module, Version: item.Version}) + set := matched[key] + if set == nil { + set = &candidateSets{ + candidate: candidate{Module: item.Module, Version: item.Version}, + arches: make(map[string]bool), + asmFiles: make(map[string]bool), + } + matched[key] = set + } + for _, arch := range item.Architectures { + set.arches[arch] = true + } + for _, asmFile := range item.AsmFiles { + set.asmFiles[asmFile] = true + } + scanned[key] = moduleVersion{Path: item.Module, Version: item.Version} + } + for reportIndex, report := range []discoveryReport{base, update} { + isUpdate := reportIndex == 1 + for _, item := range report.Scanned { + if !keep(isUpdate, item.Path, item.Version) { + continue + } + scanned[scanKey(item)] = item + } + for _, item := range report.Matched { + if !keep(isUpdate, item.Module, item.Version) { + continue + } + addCandidate(item) + } + for _, item := range report.Failures { + if !keep(isUpdate, item.Module, item.Version) { + continue + } + failures[scanKey(moduleVersion{Path: item.Module, Version: item.Version})] = item + } + } + modules := make(map[string]bool) + for key, item := range scanned { + merged.Scanned = append(merged.Scanned, item) + modules[item.Path] = true + delete(failures, key) + } + for _, set := range matched { + for arch := range set.arches { + set.candidate.Architectures = append(set.candidate.Architectures, arch) + } + for asmFile := range set.asmFiles { + set.candidate.AsmFiles = append(set.candidate.AsmFiles, asmFile) + } + merged.Matched = append(merged.Matched, set.candidate) + modules[set.candidate.Module] = true + } + for _, item := range failures { + merged.Failures = append(merged.Failures, item) + modules[item.Module] = true + } + merged.UniqueModules = len(modules) + sortDiscoveryReport(&merged) + return merged, nil } -func main() { - indexURL := flag.String("index-url", defaultIndexURL, "Go module index endpoint") - proxyURL := flag.String("proxy-url", defaultProxyURL, "Go module proxy endpoint") - since := flag.String("since", "", "oldest index timestamp (RFC3339); empty starts at the beginning") - limit := flag.Int("limit", defaultScanLimit, "maximum index records to inspect; 0 scans until the feed ends") - workers := flag.Int("workers", 8, "concurrent module ZIP inspections") - maxZipSize := flag.Int64("max-zip-bytes", defaultMaxZipSize, "maximum remote module ZIP size considered") - httpTimeout := flag.Duration("http-timeout", defaultHTTPTimeout, "timeout for each index or proxy request") - out := flag.String("out", "", "write JSON to this file instead of stdout") - var seenReports pathListFlag - flag.Var(&seenReports, "seen-report", "prior discovery report to skip (repeatable)") - flag.Parse() - seen, err := loadSeenReports(seenReports) - if err != nil { - fatal(err) +func indexRangeSetsOverlap(a, b []indexRange) bool { + for _, left := range a { + for _, right := range b { + if timestampBefore(left.Since, right.Before) && timestampBefore(right.Since, left.Before) { + return true + } + } } + return false +} - cfg := config{ - indexURL: *indexURL, - proxyURL: strings.TrimRight(*proxyURL, "/"), - since: *since, - limit: *limit, - workers: *workers, - maxZipSize: *maxZipSize, - httpTimeout: *httpTimeout, - seen: seen, +func chooseAuthoritativeVersion(versions map[string]moduleCheckpoint, modulePath, version string) { + if modulePath == "" || !semver.IsValid(version) { + return } - if err := validateConfig(cfg); err != nil { - fatal(err) + family := moduleFamily(modulePath) + candidate := moduleCheckpoint{Path: modulePath, Version: version} + if previous, ok := versions[family]; !ok || compareModuleCheckpoints(previous, candidate) < 0 { + versions[family] = candidate } +} - ctx := context.Background() - client := &http.Client{Timeout: cfg.httpTimeout} - report, err := discover(ctx, client, cfg) - if err != nil { - fatal(err) - } - var writer io.Writer = os.Stdout - if *out != "" { - file, err := os.Create(*out) - if err != nil { - fatal(err) +func mergeIndexRanges(groups ...[]indexRange) ([]indexRange, error) { + type timedIndexRange struct { + value indexRange + since time.Time + before time.Time + } + var ranges []timedIndexRange + for _, group := range groups { + for _, item := range group { + since, err := time.Parse(time.RFC3339Nano, item.Since) + if err != nil { + return nil, fmt.Errorf("invalid index range since %q: %w", item.Since, err) + } + before, err := time.Parse(time.RFC3339Nano, item.Before) + if err != nil { + return nil, fmt.Errorf("invalid index range before %q: %w", item.Before, err) + } + if since.After(before) || since.Equal(before) && item.IndexEntries != 0 { + return nil, fmt.Errorf("invalid index range [%s,%s): since must precede before unless the range is an empty cursor anchor", item.Since, item.Before) + } + if item.IndexEntries < 0 { + return nil, fmt.Errorf("invalid index range [%s,%s): index_entries must be nonnegative", item.Since, item.Before) + } + item.Since = since.UTC().Format(time.RFC3339Nano) + item.Before = before.UTC().Format(time.RFC3339Nano) + ranges = append(ranges, timedIndexRange{value: item, since: since.UTC(), before: before.UTC()}) } - defer file.Close() - writer = file } - enc := json.NewEncoder(writer) - enc.SetIndent("", " ") - if err := enc.Encode(report); err != nil { - fatal(err) + sort.Slice(ranges, func(i, j int) bool { + if !ranges[i].since.Equal(ranges[j].since) { + return ranges[i].since.Before(ranges[j].since) + } + return ranges[i].before.Before(ranges[j].before) + }) + normalized := make([]indexRange, 0, len(ranges)) + for _, timed := range ranges { + item := timed.value + if len(normalized) == 0 { + normalized = append(normalized, item) + continue + } + previous := &normalized[len(normalized)-1] + if item.Since == previous.Since && item.Before == previous.Before { + if item.IndexEntries != previous.IndexEntries { + return nil, fmt.Errorf("index range [%s,%s) has conflicting entry counts %d and %d", item.Since, item.Before, previous.IndexEntries, item.IndexEntries) + } + continue + } + if timestampBefore(item.Since, previous.Before) { + return nil, fmt.Errorf("index ranges [%s,%s) and [%s,%s) overlap; exact aggregate coverage is unknown", previous.Since, previous.Before, item.Since, item.Before) + } + normalized = append(normalized, item) } + return normalized, nil } -func fatal(err error) { - fmt.Fprintln(os.Stderr, err) - os.Exit(1) +func discoveryRangesOverlap(aSince, aNext, bSince, bNext string) bool { + if aSince == "" || aNext == "" || bSince == "" || bNext == "" { + return false + } + return timestampBefore(aSince, bNext) && timestampBefore(bSince, aNext) } -func validateConfig(cfg config) error { - if _, err := url.ParseRequestURI(cfg.indexURL); err != nil { - return fmt.Errorf("invalid index URL: %w", err) +func timestampBefore(left, right string) bool { + leftTime, leftErr := time.Parse(time.RFC3339Nano, left) + rightTime, rightErr := time.Parse(time.RFC3339Nano, right) + if leftErr == nil && rightErr == nil { + return leftTime.Before(rightTime) } - if _, err := url.ParseRequestURI(cfg.proxyURL); err != nil { - return fmt.Errorf("invalid proxy URL: %w", err) + return left < right +} + +func mergeRunCount(base, update int, overlaps bool) int { + if overlaps { + if update > base { + return update + } + return base } - if cfg.since != "" { - if _, err := time.Parse(time.RFC3339Nano, cfg.since); err != nil { - return fmt.Errorf("invalid -since timestamp: %w", err) + return base + update +} + +func readShardedReports(reportPath string) (discoveryReport, error) { + if _, err := os.Stat(filepath.Join(reportPath, "manifest.json")); err == nil { + return readShardedReport(reportPath) + } else if !errors.Is(err, os.ErrNotExist) { + return discoveryReport{}, fmt.Errorf("read sharded report %q: %w", reportPath, err) + } + // Accept the former per-run tree only as an import source. Newly written + // ledgers always have one manifest and one records directory at the root. + var manifests []string + err := filepath.WalkDir(reportPath, func(name string, entry os.DirEntry, err error) error { + if err != nil { + return err } + if !entry.IsDir() && entry.Name() == "manifest.json" { + manifests = append(manifests, name) + } + return nil + }) + if err != nil { + return discoveryReport{}, fmt.Errorf("read sharded reports %q: %w", reportPath, err) } - if cfg.limit < 0 { - return errors.New("-limit must be nonnegative") + if len(manifests) == 0 { + return discoveryReport{}, fmt.Errorf("read sharded reports %q: no manifest.json found", reportPath) } - if cfg.workers <= 0 { - return errors.New("-workers must be positive") + sort.Strings(manifests) + var combined discoveryReport + for _, manifestPath := range manifests { + report, err := readShardedReport(filepath.Dir(manifestPath)) + if err != nil { + return discoveryReport{}, err + } + combined, err = mergeDiscoveryReports(combined, report) + if err != nil { + return discoveryReport{}, fmt.Errorf("read sharded reports %q: %w", reportPath, err) + } } - if cfg.maxZipSize <= 0 { - return errors.New("-max-zip-bytes must be positive") + return combined, nil +} + +func earlierTimestamp(current, candidate string) string { + if current == "" || candidate != "" && timestampBefore(candidate, current) { + return candidate } - if cfg.httpTimeout <= 0 { - return errors.New("-http-timeout must be positive") + return current +} + +func laterTimestamp(current, candidate string) string { + if candidate != "" && (current == "" || timestampBefore(current, candidate)) { + return candidate } - return nil + return current } -func discover(ctx context.Context, client *http.Client, cfg config) (discoveryReport, error) { - entries, nextSince, err := readIndex(ctx, client, cfg.indexURL, cfg.since, cfg.limit) +func readShardedReport(reportPath string) (discoveryReport, error) { + manifestPath := filepath.Join(reportPath, "manifest.json") + data, err := os.ReadFile(manifestPath) if err != nil { - return discoveryReport{}, err + return discoveryReport{}, fmt.Errorf("read sharded report manifest %q: %w", manifestPath, err) + } + var manifest shardedManifest + if err := json.Unmarshal(data, &manifest); err != nil { + return discoveryReport{}, fmt.Errorf("decode sharded report manifest %q: %w", manifestPath, err) + } + if manifest.Format != shardedFormat { + return discoveryReport{}, fmt.Errorf("decode sharded report manifest %q: unsupported format %q", manifestPath, manifest.Format) + } + if manifest.SchemaVersion != discoverySchema { + return discoveryReport{}, fmt.Errorf("decode sharded report manifest %q: unsupported schema %d", manifestPath, manifest.SchemaVersion) + } + if manifest.ShardKey != "sha256(module)[0]" { + return discoveryReport{}, fmt.Errorf("decode sharded report manifest %q: unsupported shard key %q", manifestPath, manifest.ShardKey) + } + report := discoveryReport{ + SchemaVersion: manifest.SchemaVersion, + GeneratedAt: manifest.GeneratedAt, + Since: manifest.Since, + NextSince: manifest.NextSince, + ScanDirection: manifest.ScanDirection, + NextBefore: manifest.NextBefore, + IndexRanges: manifest.IndexRanges, + IndexEntries: manifest.IndexEntries, + UniqueModules: manifest.UniqueModules, + Skipped: manifest.Skipped, + } + if len(report.IndexRanges) > 0 { + report, err = upgradeDiscoveryReport(report) + if err != nil { + return discoveryReport{}, fmt.Errorf("decode sharded report manifest %q: %w", manifestPath, err) + } + entries := 0 + for _, item := range report.IndexRanges { + entries += item.IndexEntries + } + if entries != manifest.IndexEntries { + return discoveryReport{}, fmt.Errorf("decode sharded report manifest %q: index range count is %d, want index_entries %d", manifestPath, entries, manifest.IndexEntries) + } } - moduleSet := make(map[string]string, len(entries)) + recordsDir := filepath.Join(reportPath, "records") + entries, err := os.ReadDir(recordsDir) + if err != nil { + return discoveryReport{}, fmt.Errorf("list sharded report records %q: %w", reportPath, err) + } + shards := make([]string, 0, len(entries)) for _, entry := range entries { - moduleSet[entry.Path] = entry.Version + name := entry.Name() + if entry.IsDir() || len(name) != len("00.jsonl") || !strings.HasSuffix(name, ".jsonl") { + return discoveryReport{}, fmt.Errorf("list sharded report records %q: unexpected entry %q", reportPath, name) + } + if _, err := strconv.ParseUint(name[:2], 16, 8); err != nil { + return discoveryReport{}, fmt.Errorf("list sharded report records %q: invalid shard name %q", reportPath, name) + } + shards = append(shards, filepath.Join(recordsDir, name)) + } + sort.Strings(shards) + for _, shard := range shards { + shardNumber, _ := strconv.ParseUint(filepath.Base(shard)[:2], 16, 8) + file, err := os.Open(shard) + if err != nil { + return discoveryReport{}, fmt.Errorf("read record shard %q: %w", shard, err) + } + scanner := bufio.NewScanner(file) + scanner.Buffer(make([]byte, 64<<10), 16<<20) + line := 0 + var previous shardedRecord + for scanner.Scan() { + line++ + var item shardedRecord + if err := json.Unmarshal(scanner.Bytes(), &item); err != nil { + file.Close() + return discoveryReport{}, fmt.Errorf("decode record shard %s:%d: %w", shard, line, err) + } + if item.Module == "" || item.Version == "" { + file.Close() + return discoveryReport{}, fmt.Errorf("decode record shard %s:%d: incomplete module version", shard, line) + } + hash := sha256.Sum256([]byte(item.Module)) + if hash[0] != byte(shardNumber) { + file.Close() + return discoveryReport{}, fmt.Errorf("decode record shard %s:%d: module %q belongs in %02x.jsonl", shard, line, item.Module, hash[0]) + } + if line > 1 && compareShardedRecords(previous, item) >= 0 { + file.Close() + return discoveryReport{}, fmt.Errorf("decode record shard %s:%d: records are duplicated or not in module/semver/kind order", shard, line) + } + previous = item + switch item.Kind { + case "scanned": + if !semver.IsValid(item.Version) { + file.Close() + return discoveryReport{}, fmt.Errorf("decode record shard %s:%d: invalid scanned module version %q", shard, line, item.Version) + } + report.Scanned = append(report.Scanned, moduleVersion{Path: item.Module, Version: item.Version}) + case "matched": + if !semver.IsValid(item.Version) { + file.Close() + return discoveryReport{}, fmt.Errorf("decode record shard %s:%d: invalid matched module version %q", shard, line, item.Version) + } + report.Matched = append(report.Matched, candidate{ + Module: item.Module, Version: item.Version, + Architectures: item.Architectures, AsmFiles: item.AsmFiles, + }) + case "failure": + report.Failures = append(report.Failures, scanFailure{Module: item.Module, Version: item.Version, Error: item.Error}) + default: + file.Close() + return discoveryReport{}, fmt.Errorf("decode record shard %s:%d: unknown record kind %q", shard, line, item.Kind) + } + } + scanErr := scanner.Err() + closeErr := file.Close() + if scanErr != nil { + return discoveryReport{}, fmt.Errorf("read record shard %q: %w", shard, scanErr) + } + if closeErr != nil { + return discoveryReport{}, fmt.Errorf("close record shard %q: %w", shard, closeErr) + } } - modules := make([]moduleVersion, 0, len(moduleSet)) - for modulePath, version := range moduleSet { - modules = append(modules, moduleVersion{Path: modulePath, Version: version}) + if len(report.Scanned) != manifest.Scanned || len(report.Matched) != manifest.Matched || len(report.Failures) != manifest.Failures { + return discoveryReport{}, fmt.Errorf( + "read sharded report %q: record counts are scanned=%d/%d matched=%d/%d failures=%d/%d", + reportPath, len(report.Scanned), manifest.Scanned, len(report.Matched), manifest.Matched, len(report.Failures), manifest.Failures, + ) } - sort.Slice(modules, func(i, j int) bool { return modules[i].Path < modules[j].Path }) - uniqueModules := len(modules) - modules, skipped := filterPreviouslyScanned(modules, cfg.seen) - - matched, failures, scanned := inspectModules(ctx, client, cfg.proxyURL, modules, cfg.workers, cfg.maxZipSize) - return discoveryReport{ - SchemaVersion: discoverySchema, - GeneratedAt: time.Now().UTC(), - Since: cfg.since, - NextSince: nextSince, - IndexEntries: len(entries), - UniqueModules: uniqueModules, - Skipped: skipped, - Scanned: scanned, - Matched: matched, - Failures: failures, - }, nil + sortDiscoveryReport(&report) + return report, nil } -func loadSeenReports(paths []string) (map[string]struct{}, error) { - seen := make(map[string]struct{}) - for _, reportPath := range paths { - data, err := os.ReadFile(reportPath) - if err != nil { - return nil, fmt.Errorf("read seen report %q: %w", reportPath, err) +func sortDiscoveryReport(report *discoveryReport) { + sort.Slice(report.Scanned, func(i, j int) bool { + if report.Scanned[i].Path != report.Scanned[j].Path { + return report.Scanned[i].Path < report.Scanned[j].Path } - var report discoveryReport - if err := json.Unmarshal(data, &report); err != nil { - return nil, fmt.Errorf("decode seen report %q: %w", reportPath, err) + return compareModuleVersions(report.Scanned[i].Version, report.Scanned[j].Version) < 0 + }) + for i := range report.Matched { + sort.Strings(report.Matched[i].AsmFiles) + report.Matched[i].Architectures = discoverymeta.ArchitectureHints(report.Matched[i].AsmFiles) + } + sort.Slice(report.Matched, func(i, j int) bool { + if report.Matched[i].Module != report.Matched[j].Module { + return report.Matched[i].Module < report.Matched[j].Module } - for _, item := range report.Scanned { - if item.Path == "" || item.Version == "" { - return nil, fmt.Errorf("seen report %q contains an incomplete scanned version", reportPath) - } - seen[scanKey(item)] = struct{}{} + return compareModuleVersions(report.Matched[i].Version, report.Matched[j].Version) < 0 + }) + sort.Slice(report.Failures, func(i, j int) bool { + if report.Failures[i].Module != report.Failures[j].Module { + return report.Failures[i].Module < report.Failures[j].Module } - // Older reports did not contain the complete scanned set, but their - // successful matches are still safe to reuse. - for _, item := range report.Matched { - if item.Module != "" && item.Version != "" { - seen[scanKey(moduleVersion{Path: item.Module, Version: item.Version})] = struct{}{} - } + return compareModuleVersions(report.Failures[i].Version, report.Failures[j].Version) < 0 + }) +} + +func compareModuleVersions(a, b string) int { + aValid, bValid := semver.IsValid(a), semver.IsValid(b) + if aValid && bValid { + if compared := semver.Compare(a, b); compared != 0 { + return compared } + } else if aValid != bValid { + if aValid { + return -1 + } + return 1 } - return seen, nil + return strings.Compare(a, b) } -func filterPreviouslyScanned(modules []moduleVersion, seen map[string]struct{}) ([]moduleVersion, int) { - if len(seen) == 0 { - return modules, 0 +func compareShardedRecords(a, b shardedRecord) int { + if compared := strings.Compare(a.Module, b.Module); compared != 0 { + return compared } - pending := make([]moduleVersion, 0, len(modules)) - skipped := 0 - for _, module := range modules { - if _, ok := seen[scanKey(module)]; ok { - skipped++ - continue - } - pending = append(pending, module) + if compared := compareModuleVersions(a.Version, b.Version); compared != 0 { + return compared } - return pending, skipped + return strings.Compare(a.Kind, b.Kind) } func scanKey(module moduleVersion) string { @@ -354,23 +1923,233 @@ func readIndex(ctx context.Context, client *http.Client, endpoint, since string, return entries, cursor, nil } -func inspectModules(ctx context.Context, client *http.Client, proxyURL string, modules []moduleVersion, workers int, maxZipSize int64) ([]candidate, []scanFailure, []moduleVersion) { +// readIndexBackwards returns the newest index entries strictly before before. +// index.golang.org only exposes an ascending `since` API, so each reverse page +// brackets a small time window whose complete contents fit in one server page, +// then keeps its newest entries. The earliest timestamp group is kept whole so +// the returned cursor can be used as an exclusive upper bound without losing +// entries that share a timestamp. +func readIndexBackwards(ctx context.Context, client *http.Client, endpoint, before string, limit int) ([]indexEntry, string, error) { + return readIndexBackwardsFromWithHint(ctx, client, endpoint, before, indexEpoch, limit, time.Hour) +} + +// readIndexBackwardsFrom returns newest entries in [after,before). Keeping the +// lower bound explicit lets the completed history scan later reuse the same +// timestamp-safe reverse reader for only the newly published head interval. +func readIndexBackwardsFrom(ctx context.Context, client *http.Client, endpoint, before, after string, limit int) ([]indexEntry, string, error) { + return readIndexBackwardsFromWithHint(ctx, client, endpoint, before, after, limit, time.Hour) +} + +func readIndexBackwardsFromWithHint(ctx context.Context, client *http.Client, endpoint, before, after string, limit int, initialSpanHint time.Duration) ([]indexEntry, string, error) { + upper, err := time.Parse(time.RFC3339Nano, before) + if err != nil { + return nil, "", fmt.Errorf("invalid reverse index cursor %q: %w", before, err) + } + lowerBound, err := time.Parse(time.RFC3339Nano, after) + if err != nil { + return nil, "", fmt.Errorf("invalid reverse index lower bound %q: %w", after, err) + } + if upper.Before(lowerBound) { + return nil, "", fmt.Errorf("reverse index cursor %s precedes lower bound %s", before, after) + } + if limit < 0 { + return nil, "", errors.New("reverse index limit must be nonnegative") + } + var entries []indexEntry + spanHint := initialSpanHint + if spanHint <= 0 { + spanHint = time.Hour + } + for limit == 0 || len(entries) < limit { + target := reversePageTarget + if limit > 0 && limit-len(entries) < target { + target = limit - len(entries) + } + page, nextSpanHint, err := readIndexPageBefore(ctx, client, endpoint, upper, lowerBound, target, spanHint) + if err != nil { + return nil, "", err + } + if len(page) == 0 { + upper = lowerBound + break + } + entries = append(entries, page...) + upper = page[0].Timestamp + spanHint = nextSpanHint + if limit > 0 && limit-len(entries) > 0 && limit-len(entries) < reversePageTarget/10 { + break + } + } + sort.Slice(entries, func(i, j int) bool { + if !entries[i].Timestamp.Equal(entries[j].Timestamp) { + return entries[i].Timestamp.Before(entries[j].Timestamp) + } + if entries[i].Path != entries[j].Path { + return entries[i].Path < entries[j].Path + } + return compareModuleVersions(entries[i].Version, entries[j].Version) < 0 + }) + return entries, upper.Format(time.RFC3339Nano), nil +} + +func readIndexPageBefore(ctx context.Context, client *http.Client, endpoint string, upper, lowerBound time.Time, target int, spanHint time.Duration) ([]indexEntry, time.Duration, error) { + if target <= 0 || target > reversePageTarget { + return nil, 0, fmt.Errorf("reverse index page target %d is outside 1..%d", target, reversePageTarget) + } + if !upper.After(lowerBound) { + return nil, spanHint, nil + } + var narrow, wide time.Duration + span := spanHint + if span <= 0 { + span = time.Hour + } + for attempts := 0; attempts < 80; attempts++ { + lower := upper.Add(-span) + if lower.Before(lowerBound) { + lower = lowerBound + } + page, err := fetchIndexPage(ctx, client, endpoint, lower.Format(time.RFC3339Nano), indexPageLimit) + if err != nil { + return nil, 0, err + } + complete := len(page) < indexPageLimit + if len(page) > 0 && !page[len(page)-1].Timestamp.Before(upper) { + complete = true + } + cut := sort.Search(len(page), func(i int) bool { return !page[i].Timestamp.Before(upper) }) + beforeEntries := page[:cut] + minimumUseful := (target + 1) / 2 + if complete && (len(beforeEntries) >= minimumUseful || lower.Equal(lowerBound)) { + if len(beforeEntries) <= target { + selected := append([]indexEntry(nil), beforeEntries...) + return selected, nextReverseSpanHint(upper, selected, target, span), nil + } + first := len(beforeEntries) - target + boundary := beforeEntries[first].Timestamp + for first > 0 && beforeEntries[first-1].Timestamp.Equal(boundary) { + first-- + } + selected := append([]indexEntry(nil), beforeEntries[first:]...) + return selected, nextReverseSpanHint(upper, selected, target, span), nil + } + + if complete { + narrow = span + if wide == 0 { + span *= 2 + } else { + span = narrow + (wide-narrow)/2 + } + } else { + wide = span + span = narrow + (wide-narrow)/2 + } + if span <= 0 || wide > 0 && wide-narrow <= time.Nanosecond { + return nil, 0, fmt.Errorf("cannot isolate %d index entries before %s in one page", target, upper.Format(time.RFC3339Nano)) + } + } + return nil, 0, fmt.Errorf("cannot bracket %d index entries before %s", target, upper.Format(time.RFC3339Nano)) +} + +func nextReverseSpanHint(upper time.Time, selected []indexEntry, target int, fallback time.Duration) time.Duration { + if len(selected) == 0 { + return fallback + } + observed := upper.Sub(selected[0].Timestamp) + if observed <= 0 { + return time.Nanosecond + } + hint := time.Duration(float64(observed) * float64(target) / float64(len(selected))) + if hint <= 0 { + return time.Nanosecond + } + return hint +} + +func fetchIndexPage(ctx context.Context, client *http.Client, endpoint, since string, limit int) ([]indexEntry, error) { + parsed, err := url.Parse(endpoint) + if err != nil { + return nil, err + } + query := parsed.Query() + query.Set("limit", strconv.Itoa(limit)) + if since != "" { + query.Set("since", since) + } + parsed.RawQuery = query.Encode() + resp, err := doHTTPRequest(ctx, client, http.MethodGet, parsed.String(), nil) + if err != nil { + return nil, fmt.Errorf("read module index: %w", err) + } + defer resp.Body.Close() + if resp.StatusCode != http.StatusOK { + return nil, fmt.Errorf("read module index: %s", resp.Status) + } + scanner := bufio.NewScanner(resp.Body) + scanner.Buffer(make([]byte, 64<<10), 1<<20) + entries := make([]indexEntry, 0, limit) + for scanner.Scan() { + var entry indexEntry + if err := json.Unmarshal(scanner.Bytes(), &entry); err != nil { + return nil, fmt.Errorf("decode module index: %w", err) + } + if entry.Path == "" || entry.Timestamp.IsZero() { + return nil, errors.New("module index entry is missing Path or Timestamp") + } + if len(entries) > 0 && entry.Timestamp.Before(entries[len(entries)-1].Timestamp) { + return nil, fmt.Errorf("module index page is not ordered by timestamp: %s precedes %s", entry.Timestamp.Format(time.RFC3339Nano), entries[len(entries)-1].Timestamp.Format(time.RFC3339Nano)) + } + entries = append(entries, entry) + } + if err := scanner.Err(); err != nil { + return nil, fmt.Errorf("read module index: %w", err) + } + return entries, nil +} + +func inspectModules(ctx context.Context, client *http.Client, proxyURL string, modules []moduleVersion, seen, sourceSeen map[string]seenResult, workers int, maxZipSize int64) ([]candidate, []scanFailure, []moduleVersion, int) { + sourceCache := newSourceInspectionCache(sourceSeen) tasks := make(chan moduleVersion) results := make(chan candidate) errorsOut := make(chan scanFailure) completed := make(chan moduleVersion) + reused := make(chan struct{}) var wg sync.WaitGroup for i := 0; i < workers; i++ { wg.Add(1) go func() { defer wg.Done() for module := range tasks { - item, scanned, err := inspectIndexedModule(ctx, client, proxyURL, module, maxZipSize) - for _, version := range scanned { - completed <- version + moduleCtx := withTrafficModule(ctx, module.Path) + collector, _ := trafficContext(moduleCtx) + if collector != nil { + collector.setModuleScan(module.Path, module.Version, "", "") + } + item, latest, didScan, wasReused, err := inspectLatestModule(moduleCtx, client, proxyURL, module.Path, seen, sourceCache, maxZipSize) + if collector != nil { + outcome := "scanned" + switch { + case err != nil: + outcome = "failure" + case wasReused: + outcome = "reused_scanned" + if len(item.AsmFiles) > 0 { + outcome = "reused_matched" + } + case len(item.AsmFiles) > 0: + outcome = "matched" + } + collector.setModuleScan(module.Path, module.Version, latest.Version, outcome) + } + if didScan || wasReused { + completed <- latest + } + if wasReused { + reused <- struct{}{} } if err != nil { - errorsOut <- scanFailure{Module: module.Path, Version: module.Version, Error: err.Error()} + errorsOut <- scanFailure{Module: latest.Path, Version: latest.Version, Error: err.Error()} continue } if len(item.AsmFiles) > 0 { @@ -388,12 +2167,14 @@ func inspectModules(ctx context.Context, client *http.Client, proxyURL string, m close(results) close(errorsOut) close(completed) + close(reused) }() matched := make([]candidate, 0) failures := make([]scanFailure, 0) scannedSet := make(map[string]moduleVersion) - for results != nil || errorsOut != nil || completed != nil { + skipped := 0 + for results != nil || errorsOut != nil || completed != nil || reused != nil { select { case item, ok := <-results: if !ok { @@ -413,6 +2194,12 @@ func inspectModules(ctx context.Context, client *http.Client, proxyURL string, m continue } scannedSet[scanKey(item)] = item + case _, ok := <-reused: + if !ok { + reused = nil + continue + } + skipped++ } } scanned := make([]moduleVersion, 0, len(scannedSet)) @@ -427,31 +2214,30 @@ func inspectModules(ctx context.Context, client *http.Client, proxyURL string, m } return scanned[i].Version < scanned[j].Version }) - return matched, failures, scanned + return matched, failures, scanned, skipped } -func inspectIndexedModule(ctx context.Context, client *http.Client, proxyURL string, module moduleVersion, maxZipSize int64) (candidate, []moduleVersion, error) { - indexed, err := inspectModuleVersion(ctx, client, proxyURL, module.Path, module.Version, maxZipSize) +func inspectLatestModule(ctx context.Context, client *http.Client, proxyURL, modulePath string, seen map[string]seenResult, sourceCache *sourceInspectionCache, maxZipSize int64) (candidate, moduleVersion, bool, bool, error) { + latest := moduleVersion{Path: modulePath, Version: "@latest"} + latestVersion, err := resolveLatest(ctx, client, proxyURL, modulePath) if err != nil { - return candidate{}, nil, fmt.Errorf("inspect indexed version %s: %w", module.Version, err) + return candidate{}, latest, false, false, err } - scanned := []moduleVersion{module} - if len(indexed.AsmFiles) == 0 { - return indexed, scanned, nil + latest.Version = latestVersion + if previous, ok := seen[scanKey(latest)]; ok { + return previous.Match, latest, false, true, nil } - latestVersion, err := resolveLatest(ctx, client, proxyURL, module.Path) + item, sourceReused, err := sourceCache.inspect(ctx, sourceScanKey(latest), func() (candidate, error) { + return inspectModuleVersion(ctx, client, proxyURL, modulePath, latestVersion, maxZipSize) + }) if err != nil { - return candidate{}, scanned, err - } - if latestVersion == module.Version { - return indexed, scanned, nil + return candidate{}, latest, false, false, err } - latest, err := inspectModuleVersion(ctx, client, proxyURL, module.Path, latestVersion, maxZipSize) - if err != nil { - return candidate{}, scanned, err + if sourceReused && item.Module != "" { + item.Module = modulePath + item.Version = latestVersion } - scanned = append(scanned, moduleVersion{Path: module.Path, Version: latestVersion}) - return latest, scanned, nil + return item, latest, !sourceReused, sourceReused, nil } func resolveLatest(ctx context.Context, client *http.Client, proxyURL, modulePath string) (string, error) { @@ -465,9 +2251,12 @@ func resolveLatest(ctx context.Context, client *http.Client, proxyURL, modulePat return "", fmt.Errorf("resolve @latest: %w", err) } var latest latestInfo - if err := json.Unmarshal(latestBody, &latest); err != nil || latest.Version == "" { + if err := json.Unmarshal(latestBody, &latest); err != nil { return "", fmt.Errorf("decode @latest: %w", err) } + if latest.Version == "" { + return "", errors.New("decode @latest: missing Version") + } return latest.Version, nil } @@ -626,18 +2415,20 @@ func assemblySourceHasContent(data []byte) bool { } type remoteZipReaderAt struct { - ctx context.Context - client *http.Client - endpoint string - cachedTail []byte - cacheMu sync.Mutex - cachedData map[int64][]byte - tailStart int64 - size int64 + ctx context.Context + client *http.Client + endpoint string + cachedTail []byte + cachedDirectory []byte + cacheMu sync.Mutex + cachedData map[int64][]byte + tailStart int64 + directoryStart int64 + size int64 } func newHTTPReaderAt(ctx context.Context, client *http.Client, endpoint string, maxSize int64) (io.ReaderAt, int64, error) { - return newHTTPReaderAtWithTail(ctx, client, endpoint, maxSize, zipDirectoryTail) + return newHTTPReaderAtWithTail(ctx, client, endpoint, maxSize, zipEOCDSize) } func newHTTPReaderAtWithTail(ctx context.Context, client *http.Client, endpoint string, maxSize, tailSize int64) (io.ReaderAt, int64, error) { @@ -659,6 +2450,54 @@ func newHTTPReaderAtWithTail(ctx context.Context, client *http.Client, endpoint return nil, 0, fmt.Errorf("ZIP is %d bytes (limit %d)", resp.ContentLength, maxSize) } size := resp.ContentLength + if collector, modulePath := trafficContext(ctx); collector != nil { + collector.setAdvertisedZIPBytes(modulePath, size) + } + if size <= zipSmallWholeLimit { + tailSize = size + } + data, start, err := readZIPTail(ctx, client, endpoint, size, tailSize) + if err != nil { + return nil, 0, err + } + directoryStart, directoryEnd, parseErr := zipCentralDirectoryRange(data, start) + if parseErr != nil && tailSize < zipMaxEOCDSearch { + data, start, err = readZIPTail(ctx, client, endpoint, size, zipMaxEOCDSearch) + if err != nil { + return nil, 0, err + } + directoryStart, directoryEnd, parseErr = zipCentralDirectoryRange(data, start) + } + if parseErr != nil { + return nil, 0, parseErr + } + if directoryStart < 0 || directoryEnd < directoryStart || directoryEnd > size { + return nil, 0, fmt.Errorf("ZIP central directory range [%d,%d) is outside archive of %d bytes", directoryStart, directoryEnd, size) + } + cacheStart := directoryStart + if eocdProbeStart := size - 1024; eocdProbeStart >= 0 && eocdProbeStart < cacheStart { + cacheStart = eocdProbeStart + } + reader := &remoteZipReaderAt{ + ctx: ctx, + client: client, + endpoint: endpoint, + cachedTail: data, + cachedData: make(map[int64][]byte), + tailStart: start, + directoryStart: cacheStart, + size: size, + } + if cacheStart < start { + reader.cachedDirectory, err = reader.readRange(cacheStart, start) + if err != nil { + return nil, 0, fmt.Errorf("read ZIP central directory: %w", err) + } + } + return reader, size, nil +} + +func readZIPTail(ctx context.Context, client *http.Client, endpoint string, size, tailSize int64) ([]byte, int64, error) { start := size - tailSize if start < 0 { start = 0 @@ -667,7 +2506,7 @@ func newHTTPReaderAtWithTail(ctx context.Context, client *http.Client, endpoint if start > 0 { headers.Set("Range", fmt.Sprintf("bytes=%d-%d", start, size-1)) } - resp, err = doHTTPRequest(ctx, client, http.MethodGet, endpoint, headers) + resp, err := doHTTPRequest(ctx, client, http.MethodGet, endpoint, headers) if err != nil { return nil, 0, err } @@ -687,15 +2526,46 @@ func newHTTPReaderAtWithTail(ctx context.Context, client *http.Client, endpoint if int64(len(data)) != wantBytes { return nil, 0, fmt.Errorf("ZIP tail returned %d bytes, want %d", len(data), wantBytes) } - return &remoteZipReaderAt{ - ctx: ctx, - client: client, - endpoint: endpoint, - cachedTail: data, - cachedData: make(map[int64][]byte), - tailStart: start, - size: size, - }, size, nil + return data, start, nil +} + +func zipCentralDirectoryRange(tail []byte, tailStart int64) (int64, int64, error) { + const ( + eocdSignature = 0x06054b50 + zip64EOCDSignature = 0x06064b50 + zip64LocatorSignature = 0x07064b50 + ) + for offset := len(tail) - zipEOCDSize; offset >= 0; offset-- { + if binary.LittleEndian.Uint32(tail[offset:]) != eocdSignature { + continue + } + commentLength := int(binary.LittleEndian.Uint16(tail[offset+20:])) + if offset+zipEOCDSize+commentLength != len(tail) { + continue + } + directorySize := uint64(binary.LittleEndian.Uint32(tail[offset+12:])) + directoryOffset := uint64(binary.LittleEndian.Uint32(tail[offset+16:])) + if directorySize == uint64(^uint32(0)) || directoryOffset == uint64(^uint32(0)) { + locatorOffset := offset - 20 + if locatorOffset < 0 || binary.LittleEndian.Uint32(tail[locatorOffset:]) != zip64LocatorSignature { + return 0, 0, errors.New("ZIP64 end record is outside cached tail") + } + zip64Offset := int64(binary.LittleEndian.Uint64(tail[locatorOffset+8:])) + zip64Relative := zip64Offset - tailStart + if zip64Relative < 0 || zip64Relative+56 > int64(len(tail)) || + binary.LittleEndian.Uint32(tail[zip64Relative:]) != zip64EOCDSignature { + return 0, 0, errors.New("ZIP64 end record is outside cached tail") + } + directorySize = binary.LittleEndian.Uint64(tail[zip64Relative+40:]) + directoryOffset = binary.LittleEndian.Uint64(tail[zip64Relative+48:]) + } + if directoryOffset > uint64(^uint64(0)>>1) || directorySize > uint64(^uint64(0)>>1)-directoryOffset { + return 0, 0, errors.New("ZIP central directory range overflows int64") + } + start := int64(directoryOffset) + return start, start + int64(directorySize), nil + } + return 0, 0, errors.New("ZIP end-of-central-directory record not found") } func (r *remoteZipReaderAt) ReadAt(p []byte, offset int64) (int, error) { @@ -712,6 +2582,10 @@ func (r *remoteZipReaderAt) ReadAt(p []byte, offset int64) (int, error) { written += copy(p[written:], r.cachedTail[current-r.tailStart:]) continue } + if current >= r.directoryStart && current < r.directoryStart+int64(len(r.cachedDirectory)) { + written += copy(p[written:], r.cachedDirectory[current-r.directoryStart:]) + continue + } blockStart := current - current%zipReadAhead r.cacheMu.Lock() block, ok := r.cachedData[blockStart] @@ -768,8 +2642,26 @@ func doHTTPRequest(ctx context.Context, client *http.Client, method, endpoint st if err != nil { return nil, err } - req.Header = headers.Clone() + if headers != nil { + req.Header = headers.Clone() + } + if req.Header.Get("Accept-Encoding") == "" { + req.Header.Set("Accept-Encoding", "identity") + } + collector, modulePath := trafficContext(ctx) + phase := trafficPhase(modulePath, method, endpoint, req.Header) + if collector != nil { + collector.addRequest(modulePath, phase) + } resp, err := client.Do(req) + if resp != nil && collector != nil { + resp.Body = &trafficReadCloser{ + ReadCloser: resp.Body, + collector: collector, + module: modulePath, + phase: phase, + } + } if err == nil && !isTransientHTTPStatus(resp.StatusCode) { return resp, nil } @@ -811,13 +2703,7 @@ func containsPathElement(name, element string) bool { } func inferAssemblyArchitecture(name string) string { - base := strings.TrimSuffix(path.Base(name), ".s") - for _, arch := range []string{"386", "amd64", "arm", "arm64", "wasm"} { - if strings.HasSuffix(base, "_"+arch) { - return arch - } - } - return "unknown" + return discoverymeta.InferArchitecture(name) } // escapeProxyPath implements the uppercase escaping used by the Go module diff --git a/cmd/plan9asmdiscover/main_test.go b/cmd/plan9asmdiscover/main_test.go index 5a68ae73..cfe1647c 100644 --- a/cmd/plan9asmdiscover/main_test.go +++ b/cmd/plan9asmdiscover/main_test.go @@ -3,7 +3,9 @@ package main import ( "archive/zip" "bytes" + "compress/gzip" "context" + "crypto/sha256" "encoding/json" "fmt" "io" @@ -12,6 +14,7 @@ import ( "os" "path/filepath" "reflect" + "sort" "strconv" "strings" "sync/atomic" @@ -33,6 +36,9 @@ func TestValidateConfigRejectsNonPositiveHTTPTimeout(t *testing.T) { err := validateConfig(config{ indexURL: defaultIndexURL, proxyURL: defaultProxyURL, + scanMode: scanModeHistory, + before: "2026-09-15T00:00:00Z", + after: indexEpoch, workers: 1, maxZipSize: 1, httpTimeout: 0, @@ -42,7 +48,16 @@ func TestValidateConfigRejectsNonPositiveHTTPTimeout(t *testing.T) { } } -func TestSeenReportsSkipOnlyCompletedExactVersions(t *testing.T) { +func TestIncrementalScanIgnoresHistoryBatchLimit(t *testing.T) { + if got := scanLimit(scanModeIncremental, defaultScanLimit); got != 0 { + t.Fatalf("incremental scan limit = %d, want complete head interval", got) + } + if got := scanLimit(scanModeHistory, 123); got != 123 { + t.Fatalf("history scan limit = %d, want requested 123", got) + } +} + +func TestSeenReportsRecordOnlyCompletedExactVersions(t *testing.T) { reportPath := filepath.Join(t.TempDir(), "previous.json") data, err := json.Marshal(discoveryReport{ SchemaVersion: 1, @@ -55,54 +70,1340 @@ func TestSeenReportsSkipOnlyCompletedExactVersions(t *testing.T) { if err != nil { t.Fatal(err) } - if err := os.WriteFile(reportPath, data, 0o600); err != nil { + if err := os.WriteFile(reportPath, data, 0o600); err != nil { + t.Fatal(err) + } + seen, err := loadSeenReports([]string{reportPath}) + if err != nil { + t.Fatal(err) + } + wantSeen := []moduleVersion{ + {Path: "example.com/a", Version: "v1.0.0"}, + {Path: "example.com/noasm", Version: "v2.0.0"}, + {Path: "example.com/old-match", Version: "v3.0.0"}, + } + for _, item := range wantSeen { + if _, ok := seen[scanKey(item)]; !ok { + t.Errorf("completed version is not recorded: %s@%s", item.Path, item.Version) + } + } + for _, item := range []moduleVersion{ + {Path: "example.com/a", Version: "v1.1.0"}, + {Path: "example.com/new", Version: "v1.0.0"}, + } { + if _, ok := seen[scanKey(item)]; ok { + t.Errorf("unscanned exact version is recorded: %s@%s", item.Path, item.Version) + } + } +} + +func TestSeenReportsReadCompressedLedger(t *testing.T) { + reportPath := filepath.Join(t.TempDir(), "scan-ledger.json.gz") + file, err := os.Create(reportPath) + if err != nil { + t.Fatal(err) + } + zw := gzip.NewWriter(file) + if err := json.NewEncoder(zw).Encode(discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{ + {Path: "example.com/with-asm", Version: "v1.0.0"}, + {Path: "example.com/without-asm", Version: "v2.0.0"}, + }, + }); err != nil { + t.Fatal(err) + } + if err := zw.Close(); err != nil { + t.Fatal(err) + } + if err := file.Close(); err != nil { + t.Fatal(err) + } + + seen, err := loadSeenReports([]string{reportPath}) + if err != nil { + t.Fatal(err) + } + for _, item := range []moduleVersion{ + {Path: "example.com/with-asm", Version: "v1.0.0"}, + {Path: "example.com/without-asm", Version: "v2.0.0"}, + } { + if _, ok := seen[scanKey(item)]; !ok { + t.Errorf("compressed ledger omitted %s@%s", item.Path, item.Version) + } + } +} + +func TestLoadSeenReportsPreservesMatchAcrossReportOrder(t *testing.T) { + dir := t.TempDir() + item := candidate{ + Module: "example.com/asm", Version: "v1.0.0", + Architectures: []string{"amd64"}, AsmFiles: []string{"asm_amd64.s"}, + } + paths := []string{filepath.Join(dir, "matched.json"), filepath.Join(dir, "scanned.json")} + for i, report := range []discoveryReport{ + {SchemaVersion: discoverySchema, Matched: []candidate{item}}, + {SchemaVersion: discoverySchema, Scanned: []moduleVersion{{Path: item.Module, Version: item.Version}}}, + } { + data, err := json.Marshal(report) + if err != nil { + t.Fatal(err) + } + if err := os.WriteFile(paths[i], data, 0o600); err != nil { + t.Fatal(err) + } + } + seen, err := loadSeenReports(paths) + if err != nil { + t.Fatal(err) + } + if got := seen[scanKey(moduleVersion{Path: item.Module, Version: item.Version})].Match; !reflect.DeepEqual(got, item) { + t.Fatalf("later scanned-only report erased assembly metadata: %#v", got) + } +} + +func TestLoadSeenReportsIndexesGitHubPseudoVersionCaseAliases(t *testing.T) { + version := "v0.0.0-20260914132724-051eaffddbc5" + reportPath := filepath.Join(t.TempDir(), "seen.json") + data, err := json.Marshal(discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{{Path: "github.com/L2Beat/l2beat", Version: version}}, + }) + if err != nil { + t.Fatal(err) + } + if err := os.WriteFile(reportPath, data, 0o600); err != nil { + t.Fatal(err) + } + seen, sourceSeen, err := loadSeenState([]string{reportPath}) + if err != nil { + t.Fatal(err) + } + alias := moduleVersion{Path: "github.com/l2beat/l2beat", Version: version} + if key := sourceScanKey(alias); key == "" { + t.Fatal("sourceScanKey() did not recognize GitHub pseudo-version") + } else if _, ok := sourceSeen[key]; !ok { + t.Fatalf("seen report did not index case-insensitive repository source key %q", key) + } + if len(seen) != 1 { + t.Fatalf("source aliases polluted exact-version checkpoint count: %d", len(seen)) + } + if key := sourceScanKey(moduleVersion{Path: "github.com/l2beat/l2beat", Version: "v1.2.3"}); key != "" { + t.Fatalf("sourceScanKey() unsafely reused mutable semantic tag as %q", key) + } + if a, b := sourceScanKey(alias), sourceScanKey(moduleVersion{Path: "github.com/L2BEAT/l2beat", Version: version}); a != b { + t.Fatalf("GitHub owner/repository case aliases differ: %q != %q", a, b) + } + if a, b := sourceScanKey( + moduleVersion{Path: "github.com/l2beat/l2beat/Sub", Version: version}, + ), sourceScanKey(moduleVersion{Path: "github.com/l2beat/l2beat/sub", Version: version}); a == b { + t.Fatalf("sourceScanKey() folded case-sensitive module subdirectory: %q", a) + } +} + +func TestShardedReportRoundTripIsDeterministic(t *testing.T) { + report := discoveryReport{ + SchemaVersion: discoverySchema, + GeneratedAt: time.Date(2026, 9, 13, 12, 34, 56, 0, time.UTC), + ScanDirection: "bidirectional", + IndexRanges: []indexRange{{ + Since: "2019-04-10T00:00:00Z", Before: "2019-04-11T00:00:00Z", IndexEntries: 3, + }}, + IndexEntries: 3, + UniqueModules: 3, + Scanned: []moduleVersion{ + {Path: "example.com/noasm", Version: "v2.0.0"}, + {Path: "example.com/asm", Version: "v1.0.0"}, + }, + Matched: []candidate{{ + Module: "example.com/asm", + Version: "v1.0.0", + Architectures: []string{"arm64", "amd64"}, + AsmFiles: []string{"z_arm64.s", "a_amd64.s"}, + }}, + Failures: []scanFailure{{ + Module: "example.com/broken", Version: "v3.0.0", Error: "missing ZIP", + }}, + } + + dir1 := filepath.Join(t.TempDir(), "run-one") + if err := writeShardedReport(dir1, report); err != nil { + t.Fatal(err) + } + reordered := report + reordered.Scanned = append([]moduleVersion(nil), report.Scanned...) + reordered.Scanned[0], reordered.Scanned[1] = reordered.Scanned[1], reordered.Scanned[0] + dir2 := filepath.Join(t.TempDir(), "run-two") + if err := writeShardedReport(dir2, reordered); err != nil { + t.Fatal(err) + } + + files1 := readDirectoryFiles(t, dir1) + files2 := readDirectoryFiles(t, dir2) + if !reflect.DeepEqual(files1, files2) { + t.Fatalf("sharded output depends on input order\nfirst: %#v\nsecond: %#v", files1, files2) + } + if _, ok := files1["manifest.json"]; !ok { + t.Fatal("sharded output has no manifest.json") + } + for name, data := range files1 { + if strings.HasSuffix(name, ".gz") { + t.Fatalf("sharded output contains opaque gzip file %q", name) + } + if strings.HasPrefix(name, "records/") && !bytes.HasSuffix(data, []byte("\n")) { + t.Errorf("JSONL shard %q has no trailing newline", name) + } + } + + loaded, err := readSeenReport(dir1) + if err != nil { + t.Fatal(err) + } + sortDiscoveryReport(&report) + if !reflect.DeepEqual(loaded, report) { + t.Fatalf("round trip = %#v, want %#v", loaded, report) + } + + hash := sha256.Sum256([]byte("example.com/asm")) + wantShard := fmt.Sprintf("records/%02x.jsonl", hash[0]) + if _, ok := files1[wantShard]; !ok { + t.Fatalf("module was not written to stable shard %q; files: %#v", wantShard, files1) + } +} + +func TestShardedLedgerUpdateReplacesOlderModuleVersions(t *testing.T) { + ledger := filepath.Join(t.TempDir(), "ledger") + initial := discoveryReport{ + SchemaVersion: discoverySchema, + GeneratedAt: time.Date(2026, 9, 13, 12, 0, 0, 0, time.UTC), + ScanDirection: "bidirectional", + IndexRanges: []indexRange{{ + Since: "2026-09-01T00:00:00Z", Before: "2026-09-02T00:00:00Z", IndexEntries: 10, + }}, + IndexEntries: 10, + Skipped: 3, + Scanned: []moduleVersion{ + {Path: "example.com/a", Version: "v1.9.0"}, + {Path: "example.com/a", Version: "v1.10.0-rc.1"}, + }, + Matched: []candidate{{ + Module: "example.com/a", Version: "v1.9.0", + Architectures: []string{"amd64"}, AsmFiles: []string{"old_amd64.s"}, + }}, + Failures: []scanFailure{{Module: "example.com/a", Version: "v1.10.0", Error: "temporary proxy failure"}}, + } + if err := writeShardedReport(ledger, initial); err != nil { + t.Fatal(err) + } + update := discoveryReport{ + SchemaVersion: discoverySchema, + GeneratedAt: time.Date(2026, 9, 14, 12, 0, 0, 0, time.UTC), + ScanDirection: "bidirectional", + IndexRanges: []indexRange{{ + Since: "2026-08-31T00:00:00Z", Before: "2026-09-01T00:00:00Z", IndexEntries: 11, + }}, + IndexEntries: 11, + Skipped: 4, + Scanned: []moduleVersion{{Path: "example.com/a", Version: "v1.10.0"}}, + Matched: []candidate{{ + Module: "example.com/a", Version: "v1.10.0", + Architectures: []string{"arm64"}, AsmFiles: []string{"new_arm64.s"}, + }}, + } + if err := writeShardedReport(ledger, update); err != nil { + t.Fatal(err) + } + + report, err := readSeenReport(ledger) + if err != nil { + t.Fatal(err) + } + wantScanned := []moduleVersion{{Path: "example.com/a", Version: "v1.10.0"}} + if !reflect.DeepEqual(report.Scanned, wantScanned) { + t.Fatalf("scanned versions = %#v, want only current latest %#v", report.Scanned, wantScanned) + } + if len(report.Matched) != 1 || report.Matched[0].Version != "v1.10.0" || len(report.Failures) != 0 { + t.Fatalf("updated ledger retained an obsolete version or completed failure: %#v", report) + } + if report.IndexEntries != 21 || report.UniqueModules != 1 { + t.Fatalf("updated ledger counts = index %d, modules %d; want 21, 1", report.IndexEntries, report.UniqueModules) + } + if earliestIndexRangeLower(report.IndexRanges) != "2026-08-31T00:00:00Z" || latestIndexRangeUpper(report.IndexRanges) != "2026-09-02T00:00:00Z" || len(report.IndexRanges) != 2 { + t.Fatalf("derived dual scan cursors are inconsistent with ranges %#v", report.IndexRanges) + } + if report.Skipped != 7 { + t.Fatalf("skipped count = %d, want 7 across disjoint ranges", report.Skipped) + } + files := readDirectoryFiles(t, ledger) + for name := range files { + if strings.HasPrefix(name, "runs/") { + t.Fatalf("updated ledger created a per-run path %q", name) + } + } + hash := sha256.Sum256([]byte("example.com/a")) + shardName := fmt.Sprintf("records/%02x.jsonl", hash[0]) + shard := string(files[shardName]) + if strings.Contains(shard, `"version":"v1.9.0"`) || strings.Contains(shard, `"version":"v1.10.0-rc.1"`) { + t.Fatalf("record shard retained obsolete module versions:\n%s", shard) + } + beforeRerun := readDirectoryFiles(t, ledger) + if err := writeShardedReport(ledger, update); err != nil { + t.Fatal(err) + } + afterRerun := readDirectoryFiles(t, ledger) + if !reflect.DeepEqual(afterRerun, beforeRerun) { + t.Fatal("rerunning an identical reverse range changed the canonical ledger") + } +} + +func TestMergeDiscoveryReportsRejectsPartiallyOverlappingIndexRanges(t *testing.T) { + _, err := mergeDiscoveryReports( + discoveryReport{SchemaVersion: discoverySchema, IndexRanges: []indexRange{{ + Since: "2026-09-01T00:00:00Z", Before: "2026-09-03T00:00:00Z", IndexEntries: 20, + }}}, + discoveryReport{SchemaVersion: discoverySchema, IndexRanges: []indexRange{{ + Since: "2026-09-02T00:00:00Z", Before: "2026-09-04T00:00:00Z", IndexEntries: 20, + }}}, + ) + if err == nil { + t.Fatal("mergeDiscoveryReports() accepted ranges whose aggregate count cannot be computed exactly") + } +} + +func TestMergeDiscoveryReportsRejectsGapBetweenDualCursors(t *testing.T) { + _, err := mergeDiscoveryReports( + discoveryReport{ + SchemaVersion: discoverySchema, + IndexRanges: []indexRange{{ + Since: "2026-09-01T00:00:00Z", Before: "2026-09-02T00:00:00Z", IndexEntries: 20, + }}, + }, + discoveryReport{ + SchemaVersion: discoverySchema, + IndexRanges: []indexRange{{ + Since: "2026-09-03T00:00:00Z", Before: "2026-09-04T00:00:00Z", IndexEntries: 20, + }}, + }, + ) + if err == nil || !strings.Contains(err.Error(), "unverified gap") { + t.Fatalf("mergeDiscoveryReports() error = %v, want dual-cursor gap rejection", err) + } +} + +func TestResolveScanWindowStartsEmptyLedgerAtCurrentTime(t *testing.T) { + now := time.Date(2026, 9, 15, 12, 0, 0, 0, time.UTC) + history, err := resolveScanWindow(&discoveryReport{}, scanModeHistory, "", now) + if err != nil { + t.Fatal(err) + } + if history.Before != now.Format(time.RFC3339Nano) || history.After != indexEpoch { + t.Fatalf("empty history window = %#v", history) + } + incremental, err := resolveScanWindow(&discoveryReport{}, scanModeIncremental, "", now) + if err != nil { + t.Fatal(err) + } + if incremental.Before != now.Format(time.RFC3339Nano) || incremental.After != incremental.Before { + t.Fatalf("empty incremental window = %#v", incremental) + } +} + +func TestEmptyIncrementalScanPersistsStableCursorAnchor(t *testing.T) { + anchor := "2026-09-15T12:00:00Z" + report, err := discover(context.Background(), http.DefaultClient, config{ + indexURL: "https://index.invalid/index", + proxyURL: "https://proxy.invalid", + scanMode: scanModeIncremental, + before: anchor, + after: anchor, + limit: 0, + workers: 1, + maxZipSize: 1, + httpTimeout: time.Second, + }) + if err != nil { + t.Fatal(err) + } + wantRanges := []indexRange{{Since: anchor, Before: anchor, IndexEntries: 0}} + if !reflect.DeepEqual(report.IndexRanges, wantRanges) { + t.Fatalf("empty incremental ranges = %#v, want stable anchor %#v", report.IndexRanges, wantRanges) + } + ledger := filepath.Join(t.TempDir(), "ledger") + if err := writeShardedReport(ledger, report); err != nil { + t.Fatal(err) + } + loaded, err := readShardedReport(ledger) + if err != nil { + t.Fatal(err) + } + next, err := resolveScanWindow(&loaded, scanModeIncremental, "", time.Date(2026, 9, 16, 0, 0, 0, 0, time.UTC)) + if err != nil { + t.Fatal(err) + } + if next.After != anchor { + t.Fatalf("incremental scan lost empty-ledger anchor: %#v", next) + } +} + +func TestResolveScanWindowRejectsHistoryCursorThatWouldLeaveGap(t *testing.T) { + existing := discoveryReport{IndexRanges: []indexRange{{ + Since: "2026-09-14T00:00:00Z", Before: "2026-09-15T00:00:00Z", IndexEntries: 10, + }}} + _, err := resolveScanWindow(&existing, scanModeHistory, "2026-09-13T23:00:00Z", time.Now()) + if err == nil || !strings.Contains(err.Error(), "derived history cursor") { + t.Fatalf("resolveScanWindow() error = %v, want gap prevention", err) + } +} + +func TestMergeDiscoveryReportsNewestExactFailureReplacesOlderSuccess(t *testing.T) { + base := discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{{Path: "example.com/a", Version: "v1.0.0"}}, + Matched: []candidate{{ + Module: "example.com/a", Version: "v1.0.0", AsmFiles: []string{"old_amd64.s"}, + }}, + } + update := discoveryReport{ + SchemaVersion: discoverySchema, + Failures: []scanFailure{{ + Module: "example.com/a", Version: "v1.1.0", Error: "temporary proxy failure", + }}, + } + merged, err := mergeDiscoveryReports(base, update) + if err != nil { + t.Fatal(err) + } + if len(merged.Scanned) != 0 || len(merged.Matched) != 0 { + t.Fatalf("new latest failure retained obsolete successful version: %#v", merged) + } + wantFailure := update.Failures + if !reflect.DeepEqual(merged.Failures, wantFailure) { + t.Fatalf("failures = %#v, want %#v", merged.Failures, wantFailure) + } +} + +func TestMergeDiscoveryReportsMajorUpgradeReplacesLowerModulePaths(t *testing.T) { + base := discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{{Path: "example.com/lib/v2", Version: "v2.99.0"}}, + Matched: []candidate{{ + Module: "example.com/lib/v2", Version: "v2.99.0", AsmFiles: []string{"old_amd64.s"}, + }}, + } + update := discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{{Path: "example.com/lib/v3", Version: "v3.1.0"}}, + Matched: []candidate{{ + Module: "example.com/lib/v3", Version: "v3.1.0", AsmFiles: []string{"new_amd64.s"}, + }}, + } + merged, err := mergeDiscoveryReports(base, update) + if err != nil { + t.Fatal(err) + } + if len(merged.Scanned) != 1 || merged.Scanned[0].Path != "example.com/lib/v3" || + len(merged.Matched) != 1 || merged.Matched[0].Module != "example.com/lib/v3" { + t.Fatalf("major upgrade retained lower module path: %#v", merged) + } + + obsolete := discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{{Path: "example.com/lib/v2", Version: "v2.100.0"}}, + } + merged, err = mergeDiscoveryReports(merged, obsolete) + if err != nil { + t.Fatal(err) + } + if len(merged.Scanned) != 1 || merged.Scanned[0].Path != "example.com/lib/v3" || + len(merged.Matched) != 1 || merged.Matched[0].Module != "example.com/lib/v3" { + t.Fatalf("later lower-major history record displaced v3: %#v", merged) + } +} + +func TestMergeDiscoveryReportsRetainsOnlyCurrentLatestResolutionFailure(t *testing.T) { + base := discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{{Path: "example.com/a", Version: "v1.0.0"}}, + } + failedResolution := discoveryReport{ + SchemaVersion: discoverySchema, + Failures: []scanFailure{{Module: "example.com/a", Version: "@latest", Error: "proxy unavailable"}}, + } + merged, err := mergeDiscoveryReports(base, failedResolution) + if err != nil { + t.Fatal(err) + } + if len(merged.Scanned) != 1 || !reflect.DeepEqual(merged.Failures, failedResolution.Failures) { + t.Fatalf("latest resolution failure did not preserve retry and last exact result: %#v", merged) + } + success := discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{{Path: "example.com/a", Version: "v1.1.0"}}, + } + merged, err = mergeDiscoveryReports(merged, success) + if err != nil { + t.Fatal(err) + } + if !reflect.DeepEqual(merged.Scanned, success.Scanned) || len(merged.Failures) != 0 { + t.Fatalf("successful latest resolution retained obsolete records: %#v", merged) + } +} + +func TestMergeDiscoveryReportsPreservesUntouchedLatestResolutionFailure(t *testing.T) { + base := discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{{Path: "example.com/a", Version: "v1.0.0"}}, + Failures: []scanFailure{{Module: "example.com/a", Version: "@latest", Error: "proxy unavailable"}}, + } + update := discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{{Path: "example.com/b", Version: "v2.0.0"}}, + } + merged, err := mergeDiscoveryReports(base, update) + if err != nil { + t.Fatal(err) + } + if !reflect.DeepEqual(merged.Failures, base.Failures) { + t.Fatalf("unrelated update discarded retryable @latest failure: %#v", merged) + } +} + +func TestSortDiscoveryReportUsesGoSemver(t *testing.T) { + report := discoveryReport{Scanned: []moduleVersion{ + {Path: "example.com/a", Version: "v1.10.1-0.20260914000000-0123456789ab"}, + {Path: "example.com/a", Version: "v1.10.0+incompatible"}, + {Path: "example.com/a", Version: "v1.9.0"}, + {Path: "example.com/a", Version: "v1.10.0"}, + {Path: "example.com/a", Version: "v1.10.0-rc.1"}, + }} + sortDiscoveryReport(&report) + want := []string{ + "v1.9.0", + "v1.10.0-rc.1", + "v1.10.0", + "v1.10.0+incompatible", + "v1.10.1-0.20260914000000-0123456789ab", + } + for i, item := range report.Scanned { + if item.Version != want[i] { + t.Fatalf("semver order[%d] = %q, want %q; all: %#v", i, item.Version, want[i], report.Scanned) + } + } +} + +func TestLoadSeenReportsAcceptsSingleLedgerDirectory(t *testing.T) { + ledger := filepath.Join(t.TempDir(), "ledger") + report := discoveryReport{ + SchemaVersion: discoverySchema, + Scanned: []moduleVersion{ + {Path: "example.com/a", Version: "v1.0.0"}, + {Path: "example.com/b", Version: "v2.0.0"}, + }, + } + if err := writeShardedReport(ledger, report); err != nil { + t.Fatal(err) + } + seen, err := loadSeenReports([]string{ledger}) + if err != nil { + t.Fatal(err) + } + for _, item := range []moduleVersion{ + {Path: "example.com/a", Version: "v1.0.0"}, + {Path: "example.com/b", Version: "v2.0.0"}, + } { + if _, ok := seen[scanKey(item)]; !ok { + t.Errorf("ledger directory omitted %s@%s", item.Path, item.Version) + } + } + loaded, err := readSeenReport(ledger) + if err != nil { + t.Fatal(err) + } + if len(loaded.Scanned) != 2 || len(loaded.Failures) != 0 || loaded.UniqueModules != 2 { + t.Fatalf("ledger report was not normalized: %#v", loaded) + } +} + +func TestShardedReportRejectsInvalidOrUnsafeInput(t *testing.T) { + t.Run("existing output without manifest", func(t *testing.T) { + dir := t.TempDir() + if err := writeShardedReport(dir, discoveryReport{SchemaVersion: discoverySchema}); err == nil { + t.Fatal("writeShardedReport() overwrote a directory that is not a ledger") + } + }) + + t.Run("missing manifest", func(t *testing.T) { + if _, err := readSeenReport(t.TempDir()); err == nil { + t.Fatal("readSeenReport() accepted a directory without a manifest") + } + }) + + tests := map[string]struct { + manifest shardedManifest + record string + }{ + "unsupported format": { + manifest: shardedManifest{SchemaVersion: discoverySchema, Format: "unknown"}, + }, + "invalid JSONL": { + manifest: shardedManifest{SchemaVersion: discoverySchema, Format: shardedFormat, Scanned: 1}, + record: "not json\n", + }, + "incomplete module": { + manifest: shardedManifest{SchemaVersion: discoverySchema, Format: shardedFormat, Scanned: 1}, + record: `{"kind":"scanned","module":"example.com/lib"}` + "\n", + }, + "unknown kind": { + manifest: shardedManifest{SchemaVersion: discoverySchema, Format: shardedFormat, Scanned: 1}, + record: `{"kind":"mystery","module":"example.com/lib","version":"v1.0.0"}` + "\n", + }, + "wrong count": { + manifest: shardedManifest{SchemaVersion: discoverySchema, Format: shardedFormat, Scanned: 2}, + record: `{"kind":"scanned","module":"example.com/lib","version":"v1.0.0"}` + "\n", + }, + } + for name, test := range tests { + t.Run(name, func(t *testing.T) { + dir := t.TempDir() + manifest, err := json.Marshal(test.manifest) + if err != nil { + t.Fatal(err) + } + if err := os.WriteFile(filepath.Join(dir, "manifest.json"), manifest, 0o600); err != nil { + t.Fatal(err) + } + if test.record != "" { + if err := os.Mkdir(filepath.Join(dir, "records"), 0o700); err != nil { + t.Fatal(err) + } + if err := os.WriteFile(filepath.Join(dir, "records", "00.jsonl"), []byte(test.record), 0o600); err != nil { + t.Fatal(err) + } + } + if _, err := readSeenReport(dir); err == nil { + t.Fatal("readSeenReport() accepted an invalid sharded report") + } + }) + } +} + +func TestShardedReportRefusesConcurrentLedgerWriter(t *testing.T) { + ledger := filepath.Join(t.TempDir(), "ledger") + release, err := acquireLedgerLock(ledger) + if err != nil { + t.Fatal(err) + } + defer func() { + if err := release(); err != nil { + t.Error(err) + } + }() + err = writeShardedReport(ledger, discoveryReport{SchemaVersion: discoverySchema}) + if err == nil || !strings.Contains(err.Error(), "another discovery writer") { + t.Fatalf("writeShardedReport() with held lock error = %v", err) + } +} + +func readDirectoryFiles(t *testing.T, root string) map[string][]byte { + t.Helper() + files := make(map[string][]byte) + err := filepath.WalkDir(root, func(name string, entry os.DirEntry, err error) error { + if err != nil { + return err + } + if entry.IsDir() { + return nil + } + data, err := os.ReadFile(name) + if err != nil { + return err + } + relative, err := filepath.Rel(root, name) + if err != nil { + return err + } + files[filepath.ToSlash(relative)] = data + return nil + }) + if err != nil { + t.Fatal(err) + } + return files +} + +func TestSeenReportsRejectInvalidInput(t *testing.T) { + tests := map[string][]byte{ + "invalid-json": []byte("not json"), + "invalid-gzip-header": {0x1f, 0x8b}, + } + var compressed bytes.Buffer + zw := gzip.NewWriter(&compressed) + _, _ = zw.Write([]byte(`{"schema_version":2}`)) + if err := zw.Close(); err != nil { + t.Fatal(err) + } + corrupt := append([]byte(nil), compressed.Bytes()...) + corrupt[len(corrupt)-1] ^= 0xff + tests["invalid-gzip-checksum"] = corrupt + + for name, data := range tests { + t.Run(name, func(t *testing.T) { + reportPath := filepath.Join(t.TempDir(), name) + if err := os.WriteFile(reportPath, data, 0o600); err != nil { + t.Fatal(err) + } + if _, err := loadSeenReports([]string{reportPath}); err == nil { + t.Fatal("loadSeenReports() accepted invalid input") + } + }) + } + + if _, err := loadSeenReports([]string{filepath.Join(t.TempDir(), "missing.json")}); err == nil { + t.Fatal("loadSeenReports() accepted a missing report") + } +} + +func TestCommittedScanLedger(t *testing.T) { + reportPath := filepath.Join("..", "..", "testdata", "discovery", "ledger") + err := filepath.WalkDir(filepath.Dir(reportPath), func(name string, entry os.DirEntry, err error) error { + if err != nil { + return err + } + if !entry.IsDir() && strings.HasSuffix(entry.Name(), ".gz") { + t.Errorf("compressed discovery result must not be committed: %s", name) + } + if relative, relErr := filepath.Rel(reportPath, name); relErr == nil { + relative = filepath.ToSlash(relative) + if relative == "." || relative == ".." || strings.HasPrefix(relative, "../") { + return nil + } + parts := strings.Split(relative, "/") + if parts[0] != "manifest.json" && parts[0] != "records" { + t.Errorf("discovery ledger contains a per-run or unexpected path: %s", relative) + } + if len(parts) > 2 { + t.Errorf("discovery ledger must have exactly one records directory: %s", relative) + } + } + return nil + }) + if err != nil { + t.Fatal(err) + } + report, err := readSeenReport(reportPath) + if err != nil { + t.Fatal(err) + } + if report.SchemaVersion != discoverySchema { + t.Fatalf("ledger schema = %d, want %d", report.SchemaVersion, discoverySchema) + } + if report.IndexEntries == 0 || len(report.Scanned) == 0 { + t.Fatalf("ledger is empty: %d index entries, %d scanned versions", report.IndexEntries, len(report.Scanned)) + } + if report.ScanDirection != "bidirectional" { + t.Fatalf("ledger scan direction = %q, want bidirectional", report.ScanDirection) + } + historyBefore := earliestIndexRangeLower(report.IndexRanges) + if _, err := time.Parse(time.RFC3339Nano, historyBefore); err != nil { + t.Fatalf("invalid derived history ledger cursor %q: %v", historyBefore, err) + } + incrementalSince := latestIndexRangeUpper(report.IndexRanges) + if _, err := time.Parse(time.RFC3339Nano, incrementalSince); err != nil { + t.Fatalf("invalid derived incremental ledger cursor %q: %v", incrementalSince, err) + } + entries := 0 + for _, item := range report.IndexRanges { + entries += item.IndexEntries + } + if entries != report.IndexEntries { + t.Fatalf("ledger index ranges contain %d entries, want manifest total %d", entries, report.IndexEntries) + } + + seen, err := loadSeenReports([]string{reportPath}) + if err != nil { + t.Fatal(err) + } + if len(seen) != len(report.Scanned) { + t.Fatalf("ledger has %d unique completed versions, want %d", len(seen), len(report.Scanned)) + } + for _, item := range report.Matched { + key := scanKey(moduleVersion{Path: item.Module, Version: item.Version}) + if _, ok := seen[key]; !ok { + t.Errorf("assembly match is not recorded as scanned: %s@%s", item.Module, item.Version) + } + } + for _, item := range report.Failures { + key := scanKey(moduleVersion{Path: item.Module, Version: item.Version}) + if _, ok := seen[key]; ok { + t.Errorf("failed version must remain eligible for retry: %s@%s", item.Module, item.Version) + } + } + + issueMatches := map[string]candidate{} + for _, item := range report.Matched { + issueMatches[scanKey(moduleVersion{Path: item.Module, Version: item.Version})] = item + } + wantIssueFiles := map[string][]string{ + scanKey(moduleVersion{Path: "github.com/coder/websocket", Version: "v1.8.15"}): { + "mask_amd64.s", + "mask_arm64.s", + }, + scanKey(moduleVersion{Path: "github.com/klauspost/compress", Version: "v1.20.0"}): { + "huff0/decompress_amd64.s", + "huff0/decompress_arm64.s", + "internal/cpuinfo/cpuinfo_amd64.s", + "s2/decode_amd64.s", + "s2/decode_arm64.s", + "s2/encodeblock_amd64.s", + "s2/encodeblock_arm64.s", + "zstd/fse_decoder_amd64.s", + "zstd/fse_decoder_arm64.s", + "zstd/internal/xxhash/xxhash_amd64.s", + "zstd/internal/xxhash/xxhash_arm64.s", + "zstd/matchlen_amd64.s", + "zstd/seqdec_amd64.s", + "zstd/seqdec_arm64.s", + }, + scanKey(moduleVersion{Path: "github.com/tmthrgd/go-hex", Version: "v0.0.0-20190904060850-447a3041c3bc"}): { + "hex_decode_amd64.s", + "hex_encode_amd64.s", + }, + } + for exactKey, wantFiles := range wantIssueFiles { + match, ok := issueMatches[exactKey] + if !ok { + t.Errorf("issue library version was not independently discovered: %s", strings.Replace(exactKey, "\x00", "@", 1)) + continue + } + if !reflect.DeepEqual(match.AsmFiles, wantFiles) { + t.Errorf("discovered assembly for %s = %#v, want %#v", strings.Replace(exactKey, "\x00", "@", 1), match.AsmFiles, wantFiles) + } + } +} + +func TestInspectModulesRecordsLatestVersionWhenInspectionFails(t *testing.T) { + archive := testModuleZip(t) + server := httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + switch { + case strings.HasSuffix(r.URL.Path, "/@latest"): + _, _ = io.WriteString(w, `{"Version":"v1.1.0"}`) + case strings.HasSuffix(r.URL.Path, "/@v/v1.0.0.zip"): + serveRangeData(t, w, r, archive) + case strings.HasSuffix(r.URL.Path, "/@v/v1.1.0.zip"): + http.Error(w, "missing", http.StatusNotFound) + default: + http.NotFound(w, r) + } + })) + defer server.Close() + + matched, failures, scanned, skipped := inspectModules(context.Background(), server.Client(), server.URL, []moduleVersion{ + {Path: "example.com/lib", Version: "v1.0.0"}, + }, nil, nil, 1, int64(len(archive))+1) + if len(matched) != 0 || len(failures) != 1 { + t.Fatalf("inspectModules() matched %d and failed %d modules, want 0 and 1", len(matched), len(failures)) + } + if len(scanned) != 0 { + t.Fatalf("scanned versions = %#v, want none", scanned) + } + if failures[0].Module != "example.com/lib" || failures[0].Version != "v1.1.0" { + t.Fatalf("failure version = %#v, want exact latest version", failures[0]) + } + if skipped != 0 { + t.Fatalf("skipped versions = %d, want 0", skipped) + } +} + +func TestInspectModulesRecordsLatestResolutionFailure(t *testing.T) { + server := httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + if strings.HasSuffix(r.URL.Path, "/@latest") { + _, _ = io.WriteString(w, `{}`) + return + } + http.NotFound(w, r) + })) + defer server.Close() + + matched, failures, scanned, skipped := inspectModules(context.Background(), server.Client(), server.URL, []moduleVersion{ + {Path: "example.com/lib", Version: "v1.0.0"}, + }, nil, nil, 1, 1<<20) + if len(matched) != 0 || len(scanned) != 0 || skipped != 0 || len(failures) != 1 { + t.Fatalf("unexpected result: matched=%#v failures=%#v scanned=%#v skipped=%d", matched, failures, scanned, skipped) + } + if failures[0].Version != "@latest" || failures[0].Error != "decode @latest: missing Version" { + t.Fatalf("resolution failure = %#v", failures[0]) + } +} + +func TestInspectModulesSkipsPreviouslyCompletedLatestVersion(t *testing.T) { + archive := testModuleZip(t) + var latestZipRequests atomic.Int64 + server := httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + switch { + case strings.HasSuffix(r.URL.Path, "/@latest"): + _, _ = io.WriteString(w, `{"Version":"v1.1.0"}`) + case strings.HasSuffix(r.URL.Path, "/@v/v1.0.0.zip"): + serveRangeData(t, w, r, archive) + case strings.HasSuffix(r.URL.Path, "/@v/v1.1.0.zip"): + latestZipRequests.Add(1) + serveRangeData(t, w, r, archive) + default: + http.NotFound(w, r) + } + })) + defer server.Close() + + latest := moduleVersion{Path: "example.com/lib", Version: "v1.1.0"} + priorMatch := candidate{ + Module: latest.Path, Version: latest.Version, + Architectures: []string{"amd64"}, AsmFiles: []string{"asm_amd64.s"}, + } + collector := newTrafficCollector() + ctx := context.WithValue(context.Background(), trafficCollectorContextKey{}, collector) + matched, failures, scanned, skipped := inspectModules(ctx, server.Client(), server.URL, []moduleVersion{ + {Path: "example.com/lib", Version: "v1.0.0"}, + }, map[string]seenResult{scanKey(latest): {Match: priorMatch}}, nil, 1, int64(len(archive))+1) + if !reflect.DeepEqual(matched, []candidate{priorMatch}) || len(failures) != 0 { + t.Fatalf("inspectModules() matched %#v and failed %d modules, want reused match", matched, len(failures)) + } + wantScanned := []moduleVersion{latest} + if !reflect.DeepEqual(scanned, wantScanned) { + t.Fatalf("scanned versions = %#v, want reused latest checkpoint %#v", scanned, wantScanned) + } + if got := latestZipRequests.Load(); got != 0 { + t.Fatalf("previously completed latest version fetched %d times, want 0", got) + } + if skipped != 1 { + t.Fatalf("skipped versions = %d, want 1", skipped) + } + report := collector.snapshot(time.Unix(0, 0).UTC(), scanModeHistory, discoveryReport{}) + if len(report.Modules) != 1 || report.Modules[0].Outcome != "reused_matched" { + t.Fatalf("reused match traffic outcome = %#v, want reused_matched", report.Modules) + } +} + +func TestInspectModulesReusesGitHubPseudoVersionCaseAlias(t *testing.T) { + version := "v0.0.0-20260914132724-051eaffddbc5" + var zipRequests atomic.Int64 + server := httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + if strings.HasSuffix(r.URL.Path, "/@latest") { + _, _ = fmt.Fprintf(w, `{"Version":%q}`, version) + return + } + zipRequests.Add(1) + http.Error(w, "ZIP must be reused", http.StatusInternalServerError) + })) + defer server.Close() + + upper := moduleVersion{Path: "github.com/L2Beat/l2beat", Version: version} + lower := moduleVersion{Path: "github.com/l2beat/l2beat", Version: version} + prior := candidate{Module: upper.Path, Version: version, AsmFiles: []string{"asm_amd64.s"}} + sourceSeen := map[string]seenResult{sourceScanKey(upper): {Match: prior}} + matched, failures, scanned, skipped := inspectModules( + context.Background(), server.Client(), server.URL, + []moduleVersion{lower}, nil, sourceSeen, 1, 1<<20, + ) + wantMatch := prior + wantMatch.Module = lower.Path + if !reflect.DeepEqual(matched, []candidate{wantMatch}) || len(failures) != 0 || !reflect.DeepEqual(scanned, []moduleVersion{lower}) || skipped != 1 { + t.Fatalf("case-alias reuse = matched %#v failures %#v scanned %#v skipped %d", matched, failures, scanned, skipped) + } + if got := zipRequests.Load(); got != 0 { + t.Fatalf("case-alias pseudo-version fetched ZIP %d times, want 0", got) + } +} + +func TestInspectModulesCoalescesConcurrentGitHubPseudoVersionCaseAliases(t *testing.T) { + version := "v0.0.0-20260914132724-051eaffddbc5" + archive := testModuleZip(t) + var latestRequests atomic.Int64 + var zipRequests atomic.Int64 + latestReady := make(chan struct{}) + server := httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + if strings.HasSuffix(r.URL.Path, "/@latest") { + if latestRequests.Add(1) == 2 { + close(latestReady) + } + <-latestReady + _, _ = fmt.Fprintf(w, `{"Version":%q}`, version) + return + } + zipRequests.Add(1) + serveRangeData(t, w, r, archive) + })) + defer server.Close() + + collector := newTrafficCollector() + ctx := context.WithValue(context.Background(), trafficCollectorContextKey{}, collector) + modules := []moduleVersion{ + {Path: "github.com/L2Beat/l2beat", Version: version}, + {Path: "github.com/l2beat/l2beat", Version: version}, + } + matched, failures, scanned, skipped := inspectModules( + ctx, server.Client(), server.URL, modules, nil, nil, 2, int64(len(archive))+1, + ) + if len(matched) != 2 || len(failures) != 0 || len(scanned) != 2 || skipped != 1 { + t.Fatalf("concurrent alias result = matched %d failures %d scanned %d skipped %d", len(matched), len(failures), len(scanned), skipped) + } + if got := zipRequests.Load(); got != 2 { + t.Fatalf("concurrent aliases made %d ZIP requests, want one HEAD and one body request", got) + } + report := collector.snapshot(time.Unix(0, 0).UTC(), scanModeHistory, discoveryReport{}) + var outcomes []string + for _, item := range report.Modules { + outcomes = append(outcomes, item.Outcome) + } + sort.Strings(outcomes) + if want := []string{"matched", "reused_matched"}; !reflect.DeepEqual(outcomes, want) { + t.Fatalf("concurrent alias outcomes = %#v, want %#v", outcomes, want) + } +} + +func TestInspectModulesChecksLatestWhenIndexedVersionHasNoAssembly(t *testing.T) { + var noAsm bytes.Buffer + zw := zip.NewWriter(&noAsm) + file, err := zw.Create("example.com/lib@v1.0.0/lib.go") + if err != nil { + t.Fatal(err) + } + if _, err := file.Write([]byte("package lib\n")); err != nil { + t.Fatal(err) + } + if err := zw.Close(); err != nil { + t.Fatal(err) + } + latestArchive := testModuleZip(t) + var indexedZipRequests atomic.Int64 + server := httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + switch { + case strings.HasSuffix(r.URL.Path, "/@latest"): + _, _ = io.WriteString(w, `{"Version":"v1.1.0"}`) + case strings.HasSuffix(r.URL.Path, "/@v/v1.0.0.zip"): + indexedZipRequests.Add(1) + serveRangeData(t, w, r, noAsm.Bytes()) + case strings.HasSuffix(r.URL.Path, "/@v/v1.1.0.zip"): + serveRangeData(t, w, r, latestArchive) + default: + http.NotFound(w, r) + } + })) + defer server.Close() + + matched, failures, scanned, skipped := inspectModules(context.Background(), server.Client(), server.URL, []moduleVersion{ + {Path: "example.com/lib", Version: "v1.0.0"}, + }, nil, nil, 1, int64(len(latestArchive))+1) + if len(failures) != 0 { + t.Fatalf("inspectModules() failures = %#v", failures) + } + wantScanned := []moduleVersion{{Path: "example.com/lib", Version: "v1.1.0"}} + if !reflect.DeepEqual(scanned, wantScanned) { + t.Fatalf("scanned versions = %#v, want %#v", scanned, wantScanned) + } + if len(matched) != 1 || matched[0].Module != "example.com/lib" || matched[0].Version != "v1.1.0" { + t.Fatalf("matched versions = %#v, want latest module version", matched) + } + if got := indexedZipRequests.Load(); got != 0 { + t.Fatalf("indexed archive fetched %d times, want 0; index should only discover module paths", got) + } + if skipped != 0 { + t.Fatalf("skipped versions = %d, want 0", skipped) + } +} + +func TestDiscoverDoesNotTreatAnIndexedVersionAsTheLatestCheckpoint(t *testing.T) { + archive := testModuleZip(t) + server := httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + switch { + case r.URL.Path == "/index": + _ = json.NewEncoder(w).Encode(indexEntry{ + Path: "example.com/lib", + Version: "v1.0.0", + Timestamp: time.Date(2019, 4, 10, 0, 0, 0, 0, time.UTC), + }) + case strings.HasSuffix(r.URL.Path, "/@latest"): + _, _ = io.WriteString(w, `{"Version":"v1.1.0"}`) + case strings.HasSuffix(r.URL.Path, "/@v/v1.1.0.zip"): + serveRangeData(t, w, r, archive) + default: + http.NotFound(w, r) + } + })) + defer server.Close() + + report, err := discover(context.Background(), server.Client(), config{ + indexURL: server.URL + "/index", + proxyURL: server.URL, + scanMode: scanModeHistory, + before: time.Date(2019, 4, 10, 0, 0, 1, 0, time.UTC).Format(time.RFC3339Nano), + after: indexEpoch, + limit: 1, + workers: 1, + maxZipSize: int64(len(archive)) + 1, + httpTimeout: time.Second, + seen: map[string]seenResult{ + scanKey(moduleVersion{Path: "example.com/lib", Version: "v1.0.0"}): {}, + }, + }) + if err != nil { + t.Fatal(err) + } + want := []moduleVersion{{Path: "example.com/lib", Version: "v1.1.0"}} + if !reflect.DeepEqual(report.Scanned, want) { + t.Fatalf("scanned versions = %#v, want latest %#v", report.Scanned, want) + } +} + +func TestModulesNeedingInspectionSkipsOlderIndexedVersionsByModule(t *testing.T) { + entries := []indexEntry{ + {Path: "example.com/already", Version: "v1.0.0"}, + {Path: "example.com/already", Version: "v1.1.0"}, + {Path: "example.com/new-release", Version: "v1.2.0"}, + {Path: "example.com/retry-separately", Version: "v9.0.0"}, + {Path: "example.com/unseen", Version: "v0.1.0"}, + } + checkpoints := map[string]moduleCheckpoint{ + "example.com/already": {Path: "example.com/already", Version: "v1.1.0"}, + "example.com/new-release": {Path: "example.com/new-release", Version: "v1.1.0"}, + "example.com/retry-separately": {Path: "example.com/retry-separately", Version: "@latest"}, + } + got, skipped := modulesNeedingInspection(entries, checkpoints) + want := []moduleVersion{ + {Path: "example.com/new-release", Version: "v1.2.0"}, + {Path: "example.com/unseen", Version: "v0.1.0"}, + } + if !reflect.DeepEqual(got, want) { + t.Fatalf("modulesNeedingInspection() = %#v, want %#v", got, want) + } + if skipped != 2 { + t.Fatalf("skipped module paths = %d, want 2", skipped) + } +} + +func TestModulesNeedingInspectionKeepsOnlyHighestModulePathMajor(t *testing.T) { + entries := []indexEntry{ + {Path: "example.com/lib/v2", Version: "v2.9.0"}, + {Path: "example.com/lib", Version: "v1.10.0"}, + {Path: "example.com/lib/v3", Version: "v3.1.0"}, + {Path: "gopkg.in/yaml.v2", Version: "v2.4.0"}, + {Path: "gopkg.in/yaml.v3", Version: "v3.0.1"}, + } + got, skipped := modulesNeedingInspection(entries, nil) + want := []moduleVersion{ + {Path: "example.com/lib/v3", Version: "v3.1.0"}, + {Path: "gopkg.in/yaml.v3", Version: "v3.0.1"}, + } + if !reflect.DeepEqual(got, want) { + t.Fatalf("modulesNeedingInspection() = %#v, want only highest majors %#v", got, want) + } + if skipped != 3 { + t.Fatalf("skipped obsolete major paths = %d, want 3", skipped) + } +} + +func TestModulesNeedingInspectionOrdersByMajorThenSemverAcrossHistory(t *testing.T) { + checkpoints := map[string]moduleCheckpoint{} + + first, _ := modulesNeedingInspection([]indexEntry{ + {Path: "example.com/lib/v2", Version: "v2.9.0"}, + }, checkpoints) + if want := []moduleVersion{{Path: "example.com/lib/v2", Version: "v2.9.0"}}; !reflect.DeepEqual(first, want) { + t.Fatalf("first history window = %#v, want %#v", first, want) + } + chooseModuleCheckpoint(checkpoints, first[0].Path, first[0].Version) + + // This v3 index record is older than the v2 record above, but the module + // path major has priority over both index time and the v2 semver. + second, _ := modulesNeedingInspection([]indexEntry{ + {Path: "example.com/lib/v3", Version: "v3.1.0"}, + }, checkpoints) + if want := []moduleVersion{{Path: "example.com/lib/v3", Version: "v3.1.0"}}; !reflect.DeepEqual(second, want) { + t.Fatalf("older history window = %#v, want major upgrade %#v", second, want) + } + chooseModuleCheckpoint(checkpoints, second[0].Path, second[0].Version) + + obsolete, _ := modulesNeedingInspection([]indexEntry{ + {Path: "example.com/lib", Version: "v1.99.0"}, + {Path: "example.com/lib/v2", Version: "v2.99.0"}, + {Path: "example.com/lib/v3", Version: "v3.0.0"}, + }, checkpoints) + if len(obsolete) != 0 { + t.Fatalf("later history revisited lower priority modules: %#v", obsolete) + } + + upgrade, _ := modulesNeedingInspection([]indexEntry{ + {Path: "example.com/lib/v3", Version: "v3.2.0"}, + }, checkpoints) + if want := []moduleVersion{{Path: "example.com/lib/v3", Version: "v3.2.0"}}; !reflect.DeepEqual(upgrade, want) { + t.Fatalf("incremental same-major upgrade = %#v, want %#v", upgrade, want) + } +} + +func TestModulesNeedingInspectionUsesSemverNotIndexArrivalOrder(t *testing.T) { + entries := []indexEntry{ + {Path: "example.com/lib/v3", Version: "v3.2.0"}, + {Path: "example.com/lib/v3", Version: "v3.1.0"}, + } + got, _ := modulesNeedingInspection(entries, nil) + want := []moduleVersion{{Path: "example.com/lib/v3", Version: "v3.2.0"}} + if !reflect.DeepEqual(got, want) { + t.Fatalf("modulesNeedingInspection() = %#v, want semver maximum %#v", got, want) + } +} + +func TestModulesNeedingInspectionAllowsNewMajorPastCheckpoint(t *testing.T) { + entries := []indexEntry{ + {Path: "example.com/lib", Version: "v1.10.0"}, + {Path: "example.com/lib/v2", Version: "v2.9.0"}, + {Path: "example.com/lib/v3", Version: "v3.0.0"}, + } + checkpoints := map[string]moduleCheckpoint{ + "example.com/lib": {Path: "example.com/lib/v2", Version: "v2.8.0"}, + } + got, _ := modulesNeedingInspection(entries, checkpoints) + want := []moduleVersion{{Path: "example.com/lib/v3", Version: "v3.0.0"}} + if !reflect.DeepEqual(got, want) { + t.Fatalf("modulesNeedingInspection() = %#v, want new major %#v", got, want) + } +} + +func TestModulesNeedingInspectionAllowsNewMajorPastLatestFailure(t *testing.T) { + entries := []indexEntry{{Path: "example.com/lib/v3", Version: "v3.0.0"}} + checkpoints := map[string]moduleCheckpoint{ + "example.com/lib": {Path: "example.com/lib/v2", Version: "@latest"}, + } + got, _ := modulesNeedingInspection(entries, checkpoints) + want := []moduleVersion{{Path: "example.com/lib/v3", Version: "v3.0.0"}} + if !reflect.DeepEqual(got, want) { + t.Fatalf("modulesNeedingInspection() = %#v, want new major past v2 retry %#v", got, want) + } +} + +func TestResolveScanWindowSeparatesHistoryAndIncrementalCursors(t *testing.T) { + now := time.Date(2026, 9, 15, 12, 0, 0, 0, time.UTC) + existing := discoveryReport{ + IndexRanges: []indexRange{ + {Since: "2025-01-01T00:00:00Z", Before: "2026-09-15T00:00:00Z", IndexEntries: 100}, + }, + } + + history, err := resolveScanWindow(&existing, scanModeHistory, "", now) + if err != nil { + t.Fatal(err) + } + if history.Before != "2025-01-01T00:00:00Z" || history.After != indexEpoch { + t.Fatalf("history window = %#v, want only the saved backwards cursor", history) + } + + incremental, err := resolveScanWindow(&existing, scanModeIncremental, "", now) + if err != nil { + t.Fatal(err) + } + if incremental.Before != now.Format(time.RFC3339Nano) || incremental.After != "2026-09-15T00:00:00Z" { + t.Fatalf("incremental window = %#v, want only the new head interval", incremental) + } +} + +func TestResolveScanWindowAllowsIncrementalBeforeHistoryCompletes(t *testing.T) { + existing := discoveryReport{ + IndexRanges: []indexRange{{ + Since: "2025-01-01T00:00:00Z", Before: "2026-09-15T00:00:00Z", IndexEntries: 10, + }}, + } + window, err := resolveScanWindow(&existing, scanModeIncremental, "", time.Date(2026, 9, 16, 0, 0, 0, 0, time.UTC)) + if err != nil { t.Fatal(err) } - seen, err := loadSeenReports([]string{reportPath}) + if window.After != "2026-09-15T00:00:00Z" { + t.Fatalf("incremental window = %#v, want independent head cursor", window) + } +} + +func TestMergeDiscoveryReportsDerivesDualCursorsFromRanges(t *testing.T) { + base := discoveryReport{ + SchemaVersion: discoverySchema, + IndexRanges: []indexRange{{ + Since: "2025-01-01T00:00:00Z", Before: "2026-09-15T00:00:00Z", IndexEntries: 10, + }}, + } + history := discoveryReport{ + SchemaVersion: discoverySchema, + IndexRanges: []indexRange{{ + Since: "2024-01-01T00:00:00Z", Before: "2025-01-01T00:00:00Z", IndexEntries: 20, + }}, + } + merged, err := mergeDiscoveryReports(base, history) if err != nil { t.Fatal(err) } - pending, skipped := filterPreviouslyScanned([]moduleVersion{ - {Path: "example.com/a", Version: "v1.0.0"}, - {Path: "example.com/a", Version: "v1.1.0"}, - {Path: "example.com/noasm", Version: "v2.0.0"}, - {Path: "example.com/old-match", Version: "v3.0.0"}, - {Path: "example.com/new", Version: "v1.0.0"}, - }, seen) - want := []moduleVersion{ - {Path: "example.com/a", Version: "v1.1.0"}, - {Path: "example.com/new", Version: "v1.0.0"}, + if earliestIndexRangeLower(merged.IndexRanges) != "2024-01-01T00:00:00Z" || latestIndexRangeUpper(merged.IndexRanges) != "2026-09-15T00:00:00Z" { + t.Fatalf("history merge cursors = %#v", merged) + } + incremental := discoveryReport{ + SchemaVersion: discoverySchema, + IndexRanges: []indexRange{{ + Since: "2026-09-15T00:00:00Z", Before: "2026-09-16T00:00:00Z", IndexEntries: 3, + }}, + } + merged, err = mergeDiscoveryReports(merged, incremental) + if err != nil { + t.Fatal(err) } - if !reflect.DeepEqual(pending, want) || skipped != 3 { - t.Fatalf("filterPreviouslyScanned() = (%#v, %d), want (%#v, 3)", pending, skipped, want) + if earliestIndexRangeLower(merged.IndexRanges) != "2024-01-01T00:00:00Z" || latestIndexRangeUpper(merged.IndexRanges) != "2026-09-16T00:00:00Z" { + t.Fatalf("incremental merge cursors = %#v", merged) } } -func TestInspectModulesRecordsIndexedVersionWhenLatestFails(t *testing.T) { - archive := testModuleZip(t) - server := httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { - switch { - case strings.HasSuffix(r.URL.Path, "/@latest"): - _, _ = io.WriteString(w, `{"Version":"v1.1.0"}`) - case strings.HasSuffix(r.URL.Path, "/@v/v1.0.0.zip"): - serveRangeData(t, w, r, archive) - case strings.HasSuffix(r.URL.Path, "/@v/v1.1.0.zip"): - http.Error(w, "missing", http.StatusNotFound) - default: - http.NotFound(w, r) - } - })) - defer server.Close() +func TestReverseIndexSpanHintUsesAdjacentCoveredRange(t *testing.T) { + existing := &discoveryReport{IndexRanges: []indexRange{{ + Since: "2026-09-14T20:00:00Z", Before: "2026-09-15T00:00:00Z", IndexEntries: 20_000, + }}} + got := reverseIndexSpanHint(existing, scanWindow{Before: "2026-09-14T20:00:00Z", After: indexEpoch}) + want := time.Duration(float64(4*time.Hour) * float64(reversePageTarget) / 20_000) + if got != want { + t.Fatalf("history span hint = %s, want %s", got, want) + } + got = reverseIndexSpanHint(existing, scanWindow{Before: "2026-09-15T01:00:00Z", After: "2026-09-15T00:00:00Z"}) + if got != want { + t.Fatalf("incremental span hint = %s, want %s", got, want) + } +} - matched, failures, scanned := inspectModules(context.Background(), server.Client(), server.URL, []moduleVersion{ - {Path: "example.com/lib", Version: "v1.0.0"}, - }, 1, int64(len(archive))+1) - if len(matched) != 0 || len(failures) != 1 { - t.Fatalf("inspectModules() matched %d and failed %d modules, want 0 and 1", len(matched), len(failures)) +func TestModuleCheckpointsIncludeFailuresWithoutDowngradingExactVersion(t *testing.T) { + report := discoveryReport{ + Scanned: []moduleVersion{ + {Path: "example.com/a", Version: "v1.1.0"}, + {Path: "example.com/b", Version: "v2.0.0"}, + }, + Failures: []scanFailure{ + {Module: "example.com/a", Version: "v1.0.0", Error: "old failure"}, + {Module: "example.com/b", Version: "@latest", Error: "retry separately"}, + {Module: "example.com/c", Version: "v3.0.0", Error: "retry separately"}, + }, + } + want := map[string]moduleCheckpoint{ + "example.com/a": {Path: "example.com/a", Version: "v1.1.0"}, + "example.com/b": {Path: "example.com/b", Version: "@latest"}, + "example.com/c": {Path: "example.com/c", Version: "v3.0.0"}, } - want := []moduleVersion{{Path: "example.com/lib", Version: "v1.0.0"}} - if !reflect.DeepEqual(scanned, want) { - t.Fatalf("scanned versions = %#v, want %#v", scanned, want) + if got := moduleCheckpoints(report); !reflect.DeepEqual(got, want) { + t.Fatalf("moduleCheckpoints() = %#v, want %#v", got, want) + } +} + +func TestModulesForFailureRetryUsesHighestMajorThenSemver(t *testing.T) { + report := discoveryReport{Failures: []scanFailure{ + {Module: "example.com/lib/v2", Version: "v2.9.0", Error: "old v2"}, + {Module: "example.com/lib/v3", Version: "v3.1.0", Error: "current v3"}, + {Module: "example.com/other", Version: "v1.0.0", Error: "exact failed"}, + {Module: "example.com/other", Version: "@latest", Error: "resolution failed"}, + }} + got := modulesForFailureRetry(report) + want := []moduleVersion{ + {Path: "example.com/lib/v3", Version: "v3.1.0"}, + {Path: "example.com/other", Version: "@latest"}, + } + if !reflect.DeepEqual(got, want) { + t.Fatalf("modulesForFailureRetry() = %#v, want %#v", got, want) } } @@ -162,6 +1463,11 @@ func TestInferAssemblyArchitecture(t *testing.T) { "foo_amd64.s": "amd64", "foo_arm.s": "arm", "foo_arm64.s": "arm64", + "foo_loong64.s": "loong64", + "foo_mips64x.s": "unknown", + "foo_ppc64le.s": "ppc64le", + "foo_riscv64.s": "riscv64", + "foo_s390x.s": "s390x", "foo_wasm.s": "wasm", "asm_darwin_x86_gc.s": "unknown", } @@ -172,6 +1478,24 @@ func TestInferAssemblyArchitecture(t *testing.T) { } } +func TestSortDiscoveryReportRebuildsArchitectureHintsFromAllAssemblyPaths(t *testing.T) { + report := discoveryReport{Matched: []candidate{{ + Module: "example.com/future", + Version: "v1.0.0", + Architectures: []string{"amd64"}, + AsmFiles: []string{ + "asm_amd64.s", + "asm_riscv64.s", + "portable.s", + }, + }}} + sortDiscoveryReport(&report) + want := []string{"amd64", "riscv64", "unknown"} + if got := report.Matched[0].Architectures; !reflect.DeepEqual(got, want) { + t.Fatalf("architecture hints = %#v, want %#v", got, want) + } +} + func TestHTTPReaderAtFetchesCentralDirectoryOutsideCachedTail(t *testing.T) { archive := testModuleZip(t) server := newRangeServer(t, archive, nil) @@ -193,6 +1517,153 @@ func TestHTTPReaderAtFetchesCentralDirectoryOutsideCachedTail(t *testing.T) { } } +func TestHTTPReaderAtDoesNotPrefetchLargeModuleTail(t *testing.T) { + var archive bytes.Buffer + zw := zip.NewWriter(&archive) + large, err := zw.CreateHeader(&zip.FileHeader{ + Name: "example.com/lib@v1.0.0/pkg/blob.bin", + Method: zip.Store, + }) + if err != nil { + t.Fatal(err) + } + if _, err := io.CopyN(large, bytes.NewReader(make([]byte, 9<<20)), 9<<20); err != nil { + t.Fatal(err) + } + for _, name := range []string{ + "example.com/lib@v1.0.0/pkg/pkg.go", + "example.com/lib@v1.0.0/pkg/asm_amd64.s", + } { + w, err := zw.Create(name) + if err != nil { + t.Fatal(err) + } + if _, err := w.Write([]byte("TEXT ·f(SB),0,$0-0\n")); err != nil { + t.Fatal(err) + } + } + if err := zw.Close(); err != nil { + t.Fatal(err) + } + + var fetched atomic.Int64 + var malformedRange atomic.Bool + server := newRangeServer(t, archive.Bytes(), func(_ http.ResponseWriter, r *http.Request) bool { + if r.Method != http.MethodGet { + return false + } + if r.Header.Get("Range") == "" { + fetched.Add(int64(archive.Len())) + return false + } + var start, end int64 + if fields, err := fmt.Sscanf(strings.TrimPrefix(r.Header.Get("Range"), "bytes="), "%d-%d", &start, &end); err != nil || fields != 2 { + malformedRange.Store(true) + return false + } + fetched.Add(end - start + 1) + return false + }) + defer server.Close() + + reader, size, err := newHTTPReaderAt(context.Background(), server.Client(), server.URL, int64(archive.Len())) + if err != nil { + t.Fatal(err) + } + files, _, err := inspectModuleZipReader(reader, size) + if err != nil { + t.Fatal(err) + } + if want := []string{"pkg/asm_amd64.s"}; !reflect.DeepEqual(files, want) { + t.Fatalf("assembly files = %#v, want %#v", files, want) + } + if malformedRange.Load() { + t.Fatal("HTTP reader sent a malformed Range header") + } + if got, limit := fetched.Load(), int64(96<<10); got > limit { + t.Fatalf("fetched %d bytes, want at most %d", got, limit) + } +} + +func TestHTTPReaderAtNoAssemblyFetchesOnlyEOCDAndDirectory(t *testing.T) { + var archive bytes.Buffer + zw := zip.NewWriter(&archive) + large, err := zw.CreateHeader(&zip.FileHeader{ + Name: "example.com/lib@v1.0.0/pkg/blob.bin", + Method: zip.Store, + }) + if err != nil { + t.Fatal(err) + } + if _, err := io.CopyN(large, bytes.NewReader(make([]byte, 9<<20)), 9<<20); err != nil { + t.Fatal(err) + } + goFile, err := zw.Create("example.com/lib@v1.0.0/pkg/pkg.go") + if err != nil { + t.Fatal(err) + } + if _, err := io.WriteString(goFile, "package pkg\n"); err != nil { + t.Fatal(err) + } + if err := zw.Close(); err != nil { + t.Fatal(err) + } + + var fetched atomic.Int64 + server := newRangeServer(t, archive.Bytes(), func(_ http.ResponseWriter, r *http.Request) bool { + if r.Method == http.MethodGet { + var start, end int64 + if fields, err := fmt.Sscanf(strings.TrimPrefix(r.Header.Get("Range"), "bytes="), "%d-%d", &start, &end); err == nil && fields == 2 { + fetched.Add(end - start + 1) + } + } + return false + }) + defer server.Close() + + reader, size, err := newHTTPReaderAt(context.Background(), server.Client(), server.URL, int64(archive.Len())) + if err != nil { + t.Fatal(err) + } + files, _, err := inspectModuleZipReader(reader, size) + if err != nil { + t.Fatal(err) + } + if len(files) != 0 { + t.Fatalf("no-assembly ZIP matched files %#v", files) + } + if got, limit := fetched.Load(), int64(4<<10); got > limit { + t.Fatalf("no-assembly ZIP fetched %d bytes, want at most %d", got, limit) + } +} + +func TestHTTPReaderAtFallsBackForZIPComment(t *testing.T) { + var archive bytes.Buffer + zw := zip.NewWriter(&archive) + large, err := zw.CreateHeader(&zip.FileHeader{Name: "example.com/lib@v1.0.0/blob.bin", Method: zip.Store}) + if err != nil { + t.Fatal(err) + } + if _, err := io.CopyN(large, bytes.NewReader(make([]byte, 128<<10)), 128<<10); err != nil { + t.Fatal(err) + } + if err := zw.SetComment(strings.Repeat("comment", 100)); err != nil { + t.Fatal(err) + } + if err := zw.Close(); err != nil { + t.Fatal(err) + } + server := newRangeServer(t, archive.Bytes(), nil) + defer server.Close() + reader, size, err := newHTTPReaderAt(context.Background(), server.Client(), server.URL, int64(archive.Len())) + if err != nil { + t.Fatal(err) + } + if _, _, err := inspectModuleZipReader(reader, size); err != nil { + t.Fatal(err) + } +} + func TestHTTPReaderAtRetriesTransientResponses(t *testing.T) { archive := testModuleZip(t) var heads atomic.Int32 @@ -257,6 +1728,60 @@ func TestHTTPReaderAtReusesReadAheadForAssemblyEntries(t *testing.T) { } } +func TestDiscoveryTrafficAttributesPayloadBytesPerModule(t *testing.T) { + archive := testModuleZip(t) + latestBody := []byte(`{"Version":"v1.0.0"}`) + var identityOnly atomic.Bool + identityOnly.Store(true) + server := httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + if r.Header.Get("Accept-Encoding") != "identity" { + identityOnly.Store(false) + } + if strings.HasSuffix(r.URL.Path, "/@latest") { + w.Header().Set("Content-Length", strconv.Itoa(len(latestBody))) + _, _ = w.Write(latestBody) + return + } + serveRangeData(t, w, r, archive) + })) + defer server.Close() + + collector := newTrafficCollector() + ctx := context.WithValue(context.Background(), trafficCollectorContextKey{}, collector) + matched, failures, scanned, skipped := inspectModules( + ctx, server.Client(), server.URL, + []moduleVersion{{Path: "example.com/lib", Version: "v1.0.0"}}, + nil, nil, 1, int64(len(archive))+1, + ) + if len(matched) != 1 || len(failures) != 0 || len(scanned) != 1 || skipped != 0 { + t.Fatalf("inspection result = matched %d failures %d scanned %d skipped %d", len(matched), len(failures), len(scanned), skipped) + } + if !identityOnly.Load() { + t.Fatal("discovery request allowed transparent content encoding, making payload accounting ambiguous") + } + report := collector.snapshot(time.Unix(0, 0).UTC(), scanModeHistory, discoveryReport{IndexEntries: 1}) + if len(report.Modules) != 1 { + t.Fatalf("traffic modules = %#v, want one", report.Modules) + } + got := report.Modules[0] + if got.Module != "example.com/lib" || got.IndexedVersion != "v1.0.0" || got.ResolvedVersion != "v1.0.0" || got.Outcome != "matched" { + t.Fatalf("module traffic identity = %#v", got) + } + if got.Latest.Requests != 1 || got.Latest.BodyBytes != int64(len(latestBody)) { + t.Fatalf("latest traffic = %#v", got) + } + if got.ZIPHead.Requests != 1 || got.ZIPHead.BodyBytes != 0 || got.AdvertisedZIPBytes != int64(len(archive)) { + t.Fatalf("ZIP HEAD traffic = %#v", got) + } + if got.ZIPFull.Requests != 1 || got.ZIPFull.BodyBytes != int64(len(archive)) || got.ZIPRange.Requests != 0 { + t.Fatalf("ZIP body traffic = %#v", got) + } + wantBytes := int64(len(latestBody) + len(archive)) + if got.TotalRequests != 3 || got.TotalBodyBytes != wantBytes || report.TotalBodyBytes != wantBytes { + t.Fatalf("traffic totals = module %#v report %#v, want 3 requests and %d bytes", got, report, wantBytes) + } +} + func TestReadIndexDoesNotSkipSharedBoundaryTimestamp(t *testing.T) { base := time.Date(2025, time.January, 1, 0, 0, 0, 0, time.UTC) entries := make([]indexEntry, 2001) @@ -308,6 +1833,194 @@ func TestReadIndexDoesNotSkipSharedBoundaryTimestamp(t *testing.T) { } } +func TestReadIndexBackwardsSelectsNewestCompleteTimestampGroup(t *testing.T) { + base := time.Date(2026, time.September, 15, 0, 0, 0, 0, time.UTC) + entries := []indexEntry{ + {Path: "example.com/old", Version: "v1.0.0", Timestamp: base.Add(-4 * time.Minute)}, + {Path: "example.com/a", Version: "v1.0.0", Timestamp: base.Add(-3 * time.Minute)}, + {Path: "example.com/b", Version: "v1.0.0", Timestamp: base.Add(-2 * time.Minute)}, + {Path: "example.com/c", Version: "v1.0.0", Timestamp: base.Add(-2 * time.Minute)}, + {Path: "example.com/d", Version: "v1.0.0", Timestamp: base.Add(-2 * time.Minute)}, + {Path: "example.com/new", Version: "v1.0.0", Timestamp: base.Add(-time.Minute)}, + {Path: "example.com/after", Version: "v1.0.0", Timestamp: base}, + } + server := newIndexServer(t, entries) + defer server.Close() + + got, nextBefore, err := readIndexBackwards( + context.Background(), server.Client(), server.URL, + base.Format(time.RFC3339Nano), 3, + ) + if err != nil { + t.Fatal(err) + } + want := entries[2:6] + if !reflect.DeepEqual(got, want) { + t.Fatalf("readIndexBackwards() = %#v, want newest complete timestamp group %#v", got, want) + } + if wantCursor := base.Add(-2 * time.Minute).Format(time.RFC3339Nano); nextBefore != wantCursor { + t.Fatalf("next before = %q, want %q", nextBefore, wantCursor) + } +} + +func TestReadIndexBackwardsFromStopsAtIncrementalLowerBound(t *testing.T) { + base := time.Date(2026, time.September, 15, 0, 0, 0, 0, time.UTC) + entries := []indexEntry{ + {Path: "example.com/before", Version: "v1.0.0", Timestamp: base.Add(-time.Nanosecond)}, + {Path: "example.com/at-lower", Version: "v1.0.0", Timestamp: base}, + {Path: "example.com/inside", Version: "v1.0.0", Timestamp: base.Add(time.Minute)}, + {Path: "example.com/at-upper", Version: "v1.0.0", Timestamp: base.Add(2 * time.Minute)}, + } + server := newIndexServer(t, entries) + defer server.Close() + + got, nextBefore, err := readIndexBackwardsFrom( + context.Background(), server.Client(), server.URL, + base.Add(2*time.Minute).Format(time.RFC3339Nano), + base.Format(time.RFC3339Nano), 0, + ) + if err != nil { + t.Fatal(err) + } + want := entries[1:3] + if !reflect.DeepEqual(got, want) { + t.Fatalf("readIndexBackwardsFrom() = %#v, want bounded interval %#v", got, want) + } + if wantCursor := base.Format(time.RFC3339Nano); nextBefore != wantCursor { + t.Fatalf("next before = %q, want lower bound %q", nextBefore, wantCursor) + } +} + +func TestReadIndexBackwardsConsecutiveWindowsHaveExactContiguousCoverage(t *testing.T) { + lower := time.Date(2026, time.September, 14, 0, 0, 0, 0, time.UTC) + const timestampGroups = 1001 + const entriesPerGroup = 5 + entries := make([]indexEntry, 0, timestampGroups*entriesPerGroup) + for group := 0; group < timestampGroups; group++ { + timestamp := lower.Add(time.Duration(group) * time.Millisecond) + for item := 0; item < entriesPerGroup; item++ { + entries = append(entries, indexEntry{ + Path: fmt.Sprintf("example.com/mod-%04d-%d", group, item), + Version: "v1.0.0", + Timestamp: timestamp, + }) + } + } + server := newIndexServer(t, entries) + defer server.Close() + + before := lower.Add(timestampGroups * time.Millisecond).Format(time.RFC3339Nano) + after := lower.Format(time.RFC3339Nano) + var got []indexEntry + var ranges []indexRange + for before != after { + batch, nextBefore, err := readIndexBackwardsFrom( + context.Background(), server.Client(), server.URL, before, after, 2100, + ) + if err != nil { + t.Fatal(err) + } + nextTime, nextErr := time.Parse(time.RFC3339Nano, nextBefore) + beforeTime, beforeErr := time.Parse(time.RFC3339Nano, before) + if nextErr != nil || beforeErr != nil || !nextTime.Before(beforeTime) { + t.Fatalf("reverse cursor did not advance: %q -> %q", before, nextBefore) + } + got = append(got, batch...) + ranges = append(ranges, indexRange{Since: nextBefore, Before: before, IndexEntries: len(batch)}) + before = nextBefore + } + if err := validateIndexCoverage(reverseIndexRanges(ranges)); err != nil { + t.Fatalf("consecutive reverse windows are not contiguous: %v", err) + } + sort.Slice(got, func(i, j int) bool { + if !got[i].Timestamp.Equal(got[j].Timestamp) { + return got[i].Timestamp.Before(got[j].Timestamp) + } + return got[i].Path < got[j].Path + }) + if !reflect.DeepEqual(got, entries) { + t.Fatalf("consecutive reverse windows returned %d entries, want all %d exactly once", len(got), len(entries)) + } +} + +func TestFetchIndexPageRejectsUnorderedFeed(t *testing.T) { + base := time.Date(2026, time.September, 14, 0, 0, 0, 0, time.UTC) + server := newIndexServer(t, []indexEntry{ + {Path: "example.com/new", Version: "v1.0.0", Timestamp: base.Add(time.Second)}, + {Path: "example.com/old", Version: "v1.0.0", Timestamp: base}, + }) + defer server.Close() + _, err := fetchIndexPage(context.Background(), server.Client(), server.URL, base.Add(-time.Second).Format(time.RFC3339Nano), indexPageLimit) + if err == nil || !strings.Contains(err.Error(), "not ordered") { + t.Fatalf("fetchIndexPage() error = %v, want unordered-feed rejection", err) + } +} + +func TestValidateFetchedIndexWindowRequiresCursorAtFirstCompleteGroup(t *testing.T) { + entries := []indexEntry{ + {Path: "example.com/a", Version: "v1.0.0", Timestamp: time.Date(2026, 9, 14, 0, 0, 1, 0, time.UTC)}, + {Path: "example.com/b", Version: "v1.0.0", Timestamp: time.Date(2026, 9, 14, 0, 0, 1, 0, time.UTC)}, + {Path: "example.com/c", Version: "v1.0.0", Timestamp: time.Date(2026, 9, 14, 0, 0, 2, 0, time.UTC)}, + } + if err := validateFetchedIndexWindow(entries, "2026-09-14T00:00:01Z", "2026-09-14T00:00:03Z", "2026-09-14T00:00:00Z"); err != nil { + t.Fatal(err) + } + if err := validateFetchedIndexWindow(entries, "2026-09-14T00:00:01.5Z", "2026-09-14T00:00:03Z", "2026-09-14T00:00:00Z"); err == nil { + t.Fatal("validateFetchedIndexWindow() accepted a cursor that could skip the first timestamp group") + } +} + +func TestMergeIndexRangesOrdersRFC3339ByTimeNotText(t *testing.T) { + got, err := mergeIndexRanges([]indexRange{ + {Since: "2026-09-14T00:00:00.5Z", Before: "2026-09-14T00:00:01Z", IndexEntries: 1}, + {Since: "2026-09-14T00:00:00Z", Before: "2026-09-14T00:00:00.5Z", IndexEntries: 1}, + }) + if err != nil { + t.Fatal(err) + } + if got[0].Since != "2026-09-14T00:00:00Z" || got[1].Since != "2026-09-14T00:00:00.5Z" { + t.Fatalf("mergeIndexRanges() ordered RFC3339 timestamps lexically: %#v", got) + } +} + +func reverseIndexRanges(items []indexRange) []indexRange { + out := append([]indexRange(nil), items...) + for left, right := 0, len(out)-1; left < right; left, right = left+1, right-1 { + out[left], out[right] = out[right], out[left] + } + return out +} + +func newIndexServer(t *testing.T, entries []indexEntry) *httptest.Server { + t.Helper() + return httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + limit, err := strconv.Atoi(r.URL.Query().Get("limit")) + if err != nil { + t.Fatal(err) + } + var since time.Time + if raw := r.URL.Query().Get("since"); raw != "" { + since, err = time.Parse(time.RFC3339Nano, raw) + if err != nil { + t.Fatal(err) + } + } + encoder := json.NewEncoder(w) + for _, entry := range entries { + if entry.Timestamp.Before(since) { + continue + } + if limit == 0 { + break + } + if err := encoder.Encode(entry); err != nil { + t.Fatal(err) + } + limit-- + } + })) +} + func testModuleZip(t *testing.T) []byte { t.Helper() var archive bytes.Buffer diff --git a/cmd/plan9asmll/.gitignore b/cmd/plan9asmll/.gitignore index c4fff022..8c8b20a5 100644 --- a/cmd/plan9asmll/.gitignore +++ b/cmd/plan9asmll/.gitignore @@ -1 +1,2 @@ _out/ +plan9asmll diff --git a/cmd/plan9asmll/go.mod b/cmd/plan9asmll/go.mod index 4b47a0b5..6ea389c5 100644 --- a/cmd/plan9asmll/go.mod +++ b/cmd/plan9asmll/go.mod @@ -9,6 +9,7 @@ require ( ) require ( + golang.org/x/arch v0.14.0 // indirect golang.org/x/mod v0.33.0 // indirect golang.org/x/sync v0.19.0 // indirect ) diff --git a/cmd/plan9asmll/go.sum b/cmd/plan9asmll/go.sum index 59f00a20..3d4f7ea0 100644 --- a/cmd/plan9asmll/go.sum +++ b/cmd/plan9asmll/go.sum @@ -2,6 +2,8 @@ github.com/google/go-cmp v0.6.0 h1:ofyhxvXcZhMsU5ulbFiLKl/XBFqE1GSq7atu8tAmTRI= github.com/google/go-cmp v0.6.0/go.mod h1:17dUlkBOakJ0+DkrSSNjCkIjxS6bF9zb3elmeNGIjoY= github.com/xgo-dev/llvm v0.9.9 h1:u4RZvy0vxu8nNt4oTrhttyMSyscYtmiy9geP+Kl/RYg= github.com/xgo-dev/llvm v0.9.9/go.mod h1:42vav2/cI5BAIcL543DZSMO9do8/aCK2z7JERH+AE+M= +golang.org/x/arch v0.14.0 h1:z9JUEZWr8x4rR0OU6c4/4t6E6jOZ8/QBS2bBYBm4tx4= +golang.org/x/arch v0.14.0/go.mod h1:FEVrYAQjsQXMVJ1nsMoVVXPZg6p2JE2mx8psSWTDQys= golang.org/x/mod v0.33.0 h1:tHFzIWbBifEmbwtGz65eaWyGiGZatSrT9prnU8DbVL8= golang.org/x/mod v0.33.0/go.mod h1:swjeQEj+6r7fODbD2cqrnje9PnziFuw4bmLbBZFrQ5w= golang.org/x/sync v0.19.0 h1:vV+1eWNmZ5geRlYjzm2adRgW2/mcpevXNg50YZtPCE4= diff --git a/cmd/plan9asmll/main.go b/cmd/plan9asmll/main.go index 767c1093..3ca286cd 100644 --- a/cmd/plan9asmll/main.go +++ b/cmd/plan9asmll/main.go @@ -2,13 +2,17 @@ package main import ( "encoding/json" + "errors" "flag" "fmt" "go/ast" + "go/parser" + "go/token" "go/types" "os" "os/exec" "path/filepath" + "reflect" "regexp" "runtime" "sort" @@ -18,6 +22,7 @@ import ( "github.com/xgo-dev/llvm" "github.com/xgo-dev/plan9asm" + "github.com/xgo-dev/plan9asm/internal/asmsig" "golang.org/x/tools/go/packages" ) @@ -35,6 +40,29 @@ type failItem struct { UnsupportedHits []unsupportedHit `json:"unsupported_hits,omitempty"` } +const targetNotApplicableGoTextArgSize = "go_text_arg_size_mismatch" + +type notApplicableItem struct { + PkgPath string `json:"pkg_path"` + AsmFile string `json:"asm_file"` + Kind string `json:"kind"` + Symbol string `json:"symbol"` + DeclaredArgSize int64 `json:"declared_arg_size"` + ExpectedArgSize int64 `json:"expected_arg_size"` + Reason string `json:"reason"` +} + +type asmABINotApplicableError struct { + Symbol string + Goarch string + DeclaredArgSize int64 + ExpectedArgSize int64 +} + +func (e *asmABINotApplicableError) Error() string { + return fmt.Sprintf("%s: TEXT argument size is incompatible with the Go declaration on %s: got %d, want %d", e.Symbol, e.Goarch, e.DeclaredArgSize, e.ExpectedArgSize) +} + type opCount struct { Op string `json:"op"` Count int `json:"count"` @@ -47,17 +75,20 @@ type unsupportedHit struct { } type runReport struct { - Goos string `json:"goos"` - Goarch string `json:"goarch"` - Patterns []string `json:"patterns"` - TotalPkgs int `json:"total_pkgs"` - AsmPackages []string `json:"asm_packages,omitempty"` - TotalAsm int `json:"total_asm"` - Success int `json:"success"` - Failed int `json:"failed"` - Duration string `json:"duration"` - UnsupportedOps []opCount `json:"unsupported_ops,omitempty"` - Fails []failItem `json:"fails,omitempty"` + Goos string `json:"goos"` + Goarch string `json:"goarch"` + Patterns []string `json:"patterns"` + TotalPkgs int `json:"total_pkgs"` + AsmPackages []string `json:"asm_packages,omitempty"` + AsmFiles []string `json:"asm_files,omitempty"` + TotalAsm int `json:"total_asm"` + Success int `json:"success"` + NotApplicable int `json:"not_applicable"` + Failed int `json:"failed"` + Duration string `json:"duration"` + UnsupportedOps []opCount `json:"unsupported_ops,omitempty"` + Fails []failItem `json:"fails,omitempty"` + NotApplicableItems []notApplicableItem `json:"not_applicable_items,omitempty"` } type targetSpec struct { @@ -71,11 +102,12 @@ type targetTasks struct { } type matrixReport struct { - Targets []runReport `json:"targets"` - TotalTargets int `json:"total_targets"` - TotalAsm int `json:"total_asm"` - Success int `json:"success"` - Failed int `json:"failed"` + Targets []runReport `json:"targets"` + TotalTargets int `json:"total_targets"` + TotalAsm int `json:"total_asm"` + Success int `json:"success"` + NotApplicable int `json:"not_applicable"` + Failed int `json:"failed"` } type compileConfig struct { @@ -91,6 +123,8 @@ func main() { targets = flag.String("targets", "", "comma-separated GOOS/GOARCH list (e.g. linux/amd64,windows/arm64)") allTargets = flag.Bool("all-targets", false, "run the complete default Plan 9 target matrix") patterns = flag.String("patterns", "std", "comma-separated package patterns") + asmFiles = flag.String("asm-files", "", "comma-separated module-relative assembly files to exercise exactly") + buildTags = flag.String("tags", "", "comma-separated Go build tags used to expose tagged assembly implementations") modulePath = flag.String("module-path", "", "only include packages owned by this module path") outDir = flag.String("out", "", "output dir for generated .ll files") annotate = flag.Bool("annotate", false, "emit source asm lines as IR comments") @@ -110,6 +144,11 @@ func main() { if len(pats) == 0 { fatalf("empty -patterns") } + tags := splitCSV(*buildTags) + exactAsmFiles := splitCSV(*asmFiles) + if err := validateExactAsmFiles(exactAsmFiles); err != nil { + fatalf("%v", err) + } specs, err := resolveTargets(*goos, *goarch, *targets, *allTargets) if err != nil { @@ -139,7 +178,7 @@ func main() { runOutDir = filepath.Join(baseOut, targetID(spec)) fmt.Fprintf(os.Stderr, "\n== target %s ==\n", targetID(spec)) } - rep, tasks, err := runOneTarget(spec, pats, *modulePath, runOutDir, *annotate, *limit, *keepGoing, *listOnly, *strictLoad, *repoRoot, ccfg) + rep, tasks, err := runOneTarget(spec, pats, tags, exactAsmFiles, *modulePath, runOutDir, *annotate, *limit, *keepGoing, *listOnly, *strictLoad, *repoRoot, ccfg) if err != nil { fatalf("%s: %v", targetID(spec), err) } @@ -155,7 +194,7 @@ func main() { if *listOnly { var out any - if len(taskLists) == 1 { + if !useMatrixReport(*allTargets, *targets, len(taskLists)) { out = taskLists[0].Tasks } else { out = taskLists @@ -166,7 +205,7 @@ func main() { return } - if len(allReports) == 1 { + if !useMatrixReport(*allTargets, *targets, len(allReports)) { writeReport(*reportOut, allReports[0]) if exitCode != 0 { os.Exit(exitCode) @@ -181,14 +220,19 @@ func main() { for _, r := range allReports { mr.TotalAsm += r.TotalAsm mr.Success += r.Success + mr.NotApplicable += r.NotApplicable mr.Failed += r.Failed } writeReport(*reportOut, mr) if exitCode != 0 { - fmt.Fprintf(os.Stderr, "\nmatrix finished with failures: success=%d failed=%d total=%d\n", mr.Success, mr.Failed, mr.TotalAsm) + fmt.Fprintf(os.Stderr, "\nmatrix finished with failures: success=%d not_applicable=%d failed=%d total=%d\n", mr.Success, mr.NotApplicable, mr.Failed, mr.TotalAsm) os.Exit(exitCode) } - fmt.Fprintf(os.Stderr, "\nmatrix finished: success=%d total=%d\n", mr.Success, mr.TotalAsm) + fmt.Fprintf(os.Stderr, "\nmatrix finished: success=%d not_applicable=%d total=%d\n", mr.Success, mr.NotApplicable, mr.TotalAsm) +} + +func useMatrixReport(allTargets bool, targets string, reportCount int) bool { + return allTargets || strings.TrimSpace(targets) != "" || reportCount != 1 } func resolveCompileConfig(compile bool, llcPath string, keepObj bool) (compileConfig, error) { @@ -304,22 +348,25 @@ func targetID(t targetSpec) string { return t.Goos + "-" + t.Goarch } -func runOneTarget(spec targetSpec, pats []string, modulePath, outDir string, annotate bool, limit int, keepGoing bool, listOnly, strictLoad bool, repoRoot string, ccfg compileConfig) (runReport, []asmTask, error) { +func runOneTarget(spec targetSpec, pats, buildTags, exactAsmFiles []string, modulePath, outDir string, annotate bool, limit int, keepGoing bool, listOnly, strictLoad bool, repoRoot string, ccfg compileConfig) (runReport, []asmTask, error) { arch, err := toPlan9Arch(spec.Goarch) if err != nil { return runReport{}, nil, err } - pkgs, err := loadPkgs(spec.Goos, spec.Goarch, pats, modulePath, strictLoad) + pkgs, err := loadPkgs(spec.Goos, spec.Goarch, pats, buildTags, modulePath, strictLoad, containsTestAssembly(exactAsmFiles)) if err != nil { return runReport{}, nil, fmt.Errorf("load packages: %w", err) } pkgByPath := map[string]*packages.Package{} for _, p := range pkgs { if p != nil && p.PkgPath != "" { - pkgByPath[p.PkgPath] = p + previous := pkgByPath[p.PkgPath] + if previous == nil || isTestVariantPackage(p) && !isTestVariantPackage(previous) { + pkgByPath[p.PkgPath] = p + } } } - tasks, asmPackages := collectAsmTasks(pkgs, outDir) + tasks, asmPackages := collectAsmTasks(pkgs, outDir, exactAsmFiles) if limit > 0 && limit < len(tasks) { tasks = tasks[:limit] } @@ -334,6 +381,9 @@ func runOneTarget(spec targetSpec, pats []string, modulePath, outDir string, ann AsmPackages: asmPackages, TotalAsm: len(tasks), } + for _, task := range tasks { + rep.AsmFiles = append(rep.AsmFiles, task.AsmFile) + } if len(tasks) == 0 { fmt.Fprintf(os.Stderr, "no asm files found for patterns=%v (%s/%s)\n", pats, spec.Goos, spec.Goarch) return rep, nil, nil @@ -361,11 +411,27 @@ func runOneTarget(spec targetSpec, pats []string, modulePath, outDir string, ann } continue } - err := compileOne(pkg, arch, spec.Goarch, triple, t, annotate, ccfg) + err := compileOne(pkg, arch, spec.Goos, spec.Goarch, triple, t, annotate, ccfg) if err != nil { + var abiMismatch *asmABINotApplicableError + if errors.As(err, &abiMismatch) { + fmt.Fprintf(os.Stderr, "[%d/%d] N/A %s\n", idx, len(tasks), t.AsmFile) + printFailureReason(abiMismatch.Error()) + rep.NotApplicable++ + rep.NotApplicableItems = append(rep.NotApplicableItems, notApplicableItem{ + PkgPath: t.PkgPath, + AsmFile: t.AsmFile, + Kind: targetNotApplicableGoTextArgSize, + Symbol: abiMismatch.Symbol, + DeclaredArgSize: abiMismatch.DeclaredArgSize, + ExpectedArgSize: abiMismatch.ExpectedArgSize, + Reason: abiMismatch.Error(), + }) + continue + } fmt.Fprintf(os.Stderr, "[%d/%d] FAIL %s\n", idx, len(tasks), t.AsmFile) printFailureReason(err.Error()) - unsupported, hits := unsupportedInAsmFile(t.AsmFile, arch, supportedOps) + unsupported, hits := unsupportedInAsmFile(t.AsmFile, asmSourceRoot(pkg, t.AsmFile), arch, supportedOps) if len(unsupported) > 0 { fmt.Fprintf(os.Stderr, " unsupported: %s\n", strings.Join(unsupported, ", ")) for _, op := range unsupported { @@ -395,19 +461,30 @@ func runOneTarget(spec targetSpec, pats []string, modulePath, outDir string, ann rep.Duration = time.Since(start).String() rep.UnsupportedOps = flattenUnsupportedAgg(unsupportedAgg) if rep.Failed != 0 { - fmt.Fprintf(os.Stderr, "finished with failures: success=%d failed=%d total=%d\n", rep.Success, rep.Failed, rep.TotalAsm) + fmt.Fprintf(os.Stderr, "finished with failures: success=%d not_applicable=%d failed=%d total=%d\n", rep.Success, rep.NotApplicable, rep.Failed, rep.TotalAsm) } else { - fmt.Fprintf(os.Stderr, "finished: success=%d total=%d\n", rep.Success, rep.TotalAsm) + fmt.Fprintf(os.Stderr, "finished: success=%d not_applicable=%d total=%d\n", rep.Success, rep.NotApplicable, rep.TotalAsm) } return rep, nil, nil } -func compileOne(pkg *packages.Package, arch plan9asm.Arch, goarch, triple string, t asmTask, annotate bool, ccfg compileConfig) error { - src, err := os.ReadFile(t.AsmFile) +func compileOne(pkg *packages.Package, arch plan9asm.Arch, goos, goarch, triple string, t asmTask, annotate bool, ccfg compileConfig) error { + src, err := readAsmSource(t.AsmFile, asmSourceRoot(pkg, t.AsmFile)) if err != nil { return fmt.Errorf("read asm: %w", err) } - file, err := plan9asm.Parse(arch, string(src)) + imports := make(map[string]*types.Package, len(pkg.Imports)) + for path, imported := range pkg.Imports { + if imported != nil && imported.Types != nil { + imports[path] = imported.Types + } + } + src = plan9asm.ExpandGoAssemblySource(plan9asm.GoPackage{ + Path: pkg.PkgPath, + Types: pkg.Types, + Imports: imports, + }, src, goarch) + file, err := plan9asm.ParseWithDefines(arch, string(src), plan9asm.GoAssemblerDefines(goos, goarch)) if err != nil { if strings.Contains(err.Error(), "no TEXT directive found") { return nil @@ -419,15 +496,19 @@ func compileOne(pkg *packages.Package, arch plan9asm.Arch, goarch, triple string } resolve := resolveSymFunc(pkg.PkgPath) - sigs, err := sigsForAsmFile(pkg, file, resolve, goarch) + sigs, declaredArgSizes, err := sigsForAsmFile(pkg, file, resolve, goarch) if err != nil { return fmt.Errorf("infer signatures: %w", err) } + if err := validateDeclaredTextArgSizes(file, resolve, declaredArgSizes, goarch); err != nil { + return fmt.Errorf("target applicability: %w", err) + } mod, err := plan9asm.TranslateModule(file, plan9asm.Options{ TargetTriple: triple, ResolveSym: resolve, Sigs: sigs, Goarch: goarch, + WASMABI: wasmABIForGoPackageTarget(goarch), AnnotateSource: annotate, }) if err != nil { @@ -464,6 +545,33 @@ func compileOne(pkg *packages.Package, arch plan9asm.Arch, goarch, triple string return nil } +// plan9asmll translates Go package assembly, rather than arbitrary native LLVM +// entry points. Go's wasm assembler therefore always uses the resumable +// linear-memory stack ABI; other architectures retain the direct convention. +func wasmABIForGoPackageTarget(goarch string) plan9asm.WASMABI { + if goarch == "wasm" { + return plan9asm.WASMABIGo + } + return plan9asm.WASMABIDirect +} + +func asmSourceRoot(pkg *packages.Package, asmFile string) string { + if pkg != nil && pkg.Module != nil && pkg.Module.Dir != "" { + return pkg.Module.Dir + } + return filepath.Dir(asmFile) +} + +// readAsmSource expands quoted headers that live inside the package's module. +// Go assembly commonly keeps large function-like macros in sibling .h files. +// Toolchain headers such as textflag.h and funcdata.h are resolved from the +// current GOROOT's pkg/include directory, matching the include path supplied +// by the Go command. Generated package headers such as go_asm.h remain as +// directives when they do not exist yet. +func readAsmSource(asmFile, sourceRoot string) ([]byte, error) { + return plan9asm.ReadGoAssemblySource(asmFile, sourceRoot) +} + func llcExtraArgs(goarch string) []string { switch goarch { case "amd64": @@ -480,7 +588,7 @@ func llcExtraArgs(goarch string) []string { } } -func loadPkgs(goos, goarch string, patterns []string, modulePath string, strict bool) ([]*packages.Package, error) { +func loadPkgs(goos, goarch string, patterns, buildTags []string, modulePath string, strict, includeTests bool) ([]*packages.Package, error) { cfg := &packages.Config{ Mode: packages.NeedName | packages.NeedFiles | @@ -495,6 +603,10 @@ func loadPkgs(goos, goarch string, patterns []string, modulePath string, strict "GOOS="+goos, "GOARCH="+goarch, ), + Tests: includeTests, + } + if len(buildTags) != 0 { + cfg.BuildFlags = []string{"-tags=" + strings.Join(buildTags, ",")} } pkgs, err := packages.Load(cfg, patterns...) if err != nil { @@ -507,6 +619,20 @@ func loadPkgs(goos, goarch string, patterns []string, modulePath string, strict return pkgs, nil } +func containsTestAssembly(files []string) bool { + for _, name := range files { + base := filepath.Base(filepath.FromSlash(name)) + if strings.Contains(strings.TrimSuffix(base, filepath.Ext(base)), "_test_") || strings.HasSuffix(strings.TrimSuffix(base, filepath.Ext(base)), "_test") { + return true + } + } + return false +} + +func isTestVariantPackage(pkg *packages.Package) bool { + return pkg != nil && strings.Contains(pkg.ID, " [") && strings.HasSuffix(pkg.ID, ".test]") +} + func filterPackagesByModule(pkgs []*packages.Package, modulePath string) []*packages.Package { if modulePath == "" { return pkgs @@ -520,10 +646,14 @@ func filterPackagesByModule(pkgs []*packages.Package, modulePath string) []*pack return filtered } -func collectAsmTasks(pkgs []*packages.Package, outDir string) ([]asmTask, []string) { +func collectAsmTasks(pkgs []*packages.Package, outDir string, exactAsmFiles []string) ([]asmTask, []string) { tasks := make([]asmTask, 0) asmPackages := make([]string, 0) seenPkg := map[string]bool{} + allow := make(map[string]bool, len(exactAsmFiles)) + for _, path := range exactAsmFiles { + allow[filepath.ToSlash(filepath.Clean(filepath.FromSlash(path)))] = true + } for _, p := range pkgs { if p == nil || p.PkgPath == "" { continue @@ -533,6 +663,15 @@ func collectAsmTasks(pkgs []*packages.Package, outDir string) ([]asmTask, []stri } seenPkg[p.PkgPath] = true files := asmFilesOfPkg(p) + if len(allow) != 0 { + filtered := files[:0] + for _, file := range files { + if rel, ok := moduleRelativeAsmPath(p, file); ok && allow[rel] { + filtered = append(filtered, file) + } + } + files = filtered + } if len(files) == 0 { continue } @@ -552,6 +691,27 @@ func collectAsmTasks(pkgs []*packages.Package, outDir string) ([]asmTask, []stri return tasks, asmPackages } +func validateExactAsmFiles(files []string) error { + for _, path := range files { + clean := filepath.Clean(filepath.FromSlash(path)) + if filepath.IsAbs(clean) || clean == "." || clean == ".." || strings.HasPrefix(clean, ".."+string(filepath.Separator)) { + return fmt.Errorf("invalid -asm-files entry %q: expect a module-relative path", path) + } + } + return nil +} + +func moduleRelativeAsmPath(pkg *packages.Package, path string) (string, bool) { + if pkg == nil || pkg.Module == nil || pkg.Module.Dir == "" { + return "", false + } + rel, err := filepath.Rel(pkg.Module.Dir, path) + if err != nil || rel == ".." || strings.HasPrefix(rel, ".."+string(filepath.Separator)) { + return "", false + } + return filepath.ToSlash(filepath.Clean(rel)), true +} + func asmFilesOfPkg(p *packages.Package) []string { if p == nil { return nil @@ -685,25 +845,24 @@ func resolveSymFunc(pkgPath string) func(sym string) string { } var abiSuffixRe = regexp.MustCompile(`]*>$`) -var ( - reCaseString = regexp.MustCompile(`case\s+"([A-Za-z0-9_.$]+)"`) - reCaseOp = regexp.MustCompile(`case\s+Op([A-Za-z0-9_]+)`) - reQuotedOp = regexp.MustCompile(`"([A-Za-z0-9_.$]+)"`) - reOpToken = regexp.MustCompile(`Op([A-Za-z0-9_]+)`) -) func stripABISuffix(sym string) string { return abiSuffixRe.ReplaceAllString(sym, "") } -func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(string) string, goarch string) (map[string]plan9asm.FuncSig, error) { +func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(string) string, goarch string) (map[string]plan9asm.FuncSig, map[string]int64, error) { sigs := map[string]plan9asm.FuncSig{} + declaredArgSizes := map[string]int64{} + declaredSigs := map[string]bool{} + knownABISigs := map[string]bool{} + fallbackAsmSigs := map[string]bool{} if pkg == nil || pkg.Types == nil || pkg.Types.Scope() == nil { for _, fn := range file.Funcs { - fs := fallbackSigForAsmFunc(fn, resolve(stripABISuffix(fn.Sym))) + fs := fallbackSigForAsmFunc(fn, resolve(stripABISuffix(fn.Sym)), goarch) sigs[fs.Name] = fs } - return sigs, nil + asmsig.RefineTailForwarders(file, sigs, resolve, nil) + return sigs, declaredArgSizes, nil } sz := pkg.TypesSizes @@ -711,7 +870,7 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str sz = types.SizesFor("gc", goarch) } if sz == nil { - return nil, fmt.Errorf("missing type sizes for %q", goarch) + return nil, nil, fmt.Errorf("missing type sizes for %q", goarch) } scope := pkg.Types.Scope() @@ -723,21 +882,52 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str if resolved == "" { continue } - fs, ok, err := tryDeclSig(scope, sym, resolved, linknames, goarch, sz) + fs, argSize, ok, err := tryDeclSig(scope, sym, resolved, linknames, goarch, sz) if err != nil { - return nil, err + return nil, nil, err } if !ok { - fs = fallbackSigForAsmFunc(fn, resolved) + fs = fallbackSigForAsmFunc(fn, resolved, goarch) + fallbackAsmSigs[resolved] = true + } else { + declaredArgSizes[resolved] = argSize + declaredSigs[resolved] = true + knownABISigs[resolved] = true } sigs[resolved] = fs } + // File-local WebAssembly helpers use the native wasm operand stack and + // virtual registers rather than Go's stack-frame ABI. They have no Go + // declaration, so derive their complete argument and result types from the + // instructions before resolving calls. Keeping this generic covers the + // standard library's bytealg helpers as they evolve without a name table. + if goarch == "wasm" { + for _, fn := range file.Funcs { + resolved := resolve(stripABISuffix(fn.Sym)) + fs, ok := plan9asm.LookupGoWASMNativeFuncSig(resolved) + if !ok { + if !strings.HasSuffix(stripABISuffix(fn.Sym), "<>") || !plan9asm.WASMAssemblyUsesNativeReturn(fn) { + continue + } + var err error + fs, err = plan9asm.InferWASMAssemblyFuncSig(fn, resolved) + if err != nil { + return nil, nil, err + } + } + fs.WASMNative = true + sigs[resolved] = fs + knownABISigs[resolved] = true + delete(fallbackAsmSigs, resolved) + } + } + addTargetSig := func(sym string, caller plan9asm.FuncSig, tail bool) { if sym == "" { return } - sym = stripABISuffix(strings.TrimSuffix(sym, "<>")) + sym = stripABISuffix(sym) resolved := resolve(sym) if resolved == "" { return @@ -745,9 +935,18 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str if _, ok := sigs[resolved]; ok { return } - fs, ok, err := tryDeclSig(scope, sym, resolved, linknames, goarch, sz) + if goarch == "wasm" { + if fs, ok := plan9asm.LookupGoWASMNativeFuncSig(resolved); ok { + sigs[resolved] = fs + knownABISigs[resolved] = true + return + } + } + fs, _, ok, err := tryDeclSig(scope, sym, resolved, linknames, goarch, sz) if err == nil && ok { sigs[resolved] = fs + declaredSigs[resolved] = true + knownABISigs[resolved] = true return } if tail && caller.Name != "" { @@ -759,12 +958,14 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str sigs[resolved] = plan9asm.FuncSig{Name: resolved, Ret: plan9asm.I64} } + declaredTailCallers := make(map[string][]plan9asm.FuncSig) for _, fn := range file.Funcs { - caller := sigs[resolve(stripABISuffix(fn.Sym))] + callerResolved := resolve(stripABISuffix(fn.Sym)) + caller := sigs[callerResolved] for _, ins := range fn.Instrs { op := strings.ToUpper(string(ins.Op)) - tail := op == "JMP" || op == "B" - if !(tail || op == "CALL" || op == "BL") { + tail := op == "JMP" || op == "B" || (op == "RET" && len(ins.Args) == 1) + if !(tail || op == "CALL" || op == "CALLNORESUME" || op == "WASMCALL" || op == "BL") { continue } if len(ins.Args) != 1 || ins.Args[0].Kind != plan9asm.OpSym { @@ -780,20 +981,155 @@ func sigsForAsmFile(pkg *packages.Package, file *plan9asm.File, resolve func(str continue } addTargetSig(base, caller, tail) + targetResolved := resolve(stripABISuffix(base)) + if tail && declaredSigs[callerResolved] && fallbackAsmSigs[targetResolved] { + candidate := caller + candidate.Name = targetResolved + declaredTailCallers[targetResolved] = append(declaredTailCallers[targetResolved], candidate) + } } } - return sigs, nil + // A declaration-free local helper reached only through tail transfers from + // Go-declared functions executes in the caller's frame. Copy the complete + // ABI when every caller agrees; this is how 32-bit ARM implements its 64-bit + // atomic helpers. Shared register-based bodies such as x86 memeqbody can + // have callers with different argument lists, so in that case propagate + // only a common return type and retain the helper's own inferred inputs. + for targetResolved, callers := range declaredTailCallers { + if len(callers) == 0 { + continue + } + inferred := callers[0] + fullABIAGrees := true + returnTypeAgrees := true + for _, caller := range callers[1:] { + if !reflect.DeepEqual(inferred, caller) { + fullABIAGrees = false + } + if inferred.Ret != caller.Ret { + returnTypeAgrees = false + } + } + if fullABIAGrees { + sigs[targetResolved] = inferred + knownABISigs[targetResolved] = true + continue + } + if returnTypeAgrees { + target := sigs[targetResolved] + // Explicit FP result slots are part of the helper's frame ABI and + // cannot be replaced by return-type evidence alone. With no such + // slots, the declared callers are the only reliable return oracle. + if len(target.Frame.Results) == 0 { + target.Ret = inferred.Ret + sigs[targetResolved] = target + } + } + } + + // A declaration-free TEXT can be a C-ABI entry trampoline that consists of + // a direct tail transfer to a Go-declared function. FP-slot heuristics have + // no return information for such a function, while the tail target provides + // its complete ABI. Inherit that signature only when every external tail + // target is declared and agrees, leaving ordinary register-return assembly + // on the conservative fallback above. + for _, fn := range file.Funcs { + callerResolved := resolve(stripABISuffix(fn.Sym)) + if !fallbackAsmSigs[callerResolved] { + continue + } + var inferred *plan9asm.FuncSig + valid := true + for _, ins := range fn.Instrs { + op := strings.ToUpper(string(ins.Op)) + if !(op == "JMP" || op == "B" || (op == "RET" && len(ins.Args) == 1)) || len(ins.Args) != 1 || ins.Args[0].Kind != plan9asm.OpSym { + continue + } + s := strings.TrimSpace(ins.Args[0].Sym) + if !strings.HasSuffix(s, "(SB)") { + continue + } + base, off := splitSymPlusOff(strings.TrimSuffix(s, "(SB)")) + targetResolved := resolve(stripABISuffix(base)) + target, ok := sigs[targetResolved] + if base == "" || off != 0 || !ok || !knownABISigs[targetResolved] { + valid = false + break + } + target.Name = callerResolved + if inferred == nil { + candidate := target + inferred = &candidate + } else if !reflect.DeepEqual(*inferred, target) { + valid = false + break + } + } + if valid && inferred != nil { + sigs[callerResolved] = *inferred + } + } + + asmsig.RefineTailForwarders(file, sigs, resolve, knownABISigs) + + return sigs, declaredArgSizes, nil +} + +func validateDeclaredTextArgSizes(file *plan9asm.File, resolve func(string) string, declaredArgSizes map[string]int64, goarch string) error { + for _, fn := range file.Funcs { + if !hasExplicitTextArgSize(fn) { + continue + } + // Go's own assembly uses the historical $frame-0 spelling for + // declaration-backed functions whose arguments are supplied by ABI + // wrappers or intentionally unused (for example runtime.procyieldAsm + // and exitThread on wasm). The assembler treats that zero as a legacy + // wildcard, so only a non-zero conflicting size proves incompatibility. + if fn.ArgSize == 0 { + continue + } + resolved := resolve(stripABISuffix(fn.Sym)) + expected, ok := declaredArgSizes[resolved] + if !ok || fn.ArgSize == expected { + continue + } + return &asmABINotApplicableError{ + Symbol: resolved, + Goarch: goarch, + DeclaredArgSize: fn.ArgSize, + ExpectedArgSize: expected, + } + } + return nil +} + +func hasExplicitTextArgSize(fn plan9asm.Func) bool { + for _, ins := range fn.Instrs { + if ins.Op != plan9asm.OpTEXT { + continue + } + parts := strings.Split(ins.Raw, ",") + if len(parts) < 2 { + return false + } + spec := strings.TrimSpace(parts[len(parts)-1]) + if !strings.HasPrefix(spec, "$") { + return false + } + return strings.LastIndex(strings.TrimPrefix(spec, "$"), "-") > 0 + } + return false } -func fallbackSigForAsmFunc(fn plan9asm.Func, resolved string) plan9asm.FuncSig { +func fallbackSigForAsmFunc(fn plan9asm.Func, resolved, goarch string) plan9asm.FuncSig { paramOff := map[int64]struct{}{} retOff := map[int64]struct{}{} for _, ins := range fn.Instrs { op := strings.ToUpper(string(ins.Op)) for i, a := range ins.Args { - if a.Kind != plan9asm.OpFP { + if a.Kind != plan9asm.OpFP && a.Kind != plan9asm.OpFPAddr { continue } if isLikelyResultSlot(op, i, len(ins.Args), a.FPName) { @@ -806,29 +1142,38 @@ func fallbackSigForAsmFunc(fn plan9asm.Func, resolved string) plan9asm.FuncSig { paramList := sortOffsets(paramOff) retList := sortOffsets(retOff) + word := plan9asm.I64 + if goarch == "386" || goarch == "arm" { + word = plan9asm.I32 + } params := make([]plan9asm.FrameSlot, 0, len(paramList)) for i, off := range paramList { - params = append(params, plan9asm.FrameSlot{Offset: off, Type: plan9asm.I64, Index: i, Field: -1}) + params = append(params, plan9asm.FrameSlot{Offset: off, Type: word, Index: i, Field: -1}) } results := make([]plan9asm.FrameSlot, 0, len(retList)) for i, off := range retList { - results = append(results, plan9asm.FrameSlot{Offset: off, Type: plan9asm.I64, Index: i, Field: -1}) + results = append(results, plan9asm.FrameSlot{Offset: off, Type: word, Index: i, Field: -1}) } args := make([]plan9asm.LLVMType, len(params)) for i := range args { - args[i] = plan9asm.I64 + args[i] = word } ret := plan9asm.Void switch len(results) { case 0: - ret = plan9asm.I64 + // A fallback with FP parameters follows ABI0, whose results also live + // in explicit FP slots. No result slot therefore means void. Keep the + // conservative word return only for register-only assembly helpers. + if len(params) == 0 { + ret = word + } case 1: - ret = plan9asm.I64 + ret = word default: parts := make([]string, 0, len(results)) for range results { - parts = append(parts, string(plan9asm.I64)) + parts = append(parts, string(word)) } ret = plan9asm.LLVMType("{ " + strings.Join(parts, ", ") + " }") } @@ -866,7 +1211,7 @@ func sortOffsets(m map[int64]struct{}) []int64 { return out } -func tryDeclSig(scope *types.Scope, sym, resolved string, linknames map[string]string, goarch string, sz types.Sizes) (plan9asm.FuncSig, bool, error) { +func tryDeclSig(scope *types.Scope, sym, resolved string, linknames map[string]string, goarch string, sz types.Sizes) (plan9asm.FuncSig, int64, bool, error) { declName := strings.TrimPrefix(sym, "·") if strings.ContainsRune(declName, '·') { key := strings.ReplaceAll(sym, "∕", "/") @@ -874,30 +1219,44 @@ func tryDeclSig(scope *types.Scope, sym, resolved string, linknames map[string]s if local, ok := linknames[key]; ok { declName = local } else { - return plan9asm.FuncSig{}, false, nil + dot := strings.LastIndexByte(key, '.') + if dot < 0 || dot == len(key)-1 { + return plan9asm.FuncSig{}, 0, false, nil + } + candidate := key[dot+1:] + obj := scope.Lookup(candidate) + if obj == nil || (key != resolved && (obj.Pkg() == nil || resolved != obj.Pkg().Path()+"."+candidate)) { + return plan9asm.FuncSig{}, 0, false, nil + } + declName = candidate } } obj := scope.Lookup(declName) if obj == nil { - return plan9asm.FuncSig{}, false, nil + return plan9asm.FuncSig{}, 0, false, nil } fn, ok := obj.(*types.Func) if !ok { - return plan9asm.FuncSig{}, false, nil + return plan9asm.FuncSig{}, 0, false, nil } sig := fn.Type().(*types.Signature) if sig.Recv() != nil || sig.Variadic() { - return plan9asm.FuncSig{}, false, nil + return plan9asm.FuncSig{}, 0, false, nil } args, frameParams, nextOff, err := llvmArgsAndFrameSlotsForTuple(sig.Params(), goarch, sz, 0, false) if err != nil { - return plan9asm.FuncSig{}, false, fmt.Errorf("%s: %w", fn.FullName(), err) + return plan9asm.FuncSig{}, 0, false, fmt.Errorf("%s: %w", fn.FullName(), err) } - nextOff = alignOff(nextOff, int64(wordSize(goarch))) - retTys, frameResults, _, err := llvmArgsAndFrameSlotsForTuple(sig.Results(), goarch, sz, nextOff, true) + // Go's TEXT argument size ends at the last declared parameter when a + // function has no results. The word-aligned gap separates parameters from + // results, so it exists only when there is a result section. + if sig.Results() != nil && sig.Results().Len() != 0 { + nextOff = alignOff(nextOff, int64(wordSize(goarch))) + } + retTys, frameResults, argSize, err := llvmArgsAndFrameSlotsForTuple(sig.Results(), goarch, sz, nextOff, true) if err != nil { - return plan9asm.FuncSig{}, false, fmt.Errorf("%s: %w", fn.FullName(), err) + return plan9asm.FuncSig{}, 0, false, fmt.Errorf("%s: %w", fn.FullName(), err) } ret := tupleRetType(retTys) return plan9asm.FuncSig{ @@ -908,7 +1267,7 @@ func tryDeclSig(scope *types.Scope, sym, resolved string, linknames map[string]s Params: frameParams, Results: frameResults, }, - }, true, nil + }, argSize, true, nil } func tupleRetType(ts []plan9asm.LLVMType) plan9asm.LLVMType { @@ -992,15 +1351,25 @@ func llvmArgsAndFrameSlotsForTuple(tup *types.Tuple, goarch string, sz types.Siz off := startOff argIdx := 0 for i := 0; i < tup.Len(); i++ { + name := "" + if flattenAgg { + name = tup.At(i).Name() + } t := tup.At(i).Type() off = align(off, int64(sz.Alignof(t))) + if sz.Sizeof(t) == 0 { + continue + } - parts, ok := framePartsForType(t, goarch) + parts, ok, e := framePartsForType(t, goarch, sz) + if e != nil { + return nil, nil, 0, e + } if ok { if flattenAgg { for _, part := range parts { args = append(args, part.Type) - slots = append(slots, plan9asm.FrameSlot{Offset: off + part.Offset, Type: part.Type, Index: argIdx, Field: -1}) + slots = append(slots, plan9asm.FrameSlot{Offset: off + part.Offset, Type: part.Type, Index: argIdx, Field: -1, Name: name}) argIdx++ } } else { @@ -1010,7 +1379,7 @@ func llvmArgsAndFrameSlotsForTuple(tup *types.Tuple, goarch string, sz types.Siz } args = append(args, ty) for _, part := range parts { - slots = append(slots, plan9asm.FrameSlot{Offset: off + part.Offset, Type: part.Type, Index: argIdx, Field: part.Field}) + slots = append(slots, plan9asm.FrameSlot{Offset: off + part.Offset, Type: part.Type, Index: argIdx, Field: part.Field, Fields: part.Fields}) } argIdx++ } @@ -1023,7 +1392,7 @@ func llvmArgsAndFrameSlotsForTuple(tup *types.Tuple, goarch string, sz types.Siz return nil, nil, 0, e } args = append(args, ty) - slots = append(slots, plan9asm.FrameSlot{Offset: off, Type: ty, Index: argIdx, Field: -1}) + slots = append(slots, plan9asm.FrameSlot{Offset: off, Type: ty, Index: argIdx, Field: -1, Name: name}) argIdx++ off += int64(sz.Sizeof(t)) } @@ -1034,39 +1403,114 @@ type framePart struct { Offset int64 Type plan9asm.LLVMType Field int + Fields []int } -func framePartsForType(t types.Type, goarch string) ([]framePart, bool) { +func framePartsForType(t types.Type, goarch string, sz types.Sizes) ([]framePart, bool, error) { word := int64(wordSize(goarch)) wordTy := plan9asm.I64 if word == 4 { wordTy = plan9asm.LLVMType("i32") } - switch u := types.Unalias(t).(type) { + switch u := types.Unalias(t).Underlying().(type) { case *types.Basic: - if u.Kind() == types.String { + switch u.Kind() { + case types.String: return []framePart{ {Offset: 0, Type: plan9asm.Ptr, Field: 0}, {Offset: word, Type: wordTy, Field: 1}, - }, true + }, true, nil + case types.Complex64: + return []framePart{ + {Offset: 0, Type: plan9asm.LLVMType("float"), Field: 0}, + {Offset: 4, Type: plan9asm.LLVMType("float"), Field: 1}, + }, true, nil + case types.Complex128: + return []framePart{ + {Offset: 0, Type: plan9asm.LLVMType("double"), Field: 0}, + {Offset: 8, Type: plan9asm.LLVMType("double"), Field: 1}, + }, true, nil } case *types.Slice: return []framePart{ {Offset: 0, Type: plan9asm.Ptr, Field: 0}, {Offset: word, Type: wordTy, Field: 1}, {Offset: 2 * word, Type: wordTy, Field: 2}, - }, true + }, true, nil case *types.Interface: // Both empty and non-empty interfaces occupy two pointers in Go ABI. return []framePart{ {Offset: 0, Type: plan9asm.Ptr, Field: 0}, {Offset: word, Type: plan9asm.Ptr, Field: 1}, - }, true + }, true, nil + case *types.Array: + elemParts, elemAggregate, err := framePartsForType(u.Elem(), goarch, sz) + if err != nil { + return nil, false, err + } + if !elemAggregate { + elemType, err := llvmTypeForGo(u.Elem(), goarch) + if err != nil { + return nil, false, err + } + elemParts = []framePart{{Type: elemType, Field: -1}} + } + elemSize := int64(sz.Sizeof(u.Elem())) + parts := make([]framePart, 0, int(u.Len())*len(elemParts)) + for i := int64(0); i < u.Len(); i++ { + for _, part := range elemParts { + parts = append(parts, nestedFramePart(part, int(i), i*elemSize)) + } + } + return parts, true, nil + case *types.Struct: + fields := make([]*types.Var, u.NumFields()) + for i := range fields { + fields[i] = u.Field(i) + } + offsets := sz.Offsetsof(fields) + var parts []framePart + for i, field := range fields { + fieldParts, fieldAggregate, err := framePartsForType(field.Type(), goarch, sz) + if err != nil { + return nil, false, err + } + if !fieldAggregate { + fieldType, err := llvmTypeForGo(field.Type(), goarch) + if err != nil { + return nil, false, err + } + fieldParts = []framePart{{Type: fieldType, Field: -1}} + } + for _, part := range fieldParts { + parts = append(parts, nestedFramePart(part, i, offsets[i])) + } + } + return parts, true, nil + } + return nil, false, nil +} + +func nestedFramePart(part framePart, field int, offset int64) framePart { + path := make([]int, 0, 1+len(part.Fields)+1) + path = append(path, field) + if len(part.Fields) != 0 { + path = append(path, part.Fields...) + } else if part.Field >= 0 { + path = append(path, part.Field) + } + part.Offset += offset + part.Field = field + if len(path) > 1 { + part.Fields = path + } else { + part.Fields = nil } - return nil, false + return part } func llvmTypeForGo(t types.Type, goarch string) (plan9asm.LLVMType, error) { + t = types.Unalias(t) switch tt := t.(type) { case *types.Basic: switch tt.Kind() { @@ -1091,6 +1535,10 @@ func llvmTypeForGo(t types.Type, goarch string) (plan9asm.LLVMType, error) { return plan9asm.LLVMType("float"), nil case types.Float64: return plan9asm.LLVMType("double"), nil + case types.Complex64: + return plan9asm.LLVMType("{ float, float }"), nil + case types.Complex128: + return plan9asm.LLVMType("{ double, double }"), nil case types.String: if wordSize(goarch) == 8 { return plan9asm.LLVMType("{ ptr, i64 }"), nil @@ -1101,6 +1549,8 @@ func llvmTypeForGo(t types.Type, goarch string) (plan9asm.LLVMType, error) { } case *types.Pointer: return plan9asm.Ptr, nil + case *types.Signature, *types.Map, *types.Chan: + return plan9asm.Ptr, nil case *types.Slice: if wordSize(goarch) == 8 { return plan9asm.LLVMType("{ ptr, i64, i64 }"), nil @@ -1108,6 +1558,25 @@ func llvmTypeForGo(t types.Type, goarch string) (plan9asm.LLVMType, error) { return plan9asm.LLVMType("{ ptr, i32, i32 }"), nil case *types.Interface: return plan9asm.LLVMType("{ ptr, ptr }"), nil + case *types.Array: + elem, err := llvmTypeForGo(tt.Elem(), goarch) + if err != nil { + return "", err + } + return plan9asm.LLVMType(fmt.Sprintf("[%d x %s]", tt.Len(), elem)), nil + case *types.Struct: + if tt.NumFields() == 0 { + return plan9asm.LLVMType("[0 x i8]"), nil + } + fields := make([]string, tt.NumFields()) + for i := range fields { + fieldType, err := llvmTypeForGo(tt.Field(i).Type(), goarch) + if err != nil { + return "", err + } + fields[i] = string(fieldType) + } + return plan9asm.LLVMType("{ " + strings.Join(fields, ", ") + " }"), nil case *types.Named: return llvmTypeForGo(tt.Underlying(), goarch) default: @@ -1117,7 +1586,7 @@ func llvmTypeForGo(t types.Type, goarch string) (plan9asm.LLVMType, error) { func wordSize(goarch string) int { switch goarch { - case "amd64", "arm64", "loong64", "mips64", "mips64le", "ppc64", "ppc64le", "riscv64", "s390x": + case "amd64", "arm64", "loong64", "mips64", "mips64le", "ppc64", "ppc64le", "riscv64", "s390x", "wasm": return 8 default: return 4 @@ -1235,46 +1704,191 @@ func extractSupportedOps(repoRoot, goarch string) (map[string]struct{}, error) { if err != nil { return nil, fmt.Errorf("read %s: %w", f, err) } - for _, m := range reCaseString.FindAllSubmatch(src, -1) { - nop := normalizeOp(string(m[1])) - if nop != "" { - supported[nop] = struct{}{} + parsed, err := parser.ParseFile(token.NewFileSet(), f, src, 0) + if err != nil { + return nil, fmt.Errorf("parse %s for supported instructions: %w", f, err) + } + // Package-level opcode specification maps are dispatch tables even when + // their variable name does not contain "op" (for example a complete + // instruction-family Specs table). Restrict this broader inference to + // package declarations so local maps for predicates, registers, and LLVM + // spellings cannot accidentally advertise instructions. + for _, decl := range parsed.Decls { + gen, ok := decl.(*ast.GenDecl) + if !ok || gen.Tok != token.VAR { + continue } - } - for _, m := range reCaseOp.FindAllSubmatch(src, -1) { - nop := normalizeOp(string(m[1])) - if nop != "" { - supported[nop] = struct{}{} + for _, declared := range gen.Specs { + spec, ok := declared.(*ast.ValueSpec) + if !ok { + continue + } + for _, value := range spec.Values { + literal, ok := value.(*ast.CompositeLit) + if !ok { + continue + } + collectSupportedOpcodeMap(supported, literal) + } } } - // Handle multi-value case clauses like: - // case "A", "B", "C": - for _, ln := range strings.Split(string(src), "\n") { - if !strings.Contains(ln, "case") { - continue + ast.Inspect(parsed, func(node ast.Node) bool { + // Family lowerers commonly reject everything except their opcode at + // the top of the function (for example `if op != "VDUP"`). Those + // handlers are just as authoritative as switch cases and opcode maps; + // include only comparisons whose other operand is literally named op + // so unrelated string predicates cannot advertise false support. + if comparison, ok := node.(*ast.BinaryExpr); ok && + (comparison.Op == token.EQL || comparison.Op == token.NEQ) { + if candidate, ok := opcodeComparedWithOp(comparison.X, comparison.Y); ok { + if nop := normalizeOp(candidate); nop != "" { + supported[nop] = struct{}{} + } + } } - for _, m := range reQuotedOp.FindAllStringSubmatch(ln, -1) { - nop := normalizeOp(m[1]) - if nop != "" { - supported[nop] = struct{}{} + if spec, ok := node.(*ast.ValueSpec); ok { + for i, name := range spec.Names { + // Several backends keep their complete opcode tables in a + // map[string]spec rather than map[Op]spec. Limit string-key + // extraction to declarations explicitly named as opcode maps; + // otherwise condition-code and register-name tables would be + // mistaken for supported instructions. + if !strings.Contains(strings.ToLower(name.Name), "op") || len(spec.Values) == 0 { + continue + } + valueIndex := i + if len(spec.Values) == 1 { + valueIndex = 0 + } + if valueIndex >= len(spec.Values) { + continue + } + literal, ok := spec.Values[valueIndex].(*ast.CompositeLit) + if !ok { + continue + } + mapType, isMap := literal.Type.(*ast.MapType) + keyType, stringKeyed := mapTypeKeyIdent(mapType) + if !isMap || !stringKeyed || keyType != "string" { + continue + } + for _, elt := range literal.Elts { + pair, ok := elt.(*ast.KeyValueExpr) + if !ok { + continue + } + key, ok := pair.Key.(*ast.BasicLit) + if !ok || key.Kind != token.STRING { + continue + } + candidate, _ := strconv.Unquote(key.Value) + if nop := normalizeOp(candidate); nop != "" { + supported[nop] = struct{}{} + } + } } } - for _, m := range reOpToken.FindAllStringSubmatch(ln, -1) { - nop := normalizeOp(m[1]) - if nop != "" { + literal, ok := node.(*ast.CompositeLit) + if ok { + mapType, isMap := literal.Type.(*ast.MapType) + keyType, isOpMap := mapTypeKeyIdent(mapType) + if isMap && isOpMap && keyType == "Op" { + for _, elt := range literal.Elts { + pair, ok := elt.(*ast.KeyValueExpr) + if !ok { + continue + } + key, ok := pair.Key.(*ast.BasicLit) + if !ok || key.Kind != token.STRING { + continue + } + candidate, _ := strconv.Unquote(key.Value) + if nop := normalizeOp(candidate); nop != "" { + supported[nop] = struct{}{} + } + } + } + } + clause, ok := node.(*ast.CaseClause) + if !ok { + return true + } + for _, expr := range clause.List { + candidate := "" + switch value := expr.(type) { + case *ast.BasicLit: + if value.Kind == token.STRING { + candidate, _ = strconv.Unquote(value.Value) + } + case *ast.Ident: + if strings.HasPrefix(value.Name, "Op") { + candidate = strings.TrimPrefix(value.Name, "Op") + } + } + if nop := normalizeOp(candidate); nop != "" { supported[nop] = struct{}{} } } - } + return true + }) } return supported, nil } -func unsupportedInAsmFile(path string, arch plan9asm.Arch, supported map[string]struct{}) ([]string, []unsupportedHit) { +func opcodeComparedWithOp(left, right ast.Expr) (string, bool) { + if ident, ok := left.(*ast.Ident); ok && ident.Name == "op" { + if literal, ok := right.(*ast.BasicLit); ok && literal.Kind == token.STRING { + candidate, err := strconv.Unquote(literal.Value) + return candidate, err == nil + } + } + if ident, ok := right.(*ast.Ident); ok && ident.Name == "op" { + if literal, ok := left.(*ast.BasicLit); ok && literal.Kind == token.STRING { + candidate, err := strconv.Unquote(literal.Value) + return candidate, err == nil + } + } + return "", false +} + +func collectSupportedOpcodeMap(supported map[string]struct{}, literal *ast.CompositeLit) { + mapType, isMap := literal.Type.(*ast.MapType) + keyType, supportedKey := mapTypeKeyIdent(mapType) + if !isMap || !supportedKey || keyType != "string" && keyType != "Op" { + return + } + for _, elt := range literal.Elts { + pair, ok := elt.(*ast.KeyValueExpr) + if !ok { + continue + } + key, ok := pair.Key.(*ast.BasicLit) + if !ok || key.Kind != token.STRING { + continue + } + candidate, _ := strconv.Unquote(key.Value) + if nop := normalizeOp(candidate); nop != "" { + supported[nop] = struct{}{} + } + } +} + +func mapTypeKeyIdent(mapType *ast.MapType) (string, bool) { + if mapType == nil { + return "", false + } + ident, ok := mapType.Key.(*ast.Ident) + if !ok { + return "", false + } + return ident.Name, true +} + +func unsupportedInAsmFile(path, sourceRoot string, arch plan9asm.Arch, supported map[string]struct{}) ([]string, []unsupportedHit) { if len(supported) == 0 { return nil, nil } - src, err := os.ReadFile(path) + src, err := readAsmSource(path, sourceRoot) if err != nil { return nil, nil } diff --git a/cmd/plan9asmll/main_test.go b/cmd/plan9asmll/main_test.go index 480b5a61..d6e0cbc3 100644 --- a/cmd/plan9asmll/main_test.go +++ b/cmd/plan9asmll/main_test.go @@ -1,17 +1,1362 @@ package main import ( + "errors" + "fmt" + "go/constant" "go/token" "go/types" "os" "path/filepath" "reflect" + "strings" "testing" "github.com/xgo-dev/plan9asm" "golang.org/x/tools/go/packages" ) +func TestWASMABIForGoPackageTarget(t *testing.T) { + if got := wasmABIForGoPackageTarget("wasm"); got != plan9asm.WASMABIGo { + t.Fatalf("wasmABIForGoPackageTarget(wasm) = %v, want Go stack ABI", got) + } + for _, goarch := range []string{"amd64", "386", "arm", "arm64"} { + if got := wasmABIForGoPackageTarget(goarch); got != plan9asm.WASMABIDirect { + t.Fatalf("wasmABIForGoPackageTarget(%s) = %v, want direct ABI", goarch, got) + } + } +} + +func TestContainsTestAssembly(t *testing.T) { + for _, name := range []string{"pkg/routine_test_amd64.s", "pkg/routine_test.s"} { + if !containsTestAssembly([]string{name}) { + t.Errorf("containsTestAssembly(%q) = false, want true", name) + } + } + if containsTestAssembly([]string{"pkg/contest_amd64.s", "pkg/routine_amd64.s"}) { + t.Fatal("containsTestAssembly accepted non-test assembly") + } +} + +func TestIsTestVariantPackage(t *testing.T) { + base := &packages.Package{ID: "example.com/p", PkgPath: "example.com/p"} + variant := &packages.Package{ID: "example.com/p [example.com/p.test]", PkgPath: "example.com/p"} + if isTestVariantPackage(base) || !isTestVariantPackage(variant) { + t.Fatalf("test variant classification: base=%v variant=%v", isTestVariantPackage(base), isTestVariantPackage(variant)) + } +} + +func TestRunOneTargetUsesTestDeclarationForExactTestAssembly(t *testing.T) { + report, _, err := runOneTarget( + targetSpec{Goos: "linux", Goarch: "amd64"}, + []string{"./testdata/testsignature"}, + nil, + []string{"testdata/testsignature/convert_test_amd64.s"}, + "github.com/xgo-dev/plan9asm/cmd/plan9asmll", + t.TempDir(), + false, + 0, + true, + false, + false, + filepath.Join("..", ".."), + compileConfig{}, + ) + if err != nil { + t.Fatal(err) + } + if report.TotalAsm != 1 || report.Success != 1 || report.Failed != 0 { + t.Fatalf("test assembly report = %#v, want one successful translation", report) + } +} + +func TestCompileOneExpandsGoAsmPackageConstants(t *testing.T) { + typesPkg := types.NewPackage("example.com/constants", "constants") + typesPkg.Scope().Insert(types.NewConst(token.NoPos, typesPkg, "q", types.Typ[types.UntypedInt], constant.MakeUint64(2013265921))) + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, "vectorConstant", types.NewSignatureType(nil, nil, nil, nil, nil, false))) + pkg := &packages.Package{ + PkgPath: "example.com/constants", + Types: typesPkg, + Imports: map[string]*packages.Package{}, + } + dir := t.TempDir() + asm := filepath.Join(dir, "constant_arm64.s") + if err := os.WriteFile(asm, []byte("TEXT ·vectorConstant(SB),$0-0\n\tVMOVS $const_q, V0\n\tRET\n"), 0o600); err != nil { + t.Fatal(err) + } + out := filepath.Join(dir, "constant.ll") + if err := compileOne(pkg, plan9asm.ArchARM64, "linux", "arm64", "aarch64-unknown-linux-gnu", asmTask{ + PkgPath: pkg.PkgPath, + AsmFile: asm, + OutLL: out, + }, false, compileConfig{}); err != nil { + t.Fatal(err) + } + ir, err := os.ReadFile(out) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(string(ir), "i32 2013265921") { + t.Fatalf("translated package constant is absent from IR:\n%s", ir) + } +} + +func TestCompileOneInfersVoidABI0LocalHelperAtTargetWordSize(t *testing.T) { + typesPkg := types.NewPackage("runtime", "runtime") + voidSignature := types.NewSignatureType(nil, nil, nil, nil, nil, false) + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, "systemstack", voidSignature)) + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", "386"), + Imports: map[string]*packages.Package{}, + } + dir := t.TempDir() + asm := filepath.Join(dir, "asm_386.s") + const source = `TEXT runtime·systemstack(SB),NOSPLIT,$0-0 + CALL gosave_systemstack_switch<>(SB) + RET + +TEXT gosave_systemstack_switch<>(SB),NOSPLIT,$0 + LEAL arg+0(FP), AX + RET +` + if err := os.WriteFile(asm, []byte(source), 0o600); err != nil { + t.Fatal(err) + } + out := filepath.Join(dir, "asm_386.ll") + if err := compileOne(pkg, plan9asm.ArchAMD64, "linux", "386", "i386-unknown-linux-gnu", asmTask{ + PkgPath: pkg.PkgPath, + AsmFile: asm, + OutLL: out, + }, false, compileConfig{}); err != nil { + t.Fatal(err) + } + ir, err := os.ReadFile(out) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + `define void @"runtime.gosave_systemstack_switch$local"(i32 %arg0)`, + `call void @"runtime.gosave_systemstack_switch$local"(i32 %`, + } { + if !strings.Contains(string(ir), want) { + t.Fatalf("translated ABI0 local helper omitted %q:\n%s", want, ir) + } + } +} + +func TestTryDeclSigResolvesSamePackageQualifiedPlan9Symbol(t *testing.T) { + pkg := types.NewPackage("runtime/internal/atomic", "atomic") + params := types.NewTuple( + types.NewParam(token.NoPos, pkg, "ptr", types.NewPointer(types.Typ[types.Uint64])), + types.NewParam(token.NoPos, pkg, "delta", types.Typ[types.Int64]), + ) + results := types.NewTuple(types.NewParam(token.NoPos, pkg, "ret", types.Typ[types.Uint64])) + signature := types.NewSignatureType(nil, nil, nil, params, results, false) + pkg.Scope().Insert(types.NewFunc(token.NoPos, pkg, "Xadd64", signature)) + + got, _, ok, err := tryDeclSig( + pkg.Scope(), + "runtime∕internal∕atomic·Xadd64", + "runtime/internal/atomic.Xadd64", + nil, + "386", + types.SizesFor("gc", "386"), + ) + if err != nil { + t.Fatal(err) + } + if !ok || got.Ret != plan9asm.I64 || len(got.Args) != 2 || got.Args[0] != plan9asm.Ptr || got.Args[1] != plan9asm.I64 { + t.Fatalf("qualified declaration signature = %#v, ok=%v; want (ptr, i64) i64", got, ok) + } +} + +func TestTryDeclSigUsesOfficialWASMFrameWordSize(t *testing.T) { + pkg := types.NewPackage("internal/bytealg", "bytealg") + params := types.NewTuple( + types.NewParam(token.NoPos, pkg, "a", types.Typ[types.String]), + types.NewParam(token.NoPos, pkg, "b", types.Typ[types.String]), + ) + results := types.NewTuple(types.NewParam(token.NoPos, pkg, "ret", types.Typ[types.Int])) + pkg.Scope().Insert(types.NewFunc(token.NoPos, pkg, "abigen_runtime_cmpstring", types.NewSignatureType(nil, nil, nil, params, results, false))) + + sig, argSize, ok, err := tryDeclSig( + pkg.Scope(), + "runtime·cmpstring", + "runtime.cmpstring", + map[string]string{"runtime.cmpstring": "abigen_runtime_cmpstring"}, + "wasm", + types.SizesFor("gc", "wasm"), + ) + if err != nil { + t.Fatal(err) + } + if !ok { + t.Fatal("runtime.cmpstring declaration was not resolved") + } + var paramOffsets []int64 + for _, slot := range sig.Frame.Params { + paramOffsets = append(paramOffsets, slot.Offset) + } + if want := []int64{0, 8, 16, 24}; !reflect.DeepEqual(paramOffsets, want) { + t.Fatalf("wasm frame parameter offsets = %v, want %v", paramOffsets, want) + } + if len(sig.Frame.Results) != 1 || sig.Frame.Results[0].Offset != 32 || argSize != 40 { + t.Fatalf("wasm result frame = %#v, arg size = %d; want result at 32 and size 40", sig.Frame.Results, argSize) + } +} + +func TestSigsForAsmFileInfersWASMLocalNativeSignature(t *testing.T) { + typesPkg := types.NewPackage("internal/bytealg", "bytealg") + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", "wasm"), + } + file, err := plan9asm.Parse(plan9asm.ArchWASM, `TEXT memchr<>(SB), NOSPLIT, $0 + Get R0 + I32Load8U $0 + Get R1 + I32Eq + Get R2 + Select + Return +`) + if err != nil { + t.Fatal(err) + } + resolve := resolveSymFunc(pkg.PkgPath) + sigs, _, err := sigsForAsmFile(pkg, file, resolve, "wasm") + if err != nil { + t.Fatal(err) + } + wantName := pkg.PkgPath + ".memchr$local" + got, ok := sigs[wantName] + if !ok { + t.Fatalf("local wasm signature %q is missing; signatures: %#v", wantName, sigs) + } + wantArgs := []plan9asm.LLVMType{plan9asm.I32, plan9asm.I32, plan9asm.I32} + wantRegs := []plan9asm.Reg{"R0", "R1", "R2"} + if !reflect.DeepEqual(got.Args, wantArgs) || !reflect.DeepEqual(got.ArgRegs, wantRegs) || got.Ret != plan9asm.I32 || !got.WASMNative { + t.Fatalf("local wasm signature = %#v; want args %v in %v, i32 return, native ABI", got, wantArgs, wantRegs) + } +} + +func TestSigsForAsmFileUsesGoWASMSpecialNativeSignature(t *testing.T) { + typesPkg := types.NewPackage("runtime", "runtime") + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", "wasm"), + } + file, err := plan9asm.Parse(plan9asm.ArchWASM, `TEXT gcWriteBarrier<>(SB), NOSPLIT, $0 + Get R1 + Get R0 + I64Add + Set R1 + Get R1 + I64Load 0(R2) + I64LeU + If + Get R1 + Get R0 + I64Sub + Return + End +`) + if err != nil { + t.Fatal(err) + } + sigs, _, err := sigsForAsmFile(pkg, file, resolveSymFunc(pkg.PkgPath), "wasm") + if err != nil { + t.Fatal(err) + } + wantName := pkg.PkgPath + ".gcWriteBarrier$local" + got := sigs[wantName] + if wantArgs := []plan9asm.LLVMType{plan9asm.I64}; !reflect.DeepEqual(got.Args, wantArgs) || !reflect.DeepEqual(got.ArgRegs, []plan9asm.Reg{"R0"}) || got.Ret != plan9asm.I64 || !got.WASMNative { + t.Fatalf("special local wasm signature = %#v; want R0:i64 -> i64 native ABI", got) + } +} + +func TestSigsForAsmFileUsesGoWASMSpecialReferencedSignature(t *testing.T) { + typesPkg := types.NewPackage("runtime", "runtime") + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", "wasm"), + } + file, err := plan9asm.Parse(plan9asm.ArchWASM, "TEXT wasm_export_run(SB),NOSPLIT,$0\n\tCall wasm_pc_f_loop(SB)\n\tReturn\n") + if err != nil { + t.Fatal(err) + } + sigs, _, err := sigsForAsmFile(pkg, file, resolveSymFunc(pkg.PkgPath), "wasm") + if err != nil { + t.Fatal(err) + } + got, ok := sigs["wasm_pc_f_loop"] + if !ok || len(got.Args) != 0 || got.Ret != plan9asm.Void || !got.WASMNative { + t.Fatalf("referenced special wasm signature = %#v, present=%v; want () -> void native ABI", got, ok) + } +} + +func TestSigsForAsmFileKeepsWASMLocalRETHelperOnGoABI(t *testing.T) { + typesPkg := types.NewPackage("runtime", "runtime") + voidSig := types.NewSignatureType(nil, nil, nil, nil, nil, false) + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, "caller", voidSig)) + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", "wasm"), + } + file, err := plan9asm.Parse(plan9asm.ArchWASM, `TEXT ·caller(SB), NOSPLIT, $0-0 + CALL callRet<>(SB) + RET +TEXT callRet<>(SB), NOSPLIT, $40-0 + RET +`) + if err != nil { + t.Fatal(err) + } + sigs, _, err := sigsForAsmFile(pkg, file, resolveSymFunc(pkg.PkgPath), "wasm") + if err != nil { + t.Fatal(err) + } + got := sigs[pkg.PkgPath+".callRet$local"] + if got.WASMNative { + t.Fatalf("RET-based local helper signature = %#v; want Go WebAssembly ABI", got) + } +} + +func TestFallbackSigIncludesAddressedFrameParameters(t *testing.T) { + fn := plan9asm.Func{ + Sym: "kernelCAS64<>", + Instrs: []plan9asm.Instr{ + {Op: "MOVW", Args: []plan9asm.Operand{{Kind: plan9asm.OpFP, FPName: "addr", FPOffset: 0}, {Kind: plan9asm.OpReg, Reg: "R2"}}}, + {Op: "MOVW", Args: []plan9asm.Operand{{Kind: plan9asm.OpFPAddr, FPName: "oldval", FPOffset: 4}, {Kind: plan9asm.OpReg, Reg: "R0"}}}, + {Op: "MOVW", Args: []plan9asm.Operand{{Kind: plan9asm.OpFPAddr, FPName: "newval", FPOffset: 12}, {Kind: plan9asm.OpReg, Reg: "R1"}}}, + {Op: "MOVW", Args: []plan9asm.Operand{{Kind: plan9asm.OpReg, Reg: "R0"}, {Kind: plan9asm.OpFP, FPName: "ret", FPOffset: 20}}}, + }, + } + sig := fallbackSigForAsmFunc(fn, "example.kernelCAS64$local", "arm") + var offsets []int64 + for _, slot := range sig.Frame.Params { + offsets = append(offsets, slot.Offset) + } + want := []int64{0, 4, 12} + if !reflect.DeepEqual(offsets, want) { + t.Fatalf("fallback frame parameter offsets = %v, want %v", offsets, want) + } +} + +func TestSigsForAsmFileDiscoversRETTailTarget(t *testing.T) { + typesPkg := types.NewPackage("example.com/retjmp", "retjmp") + voidSig := types.NewSignatureType(nil, nil, nil, nil, nil, false) + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, "f", voidSig)) + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, "f2", voidSig)) + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", "wasm"), + } + file, err := plan9asm.Parse(plan9asm.ArchWASM, "TEXT ·f(SB), NOSPLIT, $0-0\n\tRET ·f2(SB)\n") + if err != nil { + t.Fatal(err) + } + resolve := resolveSymFunc(pkg.PkgPath) + sigs, _, err := sigsForAsmFile(pkg, file, resolve, "wasm") + if err != nil { + t.Fatal(err) + } + want := pkg.PkgPath + ".f2" + if sig, ok := sigs[want]; !ok || sig.Name != want || sig.Ret != plan9asm.Void { + t.Fatalf("RET tail target signature = %#v, present=%v; want void signature for %q", sig, ok, want) + } +} + +func TestSigsForAsmFilePreservesLocalMarkerOnDirectCallTarget(t *testing.T) { + typesPkg := types.NewPackage("example.com/caller", "caller") + voidSig := types.NewSignatureType(nil, nil, nil, nil, nil, false) + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, "MoreStack", voidSig)) + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", "amd64"), + } + file, err := plan9asm.Parse(plan9asm.ArchAMD64, "TEXT ·MoreStack(SB),NOSPLIT,$0-0\n\tCALL runtime·morestack_noctxt<>(SB)\n\tRET\n") + if err != nil { + t.Fatal(err) + } + sigs, _, err := sigsForAsmFile(pkg, file, resolveSymFunc(pkg.PkgPath), "amd64") + if err != nil { + t.Fatal(err) + } + if _, ok := sigs["runtime.morestack_noctxt$local"]; !ok { + t.Fatalf("local direct-call target signature missing; signatures: %#v", sigs) + } +} + +func TestSigsForAsmFileDiscoversAllDirectCallOpcodes(t *testing.T) { + for _, tc := range []struct { + name string + goarch string + arch plan9asm.Arch + op string + }{ + {name: "wasm native call", goarch: "wasm", arch: plan9asm.ArchWASM, op: "Call"}, + {name: "wasm no-resume call", goarch: "wasm", arch: plan9asm.ArchWASM, op: "CALLNORESUME"}, + {name: "machine call", goarch: "amd64", arch: plan9asm.ArchAMD64, op: "CALL"}, + {name: "arm branch-link", goarch: "arm", arch: plan9asm.ArchARM, op: "BL"}, + } { + t.Run(tc.name, func(t *testing.T) { + typesPkg := types.NewPackage("example.com/calls", "calls") + voidSig := types.NewSignatureType(nil, nil, nil, nil, nil, false) + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, "caller", voidSig)) + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, "target", voidSig)) + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", tc.goarch), + } + file, err := plan9asm.Parse(tc.arch, "TEXT ·caller(SB),NOSPLIT,$0-0\n\t"+tc.op+" ·target(SB)\n\tRET\n") + if err != nil { + t.Fatal(err) + } + sigs, _, err := sigsForAsmFile(pkg, file, resolveSymFunc(pkg.PkgPath), tc.goarch) + if err != nil { + t.Fatal(err) + } + want := pkg.PkgPath + ".target" + if sig, ok := sigs[want]; !ok || sig.Name != want || sig.Ret != plan9asm.Void { + t.Fatalf("%s target signature = %#v, present=%v; want void signature for %q", tc.op, sig, ok, want) + } + }) + } +} + +func TestSigsForAsmFileInfersUndeclaredTailForwarderFromDeclaredTarget(t *testing.T) { + typesPkg := types.NewPackage("example.com/fakecgo", "fakecgo") + params := types.NewTuple( + types.NewParam(token.NoPos, typesPkg, "g", types.NewPointer(types.Typ[types.Uint8])), + types.NewParam(token.NoPos, typesPkg, "setg", types.Typ[types.Uintptr]), + ) + voidSig := types.NewSignatureType(nil, nil, nil, params, nil, false) + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, "x_cgo_init", voidSig)) + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", "386"), + } + file, err := plan9asm.Parse(plan9asm.ArchAMD64, "TEXT x_cgo_init_trampoline(SB),NOSPLIT|NOFRAME,$0\n\tJMP ·x_cgo_init(SB)\n\tRET\n") + if err != nil { + t.Fatal(err) + } + resolve := resolveSymFunc(pkg.PkgPath) + sigs, _, err := sigsForAsmFile(pkg, file, resolve, "386") + if err != nil { + t.Fatal(err) + } + caller := sigs["x_cgo_init_trampoline"] + target := sigs[pkg.PkgPath+".x_cgo_init"] + if caller.Ret != plan9asm.Void || len(caller.Args) != 2 || caller.Args[0] != plan9asm.Ptr || caller.Args[1] != plan9asm.I32 { + t.Fatalf("tail-forwarder signature = %#v, target = %#v; want (ptr, i32) void inherited from declared target", caller, target) + } +} + +func TestSigsForAsmFileInfersPureTailForwarderFromABI0Body(t *testing.T) { + // The Go declarations may be disabled by build tags while the assembly + // remains selected (gomlx/compute uses goexperiment.simd this way). + for _, tc := range []struct { + arch plan9asm.Arch + goarch, move, branch, reg string + word int + }{ + {plan9asm.ArchAMD64, "amd64", "MOVQ", "JMP", "AX", 8}, + {plan9asm.ArchAMD64, "386", "MOVL", "JMP", "AX", 4}, + {plan9asm.ArchARM, "arm", "MOVW", "B", "R0", 4}, + {plan9asm.ArchARM64, "arm64", "MOVD", "B", "R0", 8}, + } { + t.Run(tc.goarch, func(t *testing.T) { + typesPkg := types.NewPackage("example.com/forward", "forward") + pkg := &packages.Package{PkgPath: typesPkg.Path(), Types: typesPkg, TypesSizes: types.SizesFor("gc", tc.goarch)} + for _, body := range []string{ + "TEXT ·forward(SB),$0-%d\n\t%s ·body(SB)\n", + "TEXT ·forward(SB),$0-%d\n\t%s ·middle(SB)\nTEXT ·middle(SB),$0\n\t" + tc.branch + " ·body(SB)\n", + } { + source := fmt.Sprintf(body, tc.word, tc.branch) + fmt.Sprintf("TEXT ·body(SB),$0-%d\n\t%s arg+0(FP), %s\n\tRET\n", tc.word, tc.move, tc.reg) + file, err := plan9asm.Parse(tc.arch, source) + if err != nil { + t.Fatal(err) + } + sigs, _, err := sigsForAsmFile(pkg, file, resolveSymFunc(pkg.PkgPath), tc.goarch) + if err != nil { + t.Fatal(err) + } + want := sigs[pkg.PkgPath+".body"] + got := sigs[pkg.PkgPath+".forward"] + want.Name = got.Name + if !reflect.DeepEqual(got, want) || got.Ret != plan9asm.Void || len(got.Args) != 1 { + t.Fatalf("pure tail forwarder = %#v, want body ABI %#v", got, want) + } + if _, err := plan9asm.Translate(file, plan9asm.Options{Goarch: tc.goarch, ResolveSym: resolveSymFunc(pkg.PkgPath), Sigs: sigs}); err != nil { + t.Fatal(err) + } + } + }) + } +} + +func TestSigsForAsmFileInfersLocalTailTargetFromDeclaredCaller(t *testing.T) { + typesPkg := types.NewPackage("internal/runtime/atomic", "atomic") + params := types.NewTuple( + types.NewParam(token.NoPos, typesPkg, "addr", types.NewPointer(types.Typ[types.Uint64])), + types.NewParam(token.NoPos, typesPkg, "delta", types.Typ[types.Int64]), + ) + results := types.NewTuple(types.NewParam(token.NoPos, typesPkg, "new", types.Typ[types.Uint64])) + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, "Xadd64", types.NewSignatureType(nil, nil, nil, params, results, false))) + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", "arm"), + } + file, err := plan9asm.Parse(plan9asm.ArchARM, `TEXT ·Xadd64(SB),NOSPLIT,$-4-20 + B armXadd64<>(SB) +TEXT armXadd64<>(SB),NOSPLIT,$0-20 + MOVW R4, new_lo+12(FP) + MOVW R5, new_hi+16(FP) + RET +`) + if err != nil { + t.Fatal(err) + } + resolve := resolveSymFunc(pkg.PkgPath) + sigs, _, err := sigsForAsmFile(pkg, file, resolve, "arm") + if err != nil { + t.Fatal(err) + } + caller := sigs[pkg.PkgPath+".Xadd64"] + target := sigs[pkg.PkgPath+".armXadd64$local"] + caller.Name = "" + target.Name = "" + if !reflect.DeepEqual(target, caller) { + t.Fatalf("local tail target signature = %#v, want declared caller signature %#v", target, caller) + } +} + +func TestSigsForAsmFileInfersSharedLocalTailTargetReturnFromDeclaredCallers(t *testing.T) { + typesPkg := types.NewPackage("internal/bytealg", "bytealg") + boolResult := types.NewTuple(types.NewParam(token.NoPos, typesPkg, "equal", types.Typ[types.Bool])) + for name, params := range map[string]*types.Tuple{ + "Equal": types.NewTuple( + types.NewParam(token.NoPos, typesPkg, "a", types.NewPointer(types.Typ[types.Uint8])), + types.NewParam(token.NoPos, typesPkg, "b", types.NewPointer(types.Typ[types.Uint8])), + types.NewParam(token.NoPos, typesPkg, "size", types.Typ[types.Uintptr]), + ), + "EqualVarlen": types.NewTuple( + types.NewParam(token.NoPos, typesPkg, "a", types.NewPointer(types.Typ[types.Uint8])), + types.NewParam(token.NoPos, typesPkg, "b", types.NewPointer(types.Typ[types.Uint8])), + ), + } { + typesPkg.Scope().Insert(types.NewFunc(token.NoPos, typesPkg, name, types.NewSignatureType(nil, nil, nil, params, boolResult, false))) + } + pkg := &packages.Package{ + PkgPath: typesPkg.Path(), + Types: typesPkg, + TypesSizes: types.SizesFor("gc", "386"), + } + file, err := plan9asm.Parse(plan9asm.ArchAMD64, `TEXT ·Equal(SB),NOSPLIT,$0-13 + JMP memeqbody<>(SB) +TEXT ·EqualVarlen(SB),NOSPLIT,$0-9 + JMP memeqbody<>(SB) +TEXT memeqbody<>(SB),NOSPLIT,$0-0 + RET +`) + if err != nil { + t.Fatal(err) + } + resolve := resolveSymFunc(pkg.PkgPath) + sigs, _, err := sigsForAsmFile(pkg, file, resolve, "386") + if err != nil { + t.Fatal(err) + } + target := sigs[pkg.PkgPath+".memeqbody$local"] + if target.Ret != plan9asm.I1 { + t.Fatalf("shared local tail target signature = %#v, want common declared return i1", target) + } + if len(target.Args) != 0 || len(target.Frame.Params) != 0 || len(target.Frame.Results) != 0 { + t.Fatalf("shared local tail target inherited incompatible caller frame: %#v", target) + } +} + +func TestValidateDeclaredTextArgSizesClassifiesOnlyExplicitABIMismatches(t *testing.T) { + resolve := func(sym string) string { return "example.com/ext." + strings.TrimPrefix(sym, "·") } + declared := map[string]int64{"example.com/ext.StructFieldB": 17} + + tests := []struct { + name string + text string + argSize int64 + wantErr bool + }{ + {name: "wrong explicit size", text: "TEXT ·StructFieldB(SB), $0-25", argSize: 25, wantErr: true}, + {name: "matching explicit size", text: "TEXT ·StructFieldB(SB), $0-17", argSize: 17}, + {name: "legacy zero size", text: "TEXT ·StructFieldB(SB), $0-0"}, + {name: "omitted argument size", text: "TEXT ·StructFieldB(SB), $0"}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + file := &plan9asm.File{Funcs: []plan9asm.Func{{ + Sym: "·StructFieldB", + ArgSize: test.argSize, + Instrs: []plan9asm.Instr{{Op: plan9asm.OpTEXT, Raw: test.text}}, + }}} + err := validateDeclaredTextArgSizes(file, resolve, declared, "386") + var mismatch *asmABINotApplicableError + if test.wantErr { + if !errors.As(err, &mismatch) { + t.Fatalf("validateDeclaredTextArgSizes() error = %v, want asmABINotApplicableError", err) + } + if mismatch.Symbol != "example.com/ext.StructFieldB" || mismatch.DeclaredArgSize != test.argSize || mismatch.ExpectedArgSize != 17 || mismatch.Goarch != "386" { + t.Fatalf("mismatch = %#v", mismatch) + } + return + } + if err != nil { + t.Fatalf("validateDeclaredTextArgSizes() error = %v", err) + } + }) + } +} + +func TestTryDeclSigDoesNotPadVoidArgumentFrame(t *testing.T) { + tests := []struct { + name string + goarch string + params []types.Type + results []types.Type + want int64 + }{ + {name: "amd64 uint32 void", goarch: "amd64", params: []types.Type{types.Typ[types.Uint32]}, want: 4}, + {name: "arm64 uint32 void", goarch: "arm64", params: []types.Type{types.Typ[types.Uint32]}, want: 4}, + {name: "amd64 slice and uint32 void", goarch: "amd64", params: []types.Type{types.NewSlice(types.Typ[types.Byte]), types.Typ[types.Uint32]}, want: 28}, + {name: "amd64 uint32 result remains word aligned", goarch: "amd64", params: []types.Type{types.Typ[types.Uint32]}, results: []types.Type{types.Typ[types.Uint32]}, want: 12}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + pkg := types.NewPackage("example.com/frame", "frame") + vars := func(items []types.Type) *types.Tuple { + out := make([]*types.Var, len(items)) + for i, item := range items { + out[i] = types.NewParam(token.NoPos, pkg, "", item) + } + return types.NewTuple(out...) + } + sig := types.NewSignatureType(nil, nil, nil, vars(test.params), vars(test.results), false) + pkg.Scope().Insert(types.NewFunc(token.NoPos, pkg, "frame", sig)) + _, got, ok, err := tryDeclSig(pkg.Scope(), "·frame", pkg.Path()+".frame", nil, test.goarch, types.SizesFor("gc", test.goarch)) + if err != nil { + t.Fatal(err) + } + if !ok { + t.Fatal("tryDeclSig did not find declaration") + } + if got != test.want { + t.Fatalf("TEXT argument size = %d, want %d", got, test.want) + } + }) + } +} + +func TestReadAsmSourceExpandsLocalIncludesRecursively(t *testing.T) { + dir := t.TempDir() + write := func(name, contents string) { + t.Helper() + if err := os.WriteFile(filepath.Join(dir, name), []byte(contents), 0o600); err != nil { + t.Fatal(err) + } + } + write("ops.h", "#define STEP(a, b) ADDQ a, b\n") + write("macros.h", "#include \"ops.h\"\n#define ROUND(a, b) STEP(a, b)\n") + write("macro_amd64.s", "#include \"textflag.h\"\n#include \"macros.h\"\nTEXT ·macro(SB),NOSPLIT,$0-0\nROUND(AX, BX)\nRET\n") + + src, err := readAsmSource(filepath.Join(dir, "macro_amd64.s"), dir) + if err != nil { + t.Fatal(err) + } + if strings.Contains(string(src), `#include "macros.h"`) || !strings.Contains(string(src), "#define STEP") { + t.Fatalf("local include was not expanded:\n%s", src) + } + if strings.Contains(string(src), `#include "textflag.h"`) || !strings.Contains(string(src), "#define NOSPLIT") { + t.Fatalf("standard textflag.h was not expanded from GOROOT:\n%s", src) + } + file, err := plan9asm.Parse(plan9asm.ArchAMD64, string(src)) + if err != nil { + t.Fatal(err) + } + if got := file.Funcs[0].Instrs[1].Op; got != plan9asm.Op("ADDQ") { + t.Fatalf("expanded opcode = %s, want ADDQ", got) + } +} + +func TestReadAsmSourceExpandsStandardFuncdataMacros(t *testing.T) { + dir := t.TempDir() + asm := filepath.Join(dir, "macro_amd64.s") + src := `#include "funcdata.h" +TEXT ·macro(SB),NOSPLIT,$0-0 +GO_ARGS +GO_RESULTS_INITIALIZED +NO_LOCAL_POINTERS +RET +` + if err := os.WriteFile(asm, []byte(src), 0o600); err != nil { + t.Fatal(err) + } + expanded, err := readAsmSource(asm, dir) + if err != nil { + t.Fatal(err) + } + if strings.Contains(string(expanded), `#include "funcdata.h"`) || !strings.Contains(string(expanded), "#define GO_ARGS") { + t.Fatalf("standard funcdata.h was not expanded from GOROOT:\n%s", expanded) + } + file, err := plan9asm.Parse(plan9asm.ArchAMD64, string(expanded)) + if err != nil { + t.Fatal(err) + } + var got []plan9asm.Op + for _, ins := range file.Funcs[0].Instrs { + got = append(got, ins.Op) + } + want := []plan9asm.Op{"TEXT", "FUNCDATA", "PCDATA", "FUNCDATA", plan9asm.OpRET} + if !reflect.DeepEqual(got, want) { + t.Fatalf("expanded funcdata ops = %v, want %v", got, want) + } +} + +func TestReadAsmSourceResolvesGoIncludePathRelativeToPkgInclude(t *testing.T) { + dir := t.TempDir() + asm := filepath.Join(dir, "tls_386.s") + if err := os.WriteFile(asm, []byte("#include \"../../src/runtime/go_tls.h\"\nTEXT ·tls(SB),NOSPLIT,$0-0\nRET\n"), 0o600); err != nil { + t.Fatal(err) + } + expanded, err := readAsmSource(asm, dir) + if err != nil { + t.Fatal(err) + } + if strings.Contains(string(expanded), `#include "../../src/runtime/go_tls.h"`) || !strings.Contains(string(expanded), "get_tls") { + t.Fatalf("GOROOT-relative runtime header was not expanded:\n%s", expanded) + } +} + +func TestExtractSupportedOpsFindsCompleteAddedInstructionFamilies(t *testing.T) { + repoRoot, err := filepath.Abs(filepath.Join("..", "..")) + if err != nil { + t.Fatal(err) + } + supported, err := extractSupportedOps(repoRoot, "amd64") + if err != nil { + t.Fatal(err) + } + want := []string{ + "MOVD", "VMOVD", "VMOVQ", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "UD2", + "CVTSL2SS", "CVTSL2SD", "CVTSQ2SS", "CVTSQ2SD", "CVTPL2PS", "CVTPL2PD", + "VBROADCASTSS", "VBROADCASTSD", + "PMULDQ", "PMULULQ", "VPMULDQ", "VPMULUDQ", + "MOVDDUP", "MOVSHDUP", "MOVSLDUP", + "VMOVDDUP", "VMOVSHDUP", "VMOVSLDUP", + "PMULLD", "VPMULLD", + "PMULLW", "PMULHW", "PMULHUW", "PMULHRSW", + "VPMULLW", "VPMULHW", "VPMULHUW", "VPMULHRSW", + "PMADDWL", "VPMADDWD", "PMADDUBSW", "VPMADDUBSW", + "VPDPBUSD", "VPDPBUSDS", "VPDPWSSD", "VPDPWSSDS", + "PAVGB", "PAVGW", "VPAVGB", "VPAVGW", + "PCMPGTB", "PCMPGTW", "PCMPGTL", "PCMPGTQ", + "PSRAW", "PSRAL", "VPSRAW", "VPSRAD", "VPSRAQ", + "VPMINSB", "VPMINUB", "VPMAXSB", "VPMAXUB", + "VPMINSW", "VPMINUW", "VPMAXSW", "VPMAXUW", + "VPMINSD", "VPMINUD", "VPMAXSD", "VPMAXUD", + "VPMINSQ", "VPMINUQ", "VPMAXSQ", "VPMAXUQ", + "SHUFPS", "SHUFPD", "VSHUFPS", "VSHUFPD", + "PBLENDW", "BLENDPS", "BLENDPD", "VPBLENDW", "VPBLENDD", "VBLENDPS", "VBLENDPD", + "PUNPCKLBW", "PUNPCKHBW", "PUNPCKLWL", "PUNPCKHWL", + "PUNPCKLLQ", "PUNPCKHLQ", "PUNPCKLQDQ", "PUNPCKHQDQ", + "VPUNPCKLBW", "VPUNPCKHBW", "VPUNPCKLWD", "VPUNPCKHWD", + "VPUNPCKLDQ", "VPUNPCKHDQ", "VPUNPCKLQDQ", "VPUNPCKHQDQ", + "UNPCKLPS", "UNPCKHPS", "UNPCKLPD", "UNPCKHPD", + "VUNPCKLPS", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKHPD", + "VPERMQ", "VPERMPD", + "VPERMILPD", "VPERMILPS", + "VMOVAPD", "VMOVAPS", "VMOVUPD", "VMOVUPS", + "VMOVDQA32", "VMOVDQA64", "VMOVDQU8", "VMOVDQU16", "VMOVDQU32", "VMOVDQU64", + "MOVNTO", "MOVNTPD", "MOVNTPS", "MOVNTDQA", + "VMOVNTDQ", "VMOVNTPD", "VMOVNTPS", "VMOVNTDQA", + "MOVNTQ", "MOVNTDQ", "MOVQOZX", "MOVDQ2Q", "PSHUFW", + "VINSERTF128", "VINSERTI128", + "VINSERTF32X4", "VINSERTF64X2", "VINSERTI32X4", "VINSERTI64X2", + "VINSERTF32X8", "VINSERTF64X4", "VINSERTI32X8", "VINSERTI64X4", + "PSHUFB", "VPSHUFB", + "ADDSUBPS", "ADDSUBPD", "VADDSUBPS", "VADDSUBPD", + "VCVTDQ2PS", "VCVTPS2DQ", "VCVTTPS2DQ", "VSQRTPD", "VSQRTPS", + "PMOVSXBW", "PMOVSXBD", "PMOVSXBQ", "PMOVSXWD", "PMOVSXWQ", "PMOVSXDQ", + "VPMOVSXBW", "VPMOVSXBD", "VPMOVSXBQ", "VPMOVSXWD", "VPMOVSXWQ", "VPMOVSXDQ", + "PMOVZXBW", "PMOVZXBD", "PMOVZXBQ", "PMOVZXWD", "PMOVZXWQ", "PMOVZXDQ", + "VPMOVZXBW", "VPMOVZXBD", "VPMOVZXBQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMOVZXDQ", + "PHADDD", "PHADDSW", "PHADDW", "PHSUBD", "PHSUBSW", "PHSUBW", + "VPHADDD", "VPHADDSW", "VPHADDW", "VPHSUBD", "VPHSUBSW", "VPHSUBW", + "PHMINPOSUW", "VPHMINPOSUW", + "MASKMOVQ", "MASKMOVOU", "MASKMOVDQU", "VMASKMOVDQU", + "JCXZW", "JCXZL", "JCXZQ", + "PALIGNR", "VPALIGNR", + "PCLMULQDQ", "VPCLMULQDQ", + "PSLLO", "PSLLDQ", "PSRLO", "PSRLDQ", "VPSLLDQ", "VPSRLDQ", + "RCLB", "RCLW", "RCLL", "RCLQ", "RCRB", "RCRW", "RCRL", "RCRQ", + "PSHUFHW", "PSHUFLW", "VPSHUFHW", "VPSHUFLW", + "AESENC", "AESENCLAST", "AESDEC", "AESDECLAST", "AESIMC", "AESKEYGENASSIST", + "VAESENC", "VAESENCLAST", "VAESDEC", "VAESDECLAST", "VAESIMC", "VAESKEYGENASSIST", + "CVTSS2SL", "CVTSS2SQ", "CVTSD2SL", "CVTSD2SQ", + "CVTTSS2SL", "CVTTSS2SQ", "CVTTSD2SL", "CVTTSD2SQ", + "VCVTSS2SI", "VCVTSS2SIQ", "VCVTSD2SI", "VCVTSD2SIQ", + "VCVTTSS2SI", "VCVTTSS2SIQ", "VCVTTSD2SI", "VCVTTSD2SIQ", + "VCVTSS2USIL", "VCVTSS2USIQ", "VCVTSD2USIL", "VCVTSD2USIQ", + "VCVTTSS2USIL", "VCVTTSS2USIQ", "VCVTTSD2USIL", "VCVTTSD2USIQ", + "ROUNDPS", "ROUNDPD", "ROUNDSS", "ROUNDSD", + "VROUNDPS", "VROUNDPD", "VROUNDSS", "VROUNDSD", + "DPPD", "DPPS", "VDPPD", "VDPPS", + "BOUNDW", "BOUNDL", + "CLC", "STC", "CMC", + "PUSHW", "PUSHL", "PUSHQ", "POPW", "POPL", "POPQ", + "PUSHFW", "PUSHFL", "PUSHFQ", "POPFW", "POPFL", "POPFQ", + "PSLLW", "PSLLL", "PSLLQ", "PSRLW", "PSRLL", "PSRLQ", + "VPSLLW", "VPSLLD", "VPSLLQ", "VPSRLW", "VPSRLD", "VPSRLQ", + "PMULLW", "PMULHW", "PMULHUW", "PMULHRSW", + "VPMULLW", "VPMULHW", "VPMULHUW", "VPMULHRSW", + "LDMXCSR", "VLDMXCSR", "STMXCSR", "VSTMXCSR", + "CVTPS2PL", "CVTTPS2PL", "CVTPS2PD", "VCVTPS2PD", + "RCPPS", "RSQRTPS", "VRCPPS", "VRSQRTPS", + "RCPSS", "RSQRTSS", "VRCPSS", "VRSQRTSS", + "PCMPESTRI", "PCMPESTRM", "PCMPISTRI", "PCMPISTRM", + "VPCMPESTRI", "VPCMPESTRM", "VPCMPISTRI", "VPCMPISTRM", + "KUNPCKBW", "KUNPCKWD", "KUNPCKDQ", + "VRCP14PS", "VRCP14PD", "VRCP14SS", "VRCP14SD", + "VRSQRT14PS", "VRSQRT14PD", "VRSQRT14SS", "VRSQRT14SD", + "VEXP2PS", "VEXP2PD", + "VRCP28PS", "VRCP28PD", "VRCP28SS", "VRCP28SD", + "VRSQRT28PS", "VRSQRT28PD", "VRSQRT28SS", "VRSQRT28SD", + "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VP4DPWSSD", "VP4DPWSSDS", + "VPCMPEQB", "VPCMPEQW", "VPCMPEQD", "VPCMPEQQ", + "VPCMPGTB", "VPCMPGTW", "VPCMPGTD", "VPCMPGTQ", + "VPTESTMB", "VPTESTMW", "VPTESTMD", "VPTESTMQ", + "VPTESTNMB", "VPTESTNMW", "VPTESTNMD", "VPTESTNMQ", + "PTEST", "VPTEST", "VTESTPD", "VTESTPS", + "VPCONFLICTD", "VPCONFLICTQ", + "VBLENDMPS", "VBLENDMPD", + "VEXPANDPD", "VEXPANDPS", "VPEXPANDB", "VPEXPANDW", "VPEXPANDD", "VPEXPANDQ", + "PAND", "PANDN", "POR", "PXOR", "VPANDN", "VPANDND", "VPANDNQ", + "VPBROADCASTB", "VPBROADCASTW", "VPBROADCASTD", "VPBROADCASTQ", + "VPBROADCASTMB2Q", "VPBROADCASTMW2D", + "PADDB", "PADDL", "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB", "PADDUSW", "PADDW", + "VPADDB", "VPADDD", "VPADDQ", "VPADDSB", "VPADDSW", "VPADDUSB", "VPADDUSW", "VPADDW", + "PSUBB", "PSUBL", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW", + "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB", "VPSUBSW", "VPSUBUSB", "VPSUBUSW", "VPSUBW", + "PSADBW", "VPSADBW", "MPSADBW", "VMPSADBW", "VDBPSADBW", + "PINSRB", "PINSRW", "PINSRD", "PINSRQ", + "VPINSRB", "VPINSRW", "VPINSRD", "VPINSRQ", + "VPMOVDB", "VPMOVDW", "VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVWB", + "VPMOVSDB", "VPMOVSDW", "VPMOVSQB", "VPMOVSQD", "VPMOVSQW", "VPMOVSWB", + "VPMOVUSDB", "VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW", "VPMOVUSWB", + "EXTRACTPS", "VEXTRACTPS", "VEXTRACTF128", "VEXTRACTI128", + "VEXTRACTF32X4", "VEXTRACTF64X2", "VEXTRACTI32X4", "VEXTRACTI64X2", + "VEXTRACTF32X8", "VEXTRACTF64X4", "VEXTRACTI32X8", "VEXTRACTI64X4", + "PEXTRB", "PEXTRW", "PEXTRD", "PEXTRQ", + "VPEXTRB", "VPEXTRW", "VPEXTRD", "VPEXTRQ", + "MOVHLPS", "MOVLHPS", "VMOVHLPS", "VMOVLHPS", + "MOVHPS", "MOVLPS", "MOVHPD", "MOVLPD", "VMOVHPS", "VMOVLPS", "VMOVHPD", "VMOVLPD", + "LDDQU", "VLDDQU", + "POPCNTW", "POPCNTL", "POPCNTQ", + "NOTB", "NOTW", "NOTL", "NOTQ", + "PDEPL", "PDEPQ", "PEXTL", "PEXTQ", + "BTW", "BTL", "BTQ", "BTCW", "BTCL", "BTCQ", + "BTRW", "BTRL", "BTRQ", "BTSW", "BTSL", "BTSQ", + "RDMSR", "WRMSR", + "VMRUN", "VMMCALL", "VMLOAD", "VMSAVE", "STGI", "CLGI", "SKINIT", "INVLPGA", + "LGDT", "LIDT", "SGDT", "SIDT", + "LLDT", "LTR", "LMSW", + "LARW", "LARL", "LARQ", "LSLW", "LSLL", "LSLQ", + "VERR", "VERW", + "LFSW", "LFSL", "LFSQ", "LGSW", "LGSL", "LGSQ", "LSSW", "LSSL", "LSSQ", + "FXSAVE", "FXSAVE64", "FXRSTOR", "FXRSTOR64", + "XSAVE", "XSAVE64", "XSAVEOPT", "XSAVEOPT64", "XSAVEC", "XSAVEC64", "XSAVES", "XSAVES64", + "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", + "RDFSBASEL", "RDFSBASEQ", "RDGSBASEL", "RDGSBASEQ", + "WRFSBASEL", "WRFSBASEQ", "WRGSBASEL", "WRGSBASEQ", + "SLDTW", "SLDTL", "SLDTQ", + "SMSWW", "SMSWL", "SMSWQ", + "STRW", "STRL", "STRQ", + "CLFLUSH", "CLFLUSHOPT", "CLWB", + "CLDEMOTE", "INVLPG", "INVPCID", + "MONITOR", "MWAIT", "RDPMC", "RDPKRU", "WRPKRU", "XSETBV", "UMONITOR", "UMWAIT", "TPAUSE", + "XBEGIN", "XABORT", "XEND", "XTEST", + "CLAC", "CLI", "CLTS", "ENDBR64", "ICEBP", "INVD", "RSM", "STAC", "STI", "SWAPGS", "UD1", "WBINVD", + "IRETW", "IRETL", "IRETQ", "RETFW", "RETFL", "RETFQ", + "SYSENTER", "SYSENTER64", "SYSEXIT", "SYSEXIT64", "SYSRET", + "LEAVEW", "LEAVEL", "LEAVEQ", "XLAT", + "XADDB", "XADDW", "XADDL", "XADDQ", + "XCHGB", "XCHGW", "XCHGL", "XCHGQ", + "NEGB", "NEGW", "NEGL", "NEGQ", + "SARXL", "SARXQ", "SHLXL", "SHLXQ", "SHRXL", "SHRXQ", + "BEXTRL", "BEXTRQ", "BZHIL", "BZHIQ", + "CRC32B", "CRC32W", "CRC32L", "CRC32Q", + "CMPSB", "CMPSW", "CMPSL", "CMPSQ", + "LODSB", "LODSW", "LODSL", "LODSQ", + "NOPW", "NOPL", + "MOVBEW", "MOVBEL", "MOVBEQ", + "MOVNTIL", "MOVNTIQ", + "CBW", "CWDE", "CDQE", "CWD", "CDQ", "CQO", + "FCMOVCC", "FCMOVCS", "FCMOVEQ", "FCMOVHI", "FCMOVLS", + "FCMOVB", "FCMOVBE", "FCMOVNB", "FCMOVNBE", "FCMOVE", "FCMOVNE", "FCMOVNU", "FCMOVU", "FCMOVUN", + "LEAW", "LEAL", "LEAQ", + "LZCNTW", "LZCNTL", "LZCNTQ", + "ADCXL", "ADCXQ", "ADOXL", "ADOXQ", + "CMPXCHGB", "CMPXCHGW", "CMPXCHGL", "CMPXCHGQ", "CMPXCHG8B", "CMPXCHG16B", + "TZCNTW", "TZCNTL", "TZCNTQ", + "CMPPD", "CMPPS", "CMPSD", "CMPSS", "VCMPPD", "VCMPPS", "VCMPSD", "VCMPSS", + "PACKSSLW", "PACKSSWB", "PACKUSDW", "PACKUSWB", + "VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB", + "VPERMD", "VPERMPS", + "SETCC", "SETCS", "SETEQ", "SETGE", "SETGT", "SETHI", "SETLE", "SETLS", + "SETLT", "SETMI", "SETNE", "SETOC", "SETOS", "SETPC", "SETPL", "SETPS", + "VMOVSD", "VMOVSS", + "VCOMISD", "VCOMISS", "VUCOMISD", "VUCOMISS", + "INCB", "INCW", "INCL", "INCQ", "DECB", "DECW", "DECL", "DECQ", + "MOVBWSX", "MOVBWZX", "MOVBLSX", "MOVBLZX", "MOVBQSX", "MOVBQZX", + "MOVWLSX", "MOVWLZX", "MOVWQSX", "MOVWQZX", "MOVLQSX", "MOVLQZX", + "MOVSWW", "MOVZWW", + "KMOVB", "KMOVW", "KMOVD", "KMOVQ", + "KADDB", "KADDW", "KADDD", "KADDQ", + "KSHIFTLB", "KSHIFTLW", "KSHIFTLD", "KSHIFTLQ", + "KSHIFTRB", "KSHIFTRW", "KSHIFTRD", "KSHIFTRQ", + "VGATHERDPS", "VGATHERQPD", "VPGATHERDD", "VPGATHERQQ", + "VGATHERDPD", "VPGATHERDQ", "VGATHERQPS", "VPGATHERQD", + "VGATHERPF0DPD", "VGATHERPF0DPS", "VGATHERPF0QPD", "VGATHERPF0QPS", + "VGATHERPF1DPD", "VGATHERPF1DPS", "VGATHERPF1QPD", "VGATHERPF1QPS", + "VSCATTERPF0DPD", "VSCATTERPF0DPS", "VSCATTERPF0QPD", "VSCATTERPF0QPS", + "VSCATTERPF1DPD", "VSCATTERPF1DPS", "VSCATTERPF1QPD", "VSCATTERPF1QPS", + "VPTERNLOGD", "VPTERNLOGQ", + "VALIGND", "VALIGNQ", + "VPMADD52HUQ", "VPMADD52LUQ", + "VPSHLDW", "VPSHLDD", "VPSHLDQ", "VPSHLDVW", "VPSHLDVD", "VPSHLDVQ", + "VPSHRDW", "VPSHRDD", "VPSHRDQ", "VPSHRDVW", "VPSHRDVD", "VPSHRDVQ", + "VPROLD", "VPROLQ", "VPROLVD", "VPROLVQ", + "VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", + "VPANDD", "VPANDQ", "VPANDND", "VPANDNQ", + "VPORD", "VPORQ", "VPXORD", "VPXORQ", + "ANDPS", "ANDPD", "ANDNPS", "ANDNPD", "ORPS", "ORPD", "XORPS", "XORPD", + "VANDPS", "VANDPD", "VANDNPS", "VANDNPD", "VORPS", "VORPD", "VXORPS", "VXORPD", + "HADDPS", "HADDPD", "HSUBPS", "HSUBPD", "VHADDPS", "VHADDPD", "VHSUBPS", "VHSUBPD", + "PABSB", "PABSW", "PABSD", "VPABSB", "VPABSW", "VPABSD", "VPABSQ", + "PSIGNB", "PSIGNW", "PSIGND", "VPSIGNB", "VPSIGNW", "VPSIGND", + "VCVTPH2PS", "VCVTPS2PH", + "CVTPD2PL", "CVTTPD2PL", "VCVTDQ2PD", + "VCVTPD2DQ", "VCVTPD2DQX", "VCVTPD2DQY", + "VCVTTPD2DQ", "VCVTTPD2DQX", "VCVTTPD2DQY", + "VSQRTSS", "VSQRTSD", + "VCVTSI2SDL", "VCVTSI2SDQ", "VCVTSI2SSL", "VCVTSI2SSQ", + "VCVTUSI2SDL", "VCVTUSI2SDQ", "VCVTUSI2SSL", "VCVTUSI2SSQ", + "FMOVB", "FMOVBP", "FMOVD", "FMOVDP", "FMOVF", "FMOVFP", "FMOVL", "FMOVLP", + "FMOVV", "FMOVVP", "FMOVW", "FMOVWP", "FMOVX", "FMOVXP", + "FCOMD", "FCOMDP", "FCOMDPP", "FCOMF", "FCOMFP", "FCOMI", "FCOMIP", + "FCOML", "FCOMLP", "FCOMW", "FCOMWP", "FUCOM", "FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP", + "FBLD", "FBSTP", "FLDCW", "FLDENV", "FRSTOR", "FSAVE", "FSTCW", "FSTENV", "FSTSW", + "F2XM1", "FABS", "FCHS", "FCLEX", "FCOS", "FDECSTP", "FINCSTP", "FINIT", + "FLD1", "FLDL2E", "FLDL2T", "FLDLG2", "FLDLN2", "FLDPI", "FLDZ", "FNOP", + "FPATAN", "FPREM", "FPREM1", "FPTAN", "FRNDINT", "FSCALE", "FSIN", "FSINCOS", + "FSQRT", "FTST", "FXAM", "FXTRACT", "FYL2X", "FYL2XP1", "FXCHD", "LAHF", "SAHF", + } + for _, stem := range []string{"FADD", "FMUL", "FSUB", "FSUBR", "FDIV", "FDIVR"} { + for _, suffix := range []string{"W", "L", "F", "D", "DP"} { + want = append(want, stem+suffix) + } + } + for _, stem := range []string{"ROL", "ROR", "SAR", "SAL", "SHL", "SHR"} { + for _, width := range []string{"B", "W", "L", "Q"} { + want = append(want, stem+width) + } + } + for _, stem := range []string{"KAND", "KANDN", "KOR", "KXNOR", "KXOR", "KNOT", "KTEST", "KORTEST"} { + for _, width := range []string{"B", "W", "D", "Q"} { + want = append(want, stem+width) + } + } + for _, family := range []string{"VFMADD", "VFMSUB", "VFNMADD", "VFNMSUB", "VFMADDSUB", "VFMSUBADD"} { + for _, order := range []string{"132", "213", "231"} { + for _, element := range []string{"PS", "PD"} { + want = append(want, family+order+element) + } + if family != "VFMADDSUB" && family != "VFMSUBADD" { + for _, element := range []string{"SS", "SD"} { + want = append(want, family+order+element) + } + } + } + } + for _, family := range []string{"VADD", "VSUB", "VMUL", "VDIV", "VMAX", "VMIN"} { + for _, element := range []string{"PS", "PD", "SS", "SD"} { + want = append(want, family+element) + } + } + for _, width := range []string{"W", "L", "Q"} { + for _, condition := range []string{"CC", "CS", "EQ", "GE", "GT", "HI", "LE", "LS", "LT", "MI", "NE", "OC", "OS", "PC", "PL", "PS"} { + want = append(want, "CMOV"+width+condition) + } + } + for _, op := range want { + if _, ok := supported[op]; !ok { + t.Errorf("supported opcode extraction omitted %s", op) + } + } + for _, op := range []string{ + "VPOPCNTB", "VPOPCNTW", "VPOPCNTD", "VPOPCNTQ", + "VPLZCNTD", "VPLZCNTQ", + "VGF2P8MULB", "VGF2P8AFFINEQB", "VGF2P8AFFINEINVQB", + "VPERMB", "VPERMW", + "VPERMI2B", "VPERMI2W", "VPERMI2D", "VPERMI2Q", "VPERMI2PS", "VPERMI2PD", + "VPERMT2B", "VPERMT2W", "VPERMT2D", "VPERMT2Q", "VPERMT2PS", "VPERMT2PD", + "VPMULTISHIFTQB", "VPSHUFBITQMB", + "VRANGEPS", "VRANGEPD", "VRANGESS", "VRANGESD", + "VMASKMOVPS", "VMASKMOVPD", "VPMASKMOVD", "VPMASKMOVQ", + "VFPCLASSPDX", "VFPCLASSPDY", "VFPCLASSPDZ", + "VFPCLASSPSX", "VFPCLASSPSY", "VFPCLASSPSZ", "VFPCLASSSD", "VFPCLASSSS", + "VGETEXPPS", "VGETEXPPD", "VGETEXPSS", "VGETEXPSD", + "VGETMANTPS", "VGETMANTPD", "VGETMANTSS", "VGETMANTSD", + "VFIXUPIMMPS", "VFIXUPIMMPD", "VFIXUPIMMSS", "VFIXUPIMMSD", + "VRNDSCALEPS", "VRNDSCALEPD", "VRNDSCALESS", "VRNDSCALESD", + "VREDUCEPS", "VREDUCEPD", "VREDUCESS", "VREDUCESD", + "VSCALEFPS", "VSCALEFPD", "VSCALEFSS", "VSCALEFSD", + "VCVTPD2QQ", "VCVTPD2UQQ", "VCVTTPD2QQ", "VCVTTPD2UQQ", + "VCVTPS2QQ", "VCVTPS2UQQ", "VCVTTPS2QQ", "VCVTTPS2UQQ", + "VCVTPS2UDQ", "VCVTTPS2UDQ", "VCVTUDQ2PS", "VCVTUDQ2PD", + "VCVTPD2UDQ", "VCVTPD2UDQX", "VCVTPD2UDQY", + "VCVTTPD2UDQ", "VCVTTPD2UDQX", "VCVTTPD2UDQY", + "VCVTQQ2PD", "VCVTUQQ2PD", "VCVTQQ2PS", "VCVTQQ2PSX", "VCVTQQ2PSY", + "VCVTUQQ2PS", "VCVTUQQ2PSX", "VCVTUQQ2PSY", + "VCOMPRESSPS", "VCOMPRESSPD", "VPCOMPRESSB", "VPCOMPRESSW", "VPCOMPRESSD", "VPCOMPRESSQ", + "VBROADCASTF128", "VBROADCASTI128", + } { + if _, ok := supported[op]; !ok { + t.Errorf("supported opcode extraction omitted %s", op) + } + } + arm64Supported, err := extractSupportedOps(repoRoot, "arm64") + if err != nil { + t.Fatal(err) + } + for _, op := range []string{ + "ADR", "ADRP", + "VFCVTNS", "VFCVTNU", "VFCVTMS", "VFCVTMU", "VFCVTAS", "VFCVTAU", "VFCVTPS", "VFCVTPU", "VFCVTZS", "VFCVTZU", + "VZIP1", "VZIP2", "VUZP1", "VUZP2", "VTRN1", "VTRN2", + "VUSHLL", "VUSHLL2", "VSSHLL", "VSSHLL2", + "VUXTL", "VUXTL2", "VSXTL", "VSXTL2", + "SXTB", "SXTBW", "SXTH", "SXTHW", "SXTW", + "UXTB", "UXTBW", "UXTH", "UXTHW", "UXTW", + "VCNT", + "VUADDW", "VUADDW2", + } { + if _, ok := arm64Supported[op]; !ok { + t.Errorf("ARM64 supported opcode extraction omitted %s", op) + } + } +} + +func TestExtractSupportedOpsFindsPackageLevelSpecTableWithoutOpcodeName(t *testing.T) { + dir := t.TempDir() + if err := os.WriteFile(filepath.Join(dir, "amd64_table.go"), []byte(`package sample +var packedFamilySpecs = map[string]int{ + "VTABLEOP": 1, +} +`), 0o600); err != nil { + t.Fatal(err) + } + if err := os.WriteFile(filepath.Join(dir, "translate.go"), []byte("package sample\n"), 0o600); err != nil { + t.Fatal(err) + } + supported, err := extractSupportedOps(dir, "amd64") + if err != nil { + t.Fatal(err) + } + if _, ok := supported["VTABLEOP"]; !ok { + t.Fatal("package-level table-driven opcode was not extracted") + } +} + +func TestExplicitSingleTargetUsesMatrixReport(t *testing.T) { + tests := []struct { + name string + allTargets bool + targets string + reports int + want bool + }{ + {name: "legacy-default-single", reports: 1, want: false}, + {name: "explicit-single", targets: "linux/amd64", reports: 1, want: true}, + {name: "explicit-multiple", targets: "linux/amd64,windows/amd64", reports: 2, want: true}, + {name: "all-targets", allTargets: true, reports: 9, want: true}, + } + for _, test := range tests { + t.Run(test.name, func(t *testing.T) { + if got := useMatrixReport(test.allTargets, test.targets, test.reports); got != test.want { + t.Fatalf("useMatrixReport(%v, %q, %d) = %v, want %v", test.allTargets, test.targets, test.reports, got, test.want) + } + }) + } +} + +func TestExtractSupportedOpsFindsCompleteARM64AddedFamilies(t *testing.T) { + repoRoot, err := filepath.Abs(filepath.Join("..", "..")) + if err != nil { + t.Fatal(err) + } + supported, err := extractSupportedOps(repoRoot, "arm64") + if err != nil { + t.Fatal(err) + } + for _, op := range []string{ + "FABSS", "FABSD", "FNEGS", "FNEGD", "FSQRTS", "FSQRTD", "FMOVS", "FMOVD", + "FCVTSD", "FCVTDS", "FCVTSH", "FCVTHS", "FCVTDH", "FCVTHD", + "FRINTNS", "FRINTND", "FRINTPS", "FRINTPD", "FRINTMS", "FRINTMD", + "FRINTZS", "FRINTZD", "FRINTAS", "FRINTAD", "FRINTXS", "FRINTXD", "FRINTIS", "FRINTID", + "FMADDS", "FMADDD", "FMSUBS", "FMSUBD", "FNMADDS", "FNMADDD", "FNMSUBS", "FNMSUBD", + "SCVTFD", "SCVTFS", "SCVTFWD", "SCVTFWS", "UCVTFD", "UCVTFS", "UCVTFWD", "UCVTFWS", + "FADDS", "FADDD", "FSUBS", "FSUBD", "FMULS", "FMULD", "FNMULS", "FNMULD", "FDIVS", "FDIVD", + "FMAXS", "FMAXD", "FMINS", "FMIND", "FMAXNMS", "FMAXNMD", "FMINNMS", "FMINNMD", + "CASPW", "CASPD", + "LDXPW", "LDXP", "LDAXPW", "LDAXP", + "STXPW", "STXP", "STLXPW", "STLXP", + "VADDV", "VSMAX", "VSMIN", "VUMAX", "VUMIN", "VSMAXP", "VSMINP", "VUMAXP", "VUMINP", + "VABS", "VNEG", "VSQABS", "VSQNEG", + "VSSHR", "VSSRA", "VSRSHR", "VSRSRA", "VUSHR", "VUSRA", "VURSHR", "VURSRA", + "VSQSHRN", "VSQSHRN2", "VSQRSHRN", "VSQRSHRN2", + "VSQSHRUN", "VSQSHRUN2", "VSQRSHRUN", "VSQRSHRUN2", + "VUQSHRN", "VUQSHRN2", "VUQRSHRN", "VUQRSHRN2", + "VXTN", "VXTN2", "VSQXTN", "VSQXTN2", "VSQXTUN", "VSQXTUN2", "VUQXTN", "VUQXTN2", + "VSHADD", "VSRHADD", "VUHADD", "VURHADD", + "VSQADD", "VUQADD", "VSQSUB", "VUQSUB", + "VSMULL", "VSMULL2", "VSMLAL", "VSMLAL2", "VSMLSL", "VSMLSL2", + "VUMULL", "VUMULL2", "VUMLAL", "VUMLAL2", "VUMLSL", "VUMLSL2", + "VMUL", "VMLA", "VMLS", + "VCMHI", "VCMHS", + "VSMAXV", "VSMINV", "VUMAXV", "VUMINV", + "VFMAXV", "VFMINV", "VFMAXNMV", "VFMINNMV", + "VLD1", "VLD2", "VLD3", "VLD4", "VLD1R", "VLD2R", "VLD3R", "VLD4R", "VST1", "VST2", "VST3", "VST4", + "VMOVS", "VMOVD", "VMOVQ", "VDUP", "VADD", "VSUB", + "VCLS", "VCLZ", + "VEXT", + "VEOR3", "VBCAX", "VRAX1", "VXAR", + "SHA1C", "SHA1P", "SHA1M", "SHA1H", "SHA1SU0", "SHA1SU1", + "SHA256H", "SHA256H2", "SHA256SU0", "SHA256SU1", + "SHA512H", "SHA512H2", "SHA512SU0", "SHA512SU1", + "VSHL", "VSSHL", "VSRSHL", "VUSHL", "VURSHL", + "ZAND", "ZBIC", "ZEOR", "ZORR", + "ZSUB", "ZSUBR", "ZSQADD", "ZSQSUB", "ZSQSUBR", "ZUQADD", "ZUQSUB", "ZUQSUBR", + "ZASR", "ZLSL", + "ZFADD", "ZFSUB", "ZFSUBR", + "ZCMPEQ", "ZCMPGE", "ZCMPGT", "ZCMPHI", "ZCMPHS", "ZCMPNE", + "ZFACGE", "ZFACGT", "ZFCMEQ", "ZFCMGE", "ZFCMGT", "ZFCMLE", "ZFCMLT", "ZFCMNE", "ZFCMUO", + "ZSMAX", "ZSMAXP", "ZSMAXQV", "ZSMAXVB", "ZSMAXVH", "ZSMAXVS", "ZSMAXVD", + "ZSMIN", "ZSMINP", "ZSMINQV", "ZSMINVB", "ZSMINVH", "ZSMINVS", "ZSMINVD", + "ZUMAX", "ZUMAXP", "ZUMAXQV", "ZUMAXVB", "ZUMAXVH", "ZUMAXVS", "ZUMAXVD", + "ZUMIN", "ZUMINP", "ZUMINQV", "ZUMINVB", "ZUMINVH", "ZUMINVS", "ZUMINVD", + "ZADDQV", "ZANDQV", "ZANDVB", "ZANDVH", "ZANDVS", "ZANDVD", + "ZEORQV", "ZEORVB", "ZEORVH", "ZEORVS", "ZEORVD", + "ZORQV", "ZORVB", "ZORVH", "ZORVS", "ZORVD", + "ZFADDAD", "ZFADDAH", "ZFADDAS", "ZFADDQV", "ZFADDVD", "ZFADDVH", "ZFADDVS", + "ZSADDVD", "ZUADDVD", + "ZADDHNB", "ZADDHNT", "ZRADDHNB", "ZRADDHNT", "ZSUBHNB", "ZSUBHNT", "ZRSUBHNB", "ZRSUBHNT", + "ZSADDLB", "ZSADDLBT", "ZSADDLT", "ZSADDWB", "ZSADDWT", + "ZSSUBLB", "ZSSUBLBT", "ZSSUBLT", "ZSSUBLTB", "ZSSUBWB", "ZSSUBWT", + "ZUADDLB", "ZUADDLT", "ZUADDWB", "ZUADDWT", "ZUSUBLB", "ZUSUBLT", "ZUSUBWB", "ZUSUBWT", + "ZSABA", "ZUABA", "ZSABD", "ZUABD", + "ZSABALB", "ZSABALT", "ZUABALB", "ZUABALT", + "ZSABDLB", "ZSABDLT", "ZUABDLB", "ZUABDLT", "ZSADALP", "ZUADALP", + "ZSHADD", "ZSRHADD", "ZUHADD", "ZURHADD", "ZSHSUB", "ZSHSUBR", "ZUHSUB", "ZUHSUBR", + "ZSDIV", "ZSDIVR", "ZUDIV", "ZUDIVR", + "ZBCAX", "ZBSL", "ZBSL1N", "ZBSL2N", "ZEOR3", "ZNBSL", + "ZBDEP", "ZBEXT", "ZBGRP", + "ZADCLB", "ZADCLT", "ZSBCLB", "ZSBCLT", + "ZSCLAMP", "ZUCLAMP", "ZFCLAMP", "ZBFCLAMP", + "ZSUNPKHI", "ZSUNPKLO", "ZUUNPKHI", "ZUUNPKLO", + "ZSQXTNB", "ZSQXTNT", "ZSQXTUNB", "ZSQXTUNT", "ZUQXTNB", "ZUQXTNT", + "ZSHRNB", "ZSHRNT", "ZRSHRNB", "ZRSHRNT", + "ZSQSHRNB", "ZSQSHRNT", "ZSQRSHRNB", "ZSQRSHRNT", + "ZSQSHRUNB", "ZSQSHRUNT", "ZSQRSHRUNB", "ZSQRSHRUNT", + "ZUQSHRNB", "ZUQSHRNT", "ZUQRSHRNB", "ZUQRSHRNT", + "ZSQRSHL", "ZSQRSHLR", "ZSQSHLR", "ZUQRSHL", "ZUQRSHLR", "ZUQSHLR", + "ZSRSHL", "ZSRSHLR", "ZURSHL", "ZURSHLR", + "ZFMAX", "ZFMAXP", "ZFMAXQV", "ZFMAXVH", "ZFMAXVS", "ZFMAXVD", + "ZFMIN", "ZFMINP", "ZFMINQV", "ZFMINVH", "ZFMINVS", "ZFMINVD", + "ZFMAXNM", "ZFMAXNMP", "ZFMAXNMQV", "ZFMAXNMVH", "ZFMAXNMVS", "ZFMAXNMVD", + "ZFMINNM", "ZFMINNMP", "ZFMINNMQV", "ZFMINNMVH", "ZFMINNMVS", "ZFMINNMVD", + "ZFABS", "ZFNEG", "ZFRECPE", "ZFRECPX", "ZFRSQRTE", "ZFSQRT", + "ZFRINT32X", "ZFRINT32Z", "ZFRINT64X", "ZFRINT64Z", + "ZFRINTA", "ZFRINTI", "ZFRINTM", "ZFRINTN", "ZFRINTP", "ZFRINTX", "ZFRINTZ", + "ZABS", "ZCLS", "ZCLZ", "ZCNOT", "ZCNT", "ZNEG", "ZNOT", "ZRBIT", + "ZREV", "ZREVB", "ZREVH", "ZREVW", + "PAND", "PANDS", "PBIC", "PBICS", "PEOR", "PEORS", "PNAND", "PNANDS", + "PNOR", "PNORS", "PORN", "PORNS", "PORR", "PORRS", + "PBRKA", "PBRKAS", "PBRKB", "PBRKBS", "PBRKN", "PBRKNS", + "PBRKPA", "PBRKPAS", "PBRKPB", "PBRKPBS", + "PREV", "PTRN1", "PTRN2", "PUZP1", "PUZP2", "PZIP1", "PZIP2", + "PPUNPKHI", "PPUNPKLO", + "PSEL", + "PPFALSE", "PPTEST", + "PRDFFR", "PRDFFRS", "PWRFFR", "SETFFR", + "PPFIRST", "PPNEXT", + "PFIRSTP", "PLASTP", + "PPTRUE", "PCNTP", "PPEXT", + "PWHILEGE", "PWHILEGT", "PWHILEHI", "PWHILEHS", + "PWHILELE", "PWHILELO", "PWHILELS", "PWHILELT", + "PWHILEGEW", "PWHILEGTW", "PWHILEHIW", "PWHILEHSW", + "PWHILELEW", "PWHILELOW", "PWHILELSW", "PWHILELTW", + "PWHILERW", "PWHILEWR", + "PDECP", "PINCP", "PSQDECP", "PSQDECPW", "PSQINCP", "PSQINCPW", + "PUQDECP", "PUQDECPW", "PUQINCP", "PUQINCPW", + "PLDR", "PSTR", "PPRFB", "PPRFH", "PPRFW", "PPRFD", + "ZLDR", "ZSTR", + "ZPRFB", "ZPRFH", "ZPRFW", "ZPRFD", + "ZLDNT1B", "ZLDNT1H", "ZLDNT1W", "ZLDNT1D", "ZLDNT1SB", "ZLDNT1SH", "ZLDNT1SW", + "ZSTNT1B", "ZSTNT1H", "ZSTNT1W", "ZSTNT1D", + "ZLDFF1B", "ZLDFF1H", "ZLDFF1W", "ZLDFF1D", "ZLDFF1SB", "ZLDFF1SH", "ZLDFF1SW", + "ZLDNF1B", "ZLDNF1H", "ZLDNF1W", "ZLDNF1D", "ZLDNF1SB", "ZLDNF1SH", "ZLDNF1SW", + "ZLD1RB", "ZLD1RH", "ZLD1RW", "ZLD1RD", "ZLD1RSB", "ZLD1RSH", "ZLD1RSW", + "ZLD1ROB", "ZLD1ROH", "ZLD1ROW", "ZLD1ROD", "ZLD1RQB", "ZLD1RQH", "ZLD1RQW", "ZLD1RQD", + "CTERMEQ", "CTERMEQW", "CTERMNE", "CTERMNEW", + "ZLD1B", "ZLD1H", "ZLD1W", "ZLD1D", "ZLD1Q", "ZLD1SB", "ZLD1SH", "ZLD1SW", + "ZST1B", "ZST1H", "ZST1W", "ZST1D", "ZST1Q", + "ZLD2B", "ZLD2H", "ZLD2W", "ZLD2D", "ZLD2Q", + "ZLD3B", "ZLD3H", "ZLD3W", "ZLD3D", "ZLD3Q", + "ZLD4B", "ZLD4H", "ZLD4W", "ZLD4D", "ZLD4Q", + "ZST2B", "ZST2H", "ZST2W", "ZST2D", "ZST2Q", + "ZST3B", "ZST3H", "ZST3W", "ZST3D", "ZST3Q", + "ZST4B", "ZST4H", "ZST4W", "ZST4D", "ZST4Q", + "ZPMOV", + "ZINDEX", "ZINDEXW", + "ZINSR", "ZINSRW", "ZINSRB", "ZINSRH", "ZINSRS", "ZINSRD", + "ZLASTA", "ZLASTAW", "ZLASTAB", "ZLASTAH", "ZLASTAS", "ZLASTAD", + "ZLASTB", "ZLASTBW", "ZLASTBB", "ZLASTBH", "ZLASTBS", "ZLASTBD", + "ZCLASTA", "ZCLASTAW", "ZCLASTAB", "ZCLASTAH", "ZCLASTAS", "ZCLASTAD", + "ZCLASTB", "ZCLASTBW", "ZCLASTBB", "ZCLASTBH", "ZCLASTBS", "ZCLASTBD", + "ZCOMPACT", + "ZMOVPRFX", + "ZEXT", "ZEXTQ", "ZSPLICE", + "ZCPY", "ZCPYW", "ZCPYB", "ZCPYH", "ZCPYS", "ZCPYD", + "ZFCVT", "ZFCVTZS", "ZFCVTZU", "ZSCVTF", "ZUCVTF", + "ZFCVTLT", "ZFCVTX", "ZFCVTXNT", + "ZSQABS", "ZSQNEG", "ZSXTB", "ZSXTH", "ZSXTW", + "ZUXTB", "ZUXTH", "ZUXTW", "ZURECPE", "ZURSQRTE", + "ZSMULH", "ZUMULH", + "ZSQSHL", "ZUQSHL", + "ZFMUL", "ZFMULX", "ZFTMAD", "ZFTSMUL", "ZFTSSEL", "ZFCMLA", "ZFMLA", "ZFMLS", "ZFMAD", "ZFMSB", + "ZFNMLA", "ZFNMLS", "ZFNMAD", "ZFNMSB", "ZMLA", "ZMLS", + "ZSQDMULH", "ZSQRDMULH", + "ZPMUL", "ZPMULL", "ZPMULLB", "ZPMULLT", "ZPMLAL", + "ZSMULLB", "ZSMULLT", "ZUMULLB", "ZUMULLT", "ZSQDMULLB", "ZSQDMULLT", + "ZSQDMLALB", "ZSQDMLALT", "ZSQDMLALBT", "ZSQDMLSLB", "ZSQDMLSLT", "ZSQDMLSLBT", + "ZSMMLA", "ZUMMLA", "ZUSMMLA", "ZBFMMLA", "ZFMMLA", + "ZADDP", "ZADDPT", "ZSUBPT", + "ZDECP", "ZINCP", "ZSQDECP", "ZSQINCP", "ZUQDECP", "ZUQINCP", + "ZSSHLLB", "ZSSHLLT", "ZUSHLLB", "ZUSHLLT", + "ZFRECPS", "ZFRSQRTS", + "ZFABD", "ZFADDP", "ZFAMAX", "ZFAMIN", + "ZMATCH", "ZNMATCH", + "ZHISTCNT", "ZHISTSEG", + "ZMADPT", "ZMLAPT", + "ZCADD", "ZSQCADD", + "ZXAR", + "ZEXPAND", + "ZFEXPA", "ZFLOGB", + "ZFCPY", "ZFDUP", + "ZFDIV", "ZFDIVR", "ZFSCALE", + "ZSUQADD", "ZUSQADD", + "ZFCADD", + "ZDUPW", + "ZDUPQ", + "ZDUPM", + "ZFDOT", + "ZCDOT", + "ZLUTI2", "ZLUTI4", + "ZFMLALB", "ZFMLALT", "ZFMLSLB", "ZFMLSLT", + "ZFMLALLBB", "ZFMLALLBT", "ZFMLALLTB", "ZFMLALLTT", + "ZSQCVTN", "ZSQCVTUN", "ZUQCVTN", + "ZSQRSHRN", "ZSQRSHRUN", "ZUQRSHRN", + "ZBF1CVT", "ZBF1CVTLT", "ZBF2CVT", "ZBF2CVTLT", + "ZF1CVT", "ZF1CVTLT", "ZF2CVT", "ZF2CVTLT", + "ZBFCVT", "ZBFCVTN", "ZBFCVTNT", "ZFCVTN", "ZFCVTNB", "ZFCVTNT", + "ZBFADD", "ZBFSUB", "ZBFMUL", "ZBFMAX", "ZBFMAXNM", "ZBFMIN", "ZBFMINNM", "ZBFSCALE", + "ZBFMLA", "ZBFMLS", "ZBFMLALB", "ZBFMLALT", "ZBFMLSLB", "ZBFMLSLT", + "ZAESD", "ZAESDIMC", "ZAESE", "ZAESEMC", + "ZRAX1", "ZSM4E", "ZSM4EKEY", + "ZASRD", "ZASRR", "ZLSLR", "ZLSRR", "ZSLI", "ZSRI", "ZSRSHR", "ZSRSRA", "ZSSRA", "ZURSHR", "ZURSRA", "ZUSRA", "ZSQSHLU", + "ZCMLA", "ZSQRDCMLAH", + "ZSQRDMLAH", "ZSQRDMLSH", + "ZADR", + "RBIT", "RBITW", "CLZ", "CLZW", "CLS", "CLSW", + "BIC", "BICW", "BICS", "BICSW", "ADDS", "ADDSW", + "FCMPS", "FCMPD", "FCMPES", "FCMPED", + "FCCMPS", "FCCMPD", "FCCMPES", "FCCMPED", + "DMB", "DSB", "ISB", "DC", "PRFM", "RPRFM", "BRK", "UNDEF", "HINT", "YIELD", "WFE", "WFI", "SEV", "SEVL", "NOP", + } { + if _, ok := supported[op]; !ok { + t.Errorf("supported opcode extraction omitted %s", op) + } + } + for _, suboperation := range []string{"IVAC", "CIGDVADP", "PLDL1KEEP", "PSTL3STRM"} { + if _, ok := supported[suboperation]; ok { + t.Errorf("supported opcode extraction advertised %s suboperation as an instruction", suboperation) + } + } +} + +func TestExtractSupportedOpsFindsCompleteARMAddedFamilies(t *testing.T) { + repoRoot, err := filepath.Abs(filepath.Join("..", "..")) + if err != nil { + t.Fatal(err) + } + supported, err := extractSupportedOps(repoRoot, "arm") + if err != nil { + t.Fatal(err) + } + for _, op := range []string{ + "MOVF", "MOVD", + "NEGF", "NEGD", "ABSF", "ABSD", "SQRTF", "SQRTD", "MOVFD", "MOVDF", "CMPF", "CMPD", + "ADDF", "ADDD", "SUBF", "SUBD", "MULF", "MULD", "NMULF", "NMULD", "DIVF", "DIVD", + "MULAF", "MULAD", "MULSF", "MULSD", "NMULAF", "NMULAD", "NMULSF", "NMULSD", + "FMULAF", "FMULAD", "FMULSF", "FMULSD", "FNMULAF", "FNMULAD", "FNMULSF", "FNMULSD", + "MOVWF", "MOVWD", "MOVFW", "MOVDW", "PLD", + "DIV", "DIVU", "MOD", "MODU", + } { + if _, ok := supported[op]; !ok { + t.Errorf("supported opcode extraction omitted %s", op) + } + } +} + +func TestExtractSupportedOpsFindsCompleteWasmFloatUnaryFamily(t *testing.T) { + repoRoot, err := filepath.Abs(filepath.Join("..", "..")) + if err != nil { + t.Fatal(err) + } + supported, err := extractSupportedOps(repoRoot, "wasm") + if err != nil { + t.Fatal(err) + } + for _, width := range []string{"F32", "F64"} { + for _, operation := range []string{"ABS", "NEG", "CEIL", "FLOOR", "TRUNC", "NEAREST", "SQRT"} { + op := width + operation + if _, ok := supported[op]; !ok { + t.Errorf("supported opcode extraction omitted %s", op) + } + } + } +} + func TestAsmFilesOfPkgSkipsCommentOnlyAssembly(t *testing.T) { dir := t.TempDir() comments := filepath.Join(dir, "comments.s") @@ -34,6 +1379,33 @@ func TestAsmFilesOfPkgSkipsCommentOnlyAssembly(t *testing.T) { } } +func TestCollectAsmTasksHonorsExactModuleRelativeAllowlist(t *testing.T) { + dir := t.TempDir() + pkgDir := filepath.Join(dir, "pkg") + if err := os.MkdirAll(pkgDir, 0o755); err != nil { + t.Fatal(err) + } + amd64File := filepath.Join(pkgDir, "fast.s") + arm64File := filepath.Join(pkgDir, "portable.s") + for _, path := range []string{amd64File, arm64File} { + if err := os.WriteFile(path, []byte("TEXT ·f(SB),0,$0-0\nRET\n"), 0o600); err != nil { + t.Fatal(err) + } + } + pkg := &packages.Package{ + PkgPath: "example.com/root/pkg", + OtherFiles: []string{amd64File, arm64File}, + Module: &packages.Module{Path: "example.com/root", Dir: dir}, + } + tasks, packages := collectAsmTasks([]*packages.Package{pkg}, "/out", []string{"pkg/portable.s"}) + if len(tasks) != 1 || tasks[0].AsmFile != arm64File { + t.Fatalf("collectAsmTasks() tasks = %#v, want only %s", tasks, arm64File) + } + if !reflect.DeepEqual(packages, []string{"example.com/root/pkg"}) { + t.Fatalf("collectAsmTasks() packages = %#v", packages) + } +} + func TestFilterPackagesByModuleExcludesNestedModules(t *testing.T) { pkgs := []*packages.Package{ {PkgPath: "example.com/root/pkg", Module: &packages.Module{Path: "example.com/root"}}, @@ -126,9 +1498,9 @@ func TestLLVMArgsAndFrameSlotsForTupleSliceResultFlatten(t *testing.T) { t.Fatalf("args mismatch: %#v", args) } wantSlots := []plan9asm.FrameSlot{ - {Offset: 0, Type: plan9asm.Ptr, Index: 0, Field: -1}, - {Offset: 8, Type: plan9asm.I64, Index: 1, Field: -1}, - {Offset: 16, Type: plan9asm.I64, Index: 2, Field: -1}, + {Offset: 0, Type: plan9asm.Ptr, Index: 0, Field: -1, Name: "r"}, + {Offset: 8, Type: plan9asm.I64, Index: 1, Field: -1, Name: "r"}, + {Offset: 16, Type: plan9asm.I64, Index: 2, Field: -1, Name: "r"}, } if !reflect.DeepEqual(slots, wantSlots) { t.Fatalf("slots mismatch: got=%#v want=%#v", slots, wantSlots) @@ -161,3 +1533,163 @@ func TestLLVMArgsAndFrameSlotsForTupleInterfaceParam(t *testing.T) { t.Fatalf("nextOff mismatch: got=%d want=16", nextOff) } } + +func TestLLVMArgsAndFrameSlotsForTupleNamedInterfaceParam(t *testing.T) { + iface := types.NewInterfaceType(nil, nil) + iface.Complete() + named := types.NewNamed(types.NewTypeName(token.NoPos, nil, "Reader", nil), iface, nil) + tup := types.NewTuple(types.NewVar(token.NoPos, nil, "v", named)) + sz := types.SizesFor("gc", "amd64") + args, slots, _, err := llvmArgsAndFrameSlotsForTuple(tup, "amd64", sz, 0, false) + if err != nil { + t.Fatal(err) + } + if !reflect.DeepEqual(args, []plan9asm.LLVMType{"{ ptr, ptr }"}) { + t.Fatalf("args mismatch: %#v", args) + } + wantSlots := []plan9asm.FrameSlot{ + {Offset: 0, Type: plan9asm.Ptr, Index: 0, Field: 0}, + {Offset: 8, Type: plan9asm.Ptr, Index: 0, Field: 1}, + } + if !reflect.DeepEqual(slots, wantSlots) { + t.Fatalf("slots mismatch: got=%#v want=%#v", slots, wantSlots) + } +} + +func TestLLVMArgsAndFrameSlotsForNestedAggregateParam(t *testing.T) { + slice := types.NewSlice(types.Typ[types.Byte]) + array := types.NewArray(slice, 2) + tup := types.NewTuple(types.NewVar(token.NoPos, nil, "blocks", array)) + sz := types.SizesFor("gc", "amd64") + args, slots, nextOff, err := llvmArgsAndFrameSlotsForTuple(tup, "amd64", sz, 0, false) + if err != nil { + t.Fatal(err) + } + if !reflect.DeepEqual(args, []plan9asm.LLVMType{"[2 x { ptr, i64, i64 }]"}) { + t.Fatalf("args mismatch: %#v", args) + } + wantSlots := []plan9asm.FrameSlot{ + {Offset: 0, Type: plan9asm.Ptr, Index: 0, Field: 0, Fields: []int{0, 0}}, + {Offset: 8, Type: plan9asm.I64, Index: 0, Field: 0, Fields: []int{0, 1}}, + {Offset: 16, Type: plan9asm.I64, Index: 0, Field: 0, Fields: []int{0, 2}}, + {Offset: 24, Type: plan9asm.Ptr, Index: 0, Field: 1, Fields: []int{1, 0}}, + {Offset: 32, Type: plan9asm.I64, Index: 0, Field: 1, Fields: []int{1, 1}}, + {Offset: 40, Type: plan9asm.I64, Index: 0, Field: 1, Fields: []int{1, 2}}, + } + if !reflect.DeepEqual(slots, wantSlots) { + t.Fatalf("slots mismatch: got=%#v want=%#v", slots, wantSlots) + } + if nextOff != 48 { + t.Fatalf("nextOff mismatch: got=%d want=48", nextOff) + } +} + +func TestLLVMArgsAndFrameSlotsForStructParam(t *testing.T) { + st := types.NewStruct([]*types.Var{ + types.NewVar(token.NoPos, nil, "A", types.NewArray(types.Typ[types.Uint16], 3)), + types.NewVar(token.NoPos, nil, "B", types.Typ[types.Byte]), + types.NewVar(token.NoPos, nil, "C", types.Typ[types.String]), + }, nil) + tup := types.NewTuple(types.NewVar(token.NoPos, nil, "v", st)) + sz := types.SizesFor("gc", "amd64") + args, slots, nextOff, err := llvmArgsAndFrameSlotsForTuple(tup, "amd64", sz, 0, false) + if err != nil { + t.Fatal(err) + } + if !reflect.DeepEqual(args, []plan9asm.LLVMType{"{ [3 x i16], i8, { ptr, i64 } }"}) { + t.Fatalf("args mismatch: %#v", args) + } + wantSlots := []plan9asm.FrameSlot{ + {Offset: 0, Type: plan9asm.I16, Index: 0, Field: 0, Fields: []int{0, 0}}, + {Offset: 2, Type: plan9asm.I16, Index: 0, Field: 0, Fields: []int{0, 1}}, + {Offset: 4, Type: plan9asm.I16, Index: 0, Field: 0, Fields: []int{0, 2}}, + {Offset: 6, Type: plan9asm.I8, Index: 0, Field: 1}, + {Offset: 8, Type: plan9asm.Ptr, Index: 0, Field: 2, Fields: []int{2, 0}}, + {Offset: 16, Type: plan9asm.I64, Index: 0, Field: 2, Fields: []int{2, 1}}, + } + if !reflect.DeepEqual(slots, wantSlots) { + t.Fatalf("slots mismatch: got=%#v want=%#v", slots, wantSlots) + } + if nextOff != 24 { + t.Fatalf("nextOff mismatch: got=%d want=24", nextOff) + } +} + +func TestLLVMArgsAndFrameSlotsFlattensArrayResult(t *testing.T) { + array := types.NewArray(types.Typ[types.Byte], 7) + tup := types.NewTuple(types.NewVar(token.NoPos, nil, "result", array)) + sz := types.SizesFor("gc", "amd64") + args, slots, nextOff, err := llvmArgsAndFrameSlotsForTuple(tup, "amd64", sz, 0, true) + if err != nil { + t.Fatal(err) + } + wantArgs := []plan9asm.LLVMType{ + plan9asm.I8, plan9asm.I8, plan9asm.I8, plan9asm.I8, + plan9asm.I8, plan9asm.I8, plan9asm.I8, + } + if !reflect.DeepEqual(args, wantArgs) { + t.Fatalf("args mismatch: got=%#v want=%#v", args, wantArgs) + } + for i, slot := range slots { + want := plan9asm.FrameSlot{Offset: int64(i), Type: plan9asm.I8, Index: i, Field: -1, Name: "result"} + if !reflect.DeepEqual(slot, want) { + t.Fatalf("slot %d = %#v, want %#v", i, slot, want) + } + } + if nextOff != 7 { + t.Fatalf("nextOff mismatch: got=%d want=7", nextOff) + } +} + +func TestLLVMArgsAndFrameSlotsForComplexParamsAndResults(t *testing.T) { + for _, goarch := range []string{"386", "amd64", "arm", "arm64"} { + t.Run(goarch, func(t *testing.T) { + tup := types.NewTuple( + types.NewVar(token.NoPos, nil, "c64", types.Typ[types.Complex64]), + types.NewVar(token.NoPos, nil, "c128", types.Typ[types.Complex128]), + ) + sz := types.SizesFor("gc", goarch) + args, slots, nextOff, err := llvmArgsAndFrameSlotsForTuple(tup, goarch, sz, 0, false) + if err != nil { + t.Fatal(err) + } + wantArgs := []plan9asm.LLVMType{"{ float, float }", "{ double, double }"} + if !reflect.DeepEqual(args, wantArgs) { + t.Fatalf("parameter args mismatch: got=%#v want=%#v", args, wantArgs) + } + wantSlots := []plan9asm.FrameSlot{ + {Offset: 0, Type: plan9asm.LLVMType("float"), Index: 0, Field: 0}, + {Offset: 4, Type: plan9asm.LLVMType("float"), Index: 0, Field: 1}, + {Offset: 8, Type: plan9asm.LLVMType("double"), Index: 1, Field: 0}, + {Offset: 16, Type: plan9asm.LLVMType("double"), Index: 1, Field: 1}, + } + if !reflect.DeepEqual(slots, wantSlots) { + t.Fatalf("parameter slots mismatch: got=%#v want=%#v", slots, wantSlots) + } + if nextOff != 24 { + t.Fatalf("parameter nextOff = %d, want 24", nextOff) + } + + results, resultSlots, resultEnd, err := llvmArgsAndFrameSlotsForTuple(tup, goarch, sz, 0, true) + if err != nil { + t.Fatal(err) + } + wantResults := []plan9asm.LLVMType{"float", "float", "double", "double"} + if !reflect.DeepEqual(results, wantResults) { + t.Fatalf("flattened result args mismatch: got=%#v want=%#v", results, wantResults) + } + wantResultSlots := []plan9asm.FrameSlot{ + {Offset: 0, Type: plan9asm.LLVMType("float"), Index: 0, Field: -1, Name: "c64"}, + {Offset: 4, Type: plan9asm.LLVMType("float"), Index: 1, Field: -1, Name: "c64"}, + {Offset: 8, Type: plan9asm.LLVMType("double"), Index: 2, Field: -1, Name: "c128"}, + {Offset: 16, Type: plan9asm.LLVMType("double"), Index: 3, Field: -1, Name: "c128"}, + } + if !reflect.DeepEqual(resultSlots, wantResultSlots) { + t.Fatalf("result slots mismatch: got=%#v want=%#v", resultSlots, wantResultSlots) + } + if resultEnd != 24 { + t.Fatalf("result nextOff = %d, want 24", resultEnd) + } + }) + } +} diff --git a/cmd/plan9asmll/modern_x86_raw_test.go b/cmd/plan9asmll/modern_x86_raw_test.go new file mode 100644 index 00000000..d8ee36e6 --- /dev/null +++ b/cmd/plan9asmll/modern_x86_raw_test.go @@ -0,0 +1,70 @@ +package main + +import ( + "fmt" + "strings" + "testing" + + plan9asm "github.com/xgo-dev/plan9asm" +) + +func TestModernX86RawAVX2DirectiveStreamDecodesAtInstructionBoundaries(t *testing.T) { + // This is the complete AVX2 register-setup sequence used by the BLAKE2b + // assembly shared by golang.org/x/crypto and many go-ethereum forks. Each + // instruction addresses registers or memory through general registers; none + // of them is PC-relative. + code := []byte{ + 0xc5, 0x7a, 0x7e, 0x26, + 0xc5, 0x7a, 0x7e, 0x5e, 0x20, + 0xc4, 0x63, 0x99, 0x22, 0x66, 0x10, 0x01, + 0xc4, 0x63, 0xa1, 0x22, 0x5e, 0x30, 0x01, + } + var source strings.Builder + source.WriteString("TEXT rawAVX2(SB), NOSPLIT, $0-0\n") + for _, value := range code { + fmt.Fprintf(&source, "\tBYTE $%#02x\n", value) + } + source.WriteString("\tRET\n") + + file, err := plan9asm.Parse(plan9asm.ArchAMD64, source.String()) + if err != nil { + t.Fatal(err) + } + if _, err := plan9asm.Translate(file, plan9asm.Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]plan9asm.FuncSig{ + "rawAVX2": {Name: "rawAVX2", Ret: plan9asm.Void}, + }, + }); err != nil { + t.Fatalf("Translate() error = %v", err) + } +} + +func TestModernX86RawCRC32WidthIsPreserved(t *testing.T) { + // 66 f2 0f 38 f1 /r is the register/memory 16-bit CRC32 form. The + // architecture decoder names every width CRC32, so plan9asm must restore + // the Plan 9 width suffix before operand-form validation. + const source = `TEXT rawCRC32W(SB), NOSPLIT, $0-0 + BYTE $0x66 + BYTE $0xf2 + BYTE $0x0f + BYTE $0x38 + BYTE $0xf1 + BYTE $0x06 + RET +` + file, err := plan9asm.Parse(plan9asm.ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + if _, err := plan9asm.Translate(file, plan9asm.Options{ + Goarch: "amd64", + TargetTriple: "x86_64-unknown-linux-gnu", + Sigs: map[string]plan9asm.FuncSig{ + "rawCRC32W": {Name: "rawCRC32W", Ret: plan9asm.Void}, + }, + }); err != nil { + t.Fatalf("Translate() error = %v", err) + } +} diff --git a/cmd/plan9asmll/testdata/testsignature/convert_test.go b/cmd/plan9asmll/testdata/testsignature/convert_test.go new file mode 100644 index 00000000..16588176 --- /dev/null +++ b/cmd/plan9asmll/testdata/testsignature/convert_test.go @@ -0,0 +1,3 @@ +package testsignature + +func convert(byte) float32 diff --git a/cmd/plan9asmll/testdata/testsignature/convert_test_amd64.s b/cmd/plan9asmll/testdata/testsignature/convert_test_amd64.s new file mode 100644 index 00000000..abea3ba2 --- /dev/null +++ b/cmd/plan9asmll/testdata/testsignature/convert_test_amd64.s @@ -0,0 +1,3 @@ +TEXT ·convert(SB),$0-12 + MOVSS X0, ret+8(FP) + RET diff --git a/cmd/plan9asmll/testdata/testsignature/package.go b/cmd/plan9asmll/testdata/testsignature/package.go new file mode 100644 index 00000000..bc9ac3b2 --- /dev/null +++ b/cmd/plan9asmll/testdata/testsignature/package.go @@ -0,0 +1 @@ +package testsignature diff --git a/cmd/plan9asmscan/main.go b/cmd/plan9asmscan/main.go index b6bb6c90..2a6cafe6 100644 --- a/cmd/plan9asmscan/main.go +++ b/cmd/plan9asmscan/main.go @@ -7,6 +7,9 @@ import ( "errors" "flag" "fmt" + "go/ast" + "go/parser" + "go/token" "io" "os" "os/exec" @@ -14,6 +17,7 @@ import ( "regexp" "runtime" "sort" + "strconv" "strings" "github.com/xgo-dev/plan9asm" @@ -143,7 +147,6 @@ type conformanceManifest struct { } var ( - reCaseClause = regexp.MustCompile(`case\s+([^:]+):`) reOpcodeName = regexp.MustCompile("(?m)^\\s*(?:obj\\.A_ARCHSPECIFIC:\\s*)?\"([A-Z][A-Za-z0-9.]*)\",\\s*$") ) @@ -365,26 +368,35 @@ func scanPackages(pkgs []pkgJSON, arch plan9asm.Arch, goarch string) (map[string continue } for _, fn := range file.Funcs { - for _, ins := range fn.Instrs { + for i := 0; i < len(fn.Instrs); { + ins := fn.Instrs[i] if ins.Op == plan9asm.OpLABEL { + i++ + continue + } + if isX86RawDirective(arch, ins) { + end := i + 1 + for end < len(fn.Instrs) && isX86RawDirective(arch, fn.Instrs[end]) { + end++ + } + sequence := fn.Instrs[i:end] + probeErr := plan9asm.ProbeInstructionSequence(arch, goarch, sequence) + probeKey := instructionSequenceProbeKey(sequence) + for _, raw := range sequence { + addFormStatWithProbeResult(forms, arch, goarch, raw, rel, probeKey, probeErr) + addOpStat(ops, string(raw.Op), rel, p.ImportPath, 1) + } + i = end continue } nop := normalizeOp(string(ins.Op)) if nop == "" { + i++ continue } addFormStat(forms, arch, goarch, ins, rel) - s := ops[nop] - if s == nil { - s = &opStat{ - Files: map[string]int{}, - Pkgs: map[string]int{}, - } - ops[nop] = s - } - s.Count++ - s.Files[rel]++ - s.Pkgs[p.ImportPath]++ + addOpStat(ops, nop, rel, p.ImportPath, 1) + i++ } } if len(file.Data) > 0 { @@ -399,9 +411,26 @@ func scanPackages(pkgs []pkgJSON, arch plan9asm.Arch, goarch string) (map[string } func addFormStat(forms map[string]*formStat, arch plan9asm.Arch, goarch string, ins plan9asm.Instr, file string) { + probeKey := fmt.Sprintf("%s %#v", ins.Op, ins.Args) + st, fresh := prepareFormStat(forms, arch, goarch, ins, file, probeKey) + if st == nil || !fresh { + return + } + classifyFormProbe(st, plan9asm.ProbeInstruction(arch, goarch, ins)) +} + +func addFormStatWithProbeResult(forms map[string]*formStat, arch plan9asm.Arch, goarch string, ins plan9asm.Instr, file, probeKey string, probeErr error) { + st, fresh := prepareFormStat(forms, arch, goarch, ins, file, probeKey) + if st == nil || !fresh { + return + } + classifyFormProbe(st, probeErr) +} + +func prepareFormStat(forms map[string]*formStat, arch plan9asm.Arch, goarch string, ins plan9asm.Instr, file, probeKey string) (*formStat, bool) { desc := plan9asm.DescribeInstruction(arch, goarch, ins) if desc.Opcode == "" || desc.Opcode == string(plan9asm.OpLABEL) { - return + return nil, false } st := forms[desc.Form] if st == nil { @@ -421,12 +450,14 @@ func addFormStat(forms map[string]*formStat, arch plan9asm.Arch, goarch string, // Descriptor forms intentionally collapse concrete register numbers and // immediate values. Those values can still select different lowerer paths, // so cache exact instructions and aggregate their outcomes into the form. - probeKey := fmt.Sprintf("%s %#v", ins.Op, ins.Args) if _, ok := st.ProbeKeys[probeKey]; ok { - return + return st, false } st.ProbeKeys[probeKey] = struct{}{} - err := plan9asm.ProbeInstruction(arch, goarch, ins) + return st, true +} + +func classifyFormProbe(st *formStat, err error) { switch { case err == nil: st.SupportedCount++ @@ -440,6 +471,27 @@ func addFormStat(forms map[string]*formStat, arch plan9asm.Arch, goarch string, } } +func isX86RawDirective(arch plan9asm.Arch, ins plan9asm.Instr) bool { + if arch != plan9asm.ArchAMD64 { + return false + } + switch normalizeOp(string(ins.Op)) { + case "BYTE", "WORD", "LONG", "QUAD": + return true + default: + return false + } +} + +func instructionSequenceProbeKey(instrs []plan9asm.Instr) string { + var b strings.Builder + b.WriteString("sequence") + for _, ins := range instrs { + fmt.Fprintf(&b, " %s %#v;", ins.Op, ins.Args) + } + return b.String() +} + func scanGoAssemblerTestdata(goroot string, arch plan9asm.Arch, goarch string) (map[string]*opStat, map[string]*formStat, []parseErr, int, error) { files, err := goAssemblerTestdataFiles(goroot, goarch) if err != nil { @@ -770,58 +822,171 @@ func extractSupportedOps(repoRoot, goarch string) (map[string]struct{}, error) { "PCDATA": {}, } - seen := map[string]struct{}{} - var files []string loweringArch := goarch if loweringArch == "386" { loweringArch = "amd64" } - patterns := []string{ - filepath.Join(repoRoot, loweringArch+"_*.go"), - filepath.Join(repoRoot, "parser.go"), + files, err := filepath.Glob(filepath.Join(repoRoot, loweringArch+"_*.go")) + if err != nil { + return nil, err } - for _, pattern := range patterns { - matches, err := filepath.Glob(pattern) - if err != nil { - return nil, err - } - sort.Strings(matches) - for _, match := range matches { - if strings.HasSuffix(match, "_test.go") { - continue - } - if _, ok := seen[match]; ok { - continue - } - seen[match] = struct{}{} - files = append(files, match) - } + parserPath := filepath.Join(repoRoot, "parser.go") + if _, err := os.Stat(parserPath); err == nil { + files = append(files, parserPath) + } else if !errors.Is(err, os.ErrNotExist) { + return nil, fmt.Errorf("stat %s: %w", parserPath, err) } + sort.Strings(files) for _, f := range files { + if strings.HasSuffix(f, "_test.go") { + continue + } src, err := os.ReadFile(f) if err != nil { return nil, fmt.Errorf("read %s: %w", f, err) } - for _, m := range reCaseClause.FindAllSubmatch(src, -1) { - items := strings.Split(string(m[1]), ",") - for _, item := range items { - item = strings.TrimSpace(item) - switch { - case strings.HasPrefix(item, "\"") && strings.HasSuffix(item, "\"") && len(item) >= 2: - if op := normalizeOp(strings.Trim(item, "\"")); op != "" { - supported[op] = struct{}{} + parsed, err := parser.ParseFile(token.NewFileSet(), f, src, 0) + if err != nil { + return nil, fmt.Errorf("parse %s for supported instructions: %w", f, err) + } + for _, decl := range parsed.Decls { + gen, ok := decl.(*ast.GenDecl) + if !ok || gen.Tok != token.VAR { + continue + } + for _, declared := range gen.Specs { + spec, ok := declared.(*ast.ValueSpec) + if !ok { + continue + } + for _, value := range spec.Values { + literal, ok := value.(*ast.CompositeLit) + if ok { + collectSupportedOpcodeMap(supported, literal) } - case strings.HasPrefix(item, "Op"): - if op := normalizeOp(strings.TrimPrefix(item, "Op")); op != "" { + } + } + } + ast.Inspect(parsed, func(node ast.Node) bool { + // A single-family lowerer often starts with `if op != "VEXT"` rather + // than a switch. This is an implementation-backed support claim just + // like an opcode switch case. Only accept a literal compared directly + // with an identifier named op so unrelated strings cannot leak into + // the supported-instruction inventory. + if comparison, ok := node.(*ast.BinaryExpr); ok && + (comparison.Op == token.EQL || comparison.Op == token.NEQ) { + if candidate, ok := opcodeComparedWithOp(comparison.X, comparison.Y); ok { + if op := normalizeOp(candidate); op != "" { supported[op] = struct{}{} } } } - } + if spec, ok := node.(*ast.ValueSpec); ok { + for i, name := range spec.Names { + if !strings.Contains(strings.ToLower(name.Name), "op") || len(spec.Values) == 0 { + continue + } + valueIndex := i + if len(spec.Values) == 1 { + valueIndex = 0 + } + if valueIndex >= len(spec.Values) { + continue + } + literal, ok := spec.Values[valueIndex].(*ast.CompositeLit) + if !ok { + continue + } + mapType, isMap := literal.Type.(*ast.MapType) + keyType, stringKeyed := mapTypeKeyIdent(mapType) + if !isMap || !stringKeyed || keyType != "string" { + continue + } + collectSupportedOpcodeMap(supported, literal) + } + } + if literal, ok := node.(*ast.CompositeLit); ok { + mapType, isMap := literal.Type.(*ast.MapType) + keyType, opKeyed := mapTypeKeyIdent(mapType) + if isMap && opKeyed && keyType == "Op" { + collectSupportedOpcodeMap(supported, literal) + } + } + clause, ok := node.(*ast.CaseClause) + if !ok { + return true + } + for _, expr := range clause.List { + candidate := "" + switch value := expr.(type) { + case *ast.BasicLit: + if value.Kind == token.STRING { + candidate, _ = strconv.Unquote(value.Value) + } + case *ast.Ident: + if strings.HasPrefix(value.Name, "Op") { + candidate = strings.TrimPrefix(value.Name, "Op") + } + } + if op := normalizeOp(candidate); op != "" { + supported[op] = struct{}{} + } + } + return true + }) } return supported, nil } +func opcodeComparedWithOp(left, right ast.Expr) (string, bool) { + if ident, ok := left.(*ast.Ident); ok && ident.Name == "op" { + if literal, ok := right.(*ast.BasicLit); ok && literal.Kind == token.STRING { + candidate, err := strconv.Unquote(literal.Value) + return candidate, err == nil + } + } + if ident, ok := right.(*ast.Ident); ok && ident.Name == "op" { + if literal, ok := left.(*ast.BasicLit); ok && literal.Kind == token.STRING { + candidate, err := strconv.Unquote(literal.Value) + return candidate, err == nil + } + } + return "", false +} + +func collectSupportedOpcodeMap(supported map[string]struct{}, literal *ast.CompositeLit) { + mapType, isMap := literal.Type.(*ast.MapType) + keyType, supportedKey := mapTypeKeyIdent(mapType) + if !isMap || !supportedKey || keyType != "string" && keyType != "Op" { + return + } + for _, elt := range literal.Elts { + pair, ok := elt.(*ast.KeyValueExpr) + if !ok { + continue + } + key, ok := pair.Key.(*ast.BasicLit) + if !ok || key.Kind != token.STRING { + continue + } + candidate, _ := strconv.Unquote(key.Value) + if op := normalizeOp(candidate); op != "" { + supported[op] = struct{}{} + } + } +} + +func mapTypeKeyIdent(mapType *ast.MapType) (string, bool) { + if mapType == nil { + return "", false + } + ident, ok := mapType.Key.(*ast.Ident) + if !ok { + return "", false + } + return ident.Name, true +} + func attachEncoderCatalog(rep *report, ops map[string]*opStat, catalog []encoderFormReport) { rep.EncoderCatalog = catalog rep.EncoderForms = len(catalog) diff --git a/cmd/plan9asmscan/main_test.go b/cmd/plan9asmscan/main_test.go index 0d983d8a..f5377a38 100644 --- a/cmd/plan9asmscan/main_test.go +++ b/cmd/plan9asmscan/main_test.go @@ -127,7 +127,7 @@ func TestClusterOfAndTopFiles(t *testing.T) { func TestShortStdPath(t *testing.T) { goroot := runtime.GOROOT() if goroot == "" { - t.Skip("GOROOT not available") + t.Fatal("GOROOT not available") } inRoot := filepath.Join(goroot, "src", "runtime", "sys_arm64.s") @@ -379,15 +379,97 @@ GLOBL foo(SB), RODATA, $8 } } +func TestScanPackagesProbesContiguousX86RawDirectiveGroups(t *testing.T) { + t.Run("complete stream", func(t *testing.T) { + dir := t.TempDir() + src := `TEXT ·f(SB),NOSPLIT,$0-0 + BYTE $0xEB + BYTE $0x00 + RET +` + if err := os.WriteFile(filepath.Join(dir, "raw.s"), []byte(src), 0o644); err != nil { + t.Fatal(err) + } + _, forms, parseErrs, _, _, err := scanPackages([]pkgJSON{{ + ImportPath: "example/raw", + Dir: dir, + SFiles: []string{"raw.s"}, + }}, plan9asm.ArchAMD64, "amd64") + if err != nil { + t.Fatal(err) + } + if len(parseErrs) != 0 { + t.Fatalf("parse errors = %#v", parseErrs) + } + stat := forms["BYTE immediate"] + if stat == nil { + t.Fatalf("missing BYTE immediate form in %#v", forms) + } + if stat.Count != 2 || stat.SupportedCount != 1 || stat.UnsupportedCount != 0 { + t.Fatalf("BYTE stream stats = count %d, supported %d, unsupported %d; want 2, 1, 0", + stat.Count, stat.SupportedCount, stat.UnsupportedCount) + } + }) + + t.Run("truncated stream", func(t *testing.T) { + dir := t.TempDir() + src := `TEXT ·f(SB),NOSPLIT,$0-0 + BYTE $0xEB + RET +` + if err := os.WriteFile(filepath.Join(dir, "raw.s"), []byte(src), 0o644); err != nil { + t.Fatal(err) + } + _, forms, _, _, _, err := scanPackages([]pkgJSON{{ + ImportPath: "example/raw", + Dir: dir, + SFiles: []string{"raw.s"}, + }}, plan9asm.ArchAMD64, "amd64") + if err != nil { + t.Fatal(err) + } + stat := forms["BYTE immediate"] + if stat == nil || stat.UnsupportedCount != 1 { + t.Fatalf("truncated BYTE stream stats = %#v; want one unsupported probe", stat) + } + }) +} + +func TestScanPackagesProbesARMRawUndefinedInstruction(t *testing.T) { + dir := t.TempDir() + src := `TEXT ·f(SB),NOSPLIT,$0-0 + WORD $0xe7f001f0 +` + if err := os.WriteFile(filepath.Join(dir, "raw.s"), []byte(src), 0o644); err != nil { + t.Fatal(err) + } + _, forms, parseErrs, _, _, err := scanPackages([]pkgJSON{{ + ImportPath: "example/raw", + Dir: dir, + SFiles: []string{"raw.s"}, + }}, plan9asm.ArchARM, "arm") + if err != nil { + t.Fatal(err) + } + if len(parseErrs) != 0 { + t.Fatalf("parse errors = %#v", parseErrs) + } + stat := forms["WORD immediate"] + if stat == nil || stat.Count != 1 || stat.SupportedCount != 1 || stat.UnsupportedCount != 0 { + t.Fatalf("ARM WORD stats = %#v; want one supported probe", stat) + } +} + func TestAddFormStatCachesConcreteInstructionsWithoutCollapsingValues(t *testing.T) { forms := map[string]*formStat{} - for _, imm := range []int64{1, 7, 7} { + for _, imm := range []int64{1, 256, 256} { addFormStat(forms, plan9asm.ArchAMD64, "amd64", plan9asm.Instr{ - Op: "RCRQ", - Raw: "RCRQ immediate, AX", + Op: "PALIGNR", + Raw: "PALIGNR immediate, X0, X1", Args: []plan9asm.Operand{ {Kind: plan9asm.OpImm, Imm: imm}, - {Kind: plan9asm.OpReg, Reg: plan9asm.AX}, + {Kind: plan9asm.OpReg, Reg: "X0"}, + {Kind: plan9asm.OpReg, Reg: "X1"}, }, }, "fixture.s") } @@ -432,6 +514,58 @@ func TestBuildOpcodeCatalogIncludesGeneratedTables(t *testing.T) { } } +func TestExtractSupportedOpsFindsPackageLevelSpecTableWithoutOpcodeName(t *testing.T) { + dir := t.TempDir() + if err := os.WriteFile(filepath.Join(dir, "amd64_table.go"), []byte(`package sample +var packedFamilySpecs = map[string]int{ + "VTABLEOP": 1, +} +`), 0o600); err != nil { + t.Fatal(err) + } + if err := os.WriteFile(filepath.Join(dir, "parser.go"), []byte("package sample\n"), 0o600); err != nil { + t.Fatal(err) + } + supported, err := extractSupportedOps(dir, "amd64") + if err != nil { + t.Fatal(err) + } + if _, ok := supported["VTABLEOP"]; !ok { + t.Fatal("package-level table-driven opcode was not extracted") + } +} + +func TestExtractSupportedOpsFindsSingleFamilyOpcodeComparison(t *testing.T) { + dir := t.TempDir() + src := `package sample + +func lowerSingleFamily(op string, unrelated string) bool { + if op != "VEXT" { + return false + } + if "PRFM" == op { + return true + } + return unrelated == "NOT_AN_OPCODE" +} +` + if err := os.WriteFile(filepath.Join(dir, "arm64_lower_single.go"), []byte(src), 0o600); err != nil { + t.Fatal(err) + } + supported, err := extractSupportedOps(dir, "arm64") + if err != nil { + t.Fatal(err) + } + for _, op := range []string{"VEXT", "PRFM"} { + if _, ok := supported[op]; !ok { + t.Errorf("single-family opcode comparison omitted %s", op) + } + } + if _, ok := supported["NOT_AN_OPCODE"]; ok { + t.Fatal("unrelated string comparison was advertised as an opcode") + } +} + func TestBuildWASMOpcodeCatalogNormalizesOfficialNames(t *testing.T) { goroot := t.TempDir() dir := filepath.Join(goroot, "src", "cmd", "internal", "obj", "wasm") diff --git a/doc/plan9asm-corpus.md b/doc/plan9asm-corpus.md index 80ee4bc5..185a2002 100644 --- a/doc/plan9asm-corpus.md +++ b/doc/plan9asm-corpus.md @@ -154,36 +154,52 @@ native-Go-accepted family subset: Discover public modules containing Go assembly from the official index: go run ./cmd/plan9asmdiscover \ - -since 2025-01-01T00:00:00Z \ -limit 2000 \ - -out /tmp/plan9asm-discovery.json + -out-dir testdata/discovery/ledger -Continue at the exact cursor returned by the previous batch: +This starts at the current time and selects the newest records first. Continue +backwards from the ledger-derived earliest covered endpoint, down to the fixed +`2019-04-10T00:00:00Z` cutoff: go run ./cmd/plan9asmdiscover \ - -since "$(jq -r .next_since /tmp/plan9asm-discovery.json)" \ -limit 2000 \ - -out /tmp/plan9asm-discovery-next.json + -out-dir testdata/discovery/ledger -To resume or deliberately rescan an overlapping range without repeating -completed work, load every earlier report as scan state: +The range ledger is the cursor: every update must attach exactly to its earliest +or latest endpoint, and reads/writes reject gaps, overlaps, and conflicting +range counts. To reuse completed exact versions from an additional legacy +report, load it as scan state: go run ./cmd/plan9asmdiscover \ - -since 2025-01-01T00:00:00Z \ + -before 2025-01-01T00:00:00Z \ -limit 2000 \ -seen-report /tmp/plan9asm-discovery.json \ - -seen-report /tmp/plan9asm-discovery-next.json \ -out /tmp/plan9asm-discovery-resumed.json Each report's `scanned` array records every successfully inspected exact `module@version`, including modules with no assembly. `-seen-report` skips only -those exact versions, so a newly published version is still inspected. Failed -versions are listed with their version in `failures`, are not added to -`scanned`, and are retried on a later run. Reports are incremental rather than -cumulative, hence every earlier report must be passed when ranges overlap. +that exact version, so a newly published `@latest` version is still inspected +and replaces the obsolete version. Failed versions are listed with their +version in `failures`, are not added to `scanned`, and are retried on a later +run. Sharded ledgers retain one exact, contiguous range chain and reject gaps, +overlaps, or conflicting range counts. -Use `-limit 0` to continue until the current end of the feed. The discovery -step reads ZIP directory metadata with ranged requests, retries transient +Within a logical module family, selection is ordered by module-path major and +then Go semver. Thus an older index window can upgrade `/v2` to `/v3`, while +subsequent `/v2` records are skipped. The same rule lets a future incremental +window discover `/v4` or a newer version within the retained major. + +Use `-limit 0` to continue backwards to the 2019 cutoff. Scan newly published +index records independently whenever needed with: + + go run ./cmd/plan9asmdiscover \ + -scan-mode incremental \ + -out-dir testdata/discovery/ledger + +Incremental mode uses the greatest covered upper bound as its lower bound and +always drains the full new head interval; `-limit` is ignored so a high-water +mark cannot hide an unfinished gap. +The discovery step reads ZIP directory metadata with ranged requests, retries transient index/proxy failures, ignores `testdata`, zero-byte, and comment-only assembly placeholders, and requires a `.go` file beside a `.s` file so vendored non-Go assembler trees are not reported as packages. @@ -216,20 +232,24 @@ The currently tracked reports are: The ecosystem scan also pins these latest modules: - `github.com/RoaringBitmap/roaring v1.9.4` +- `github.com/aead/siphash v1.0.1` - `github.com/anacrolix/mmsg v1.1.1` - `github.com/btcsuite/fastsha256 v0.0.0-20160815193821-637e65642941` - `github.com/cespare/xxhash v1.1.0` - `github.com/cespare/xxhash/v2 v2.3.0` +- `github.com/chain/txvm v0.0.0-20190422181059-ff6bfbe53892` - `github.com/dchest/siphash v1.2.3` - `github.com/dgryski/go-bits v0.0.0-20180113010104-bd8a69a71dc2` - `github.com/dgryski/go-marvin32 v0.0.0-20240117220238-0d39e8c5a8a9` - `github.com/golang/snappy v1.0.0` - `github.com/klauspost/cpuid v1.3.1` - `github.com/klauspost/cpuid/v2 v2.4.0` +- `github.com/klauspost/crc32 v1.3.0` - `github.com/klauspost/reedsolomon v1.14.2` - `github.com/minio/highwayhash v1.0.4` - `github.com/modern-go/gls v0.0.0-20250215024828-78308f6bb19d` - `github.com/pierrec/lz4/v4 v4.1.30` +- `github.com/phuslu/log v1.0.134` - `github.com/stevvooe/resumable v0.0.0-20180830230917-22b14a53ba50` - `github.com/tmthrgd/go-bitwise v0.0.0-20190904053232-1430ee983fca` - `github.com/tmthrgd/go-popcount v0.0.0-20190904054823-afb1ace8b04f` @@ -329,7 +349,7 @@ The Go 1.27 snapshot currently reports: | GOARCH | official names | encoder forms | observed ops | observed forms | supported | context | unsupported | runtime verified | parse failures | |---|---:|---:|---:|---:|---:|---:|---:|---:|---:| | 386 | 1600 shared x86 names | 4997 shared x86 forms | 21 | 60 | 41 | 6 | 13 | 0 | 0 | -| amd64 | 1600 shared x86 names | 4997 shared x86 forms | 1456 | 6742 | 755 | 6 | 5981 | 35 | 0 | +| amd64 | 1600 shared x86 names | 4997 shared x86 forms | 1456 | 6742 | 804 | 6 | 5932 | 51 | 0 | | arm | 181 | 528 | 135 | 500 | 312 | 34 | 154 | 0 | 0 | | arm64 | 1417 including SVE | 2964 | 1281 | 1980 | 457 | 47 | 1476 | 62 | 0 | | wasm | 463 | 463 opcode-only rows | 71 | 120 | 0 | 120 | 0 | 0 | 0 | diff --git a/ecosystem_forms_test.go b/ecosystem_forms_test.go index be2125b7..5c694647 100644 --- a/ecosystem_forms_test.go +++ b/ecosystem_forms_test.go @@ -126,13 +126,66 @@ TEXT vectors(SB),NOSPLIT,$0-0 POPCNTL 4(AX), R10 RET `) - for _, want := range []string{"mul <2 x i64>", "shufflevector <4 x i32>", "shufflevector <8 x i8>", "@llvm.ctpop.i64", "@llvm.ctpop.i32"} { + for _, want := range []string{"mul <2 x i64>", "shufflevector <4 x i32>", "shufflevector <2 x i64>", "@llvm.ctpop.i64", "@llvm.ctpop.i32"} { if !strings.Contains(ir, want) { t.Fatalf("discovered x86 vector forms are missing %q:\n%s", want, ir) } } } +// These forms come from github.com/aead/siphash@v1.0.1, +// github.com/klauspost/crc32@v1.3.0, and github.com/phuslu/log@v1.0.132. +// The packed min/max forms are tested as a family because the Go assembler +// accepts the same register-or-memory source shape for every lane width and +// signedness combination. +func TestTranslateExpandedEcosystemX86VectorForms(t *testing.T) { + ir := translateEcosystemScalarForms(t, ArchAMD64, "x86_64-unknown-linux-gnu", "amd64", ` +TEXT vectors(SB),NOSPLIT,$0-0 + MOVQ $13, AX + VMOVQ AX, X0 + PSLLQ $13, X0 + PSRLQ $64, X0 + PMINUB X1, X0 + PMINSB X1, X0 + PMINUW X1, X0 + PMINSW X1, X0 + PMINUD X1, X0 + PMINSD X1, X0 + PMAXUB X1, X0 + PMAXSB X1, X0 + PMAXUW X1, X0 + PMAXSW X1, X0 + PMAXUD X1, X0 + PMAXSD 16(BX), X0 + VMOVQ X0, CX + VZEROUPPER + RET +`) + for want, count := range map[string]int{ + "shl <2 x i64>": 1, + "icmp ult <16 x i8>": 1, + "icmp slt <16 x i8>": 1, + "icmp ult <8 x i16>": 1, + "icmp slt <8 x i16>": 1, + "icmp ult <4 x i32>": 1, + "icmp slt <4 x i32>": 1, + "icmp ugt <16 x i8>": 1, + "icmp sgt <16 x i8>": 1, + "icmp ugt <8 x i16>": 1, + "icmp sgt <8 x i16>": 1, + "icmp ugt <4 x i32>": 1, + "icmp sgt <4 x i32>": 1, + "extractelement <2 x i64>": 1, + } { + if got := strings.Count(ir, want); got != count { + t.Fatalf("expanded ecosystem form %q count = %d, want %d:\n%s", want, got, count, ir) + } + } + if !strings.Contains(ir, "store <16 x i8> zeroinitializer") { + t.Fatalf("PSRLQ with an oversized count must clear the vector:\n%s", ir) + } +} + func translateEcosystemScalarForms(t *testing.T, arch Arch, triple, goarch, src string) string { t.Helper() file, err := Parse(arch, src) diff --git a/feature_attrs.go b/feature_attrs.go index d8b648be..4da8a3bb 100644 --- a/feature_attrs.go +++ b/feature_attrs.go @@ -69,22 +69,755 @@ func inferFuncTargetFeaturesForGOARCH(arch Arch, goarch string, fn Func) string switch arch { case ArchAMD64: switch { + case op == "XBEGIN" || op == "XABORT" || op == "XEND" || op == "XTEST": + add("+rtm") + case op == "RDPKRU" || op == "WRPKRU": + add("+pku") + case op == "UMONITOR" || op == "UMWAIT" || op == "TPAUSE": + add("+waitpkg") + case op == "XSETBV": + add("+xsave") + case op == "CLDEMOTE": + add("+cldemote") + case op == "INVPCID": + add("+invpcid") + case strings.Contains(op, "FSBASE") || strings.Contains(op, "GSBASE"): + add("+fsgsbase") + case strings.HasPrefix(op, "FXSAVE") || strings.HasPrefix(op, "FXRSTOR"): + add("+fxsr") + case strings.HasPrefix(op, "XSAVEOPT"): + add("+xsave", "+xsaveopt") + case strings.HasPrefix(op, "XSAVEC"): + add("+xsave", "+xsavec") + case strings.HasPrefix(op, "XSAVES") || strings.HasPrefix(op, "XRSTORS"): + add("+xsave", "+xsaves") + case strings.HasPrefix(op, "XSAVE") || strings.HasPrefix(op, "XRSTOR"): + add("+xsave") + case strings.HasPrefix(op, "VPCMPESTR") || strings.HasPrefix(op, "VPCMPISTR"): + add("+avx", "+sse4.2") + case strings.HasPrefix(op, "PCMPESTR") || strings.HasPrefix(op, "PCMPISTR"): + add("+sse4.2") + case strings.HasPrefix(op, "VEXP2") || strings.HasPrefix(op, "VRCP28") || strings.HasPrefix(op, "VRSQRT28"): + // LLVM 22 removed the avx512er feature flag and target intrinsics, + // but its x86 assembler still supports these encodings. AVX512F + // supplies the Z/K register classes used by the inline assembly. + add("+avx512f") + case strings.HasPrefix(op, "VRCP14") || strings.HasPrefix(op, "VRSQRT14"): + add("+avx512f", "+avx512vl") + case op == "VDPPD" || op == "VDPPS": + add("+avx", "+sse4.1") + case op == "DPPD" || op == "DPPS": + add("+sse4.1") + case op == "VMPSADBW": + add("+avx", "+sse4.1") + for _, arg := range ins.Args { + if arg.Kind == OpReg && isAMD64YReg(arg.Reg) { + add("+avx2") + } + } + case op == "MPSADBW": + add("+sse4.1") + case strings.HasPrefix(op, "RDRAND"): + add("+rdrnd") + case strings.HasPrefix(op, "LZCNT"): + add("+lzcnt") + case strings.HasPrefix(op, "ADCX") || strings.HasPrefix(op, "ADOX"): + add("+adx") + case strings.HasPrefix(op, "RDSEED"): + add("+rdseed") + case op == "CLFLUSHOPT": + add("+clflushopt") + case op == "CLWB": + add("+clwb") + case op == "RDPID": + add("+rdpid") + case op == "CMPXCHG16B": + add("+cx16") + case strings.HasPrefix(op, "BLS"): + add("+bmi") + case strings.HasPrefix(op, "ANDN"): + add("+bmi") + case strings.HasPrefix(op, "BEXTR"): + add("+bmi") + case strings.HasPrefix(op, "MULX") || strings.HasPrefix(op, "RORX") || strings.HasPrefix(op, "SHLX") || strings.HasPrefix(op, "SHRX") || strings.HasPrefix(op, "SARX") || strings.HasPrefix(op, "PDEP") || strings.HasPrefix(op, "PEXT") || strings.HasPrefix(op, "BZHI"): + add("+bmi2") + case op == "RCPPS" || op == "RSQRTPS" || op == "RCPSS" || op == "RSQRTSS": + add("+sse") + case op == "VRCPPS" || op == "VRSQRTPS" || op == "VRCPSS" || op == "VRSQRTSS": + add("+avx", "+sse") + case strings.HasPrefix(op, "VROUND"): + add("+avx") + case strings.HasPrefix(op, "ROUND"): + add("+sse4.1") case goarch == "386" && (op == "MOVOU" || op == "PCMPEQB" || op == "PCMPEQL" || op == "PMOVMSKB"): add("+sse2") case strings.HasPrefix(op, "CRC32"): add("+crc32", "+sse4.2") - case op == "PCLMULQDQ": + case op == "MOVNTIL" || op == "MOVNTIQ": + add("+sse2") + case strings.HasPrefix(op, "MOVBE"): + add("+movbe") + case op == "PCLMULQDQ" || op == "VPCLMULQDQ": add("+pclmul", "+sse4.1") case op == "PSHUFB" || op == "VPSHUFB": add("+ssse3") - case op == "AESENC" || op == "AESENCLAST" || op == "AESDEC" || op == "AESDECLAST" || op == "AESIMC" || op == "AESKEYGENASSIST": + case op == "AESENC" || op == "AESENCLAST" || op == "AESDEC" || op == "AESDECLAST" || op == "AESIMC" || op == "AESKEYGENASSIST" || + op == "VAESENC" || op == "VAESENCLAST" || op == "VAESDEC" || op == "VAESDECLAST" || op == "VAESIMC" || op == "VAESKEYGENASSIST": add("+aes") } case ArchARM64: + if arm64CTERMOps[Op(op)] { + add("+sve") + } + if op == "VPMULL" || op == "VPMULL2" { + add("+aes") + } + if op == "AESE" || op == "AESD" || op == "AESMC" || op == "AESIMC" { + add("+aes") + } + if strings.HasPrefix(op, "SHA1") || strings.HasPrefix(op, "SHA256") { + add("+sha2") + } + if strings.HasPrefix(op, "SHA512") { + add("+sha3") + } if strings.HasPrefix(op, "CRC32") { add("+crc") } + if op == "ADDVL" || op == "ADDPL" || op == "RDVL" || op == "ZADR" || op == "ZDUP" || op == "ZADD" || op == "ZSEL" || op == "ZMUL" || op == "ZAND" || op == "ZBIC" || op == "ZEOR" || op == "ZORR" || op == "ZTBL" || op == "ZUMULLB" { + add("+sve") + } + if _, ok := arm64SVEShiftSpecs[Op(op)]; ok { + add("+sve") + } + if spec, ok := arm64SVEImmediateShiftSpecs[Op(op)]; ok { + add("+sve") + if spec.sve2 { + add("+sve2") + } + } + if _, ok := arm64SVEReverseShiftIntrinsics[Op(op)]; ok { + add("+sve") + } + add(arm64SVEMatrixMultiplyFeatures(Op(op), ins)...) + if op == "ZADDP" { + add("+sve", "+sve2") + } + if _, ok := arm64SVETailOps[Op(op)]; ok { + add("+sve", "+cpa") + } + if _, ok := arm64SVEMultiplyAddTailOps[Op(op)]; ok { + add("+sve", "+cpa") + } + if _, ok := arm64SVEVectorPredicateIncDecSpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEAddSubSpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEFloatAddSubSpecs[Op(op)]; ok { + add("+sve") + } + if op == "ZFMUL" || op == "ZFMULX" { + add("+sve") + } + if _, ok := arm64SVEFloatTrigIntrinsics[Op(op)]; ok { + add("+sve") + } + if op == "ZFTMAD" || op == "ZFCMLA" { + add("+sve") + } + if _, ok := arm64SVEFloatMultiplyAccumulateSpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEMultiplyAccumulateIntrinsics[Op(op)]; ok { + add("+sve") + if arm64SVEMultiplyAccumulateNeedsSVE2(ins) { + add("+sve2") + } + } + if _, ok := arm64SVEMADMSBIntrinsics[Op(op)]; ok { + add("+sve") + } + if op == "ZBFDOT" { + add("+bf16", "+sve") + } + if _, ok := arm64SVEIntegerDotSpecs[Op(op)]; ok { + add("+sve", "+sve2", arm64SVEIntegerDotFeature(ins)) + if op == "ZSUDOT" || op == "ZUSDOT" { + add("+i8mm") + } + } + if _, ok := arm64SVEAESMixIntrinsics[Op(op)]; ok { + add("+sve2-aes") + } + if _, ok := arm64SVEAESRoundIntrinsics[Op(op)]; ok { + if arm64SVEAESRoundIsMulti(ins) { + add("+sve", "+sve-aes2") + } else { + add("+sve2-aes") + } + } + if spec, ok := arm64SVEOptionalCryptoSpecs[Op(op)]; ok { + add(spec.feature) + } + if op == "ZREVD" { + add("+sve", "+sve2p1") + if arm64SVERevdNeedsSVE2P2(ins) { + add("+sve2p2") + } + } + if op == "ZPMUL" { + add("+sve", "+sve2") + } + if _, ok := arm64SVEPMULLIntrinsics[Op(op)]; ok { + add("+sve", "+sve2") + if arm64SVEPMULLNeedsSVE2AES(ins) { + add("+sve2-aes") + } + } + if op == "ZPMULL" || op == "ZPMLAL" { + add("+sve", "+sve-aes2") + } + if _, ok := arm64SVESaturatingMultiplyHighIntrinsics[Op(op)]; ok { + add("+sve") + add("+sve2") + } + if _, ok := arm64SVEComplexMultiplyAccumulateIntrinsics[Op(op)]; ok { + add("+sve") + add("+sve2") + } + if _, ok := arm64SVEComplexAddIntrinsics[Op(op)]; ok { + add("+sve", "+sve2") + } + if op == "ZXAR" { + add("+sve", "+sve2") + } + if _, ok := arm64SVESaturatingRoundingMultiplyAccumulateHighIntrinsics[Op(op)]; ok { + add("+sve") + add("+sve2") + } + if spec, ok := arm64SVEFloatMinMaxSpecs[Op(op)]; ok { + add("+sve") + if spec.kind == arm64SVEFloatMinMaxPairwise { + add("+sve2") + } + if spec.kind == arm64SVEFloatMinMaxQuadReduce { + add("+sve2p1") + } + } + if _, ok := arm64SVECharacterMatchIntrinsics[Op(op)]; ok { + add("+sve", "+sve2") + } + if _, ok := arm64SVEHistogramOps[Op(op)]; ok { + add("+sve", "+sve2") + } + if _, ok := arm64SVEFloatReciprocalStepIntrinsics[Op(op)]; ok { + add("+sve") + } + if op == "ZFEXPA" { + add("+sve") + } + if op == "ZFLOGB" { + add("+sve", "+sve2") + } + if op == "ZFCPY" || op == "ZFDUP" { + add("+sve") + } + if op == "ZFDIV" || op == "ZFDIVR" || op == "ZFSCALE" { + add("+sve") + } + if op == "ZSUQADD" || op == "ZUSQADD" { + add("+sve", "+sve2") + } + if op == "ZFCADD" { + add("+sve", "+sve2") + } + if op == "ZDUPW" { + add("+sve") + } + if op == "ZDUPQ" { + add("+sve", "+sve2p1") + } + if op == "ZDUPM" { + add("+sve") + } + if op == "ZFDOT" { + if sourceBits, destinationBits, ok := arm64SVEFDOTFeatureClass(ins); ok { + add("+sve", "+sve2") + if sourceBits == 8 { + add("+fp8", "+sve2p2") + if destinationBits == 16 { + add("+ssve-fp8dot2") + } else if destinationBits == 32 { + add("+ssve-fp8dot4") + } + } else if sourceBits == 16 && destinationBits == 32 { + add("+f16f32dot", "+sve2p1") + } + } + } + if op == "ZCDOT" { + add("+sve", "+sve2") + } + if op == "ZLUTI2" || op == "ZLUTI4" { + add("+lut", "+sve", "+sve2") + } + if _, ok := arm64SVEWideningFloatMLASpecs[Op(op)]; ok { + if sourceBits, sourceOK := arm64SVEWideningFloatMLAFeatureClass(ins); sourceOK { + add("+sve", "+sve2") + if sourceBits == 8 { + add("+fp8", "+ssve-fp8fma", "+sve2p2") + } + } + } + if _, ok := arm64SVEMultiNarrowSpecs[Op(op)]; ok { + add("+sve", "+sve2p1") + } + if arm64SVEFloatNarrowConversionOp(Op(op)) { + add("+sve") + if Op(op) == "ZFCVTNT" { + add("+sve2") + if len(ins.Args) == 3 { + if _, zeroing := arm64ParseSVEPredicateMode(ins.Args[1], "Z", 7); zeroing { + add("+sve2p2") + } + } + } + if arm64SVEFloatNarrowConversionUsesFP8(Op(op), ins) { + add("+fp8", "+sve2", "+sve2p2") + } + if Op(op) == "ZBFCVT" || Op(op) == "ZBFCVTNT" { + add("+bf16") + } + } + if spec, ok := arm64SVEBFloatArithmeticSpecs[Op(op)]; ok { + add("+sve") + if spec.scale { + add("+sve-bfscale") + } else { + add("+sve-b16b16") + } + } + if spec, ok := arm64SVEBFloatMLASpecs[Op(op)]; ok { + add("+sve") + switch { + case spec.subtractLong: + add("+bf16", "+sve2p1") + case spec.widening: + add("+bf16") + default: + add("+sve-b16b16") + } + } + if spec, ok := arm64SVEFloatPredicatedPairwiseSpecs[Op(op)]; ok { + add("+sve") + if spec.sve2 { + add("+sve2") + } + if spec.faminmax { + add("+faminmax") + } + } + if spec, ok := arm64SVEFloatUnarySpecs[Op(op)]; ok { + add("+sve") + if spec.fptoint { + add("+fptoint") + } + } + if spec, ok := arm64SVEIntegerUnarySpecs[Op(op)]; ok { + add("+sve") + if spec.sve2 { + add("+sve2") + } + } + if _, ok := arm64SVEPredicateLogicalSpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEPredicateBreakSpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEPredicatePermuteSpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEPredicateSelectOps[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEPredicateStateSpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEPredicateIterateSpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEPredicatePositionIntrinsics[Op(op)]; ok { + add("+sve", "+sve2p2") + } + if _, ok := arm64SVEPredicateCounterOps[Op(op)]; ok { + add("+sve") + if arm64SVEPredicateCounterNeedsSVE2P1(Op(op), ins) { + add("+sve2p1") + } + } + if spec, ok := arm64SVEPredicateWhileSpecs[Op(op)]; ok { + add("+sve") + if spec.pointer { + add("+sve2") + } + if arm64SVEPredicateWhileNeedsSVE2P1(ins) { + add("+sve2p1") + } + } + if _, ok := arm64SVEPredicateIncDecSpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEPredicateMemoryOps[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEWholeVectorMemoryOps[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEVectorPrefetchBits[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVENonTemporalMemorySpecs[Op(op)]; ok { + add("+sve") + if arm64SVENonTemporalMemoryNeedsSVE2P1(ins) { + add("+sve2p1") + } + } + if _, ok := arm64SVEOrdinaryMemorySpecs[Op(op)]; ok { + add("+sve") + if arm64SVEOrdinaryMemoryNeedsSVE2P1(ins) { + add("+sve2p1") + } + } + if spec, ok := arm64SVEStructuredMemorySpecs[Op(op)]; ok { + add("+sve") + if spec.q { + add("+sve2p1") + } + } + if _, ok := arm64SVEFirstFaultMemorySpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVENonFaultingMemorySpecs[Op(op)]; ok { + add("+sve") + } + if spec, ok := arm64SVEReplicateMemorySpecs[Op(op)]; ok { + add("+sve") + if spec.blockBytes == 32 { + add("+f64mm") + } + } + if op == "ZPMOV" { + add("+sve", "+sve2p1") + } + if op == "ZINDEX" || op == "ZINDEXW" { + add("+sve") + } + if _, ok := arm64SVEInsertBaseSize[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVELastSpecs[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVECLastSpecs[Op(op)]; ok { + add("+sve") + } + if op == "ZCOMPACT" { + add("+sve") + if arm64SVECompactNeedsSVE2P2(ins) { + add("+sve2p2") + } + } + if op == "ZEXPAND" { + add("+sve", "+sve2p2") + } + if op == "ZMOVPRFX" { + add("+sve") + } + if op == "ZEXT" { + add("+sve") + } + if op == "ZEXTQ" { + add("+sve", "+sve2p1") + } + if op == "ZSPLICE" { + add("+sve") + } + if op == "ZCPY" || op == "ZCPYW" { + add("+sve") + } + if _, ok := arm64SVECopyVectorBaseSize[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVEConvertSpecs[Op(op)]; ok { + add("+sve") + if op == "ZFCVTLT" || op == "ZFCVTXNT" { + add("+sve2p2") + } + } + if _, ok := arm64SVECompareSpecs[Op(op)]; ok { + add("+sve") + } + if spec, ok := arm64SVEMinMaxSpecs[Op(op)]; ok { + add("+sve") + if spec.kind == arm64SVEMinMaxPairwise { + add("+sve2") + } + if spec.kind == arm64SVEMinMaxQuadReduce { + add("+sve2p1") + } + } + if spec, ok := arm64SVEIntegerReductionSpecs[Op(op)]; ok { + add("+sve") + if spec.quad { + add("+sve2p1") + } + } + if spec, ok := arm64SVEAddReductionSpecs[Op(op)]; ok { + add("+sve") + if spec.kind == arm64SVEFloatAddQuadReduce { + add("+sve2p1") + } + } + if _, ok := arm64SVEWideningAddSubSpecs[Op(op)]; ok { + add("+sve", "+sve2") + } + if _, ok := arm64SVEShiftLongIntrinsics[Op(op)]; ok { + add("+sve", "+sve2") + } + if spec, ok := arm64SVEAbsoluteDifferenceSpecs[Op(op)]; ok { + add("+sve") + if spec.kind != arm64SVEAbsoluteDifference { + add("+sve2") + } + } + if _, ok := arm64SVEHalvingAddSubIntrinsics[Op(op)]; ok { + add("+sve", "+sve2") + } + if _, ok := arm64SVEDivideIntrinsics[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVETernaryBitwiseIntrinsics[Op(op)]; ok { + add("+sve", "+sve2") + } + if _, ok := arm64SVEEORInterleaveIntrinsics[Op(op)]; ok { + add("+sve", "+sve2") + } + if _, ok := arm64SVEBitPermuteIntrinsics[Op(op)]; ok { + add("+sve", "+sve-bitperm", "+sve2") + } + if _, ok := arm64SVECarryLongIntrinsics[Op(op)]; ok { + add("+sve", "+sve2") + } + if spec, ok := arm64SVEClampSpecs[Op(op)]; ok { + if spec.kind == arm64SVEClampBFloat { + add("+sve", "+sve-b16b16") + } else { + add("+sve", "+sve2p1") + } + } + if _, ok := arm64SVEUnpackIntrinsics[Op(op)]; ok { + add("+sve") + } + if _, ok := arm64SVESaturatingNarrowSpecs[Op(op)]; ok { + add("+sve", "+sve2") + } + if _, ok := arm64SVEShiftNarrowSpecs[Op(op)]; ok { + add("+sve", "+sve2") + } + if _, ok := arm64SVESaturatingShiftNarrowSpecs[Op(op)]; ok { + add("+sve", "+sve2") + } + if op == "ZDUP" && len(ins.Args) == 2 { + if _, bits, _, ok := arm64ParseSVEDupElementReg(ins.Args[0]); ok && bits == 128 { + add("+sve2p1") + } + } + if op == "ZMUL" && arm64SVEMultiplyNeedsSVE2(ins) { + add("+sve2") + } + if _, ok := arm64SVEMultiplyHighIntrinsics[Op(op)]; ok { + add("+sve") + if arm64SVEMultiplyHighNeedsSVE2(ins) { + add("+sve2") + } + } + if _, ok := arm64SVEVariableShiftSpecs[Op(op)]; ok { + add("+sve", "+sve2") + } + if op == "ZTBL" && arm64SVETableNeedsSVE2(ins) { + add("+sve2") + } + if _, ok := arm64SVETableExtensionIntrinsics[Op(op)]; ok { + add("+sve") + if op == "ZTBX" { + add("+sve2") + } else { + add("+sve2p1") + } + } + if _, ok := arm64SVEMultiplyLongSpecs[Op(op)]; ok { + add("+sve", "+sve2") + } + if _, ok := arm64SVEMultiplyAccumulateLongIntrinsics[Op(op)]; ok { + add("+sve", "+sve2") + } + if _, ok := arm64SVEPermuteIntrinsics[Op(op)]; ok { + add("+sve") + if arm64SVEIsQPermuteOp(Op(op)) { + add("+sve2p1") + } else if arm64SVEPermuteNeedsF64MM(ins) { + add("+f64mm") + } + } + if op == "WORD" && len(ins.Args) == 1 && ins.Args[0].Kind == OpImm && ins.Args[0].ImmRaw == "" { + word := uint32(ins.Args[0].Imm) + if decoded, err := decodeARM64RawWordInstruction(ins); err == nil { + decodedFeatures := inferFuncTargetFeaturesForGOARCH(ArchARM64, goarch, Func{Instrs: []Instr{decoded}}) + add(strings.Split(decodedFeatures, ",")...) + } + if _, ok := decodeARM64RawAES(word); ok { + add("+aes") + } + if _, ok := decodeARM64RawFloatMultiplyLong(word); ok { + add("+fp16fml") + } + if form, ok := decodeARM64RawFMULByElement(word); ok && form.arrangement.elementBits == 16 { + add("+fullfp16") + } + if _, ok := decodeARM64RawSVEAddress(word); ok { + add("+sve") + } + if _, ok := decodeARM64RawSVECnt(word); ok { + add("+sve") + } + if _, ok := decodeARM64RawSVEPTrue(word); ok { + add("+sve") + } + if _, ok := decodeARM64RawSVELDST1D(word); ok { + add("+sve") + } + if _, ok := decodeARM64RawSVELDST1W(word); ok { + add("+sve") + } + if _, ok := decodeARM64RawSVEFloat(word); ok { + add("+sve") + } + if _, ok := decodeARM64RawSVELoadStore(word); ok { + add("+sve") + } + if _, ok := decodeARM64RawSVEDupImmediate(word); ok { + add("+sve") + } + if _, ok := decodeARM64RawSVEDupGeneral(word); ok { + add("+sve") + } + if form, ok := decodeARM64RawSVEDupElement(word); ok { + add("+sve") + if form.elementBits == 128 { + add("+sve2p1") + } + } + if _, ok := decodeARM64RawSVEAdd(word); ok { + add("+sve") + } + if _, ok := decodeARM64RawSVELSR(word); ok { + add("+sve") + } + if _, ok := decodeARM64RawSVESelect(word); ok { + add("+sve") + } + if form, ok := decodeARM64RawSVEMultiply(word); ok { + add("+sve") + if form.mode == arm64SVEMultiplyUnpredicated || form.mode == arm64SVEMultiplyLane { + add("+sve2") + } + } + if _, ok := decodeARM64RawSVEEOR(word); ok { + add("+sve") + } + if form, ok := decodeARM64RawSVETable(word); ok { + add("+sve") + if form.tableCount == 2 { + add("+sve2") + } + } + if _, ok := decodeARM64RawSVEUMULLB(word); ok { + add("+sve", "+sve2") + } + if _, ok := decodeARM64RawSVEMultiplyAccumulateLong(word); ok { + add("+sve", "+sve2") + } + if form, ok := decodeARM64RawSVEPermute(word); ok { + add("+sve") + if form.quad { + add("+f64mm") + } + } + } case ArchARM: + if op == "WORD" && len(ins.Args) == 1 && ins.Args[0].Kind == OpImm { + if _, ok := decodeARMRawVFPMove(uint32(ins.Args[0].Imm)); ok { + add("+vfp2") + } + if form, ok := decodeARMRawNEONPairwiseMinMax(uint32(ins.Args[0].Imm)); ok { + add("+neon") + if form.floating && form.elementBits == 16 { + add("+fullfp16") + } + } + if form, ok := decodeARMRawNEONMinMax(uint32(ins.Args[0].Imm)); ok { + add("+neon") + if form.floating && form.elementBits == 16 { + add("+fullfp16") + } + } + if _, ok := decodeARMRawVFPStatusTransfer(uint32(ins.Args[0].Imm)); ok { + add("+vfp2") + } + if _, ok := decodeARMRawVFPScalarArithmetic(uint32(ins.Args[0].Imm)); ok { + add("+vfp2") + } + if form, ok := decodeARMRawNEONMultiplyLane(uint32(ins.Args[0].Imm)); ok { + add("+neon") + if form.floating && form.elementBits == 16 { + add("+fullfp16") + } + } + if _, ok := decodeARMRawNEONConvertFloat32(uint32(ins.Args[0].Imm)); ok { + add("+neon") + } + if _, ok := decodeARMRawNEONMoveLong(uint32(ins.Args[0].Imm)); ok { + add("+neon") + } + if _, ok := decodeARMRawNEONWideningSubtract(uint32(ins.Args[0].Imm)); ok { + add("+neon") + } + if _, ok := decodeARMRawNEONDup(uint32(ins.Args[0].Imm)); ok { + add("+neon") + } + if decoded, err := decodeARMRawWordInstruction(ins); err == nil { + decodedFeatures := inferFuncTargetFeaturesForGOARCH(ArchARM, goarch, Func{Instrs: []Instr{decoded}}) + add(strings.Split(decodedFeatures, ",")...) + } + if _, ok := decodeARMRawVFPImmediate(uint32(ins.Args[0].Imm)); ok { + add("+vfp2") + } + if _, ok := decodeARMRawVMOVPair(uint32(ins.Args[0].Imm)); ok { + add("+vfp2") + } + if _, ok := decodeARMRawVFPMultiple(uint32(ins.Args[0].Imm)); ok { + add("+vfp2") + } + if _, ok := decodeARMRawNEONStructureOne(uint32(ins.Args[0].Imm)); ok { + add("+neon") + } + if _, ok := decodeARMRawNEONEOR(uint32(ins.Args[0].Imm)); ok { + add("+neon") + } + } // Go's ARM runtime keeps VFP save/restore instructions in the // GOARM=5 image and guards their execution with goarmsoftfp. LLVM // still needs VFP enabled while assembling that otherwise-dead path. @@ -101,7 +834,7 @@ func inferFuncTargetFeaturesForGOARCH(arch Arch, goarch string, fn Func) string default: continue } - if reg == "FPCR" || reg == "FPSR" || strings.HasPrefix(reg, "F") { + if reg == "FPCR" || reg == "FPSR" || reg == "FPSCR" || strings.HasPrefix(reg, "F") || strings.HasPrefix(reg, "S") { add("+vfp2") break } diff --git a/feature_attrs_test.go b/feature_attrs_test.go index 69547866..885063fe 100644 --- a/feature_attrs_test.go +++ b/feature_attrs_test.go @@ -24,7 +24,7 @@ func TestInferFuncTargetFeatures(t *testing.T) { { name: "amd64 pclmul", arch: ArchAMD64, - ops: []Op{"PCLMULQDQ"}, + ops: []Op{"PCLMULQDQ", "VPCLMULQDQ"}, want: "+pclmul,+sse4.1", }, { @@ -36,9 +36,33 @@ func TestInferFuncTargetFeatures(t *testing.T) { { name: "amd64 aes", arch: ArchAMD64, - ops: []Op{"AESENC", "AESENCLAST", "AESDEC", "AESDECLAST", "AESIMC", "AESKEYGENASSIST"}, + ops: []Op{"AESENC", "AESENCLAST", "AESDEC", "AESDECLAST", "AESIMC", "AESKEYGENASSIST", "VAESENC", "VAESENCLAST", "VAESDEC", "VAESDECLAST", "VAESIMC", "VAESKEYGENASSIST"}, want: "+aes", }, + { + name: "amd64 cmpxchg16b", + arch: ArchAMD64, + ops: []Op{"CMPXCHG16B"}, + want: "+cx16", + }, + { + name: "x86 cache line writeback", + arch: ArchAMD64, + ops: []Op{"CLFLUSH", "CLFLUSHOPT", "CLWB"}, + want: "+clflushopt,+clwb", + }, + { + name: "amd64 round", + arch: ArchAMD64, + ops: []Op{"ROUNDPS", "ROUNDPD", "ROUNDSS", "ROUNDSD", "VROUNDPS", "VROUNDPD", "VROUNDSS", "VROUNDSD"}, + want: "+avx,+sse4.1", + }, + { + name: "x86 reciprocal14", + arch: ArchAMD64, + ops: []Op{"VRCP14SS", "VRSQRT14PD.Z"}, + want: "+avx512f,+avx512vl", + }, { name: "amd64 combined sorted deduped", arch: ArchAMD64, diff --git a/frame_type_size.go b/frame_type_size.go new file mode 100644 index 00000000..967e2a53 --- /dev/null +++ b/frame_type_size.go @@ -0,0 +1,22 @@ +package plan9asm + +// frameTypeSize returns the byte width occupied by a scalar FrameLayout slot. +// Pointer width is target-specific, so architecture lowerers provide it. +func frameTypeSize(ty LLVMType, pointerSize int64) int64 { + switch ty { + case I1, I8: + return 1 + case I16: + return 2 + case Ptr: + return pointerSize + case I32, LLVMType("float"): + return 4 + case I64, LLVMType("double"): + return 8 + default: + // FrameLayout normally contains scalar parts. Keep enough room for an + // unexpected aggregate so address formation remains within the alloca. + return 16 + } +} diff --git a/go.mod b/go.mod index cdfd5ad3..1f8f3fa8 100644 --- a/go.mod +++ b/go.mod @@ -3,3 +3,8 @@ module github.com/xgo-dev/plan9asm go 1.20 require github.com/xgo-dev/llvm v0.9.9 + +require ( + golang.org/x/arch v0.14.0 + golang.org/x/mod v0.20.0 +) diff --git a/go.sum b/go.sum index b04bd084..b9237e16 100644 --- a/go.sum +++ b/go.sum @@ -1,2 +1,6 @@ github.com/xgo-dev/llvm v0.9.9 h1:u4RZvy0vxu8nNt4oTrhttyMSyscYtmiy9geP+Kl/RYg= github.com/xgo-dev/llvm v0.9.9/go.mod h1:42vav2/cI5BAIcL543DZSMO9do8/aCK2z7JERH+AE+M= +golang.org/x/arch v0.14.0 h1:z9JUEZWr8x4rR0OU6c4/4t6E6jOZ8/QBS2bBYBm4tx4= +golang.org/x/arch v0.14.0/go.mod h1:FEVrYAQjsQXMVJ1nsMoVVXPZg6p2JE2mx8psSWTDQys= +golang.org/x/mod v0.20.0 h1:utOm6MM3R3dnawAiJgn0y+xvuYRsm1RKM/4giyfDgV0= +golang.org/x/mod v0.20.0/go.mod h1:hTbmBsO62+eylJbnUtE2MGJUyE7QWk4xUqPFrRgJ+7c= diff --git a/go_translate.go b/go_translate.go index e9f73dd1..384372f2 100644 --- a/go_translate.go +++ b/go_translate.go @@ -99,16 +99,9 @@ func TranslateGoModule(pkg GoPackage, src []byte, opt GoModuleOptions) (*GoModul resolve = func(sym string) string { return goStripABISuffix(sym) } } - if bytes.Contains(src, []byte("const_")) { - src = goExpandConsts(src, pkg.Types, pkg.Imports) - } - // Struct layout macros only exist when the assembly includes go_asm.h. - // Keep the common path cheap: building them walks every package-scope type. - if bytes.Contains(src, []byte("go_asm.h")) { - src = goExpandAsmHeaderTypes(src, pkg.Types, opt.GOARCH) - } + src = ExpandGoAssemblySource(pkg, src, opt.GOARCH) - file, err := Parse(arch, string(src)) + file, err := ParseWithDefines(arch, string(src), GoAssemblerDefines(opt.GOOS, opt.GOARCH)) if err != nil { return nil, fmt.Errorf("%s: parse %s: %w", pkgPath, asmName, err) } @@ -148,6 +141,23 @@ func TranslateGoModule(pkg GoPackage, src []byte, opt GoModuleOptions) (*GoModul return &GoModuleTranslation{Module: mod, Signatures: sigs, Functions: funcs}, nil } +// ExpandGoAssemblySource resolves the constants and type-layout identifiers +// that cmd/compile writes to a package's generated go_asm.h. Callers that parse +// package assembly themselves must run this before Parse; leaving a $const_X +// token unresolved can otherwise be mistaken for a successfully translated +// zero value or rejected only after unrelated lowering has begun. +func ExpandGoAssemblySource(pkg GoPackage, src []byte, goarch string) []byte { + if bytes.Contains(src, []byte("const_")) { + src = goExpandConsts(src, pkg.Types, pkg.Imports) + } + // Struct layout macros only exist when the assembly includes go_asm.h. + // Keep the common path cheap: building them walks every package-scope type. + if bytes.Contains(src, []byte("go_asm.h")) { + src = goExpandAsmHeaderTypes(src, pkg.Types, goarch) + } + return src +} + var goABISuffixRe = regexp.MustCompile(`]*>$`) var goConstRefRe = regexp.MustCompile(`\bconst_[A-Za-z0-9_]+\b`) var goConstPlusRefRe = regexp.MustCompile(`([\pL\pN_∕·./]+)\+const_([A-Za-z0-9_]+)`) @@ -256,6 +266,13 @@ func wasmUsesNativeReturn(fn Func) bool { return false } +// WASMAssemblyUsesNativeReturn reports whether fn contains Go's WebAssembly +// Return pseudo-instruction. Unlike RET, Return exchanges a result through the +// native wasm operand stack and therefore requires a native wasm signature. +func WASMAssemblyUsesNativeReturn(fn Func) bool { + return wasmUsesNativeReturn(fn) +} + type goSigBuilder struct { sigs map[string]FuncSig localSigs map[string]bool @@ -362,6 +379,15 @@ func wasmGoNativeFuncSig(name string) (FuncSig, bool) { return FuncSig{}, false } +// LookupGoWASMNativeFuncSig returns the native WebAssembly ABI used by Go +// assembly entry points whose signatures are not described by Go declarations. +// These functions are part of the Go runtime/standard-library assembly +// contract and intentionally exchange values through wasm registers or the +// operand stack instead of the ordinary Go stack ABI. +func LookupGoWASMNativeFuncSig(name string) (FuncSig, bool) { + return wasmGoNativeFuncSig(name) +} + func (b *goSigBuilder) addReferencedFuncSigs(file *File) error { for _, fn := range file.Funcs { callerResolved := b.resolve(goTextSymbolForResolution(fn.Sym)) @@ -637,44 +663,47 @@ func goExpandConsts(src []byte, pkgTypes *types.Package, imports map[string]*typ return "", false } - src = goConstPlusRefRe.ReplaceAllFunc(src, func(m []byte) []byte { - sub := goConstPlusRefRe.FindSubmatch(m) - if len(sub) != 3 { - return m - } - prefix := string(sub[1]) - name := string(sub[2]) - if i := strings.LastIndex(prefix, "/"); i >= 0 { - path := prefix[:i] - sym := prefix[i+1:] - if tp := typeByPath[path]; tp != nil { - if val, ok := lookupConst(tp, name); ok { - return []byte(path + "/" + sym + "+" + val) + expand := func(fragment []byte) []byte { + fragment = goConstPlusRefRe.ReplaceAllFunc(fragment, func(m []byte) []byte { + sub := goConstPlusRefRe.FindSubmatch(m) + if len(sub) != 3 { + return m + } + prefix := string(sub[1]) + name := string(sub[2]) + if i := strings.LastIndex(prefix, "/"); i >= 0 { + path := prefix[:i] + sym := prefix[i+1:] + if tp := typeByPath[path]; tp != nil { + if val, ok := lookupConst(tp, name); ok { + return []byte(path + "/" + sym + "+" + val) + } } } - } - if j := strings.LastIndex(prefix, "."); j >= 0 { - path := prefix[:j] - sym := prefix[j+1:] - if tp := typeByPath[path]; tp != nil { - if val, ok := lookupConst(tp, name); ok { - return []byte(path + "." + sym + "+" + val) + if j := strings.LastIndex(prefix, "."); j >= 0 { + path := prefix[:j] + sym := prefix[j+1:] + if tp := typeByPath[path]; tp != nil { + if val, ok := lookupConst(tp, name); ok { + return []byte(path + "." + sym + "+" + val) + } } } - } - if val, ok := lookupConst(pkgTypes, name); ok { - return []byte(prefix + "+" + val) - } - return m - }) + if val, ok := lookupConst(pkgTypes, name); ok { + return []byte(prefix + "+" + val) + } + return m + }) - return goConstRefRe.ReplaceAllFunc(src, func(m []byte) []byte { - name := strings.TrimPrefix(string(m), "const_") - if val, ok := lookupConst(pkgTypes, name); ok { - return []byte(val) - } - return m - }) + return goConstRefRe.ReplaceAllFunc(fragment, func(m []byte) []byte { + name := strings.TrimPrefix(string(m), "const_") + if val, ok := lookupConst(pkgTypes, name); ok { + return []byte(val) + } + return m + }) + } + return goExpandAssemblyMacroUses(src, expand) } // goExpandAsmHeaderTypes expands the struct size and field offset macros that @@ -690,6 +719,13 @@ func goExpandAsmHeaderTypes(src []byte, pkgTypes *types.Package, goarch string) if sizes == nil { return src } + referenced := make(map[string]bool) + goExpandAssemblyMacroUses(src, func(fragment []byte) []byte { + for _, ident := range goAsmHeaderIdentRe.FindAll(fragment, -1) { + referenced[string(ident)] = true + } + return fragment + }) macros := make(map[string]string) for _, name := range pkgTypes.Scope().Names() { obj, ok := pkgTypes.Scope().Lookup(name).(*types.TypeName) @@ -700,34 +736,120 @@ func goExpandAsmHeaderTypes(src []byte, pkgTypes *types.Package, goarch string) if !ok { continue } - size := sizes.Sizeof(obj.Type()) - if size < 0 { + needSize := referenced[name+"__size"] + needOffsets := false + for i := 0; i < st.NumFields(); i++ { + field := st.Field(i) + if field.Name() != "_" && referenced[name+"_"+field.Name()] { + needOffsets = true + break + } + } + if !needSize && !needOffsets { + continue + } + if goTypeHasUnboundTypeParams(obj.Type()) { + continue + } + if needSize { + size := sizes.Sizeof(obj.Type()) + if size >= 0 { + macros[name+"__size"] = strconv.FormatInt(size, 10) + } + } + if !needOffsets { continue } - macros[name+"__size"] = strconv.FormatInt(size, 10) fields := make([]*types.Var, st.NumFields()) for i := range fields { fields[i] = st.Field(i) } for i, offset := range sizes.Offsetsof(fields) { field := fields[i] - if field.Name() == "_" || offset < 0 { + macro := name + "_" + field.Name() + if field.Name() == "_" || !referenced[macro] || offset < 0 { continue } - macros[name+"_"+field.Name()] = strconv.FormatInt(offset, 10) + macros[macro] = strconv.FormatInt(offset, 10) } } if len(macros) == 0 { return src } - return goAsmHeaderIdentRe.ReplaceAllFunc(src, func(ident []byte) []byte { - if value, ok := macros[string(ident)]; ok { - return []byte(value) - } - return ident + return goExpandAssemblyMacroUses(src, func(fragment []byte) []byte { + return goAsmHeaderIdentRe.ReplaceAllFunc(fragment, func(ident []byte) []byte { + if value, ok := macros[string(ident)]; ok { + return []byte(value) + } + return ident + }) }) } +func goTypeHasUnboundTypeParams(typ types.Type) bool { + generic, ok := typ.(interface { + TypeParams() *types.TypeParamList + TypeArgs() *types.TypeList + }) + return ok && generic.TypeParams().Len() != 0 && generic.TypeArgs().Len() == 0 +} + +// goExpandAssemblyMacroUses applies a generated-header expansion everywhere +// except the name and formal-parameter list of a #define directive. Package +// assembly may include a real generated header (for example ffi.h) alongside +// Go's virtual go_asm.h. Rewriting the definition name would turn a valid +// directive such as "#define const_type64 0" into "#define 0 0" before the +// ordinary preprocessor has a chance to consume it. +func goExpandAssemblyMacroUses(src []byte, expand func([]byte) []byte) []byte { + var out bytes.Buffer + for _, line := range bytes.SplitAfter(src, []byte{'\n'}) { + protected := goAssemblyDefinePrefixLen(line) + out.Write(line[:protected]) + out.Write(expand(line[protected:])) + } + return out.Bytes() +} + +func goAssemblyDefinePrefixLen(line []byte) int { + i := 0 + for i < len(line) && (line[i] == ' ' || line[i] == '\t') { + i++ + } + const directive = "#define" + if !bytes.HasPrefix(line[i:], []byte(directive)) { + return 0 + } + i += len(directive) + if i >= len(line) || line[i] != ' ' && line[i] != '\t' { + return 0 + } + for i < len(line) && (line[i] == ' ' || line[i] == '\t') { + i++ + } + if i >= len(line) || !isIdentStart(line[i]) { + return 0 + } + for i < len(line) && isIdentPart(line[i]) { + i++ + } + if i >= len(line) || line[i] != '(' { + return i + } + depth := 0 + for ; i < len(line); i++ { + switch line[i] { + case '(': + depth++ + case ')': + depth-- + if depth == 0 { + return i + 1 + } + } + } + return len(line) +} + func goLLVMTypeForType(t types.Type, goarch string) (LLVMType, error) { return goLLVMTypeForTypeWithSizes(t, goarch, types.SizesFor("gc", goarch)) } @@ -808,6 +930,10 @@ func goLLVMArgsAndFrameSlotsForTuple(tup *types.Tuple, goarch string, sz, frameS off := startOff argIdx := 0 for i := 0; i < tup.Len(); i++ { + name := "" + if flattenAgg { + name = tup.At(i).Name() + } t := tup.At(i).Type() a := int64(frameSz.Alignof(t)) off = goAlignOff(off, a) @@ -817,7 +943,7 @@ func goLLVMArgsAndFrameSlotsForTuple(tup *types.Tuple, goarch string, sz, frameS if flattenAgg { for _, part := range parts { args = append(args, part.Type) - slots = append(slots, FrameSlot{Offset: off + part.Offset, Type: part.Type, Index: argIdx, Field: -1}) + slots = append(slots, FrameSlot{Offset: off + part.Offset, Type: part.Type, Index: argIdx, Field: -1, Name: name}) argIdx++ } } else { @@ -840,7 +966,7 @@ func goLLVMArgsAndFrameSlotsForTuple(tup *types.Tuple, goarch string, sz, frameS return nil, nil, 0, e } args = append(args, ty) - slots = append(slots, FrameSlot{Offset: off, Type: ty, Index: argIdx, Field: -1}) + slots = append(slots, FrameSlot{Offset: off, Type: ty, Index: argIdx, Field: -1, Name: name}) argIdx++ off += int64(frameSz.Sizeof(t)) } diff --git a/go_translate_helpers_test.go b/go_translate_helpers_test.go index 9e9a8106..c8866c7e 100644 --- a/go_translate_helpers_test.go +++ b/go_translate_helpers_test.go @@ -141,6 +141,14 @@ MOVD $const_Bool, R5 func TestGoAsmHeaderDataConstants(t *testing.T) { pkg := types.NewPackage("test/pkg", "pkg") + genericName := types.NewTypeName(token.NoPos, pkg, "generic", nil) + typeParamName := types.NewTypeName(token.NoPos, pkg, "T", nil) + typeParam := types.NewTypeParam(typeParamName, types.NewInterfaceType(nil, nil).Complete()) + generic := types.NewNamed(genericName, types.NewStruct([]*types.Var{ + types.NewField(token.NoPos, pkg, "value", typeParam, false), + }, nil), nil) + generic.SetTypeParams([]*types.TypeParam{typeParam}) + pkg.Scope().Insert(genericName) pkg.Scope().Insert(types.NewConst(token.NoPos, pkg, "smallInt", types.Typ[types.UntypedInt], constant.MakeInt64(42))) pkg.Scope().Insert(types.NewConst(token.NoPos, pkg, "bigInt", types.Typ[types.UntypedInt], constant.MakeUint64(^uint64(0)))) pkg.Scope().Insert(types.NewConst(token.NoPos, pkg, "stringVal", types.Typ[types.UntypedString], constant.MakeString("test"))) @@ -166,6 +174,10 @@ func TestGoAsmHeaderDataConstants(t *testing.T) { if got := goExpandAsmHeaderTypes(unchanged, pkg, "unsupported"); !bytes.Equal(got, unchanged) { t.Fatalf("unsupported-arch expansion changed source: %q", got) } + genericRef := []byte("MOVD $generic__size, R0") + if got := goExpandAsmHeaderTypes(genericRef, pkg, "arm64"); !bytes.Equal(got, genericRef) { + t.Fatalf("uninstantiated generic struct macro unexpectedly expanded: %q", got) + } nonStructPkg := types.NewPackage("test/nonstruct", "nonstruct") nonStructPkg.Scope().Insert(types.NewVar(token.NoPos, nonStructPkg, "value", types.Typ[types.Int])) if got := goExpandAsmHeaderTypes(unchanged, nonStructPkg, "arm64"); !bytes.Equal(got, unchanged) { diff --git a/go_translate_test.go b/go_translate_test.go index 56deff0b..fec90fd0 100644 --- a/go_translate_test.go +++ b/go_translate_test.go @@ -76,6 +76,35 @@ TEXT ·gogo(SB),NOSPLIT,$0-8 } } +func TestExpandGoAssemblySourcePreservesIncludedMacroDefinitionNames(t *testing.T) { + pkg := mustGoPackage(t, "example.com/ffi", `package ffi +const type64 = 0 +type frame struct { value uintptr } +func asmcall() +`) + source := []byte(`// runtime has #include "go_asm.h" +#define const_type64 0x0 +#define frame__size 8 +TEXT ·asmcall(SB),NOSPLIT,$0-0 + CMPB AX, $const_type64 + MOVQ $frame__size, BX + RET +`) + expanded := ExpandGoAssemblySource(pkg, source, "amd64") + if strings.Contains(string(expanded), "#define 0 ") { + t.Fatalf("constant expansion rewrote the macro definition name:\n%s", expanded) + } + if !strings.Contains(string(expanded), "#define const_type64 0x0") { + t.Fatalf("constant expansion did not preserve the macro definition:\n%s", expanded) + } + if !strings.Contains(string(expanded), "#define frame__size 8") { + t.Fatalf("type-layout expansion did not preserve the macro definition:\n%s", expanded) + } + if _, err := ParseWithDefines(ArchAMD64, string(expanded), GoAssemblerDefines("linux", "amd64")); err != nil { + t.Fatalf("ParseWithDefines(expanded) error = %v\n%s", err, expanded) + } +} + func TestTranslateGoModule_UsesCallerWasmTypeSizes(t *testing.T) { pkg := mustGoPackage(t, "example.com/wasm32", `package wasm32 func Consume(value int, data []byte) int diff --git a/instruction.go b/instruction.go index 4331b80d..cdf5e409 100644 --- a/instruction.go +++ b/instruction.go @@ -144,10 +144,10 @@ func arm64InstructionFamily(op string) string { switch { case isARM64BranchOpcode(op): return "control-flow" + case strings.HasPrefix(op, "CAS") || strings.HasPrefix(op, "SWP") || strings.Contains(op, "XR") || strings.Contains(op, "XP"): + return "atomic-memory" case strings.HasPrefix(op, "LD") || strings.HasPrefix(op, "ST") || strings.HasPrefix(op, "MOV"): return "load-store-move" - case strings.HasPrefix(op, "CAS") || strings.HasPrefix(op, "SWP") || strings.Contains(op, "XR"): - return "atomic-memory" case strings.HasPrefix(op, "AES") || strings.HasPrefix(op, "SHA"): return "crypto" case strings.HasPrefix(op, "V"): @@ -315,6 +315,9 @@ func registerClass(arch Arch, goarch string, reg Reg) string { if r == "ZR" { return "zero-register" } + if r == "RSP" { + return "stack-pointer" + } if prefix, index, _, ok := regRangeParts(Reg(r)); ok { switch { case prefix == "Z" && index <= 31: @@ -402,6 +405,23 @@ func ProbeInstruction(arch Arch, goarch string, ins Instr) error { if strings.HasPrefix(normalizeInstructionOpcode(ins.Op), "REP") { return fmt.Errorf("%w: REP prefix must be probed with its following instruction", ErrProbeNeedsContext) } + if arch == ArchAMD64 && goarch == "386" && normalizeInstructionOpcode(ins.Op) == "JMP" && + len(ins.Args) == 1 && ins.Args[0].Kind == OpImm && ins.Args[0].ImmRaw == "" { + return fmt.Errorf("%w: %s uses the 386 assembler's legacy numeric branch relocation and requires final text layout", ErrProbeNeedsContext, ins.Raw) + } + if arch == ArchARM && normalizeInstructionOpcode(ins.Op) == "RFE" { + return fmt.Errorf("%w: %s returns through privileged exception state", ErrProbeNeedsContext, ins.Raw) + } + if arch == ArchARM64 { + op := normalizeInstructionOpcode(ins.Op) + if op == "ADR" || op == "ADRP" { + return fmt.Errorf("%w: %s requires the final function-local label layout", ErrProbeNeedsContext, ins.Raw) + } + switch op { + case "TLBI", "SYS", "SYSL", "DCPS1", "DCPS2", "DCPS3", "DRPS", "ERET", "HLT", "HVC", "SMC": + return fmt.Errorf("%w: %s depends on privileged ARM64 execution state", ErrProbeNeedsContext, ins.Raw) + } + } for _, arg := range ins.Args { switch arg.Kind { case OpFP, OpFPAddr: @@ -421,21 +441,52 @@ func ProbeInstruction(arch Arch, goarch string, ins Instr) error { } } - fn := Func{Sym: "plan9asm.probe", Instrs: []Instr{ins}} + err := probeInstructionSequence(arch, goarch, []Instr{ins}) + if arch == ArchARM && ins.Op == OpWORD && err != nil { + return fmt.Errorf("%w: %s requires surrounding instruction, register, and control-flow state: %v", ErrProbeNeedsContext, ins.Raw, err) + } + return err +} + +// ProbeInstructionSequence runs a self-contained instruction sequence through +// the real lowering pipeline. Coverage scanners use this for forms whose +// meaning spans source directives, such as consecutive x86 BYTE/WORD/LONG/QUAD +// directives that encode one or more machine instructions. +func ProbeInstructionSequence(arch Arch, goarch string, instrs []Instr) error { + if len(instrs) == 0 { + return fmt.Errorf("empty instruction probe sequence") + } + if arch == ArchWASM { + return fmt.Errorf("%w: wasm instructions require their full function", ErrProbeNeedsContext) + } + return probeInstructionSequence(arch, goarch, instrs) +} + +func probeInstructionSequence(arch Arch, goarch string, instrs []Instr) error { + fn := Func{Sym: "plan9asm.probe", Instrs: append([]Instr(nil), instrs...)} labels := map[string]struct{}{} + definedLabels := map[string]struct{}{} sigs := map[string]FuncSig{ fn.Sym: {Name: fn.Sym, Ret: Void}, } - for _, arg := range ins.Args { - if arg.Kind == OpLabel { - labels[arg.Sym] = struct{}{} - } - if arg.Kind == OpSym && (ins.Op == OpCALL || ins.Op == OpJMP || normalizeInstructionOpcode(ins.Op) == "CALLNORESUME") { - name := strings.TrimSuffix(arg.Sym, "(SB)") - sigs[name] = FuncSig{Name: name, Ret: Void} + for _, ins := range instrs { + for _, arg := range ins.Args { + if arg.Kind == OpLabel { + labels[arg.Sym] = struct{}{} + if ins.Op == OpLABEL { + definedLabels[arg.Sym] = struct{}{} + } + } + if arg.Kind == OpSym && (ins.Op == OpCALL || ins.Op == OpJMP || normalizeInstructionOpcode(ins.Op) == "CALLNORESUME") { + name := strings.TrimSuffix(arg.Sym, "(SB)") + sigs[name] = FuncSig{Name: name, Ret: Void} + } } } for label := range labels { + if _, ok := definedLabels[label]; ok { + continue + } fn.Instrs = append(fn.Instrs, Instr{Op: OpLABEL, Args: []Operand{{Kind: OpLabel, Sym: label}}, Raw: label + ":"}) } fn.Instrs = append(fn.Instrs, Instr{Op: OpRET, Raw: "RET"}) diff --git a/internal/asmsig/forward.go b/internal/asmsig/forward.go new file mode 100644 index 00000000..7c2e1655 --- /dev/null +++ b/internal/asmsig/forward.go @@ -0,0 +1,86 @@ +// Package asmsig contains signature inference shared by the command drivers. +package asmsig + +import ( + "reflect" + "strconv" + "strings" + + "github.com/xgo-dev/plan9asm" +) + +// RefineTailForwarders gives declaration-free, pure tail stubs the ABI of +// their destination. known protects signatures established by declarations or +// other reliable ABI evidence. Explicit FP slots also provide usable evidence +// when build tags hide the Go declarations but keep the assembly selected. +// Existing signatures with no such evidence are not invented or discarded. +func RefineTailForwarders(file *plan9asm.File, sigs map[string]plan9asm.FuncSig, resolve func(string) string, known map[string]bool) { + evidence := make(map[string]bool, len(known)) + for name, value := range known { + evidence[name] = value + } + // Iteration resolves chains independent of source order. Cycles without + // any frame/declaration evidence remain unresolved. + for pass := 0; pass < len(file.Funcs); pass++ { + changed := false + for _, fn := range file.Funcs { + caller := resolve(fn.Sym) + if known[caller] { + continue + } + symbol, pure := pureTailTarget(fn) + if !pure { + continue + } + targetName := resolve(symbol) + target, ok := sigs[targetName] + if !ok || (!evidence[targetName] && len(target.Frame.Params) == 0 && len(target.Frame.Results) == 0) { + continue + } + target.Name = caller + if !reflect.DeepEqual(sigs[caller], target) || !evidence[caller] { + sigs[caller] = target + evidence[caller] = true + changed = true + } + } + if !changed { + break + } + } +} + +func pureTailTarget(fn plan9asm.Func) (string, bool) { + target := "" + for _, ins := range fn.Instrs { + op := strings.ToUpper(string(ins.Op)) + switch op { + case "TEXT", "PCDATA", "FUNCDATA": + continue + case "RET": + if target != "" && len(ins.Args) == 0 { + continue // Unreachable after the unconditional tail transfer. + } + case "JMP", "B": + default: + return "", false + } + if target != "" || len(ins.Args) != 1 || ins.Args[0].Kind != plan9asm.OpSym { + return "", false + } + sym := strings.TrimSpace(ins.Args[0].Sym) + if !strings.HasSuffix(sym, "(SB)") { + return "", false + } + target = strings.TrimSuffix(sym, "(SB)") + if i := strings.LastIndexAny(target, "+-"); i > 0 { + if offset, err := strconv.ParseInt(strings.TrimSpace(target[i:]), 0, 64); err == nil { + if offset != 0 { + return "", false + } + target = strings.TrimSpace(target[:i]) + } + } + } + return target, target != "" +} diff --git a/internal/asmsig/forward_test.go b/internal/asmsig/forward_test.go new file mode 100644 index 00000000..a8183079 --- /dev/null +++ b/internal/asmsig/forward_test.go @@ -0,0 +1,64 @@ +package asmsig + +import ( + "reflect" + "testing" + + "github.com/xgo-dev/plan9asm" +) + +func TestRefineTailForwardersEvidenceAndPurity(t *testing.T) { + for _, tc := range []struct { + name, body string + knownCaller, knownTarget, frame, want bool + }{ + {name: "frame", body: "JMP target(SB)", frame: true, want: true}, + {name: "declaration", body: "JMP target(SB)", knownTarget: true, want: true}, + {name: "zero_offset", body: "JMP target+0(SB)", frame: true, want: true}, + {name: "ret_symbol", body: "RET target(SB)", frame: true, want: true}, + {name: "dead_ret", body: "JMP target(SB)\nRET", frame: true, want: true}, + {name: "unknown", body: "JMP target(SB)"}, + {name: "protected", body: "JMP target(SB)", knownCaller: true, frame: true}, + {name: "writes_register", body: "MOVQ $1, AX\nJMP target(SB)", frame: true}, + {name: "call", body: "CALL target(SB)\nRET", frame: true}, + {name: "offset", body: "JMP target+8(SB)", frame: true}, + {name: "indirect", body: "JMP AX", frame: true}, + {name: "conditional", body: "JEQ target(SB)", frame: true}, + {name: "multiple", body: "JMP target(SB)\nJMP other(SB)", frame: true}, + } { + t.Run(tc.name, func(t *testing.T) { + file, err := plan9asm.Parse(plan9asm.ArchAMD64, "TEXT caller(SB),$0\n"+tc.body+"\n") + if err != nil { + t.Fatal(err) + } + caller := plan9asm.FuncSig{Name: "caller", Ret: plan9asm.I64} + target := plan9asm.FuncSig{Name: "target", Ret: plan9asm.Void} + if tc.frame { + target.Args = []plan9asm.LLVMType{plan9asm.Ptr} + target.Frame.Params = []plan9asm.FrameSlot{{Type: plan9asm.Ptr, Field: -1}} + } + sigs := map[string]plan9asm.FuncSig{"caller": caller, "target": target} + RefineTailForwarders(file, sigs, func(s string) string { return s }, map[string]bool{"caller": tc.knownCaller, "target": tc.knownTarget}) + want := caller + if tc.want { + want = target + want.Name = "caller" + } + if !reflect.DeepEqual(sigs["caller"], want) { + t.Fatalf("got %#v, want %#v", sigs["caller"], want) + } + }) + } +} + +func TestRefineTailForwardersUnprovenCycle(t *testing.T) { + file, err := plan9asm.Parse(plan9asm.ArchAMD64, "TEXT a(SB),$0\nJMP b(SB)\nTEXT b(SB),$0\nJMP a(SB)\n") + if err != nil { + t.Fatal(err) + } + sigs := map[string]plan9asm.FuncSig{"a": {Name: "a", Ret: plan9asm.I64}, "b": {Name: "b", Ret: plan9asm.I32}} + RefineTailForwarders(file, sigs, func(s string) string { return s }, nil) + if sigs["a"].Ret != plan9asm.I64 || sigs["b"].Ret != plan9asm.I32 { + t.Fatal("unproven cycle changed signatures") + } +} diff --git a/internal/discoverymeta/filename.go b/internal/discoverymeta/filename.go new file mode 100644 index 00000000..f3aaf924 --- /dev/null +++ b/internal/discoverymeta/filename.go @@ -0,0 +1,115 @@ +// Package discoverymeta interprets the build-selection information that can be +// recovered from assembly file names without downloading a module again. +package discoverymeta + +import ( + "fmt" + "path" + "sort" + "strings" +) + +var knownGOOS = []string{ + "aix", "android", "darwin", "dragonfly", "freebsd", "illumos", "ios", "js", + "linux", "netbsd", "openbsd", "plan9", "solaris", "wasip1", "windows", +} + +var knownGOARCH = []string{ + "386", "amd64", "arm", "arm64", "loong64", "mips", "mips64", "mips64le", + "mipsle", "ppc64", "ppc64le", "riscv64", "s390x", "wasm", +} + +// InferArchitecture returns the GOARCH suffix encoded by a Go assembly file +// name. Unknown includes portable names and custom suffixes such as amd64x. +func InferArchitecture(name string) string { + stem := strings.TrimSuffix(path.Base(name), path.Ext(name)) + if architecture, ok := filenameSuffix(stem, knownGOARCH); ok { + return architecture + } + return "unknown" +} + +// ArchitectureHints returns deterministic module-level hints derived from all +// recorded assembly paths. The hints include Go ports plan9asm does not yet +// support so a future platform can be selected from the existing ledger. +func ArchitectureHints(files []string) []string { + set := make(map[string]bool) + for _, name := range files { + set[InferArchitecture(name)] = true + } + return sortedSet(set) +} + +// FilterAssemblyFiles returns paths that may be selected by at least one +// target according to Go's filename suffix convention. It only rejects a file +// when the suffix conclusively names another GOOS or GOARCH. Unknown/custom +// names remain eligible so source build constraints can be checked after the +// recorded exact module version is fetched. +func FilterAssemblyFiles(files, targets []string) ([]string, error) { + type targetPair struct{ goos, goarch string } + pairs := make([]targetPair, 0, len(targets)) + allOS := append([]string(nil), knownGOOS...) + allArch := append([]string(nil), knownGOARCH...) + for _, target := range targets { + parts := strings.Split(target, "/") + if len(parts) != 2 || parts[0] == "" || parts[1] == "" { + return nil, fmt.Errorf("invalid discovery target %q", target) + } + pairs = append(pairs, targetPair{goos: parts[0], goarch: parts[1]}) + allOS = append(allOS, parts[0]) + allArch = append(allArch, parts[1]) + } + allOS = uniqueSorted(allOS) + allArch = uniqueSorted(allArch) + + set := make(map[string]bool) + for _, name := range files { + for _, target := range pairs { + if filenameMayMatch(name, target.goos, target.goarch, allOS, allArch) { + set[name] = true + break + } + } + } + return sortedSet(set), nil +} + +func filenameMayMatch(name, goos, goarch string, allOS, allArch []string) bool { + stem := strings.TrimSuffix(path.Base(name), path.Ext(name)) + if suffix, ok := filenameSuffix(stem, allArch); ok { + if suffix != goarch { + return false + } + stem = strings.TrimSuffix(stem, "_"+suffix) + } + if suffix, ok := filenameSuffix(stem, allOS); ok && suffix != goos { + return false + } + return true +} + +func filenameSuffix(stem string, values []string) (string, bool) { + for _, value := range values { + if strings.HasSuffix(stem, "_"+value) { + return value, true + } + } + return "", false +} + +func uniqueSorted(values []string) []string { + set := make(map[string]bool, len(values)) + for _, value := range values { + set[value] = true + } + return sortedSet(set) +} + +func sortedSet(set map[string]bool) []string { + values := make([]string, 0, len(set)) + for value := range set { + values = append(values, value) + } + sort.Strings(values) + return values +} diff --git a/internal/discoverymeta/filename_test.go b/internal/discoverymeta/filename_test.go new file mode 100644 index 00000000..0f549222 --- /dev/null +++ b/internal/discoverymeta/filename_test.go @@ -0,0 +1,59 @@ +package discoverymeta + +import ( + "reflect" + "testing" +) + +func TestArchitectureHintsCoverCurrentAndFuturePlan9asmPorts(t *testing.T) { + files := []string{ + "asm_amd64.s", + "asm_loong64.s", + "asm_ppc64le.s", + "asm_riscv64.s", + "asm_s390x.s", + "asm_mips64x.s", + "portable.s", + } + want := []string{"amd64", "loong64", "ppc64le", "riscv64", "s390x", "unknown"} + if got := ArchitectureHints(files); !reflect.DeepEqual(got, want) { + t.Fatalf("ArchitectureHints() = %#v, want %#v", got, want) + } +} + +func TestFilterAssemblyFilesForNewTargetIsConservative(t *testing.T) { + files := []string{ + "asm_amd64.s", + "asm_linux_riscv64.s", + "asm_plan9_riscv64.s", + "asm_linux.s", + "asm_windows.s", + "asm_amd64x.s", + "portable.s", + } + want := []string{"asm_amd64x.s", "asm_linux.s", "asm_linux_riscv64.s", "portable.s"} + got, err := FilterAssemblyFiles(files, []string{"linux/riscv64"}) + if err != nil { + t.Fatal(err) + } + if !reflect.DeepEqual(got, want) { + t.Fatalf("FilterAssemblyFiles() = %#v, want %#v", got, want) + } +} + +func TestFilterAssemblyFilesAcceptsAPlatformNewerThanKnownLists(t *testing.T) { + got, err := FilterAssemblyFiles([]string{"asm_newos_newarch.s", "asm_linux_amd64.s"}, []string{"newos/newarch"}) + if err != nil { + t.Fatal(err) + } + want := []string{"asm_newos_newarch.s"} + if !reflect.DeepEqual(got, want) { + t.Fatalf("FilterAssemblyFiles() = %#v, want %#v", got, want) + } +} + +func TestFilterAssemblyFilesRejectsInvalidTarget(t *testing.T) { + if _, err := FilterAssemblyFiles([]string{"portable.s"}, []string{"linux"}); err == nil { + t.Fatal("FilterAssemblyFiles() accepted an invalid target") + } +} diff --git a/native_arm64_object_test.go b/native_arm64_object_test.go index 97c4dc0c..2e8aad38 100644 --- a/native_arm64_object_test.go +++ b/native_arm64_object_test.go @@ -1,6 +1,7 @@ package plan9asm import ( + "debug/macho" "encoding/binary" "os" "os/exec" @@ -47,6 +48,10 @@ DATA ·mixedEntry(SB)/8, $mixedtramp<>(SB) } func TestNativeARM64Object(t *testing.T) { + clang := findLLVM22Tool("clang") + if clang == "" { + t.Fatal("LLVM 22 clang not found") + } obj := nativeObjectFixture(t) funcs := map[string]bool{"callback": true, "mixedtramp": true} imports := map[string]string{"imported_strlen": "strlen", "imported_mixed": "mixed"} @@ -90,16 +95,32 @@ func TestNativeARM64Object(t *testing.T) { t.Fatal("accepted unknown relocation") } }) - if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { - return - } dir := t.TempDir() s := filepath.Join(dir, "native.s") - c := filepath.Join(dir, "main.c") - exe := filepath.Join(dir, "probe") + object := filepath.Join(dir, "native.o") if err := os.WriteFile(s, []byte(asm), 0600); err != nil { t.Fatal(err) } + // Every host must compile and inspect the supported Darwin ARM64 object. + // Only the executable runtime check below depends on the host platform. + cmd := exec.Command(clang, "--target=arm64-apple-darwin", "-c", s, "-o", object) + if b, err := cmd.CombinedOutput(); err != nil { + t.Fatalf("LLVM 22 ARM64 object compilation: %v\n%s", err, b) + } + machObject, err := macho.Open(object) + if err != nil { + t.Fatal(err) + } + defer machObject.Close() + if machObject.Cpu != macho.CpuArm64 || machObject.Type != macho.TypeObj { + t.Fatalf("unexpected object format: CPU=%v type=%v", machObject.Cpu, machObject.Type) + } + if runtime.GOOS != "darwin" || runtime.GOARCH != "arm64" { + t.Log("LLVM 22 ARM64 object compiled; native execution requires darwin/arm64") + return + } + c := filepath.Join(dir, "main.c") + exe := filepath.Join(dir, "probe") if err := os.WriteFile(c, []byte(`extern void *entry __asm("_probe.entry"); extern void *mixedEntry __asm("_probe.mixedEntry"); unsigned long mixed(unsigned long x, double y) { return x + (unsigned long)y; } @@ -110,7 +131,7 @@ int main(void) { `), 0600); err != nil { t.Fatal(err) } - cmd := exec.Command("clang", s, c, "-o", exe) + cmd = exec.Command(clang, object, c, "-o", exe) if b, err := cmd.CombinedOutput(); err != nil { t.Fatalf("link: %v\n%s", err, b) } @@ -119,6 +140,27 @@ int main(void) { } } +func TestNativeARM64ObjectRequiresLLVM22(t *testing.T) { + executable, err := os.Executable() + if err != nil { + t.Fatal(err) + } + cmd := exec.Command(executable, "-test.run=^TestNativeARM64Object$", "-test.v") + for _, variable := range os.Environ() { + if !strings.HasPrefix(strings.ToUpper(variable), "LLVM_CONFIG=") { + cmd.Env = append(cmd.Env, variable) + } + } + cmd.Env = append(cmd.Env, "LLVM_CONFIG="+filepath.Join(t.TempDir(), "missing-llvm-config")) + output, err := cmd.CombinedOutput() + if err == nil { + t.Fatalf("native ARM64 object test passed without required LLVM 22 tools:\n%s", output) + } + if !strings.Contains(string(output), "LLVM 22 clang not found") { + t.Fatalf("native ARM64 object test did not fail for the missing tool: %v\n%s", err, output) + } +} + func TestForeignARM64Selection(t *testing.T) { for _, tc := range []struct { src string diff --git a/parser.go b/parser.go index 963dd50f..7ff70e34 100644 --- a/parser.go +++ b/parser.go @@ -35,6 +35,12 @@ type Func struct { ArgSize int64 Instrs []Instr + + // X86RawText retains a byte-exact, address-sensitive raw TEXT body. It is + // populated only when another source instruction takes the body's address + // (including symbol+offset patching), so ordinary BYTE-encoded instructions + // still go through semantic decoding and validation. + X86RawText []byte } // Parse parses a subset of Go/Plan 9 assembly syntax. @@ -49,9 +55,15 @@ type Func struct { // - #define NAME with optional single-line continuation via '\' and // macro invocation when the entire statement is just NAME. func Parse(arch Arch, src string) (*File, error) { + return ParseWithDefines(arch, src, nil) +} + +// ParseWithDefines parses assembly with the same predefined symbols cmd/go +// supplies to cmd/asm (for example GOOS_windows or GOARM64_LSE). +func ParseWithDefines(arch Arch, src string, defines []string) (*File, error) { f := &File{Arch: arch} - pp, err := preprocess(src) + pp, err := preprocessWithDefines(src, defines) if err != nil { return nil, err } @@ -129,6 +141,12 @@ func Parse(arch Arch, src string) (*File, error) { if sym == "" { return nil, fmt.Errorf("line %d: empty TEXT symbol: %q", lineno, stmt) } + // Early Plan 9 assembly commonly spelled function definitions as + // TEXT ·name+0(SB). The zero is a symbol offset, not part of the + // linker name; current Go still accepts this legacy form. + if base, off := splitSymPlusOff(sym); base != sym && off == 0 { + sym = base + } frameSize, argSize, err := parseTEXTFrame(parts) if err != nil { return nil, fmt.Errorf("line %d: %v", lineno, err) @@ -327,14 +345,20 @@ func parseWidth(arch Arch, s string) (int64, error) { } func parseGLOBLStmt(rest string) (GloblStmt, error) { + // GLOBL sym(SB), $size // GLOBL sym(SB), flags, $size parts := strings.Split(rest, ",") - if len(parts) != 3 { + if len(parts) != 2 && len(parts) != 3 { return GloblStmt{}, fmt.Errorf("invalid GLOBL: %q", "GLOBL "+rest) } symPart := strings.TrimSpace(parts[0]) - flags := strings.TrimSpace(parts[1]) - sizePart := strings.TrimSpace(parts[2]) + flags := "" + sizePartIndex := 1 + if len(parts) == 3 { + flags = strings.TrimSpace(parts[1]) + sizePartIndex = 2 + } + sizePart := strings.TrimSpace(parts[sizePartIndex]) if !strings.HasSuffix(symPart, "(SB)") { return GloblStmt{}, fmt.Errorf("GLOBL symbol must end with (SB): %q", "GLOBL "+rest) } @@ -397,7 +421,7 @@ func parseOperandsCSV(arch Arch, op Op, s string) ([]Operand, error) { continue } legacy := []string{part} - if arch == ArchAMD64 && op == "SHLL" { + if arch == ArchAMD64 && (op == "SHLL" || op == "SHLQ" || op == "SHRL" || op == "SHRQ") { legacy = splitLegacyColonOperand(part) } for _, item := range legacy { @@ -419,6 +443,33 @@ func parseOperandsCSV(arch Arch, op Op, s string) ([]Operand, error) { } func parseOperandForArch(arch Arch, s string) (Operand, error) { + s = normalizeGoGRegister(arch, s) + if arch == ArchARM || arch == ArchARM64 { + s = normalizeARMParenthesizedRegisters(arch, s) + } + if arch == ArchAMD64 { + x86Operand := strings.TrimSpace(s) + // Go's x86 assembler accepts the historical AT&T-compatible indirect + // marker on register and memory branch targets (CALL *AX, JMP *(BX)). + // The marker does not change the underlying operand class. + if strings.HasPrefix(x86Operand, "*") { + indirect := strings.TrimSpace(strings.TrimPrefix(x86Operand, "*")) + if reg, ok := parseReg(indirect); ok { + return Operand{Kind: OpReg, Reg: reg}, nil + } + if mem, ok := parseMem(indirect); ok { + return Operand{Kind: OpMem, Mem: mem}, nil + } + } + reg := Reg(strings.ToUpper(x86Operand)) + switch reg { + case ES, CS, SS, DS: + return Operand{Kind: OpReg, Reg: reg}, nil + } + if _, _, ok := x86MachineRegister(reg); ok { + return Operand{Kind: OpReg, Reg: reg}, nil + } + } if arch == ArchWASM { if reg, ok := parseWASMReg(s); ok { return Operand{Kind: OpReg, Reg: reg}, nil @@ -432,7 +483,158 @@ func parseOperandForArch(arch Arch, s string) (Operand, error) { } } } - return parseOperand(s) + op, err := parseOperand(s) + if err != nil { + return Operand{}, err + } + if arch == ArchARM64 { + preserveARM64PhysicalStackPointer(s, &op) + } + return op, nil +} + +// Go's frontend assigns a different physical register to g on each ISA. +// Normalize only register positions, including an +// address immediate or indirect branch. A symbol such as g(SB) stays intact. +// The shared x86 parser also serves 386; its operand validators reject R14. +func normalizeGoGRegister(arch Arch, source string) string { + register := "" + switch arch { + case ArchAMD64: + register = "R14" + case ArchARM: + register = "R10" + case ArchARM64: + register = "R28" + default: + return source + } + s := strings.TrimSpace(source) + if s == "g" { + return register + } + if strings.HasPrefix(s, "*") && strings.TrimSpace(s[1:]) == "g" { + return "*" + register + } + for start := 0; start < len(s); { + open := strings.IndexByte(s[start:], '(') + if open < 0 { + break + } + open += start + end := strings.IndexByte(s[open+1:], ')') + if end < 0 { + break + } + end += open + 1 + inner := strings.TrimSpace(s[open+1 : end]) + reg := strings.TrimSpace(strings.SplitN(inner, "*", 2)[0]) + if reg == "g" { + replacement := register + strings.TrimPrefix(inner, "g") + s = s[:open+1] + replacement + s[end:] + end = open + 1 + len(replacement) + } + start = end + 1 + } + return s +} + +// normalizeARMParenthesizedRegisters implements the numeric register-prefix +// syntax accepted by Go's ARM assemblers, such as R(3), F(7), and V(16). +// Keeping this architecture-specific prevents a symbol such as SPR(269) from +// being mistaken for an ARM general-purpose register. +func normalizeARMParenthesizedRegisters(arch Arch, source string) string { + limits := map[string]int{} + switch arch { + case ArchARM: + limits = map[string]int{"R": 15, "F": 15} + case ArchARM64: + limits = map[string]int{"R": 30, "F": 31, "V": 31, "Z": 31, "P": 15, "PN": 15} + default: + return source + } + prefixes := []string{"PN", "R", "F", "V", "Z", "P"} + var out strings.Builder + for i := 0; i < len(source); { + matched := false + for _, prefix := range prefixes { + endPrefix := i + len(prefix) + if endPrefix >= len(source) || !strings.EqualFold(source[i:endPrefix], prefix) || source[endPrefix] != '(' { + continue + } + if i > 0 && isIdentifierByte(source[i-1]) { + continue + } + close := strings.IndexByte(source[endPrefix+1:], ')') + if close < 0 { + continue + } + close += endPrefix + 1 + numberText := strings.TrimSpace(source[endPrefix+1 : close]) + number, err := strconv.Atoi(numberText) + limit, validPrefix := limits[prefix] + if err != nil || !validPrefix || number < 0 || number > limit { + continue + } + out.WriteString(prefix) + out.WriteString(strconv.Itoa(number)) + i = close + 1 + matched = true + break + } + if matched { + continue + } + out.WriteByte(source[i]) + i++ + } + return out.String() +} + +func isIdentifierByte(ch byte) bool { + return ch == '_' || ch >= '0' && ch <= '9' || ch >= 'A' && ch <= 'Z' || ch >= 'a' && ch <= 'z' +} + +// Go's arm64 assembler distinguishes the hardware stack pointer RSP from the +// pseudo stack pointer SP. parseReg historically canonicalizes both to SP, so +// restore the distinction here where the source spelling is still available. +// This matters for exact optab validation: (RSP) is a C_ZOREG address, while a +// named local+0(SP) address is C_ZAUTO, and RSP in a paired data operand +// encodes register 31 (the zero register) rather than a writable stack pointer. +func preserveARM64PhysicalStackPointer(source string, op *Operand) { + source = strings.TrimSpace(source) + switch op.Kind { + case OpReg: + if strings.EqualFold(source, "RSP") { + op.Reg = Reg("RSP") + } + case OpMem: + if strings.Contains(strings.ToUpper(source), "(RSP)") { + if op.Mem.Base == SP { + op.Mem.Base = Reg("RSP") + } + if op.Mem.Index == SP { + op.Mem.Index = Reg("RSP") + } + } + case OpRegList: + if len(source) < 2 { + return + } + inner := strings.TrimSpace(strings.Trim(source, "()[]")) + parts := splitTopLevelCSV(inner) + index := 0 + for _, part := range parts { + regs, ok := expandRegRange(strings.TrimSpace(part)) + if !ok { + return + } + if len(regs) == 1 && strings.EqualFold(strings.TrimSpace(part), "RSP") && index < len(op.RegList) { + op.RegList[index] = Reg("RSP") + } + index += len(regs) + } + } } func parseWASMMem(s string) (mem MemRef, matched bool, err error) { diff --git a/parser_character_immediate_test.go b/parser_character_immediate_test.go new file mode 100644 index 00000000..294ffdaf --- /dev/null +++ b/parser_character_immediate_test.go @@ -0,0 +1,51 @@ +package plan9asm + +import "testing" + +func TestParseCharacterImmediateAndExpressions(t *testing.T) { + for _, tc := range []struct { + text string + want int64 + }{ + {text: "$'\\n'", want: 10}, + {text: "$'Z'", want: 'Z'}, + {text: "$'\\x7f'", want: 0x7f}, + {text: "$'\\377'", want: 0xff}, + {text: "$'\\u03bb'", want: '\u03bb'}, + {text: "$'A'+1", want: 'B'}, + {text: "$('A' * 2)", want: 130}, + } { + t.Run(tc.text, func(t *testing.T) { + op, err := parseOperand(tc.text) + if err != nil { + t.Fatal(err) + } + if op.Kind != OpImm || op.Imm != tc.want || op.ImmRaw != "" { + t.Fatalf("parseOperand(%q) = %#v, want immediate %d", tc.text, op, tc.want) + } + }) + } +} + +func TestParseRejectsInvalidCharacterImmediate(t *testing.T) { + for _, text := range []string{"$''", "$'ab'", "$'\\q'", "$'unterminated"} { + t.Run(text, func(t *testing.T) { + if _, err := parseOperand(text); err == nil { + t.Fatalf("parseOperand(%q) unexpectedly succeeded", text) + } + }) + } +} + +func TestParseAssemblyWithCharacterImmediate(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT character(SB),NOSPLIT,$0-0\n\tCMPB (SI), $'\\n'\n\tCMPB AX, $'Z'\n\tRET\n") + if err != nil { + t.Fatal(err) + } + if got := file.Funcs[0].Instrs[1].Args[1].Imm; got != '\n' { + t.Fatalf("newline immediate = %d, want %d", got, '\n') + } + if got := file.Funcs[0].Instrs[2].Args[1].Imm; got != 'Z' { + t.Fatalf("Z immediate = %d, want %d", got, 'Z') + } +} diff --git a/parser_data_globl_test.go b/parser_data_globl_test.go index 877534f8..34af95dc 100644 --- a/parser_data_globl_test.go +++ b/parser_data_globl_test.go @@ -81,6 +81,46 @@ GLOBL ·symptr<>(SB), NOPTR, $(machTimebaseInfo__size) } } +func TestParseLegacyTwoOperandGloblDirective(t *testing.T) { + file, err := Parse(ArchAMD64, `DATA ·REDMASK51(SB)/8, $0x0007FFFFFFFFFFFF +GLOBL ·REDMASK51(SB), $8 +DATA ·ROUNDING(SB)/2, $0x137f +GLOBL ·ROUNDING(SB), $2 +`) + if err != nil { + t.Fatal(err) + } + if got, want := len(file.Globl), 2; got != want { + t.Fatalf("len(Globl) = %d, want %d", got, want) + } + for i, want := range []GloblStmt{ + {Sym: "·REDMASK51", Size: 8}, + {Sym: "·ROUNDING", Size: 2}, + } { + if got := file.Globl[i]; got != want { + t.Fatalf("Globl[%d] = %#v, want %#v", i, got, want) + } + } + mod, err := TranslateModule(file, Options{ + Goarch: "amd64", + ResolveSym: func(sym string) string { + return "legacy." + strings.TrimPrefix(sym, "·") + }, + }) + if err != nil { + t.Fatal(err) + } + defer mod.Dispose() + for _, want := range []string{ + `@legacy.REDMASK51 = constant [8 x i8]`, + `@legacy.ROUNDING = constant [2 x i8]`, + } { + if ir := mod.String(); !strings.Contains(ir, want) { + t.Fatalf("legacy GLOBL translation missing %q:\n%s", want, ir) + } + } +} + func TestParseDataRejectsMalformedPayloads(t *testing.T) { for _, stmt := range []string{ `·missing(SB)/8 $1`, diff --git a/parser_g_register_test.go b/parser_g_register_test.go new file mode 100644 index 00000000..78bbccc9 --- /dev/null +++ b/parser_g_register_test.go @@ -0,0 +1,141 @@ +package plan9asm + +import ( + "reflect" + "runtime" + "strings" + "testing" +) + +func TestParseAMD64GRegisterAlias(t *testing.T) { + for _, tc := range []struct { + source string + want Operand + }{ + {"g", Operand{Kind: OpReg, Reg: "R14"}}, + {"*g", Operand{Kind: OpReg, Reg: "R14"}}, + {"0x30(g)", Operand{Kind: OpMem, Mem: MemRef{Base: "R14", Off: 48}}}, + {"*(g)", Operand{Kind: OpMem, Mem: MemRef{Base: "R14"}}}, + {"8(BX)(g*4)", Operand{Kind: OpMem, Mem: MemRef{Base: BX, Index: "R14", Scale: 4, Off: 8}}}, + {"g<>(SB)(g*8)", Operand{Kind: OpMem, Mem: MemRef{Sym: "g<>(SB)", Index: "R14", Scale: 8}}}, + {"$8(g)", Operand{Kind: OpSym, Sym: "$8(R14)"}}, + {"g(SB)", Operand{Kind: OpSym, Sym: "g(SB)"}}, + {"$g(SB)", Operand{Kind: OpSym, Sym: "$g(SB)"}}, + } { + t.Run(tc.source, func(t *testing.T) { + got, err := parseOperandForArch(ArchAMD64, tc.source) + if err != nil || !reflect.DeepEqual(got, tc.want) { + t.Fatalf("parseOperandForArch(%q) = %#v, %v; want %#v", tc.source, got, err, tc.want) + } + }) + } + for _, tc := range []struct { + arch Arch + want Reg + }{{ArchARM, "R10"}, {ArchARM64, "R28"}, {ArchWASM, "G"}} { + got, err := parseOperandForArch(tc.arch, "g") + if err != nil || got.Reg != tc.want { + t.Errorf("%s g = %#v, %v; want %s", tc.arch, got, err, tc.want) + } + } +} + +func TestTranslateAMD64GRegisterAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + const source = "TEXT gforms(SB),$0-0\n\tMOVQ 0x30(g), AX\n\tMOVQ g, CX\n\tMOVQ AX, g\n\tMOVQ 8(BX)(g*4), AX\n\tPUSHQ g\n\tPOPQ g\n\tRET\n" + requireX86GoAssemblerResult(t, "amd64", source, true) + for _, triple := range []string{"x86_64-apple-darwin", "x86_64-unknown-linux-gnu", "x86_64-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: triple, Sigs: map[string]FuncSig{"gforms": {Name: "gforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + if strings.Contains(ir, "R28") { + t.Fatal("amd64 g used ARM64's R28") + } + compileLLVMToObject(t, llc, triple, "g-alias.ll", "g-alias.o", ir) + }) + } + bad := "TEXT bad(SB),$0-0\n\tPUSHL g\n\tRET\n" + requireX86GoAssemblerResult(t, "386", bad, false) + file, err := Parse(ArchAMD64, bad) + if err != nil { + t.Fatal(err) + } + if _, err := Translate(file, Options{Goarch: "386", Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}}); err == nil { + t.Fatal("386 accepted amd64 g") + } +} + +func TestAMD64GRegisterRuntime(t *testing.T) { + crossRosetta := runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" && rosettaAvailable() + if runtime.GOARCH != "amd64" && !crossRosetta { + t.Skip("runtime execution test requires amd64 or Rosetta") + } + llc, clang, ok := findLlcAndClang(t) + if !ok { + t.Fatal("LLVM 22 llc/clang not found") + } + const source = `TEXT galias(SB),$0-16 + MOVQ input+0(FP), g + PUSHQ g + MOVQ $0, g + POPQ g + MOVQ 8(g), AX + MOVQ AX, ret+8(FP) + RET +` + requireX86GoAssemblerResult(t, "amd64", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + triple := testTargetTriple(runtime.GOOS, runtime.GOARCH) + var runPrefix []string + if crossRosetta { + triple, runPrefix = "x86_64-apple-macosx", []string{"/usr/bin/arch", "-x86_64"} + } + ir, err := Translate(file, Options{Goarch: "amd64", TargetTriple: triple, Sigs: map[string]FuncSig{ + "galias": {Name: "galias", Args: []LLVMType{Ptr}, Ret: I64, Frame: FrameLayout{ + Params: []FrameSlot{{Offset: 0, Type: Ptr, Index: 0, Field: -1}}, + Results: []FrameSlot{{Offset: 8, Type: I64, Index: 0, Field: -1}}, + }}, + }}) + if err != nil { + t.Fatal(err) + } + const mainC = "#include \nextern uint64_t galias(uint64_t *);\nint main(void) { uint64_t v[2] = {9, 0x12345678}; return galias(v) == v[1] ? 0 : 1; }\n" + compileAndRunRuntimeTestForTarget(t, llc, clang, "g_alias", triple, ir, mainC, runPrefix) +} + +func TestTranslateARMGRegisterAcrossTargets(t *testing.T) { + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + const source = "TEXT gforms(SB),$0-0\n\tMOVW g, R0\n\tMOVW 8(g), R1\n\tMOVW R0, g\n\tRET\n" + requireARMGoAssemblerResult(t, source, true) + file, err := Parse(ArchARM, source) + if err != nil { + t.Fatal(err) + } + if got := file.Funcs[0].Instrs[2].Args[0]; got.Kind != OpMem || got.Mem.Base != "R10" { + t.Fatalf("ARM g memory = %#v; want R10 base", got) + } + for _, triple := range []string{"armv7-unknown-linux-gnueabihf", "thumbv7-pc-windows-msvc"} { + t.Run(triple, func(t *testing.T) { + ir, err := Translate(file, Options{Goarch: "arm", TargetTriple: triple, Sigs: map[string]FuncSig{"gforms": {Name: "gforms", Ret: Void}}}) + if err != nil { + t.Fatal(err) + } + compileLLVMToObject(t, llc, triple, "arm-g.ll", "arm-g.o", ir) + }) + } +} diff --git a/parser_test.go b/parser_test.go index 90a0d3de..40fa8f8d 100644 --- a/parser_test.go +++ b/parser_test.go @@ -34,6 +34,16 @@ RET } } +func TestParseNormalizesLegacyZeroTextSymbolOffset(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT ·Sqrtf+0(SB),NOSPLIT,$0-8\nRET\n") + if err != nil { + t.Fatal(err) + } + if got := file.Funcs[0].Sym; got != "·Sqrtf" { + t.Fatalf("TEXT symbol = %q, want %q", got, "·Sqrtf") + } +} + func TestParseDefineAndSemicolons(t *testing.T) { src := ` #define X BYTE $0x01; BYTE $0x02 @@ -252,6 +262,46 @@ RET } } +func TestParseArithmeticOffsetBeforeBaseRegister(t *testing.T) { + file, err := Parse(ArchAMD64, ` +TEXT arithmeticOffset(SB),NOSPLIT,$0-0 + ADDQ 0+(1*16)(BP), R10 + MOVQ (-64*1024+104)(SP), AX + RET +`) + if err != nil { + t.Fatal(err) + } + first := file.Funcs[0].Instrs[1].Args[0] + if first.Kind != OpMem || first.Mem.Base != BP || first.Mem.Off != 16 { + t.Fatalf("first operand = %#v, want 16(BP)", first) + } + second := file.Funcs[0].Instrs[2].Args[0] + if second.Kind != OpMem || second.Mem.Base != SP || second.Mem.Off != -65432 { + t.Fatalf("second operand = %#v, want -65432(SP)", second) + } +} + +func TestParseX86TLSPseudoRegisterAndRelocationIndex(t *testing.T) { + file, err := Parse(ArchAMD64, ` +TEXT tlsforms(SB),NOSPLIT,$0-0 + MOVQ TLS, CX + MOVQ 0(CX)(TLS*1), BX + RET +`) + if err != nil { + t.Fatal(err) + } + loadBase := file.Funcs[0].Instrs[1].Args[0] + if loadBase.Kind != OpReg || loadBase.Reg != Reg("TLS") { + t.Fatalf("TLS source = %#v, want TLS pseudo-register", loadBase) + } + indexed := file.Funcs[0].Instrs[2].Args[0] + if indexed.Kind != OpMem || indexed.Mem.Base != CX || indexed.Mem.Index != Reg("TLS") || indexed.Mem.Scale != 1 { + t.Fatalf("TLS relocation memory = %#v, want 0(CX)(TLS*1)", indexed) + } +} + func TestParseFunctionLikeMacroCall(t *testing.T) { src := ` #define ROUND1(a,b) MOVL a, b; ADDL $1, b diff --git a/preprocess.go b/preprocess.go index 4bcbbc7d..502edad6 100644 --- a/preprocess.go +++ b/preprocess.go @@ -3,6 +3,7 @@ package plan9asm import ( "bufio" "fmt" + "os" "sort" "strings" ) @@ -18,7 +19,61 @@ type ppMacro struct { // - supports #define NAME with optional single-line continuation via '\' // - expands macros only when a statement is exactly NAME func preprocess(src string) (string, error) { + return preprocessWithDefines(src, nil) +} + +// GoAssemblerDefines returns the predefined symbols cmd/go passes to cmd/asm. +// The feature values come from the same GO* environment variables used to +// select files and configure the assembler invocation. +func GoAssemblerDefines(goos, goarch string) []string { + defines := []string{} + if goos != "" { + defines = append(defines, "GOOS_"+goos) + } + if goarch != "" { + defines = append(defines, "GOARCH_"+goarch) + } + switch goarch { + case "386": + value := os.Getenv("GO386") + if value == "" { + value = "sse2" + } + defines = append(defines, "GO386_"+value) + case "amd64": + value := os.Getenv("GOAMD64") + if value == "" { + value = "v1" + } + defines = append(defines, "GOAMD64_"+value) + case "arm": + value := os.Getenv("GOARM") + if value == "" { + value = "7" + } + if strings.Contains(value, "7") { + defines = append(defines, "GOARM_7") + } + if strings.Contains(value, "6") || strings.Contains(value, "7") { + defines = append(defines, "GOARM_6") + } + defines = append(defines, "GOARM_5") + case "arm64": + if strings.Contains(os.Getenv("GOARM64"), ",lse") { + defines = append(defines, "GOARM64_LSE") + } + } + return defines +} + +func preprocessWithDefines(src string, defines []string) (string, error) { macros := map[string]ppMacro{} + for _, name := range defines { + name = strings.TrimSpace(name) + if name != "" { + macros[name] = ppMacro{body: "1"} + } + } type ifState struct { outerActive bool @@ -91,7 +146,12 @@ func preprocess(src string) (string, error) { lineno := 0 for sc.Scan() { lineno++ - line := sc.Text() + rawLine := sc.Text() + // C-style preprocessing splices a physical backslash-newline before + // removing comments. Record it before the comment pass below can erase + // the slash from a continued multi-line #define. + physicalContinuation := strings.HasSuffix(strings.TrimRight(rawLine, " \t\r"), "\\") + line := rawLine // Strip C-style /* ... */ comments (may span lines). Some stdlib asm uses // these in addition to // comments. for { @@ -126,18 +186,15 @@ func preprocess(src string) (string, error) { line = line[:idx] } line = strings.TrimRight(line, " \t") - if strings.TrimSpace(line) == "" { - if err := flushDefine(); err != nil { - return "", fmt.Errorf("line %d: %v", lineno, err) - } - continue - } - + // cmd/asm also accepts historical assembly that places a // comment + // after the continuation slash. In that spelling the slash only becomes + // the last token after comment removal (for example "MOVQ ... \\ // why"). + physicalContinuation = physicalContinuation || strings.HasSuffix(line, "\\") if defCont { // Continue a definition body on the following line(s). if !active { // Discard bodies from inactive blocks. - if strings.HasSuffix(strings.TrimSpace(line), "\\") { + if physicalContinuation { continue } if err := flushDefine(); err != nil { @@ -146,8 +203,8 @@ func preprocess(src string) (string, error) { continue } cont := strings.TrimSpace(line) - if strings.HasSuffix(cont, "\\") { - // Continuation to the next line. + if physicalContinuation { + // Comment removal may already have removed the slash. cont = strings.TrimSpace(strings.TrimSuffix(cont, "\\")) defBody.WriteString("\n") defBody.WriteString(cont) @@ -160,6 +217,9 @@ func preprocess(src string) (string, error) { } continue } + if strings.TrimSpace(line) == "" { + continue + } trim := strings.TrimSpace(line) if strings.HasPrefix(trim, "#include") || strings.HasPrefix(trim, "#undef") { @@ -246,7 +306,7 @@ func preprocess(src string) (string, error) { } defName = name defParams = params - if strings.HasSuffix(afterName, "\\") { + if physicalContinuation { afterName = strings.TrimSpace(strings.TrimSuffix(afterName, "\\")) defBody.WriteString(afterName) defCont = true @@ -284,13 +344,98 @@ func preprocess(src string) (string, error) { } // Expand longer names first to reduce prefix shadowing. sort.Slice(macroNames, func(i, j int) bool { return len(macroNames[i]) > len(macroNames[j]) }) - var out strings.Builder + var expanded []string for _, line := range lines { for _, ex := range expandPPLine(line, macros, macroNames, 0) { - out.WriteString(ex) - out.WriteString("\n") + expanded = append(expanded, ex) } } + + // Some Go assembly deliberately places conditionals inside a continued + // macro body (runtime's ARM64 BREAK macro is the canonical example). Those + // directives become visible only after macro expansion, so evaluate a + // second conditional pass instead of leaking them into the instruction + // stream. + active = true + ifStack = nil + expandedOpen := []string{} + var out strings.Builder + for i, line := range expanded { + trim := strings.TrimSpace(line) + switch { + case strings.HasPrefix(trim, "#ifdef"): + name := strings.TrimSpace(strings.TrimPrefix(trim, "#ifdef")) + if name == "" { + return "", fmt.Errorf("expanded line %d: invalid #ifdef: %q", i+1, line) + } + st := ifState{outerActive: active, cond: isDefined(name)} + ifStack = append(ifStack, st) + expandedOpen = append(expandedOpen, trim) + active = active && st.cond + continue + case strings.HasPrefix(trim, "#ifndef"): + name := strings.TrimSpace(strings.TrimPrefix(trim, "#ifndef")) + if name == "" { + return "", fmt.Errorf("expanded line %d: invalid #ifndef: %q", i+1, line) + } + st := ifState{outerActive: active, cond: !isDefined(name)} + ifStack = append(ifStack, st) + expandedOpen = append(expandedOpen, trim) + active = active && st.cond + continue + case strings.HasPrefix(trim, "#if"): + expr := strings.TrimSpace(strings.TrimPrefix(trim, "#if")) + st := ifState{outerActive: active, cond: evalIfExpr(expr)} + ifStack = append(ifStack, st) + expandedOpen = append(expandedOpen, trim) + active = active && st.cond + continue + case strings.HasPrefix(trim, "#elif"): + if len(ifStack) == 0 { + return "", fmt.Errorf("expanded line %d: stray #elif", i+1) + } + top := ifStack[len(ifStack)-1] + if top.inElse { + return "", fmt.Errorf("expanded line %d: #elif after #else", i+1) + } + if top.cond { + active = false + continue + } + top.cond = evalIfExpr(strings.TrimSpace(strings.TrimPrefix(trim, "#elif"))) + ifStack[len(ifStack)-1] = top + active = top.outerActive && top.cond + continue + case strings.HasPrefix(trim, "#else"): + if len(ifStack) == 0 { + return "", fmt.Errorf("expanded line %d: stray #else", i+1) + } + top := ifStack[len(ifStack)-1] + if top.inElse { + return "", fmt.Errorf("expanded line %d: duplicate #else", i+1) + } + top.inElse = true + ifStack[len(ifStack)-1] = top + active = top.outerActive && !top.cond + continue + case strings.HasPrefix(trim, "#endif"): + if len(ifStack) == 0 { + return "", fmt.Errorf("expanded line %d: stray #endif", i+1) + } + top := ifStack[len(ifStack)-1] + ifStack = ifStack[:len(ifStack)-1] + expandedOpen = expandedOpen[:len(expandedOpen)-1] + active = top.outerActive + continue + } + if active { + out.WriteString(line) + out.WriteByte('\n') + } + } + if len(ifStack) != 0 { + return "", fmt.Errorf("unterminated expanded #if block: %s", strings.Join(expandedOpen, ", ")) + } return out.String(), nil } @@ -298,10 +443,24 @@ func expandPPLine(line string, macros map[string]ppMacro, macroNames []string, d if depth >= 16 { return []string{line} } + if strings.Contains(line, "\n") { + chunks := strings.Split(line, "\n") + out := make([]string, 0, len(chunks)) + for _, chunk := range chunks { + out = append(out, expandPPLine(strings.TrimSpace(chunk), macros, macroNames, depth+1)...) + } + return out + } trimLine := strings.TrimSpace(line) if trimLine == "" { return []string{""} } + // Conditional directives embedded in a continued macro are evaluated by + // preprocessWithDefines after expansion. Their identifiers are macro names, + // not replacement tokens; keep the directive text intact for that pass. + if strings.HasPrefix(trimLine, "#") { + return []string{trimLine} + } for _, name := range macroNames { m := macros[name] if m.params == nil { @@ -370,7 +529,7 @@ func ppIsIdentChar(ch byte) bool { return (ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z') || (ch >= '0' && ch <= '9') || - ch == '_' + ch == '_' || ch >= 0x80 } func expandIdentMacros(line string, macros map[string]ppMacro, macroNames []string) (string, bool) { @@ -597,7 +756,10 @@ func expandInlineMacroCalls(line, name string, m ppMacro) (string, bool) { } j += i // Identifier boundary check on the left side. - if j > 0 && isIdentPart(line[j-1]) { + // Go assembler symbols commonly prefix package-local names with the + // UTF-8 middle dot. Treat non-ASCII bytes as identifier bytes here so a + // macro named g expands in g(CX), but not inside TEXT ·g(SB). + if j > 0 && ppIsIdentChar(line[j-1]) { out.WriteString(line[i : j+1]) i = j + 1 continue diff --git a/preprocess_test.go b/preprocess_test.go index 2e924a86..6f93a291 100644 --- a/preprocess_test.go +++ b/preprocess_test.go @@ -31,3 +31,139 @@ TEXT foo(SB),NOSPLIT,$0-0 t.Fatalf("expected ROUNDS expansion, got: %q", pp) } } + +func TestPreprocessDoesNotExpandFunctionMacroInsideMiddleDotSymbol(t *testing.T) { + const src = ` +#define g(r) 0(r)(TLS*1) +TEXT ·g(SB),NOSPLIT,$0-8 + MOVQ g(CX), BX + RET +` + pp, err := preprocessWithDefines(src, []string{"GOARCH_amd64"}) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(pp, "TEXT ·g(SB),NOSPLIT,$0-8") { + t.Fatalf("function-like macro rewrote a middle-dot function symbol:\n%s", pp) + } + if !strings.Contains(pp, "MOVQ 0(CX)(TLS*1), BX") { + t.Fatalf("function-like macro call in an operand was not expanded:\n%s", pp) + } + if _, err := Parse(ArchAMD64, src); err != nil { + t.Fatalf("Parse rejected a macro whose name matches a middle-dot function symbol: %v", err) + } +} + +func TestPreprocessKeepsMultilineDefineAcrossBlockCommentsAndBlankContinuations(t *testing.T) { + // C preprocessing splices backslash-newline pairs before removing comments. + // Real assembly such as buildbarn/bb-storage relies on that ordering inside + // large function-like macros. + const src = ` +#define ROUND(dst, src) \ + MOVQ src, dst \ + /* Explain the next operation. \ + * The comment itself spans physical lines. \ + */ \ + \ + ADDQ $1, dst +TEXT macro(SB),$0-0 + ROUND(AX, BX) + RET +` + pp, err := preprocess(src) + if err != nil { + t.Fatal(err) + } + if strings.Contains(pp, "\\") { + t.Fatalf("physical continuation escaped into preprocessed assembly:\n%s", pp) + } + for _, want := range []string{"MOVQ BX, AX", "ADDQ $1, AX"} { + if !strings.Contains(pp, want) { + t.Fatalf("multiline macro omitted %q:\n%s", want, pp) + } + } + if _, err := Parse(ArchAMD64, src); err != nil { + t.Fatalf("Parse rejected a Go-assembler-compatible multiline macro: %v\n%s", err, pp) + } +} + +func TestPreprocessKeepsMultilineDefineWhenContinuationPrecedesLineComment(t *testing.T) { + // Several Go assembly packages, including IOTA, MinIO HighwayHash, and + // go-ethereum, put a line comment after the continuation slash. The Go + // assembler's preprocessor accepts this historical spelling. + const src = ` +#define ROUND(dst, src) \ + MOVQ src, dst; \ // copy the input + \ // keep this comment-only continuation in the macro + ADDQ $1, dst +TEXT macro(SB),$0-0 + ROUND(AX, BX) + RET +` + pp, err := preprocess(src) + if err != nil { + t.Fatal(err) + } + if strings.Contains(pp, "\\") { + t.Fatalf("commented continuation escaped into preprocessed assembly:\n%s", pp) + } + for _, want := range []string{"MOVQ BX, AX", "ADDQ $1, AX"} { + if !strings.Contains(pp, want) { + t.Fatalf("multiline macro omitted %q:\n%s", want, pp) + } + } + if _, err := Parse(ArchAMD64, src); err != nil { + t.Fatalf("Parse rejected a Go-assembler-compatible commented continuation: %v\n%s", err, pp) + } +} + +func TestPreprocessEvaluatesConditionalDirectivesExpandedFromMacro(t *testing.T) { + const src = ` +#define BREAK \ +#ifdef GOOS_windows \ + BRK $0xf000 \ +#else \ + BRK \ +#endif \ + +TEXT breakpoint(SB),NOSPLIT,$0-0 + BREAK + RET +` + linux, err := preprocessWithDefines(src, []string{"GOOS_linux", "GOARCH_arm64"}) + if err != nil { + t.Fatal(err) + } + if strings.Contains(linux, "#if") || strings.Contains(linux, "#else") || strings.Contains(linux, "#endif") { + t.Fatalf("conditional directive escaped from Linux macro expansion:\n%s", linux) + } + if !strings.Contains(linux, "BRK\n") || strings.Contains(linux, "$0xf000") { + t.Fatalf("Linux macro selected the wrong branch:\n%s", linux) + } + + windows, err := preprocessWithDefines(src, []string{"GOOS_windows", "GOARCH_arm64"}) + if err != nil { + t.Fatal(err) + } + if strings.Contains(windows, "#if") || strings.Contains(windows, "#else") || strings.Contains(windows, "#endif") { + t.Fatalf("conditional directive escaped from Windows macro expansion:\n%s", windows) + } + if !strings.Contains(windows, "BRK $0xf000") { + t.Fatalf("Windows macro selected the wrong branch:\n%s", windows) + } +} + +func TestGoAssemblerDefinesMatchToolchainFeatureRules(t *testing.T) { + t.Setenv("GOAMD64", "v3") + if got := strings.Join(GoAssemblerDefines("linux", "amd64"), ","); got != "GOOS_linux,GOARCH_amd64,GOAMD64_v3" { + t.Fatalf("amd64 defines = %q", got) + } + t.Setenv("GOARM", "7,hardfloat") + if got := strings.Join(GoAssemblerDefines("linux", "arm"), ","); got != "GOOS_linux,GOARCH_arm,GOARM_7,GOARM_6,GOARM_5" { + t.Fatalf("arm defines = %q", got) + } + t.Setenv("GOARM64", "v8.0,lse") + if got := strings.Join(GoAssemblerDefines("windows", "arm64"), ","); got != "GOOS_windows,GOARCH_arm64,GOARM64_LSE" { + t.Fatalf("arm64 defines = %q", got) + } +} diff --git a/runtime_exec_test.go b/runtime_exec_test.go index 1464867b..eae4f523 100644 --- a/runtime_exec_test.go +++ b/runtime_exec_test.go @@ -19,7 +19,7 @@ func TestRuntimeExecAMD64Add(t *testing.T) { llc, clang, ok := findLlcAndClang(t) if !ok { - t.Skip("llc/clang not found") + t.Fatal("llc/clang not found") } src := ` @@ -76,7 +76,7 @@ func TestRuntimeExecARM64Add(t *testing.T) { llc, clang, ok := findLlcAndClang(t) if !ok { - t.Skip("llc/clang not found") + t.Fatal("llc/clang not found") } src := ` @@ -134,7 +134,7 @@ func TestRuntimeExecAMD64AddlJLE(t *testing.T) { llc, clang, ok := findLlcAndClang(t) if !ok { - t.Skip("llc/clang not found") + t.Fatal("llc/clang not found") } src := ` @@ -199,7 +199,7 @@ func TestRuntimeExecAMD64AddlJB(t *testing.T) { llc, clang, ok := findLlcAndClang(t) if !ok { - t.Skip("llc/clang not found") + t.Fatal("llc/clang not found") } src := ` @@ -263,7 +263,7 @@ func TestRuntimeExecARM64CmpBLE(t *testing.T) { llc, clang, ok := findLlcAndClang(t) if !ok { - t.Skip("llc/clang not found") + t.Fatal("llc/clang not found") } src := ` @@ -349,6 +349,12 @@ func compileAndRunRuntimeTestWithCompiler(t *testing.T, llc string, compiler []s if err := os.WriteFile(llPath, []byte(ll), 0644); err != nil { t.Fatal(err) } + if strings.Contains(triple, "windows") { + // LLVM-generated Windows objects reference the conventional floating + // point marker normally supplied by the MSVC CRT. The MinGW clang used + // by CI does not provide it when linking these freestanding test objects. + mainC = "int _fltused = 0;\n" + mainC + } if err := os.WriteFile(mainPath, []byte(mainC), 0644); err != nil { t.Fatal(err) } @@ -357,13 +363,19 @@ func compileAndRunRuntimeTestWithCompiler(t *testing.T, llc string, compiler []s if out, err := llcCmd.CombinedOutput(); err != nil { s := string(out) if llcUnsupportedTarget(s) { - t.Skipf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) + t.Fatalf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) } t.Fatalf("llc failed: %v\n%s", err, s) } compilerArgs := append([]string(nil), compiler[1:]...) compilerArgs = append(compilerArgs, objPath, mainPath, "-O2", "-o", exePath) + if !strings.Contains(triple, "windows") { + // LLVM may lower floating intrinsics such as roundeven and fma to the C + // math library. Darwin provides those symbols through libSystem, while + // ELF linkers require an explicit libm dependency. + compilerArgs = append(compilerArgs, "-lm") + } compilerCmd := exec.Command(compiler[0], compilerArgs...) if out, err := compilerCmd.CombinedOutput(); err != nil { t.Fatalf("compile/link with %s failed: %v\n%s", compiler[0], err, string(out)) diff --git a/scripts/benchmark-compile.sh b/scripts/benchmark-compile.sh new file mode 100755 index 00000000..cccd04d3 --- /dev/null +++ b/scripts/benchmark-compile.sh @@ -0,0 +1,171 @@ +#!/usr/bin/env bash +set -euo pipefail + +repo_root=$(cd "$(dirname "$0")/.." && pwd) +go_version=$(go env GOVERSION) +if [[ ! "$go_version" =~ ^go1[.]27([.]|$) ]]; then + echo "compile benchmark requires Go 1.27, got $go_version" >&2 + exit 1 +fi +if ! command -v jq >/dev/null 2>&1; then + echo "jq not found in PATH" >&2 + exit 1 +fi + +# Resolved relative to the checked-out repository. +# shellcheck disable=SC1091 +source "$repo_root/scripts/llvm22.sh" +if ! llc_cmd=$(find_llvm22_llc); then + exit 1 +fi + +targets_csv=${PLAN9ASM_BENCHMARK_TARGETS:-linux/386,linux/amd64,linux/arm,linux/arm64,js/wasm} +IFS=',' read -r -a targets <<<"$targets_csv" +if (( ${#targets[@]} == 0 )); then + echo "PLAN9ASM_BENCHMARK_TARGETS must contain at least one GOOS/GOARCH target" >&2 + exit 2 +fi +for target in "${targets[@]}"; do + if ! [[ "$target" =~ ^[a-z0-9]+/(386|amd64|arm|arm64|wasm)$ ]]; then + echo "invalid benchmark target $target" >&2 + exit 2 + fi +done + +max_target_seconds=${PLAN9ASM_BENCHMARK_MAX_TARGET_SECONDS:-300} +max_total_seconds=${PLAN9ASM_BENCHMARK_MAX_TOTAL_SECONDS:-900} +if ! [[ "$max_target_seconds" =~ ^[1-9][0-9]*$ && "$max_total_seconds" =~ ^[1-9][0-9]*$ ]]; then + echo "benchmark time budgets must be positive integer seconds" >&2 + exit 2 +fi + +report_dir=${PLAN9ASM_BENCHMARK_REPORT_DIR:-"$repo_root/_out/compile-benchmark"} +mkdir -p "$report_dir" +find "$report_dir" -maxdepth 1 -type f \( -name '*.json' -o -name '*.md' \) -delete + +tmp_root=$(mktemp -d) +trap 'rm -rf "$tmp_root"' EXIT +translator="$tmp_root/plan9asmll" + +group_start() { + if [[ "${GITHUB_ACTIONS:-}" == "true" ]]; then + printf '::group::%s\n' "$1" + else + printf '==> %s\n' "$1" + fi +} + +group_end() { + if [[ "${GITHUB_ACTIONS:-}" == "true" ]]; then + printf '::endgroup::\n' + fi +} + +group_start "build plan9asmll benchmark driver" +build_start=$SECONDS +if go build -C "$repo_root/cmd/plan9asmll" -o "$translator" .; then + build_status=0 +else + build_status=$? +fi +build_seconds=$((SECONDS - build_start)) +group_end +printf 'benchmark driver build: %ds\n' "$build_seconds" +if (( build_status != 0 )); then + exit "$build_status" +fi + +total_wall_seconds=0 +budget_failed=0 +metric_files=() +for target in "${targets[@]}"; do + goos=${target%/*} + goarch=${target#*/} + target_id="$goos-$goarch" + report_path="$report_dir/$target_id.json" + metric_path="$tmp_root/$target_id-metric.json" + + group_start "compile benchmark $target" + target_start=$SECONDS + if "$translator" \ + -goos="$goos" \ + -goarch="$goarch" \ + -patterns=std \ + -compile \ + -llc="$llc_cmd" \ + -strict-load \ + -keep-going=false \ + -repo-root="$repo_root" \ + -out="$tmp_root/llvm/$target_id" \ + -report="$report_path"; then + target_status=0 + else + target_status=$? + fi + wall_seconds=$((SECONDS - target_start)) + group_end + if (( target_status != 0 )); then + echo "compile benchmark $target failed after ${wall_seconds}s" >&2 + exit "$target_status" + fi + + failed=$(jq -r '.failed' "$report_path") + total_asm=$(jq -r '.total_asm' "$report_path") + success=$(jq -r '.success' "$report_path") + not_applicable=$(jq -r '.not_applicable' "$report_path") + tool_duration=$(jq -r '.duration' "$report_path") + if [[ "$failed" != "0" || "$not_applicable" != "0" || "$success" != "$total_asm" || ! "$total_asm" =~ ^[1-9][0-9]*$ ]]; then + echo "compile benchmark $target requires every assembly file to compile: total=$total_asm success=$success not_applicable=$not_applicable failed=$failed" >&2 + exit 1 + fi + total_wall_seconds=$((total_wall_seconds + wall_seconds)) + if (( wall_seconds > max_target_seconds )); then + echo "compile benchmark $target exceeded ${max_target_seconds}s budget: ${wall_seconds}s" >&2 + budget_failed=1 + fi + printf 'compile benchmark %s: wall=%ds tool=%s asm=%s success=%s not_applicable=%s\n' \ + "$target" "$wall_seconds" "$tool_duration" "$total_asm" "$success" "$not_applicable" + + jq -n \ + --arg target "$target" \ + --arg tool_duration "$tool_duration" \ + --argjson wall_seconds "$wall_seconds" \ + --argjson total_asm "$total_asm" \ + --argjson success "$success" \ + --argjson not_applicable "$not_applicable" \ + '{target:$target,wall_seconds:$wall_seconds,tool_duration:$tool_duration,total_asm:$total_asm,success:$success,not_applicable:$not_applicable}' \ + >"$metric_path" + metric_files+=("$metric_path") +done + +jq -s \ + --arg go_version "$go_version" \ + --arg llc "$llc_cmd" \ + --argjson build_seconds "$build_seconds" \ + --argjson total_wall_seconds "$total_wall_seconds" \ + --argjson max_target_seconds "$max_target_seconds" \ + --argjson max_total_seconds "$max_total_seconds" \ + '{schema_version:1,go_version:$go_version,llc:$llc,build_seconds:$build_seconds,total_wall_seconds:$total_wall_seconds,max_target_seconds:$max_target_seconds,max_total_seconds:$max_total_seconds,targets:.}' \ + "${metric_files[@]}" >"$report_dir/summary.json" + +summary_path="$report_dir/summary.md" +{ + printf '### Compile benchmark\n\n' + printf '| Target | Wall | Tool duration | Asm files | Success | N/A |\n' + printf '| --- | ---: | ---: | ---: | ---: | ---: |\n' + jq -r '.targets[] | "| \(.target) | \(.wall_seconds)s | \(.tool_duration) | \(.total_asm) | \(.success) | \(.not_applicable) |"' "$report_dir/summary.json" + printf '\nBuild: %ss; target total: %ss; budgets: %ss per target / %ss total.\n' \ + "$build_seconds" "$total_wall_seconds" "$max_target_seconds" "$max_total_seconds" +} >"$summary_path" +cat "$summary_path" +if [[ -n "${GITHUB_STEP_SUMMARY:-}" ]]; then + cat "$summary_path" >>"$GITHUB_STEP_SUMMARY" +fi + +if (( total_wall_seconds > max_total_seconds )); then + echo "compile benchmark exceeded ${max_total_seconds}s total budget: ${total_wall_seconds}s" >&2 + budget_failed=1 +fi +if (( budget_failed != 0 )); then + exit 1 +fi diff --git a/scripts/check-discovered-library-corpus.sh b/scripts/check-discovered-library-corpus.sh new file mode 100755 index 00000000..a61f3d43 --- /dev/null +++ b/scripts/check-discovered-library-corpus.sh @@ -0,0 +1,77 @@ +#!/usr/bin/env bash +set -euo pipefail + +repo_root=$(cd "$(dirname "$0")/.." && pwd) +shard_index=${1:-} +shard_count=${2:-} +report_path=${3:-} +if [[ "$shard_index" == "all" ]]; then + if (( $# > 2 )); then + echo "usage: $0 all [shard-count]" >&2 + exit 2 + fi + shard_count=${2:-32} + parallelism=${PLAN9ASM_DISCOVERY_PARALLELISM:-4} + if ! [[ "$shard_count" =~ ^[1-9][0-9]*$ && "$parallelism" =~ ^[1-9][0-9]*$ ]]; then + echo "invalid shard count or PLAN9ASM_DISCOVERY_PARALLELISM" >&2 + exit 2 + fi + report_dir="$repo_root/_out/discovered-library-corpus" + mkdir -p "$report_dir" + find "$report_dir" -maxdepth 1 -type f -name 'shard-*.json' -delete + seq 0 "$((shard_count - 1))" | + xargs -P "$parallelism" -I '{}' "$0" '{}' "$shard_count" "$report_dir/shard-{}.json" + "$repo_root/scripts/verify-discovered-library-corpus.sh" "$report_dir" + exit 0 +fi +if [[ -z "$shard_index" || -z "$shard_count" || $# -gt 3 ]]; then + echo "usage: $0 [report.json]" >&2 + echo " $0 all [shard-count]" >&2 + exit 2 +fi +if ! [[ "$shard_index" =~ ^[0-9]+$ && "$shard_count" =~ ^[1-9][0-9]*$ ]] || (( shard_index >= shard_count )); then + echo "invalid shard $shard_index/$shard_count" >&2 + exit 2 +fi + +go_version=$(go env GOVERSION) +if [[ ! "$go_version" =~ ^go1[.]27([.]|$) ]]; then + echo "discovered third-party corpus requires Go 1.27, got $go_version" >&2 + exit 1 +fi + +# Resolved relative to the checked-out repository. +# shellcheck disable=SC1091 +source "$repo_root/scripts/llvm22.sh" +if ! llc_cmd=$(find_llvm22_llc); then + exit 1 +fi + +tmp_root=$(mktemp -d) +trap 'rm -rf "$tmp_root"' EXIT +translator="$tmp_root/plan9asmll" +runner="$tmp_root/plan9asmcorpus" +go build -C "$repo_root/cmd/plan9asmll" -o "$translator" . +go build -C "$repo_root" -o "$runner" ./cmd/plan9asmcorpus + +if [[ -z "$report_path" ]]; then + report_path="$repo_root/_out/discovered-library-corpus/shard-$shard_index.json" +fi + +runner_args=( + -manifest="$repo_root/testdata/corpus/reported-libraries.json" + -discovery-ledger="$repo_root/testdata/discovery/ledger" + -repo-root="$repo_root" + -translator="$translator" + -llc="$llc_cmd" + -discovery-shard-index="$shard_index" + -discovery-shard-count="$shard_count" + -discovery-report="$report_path" +) +if [[ -n "${PLAN9ASM_DISCOVERY_CANDIDATE_TIMEOUT:-}" ]]; then + runner_args+=("-candidate-timeout=$PLAN9ASM_DISCOVERY_CANDIDATE_TIMEOUT") +fi +if [[ -n "${PLAN9ASM_DISCOVERY_TARGETS:-}" ]]; then + runner_args+=("-discovery-targets=$PLAN9ASM_DISCOVERY_TARGETS") +fi +"$runner" "${runner_args[@]}" diff --git a/scripts/check-go-asm-coverage.sh b/scripts/check-go-asm-coverage.sh index b85b3887..6f3176ba 100755 --- a/scripts/check-go-asm-coverage.sh +++ b/scripts/check-go-asm-coverage.sh @@ -70,6 +70,7 @@ if actual_versions != expected_versions: "coverage baseline versions differ: " f"expected {sorted(expected_versions)}, got {sorted(actual_versions)}" ) +latest_version = max(expected_versions, key=lambda item: int(item.split(".")[1])) fields = ( "official_opcodes", @@ -154,13 +155,21 @@ for report_path in report_paths: if line.strip() and not line.lstrip().startswith("#") } catalog = {item["opcode"]: item for item in report["opcode_catalog"]} - missing_encoder = sorted(op for op in required if not catalog.get(op, {}).get("encoder_forms")) - missing_corpus = sorted(op for op in required if not catalog.get(op, {}).get("observed_in_corpus")) - unsupported = sorted(op for op in required if catalog.get(op, {}).get("unsupported_forms")) - if missing_encoder or missing_corpus or unsupported: + available = required.intersection(catalog) + unavailable = sorted(required.difference(available)) + missing_encoder = sorted(op for op in available if not catalog[op].get("encoder_forms")) + missing_corpus = sorted(op for op in available if not catalog[op].get("observed_in_corpus")) + unsupported = sorted(op for op in available if catalog[op].get("unsupported_forms")) + missing_latest = unavailable if version == latest_version else [] + if missing_latest or missing_encoder or missing_corpus or unsupported: raise SystemExit( f"{version}/arm64: incomplete required Go assembler families: " - f"missing_encoder={missing_encoder}, missing_corpus={missing_corpus}, unsupported={unsupported}" + f"missing_from_latest={missing_latest}, missing_encoder={missing_encoder}, " + f"missing_corpus={missing_corpus}, unsupported={unsupported}" ) - print(f"{version}/arm64: all {len(required)} required opcodes are encoder-defined, observed, and lowerable") + print( + f"{version}/arm64: all {len(available)} toolchain-available required opcodes " + f"are encoder-defined, observed, and lowerable" + + (f"; {len(unavailable)} future opcodes are absent from this Go release" if unavailable else "") + ) PY diff --git a/scripts/verify-discovered-library-corpus.sh b/scripts/verify-discovered-library-corpus.sh new file mode 100755 index 00000000..cf9ee1c1 --- /dev/null +++ b/scripts/verify-discovered-library-corpus.sh @@ -0,0 +1,17 @@ +#!/usr/bin/env bash +set -euo pipefail + +repo_root=$(cd "$(dirname "$0")/.." && pwd) +reports_dir=${1:-"$repo_root/_out/discovered-library-corpus"} +if (( $# > 1 )); then + echo "usage: $0 [reports-directory]" >&2 + exit 2 +fi + +go run -C "$repo_root" ./cmd/plan9asmdiscover \ + -status \ + -out-dir "$repo_root/testdata/discovery/ledger" +go run -C "$repo_root" ./cmd/plan9asmcorpus \ + -manifest "$repo_root/testdata/corpus/reported-libraries.json" \ + -discovery-ledger "$repo_root/testdata/discovery/ledger" \ + -verify-discovery-reports "$reports_dir" diff --git a/stdlib_arm64_test_helpers_test.go b/stdlib_arm64_test_helpers_test.go index c7d8b5a4..264e1d8d 100644 --- a/stdlib_arm64_test_helpers_test.go +++ b/stdlib_arm64_test_helpers_test.go @@ -20,7 +20,7 @@ func testGOROOT(t *testing.T) string { } goroot, err := testGoEnv("GOROOT") if err != nil || goroot == "" { - t.Skip("GOROOT not available") + t.Fatal("GOROOT not available") } return goroot } @@ -46,7 +46,7 @@ func compileLLVMToObject(t *testing.T, llc, triple, llName, objName, ll string) if err != nil { s := string(out) if llcUnsupportedTarget(s) { - t.Skipf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) + t.Fatalf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) } t.Fatalf("llc failed: %v\n%s", err, s) } diff --git a/stdlib_bytealg_arm_compile_test.go b/stdlib_bytealg_arm_compile_test.go index 1c2793aa..a8ee3901 100644 --- a/stdlib_bytealg_arm_compile_test.go +++ b/stdlib_bytealg_arm_compile_test.go @@ -15,15 +15,15 @@ import ( func TestStdlibInternalBytealg_ARM_Compile(t *testing.T) { llc, _, ok := findLlcAndClang(t) if !ok { - t.Skip("llc not found") + t.Fatal("llc not found") } goroot := runtime.GOROOT() if goroot == "" { - t.Skip("GOROOT not available") + t.Fatal("GOROOT not available") } sfiles := stdlibBytealgARMSigs(goroot) if len(sfiles) == 0 { - t.Skip("internal/bytealg arm asm files not present in this GOROOT") + t.Fatal("internal/bytealg arm asm files not present in this GOROOT") } resolve := func(sym string) string { sym = goStripABISuffix(sym) @@ -76,7 +76,7 @@ func TestStdlibInternalBytealg_ARM_Compile(t *testing.T) { strings.Contains(s, "unknown target triple") || strings.Contains(s, "unknown target") || strings.Contains(s, "is not a registered target") { - t.Skipf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) + t.Fatalf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) } t.Fatalf("llc failed for %s: %v\n%s", path, err, s) } diff --git a/stdlib_bytealg_compile_test.go b/stdlib_bytealg_compile_test.go index 8828d197..d8948f5d 100644 --- a/stdlib_bytealg_compile_test.go +++ b/stdlib_bytealg_compile_test.go @@ -15,17 +15,17 @@ import ( func TestStdlibInternalBytealg_ARM64_Compile(t *testing.T) { llc, _, ok := findLlcAndClang(t) if !ok { - t.Skip("llc not found") + t.Fatal("llc not found") } goroot := runtime.GOROOT() if goroot == "" { - t.Skip("GOROOT not available") + t.Fatal("GOROOT not available") } sfiles := stdlibBytealgARM64Sigs(goroot) if len(sfiles) == 0 { - t.Skip("internal/bytealg arm64 asm files not present in this GOROOT") + t.Fatal("internal/bytealg arm64 asm files not present in this GOROOT") } resolve := func(sym string) string { @@ -80,7 +80,7 @@ func TestStdlibInternalBytealg_ARM64_Compile(t *testing.T) { strings.Contains(s, "unknown target triple") || strings.Contains(s, "unknown target") || strings.Contains(s, "is not a registered target") { - t.Skipf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) + t.Fatalf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) } t.Fatalf("llc failed for %s: %v\n%s", path, err, s) } diff --git a/stdlib_bytealg_parse_test.go b/stdlib_bytealg_parse_test.go index 659f127a..c70aa494 100644 --- a/stdlib_bytealg_parse_test.go +++ b/stdlib_bytealg_parse_test.go @@ -13,12 +13,12 @@ import ( func TestParseStdlibInternalBytealgArm64Compare(t *testing.T) { goroot := runtime.GOROOT() if goroot == "" { - t.Skip("GOROOT not available") + t.Fatal("GOROOT not available") } path := filepath.Join(goroot, "src", "internal", "bytealg", "compare_arm64.s") src, err := os.ReadFile(path) if err != nil { - t.Skipf("read %s: %v", path, err) + t.Fatalf("read %s: %v", path, err) } if _, err := Parse(ArchARM64, string(src)); err != nil { t.Fatalf("parse %s: %v", path, err) @@ -28,7 +28,7 @@ func TestParseStdlibInternalBytealgArm64Compare(t *testing.T) { func TestParseStdlibInternalBytealg_Amd64AndArm64(t *testing.T) { goroot := runtime.GOROOT() if goroot == "" { - t.Skip("GOROOT not available") + t.Fatal("GOROOT not available") } dir := filepath.Join(goroot, "src", "internal", "bytealg") glob := func(pat string) []string { @@ -53,7 +53,7 @@ func TestParseStdlibInternalBytealg_Amd64AndArm64(t *testing.T) { }{arch: ArchAMD64, path: p}) } if len(files) == 0 { - t.Skipf("no bytealg asm files found under %s", dir) + t.Fatalf("no bytealg asm files found under %s", dir) } for _, f := range files { diff --git a/stdlib_cpu_arm64_test.go b/stdlib_cpu_arm64_test.go index 97177611..1572f9e8 100644 --- a/stdlib_cpu_arm64_test.go +++ b/stdlib_cpu_arm64_test.go @@ -13,14 +13,14 @@ import ( func TestStdlibInternalCPU_ARM64_Compile(t *testing.T) { llc, _, ok := findLlcAndClang(t) if !ok { - t.Skip("llc not found") + t.Fatal("llc not found") } goroot := testGOROOT(t) src, err := os.ReadFile(filepath.Join(goroot, "src", "internal", "cpu", "cpu_arm64.s")) if err != nil { if os.IsNotExist(err) { - t.Skip("internal/cpu/cpu_arm64.s not present in this GOROOT") + t.Fatal("internal/cpu/cpu_arm64.s not present in this GOROOT") } t.Fatal(err) } diff --git a/stdlib_cpu_x86_test.go b/stdlib_cpu_x86_test.go index f36f5521..603e47cf 100644 --- a/stdlib_cpu_x86_test.go +++ b/stdlib_cpu_x86_test.go @@ -15,7 +15,7 @@ import ( func TestStdlibInternalCPU_X86_CompileX86Triples(t *testing.T) { llc, _, ok := findLlcAndClang(t) if !ok { - t.Skip("llc not found") + t.Fatal("llc not found") } goroot := runtime.GOROOT() @@ -110,11 +110,11 @@ func TestStdlibInternalCPU_X86_CompileX86Triples(t *testing.T) { if strings.HasPrefix(triple, "x86_64-") { t.Fatalf("translate failed: %v", err) } - t.Skipf("translate skipped for non-x86 triple %q: %v", triple, err) + t.Fatalf("translate skipped for non-x86 triple %q: %v", triple, err) } if !strings.HasPrefix(triple, "x86_64-") { - t.Skip("llc compilation only meaningful for x86_64 triples") + t.Fatal("llc compilation only meaningful for x86_64 triples") } tmp := t.TempDir() @@ -132,7 +132,7 @@ func TestStdlibInternalCPU_X86_CompileX86Triples(t *testing.T) { strings.Contains(s, "unknown target triple") || strings.Contains(s, "unknown target") || strings.Contains(s, "is not a registered target") { - t.Skipf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) + t.Fatalf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) } t.Fatalf("llc failed for triple %q: %v\n%s", triple, err, s) } diff --git a/stdlib_crc32_amd64_test.go b/stdlib_crc32_amd64_test.go index 64888d42..31ac1582 100644 --- a/stdlib_crc32_amd64_test.go +++ b/stdlib_crc32_amd64_test.go @@ -15,7 +15,7 @@ import ( func TestStdlibHashCRC32_AMD64_Compile(t *testing.T) { _, clang, ok := findLlcAndClang(t) if !ok || clang == "" { - t.Skip("clang not found") + t.Fatal("clang not found") } goroot := runtime.GOROOT() @@ -105,10 +105,10 @@ func TestStdlibHashCRC32_AMD64_Compile(t *testing.T) { if err != nil { t.Fatal(err) } - if !strings.Contains(ll, `"target-features"="+crc32,+sse4.2"`) { + if !hasTargetFeatures(ll, "+crc32", "+sse4.2") { t.Fatalf("missing crc32 target-features attr:\n%s", ll) } - if !strings.Contains(ll, `"target-features"="+pclmul,+sse4.1"`) { + if !hasTargetFeatures(ll, "+pclmul", "+sse4.1") { t.Fatalf("missing pclmul target-features attr:\n%s", ll) } @@ -124,3 +124,43 @@ func TestStdlibHashCRC32_AMD64_Compile(t *testing.T) { t.Fatalf("clang failed: %v\n%s", err, string(out)) } } + +func hasTargetFeatures(ir string, features ...string) bool { + const marker = `"target-features"="` + for _, line := range strings.Split(ir, "\n") { + start := strings.Index(line, marker) + if start < 0 { + continue + } + value := line[start+len(marker):] + if end := strings.IndexByte(value, '"'); end >= 0 { + value = value[:end] + } + available := map[string]bool{} + for _, feature := range strings.Split(value, ",") { + available[feature] = true + } + for _, feature := range features { + if !available[feature] { + goto nextLine + } + } + return true + nextLine: + } + return false +} + +func TestHasTargetFeaturesAllowsExtrasButRequiresOneExactSet(t *testing.T) { + ir := `attributes #7 = { "target-features"="+crc32,+sse4.2" } +attributes #8 = { "target-features"="+bmi2,+pclmul,+sse4.1" }` + if !hasTargetFeatures(ir, "+pclmul", "+sse4.1") { + t.Fatal("extra target feature prevented matching the required set") + } + if hasTargetFeatures(ir, "+crc32", "+pclmul") { + t.Fatal("features from separate attributes were combined") + } + if hasTargetFeatures(ir, "+sse4") { + t.Fatal("partial feature name matched") + } +} diff --git a/stdlib_math_exp_arm64_test.go b/stdlib_math_exp_arm64_test.go index 69daac3c..390bb1bd 100644 --- a/stdlib_math_exp_arm64_test.go +++ b/stdlib_math_exp_arm64_test.go @@ -15,7 +15,7 @@ import ( func TestStdlibMathExp_ARM64_Compile(t *testing.T) { llc, _, ok := findLlcAndClang(t) if !ok { - t.Skip("llc not found") + t.Fatal("llc not found") } goroot := runtime.GOROOT() @@ -92,7 +92,7 @@ func TestStdlibMathExp_ARM64_Compile(t *testing.T) { strings.Contains(s, "unknown target triple") || strings.Contains(s, "unknown target") || strings.Contains(s, "is not a registered target") { - t.Skipf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) + t.Fatalf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) } t.Fatalf("llc failed for %q: %v\n%s", triple, err, s) } diff --git a/stdlib_runtime_sys_arm64_test.go b/stdlib_runtime_sys_arm64_test.go index d6f2c372..52a2d93c 100644 --- a/stdlib_runtime_sys_arm64_test.go +++ b/stdlib_runtime_sys_arm64_test.go @@ -1,5 +1,5 @@ -//go:build !llgo -// +build !llgo +//go:build go1.27 && !llgo +// +build go1.27,!llgo package plan9asm @@ -13,14 +13,14 @@ import ( func TestStdlibInternalRuntimeSys_ARM64_Compile(t *testing.T) { llc, _, ok := findLlcAndClang(t) if !ok { - t.Skip("llc not found") + t.Fatal("llc not found") } goroot := testGOROOT(t) src, err := os.ReadFile(filepath.Join(goroot, "src", "internal", "runtime", "sys", "dit_arm64.s")) if err != nil { if os.IsNotExist(err) { - t.Skip("internal/runtime/sys/dit_arm64.s not present in this GOROOT") + t.Fatal("internal/runtime/sys/dit_arm64.s not present in this GOROOT") } t.Fatal(err) } @@ -71,14 +71,14 @@ func TestStdlibInternalRuntimeSys_ARM64_Compile(t *testing.T) { func TestTranslateGoModule_StdlibInternalRuntimeSys_ARM64_Compile(t *testing.T) { llc, _, ok := findLlcAndClang(t) if !ok { - t.Skip("llc not found") + t.Fatal("llc not found") } goroot := testGOROOT(t) src, err := os.ReadFile(filepath.Join(goroot, "src", "internal", "runtime", "sys", "dit_arm64.s")) if err != nil { if os.IsNotExist(err) { - t.Skip("internal/runtime/sys/dit_arm64.s not present in this GOROOT") + t.Fatal("internal/runtime/sys/dit_arm64.s not present in this GOROOT") } t.Fatal(err) } diff --git a/stdlib_sig_test.go b/stdlib_sig_test.go index ea66a695..0f0f1ac5 100644 --- a/stdlib_sig_test.go +++ b/stdlib_sig_test.go @@ -15,21 +15,21 @@ import ( func TestStdlibBoringSig_CompileManyTriples(t *testing.T) { llc, _, ok := findLlcAndClang(t) if !ok { - t.Skip("llc not found") + t.Fatal("llc not found") } goroot := runtime.GOROOT() srcOther, err := os.ReadFile(filepath.Join(goroot, "src", "crypto", "internal", "boring", "sig", "sig_other.s")) if err != nil { if os.IsNotExist(err) { - t.Skip("crypto/internal/boring/sig/sig_other.s not present in this GOROOT") + t.Fatal("crypto/internal/boring/sig/sig_other.s not present in this GOROOT") } t.Fatal(err) } srcAMD64, err := os.ReadFile(filepath.Join(goroot, "src", "crypto", "internal", "boring", "sig", "sig_amd64.s")) if err != nil { if os.IsNotExist(err) { - t.Skip("crypto/internal/boring/sig/sig_amd64.s not present in this GOROOT") + t.Fatal("crypto/internal/boring/sig/sig_amd64.s not present in this GOROOT") } t.Fatal(err) } @@ -99,7 +99,7 @@ func TestStdlibBoringSig_CompileManyTriples(t *testing.T) { strings.Contains(s, "unknown target triple") || strings.Contains(s, "unknown target") || strings.Contains(s, "is not a registered target") { - t.Skipf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) + t.Fatalf("llc does not support triple %q: %s", triple, strings.TrimSpace(s)) } t.Fatalf("llc failed for triple %q: %v\n%s", triple, err, s) } @@ -118,7 +118,7 @@ func TestStdlibBoringSig_TranslateOnly(t *testing.T) { src, err := os.ReadFile(filepath.Join(goroot, "src", "crypto", "internal", "boring", "sig", "sig_amd64.s")) if err != nil { if os.IsNotExist(err) { - t.Skip("crypto/internal/boring/sig/sig_amd64.s not present in this GOROOT") + t.Fatal("crypto/internal/boring/sig/sig_amd64.s not present in this GOROOT") } t.Fatal(err) } diff --git a/testdata/conformance/amd64/conformance.go b/testdata/conformance/amd64/conformance.go index 5457bf27..bbe78146 100644 --- a/testdata/conformance/amd64/conformance.go +++ b/testdata/conformance/amd64/conformance.go @@ -18,8 +18,82 @@ func doubleShift32(out *[8]uint32, src, dst, amount uint32) func doubleShift64(out *[8]uint64, src, dst, amount uint64) +func scalarShiftRotateSemantics(out *[14]uint64, value, count uint64) + +func incDecSemantics(out *[12]uint64, value uint64) + +func scalarAddSubSemantics(out *[16]uint64, value, source uint64) + +func compareExchangeScalarSemantics(out *[24]uint64, memory *[8]uint64, expected, desired uint64) + +func compareExchangePairSemantics(out *[9]uint64, memory *uint64, expectedLow, expectedHigh, desiredLow, desiredHigh uint64) + +func parallelBitSemantics(out *[8]uint64, mask, source uint64) + +func bitTestRegisterSemantics(out *[24]uint64, value, index uint64) + +func bitTestMemorySemantics(out *[12]byte, data *[9]uint64) + +func packedWordMultiplyAddSemantics(out *[18]int32, a, b *[16]int16) + +func packedUnsignedSignedByteMultiplyAddSemantics(out *[32]int16, signed *[32]int8, unsigned *[32]uint8) + +// packedDotProductSemantics is executed by the translated LLVM runtime +// oracle; the native suite assembles the AVX-512 source without requiring the +// host CPU to execute it. +func packedDotProductSemantics(out *[64]int32, signedBytes *[64]int8, unsignedBytes *[64]uint8, wordsA, wordsB *[32]int16, accumulator *[16]int32) + +func packedIntegerMinMaxSemantics(out *[1024]byte, a, b *[64]byte) + +func packedWordMultiplySemantics(out *[64]uint16, a, b *[8]int16) + +func packedFloatShuffleSemantics(out *[96]byte, a, b *[32]byte) + +func inLaneFloatingPermuteSemantics(out *[144]byte, data, control *[32]byte) + +func immediatePackedBlendSemantics(out *[240]byte, a, b *[32]byte) + +func packedUnpackSemantics(out *[384]byte, a, b *[32]byte) + +func qwordPermuteSemantics(out *[8]uint64, data *[4]uint64) + +func qwordVariablePermuteSemantics(out *[8]uint64, data, control *[4]uint64) + +func packedFloatMoveVEXSemantics(out *[128]byte, src *[32]byte) + +func packedFloatMoveMaskSemantics(out *[688]byte, src, old *[64]byte) + +func packedSignExtendMoveVEXSemantics(out *[288]byte, src *[32]byte) + +func packedSignExtendMoveMaskSemantics(out *[768]byte, src, old *[64]byte) + func goHexVectorOps(out *[160]byte, a, b *[16]byte) func goHexWordOps(value, count uint64) uint64 func packedArithmeticShift32(out *[8]int32, src *[4]int32) + +func packedSubtractSemantics(out *[80]byte, a, b *[16]byte) + +func expandedEcosystemVectors(out *[816]byte, a, b *[16]byte) + +func parityBranches(value byte) uint64 + +func unorderedBranch(value float64) uint64 + +func packedFloatToDwordModes(out *[20]int32, src *[4]float32) + +// sameWidthPackedConversionSemantics is exercised by the translated LLVM +// runtime oracle. The native Go suite still assembles it, but deliberately +// does not execute AVX-512 on hosts which may lack that ISA. +func sameWidthPackedConversionSemantics(out *[576]byte, ints *[16]int32, floats, squares32 *[16]float32, squares64 *[8]float64) + +func packedSingleToDouble(out *[4]float64, src *[4]float32) + +func conditionalMoveCodes(out, src *[16]uint64) + +func fma3Semantics(out *[288]byte, a64, b64, c64 *[2]float64, a32, b32, c32 *[4]float32) + +func binaryFloatingSemantics(out *[384]byte, a64, b64 *[2]float64, a32, b32 *[4]float32) + +func horizontalFloatingSemantics(out *[192]byte, a32, b32 *[8]float32, a64, b64 *[4]float64) diff --git a/testdata/conformance/amd64/conformance_amd64.s b/testdata/conformance/amd64/conformance_amd64.s index 1dfe8e36..f876b29b 100644 --- a/testdata/conformance/amd64/conformance_amd64.s +++ b/testdata/conformance/amd64/conformance_amd64.s @@ -130,6 +130,967 @@ TEXT ·doubleShift64(SB), NOSPLIT, $0-32 SHRQ $7, AX, (BX) RET +// scalarShiftRotateSemantics covers the scalar B/W/L/Q family, rotations, +// memory destinations, and the Go assembler's W-width double-shift forms. +TEXT ·scalarShiftRotateSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), DI + MOVQ value+8(FP), BX + MOVQ count+16(FP), CX + + MOVQ BX, AX + ROLB CL, AL + MOVQ AX, 0(DI) + MOVQ BX, AX + RORB CL, AL + MOVQ AX, 8(DI) + MOVQ BX, AX + SARB CL, AL + MOVQ AX, 16(DI) + MOVQ BX, AX + SHRB CL, AL + MOVQ AX, 24(DI) + + MOVQ BX, AX + ROLW CX, AX + MOVQ AX, 32(DI) + MOVQ BX, AX + SARW CL, AX + MOVQ AX, 40(DI) + MOVQ BX, AX + SHLL CX, AX + MOVQ AX, 48(DI) + MOVQ BX, AX + RORQ CL, AX + MOVQ AX, 56(DI) + + MOVQ BX, 64(DI) + SHRB CL, 64(DI) + MOVQ BX, 72(DI) + ROLW CX, 72(DI) + + MOVQ BX, AX + MOVQ $0xfedcba9876543210, DX + SHLW CL, AX, DX + MOVQ DX, 80(DI) + MOVQ BX, AX + MOVQ $0xfedcba9876543210, DX + SHRW CX, AX, DX + MOVQ DX, 88(DI) + + MOVQ BX, AX + SALB $3, AL + MOVQ AX, 96(DI) + MOVQ BX, AX + SARL $3, AX + MOVQ AX, 104(DI) + RET + +// incDecSemantics validates every width, register and memory destinations, +// 32-bit zero extension, and the INC/DEC flag contract (including preserved CF). +TEXT ·incDecSemantics(SB), NOSPLIT, $0-16 + MOVQ out+0(FP), DI + MOVQ value+8(FP), BX + MOVQ BX, AX + INCB AL + MOVQ AX, 0(DI) + MOVQ BX, AX + DECB AL + MOVQ AX, 8(DI) + MOVQ BX, AX + INCW AX + MOVQ AX, 16(DI) + MOVQ BX, AX + DECW AX + MOVQ AX, 24(DI) + MOVQ BX, AX + INCL AX + MOVQ AX, 32(DI) + MOVQ BX, AX + DECL AX + MOVQ AX, 40(DI) + MOVQ BX, AX + INCQ AX + MOVQ AX, 48(DI) + MOVQ BX, AX + DECQ AX + MOVQ AX, 56(DI) + MOVQ BX, 64(DI) + INCB 64(DI) + MOVQ BX, 72(DI) + DECW 72(DI) + + MOVQ $0, 80(DI) + MOVQ $0, AX + SUBQ $1, AX + MOVQ $0x7f, AX + INCB AL + SETCS 80(DI) + SETOS 81(DI) + SETMI 82(DI) + SETEQ 83(DI) + SETPS 84(DI) + + MOVQ $0, 88(DI) + MOVQ $1, AX + DECB AL + SETCS 88(DI) + SETOS 89(DI) + SETMI 90(DI) + SETEQ 91(DI) + SETPS 92(DI) + RET + +// scalarAddSubSemantics validates every scalar width, register and memory +// destinations, partial-register preservation, L-register zero extension, +// imm32 sign extension for Q, and all arithmetic condition flags. +TEXT ·scalarAddSubSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), DI + MOVQ value+8(FP), BX + MOVQ source+16(FP), CX + + MOVQ BX, AX + ADDB CL, AL + MOVQ AX, 0(DI) + MOVQ $0, 8(DI) + SETCS 8(DI) + SETOS 9(DI) + SETEQ 10(DI) + SETMI 11(DI) + SETPS 12(DI) + + MOVQ BX, 16(DI) + SUBB $4294967295, 16(DI) + MOVQ $0, 24(DI) + SETCS 24(DI) + SETOS 25(DI) + SETEQ 26(DI) + SETMI 27(DI) + SETPS 28(DI) + + MOVQ BX, AX + ADDW CX, AX + MOVQ AX, 32(DI) + MOVQ $0, 40(DI) + SETCS 40(DI) + SETOS 41(DI) + SETEQ 42(DI) + SETMI 43(DI) + SETPS 44(DI) + + MOVQ BX, 48(DI) + SUBW $4294967295, 48(DI) + MOVQ $0, 56(DI) + SETCS 56(DI) + SETOS 57(DI) + SETEQ 58(DI) + SETMI 59(DI) + SETPS 60(DI) + + MOVQ BX, AX + ADDL CX, AX + MOVQ AX, 64(DI) + MOVQ $0, 72(DI) + SETCS 72(DI) + SETOS 73(DI) + SETEQ 74(DI) + SETMI 75(DI) + SETPS 76(DI) + + MOVQ BX, 80(DI) + SUBL $4294967295, 80(DI) + MOVQ $0, 88(DI) + SETCS 88(DI) + SETOS 89(DI) + SETEQ 90(DI) + SETMI 91(DI) + SETPS 92(DI) + + MOVQ BX, AX + ADDQ CX, AX + MOVQ AX, 96(DI) + MOVQ $0, 104(DI) + SETCS 104(DI) + SETOS 105(DI) + SETEQ 106(DI) + SETMI 107(DI) + SETPS 108(DI) + + MOVQ BX, 112(DI) + SUBQ $4294967295, 112(DI) + MOVQ $0, 120(DI) + SETCS 120(DI) + SETOS 121(DI) + SETEQ 122(DI) + SETMI 123(DI) + SETPS 124(DI) + RET + +// compareExchangeScalarSemantics executes success and failure cases for all +// four widths. Each case records destination, accumulator, then CF/OF/ZF/SF/PF. +TEXT ·compareExchangeScalarSemantics(SB), NOSPLIT, $0-32 + MOVQ out+0(FP), DI + MOVQ memory+8(FP), SI + MOVQ expected+16(FP), BX + MOVQ desired+24(FP), CX + + MOVQ BX, AX + CMPXCHGB CL, 0(SI) + MOVQ 0(SI), DX + MOVQ DX, 0(DI) + MOVQ AX, 8(DI) + MOVQ $0, 16(DI) + SETCS 16(DI) + SETOS 17(DI) + SETEQ 18(DI) + SETMI 19(DI) + SETPS 20(DI) + MOVQ BX, AX + CMPXCHGB CL, 8(SI) + MOVQ 8(SI), DX + MOVQ DX, 24(DI) + MOVQ AX, 32(DI) + MOVQ $0, 40(DI) + SETCS 40(DI) + SETOS 41(DI) + SETEQ 42(DI) + SETMI 43(DI) + SETPS 44(DI) + + MOVQ BX, AX + CMPXCHGW CX, 16(SI) + MOVQ 16(SI), DX + MOVQ DX, 48(DI) + MOVQ AX, 56(DI) + MOVQ $0, 64(DI) + SETCS 64(DI) + SETOS 65(DI) + SETEQ 66(DI) + SETMI 67(DI) + SETPS 68(DI) + MOVQ BX, AX + CMPXCHGW CX, 24(SI) + MOVQ 24(SI), DX + MOVQ DX, 72(DI) + MOVQ AX, 80(DI) + MOVQ $0, 88(DI) + SETCS 88(DI) + SETOS 89(DI) + SETEQ 90(DI) + SETMI 91(DI) + SETPS 92(DI) + + MOVQ BX, AX + CMPXCHGL CX, 32(SI) + MOVQ 32(SI), DX + MOVQ DX, 96(DI) + MOVQ AX, 104(DI) + MOVQ $0, 112(DI) + SETCS 112(DI) + SETOS 113(DI) + SETEQ 114(DI) + SETMI 115(DI) + SETPS 116(DI) + MOVQ BX, AX + CMPXCHGL CX, 40(SI) + MOVQ 40(SI), DX + MOVQ DX, 120(DI) + MOVQ AX, 128(DI) + MOVQ $0, 136(DI) + SETCS 136(DI) + SETOS 137(DI) + SETEQ 138(DI) + SETMI 139(DI) + SETPS 140(DI) + + MOVQ BX, AX + CMPXCHGQ CX, 48(SI) + MOVQ 48(SI), DX + MOVQ DX, 144(DI) + MOVQ AX, 152(DI) + MOVQ $0, 160(DI) + SETCS 160(DI) + SETOS 161(DI) + SETEQ 162(DI) + SETMI 163(DI) + SETPS 164(DI) + MOVQ BX, AX + CMPXCHGQ CX, 56(SI) + MOVQ 56(SI), DX + MOVQ DX, 168(DI) + MOVQ AX, 176(DI) + MOVQ $0, 184(DI) + SETCS 184(DI) + SETOS 185(DI) + SETEQ 186(DI) + SETMI 187(DI) + SETPS 188(DI) + RET + +// compareExchangePairSemantics validates CMPXCHG8B and CMPXCHG16B, including +// accumulator preservation on success and replacement on failure. +TEXT ·compareExchangePairSemantics(SB), NOSPLIT, $0-48 + MOVQ out+0(FP), DI + MOVQ memory+8(FP), SI + MOVQ expectedLow+16(FP), AX + MOVQ expectedHigh+24(FP), DX + MOVQ desiredLow+32(FP), BX + MOVQ desiredHigh+40(FP), CX + CMPXCHG8B 16(SI) + MOVQ 16(SI), R8 + MOVQ R8, 0(DI) + MOVQ AX, 8(DI) + MOVQ DX, 16(DI) + MOVQ $0, 24(DI) + SETEQ 24(DI) + + MOVQ expectedLow+16(FP), AX + MOVQ expectedHigh+24(FP), DX + MOVQ desiredLow+32(FP), BX + MOVQ desiredHigh+40(FP), CX + CMPXCHG16B 0(SI) + MOVQ 0(SI), R8 + MOVQ 8(SI), R9 + MOVQ R8, 32(DI) + MOVQ R9, 40(DI) + MOVQ AX, 48(DI) + MOVQ DX, 56(DI) + MOVQ $0, 64(DI) + SETEQ 64(DI) + RET + +// parallelBitSemantics validates PDEP/PEXT L/Q semantics, register and memory +// mask forms, sparse masks, and the required zero extension of L results. +TEXT ·parallelBitSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), DI + MOVQ mask+8(FP), AX + MOVQ source+16(FP), BX + PDEPQ AX, BX, CX + MOVQ CX, 0(DI) + PDEPQ mask+8(FP), BX, CX + MOVQ CX, 8(DI) + PEXTQ AX, BX, CX + MOVQ CX, 16(DI) + PEXTQ mask+8(FP), BX, CX + MOVQ CX, 24(DI) + MOVQ $-1, CX + PDEPL AX, BX, CX + MOVQ CX, 32(DI) + MOVQ $-1, CX + PDEPL mask+8(FP), BX, CX + MOVQ CX, 40(DI) + MOVQ $-1, CX + PEXTL AX, BX, CX + MOVQ CX, 48(DI) + MOVQ $-1, CX + PEXTL mask+8(FP), BX, CX + MOVQ CX, 56(DI) + RET + +// bitTestRegisterSemantics covers every BT/BTC/BTR/BTS width and verifies +// both CF and the width-specific register write behavior. +TEXT ·bitTestRegisterSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), DI + MOVQ value+8(FP), AX + BTW $-1, AX + MOVQ AX, 0(DI) + SETCS 8(DI) + MOVQ value+8(FP), AX + MOVQ index+16(FP), CX + BTCW CX, AX + MOVQ AX, 16(DI) + SETCS 24(DI) + MOVQ value+8(FP), AX + BTRW $4, AX + MOVQ AX, 32(DI) + SETCS 40(DI) + MOVQ value+8(FP), AX + MOVQ index+16(FP), CX + BTSW CX, AX + MOVQ AX, 48(DI) + SETCS 56(DI) + + MOVQ value+8(FP), AX + BTL $-1, AX + MOVQ AX, 64(DI) + SETCS 72(DI) + MOVQ value+8(FP), AX + MOVQ index+16(FP), CX + BTCL CX, AX + MOVQ AX, 80(DI) + SETCS 88(DI) + MOVQ value+8(FP), AX + BTRL $4, AX + MOVQ AX, 96(DI) + SETCS 104(DI) + MOVQ value+8(FP), AX + MOVQ index+16(FP), CX + BTSL CX, AX + MOVQ AX, 112(DI) + SETCS 120(DI) + + MOVQ value+8(FP), AX + BTQ $-1, AX + MOVQ AX, 128(DI) + SETCS 136(DI) + MOVQ value+8(FP), AX + MOVQ index+16(FP), CX + BTCQ CX, AX + MOVQ AX, 144(DI) + SETCS 152(DI) + MOVQ value+8(FP), AX + BTRQ $4, AX + MOVQ AX, 160(DI) + SETCS 168(DI) + MOVQ value+8(FP), AX + MOVQ index+16(FP), CX + BTSQ CX, AX + MOVQ AX, 176(DI) + SETCS 184(DI) + RET + +// bitTestMemorySemantics checks the unbounded memory bit string behavior for +// positive and negative register indexes at W/L/Q widths, plus imm8 masking. +TEXT ·bitTestMemorySemantics(SB), NOSPLIT, $0-16 + MOVQ out+0(FP), DI + MOVQ data+8(FP), BX + MOVQ $17, CX + BTW CX, 8(BX) + SETCS 0(DI) + BTCW CX, 8(BX) + SETCS 1(DI) + MOVQ $-1, CX + BTRW CX, 8(BX) + SETCS 2(DI) + BTSW $-128, 8(BX) + SETCS 3(DI) + + MOVQ $33, CX + BTL CX, 32(BX) + SETCS 4(DI) + BTCL CX, 32(BX) + SETCS 5(DI) + MOVQ $-1, CX + BTRL CX, 32(BX) + SETCS 6(DI) + BTSL $-128, 32(BX) + SETCS 7(DI) + + MOVQ $65, CX + BTQ CX, 56(BX) + SETCS 8(DI) + BTCQ CX, 56(BX) + SETCS 9(DI) + MOVQ $-1, CX + BTRQ CX, 56(BX) + SETCS 10(DI) + BTSQ $-128, 56(BX) + SETCS 11(DI) + RET + +// packedWordMultiplyAddSemantics covers PMADDWL's MMX/XMM rows and +// VPMADDWD's XMM/YMM rows using signed products and wrapping dword sums. +TEXT ·packedWordMultiplyAddSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), DI + MOVQ a+8(FP), BX + MOVQ b+16(FP), CX + MOVQ (CX), M0 + PMADDWL (BX), M0 + MOVQ M0, 0(DI) + EMMS + MOVOU (CX), X0 + PMADDWL (BX), X0 + MOVOU X0, 8(DI) + MOVOU (BX), X0 + MOVOU (CX), X1 + VPMADDWD X0, X1, X2 + MOVOU X2, 24(DI) + VMOVDQU (BX), Y0 + VMOVDQU (CX), Y1 + VPMADDWD Y0, Y1, Y2 + VMOVDQU Y2, 40(DI) + VZEROUPPER + RET + +// packedUnsignedSignedByteMultiplyAddSemantics verifies the asymmetric +// signed/unsigned operand order and signed-word saturation for legacy XMM and +// VEX XMM/YMM PMADDUBSW forms. +TEXT ·packedUnsignedSignedByteMultiplyAddSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), DI + MOVQ signed+8(FP), BX + MOVQ unsigned+16(FP), CX + MOVOU (CX), X0 + PMADDUBSW (BX), X0 + MOVOU X0, 0(DI) + MOVOU (CX), X1 + VPMADDUBSW (BX), X1, X2 + MOVOU X2, 16(DI) + VMOVDQU (CX), Y1 + VPMADDUBSW (BX), Y1, Y2 + VMOVDQU Y2, 32(DI) + VZEROUPPER + RET + +// packedDotProductSemantics validates unsigned-byte/signed-byte operand +// order, signed-word products, wrapping accumulation, and both saturating +// variants. Plan 9's first operand is the signed r/m source for BUSD. +TEXT ·packedDotProductSemantics(SB), NOSPLIT, $0-48 + MOVQ out+0(FP), AX + MOVQ signedBytes+8(FP), BX + MOVQ unsignedBytes+16(FP), CX + MOVQ wordsA+24(FP), DX + MOVQ wordsB+32(FP), SI + MOVQ accumulator+40(FP), DI + + VMOVDQU32 (DI), Z0 + VMOVDQU8 (CX), Z1 + VMOVDQU8 (BX), Z2 + VPDPBUSD Z2, Z1, Z0 + VMOVDQU32 Z0, 0(AX) + + VMOVDQU32 (DI), Z0 + VPDPBUSDS Z2, Z1, Z0 + VMOVDQU32 Z0, 64(AX) + + VMOVDQU32 (DI), Z0 + VMOVDQU16 (DX), Z1 + VMOVDQU16 (SI), Z2 + VPDPWSSD Z2, Z1, Z0 + VMOVDQU32 Z0, 128(AX) + + VMOVDQU32 (DI), Z0 + VPDPWSSDS Z2, Z1, Z0 + VMOVDQU32 Z0, 192(AX) + RET + +// packedIntegerMinMaxSemantics covers every signed/unsigned B/W/D/Q minimum +// and maximum in the complete VEX/EVEX family. +TEXT ·packedIntegerMinMaxSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), BX + MOVQ b+16(FP), CX + VMOVDQU8 (BX), Z0 + VMOVDQU8 (CX), Z1 + VPMINSB Z0, Z1, Z2 + VMOVDQU8 Z2, 0(AX) + VPMINUB Z0, Z1, Z2 + VMOVDQU8 Z2, 64(AX) + VPMAXSB Z0, Z1, Z2 + VMOVDQU8 Z2, 128(AX) + VPMAXUB Z0, Z1, Z2 + VMOVDQU8 Z2, 192(AX) + VPMINSW Z0, Z1, Z2 + VMOVDQU16 Z2, 256(AX) + VPMINUW Z0, Z1, Z2 + VMOVDQU16 Z2, 320(AX) + VPMAXSW Z0, Z1, Z2 + VMOVDQU16 Z2, 384(AX) + VPMAXUW Z0, Z1, Z2 + VMOVDQU16 Z2, 448(AX) + VPMINSD Z0, Z1, Z2 + VMOVDQU32 Z2, 512(AX) + VPMINUD Z0, Z1, Z2 + VMOVDQU32 Z2, 576(AX) + VPMAXSD Z0, Z1, Z2 + VMOVDQU32 Z2, 640(AX) + VPMAXUD Z0, Z1, Z2 + VMOVDQU32 Z2, 704(AX) + VPMINSQ Z0, Z1, Z2 + VMOVDQU64 Z2, 768(AX) + VPMINUQ Z0, Z1, Z2 + VMOVDQU64 Z2, 832(AX) + VPMAXSQ Z0, Z1, Z2 + VMOVDQU64 Z2, 896(AX) + VPMAXUQ Z0, Z1, Z2 + VMOVDQU64 Z2, 960(AX) + RET + +// inLaneFloatingPermuteSemantics covers immediate and variable-control +// VPERMILPS/VPERMILPD and makes the Plan 9 control/data operand order visible. +TEXT ·inLaneFloatingPermuteSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), DI + MOVQ data+8(FP), BX + MOVQ control+16(FP), CX + VPERMILPS $0x1B, (BX), X0 + MOVOU X0, 0(DI) + VPERMILPS $0x1B, (BX), Y0 + VMOVDQU Y0, 16(DI) + VMOVDQU (BX), Y1 + VPERMILPS (CX), Y1, Y2 + VMOVDQU Y2, 48(DI) + VPERMILPD $0x05, (BX), Y0 + VMOVDQU Y0, 80(DI) + VMOVDQU (BX), Y1 + VPERMILPD (CX), Y1, Y2 + VMOVDQU Y2, 112(DI) + VZEROUPPER + RET + +// packedWordMultiplySemantics covers low, signed-high, unsigned-high, and +// rounded signed-high products in both legacy and VEX forms. +TEXT ·packedWordMultiplySemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), BX + MOVQ b+16(FP), CX + MOVOU (BX), X0 + MOVOU (CX), X1 + PMULLW X0, X1 + MOVOU X1, 0(AX) + MOVOU (BX), X0 + MOVOU (CX), X1 + PMULHW X0, X1 + MOVOU X1, 16(AX) + MOVOU (BX), X0 + MOVOU (CX), X1 + PMULHUW X0, X1 + MOVOU X1, 32(AX) + MOVOU (BX), X0 + MOVOU (CX), X1 + PMULHRSW X0, X1 + MOVOU X1, 48(AX) + MOVOU (BX), X0 + MOVOU (CX), X1 + VPMULLW X0, X1, X2 + MOVOU X2, 64(AX) + VPMULHW X0, X1, X2 + MOVOU X2, 80(AX) + VPMULHUW X0, X1, X2 + MOVOU X2, 96(AX) + VPMULHRSW X0, X1, X2 + MOVOU X2, 112(AX) + RET + +// packedFloatShuffleSemantics checks the per-128-bit-lane selector rules for +// packed single and packed double legacy/VEX shuffles. +TEXT ·packedFloatShuffleSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), BX + MOVQ b+16(FP), CX + MOVOU (BX), X0 + MOVOU (CX), X1 + SHUFPS $0x1b, X0, X1 + MOVOU X1, 0(AX) + MOVOU (BX), X0 + MOVOU (CX), X1 + SHUFPD $0x02, X0, X1 + MOVOU X1, 16(AX) + VMOVDQU (BX), Y0 + VMOVDQU (CX), Y1 + VSHUFPS $0x1b, Y0, Y1, Y2 + VMOVDQU Y2, 32(AX) + VSHUFPD $0x0a, Y0, Y1, Y2 + VMOVDQU Y2, 64(AX) + VZEROUPPER + RET + +// immediatePackedBlendSemantics covers every Go 1.27 immediate packed-blend +// opcode. A non-palindromic mask validates source order, and the Y-width +// VPBLENDW result validates that its eight mask bits repeat per 128-bit lane. +TEXT ·immediatePackedBlendSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), BX + MOVQ b+16(FP), CX + + MOVOU (CX), X0 + MOVOU (BX), X1 + PBLENDW $0xa5, X1, X0 + MOVOU X0, 0(AX) + MOVOU (CX), X0 + BLENDPS $0xa5, (BX), X0 + MOVOU X0, 16(AX) + MOVOU (CX), X0 + BLENDPD $0xa5, (BX), X0 + MOVOU X0, 32(AX) + + MOVOU (CX), X1 + VPBLENDW $0xa5, (BX), X1, X2 + MOVOU X2, 48(AX) + VMOVDQU (BX), Y0 + VMOVDQU (CX), Y1 + VPBLENDW $0xa5, Y0, Y1, Y2 + VMOVDQU Y2, 64(AX) + + MOVOU (BX), X0 + MOVOU (CX), X1 + VPBLENDD $0xa5, X0, X1, X2 + MOVOU X2, 96(AX) + VMOVDQU (CX), Y1 + VPBLENDD $0xa5, (BX), Y1, Y2 + VMOVDQU Y2, 112(AX) + + MOVOU (CX), X1 + VBLENDPS $0xa5, (BX), X1, X2 + MOVOU X2, 144(AX) + VMOVDQU (BX), Y0 + VMOVDQU (CX), Y1 + VBLENDPS $0xa5, Y0, Y1, Y2 + VMOVDQU Y2, 160(AX) + + MOVOU (BX), X0 + MOVOU (CX), X1 + VBLENDPD $0xa5, X0, X1, X2 + MOVOU X2, 192(AX) + VMOVDQU (CX), Y1 + VBLENDPD $0xa5, (BX), Y1, Y2 + VMOVDQU Y2, 208(AX) + VZEROUPPER + RET + +// packedUnpackSemantics covers low/high interleaving for every 8/16/32/64-bit +// legacy opcode and every Y-width V opcode, including per-128-bit-lane rules. +TEXT ·packedUnpackSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), BX + MOVQ b+16(FP), CX + + MOVOU (CX), X0 + PUNPCKLBW (BX), X0 + MOVOU X0, 0(AX) + MOVOU (CX), X0 + PUNPCKHBW (BX), X0 + MOVOU X0, 16(AX) + MOVOU (CX), X0 + PUNPCKLWL (BX), X0 + MOVOU X0, 32(AX) + MOVOU (CX), X0 + PUNPCKHWL (BX), X0 + MOVOU X0, 48(AX) + MOVOU (CX), X0 + PUNPCKLLQ (BX), X0 + MOVOU X0, 64(AX) + MOVOU (CX), X0 + PUNPCKHLQ (BX), X0 + MOVOU X0, 80(AX) + MOVOU (CX), X0 + PUNPCKLQDQ (BX), X0 + MOVOU X0, 96(AX) + MOVOU (CX), X0 + PUNPCKHQDQ (BX), X0 + MOVOU X0, 112(AX) + + VMOVDQU (BX), Y0 + VMOVDQU (CX), Y1 + VPUNPCKLBW Y0, Y1, Y2 + VMOVDQU Y2, 128(AX) + VPUNPCKHBW Y0, Y1, Y2 + VMOVDQU Y2, 160(AX) + VPUNPCKLWD Y0, Y1, Y2 + VMOVDQU Y2, 192(AX) + VPUNPCKHWD Y0, Y1, Y2 + VMOVDQU Y2, 224(AX) + VPUNPCKLDQ Y0, Y1, Y2 + VMOVDQU Y2, 256(AX) + VPUNPCKHDQ Y0, Y1, Y2 + VMOVDQU Y2, 288(AX) + VPUNPCKLQDQ Y0, Y1, Y2 + VMOVDQU Y2, 320(AX) + VPUNPCKHQDQ Y0, Y1, Y2 + VMOVDQU Y2, 352(AX) + VZEROUPPER + RET + +// qwordPermuteSemantics validates signed immediate selectors for both +// bit-identical qword permute opcodes using AVX2 instructions. +TEXT ·qwordPermuteSemantics(SB), NOSPLIT, $0-16 + MOVQ out+0(FP), AX + MOVQ data+8(FP), BX + VMOVDQU (BX), Y0 + VPERMQ $-40, Y0, Y2 + VMOVDQU Y2, 0(AX) + VPERMPD $-40, Y0, Y2 + VMOVDQU Y2, 32(AX) + VZEROUPPER + RET + +// qwordVariablePermuteSemantics validates Plan 9's data,control,destination +// order. It is assembled natively but only executed through lowered LLVM IR, +// because the original instructions require AVX-512. +TEXT ·qwordVariablePermuteSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), AX + MOVQ data+8(FP), BX + MOVQ control+16(FP), CX + VMOVDQU (BX), Y0 + VMOVDQU (CX), Y1 + VPERMQ Y0, Y1, Y2 + VMOVDQU Y2, 0(AX) + VPERMPD Y0, Y1, Y2 + VMOVDQU Y2, 32(AX) + VZEROUPPER + RET + +// packedFloatMoveVEXSemantics executes on the native oracle and validates the +// bit-preserving behavior of all four _yvmovapd opcodes without requiring +// AVX-512. Aligned moves use register operands so the input pointer may be +// arbitrarily aligned. +TEXT ·packedFloatMoveVEXSemantics(SB), NOSPLIT, $0-16 + MOVQ out+0(FP), AX + MOVQ src+8(FP), BX + VMOVDQU (BX), Y0 + VMOVAPD Y0, Y1 + VMOVDQU Y1, 0(AX) + VMOVAPS Y0, Y1 + VMOVDQU Y1, 32(AX) + VMOVUPD (BX), Y1 + VMOVUPD Y1, 64(AX) + VMOVUPS (BX), Y1 + VMOVUPS Y1, 96(AX) + VZEROUPPER + RET + +// packedFloatMoveMaskSemantics validates PS dword masks, PD qword masks, +// merge/zero loads, register moves, and masked memory stores at X/Y/Z widths. +// It is assembled by the native oracle but executed only after LLVM lowering, +// because the original mask forms require AVX-512. +TEXT ·packedFloatMoveMaskSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), AX + MOVQ src+8(FP), BX + MOVQ old+16(FP), CX + MOVW $0xa55a, DX + KMOVW DX, K1 + + VMOVUPS (CX), X0 + VMOVUPS (BX), K1, X0 + VMOVUPS X0, 0(AX) + VMOVUPS.Z (BX), K1, X0 + VMOVUPS X0, 16(AX) + VMOVUPS (CX), X0 + VMOVUPS (BX), X1 + VMOVAPS X1, K1, X0 + VMOVUPS X0, 32(AX) + VMOVUPS (CX), X0 + VMOVUPS X0, 48(AX) + VMOVUPS (BX), X1 + VMOVAPS.Z X1, K1, 48(AX) + + VMOVUPD (CX), X0 + VMOVUPD (BX), K1, X0 + VMOVUPD X0, 64(AX) + VMOVAPD.Z (BX), K1, X0 + VMOVUPD X0, 80(AX) + VMOVUPD (CX), X0 + VMOVUPD X0, 96(AX) + VMOVUPD (BX), X1 + VMOVAPD.Z X1, K1, 96(AX) + + VMOVAPS (CX), Y0 + VMOVAPS (BX), K1, Y0 + VMOVUPS Y0, 112(AX) + VMOVAPS.Z (BX), K1, Y0 + VMOVUPS Y0, 144(AX) + VMOVUPS (CX), Y0 + VMOVUPS Y0, 176(AX) + VMOVUPS (BX), Y1 + VMOVUPS.Z Y1, K1, 176(AX) + + VMOVAPD (CX), Y0 + VMOVAPD (BX), K1, Y0 + VMOVUPD Y0, 208(AX) + VMOVAPD.Z (BX), K1, Y0 + VMOVUPD Y0, 240(AX) + VMOVUPD (CX), Y0 + VMOVUPD Y0, 272(AX) + VMOVUPD (BX), Y1 + VMOVUPD.Z Y1, K1, 272(AX) + + VMOVUPS (CX), Z0 + VMOVUPS (BX), K1, Z0 + VMOVUPS Z0, 304(AX) + VMOVUPS.Z (BX), K1, Z0 + VMOVUPS Z0, 368(AX) + VMOVAPS (CX), Z0 + VMOVAPS Z0, 432(AX) + VMOVAPS (BX), Z1 + VMOVAPS.Z Z1, K1, 432(AX) + + VMOVUPD (CX), Z0 + VMOVUPD (BX), K1, Z0 + VMOVUPD Z0, 496(AX) + VMOVUPD.Z (BX), K1, Z0 + VMOVUPD Z0, 560(AX) + VMOVAPD (CX), Z0 + VMOVAPD Z0, 624(AX) + VMOVAPD (BX), Z1 + VMOVAPD.Z Z1, K1, 624(AX) + VZEROUPPER + RET + +// packedSignExtendMoveVEXSemantics executes all six legacy and all six VEX +// signed widening opcodes. V forms use register sources to cover the form used +// by Kyber; legacy forms use exact-width memory sources. +TEXT ·packedSignExtendMoveVEXSemantics(SB), NOSPLIT, $0-16 + MOVQ out+0(FP), AX + MOVQ src+8(FP), BX + MOVOU (BX), X1 + PMOVSXBW (BX), X0 + MOVOU X0, 0(AX) + PMOVSXBD (BX), X0 + MOVOU X0, 16(AX) + PMOVSXBQ (BX), X0 + MOVOU X0, 32(AX) + PMOVSXWD (BX), X0 + MOVOU X0, 48(AX) + PMOVSXWQ (BX), X0 + MOVOU X0, 64(AX) + PMOVSXDQ (BX), X0 + MOVOU X0, 80(AX) + VPMOVSXBW X1, Y0 + VMOVUPD Y0, 96(AX) + VPMOVSXBD X1, Y0 + VMOVUPD Y0, 128(AX) + VPMOVSXBQ X1, Y0 + VMOVUPD Y0, 160(AX) + VPMOVSXWD X1, Y0 + VMOVUPD Y0, 192(AX) + VPMOVSXWQ X1, Y0 + VMOVUPD Y0, 224(AX) + VPMOVSXDQ X1, Y0 + VMOVUPD Y0, 256(AX) + VZEROUPPER + RET + +// packedSignExtendMoveMaskSemantics validates register-source merge masking +// and exact-width memory-source zero masking for all six EVEX instructions at +// Z width. It is executed only after LLVM lowering because it requires AVX-512. +TEXT ·packedSignExtendMoveMaskSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), AX + MOVQ src+8(FP), BX + MOVQ old+16(FP), CX + MOVQ $0xa55aa55a, DX + KMOVQ DX, K1 + VMOVUPD (BX), Y1 + VMOVUPD (CX), Z0 + VPMOVSXBW Y1, K1, Z0 + VMOVUPD Z0, 0(AX) + VPMOVSXBW.Z (BX), K1, Z0 + VMOVUPD Z0, 64(AX) + MOVOU (BX), X1 + VMOVUPD (CX), Z0 + VPMOVSXBD X1, K1, Z0 + VMOVUPD Z0, 128(AX) + VPMOVSXBD.Z (BX), K1, Z0 + VMOVUPD Z0, 192(AX) + VMOVUPD (CX), Z0 + VPMOVSXBQ X1, K1, Z0 + VMOVUPD Z0, 256(AX) + VPMOVSXBQ.Z (BX), K1, Z0 + VMOVUPD Z0, 320(AX) + VMOVUPD (CX), Z0 + VPMOVSXWD Y1, K1, Z0 + VMOVUPD Z0, 384(AX) + VPMOVSXWD.Z (BX), K1, Z0 + VMOVUPD Z0, 448(AX) + VMOVUPD (CX), Z0 + VPMOVSXWQ X1, K1, Z0 + VMOVUPD Z0, 512(AX) + VPMOVSXWQ.Z (BX), K1, Z0 + VMOVUPD Z0, 576(AX) + VMOVUPD (CX), Z0 + VPMOVSXDQ Y1, K1, Z0 + VMOVUPD Z0, 640(AX) + VPMOVSXDQ.Z (BX), K1, Z0 + VMOVUPD Z0, 704(AX) + VZEROUPPER + RET + // goHexVectorOps covers the packed integer forms used by go-hex. Each result // occupies one 16-byte block in out, in the order documented by its Go test. TEXT ·goHexVectorOps(SB), NOSPLIT, $0-24 @@ -208,3 +1169,657 @@ TEXT ·packedArithmeticShift32(SB), NOSPLIT, $0-16 PSRAL $32, X0 MOVOU X0, 16(AX) RET + +// packedSubtractSemantics covers wrapping and signed/unsigned saturation, +// including the non-commutative rm,v,destination order of the V forms. +TEXT ·packedSubtractSemantics(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), BX + MOVQ b+16(FP), CX + MOVOU (BX), X0 + MOVOU (CX), X1 + PSUBSB X1, X0 + MOVOU X0, 0(AX) + MOVOU (BX), X0 + MOVOU (CX), X1 + PSUBSW X1, X0 + MOVOU X0, 16(AX) + MOVOU (BX), X0 + MOVOU (CX), X1 + VPSUBUSB X1, X0, X2 + MOVOU X2, 32(AX) + MOVOU (BX), X0 + MOVOU (CX), X1 + VPSUBUSW X1, X0, X2 + MOVOU X2, 48(AX) + MOVOU (BX), X0 + MOVOU (CX), X1 + VPSUBQ X1, X0, X2 + MOVOU X2, 64(AX) + RET + +// parityBranches validates both halves of the Go assembler's parity branch +// alias family against TESTB's low-byte even-parity flag. +TEXT ·parityBranches(SB), NOSPLIT, $0-16 + MOVBLZX value+0(FP), AX + MOVQ $0, DX + TESTB AL, AL + JP parity_even + JMP parity_even_done +parity_even: + ORQ $1, DX +parity_even_done: + TESTB AL, AL + JNP parity_odd + JMP parity_odd_done +parity_odd: + ORQ $2, DX +parity_odd_done: + MOVQ DX, ret+8(FP) + RET + +// unorderedBranch validates that UCOMISD sets PF for NaN inputs. +TEXT ·unorderedBranch(SB), NOSPLIT, $0-16 + MOVSD value+0(FP), X0 + UCOMISD X0, X0 + JP unordered + MOVQ $0, ret+8(FP) + RET +unordered: + MOVQ $1, ret+8(FP) + RET + +// packedFloatToDwordModes covers CVTPS2PL's four MXCSR rounding modes and +// CVTTPS2PL's rounding-mode-independent truncation. It also exercises the +// STMXCSR/LDMXCSR memory forms through a real Go assembly stack frame. +TEXT ·packedFloatToDwordModes(SB), NOSPLIT, $8-16 + MOVQ out+0(FP), AX + MOVQ src+8(FP), BX + MOVOU (BX), X0 + + STMXCSR mxcsrOrig-8(SP) + MOVL mxcsrOrig-8(SP), DX + ANDL $0xffff9fff, DX + + MOVL DX, mxcsrMode-4(SP) + LDMXCSR mxcsrMode-4(SP) + CVTPS2PL X0, X1 + MOVOU X1, 0(AX) + + ORL $0x2000, DX + MOVL DX, mxcsrMode-4(SP) + LDMXCSR mxcsrMode-4(SP) + CVTPS2PL X0, X1 + MOVOU X1, 16(AX) + + ANDL $0xffff9fff, DX + ORL $0x4000, DX + MOVL DX, mxcsrMode-4(SP) + LDMXCSR mxcsrMode-4(SP) + CVTPS2PL X0, X1 + MOVOU X1, 32(AX) + + ORL $0x2000, DX + MOVL DX, mxcsrMode-4(SP) + LDMXCSR mxcsrMode-4(SP) + CVTPS2PL X0, X1 + MOVOU X1, 48(AX) + + CVTTPS2PL X0, X1 + MOVOU X1, 64(AX) + LDMXCSR mxcsrOrig-8(SP) + RET + +// sameWidthPackedConversionSemantics covers the five opcodes sharing Go +// 1.27's _yvcvtdq2ps table. It verifies every conversion mode, both square +// root lane widths, and all four EVEX explicit-rounding controls. +TEXT ·sameWidthPackedConversionSemantics(SB), NOSPLIT, $8-40 + MOVQ out+0(FP), AX + MOVQ ints+8(FP), BX + MOVQ floats+16(FP), CX + MOVQ squares32+24(FP), DX + MOVQ squares64+32(FP), SI + + STMXCSR sameWidthMXCSROrig-8(SP) + MOVL sameWidthMXCSROrig-8(SP), R9 + ANDL $0xffff9fff, R9 + MOVL R9, sameWidthMXCSRNearest-4(SP) + LDMXCSR sameWidthMXCSRNearest-4(SP) + + VMOVDQU32 (BX), Z0 + VCVTDQ2PS Z0, Z1 + VMOVDQU32 Z1, 0(AX) + + VMOVUPS (CX), Z0 + VCVTPS2DQ Z0, Z1 + VMOVDQU32 Z1, 64(AX) + VCVTTPS2DQ Z0, Z1 + VMOVDQU32 Z1, 128(AX) + + VMOVUPS (DX), Z0 + VSQRTPS Z0, Z1 + VMOVDQU32 Z1, 192(AX) + VMOVUPD (SI), Z0 + VSQRTPD Z0, Z1 + VMOVDQU64 Z1, 256(AX) + + VMOVUPS (CX), Z0 + VCVTPS2DQ.RN_SAE Z0, Z1 + VMOVDQU32 Z1, 320(AX) + VCVTPS2DQ.RD_SAE Z0, Z1 + VMOVDQU32 Z1, 384(AX) + VCVTPS2DQ.RU_SAE Z0, Z1 + VMOVDQU32 Z1, 448(AX) + VCVTPS2DQ.RZ_SAE Z0, Z1 + VMOVDQU32 Z1, 512(AX) + + LDMXCSR sameWidthMXCSROrig-8(SP) + RET + +// packedSingleToDouble validates both register and exact-width memory inputs. +TEXT ·packedSingleToDouble(SB), NOSPLIT, $0-16 + MOVQ out+0(FP), AX + MOVQ src+8(FP), BX + MOVOU (BX), X0 + CVTPS2PD X0, X1 + MOVOU X1, 0(AX) + CVTPS2PD 8(BX), X1 + MOVOU X1, 16(AX) + RET + +// conditionalMoveCodes establishes CF=0, PF=1, ZF=0, SF=1, OF=1, then +// checks all 16 condition codes using the yml_rl memory-source form. +TEXT ·conditionalMoveCodes(SB), NOSPLIT, $0-16 + MOVQ out+0(FP), AX + MOVQ src+8(FP), BX + MOVQ $0x7fffffffffffffff, R8 + ADDQ $1, R8 + MOVQ $-1, CX + CMOVQCC 0(BX), CX + MOVQ CX, 0(AX) + MOVQ $-1, CX + CMOVQCS 8(BX), CX + MOVQ CX, 8(AX) + MOVQ $-1, CX + CMOVQEQ 16(BX), CX + MOVQ CX, 16(AX) + MOVQ $-1, CX + CMOVQGE 24(BX), CX + MOVQ CX, 24(AX) + MOVQ $-1, CX + CMOVQGT 32(BX), CX + MOVQ CX, 32(AX) + MOVQ $-1, CX + CMOVQHI 40(BX), CX + MOVQ CX, 40(AX) + MOVQ $-1, CX + CMOVQLE 48(BX), CX + MOVQ CX, 48(AX) + MOVQ $-1, CX + CMOVQLS 56(BX), CX + MOVQ CX, 56(AX) + MOVQ $-1, CX + CMOVQLT 64(BX), CX + MOVQ CX, 64(AX) + MOVQ $-1, CX + CMOVQMI 72(BX), CX + MOVQ CX, 72(AX) + MOVQ $-1, CX + CMOVQNE 80(BX), CX + MOVQ CX, 80(AX) + MOVQ $-1, CX + CMOVQOC 88(BX), CX + MOVQ CX, 88(AX) + MOVQ $-1, CX + CMOVQOS 96(BX), CX + MOVQ CX, 96(AX) + MOVQ $-1, CX + CMOVQPC 104(BX), CX + MOVQ CX, 104(AX) + MOVQ $-1, CX + CMOVQPL 112(BX), CX + MOVQ CX, 112(AX) + MOVQ $-1, CX + CMOVQPS 120(BX), CX + MOVQ CX, 120(AX) + RET + +// fma3Semantics validates all three operand orders, all six arithmetic modes, +// packed single/double lanes, and scalar upper-lane copying using VEX forms +// that execute on both the native oracle and the lowered LLVM binary. +TEXT ·fma3Semantics(SB), NOSPLIT, $0-56 + MOVQ out+0(FP), AX + MOVQ a64+8(FP), BX + MOVQ b64+16(FP), CX + MOVQ c64+24(FP), DX + MOVQ a32+32(FP), SI + MOVQ b32+40(FP), DI + MOVQ c32+48(FP), R8 + + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DX), X2 + VFMADD132PD X0, X1, X2 + VMOVUPD X2, 0(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DX), X2 + VFMADD213PD X0, X1, X2 + VMOVUPD X2, 16(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DX), X2 + VFMADD231PD X0, X1, X2 + VMOVUPD X2, 32(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DX), X2 + VFMSUB132PD X0, X1, X2 + VMOVUPD X2, 48(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DX), X2 + VFNMADD213PD X0, X1, X2 + VMOVUPD X2, 64(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DX), X2 + VFNMSUB231PD X0, X1, X2 + VMOVUPD X2, 80(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DX), X2 + VFMADDSUB132PD X0, X1, X2 + VMOVUPD X2, 96(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DX), X2 + VFMSUBADD231PD X0, X1, X2 + VMOVUPD X2, 112(AX) + + VMOVUPS (SI), X0 + VMOVUPS (DI), X1 + VMOVUPS (R8), X2 + VFMADD132PS X0, X1, X2 + VMOVUPS X2, 128(AX) + VMOVUPS (SI), X0 + VMOVUPS (DI), X1 + VMOVUPS (R8), X2 + VFMSUB213PS X0, X1, X2 + VMOVUPS X2, 144(AX) + VMOVUPS (SI), X0 + VMOVUPS (DI), X1 + VMOVUPS (R8), X2 + VFNMADD231PS X0, X1, X2 + VMOVUPS X2, 160(AX) + VMOVUPS (SI), X0 + VMOVUPS (DI), X1 + VMOVUPS (R8), X2 + VFNMSUB132PS X0, X1, X2 + VMOVUPS X2, 176(AX) + VMOVUPS (SI), X0 + VMOVUPS (DI), X1 + VMOVUPS (R8), X2 + VFMADDSUB213PS X0, X1, X2 + VMOVUPS X2, 192(AX) + VMOVUPS (SI), X0 + VMOVUPS (DI), X1 + VMOVUPS (R8), X2 + VFMSUBADD231PS X0, X1, X2 + VMOVUPS X2, 208(AX) + + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DX), X2 + VFMADD132SD X0, X1, X2 + VMOVUPD X2, 224(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMOVUPD (DX), X2 + VFMSUB213SD X0, X1, X2 + VMOVUPD X2, 240(AX) + VMOVUPS (SI), X0 + VMOVUPS (DI), X1 + VMOVUPS (R8), X2 + VFNMADD231SS X0, X1, X2 + VMOVUPS X2, 256(AX) + VMOVUPS (SI), X0 + VMOVUPS (DI), X1 + VMOVUPS (R8), X2 + VFNMSUB132SS X0, X1, X2 + VMOVUPS X2, 272(AX) + VZEROUPPER + RET + +// binaryFloatingSemantics covers every operation in the VADD/VSUB/VMUL/ +// VDIV/VMAX/VMIN family for packed and scalar f32/f64 VEX forms. Scalar +// results also verify that upper lanes come from the second source operand. +TEXT ·binaryFloatingSemantics(SB), NOSPLIT, $0-40 + MOVQ out+0(FP), AX + MOVQ a64+8(FP), BX + MOVQ b64+16(FP), CX + MOVQ a32+24(FP), DX + MOVQ b32+32(FP), SI + + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VADDPD X0, X1, X2 + VMOVUPD X2, 0(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VSUBPD X0, X1, X2 + VMOVUPD X2, 16(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMULPD X0, X1, X2 + VMOVUPD X2, 32(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VDIVPD X0, X1, X2 + VMOVUPD X2, 48(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMAXPD X0, X1, X2 + VMOVUPD X2, 64(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMINPD X0, X1, X2 + VMOVUPD X2, 80(AX) + + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VADDPS X0, X1, X2 + VMOVUPS X2, 96(AX) + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VSUBPS X0, X1, X2 + VMOVUPS X2, 112(AX) + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VMULPS X0, X1, X2 + VMOVUPS X2, 128(AX) + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VDIVPS X0, X1, X2 + VMOVUPS X2, 144(AX) + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VMAXPS X0, X1, X2 + VMOVUPS X2, 160(AX) + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VMINPS X0, X1, X2 + VMOVUPS X2, 176(AX) + + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VADDSD X0, X1, X2 + VMOVUPD X2, 192(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VSUBSD X0, X1, X2 + VMOVUPD X2, 208(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMULSD X0, X1, X2 + VMOVUPD X2, 224(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VDIVSD X0, X1, X2 + VMOVUPD X2, 240(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMAXSD X0, X1, X2 + VMOVUPD X2, 256(AX) + VMOVUPD (BX), X0 + VMOVUPD (CX), X1 + VMINSD X0, X1, X2 + VMOVUPD X2, 272(AX) + + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VADDSS X0, X1, X2 + VMOVUPS X2, 288(AX) + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VSUBSS X0, X1, X2 + VMOVUPS X2, 304(AX) + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VMULSS X0, X1, X2 + VMOVUPS X2, 320(AX) + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VDIVSS X0, X1, X2 + VMOVUPS X2, 336(AX) + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VMAXSS X0, X1, X2 + VMOVUPS X2, 352(AX) + VMOVUPS (DX), X0 + VMOVUPS (SI), X1 + VMINSS X0, X1, X2 + VMOVUPS X2, 368(AX) + VZEROUPPER + RET + +// horizontalFloatingSemantics verifies the 128-bit lane grouping and Plan 9 +// source order for every legacy and VEX horizontal add/subtract operation. +TEXT ·horizontalFloatingSemantics(SB), NOSPLIT, $0-40 + MOVQ out+0(FP), AX + MOVQ a32+8(FP), BX + MOVQ b32+16(FP), CX + MOVQ a64+24(FP), DX + MOVQ b64+32(FP), SI + + VMOVUPS (BX), Y0 + VMOVUPS (CX), Y1 + VHADDPS Y0, Y1, Y2 + VMOVUPS Y2, 0(AX) + VMOVUPS (BX), Y0 + VMOVUPS (CX), Y1 + VHSUBPS Y0, Y1, Y2 + VMOVUPS Y2, 32(AX) + VMOVUPD (DX), Y0 + VMOVUPD (SI), Y1 + VHADDPD Y0, Y1, Y2 + VMOVUPD Y2, 64(AX) + VMOVUPD (DX), Y0 + VMOVUPD (SI), Y1 + VHSUBPD Y0, Y1, Y2 + VMOVUPD Y2, 96(AX) + + MOVUPS (BX), X0 + MOVUPS (CX), X1 + HADDPS X0, X1 + MOVUPS X1, 128(AX) + MOVUPS (BX), X0 + MOVUPS (CX), X1 + HSUBPS X0, X1 + MOVUPS X1, 144(AX) + MOVUPD (DX), X0 + MOVUPD (SI), X1 + HADDPD X0, X1 + MOVUPD X1, 160(AX) + MOVUPD (DX), X0 + MOVUPD (SI), X1 + HSUBPD X0, X1 + MOVUPD X1, 176(AX) + VZEROUPPER + RET + +// expandedEcosystemVectors covers the packed min/max family plus the scalar +// VEX move and packed-qword shift forms found by the ecosystem scan. +TEXT ·expandedEcosystemVectors(SB), NOSPLIT, $0-24 + MOVQ out+0(FP), AX + MOVQ a+8(FP), BX + MOVQ b+16(FP), CX + + MOVOU (BX), X0 + PMINUB (CX), X0 + MOVOU X0, 0(AX) + MOVOU (BX), X0 + PMINSB (CX), X0 + MOVOU X0, 16(AX) + MOVOU (BX), X0 + PMINUW (CX), X0 + MOVOU X0, 32(AX) + MOVOU (BX), X0 + PMINSW (CX), X0 + MOVOU X0, 48(AX) + MOVOU (BX), X0 + PMINUD (CX), X0 + MOVOU X0, 64(AX) + MOVOU (BX), X0 + PMINSD (CX), X0 + MOVOU X0, 80(AX) + + MOVOU (BX), X0 + PMAXUB (CX), X0 + MOVOU X0, 96(AX) + MOVOU (BX), X0 + PMAXSB (CX), X0 + MOVOU X0, 112(AX) + MOVOU (BX), X0 + PMAXUW (CX), X0 + MOVOU X0, 128(AX) + MOVOU (BX), X0 + PMAXSW (CX), X0 + MOVOU X0, 144(AX) + MOVOU (BX), X0 + PMAXUD (CX), X0 + MOVOU X0, 160(AX) + MOVOU (BX), X0 + PMAXSD (CX), X0 + MOVOU X0, 176(AX) + + MOVOU (BX), X0 + PSLLQ $13, X0 + MOVOU X0, 192(AX) + MOVOU (BX), X0 + PSRLQ $64, X0 + MOVOU X0, 208(AX) + + MOVQ $0x0123456789abcdef, DX + VMOVQ DX, X0 + VMOVQ X0, DX + MOVQ DX, 224(AX) + VMOVD DX, X0 + VMOVD X0, DX + MOVQ DX, 232(AX) + MOVOU X0, 240(AX) + MOVOU (BX), X0 + VMOVQ X0, X1 + MOVOU X1, 256(AX) + + MOVOU (BX), X0 + PAVGB (CX), X0 + MOVOU X0, 272(AX) + MOVOU (BX), X0 + PAVGW (CX), X0 + MOVOU X0, 288(AX) + + MOVOU (BX), X0 + PCMPGTB (CX), X0 + MOVOU X0, 304(AX) + MOVOU (BX), X0 + PCMPGTW (CX), X0 + MOVOU X0, 320(AX) + MOVOU (BX), X0 + PCMPGTL (CX), X0 + MOVOU X0, 336(AX) + MOVOU (BX), X0 + PCMPGTQ (CX), X0 + MOVOU X0, 352(AX) + + MOVOU (BX), X0 + PSRAW $3, X0 + MOVOU X0, 368(AX) + MOVOU (BX), X0 + PSRAW (CX), X0 + MOVOU X0, 384(AX) + + MOVOU (BX), X0 + UNPCKLPS (CX), X0 + MOVOU X0, 400(AX) + MOVOU (BX), X0 + UNPCKHPS (CX), X0 + MOVOU X0, 416(AX) + MOVOU (BX), X0 + UNPCKLPD (CX), X0 + MOVOU X0, 432(AX) + MOVOU (BX), X0 + UNPCKHPD (CX), X0 + MOVOU X0, 448(AX) + + PMOVZXBW (BX), X0 + MOVOU X0, 464(AX) + PMOVZXBD (BX), X0 + MOVOU X0, 480(AX) + PMOVZXBQ (BX), X0 + MOVOU X0, 496(AX) + PMOVZXWD (BX), X0 + MOVOU X0, 512(AX) + PMOVZXWQ (BX), X0 + MOVOU X0, 528(AX) + PMOVZXDQ (BX), X0 + MOVOU X0, 544(AX) + + MOVOU (BX), X0 + PHADDD (CX), X0 + MOVOU X0, 560(AX) + MOVOU (BX), X0 + PHADDSW (CX), X0 + MOVOU X0, 576(AX) + MOVOU (BX), X0 + PHADDW (CX), X0 + MOVOU X0, 592(AX) + MOVOU (BX), X0 + PHSUBD (CX), X0 + MOVOU X0, 608(AX) + MOVOU (BX), X0 + PHSUBSW (CX), X0 + MOVOU X0, 624(AX) + MOVOU (BX), X0 + PHSUBW (CX), X0 + MOVOU X0, 640(AX) + + PHMINPOSUW (BX), X0 + MOVOU X0, 656(AX) + + MOVOU (CX), X0 + MOVOU X0, 672(AX) + MOVOU (CX), X0 + MOVOU (BX), X1 + LEAQ 672(AX), DI + MASKMOVDQU X0, X1 + MOVOU (CX), X0 + MOVOU X0, 688(AX) + MOVOU (CX), X0 + MOVOU (BX), X1 + LEAQ 688(AX), DI + VMASKMOVDQU X0, X1 + + MOVQ $3, 800(AX) + MOVQ $0, 808(AX) + MOVOU 800(AX), X1 + MOVOU (BX), X0 + PSLLW X1, X0 + MOVOU X0, 704(AX) + MOVOU (BX), X0 + PSLLL X1, X0 + MOVOU X0, 720(AX) + MOVOU (BX), X0 + PSLLQ X1, X0 + MOVOU X0, 736(AX) + MOVOU (BX), X0 + PSRLW X1, X0 + MOVOU X0, 752(AX) + MOVOU (BX), X0 + PSRLL X1, X0 + MOVOU X0, 768(AX) + MOVOU (BX), X0 + PSRLQ X1, X0 + MOVOU X0, 784(AX) + VZEROUPPER + RET diff --git a/testdata/conformance/amd64/conformance_test.go b/testdata/conformance/amd64/conformance_test.go index e39c3750..d5d75d08 100644 --- a/testdata/conformance/amd64/conformance_test.go +++ b/testdata/conformance/amd64/conformance_test.go @@ -2,7 +2,13 @@ package amd64conformance -import "testing" +import ( + "encoding/binary" + "math" + "os" + "testing" + "unsafe" +) func TestByteMemoryDestinations(t *testing.T) { got := [4]byte{0x10, 0xf0, 0x5a, 0xa0} @@ -114,6 +120,700 @@ func TestDoubleShiftFamily(t *testing.T) { } } +func rotateLeft(value uint64, bits uint, count uint64) uint64 { + mask := uint64(1)<> (uint64(bits) - count))) & mask +} + +func rotateRight(value uint64, bits uint, count uint64) uint64 { + return rotateLeft(value, bits, uint64(bits)-count%uint64(bits)) +} + +func replaceLow(value, low uint64, bits uint) uint64 { + mask := uint64(1)<> hardwareCount + byteArithmetic = uint64(byte(int8(value) >> hardwareCount)) + } + wordCount := count & 15 + shldw := uint64(uint16(wordDst)) + shrdw := uint64(uint16(wordDst)) + if wordCount != 0 { + shldw = uint64(uint16(wordDst)<>(16-wordCount)) + shrdw = uint64(uint16(wordDst)>>wordCount | uint16(value)<<(16-wordCount)) + } + want := [14]uint64{ + replaceLow(value, rotateLeft(value, 8, count), 8), + replaceLow(value, rotateRight(value, 8, count), 8), + replaceLow(value, byteArithmetic, 8), + replaceLow(value, byteLogical, 8), + replaceLow(value, rotateLeft(value, 16, count), 16), + replaceLow(value, uint64(uint16(int16(value)>>hardwareCount)), 16), + uint64(uint32(value) << hardwareCount), + rotateRight(value, 64, count), + replaceLow(value, byteLogical, 8), + replaceLow(value, rotateLeft(value, 16, count), 16), + replaceLow(wordDst, shldw, 16), + replaceLow(wordDst, shrdw, 16), + replaceLow(value, uint64(byte(value)<<3), 8), + uint64(uint32(int32(value) >> 3)), + } + if got != want { + t.Fatalf("scalarShiftRotateSemantics(%#x, %d) = %#x, want %#x", value, count, got, want) + } + } +} + +func TestIncDecSemantics(t *testing.T) { + for _, value := range []uint64{0, 1, 0x7f, 0xff, 0xffff, 0xffffffff, 0x8123456789abcdef} { + var got [12]uint64 + incDecSemantics(&got, value) + want := [12]uint64{ + replaceLow(value, uint64(byte(value)+1), 8), + replaceLow(value, uint64(byte(value)-1), 8), + replaceLow(value, uint64(uint16(value)+1), 16), + replaceLow(value, uint64(uint16(value)-1), 16), + uint64(uint32(value) + 1), + uint64(uint32(value) - 1), + value + 1, + value - 1, + replaceLow(value, uint64(byte(value)+1), 8), + replaceLow(value, uint64(uint16(value)-1), 16), + 0x0000000000010101, + 0x0000000101000001, + } + if got != want { + t.Fatalf("incDecSemantics(%#x) = %#x, want %#x", value, got, want) + } + } +} + +func referenceScalarAddSub(add bool, bits uint, value, source uint64, registerDestination bool) (uint64, uint64) { + mask := ^uint64(0) + if bits != 64 { + mask = uint64(1)<> 32)), 0, + old16Low, old16High, old16Low, old16High, 0, + } + } + if got != want { + t.Fatalf("compareExchangePairSemantics(success=%v) = %#x, want %#x", success, got, want) + } + } +} + +func referencePDEP(mask, source uint64) uint64 { + var result uint64 + for mask != 0 { + lowest := mask & -mask + if source&1 != 0 { + result |= lowest + } + source >>= 1 + mask &= mask - 1 + } + return result +} + +func referencePEXT(mask, source uint64) uint64 { + var result, outputBit uint64 = 0, 1 + for mask != 0 { + lowest := mask & -mask + if source&lowest != 0 { + result |= outputBit + } + outputBit <<= 1 + mask &= mask - 1 + } + return result +} + +func TestParallelBitDepositExtractSemantics(t *testing.T) { + for _, tc := range []struct { + mask uint64 + source uint64 + }{ + {0, 0x0123456789abcdef}, + {^uint64(0), 0x0123456789abcdef}, + {0xaaaaaaaaaaaaaaaa, 0x0123456789abcdef}, + {0x8040201008040201, 0xfedcba9876543210}, + {0x8000000100000081, ^uint64(0)}, + } { + var got [8]uint64 + parallelBitSemantics(&got, tc.mask, tc.source) + mask32, source32 := uint64(uint32(tc.mask)), uint64(uint32(tc.source)) + want := [8]uint64{ + referencePDEP(tc.mask, tc.source), referencePDEP(tc.mask, tc.source), + referencePEXT(tc.mask, tc.source), referencePEXT(tc.mask, tc.source), + referencePDEP(mask32, source32), referencePDEP(mask32, source32), + referencePEXT(mask32, source32), referencePEXT(mask32, source32), + } + if got != want { + t.Fatalf("parallelBitSemantics(%#x, %#x) = %#x, want %#x", tc.mask, tc.source, got, want) + } + } +} + +func referenceBitTestRegister(stem string, bits int, value, index uint64) (result, carry uint64) { + bit := index & uint64(bits-1) + carry = (value >> bit) & 1 + if stem == "BT" { + return value, carry + } + mask := uint64(1) << bit + low := value + switch stem { + case "BTC": + low ^= mask + case "BTR": + low &^= mask + case "BTS": + low |= mask + } + switch bits { + case 16: + return value&^uint64(0xffff) | low&0xffff, carry + case 32: + return uint64(uint32(low)), carry + default: + return low, carry + } +} + +func TestBitTestRegisterSemantics(t *testing.T) { + const value = uint64(0xfedcba9876543210) + const index = uint64(21) + var got, want [24]uint64 + bitWidths := []int{16, 32, 64} + stems := []string{"BT", "BTC", "BTR", "BTS"} + for widthIndex, bits := range bitWidths { + for stemIndex, stem := range stems { + operandIndex := index + switch stem { + case "BT": + operandIndex = uint64(bits - 1) + case "BTR": + operandIndex = 4 + } + result, carry := referenceBitTestRegister(stem, bits, value, operandIndex) + outIndex := 2 * (widthIndex*len(stems) + stemIndex) + want[outIndex], want[outIndex+1] = result, carry + } + } + bitTestRegisterSemantics(&got, value, index) + if got != want { + t.Fatalf("bitTestRegisterSemantics() = %#x, want %#x", got, want) + } +} + +func TestBitTestMemorySemantics(t *testing.T) { + data := [9]uint64{ + ^uint64(0), uint64(1) << 17, 0, + ^uint64(0), uint64(1) << 33, 0, + ^uint64(0), 0, uint64(1) << 1, + } + wantData := data + wantData[0] &^= uint64(1) << 63 + wantData[1] = 1 + wantData[3] &^= uint64(1) << 63 + wantData[4] = 1 + wantData[6] &^= uint64(1) << 63 + wantData[7] = 1 + wantData[8] = 0 + var got [12]byte + bitTestMemorySemantics(&got, &data) + wantCarry := [12]byte{1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0} + if got != wantCarry { + t.Fatalf("bitTestMemorySemantics() carry = %#v, want %#v", got, wantCarry) + } + if data != wantData { + t.Fatalf("bitTestMemorySemantics() data = %#x, want %#x", data, wantData) + } +} + +func referencePackedWordMultiplyAdd(a, b []int16) []int32 { + result := make([]int32, len(a)/2) + for i := range result { + sum := int64(a[2*i])*int64(b[2*i]) + int64(a[2*i+1])*int64(b[2*i+1]) + result[i] = int32(uint32(sum)) + } + return result +} + +func TestPackedWordMultiplyAddSemantics(t *testing.T) { + a := [16]int16{-32768, -32768, -30000, -1, 0, 1, 12345, 32767, 7, -11, 1000, -2000, 22222, -12345, 32767, 32767} + b := [16]int16{-32768, -32768, -23456, 32767, -1, 32767, -2345, 32767, -9, 13, -3000, 4000, -11111, 23456, 32767, 32767} + var got, want [18]int32 + first2 := referencePackedWordMultiplyAdd(a[:4], b[:4]) + first4 := referencePackedWordMultiplyAdd(a[:8], b[:8]) + first8 := referencePackedWordMultiplyAdd(a[:], b[:]) + copy(want[0:2], first2) + copy(want[2:6], first4) + copy(want[6:10], first4) + copy(want[10:18], first8) + packedWordMultiplyAddSemantics(&got, &a, &b) + if got != want { + t.Fatalf("packedWordMultiplyAddSemantics() = %v, want %v", got, want) + } +} + +func referencePackedUnsignedSignedByteMultiplyAdd(signed []int8, unsigned []uint8) []int16 { + result := make([]int16, len(signed)/2) + for i := range result { + sum := int32(signed[2*i])*int32(unsigned[2*i]) + int32(signed[2*i+1])*int32(unsigned[2*i+1]) + if sum > 32767 { + sum = 32767 + } else if sum < -32768 { + sum = -32768 + } + result[i] = int16(sum) + } + return result +} + +func TestPackedUnsignedSignedByteMultiplyAddSemantics(t *testing.T) { + signed := [32]int8{ + 127, 127, -128, -128, 100, -100, 1, -1, + 64, -64, 11, 12, -13, 14, 15, -16, + 31, -32, 33, -34, 35, -36, 37, -38, + 39, -40, 41, -42, 43, -44, 45, -46, + } + unsigned := [32]uint8{ + 255, 255, 255, 255, 200, 3, 255, 128, + 250, 249, 17, 19, 23, 29, 31, 37, + 41, 43, 47, 53, 59, 61, 67, 71, + 73, 79, 83, 89, 97, 101, 103, 107, + } + var got, want [32]int16 + first8 := referencePackedUnsignedSignedByteMultiplyAdd(signed[:16], unsigned[:16]) + first16 := referencePackedUnsignedSignedByteMultiplyAdd(signed[:], unsigned[:]) + copy(want[0:8], first8) + copy(want[8:16], first8) + copy(want[16:32], first16) + packedUnsignedSignedByteMultiplyAddSemantics(&got, &signed, &unsigned) + if got != want { + t.Fatalf("packedUnsignedSignedByteMultiplyAddSemantics() = %v, want %v", got, want) + } +} + +func TestInLaneFloatingPermuteSemantics(t *testing.T) { + dataWords := [8]uint32{0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107} + controlWords := [8]uint32{3, 2, 1, 0, 4, 5, 6, 7} + var data, control [32]byte + for i := range dataWords { + binary.LittleEndian.PutUint32(data[4*i:], dataWords[i]) + binary.LittleEndian.PutUint32(control[4*i:], controlWords[i]) + } + var got, want [144]byte + write32 := func(offset int, value uint32) { + binary.LittleEndian.PutUint32(want[offset:], value) + } + for lane := 0; lane < 4; lane++ { + write32(4*lane, dataWords[3-lane]) + } + for lane := 0; lane < 8; lane++ { + write32(16+4*lane, dataWords[lane/4*4+3-lane%4]) + write32(48+4*lane, dataWords[lane/4*4+int(controlWords[lane]&3)]) + } + dataQWords := [4]uint64{} + controlQWords := [4]uint64{} + for lane := 0; lane < 4; lane++ { + dataQWords[lane] = binary.LittleEndian.Uint64(data[8*lane:]) + controlQWords[lane] = binary.LittleEndian.Uint64(control[8*lane:]) + } + for lane := 0; lane < 4; lane++ { + immediateSource := lane/2*2 + int(uint8(0x05)>>uint(lane)&1) + variableSource := lane/2*2 + int(controlQWords[lane]>>1&1) + binary.LittleEndian.PutUint64(want[80+8*lane:], dataQWords[immediateSource]) + binary.LittleEndian.PutUint64(want[112+8*lane:], dataQWords[variableSource]) + } + inLaneFloatingPermuteSemantics(&got, &data, &control) + if got != want { + t.Fatalf("inLaneFloatingPermuteSemantics() = %x, want %x", got, want) + } +} + +func TestPackedWordMultiplySemantics(t *testing.T) { + a := [8]int16{-32768, -32768, -30000, -1, 0, 1, 12345, 32767} + b := [8]int16{-32768, 32767, -23456, 32767, -1, 32767, -2345, 32767} + var got, want [64]uint16 + packedWordMultiplySemantics(&got, &a, &b) + for i := range a { + product := int32(a[i]) * int32(b[i]) + unsignedProduct := uint32(uint16(a[i])) * uint32(uint16(b[i])) + rounded := (product + 0x4000) >> 15 + values := [4]uint16{ + uint16(product), + uint16(product >> 16), + uint16(unsignedProduct >> 16), + uint16(rounded), + } + for mode, value := range values { + want[mode*8+i] = value + want[(mode+4)*8+i] = value + } + } + if got != want { + t.Fatalf("packedWordMultiplySemantics() = %#x, want %#x", got, want) + } +} + +func TestPackedFloatShuffleSemantics(t *testing.T) { + var a, b [32]byte + for i := 0; i < 8; i++ { + binary.LittleEndian.PutUint32(a[4*i:], uint32(0xa0+i)) + binary.LittleEndian.PutUint32(b[4*i:], uint32(0xb0+i)) + } + var got, want [96]byte + packedFloatShuffleSemantics(&got, &a, &b) + put32 := func(offset, value int) { + binary.LittleEndian.PutUint32(want[offset:], uint32(value)) + } + for i, value := range []int{0xb3, 0xb2, 0xa1, 0xa0} { + put32(4*i, value) + } + for i, value := range []uint64{0x000000b1000000b0, 0x000000a3000000a2} { + binary.LittleEndian.PutUint64(want[16+8*i:], value) + } + for group := 0; group < 2; group++ { + base := group * 4 + for position, value := range []int{0xb3, 0xb2, 0xa1, 0xa0} { + put32(32+4*(base+position), value+base) + } + } + for i, value := range []uint64{0x000000b1000000b0, 0x000000a3000000a2, 0x000000b5000000b4, 0x000000a7000000a6} { + binary.LittleEndian.PutUint64(want[64+8*i:], value) + } + if got != want { + t.Fatalf("packedFloatShuffleSemantics() = %#x, want %#x", got, want) + } +} + +func TestImmediatePackedBlendSemantics(t *testing.T) { + var a, b [32]byte + for i := range a { + a[i] = byte(0x20 + i) + b[i] = byte(0xc0 + i) + } + var got, want [240]byte + immediatePackedBlendSemantics(&got, &a, &b) + blocks := []struct { + offset, width, laneBytes int + }{ + {0, 16, 2}, // PBLENDW + {16, 16, 4}, // BLENDPS + {32, 16, 8}, // BLENDPD + {48, 16, 2}, // VPBLENDW X + {64, 32, 2}, // VPBLENDW Y + {96, 16, 4}, // VPBLENDD X + {112, 32, 4}, // VPBLENDD Y + {144, 16, 4}, // VBLENDPS X + {160, 32, 4}, // VBLENDPS Y + {192, 16, 8}, // VBLENDPD X + {208, 32, 8}, // VBLENDPD Y + } + const mask = 0xa5 + for _, block := range blocks { + for i := 0; i < block.width; i++ { + source := b[i] + if mask&(1< 127 { + signed = 127 + } + want[i] = byte(int8(signed)) + unsigned := int(a[i]) - int(b[i]) + if unsigned < 0 { + unsigned = 0 + } + want[32+i] = byte(unsigned) + } + for i := 0; i < 8; i++ { + av, bv := binary.LittleEndian.Uint16(a[2*i:]), binary.LittleEndian.Uint16(b[2*i:]) + signed := int(int16(av)) - int(int16(bv)) + if signed < -32768 { + signed = -32768 + } else if signed > 32767 { + signed = 32767 + } + binary.LittleEndian.PutUint16(want[16+2*i:], uint16(int16(signed))) + unsigned := int(av) - int(bv) + if unsigned < 0 { + unsigned = 0 + } + binary.LittleEndian.PutUint16(want[48+2*i:], uint16(unsigned)) + } + for i := 0; i < 2; i++ { + av, bv := binary.LittleEndian.Uint64(a[8*i:]), binary.LittleEndian.Uint64(b[8*i:]) + binary.LittleEndian.PutUint64(want[64+8*i:], av-bv) + } + if got != want { + t.Fatalf("packedSubtractSemantics() = %#v, want %#v", got, want) + } +} + +func TestParityBranchSemantics(t *testing.T) { + for _, tc := range []struct { + value byte + want uint64 + }{ + {value: 0x00, want: 1}, + {value: 0x03, want: 1}, + {value: 0x01, want: 2}, + {value: 0x07, want: 2}, + } { + if got := parityBranches(tc.value); got != tc.want { + t.Fatalf("parityBranches(%#x) = %d, want %d", tc.value, got, tc.want) + } + } + if got := unorderedBranch(1.25); got != 0 { + t.Fatalf("unorderedBranch(finite) = %d, want 0", got) + } + if got := unorderedBranch(math.NaN()); got != 1 { + t.Fatalf("unorderedBranch(NaN) = %d, want 1", got) + } +} + +func TestPackedFloatToDwordRoundingModes(t *testing.T) { + src := [4]float32{1.5, -1.5, 2.75, -2.75} + var got [20]int32 + packedFloatToDwordModes(&got, &src) + want := [20]int32{ + 2, -2, 3, -3, + 1, -2, 2, -3, + 2, -1, 3, -2, + 1, -1, 2, -2, + 1, -1, 2, -2, + } + if got != want { + t.Fatalf("packedFloatToDwordModes() = %v, want %v", got, want) + } +} + +func TestPackedSingleToDoubleSemantics(t *testing.T) { + src := [4]float32{1.5, -2.25, 3.125, -4.5} + var got [4]float64 + packedSingleToDouble(&got, &src) + want := [4]float64{1.5, -2.25, 3.125, -4.5} + if got != want { + t.Fatalf("packedSingleToDouble() = %v, want %v", got, want) + } +} + +func TestConditionalMoveConditionCodes(t *testing.T) { + var src [16]uint64 + for i := range src { + src[i] = uint64(101 + i) + } + var got [16]uint64 + conditionalMoveCodes(&got, &src) + want := [16]uint64{ + src[0], ^uint64(0), ^uint64(0), src[3], + src[4], src[5], ^uint64(0), ^uint64(0), + ^uint64(0), src[9], src[10], ^uint64(0), + src[12], ^uint64(0), ^uint64(0), src[15], + } + if got != want { + t.Fatalf("conditionalMoveCodes() = %#x, want %#x", got, want) + } +} + +func TestFMA3Semantics(t *testing.T) { + a64 := [2]float64{2, -3} + b64 := [2]float64{5, 7} + c64 := [2]float64{11, -13} + a32 := [4]float32{2, -3, 4, -5} + b32 := [4]float32{5, 7, -11, -13} + c32 := [4]float32{17, -19, 23, -29} + var got [288]byte + fma3Semantics(&got, &a64, &b64, &c64, &a32, &b32, &c32) + + read64 := func(block, lane int) float64 { + return math.Float64frombits(binary.LittleEndian.Uint64(got[16*block+8*lane:])) + } + packed64 := [8][2]float64{} + for lane := 0; lane < 2; lane++ { + a, b, c := a64[lane], b64[lane], c64[lane] + packed64[0][lane] = c*a + b + packed64[1][lane] = b*c + a + packed64[2][lane] = b*a + c + packed64[3][lane] = c*a - b + packed64[4][lane] = -(b * c) + a + packed64[5][lane] = -(b * a) - c + if lane%2 == 0 { + packed64[6][lane] = c*a - b + packed64[7][lane] = b*a + c + } else { + packed64[6][lane] = c*a + b + packed64[7][lane] = b*a - c + } + } + for block, want := range packed64 { + for lane := range want { + if value := read64(block, lane); value != want[lane] { + t.Fatalf("packed f64 block %d lane %d = %v, want %v", block, lane, value, want[lane]) + } + } + } + + read32 := func(block, lane int) float32 { + return math.Float32frombits(binary.LittleEndian.Uint32(got[16*block+4*lane:])) + } + packed32 := [6][4]float32{} + for lane := 0; lane < 4; lane++ { + a, b, c := a32[lane], b32[lane], c32[lane] + packed32[0][lane] = c*a + b + packed32[1][lane] = b*c - a + packed32[2][lane] = -(b * a) + c + packed32[3][lane] = -(c * a) - b + if lane%2 == 0 { + packed32[4][lane] = b*c - a + packed32[5][lane] = b*a + c + } else { + packed32[4][lane] = b*c + a + packed32[5][lane] = b*a - c + } + } + for block, want := range packed32 { + for lane := range want { + if value := read32(8+block, lane); value != want[lane] { + t.Fatalf("packed f32 block %d lane %d = %v, want %v", block, lane, value, want[lane]) + } + } + } + + wantScalar64 := [2][2]float64{ + {c64[0]*a64[0] + b64[0], c64[1]}, + {b64[0]*c64[0] - a64[0], c64[1]}, + } + for block, want := range wantScalar64 { + for lane := range want { + if value := read64(14+block, lane); value != want[lane] { + t.Fatalf("scalar f64 block %d lane %d = %v, want %v", block, lane, value, want[lane]) + } + } + } + wantScalar32 := [2][4]float32{ + {-(b32[0] * a32[0]) + c32[0], c32[1], c32[2], c32[3]}, + {-(c32[0] * a32[0]) - b32[0], c32[1], c32[2], c32[3]}, + } + for block, want := range wantScalar32 { + for lane := range want { + if value := read32(16+block, lane); value != want[lane] { + t.Fatalf("scalar f32 block %d lane %d = %v, want %v", block, lane, value, want[lane]) + } + } + } +} + +func TestBinaryFloatingSemantics(t *testing.T) { + a64 := [2]float64{2, -3} + b64 := [2]float64{20, 30} + a32 := [4]float32{2, -3, 4, -5} + b32 := [4]float32{20, 30, -40, -50} + var got [384]byte + binaryFloatingSemantics(&got, &a64, &b64, &a32, &b32) + + operation64 := func(operation, lane int) float64 { + a, b := a64[lane], b64[lane] + switch operation { + case 0: + return b + a + case 1: + return b - a + case 2: + return b * a + case 3: + return b / a + case 4: + if b > a { + return b + } + return a + default: + if b < a { + return b + } + return a + } + } + operation32 := func(operation, lane int) float32 { + a, b := a32[lane], b32[lane] + switch operation { + case 0: + return b + a + case 1: + return b - a + case 2: + return b * a + case 3: + return b / a + case 4: + if b > a { + return b + } + return a + default: + if b < a { + return b + } + return a + } + } + read64 := func(block, lane int) float64 { + return math.Float64frombits(binary.LittleEndian.Uint64(got[16*block+8*lane:])) + } + read32 := func(block, lane int) float32 { + return math.Float32frombits(binary.LittleEndian.Uint32(got[16*block+4*lane:])) + } + for operation := 0; operation < 6; operation++ { + for lane := 0; lane < 2; lane++ { + if value, want := read64(operation, lane), operation64(operation, lane); value != want { + t.Fatalf("packed f64 operation %d lane %d = %v, want %v", operation, lane, value, want) + } + } + for lane := 0; lane < 4; lane++ { + if value, want := read32(6+operation, lane), operation32(operation, lane); value != want { + t.Fatalf("packed f32 operation %d lane %d = %v, want %v", operation, lane, value, want) + } + } + for lane := 0; lane < 2; lane++ { + want := b64[lane] + if lane == 0 { + want = operation64(operation, 0) + } + if value := read64(12+operation, lane); value != want { + t.Fatalf("scalar f64 operation %d lane %d = %v, want %v", operation, lane, value, want) + } + } + for lane := 0; lane < 4; lane++ { + want := b32[lane] + if lane == 0 { + want = operation32(operation, 0) + } + if value := read32(18+operation, lane); value != want { + t.Fatalf("scalar f32 operation %d lane %d = %v, want %v", operation, lane, value, want) + } + } + } +} + +func TestHorizontalFloatingSemantics(t *testing.T) { + a32 := [8]float32{1, 2, 3, 4, 5, 6, 7, 8} + b32 := [8]float32{10, 20, 30, 40, 50, 60, 70, 80} + a64 := [4]float64{1, 2, 3, 4} + b64 := [4]float64{10, 20, 30, 40} + var got [192]byte + horizontalFloatingSemantics(&got, &a32, &b32, &a64, &b64) + + read32 := func(offset int) float32 { + return math.Float32frombits(binary.LittleEndian.Uint32(got[offset:])) + } + read64 := func(offset int) float64 { + return math.Float64frombits(binary.LittleEndian.Uint64(got[offset:])) + } + packed32 := [2][8]float32{ + {30, 70, 3, 7, 110, 150, 11, 15}, + {-10, -10, -1, -1, -10, -10, -1, -1}, + } + for block, want := range packed32 { + for lane := range want { + if value := read32(32*block + 4*lane); value != want[lane] { + t.Fatalf("vector f32 block %d lane %d = %v, want %v", block, lane, value, want[lane]) + } + } + } + packed64 := [2][4]float64{{30, 3, 70, 7}, {-10, -1, -10, -1}} + for block, want := range packed64 { + for lane := range want { + if value := read64(64 + 32*block + 8*lane); value != want[lane] { + t.Fatalf("vector f64 block %d lane %d = %v, want %v", block, lane, value, want[lane]) + } + } + } + legacy32 := [2][4]float32{{30, 70, 3, 7}, {-10, -10, -1, -1}} + for block, want := range legacy32 { + for lane := range want { + if value := read32(128 + 16*block + 4*lane); value != want[lane] { + t.Fatalf("legacy f32 block %d lane %d = %v, want %v", block, lane, value, want[lane]) + } + } + } + legacy64 := [2][2]float64{{30, 3}, {-10, -1}} + for block, want := range legacy64 { + for lane := range want { + if value := read64(160 + 16*block + 8*lane); value != want[lane] { + t.Fatalf("legacy f64 block %d lane %d = %v, want %v", block, lane, value, want[lane]) + } + } + } +} + +func TestExpandedEcosystemVectorSemantics(t *testing.T) { + a := [16]byte{0x00, 0x7f, 0x80, 0xff, 0x34, 0x12, 0xfe, 0xff, 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x00, 0x80} + b := [16]byte{0xff, 0x80, 0x7f, 0x00, 0x78, 0x56, 0x02, 0x00, 0xef, 0xcd, 0xab, 0x90, 0xff, 0xff, 0xff, 0x7f} + var got, want [816]byte + expandedEcosystemVectors(&got, &a, &b) + + for i := range a { + minU, maxU := a[i], a[i] + if b[i] < minU { + minU = b[i] + } + if b[i] > maxU { + maxU = b[i] + } + minS, maxS := int8(a[i]), int8(a[i]) + if int8(b[i]) < minS { + minS = int8(b[i]) + } + if int8(b[i]) > maxS { + maxS = int8(b[i]) + } + want[i], want[16+i] = minU, byte(minS) + want[96+i], want[112+i] = maxU, byte(maxS) + } + for i := 0; i < 8; i++ { + av := binary.LittleEndian.Uint16(a[2*i:]) + bv := binary.LittleEndian.Uint16(b[2*i:]) + minU, maxU := av, av + if bv < minU { + minU = bv + } + if bv > maxU { + maxU = bv + } + minS, maxS := int16(av), int16(av) + if int16(bv) < minS { + minS = int16(bv) + } + if int16(bv) > maxS { + maxS = int16(bv) + } + binary.LittleEndian.PutUint16(want[32+2*i:], minU) + binary.LittleEndian.PutUint16(want[48+2*i:], uint16(minS)) + binary.LittleEndian.PutUint16(want[128+2*i:], maxU) + binary.LittleEndian.PutUint16(want[144+2*i:], uint16(maxS)) + } + for i := 0; i < 4; i++ { + av := binary.LittleEndian.Uint32(a[4*i:]) + bv := binary.LittleEndian.Uint32(b[4*i:]) + minU, maxU := av, av + if bv < minU { + minU = bv + } + if bv > maxU { + maxU = bv + } + minS, maxS := int32(av), int32(av) + if int32(bv) < minS { + minS = int32(bv) + } + if int32(bv) > maxS { + maxS = int32(bv) + } + binary.LittleEndian.PutUint32(want[64+4*i:], minU) + binary.LittleEndian.PutUint32(want[80+4*i:], uint32(minS)) + binary.LittleEndian.PutUint32(want[160+4*i:], maxU) + binary.LittleEndian.PutUint32(want[176+4*i:], uint32(maxS)) + } + for i := 0; i < 2; i++ { + binary.LittleEndian.PutUint64(want[192+8*i:], binary.LittleEndian.Uint64(a[8*i:])<<13) + } + binary.LittleEndian.PutUint64(want[224:], 0x0123456789abcdef) + binary.LittleEndian.PutUint64(want[232:], 0x0000000089abcdef) + binary.LittleEndian.PutUint32(want[240:], 0x89abcdef) + copy(want[256:264], a[:8]) + for i := range a { + want[272+i] = byte((uint16(a[i]) + uint16(b[i]) + 1) >> 1) + } + for i := 0; i < 8; i++ { + av := binary.LittleEndian.Uint16(a[2*i:]) + bv := binary.LittleEndian.Uint16(b[2*i:]) + binary.LittleEndian.PutUint16(want[288+2*i:], uint16((uint32(av)+uint32(bv)+1)>>1)) + } + for i := range a { + if int8(a[i]) > int8(b[i]) { + want[304+i] = 0xff + } + } + for i := 0; i < 8; i++ { + if int16(binary.LittleEndian.Uint16(a[2*i:])) > int16(binary.LittleEndian.Uint16(b[2*i:])) { + binary.LittleEndian.PutUint16(want[320+2*i:], 0xffff) + } + } + for i := 0; i < 4; i++ { + if int32(binary.LittleEndian.Uint32(a[4*i:])) > int32(binary.LittleEndian.Uint32(b[4*i:])) { + binary.LittleEndian.PutUint32(want[336+4*i:], 0xffffffff) + } + } + for i := 0; i < 2; i++ { + if int64(binary.LittleEndian.Uint64(a[8*i:])) > int64(binary.LittleEndian.Uint64(b[8*i:])) { + binary.LittleEndian.PutUint64(want[352+8*i:], ^uint64(0)) + } + } + for i := 0; i < 8; i++ { + av := int16(binary.LittleEndian.Uint16(a[2*i:])) + binary.LittleEndian.PutUint16(want[368+2*i:], uint16(av>>3)) + binary.LittleEndian.PutUint16(want[384+2*i:], uint16(av>>15)) + } + for lane := 0; lane < 2; lane++ { + copy(want[400+lane*8:], a[lane*4:lane*4+4]) + copy(want[404+lane*8:], b[lane*4:lane*4+4]) + copy(want[416+lane*8:], a[8+lane*4:12+lane*4]) + copy(want[420+lane*8:], b[8+lane*4:12+lane*4]) + } + copy(want[432:440], a[0:8]) + copy(want[440:448], b[0:8]) + copy(want[448:456], a[8:16]) + copy(want[456:464], b[8:16]) + conversions := []struct{ inputBits, outputBits int }{{8, 16}, {8, 32}, {8, 64}, {16, 32}, {16, 64}, {32, 64}} + for index, conversion := range conversions { + lanes := 128 / conversion.outputBits + for lane := 0; lane < lanes; lane++ { + inputOffset := lane * conversion.inputBits / 8 + outputOffset := 464 + index*16 + lane*conversion.outputBits/8 + switch conversion.outputBits { + case 16: + binary.LittleEndian.PutUint16(want[outputOffset:], uint16(a[inputOffset])) + case 32: + value := uint32(a[inputOffset]) + if conversion.inputBits == 16 { + value = uint32(binary.LittleEndian.Uint16(a[inputOffset:])) + } + binary.LittleEndian.PutUint32(want[outputOffset:], value) + case 64: + value := uint64(a[inputOffset]) + if conversion.inputBits == 16 { + value = uint64(binary.LittleEndian.Uint16(a[inputOffset:])) + } else if conversion.inputBits == 32 { + value = uint64(binary.LittleEndian.Uint32(a[inputOffset:])) + } + binary.LittleEndian.PutUint64(want[outputOffset:], value) + } + } + } + clampWord := func(value int32) int16 { + if value < -32768 { + return -32768 + } + if value > 32767 { + return 32767 + } + return int16(value) + } + for pair := 0; pair < 2; pair++ { + a0 := binary.LittleEndian.Uint32(a[8*pair:]) + a1 := binary.LittleEndian.Uint32(a[8*pair+4:]) + b0 := binary.LittleEndian.Uint32(b[8*pair:]) + b1 := binary.LittleEndian.Uint32(b[8*pair+4:]) + binary.LittleEndian.PutUint32(want[560+4*pair:], a0+a1) + binary.LittleEndian.PutUint32(want[568+4*pair:], b0+b1) + binary.LittleEndian.PutUint32(want[608+4*pair:], a0-a1) + binary.LittleEndian.PutUint32(want[616+4*pair:], b0-b1) + } + for pair := 0; pair < 4; pair++ { + a0 := binary.LittleEndian.Uint16(a[4*pair:]) + a1 := binary.LittleEndian.Uint16(a[4*pair+2:]) + b0 := binary.LittleEndian.Uint16(b[4*pair:]) + b1 := binary.LittleEndian.Uint16(b[4*pair+2:]) + binary.LittleEndian.PutUint16(want[576+2*pair:], uint16(clampWord(int32(int16(a0))+int32(int16(a1))))) + binary.LittleEndian.PutUint16(want[584+2*pair:], uint16(clampWord(int32(int16(b0))+int32(int16(b1))))) + binary.LittleEndian.PutUint16(want[592+2*pair:], a0+a1) + binary.LittleEndian.PutUint16(want[600+2*pair:], b0+b1) + binary.LittleEndian.PutUint16(want[624+2*pair:], uint16(clampWord(int32(int16(a0))-int32(int16(a1))))) + binary.LittleEndian.PutUint16(want[632+2*pair:], uint16(clampWord(int32(int16(b0))-int32(int16(b1))))) + binary.LittleEndian.PutUint16(want[640+2*pair:], a0-a1) + binary.LittleEndian.PutUint16(want[648+2*pair:], b0-b1) + } + minimum, minimumIndex := uint16(0xffff), uint16(0) + for lane := 0; lane < 8; lane++ { + value := binary.LittleEndian.Uint16(a[2*lane:]) + if value < minimum { + minimum, minimumIndex = value, uint16(lane) + } + } + binary.LittleEndian.PutUint16(want[656:], minimum) + binary.LittleEndian.PutUint16(want[658:], minimumIndex) + for block := 0; block < 2; block++ { + for lane := range a { + want[672+16*block+lane] = b[lane] + if int8(b[lane]) < 0 { + want[672+16*block+lane] = a[lane] + } + } + } + for lane := 0; lane < 8; lane++ { + value := binary.LittleEndian.Uint16(a[2*lane:]) + binary.LittleEndian.PutUint16(want[704+2*lane:], value<<3) + binary.LittleEndian.PutUint16(want[752+2*lane:], value>>3) + } + for lane := 0; lane < 4; lane++ { + value := binary.LittleEndian.Uint32(a[4*lane:]) + binary.LittleEndian.PutUint32(want[720+4*lane:], value<<3) + binary.LittleEndian.PutUint32(want[768+4*lane:], value>>3) + } + for lane := 0; lane < 2; lane++ { + value := binary.LittleEndian.Uint64(a[8*lane:]) + binary.LittleEndian.PutUint64(want[736+8*lane:], value<<3) + binary.LittleEndian.PutUint64(want[784+8*lane:], value>>3) + } + binary.LittleEndian.PutUint64(want[800:], 3) + if got != want { + t.Fatalf("expandedEcosystemVectors() = %#v, want %#v", got, want) + } +} + func shld32(src, dst, count uint32) uint32 { count &= 31 if count == 0 { diff --git a/testdata/conformance/arm64/conformance.go b/testdata/conformance/arm64/conformance.go index 982ca64c..ca1a7aa8 100644 --- a/testdata/conformance/arm64/conformance.go +++ b/testdata/conformance/arm64/conformance.go @@ -3,3 +3,19 @@ package arm64conformance func families(out *[76]uint64, data *[8]uint64) + +func scalarFloatSquareRoots(out *[16]byte) + +func fusedMultiplyAddSemantics(out *[48]byte) + +func pairedAtomicSemantics(out *[23]uint64, data *[9]uint64) + +func vectorPermuteSemantics(out *[96]byte, n *[16]byte, m *[16]byte) + +func vectorWideningShiftSemantics(out *[128]byte, source *[16]byte) + +func scalarExtendSemantics(out *[10]uint64, value uint64) + +func vectorCountBitsSemantics(out *[32]byte, source *[16]byte) + +func unsignedWideningAddSemantics(out *[96]byte, narrow *[16]byte, addend *[16]byte) diff --git a/testdata/conformance/arm64/conformance_arm64.s b/testdata/conformance/arm64/conformance_arm64.s index 0060bff2..415772ee 100644 --- a/testdata/conformance/arm64/conformance_arm64.s +++ b/testdata/conformance/arm64/conformance_arm64.s @@ -185,3 +185,240 @@ TEXT ·families(SB), NOSPLIT, $0-16 FMOVD R2, F4 FMOVQ F4, 592(R0) RET + +// scalarFloatSquareRoots covers scalar S/D constants, F-register copies, +// F<->general-register bit moves, memory stores, and square roots. +TEXT ·scalarFloatSquareRoots(SB), NOSPLIT, $0-8 + MOVD out+0(FP), R0 + FMOVS $(4.0), F0 + FSQRTS F0, F1 + FMOVS F1, 0(R0) + FMOVS F1, R1 + FMOVS R1, F2 + FMOVS F2, 4(R0) + FMOVD $(16.0), F3 + FSQRTD F3, F4 + FMOVD F4, 8(R0) + RET + +// fusedMultiplyAddSemantics distinguishes all four sign variants and both +// scalar widths. In Go assembler order the operands are Fm, Fa, Fn, Fd. +TEXT ·fusedMultiplyAddSemantics(SB), NOSPLIT, $0-8 + MOVD out+0(FP), R0 + FMOVS $(2.0), F0 + FMOVS $(5.0), F1 + FMOVS $(3.0), F2 + FMADDS F0, F1, F2, F3 + FMSUBS F0, F1, F2, F4 + FNMADDS F0, F1, F2, F5 + FNMSUBS F0, F1, F2, F6 + FMOVS F3, 0(R0) + FMOVS F4, 4(R0) + FMOVS F5, 8(R0) + FMOVS F6, 12(R0) + + FMOVD $(2.0), F10 + FMOVD $(5.0), F11 + FMOVD $(3.0), F12 + FMADDD F10, F11, F12, F13 + FMSUBD F10, F11, F12, F14 + FNMADDD F10, F11, F12, F15 + FNMSUBD F10, F11, F12, F16 + FMOVD F13, 16(R0) + FMOVD F14, 24(R0) + FMOVD F15, 32(R0) + FMOVD F16, 40(R0) + RET + +// vectorPermuteSemantics fixes the Plan 9 Vm,Vn,Vd operand order and all six +// ZIP/UZP/TRN lane-selection variants with distinguishable byte inputs. +TEXT ·vectorPermuteSemantics(SB), NOSPLIT, $0-24 + MOVD out+0(FP), R0 + MOVD n+8(FP), R1 + MOVD m+16(FP), R2 + FMOVQ (R1), F0 + FMOVQ (R2), F1 + VZIP1 V1.B16, V0.B16, V2.B16 + FMOVQ F2, 0(R0) + VZIP2 V1.B16, V0.B16, V2.B16 + FMOVQ F2, 16(R0) + VUZP1 V1.B16, V0.B16, V2.B16 + FMOVQ F2, 32(R0) + VUZP2 V1.B16, V0.B16, V2.B16 + FMOVQ F2, 48(R0) + VTRN1 V1.B16, V0.B16, V2.B16 + FMOVQ F2, 64(R0) + VTRN2 V1.B16, V0.B16, V2.B16 + FMOVQ F2, 80(R0) + RET + +// vectorWideningShiftSemantics distinguishes signed/unsigned extension, +// low/high source halves, and the immediate-shift forms of the family. +TEXT ·vectorWideningShiftSemantics(SB), NOSPLIT, $0-16 + MOVD out+0(FP), R0 + MOVD source+8(FP), R1 + FMOVQ (R1), F0 + VUXTL V0.B8, V1.H8 + FMOVQ F1, 0(R0) + VUXTL2 V0.B16, V1.H8 + FMOVQ F1, 16(R0) + VSXTL V0.B8, V1.H8 + FMOVQ F1, 32(R0) + VSXTL2 V0.B16, V1.H8 + FMOVQ F1, 48(R0) + VUSHLL $7, V0.B8, V1.H8 + FMOVQ F1, 64(R0) + VUSHLL2 $1, V0.B16, V1.H8 + FMOVQ F1, 80(R0) + VSSHLL $3, V0.B8, V1.H8 + FMOVQ F1, 96(R0) + VSSHLL2 $2, V0.B16, V1.H8 + FMOVQ F1, 112(R0) + RET + +// scalarExtendSemantics distinguishes 64-bit and W-register destinations for +// every signed and unsigned scalar extend mnemonic in Go's shared optab row. +TEXT ·scalarExtendSemantics(SB), NOSPLIT, $0-16 + MOVD out+0(FP), R0 + MOVD value+8(FP), R1 + SXTB R1, R2 + MOVD R2, 0(R0) + SXTBW R1, R2 + MOVD R2, 8(R0) + SXTH R1, R2 + MOVD R2, 16(R0) + SXTHW R1, R2 + MOVD R2, 24(R0) + SXTW R1, R2 + MOVD R2, 32(R0) + UXTB R1, R2 + MOVD R2, 40(R0) + UXTBW R1, R2 + MOVD R2, 48(R0) + UXTH R1, R2 + MOVD R2, 56(R0) + UXTHW R1, R2 + MOVD R2, 64(R0) + UXTW R1, R2 + MOVD R2, 72(R0) + RET + +TEXT ·vectorCountBitsSemantics(SB), NOSPLIT, $0-16 + MOVD out+0(FP), R0 + MOVD source+8(FP), R1 + FMOVQ (R1), F0 + VCNT V0.B8, V1.B8 + FMOVQ F1, 0(R0) + VCNT V0.B16, V1.B16 + FMOVQ F1, 16(R0) + RET + +TEXT ·unsignedWideningAddSemantics(SB), NOSPLIT, $0-24 + MOVD out+0(FP), R0 + MOVD narrow+8(FP), R1 + MOVD addend+16(FP), R2 + FMOVQ (R1), F0 + FMOVQ (R2), F1 + VUADDW V0.B8, V1.H8, V2.H8 + FMOVQ F2, 0(R0) + VUADDW V0.H4, V1.S4, V2.S4 + FMOVQ F2, 16(R0) + VUADDW V0.S2, V1.D2, V2.D2 + FMOVQ F2, 32(R0) + VUADDW2 V0.B16, V1.H8, V2.H8 + FMOVQ F2, 48(R0) + VUADDW2 V0.H8, V1.S4, V2.S4 + FMOVQ F2, 64(R0) + VUADDW2 V0.S4, V1.D2, V2.D2 + FMOVQ F2, 80(R0) + RET + +// pairedAtomicSemantics exercises success and failure paths for both CASP +// widths and for the load-exclusive/store-exclusive pair family. +TEXT ·pairedAtomicSemantics(SB), NOSPLIT, $0-16 + MOVD out+0(FP), R0 + MOVD data+8(FP), R1 + + // CASPD success: compare registers receive the old memory pair and the + // destination pair is installed. + MOVD $0x11, R2 + MOVD $0x22, R3 + MOVD $0xaa, R4 + MOVD $0xbb, R5 + MOVD R1, R6 + CASPD (R2, R3), (R6), (R4, R5) + MOVD R2, 0(R0) + MOVD R3, 8(R0) + MOVD 0(R6), R8 + MOVD R8, 16(R0) + MOVD 8(R6), R8 + MOVD R8, 24(R0) + + // CASPD failure: memory is unchanged and the compare pair receives its + // actual contents. + MOVD $0x99, R2 + MOVD $0x88, R3 + MOVD $0xcc, R4 + MOVD $0xdd, R5 + ADD $16, R1, R6 + CASPD (R2, R3), (R6), (R4, R5) + MOVD R2, 32(R0) + MOVD R3, 40(R0) + MOVD 0(R6), R8 + MOVD R8, 48(R0) + MOVD 8(R6), R8 + MOVD R8, 56(R0) + + // CASPW compares the low 32 bits of each register and zero-extends the + // loaded pair back into the compare registers. + MOVD $0xffffffff00000011, R2 + MOVD $0xeeeeeeee00000022, R3 + MOVD $0xdddddddd000000aa, R4 + MOVD $0xcccccccc000000bb, R5 + ADD $32, R1, R6 + CASPW (R2, R3), (R6), (R4, R5) + MOVD R2, 64(R0) + MOVD R3, 72(R0) + MOVD 0(R6), R8 + MOVD R8, 80(R0) + + MOVD $0xffffffff00000099, R2 + MOVD $0xeeeeeeee00000088, R3 + MOVD $0xdddddddd000000cc, R4 + MOVD $0xcccccccc000000dd, R5 + ADD $40, R1, R6 + CASPW (R2, R3), (R6), (R4, R5) + MOVD R2, 88(R0) + MOVD R3, 96(R0) + MOVD 0(R6), R8 + MOVD R8, 104(R0) + + // A matching LDXP/STXP reservation succeeds. + ADD $48, R1, R6 + LDXP (R6), (R2, R3) + MOVD R2, 112(R0) + MOVD R3, 120(R0) + MOVD $0xcc, R4 + MOVD $0xdd, R5 + STXP (R4, R5), (R6), R7 + MOVD R7, 128(R0) + MOVD 0(R6), R8 + MOVD R8, 136(R0) + MOVD 8(R6), R8 + MOVD R8, 144(R0) + + // An intervening store invalidates an LDAXPW reservation, so STLXPW + // reports failure and leaves the intervening value in memory. + ADD $64, R1, R6 + LDAXPW (R6), (R2, R3) + MOVD R2, 152(R0) + MOVD R3, 160(R0) + MOVD $0x000000aa00000099, R8 + MOVD R8, 0(R6) + MOVD $0xcc, R4 + MOVD $0xdd, R5 + STLXPW (R4, R5), (R6), R7 + MOVD R7, 168(R0) + MOVD 0(R6), R8 + MOVD R8, 176(R0) + RET diff --git a/testdata/conformance/arm64/conformance_test.go b/testdata/conformance/arm64/conformance_test.go index b7b3e3f2..95bec46c 100644 --- a/testdata/conformance/arm64/conformance_test.go +++ b/testdata/conformance/arm64/conformance_test.go @@ -3,8 +3,11 @@ package arm64conformance import ( + "encoding/binary" + "math" "math/bits" "testing" + "unsafe" ) func TestFamilies(t *testing.T) { @@ -19,6 +22,207 @@ func TestFamilies(t *testing.T) { } } +func TestScalarFloatSquareRoots(t *testing.T) { + var got [16]byte + scalarFloatSquareRoots(&got) + if value := math.Float32frombits(binary.LittleEndian.Uint32(got[0:4])); value != 2 { + t.Fatalf("FSQRTS/FMOVS result = %v, want 2", value) + } + if value := math.Float32frombits(binary.LittleEndian.Uint32(got[4:8])); value != 2 { + t.Fatalf("FMOVS F<->R result = %v, want 2", value) + } + if value := math.Float64frombits(binary.LittleEndian.Uint64(got[8:16])); value != 4 { + t.Fatalf("FSQRTD/FMOVD result = %v, want 4", value) + } +} + +func TestFusedMultiplyAddSemantics(t *testing.T) { + var got [48]byte + fusedMultiplyAddSemantics(&got) + want32 := [...]float32{11, -1, -11, 1} + for i, want := range want32 { + value := math.Float32frombits(binary.LittleEndian.Uint32(got[i*4 : i*4+4])) + if value != want { + t.Fatalf("fusedMultiplyAddSemantics() float32[%d] = %v, want %v", i, value, want) + } + } + want64 := [...]float64{11, -1, -11, 1} + for i, want := range want64 { + value := math.Float64frombits(binary.LittleEndian.Uint64(got[16+i*8 : 24+i*8])) + if value != want { + t.Fatalf("fusedMultiplyAddSemantics() float64[%d] = %v, want %v", i, value, want) + } + } +} + +func TestVectorPermuteSemantics(t *testing.T) { + var n, m [16]byte + for i := range n { + n[i] = byte(i) + m[i] = byte(0x80 + i) + } + var got [96]byte + vectorPermuteSemantics(&got, &n, &m) + want := vectorPermuteOracle(n, m) + if got != want { + t.Fatalf("vectorPermuteSemantics() = %#v, want %#v", got, want) + } +} + +func vectorPermuteOracle(n, m [16]byte) (out [96]byte) { + for i := 0; i < 8; i++ { + out[2*i], out[2*i+1] = n[i], m[i] + out[16+2*i], out[16+2*i+1] = n[8+i], m[8+i] + out[32+i], out[32+8+i] = n[2*i], m[2*i] + out[48+i], out[48+8+i] = n[2*i+1], m[2*i+1] + out[64+2*i], out[64+2*i+1] = n[2*i], m[2*i] + out[80+2*i], out[80+2*i+1] = n[2*i+1], m[2*i+1] + } + return out +} + +func TestVectorWideningShiftSemantics(t *testing.T) { + source := [16]byte{0, 1, 0x7f, 0x80, 0xff, 2, 0x55, 0xaa, 3, 4, 0x40, 0xc0, 0xfe, 0x81, 0x11, 0xee} + var got [128]byte + vectorWideningShiftSemantics(&got, &source) + want := vectorWideningShiftOracle(source) + if got != want { + t.Fatalf("vectorWideningShiftSemantics() = %#v, want %#v", got, want) + } +} + +func vectorWideningShiftOracle(source [16]byte) (out [128]byte) { + for lane := 0; lane < 8; lane++ { + low, high := uint16(source[lane]), uint16(source[8+lane]) + signedLow, signedHigh := uint16(int16(int8(source[lane]))), uint16(int16(int8(source[8+lane]))) + values := [...]uint16{ + low, high, signedLow, signedHigh, + low << 7, high << 1, signedLow << 3, signedHigh << 2, + } + for group, value := range values { + binary.LittleEndian.PutUint16(out[group*16+lane*2:], value) + } + } + return out +} + +func TestScalarExtendSemantics(t *testing.T) { + value := uint64(0x88776655fedcba98) + var got [10]uint64 + scalarExtendSemantics(&got, value) + want := [10]uint64{ + uint64(int64(int8(value))), + uint64(uint32(int32(int8(value)))), + uint64(int64(int16(value))), + uint64(uint32(int32(int16(value)))), + uint64(int64(int32(value))), + uint64(uint8(value)), + uint64(uint32(uint8(value))), + uint64(uint16(value)), + uint64(uint32(uint16(value))), + uint64(uint32(value)), + } + if got != want { + t.Fatalf("scalarExtendSemantics() = %#v, want %#v", got, want) + } +} + +func TestVectorCountBitsSemantics(t *testing.T) { + source := [16]byte{0, 1, 2, 3, 7, 15, 31, 63, 127, 128, 129, 0xaa, 0x55, 0xfe, 0xff, 0x81} + var got, want [32]byte + vectorCountBitsSemantics(&got, &source) + for i, value := range source { + want[16+i] = byte(bits.OnesCount8(value)) + if i < 8 { + want[i] = want[16+i] + } + } + if got != want { + t.Fatalf("vectorCountBitsSemantics() = %#v, want %#v", got, want) + } +} + +func TestUnsignedWideningAddSemantics(t *testing.T) { + narrow := [16]byte{1, 2, 3, 4, 5, 6, 7, 8, 0xf1, 0xe2, 0xd3, 0xc4, 0xb5, 0xa6, 0x97, 0x88} + addend := [16]byte{0xff, 0x00, 0xfe, 0xff, 0x78, 0x56, 0x34, 0x12, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12} + var got, want [96]byte + unsignedWideningAddSemantics(&got, &narrow, &addend) + for group, narrowBytes := range []int{1, 2, 4, 1, 2, 4} { + wideBytes := narrowBytes * 2 + lanes := 16 / wideBytes + sourceOffset := 0 + if group >= 3 { + sourceOffset = 8 + } + for lane := 0; lane < lanes; lane++ { + narrowValue := readLittleEndianWidth(narrow[sourceOffset+lane*narrowBytes:], narrowBytes) + addendValue := readLittleEndianWidth(addend[lane*wideBytes:], wideBytes) + writeLittleEndianWidth(want[group*16+lane*wideBytes:], wideBytes, addendValue+narrowValue) + } + } + if got != want { + t.Fatalf("unsignedWideningAddSemantics() = %#v, want %#v", got, want) + } +} + +func readLittleEndianWidth(data []byte, width int) uint64 { + switch width { + case 1: + return uint64(data[0]) + case 2: + return uint64(binary.LittleEndian.Uint16(data)) + case 4: + return uint64(binary.LittleEndian.Uint32(data)) + case 8: + return binary.LittleEndian.Uint64(data) + default: + panic("invalid integer width") + } +} + +func writeLittleEndianWidth(data []byte, width int, value uint64) { + switch width { + case 2: + binary.LittleEndian.PutUint16(data, uint16(value)) + case 4: + binary.LittleEndian.PutUint32(data, uint32(value)) + case 8: + binary.LittleEndian.PutUint64(data, value) + default: + panic("invalid integer width") + } +} + +func TestPairedAtomicSemantics(t *testing.T) { + var storage [11]uint64 + start := 0 + if uintptr(unsafe.Pointer(&storage[0]))%16 != 0 { + start = 1 + } + data := (*[9]uint64)(unsafe.Pointer(&storage[start])) + *data = [9]uint64{ + 0x11, 0x22, + 0x33, 0x44, + 0x0000002200000011, + 0x0000004400000033, + 0x55, 0x66, + 0x0000008800000077, + } + var got [23]uint64 + pairedAtomicSemantics(&got, data) + want := [23]uint64{ + 0x11, 0x22, 0xaa, 0xbb, + 0x33, 0x44, 0x33, 0x44, + 0x11, 0x22, 0x000000bb000000aa, + 0x33, 0x44, 0x0000004400000033, + 0x55, 0x66, 0, 0xcc, 0xdd, + 0x77, 0x88, 1, 0x000000aa00000099, + } + if got != want { + t.Fatalf("pairedAtomicSemantics() = %#v, want %#v", got, want) + } +} + func familyOracle(data [8]uint64) (out [76]uint64) { src, dst := data[0], data[1] out[0] = insert(dst, src, 8, 16, 0) diff --git a/testdata/conformance/manifest.json b/testdata/conformance/manifest.json index 9ff737b7..2237e1c5 100644 --- a/testdata/conformance/manifest.json +++ b/testdata/conformance/manifest.json @@ -103,6 +103,30 @@ "PSRAL immediate,xmm" ] }, + { + "id": "amd64-expanded-ecosystem-vector-families", + "goarch": "amd64", + "asm": "amd64/conformance_amd64.s", + "validation": "execute", + "forms": [ + "VMOVQ gpr64,xmm", + "VMOVQ xmm,gpr64", + "PSLLQ immediate,xmm", + "PSRLQ immediate,xmm", + "PMINUB memory.gpr64-base,xmm", + "PMINSB memory.gpr64-base,xmm", + "PMINUW memory.gpr64-base,xmm", + "PMINSW memory.gpr64-base,xmm", + "PMINUD memory.gpr64-base,xmm", + "PMINSD memory.gpr64-base,xmm", + "PMAXUB memory.gpr64-base,xmm", + "PMAXSB memory.gpr64-base,xmm", + "PMAXUW memory.gpr64-base,xmm", + "PMAXSW memory.gpr64-base,xmm", + "PMAXUD memory.gpr64-base,xmm", + "PMAXSD memory.gpr64-base,xmm" + ] + }, { "id": "arm64-go-assembler-scalar-families", "goarch": "arm64", diff --git a/testdata/corpus/go.mod b/testdata/corpus/go.mod index 3fa2be21..cfc36cb0 100644 --- a/testdata/corpus/go.mod +++ b/testdata/corpus/go.mod @@ -4,10 +4,12 @@ go 1.26.0 require ( github.com/RoaringBitmap/roaring v1.9.4 + github.com/aead/siphash v1.0.1 github.com/anacrolix/mmsg v1.1.1 github.com/btcsuite/fastsha256 v0.0.0-20160815193821-637e65642941 github.com/cespare/xxhash v1.1.0 github.com/cespare/xxhash/v2 v2.3.0 + github.com/chain/txvm v0.0.0-20190422181059-ff6bfbe53892 github.com/coder/websocket v1.8.15 github.com/dchest/siphash v1.2.3 github.com/dgryski/go-bits v0.0.0-20180113010104-bd8a69a71dc2 @@ -16,9 +18,11 @@ require ( github.com/klauspost/compress v1.20.0 github.com/klauspost/cpuid v1.3.1 github.com/klauspost/cpuid/v2 v2.4.0 + github.com/klauspost/crc32 v1.3.0 github.com/klauspost/reedsolomon v1.14.2 github.com/minio/highwayhash v1.0.4 github.com/modern-go/gls v0.0.0-20250215024828-78308f6bb19d + github.com/phuslu/log v1.0.134 github.com/pierrec/lz4/v4 v4.1.30 github.com/stevvooe/resumable v0.0.0-20180830230917-22b14a53ba50 github.com/tmthrgd/go-bitwise v0.0.0-20190904053232-1430ee983fca @@ -30,4 +34,9 @@ require ( golang.org/x/sys v0.48.0 ) -require github.com/modern-go/reflect2 v1.0.2 // indirect +require ( + github.com/golang/protobuf v1.3.1 // indirect + github.com/miscreant/miscreant v0.3.0 // indirect + github.com/modern-go/reflect2 v1.0.2 // indirect + golang.org/x/sync v0.0.0-20190227155943-e225da77a7e6 // indirect +) diff --git a/testdata/corpus/go.sum b/testdata/corpus/go.sum index 8e7ff470..fdce90fe 100644 --- a/testdata/corpus/go.sum +++ b/testdata/corpus/go.sum @@ -1,6 +1,8 @@ github.com/OneOfOne/xxhash v1.2.2/go.mod h1:HSdplMjZKSmBqAxg5vPj2TmRDmfkzw+cTzAElWljhcU= github.com/RoaringBitmap/roaring v1.9.4 h1:yhEIoH4YezLYT04s1nHehNO64EKFTop/wBhxv2QzDdQ= github.com/RoaringBitmap/roaring v1.9.4/go.mod h1:6AXUsoIEzDTFFQCe1RbGA6uFONMhvejWj5rqITANK90= +github.com/aead/siphash v1.0.1 h1:FwHfE/T45KPKYuuSAKyyvE+oPWcaQ+CUmFW0bPlM+kg= +github.com/aead/siphash v1.0.1/go.mod h1:Nywa3cDsYNNK3gaciGTWPwHt0wlpNV15vwmswBAUSII= github.com/anacrolix/mmsg v1.1.1 h1:4ce/3I5kM7qSF6T5A8MOmDCfac3UqYlk5Bzh5XsWebM= github.com/anacrolix/mmsg v1.1.1/go.mod h1:lPCXEN1eDDQtKktdKEzdw+roswx6wWPpeXAl/WpWVDU= github.com/bits-and-blooms/bitset v1.12.0 h1:U/q1fAF7xXRhFCrhROzIfffYnu+dlS38vCZtmFVPHmA= @@ -11,16 +13,22 @@ github.com/cespare/xxhash v1.1.0 h1:a6HrQnmkObjyL+Gs60czilIUGqrzKutQD6XZog3p+ko= github.com/cespare/xxhash v1.1.0/go.mod h1:XrSqR1VqqWfGrhpAt58auRo0WTKS1nRRg3ghfAqPWnc= github.com/cespare/xxhash/v2 v2.3.0 h1:UL815xU9SqsFlibzuggzjXhog7bL6oX9BbNZnL2UFvs= github.com/cespare/xxhash/v2 v2.3.0/go.mod h1:VGX0DQ3Q6kWi7AoAeZDth3/j3BFtOZR5XLFGgcrjCOs= +github.com/chain/txvm v0.0.0-20190422181059-ff6bfbe53892 h1:SJFPYaLE/8bSiOrLb4Fdj9nytBlDhfVZFZpWKERoct8= +github.com/chain/txvm v0.0.0-20190422181059-ff6bfbe53892/go.mod h1:Z5JK05iaidjr5mSP5SucFOSqgRqDy2t13TNP1RlweBE= github.com/coder/websocket v1.8.15 h1:6B2JPeOGlpff2Uz6vOEH1Vzpi0iUz20A+lPVhPHtNUA= github.com/coder/websocket v1.8.15/go.mod h1:NX3SzP+inril6yawo5CQXx8+fk145lPDC6pumgx0mVg= github.com/davecgh/go-spew v1.1.0 h1:ZDRjVQ15GmhC3fiQ8ni8+OwkZQO4DARzQgrnXU1Liz8= github.com/davecgh/go-spew v1.1.0/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38= +github.com/davecgh/go-spew v1.1.1 h1:vj9j/u1bqnvCEfJOwUhtlOARqs3+rkHYY13jYWTU97c= +github.com/davecgh/go-spew v1.1.1/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38= github.com/dchest/siphash v1.2.3 h1:QXwFc8cFOR2dSa/gE6o/HokBMWtLUaNDVd+22aKHeEA= github.com/dchest/siphash v1.2.3/go.mod h1:0NvQU092bT0ipiFN++/rXm69QG9tVxLAlQHIXMPAkHc= github.com/dgryski/go-bits v0.0.0-20180113010104-bd8a69a71dc2 h1:2+yip7nN/auel0PDwY7SIaTOxQPI2NwdkZkvpgtc3Pk= github.com/dgryski/go-bits v0.0.0-20180113010104-bd8a69a71dc2/go.mod h1:/9UYwwvZuEgp+mQ4960SHWCU1FS+FgdFX+m5ExFByNs= github.com/dgryski/go-marvin32 v0.0.0-20240117220238-0d39e8c5a8a9 h1:KOgsh3nPHIgGUJe+oJ5NhC8GpgHiWDd7PagBmerkxOw= github.com/dgryski/go-marvin32 v0.0.0-20240117220238-0d39e8c5a8a9/go.mod h1:jqLmu3zlC7A21QyKV/jo2F3W0IvHEAj00ZooZH+Y7jY= +github.com/golang/protobuf v1.3.1 h1:YF8+flBXS5eO826T4nzqPrxfhQThhXl0YzfuUPu4SBg= +github.com/golang/protobuf v1.3.1/go.mod h1:6lQm79b+lXiMfvg/cZm0SGofjICqVBUtrP5yJMmIC1U= github.com/golang/snappy v1.0.0 h1:Oy607GVXHs7RtbggtPBnr2RmDArIsAefDwvrdWvRhGs= github.com/golang/snappy v1.0.0/go.mod h1:/XxbfmMg8lxefKM7IXC3fBNl/7bRcc72aCRzEWrmP2Q= github.com/klauspost/compress v1.20.0 h1:a3C1ke2ohxFymNlb2HWAHjDeKCI90scRskErZkR0ezA= @@ -29,16 +37,22 @@ github.com/klauspost/cpuid v1.3.1 h1:5JNjFYYQrZeKRJ0734q51WCEEn2huer72Dc7K+R/b6s github.com/klauspost/cpuid v1.3.1/go.mod h1:bYW4mA6ZgKPob1/Dlai2LviZJO7KGI3uoWLd42rAQw4= github.com/klauspost/cpuid/v2 v2.4.0 h1:S6Hrbc7+ywsr0r+RLapfGBHfyefhCTwEh3A0tV913Dw= github.com/klauspost/cpuid/v2 v2.4.0/go.mod h1:19jmZ9mjzoF//ddRSUsv0zfBTJWh3QJh9FNxZTMrGxU= +github.com/klauspost/crc32 v1.3.0 h1:sSmTt3gUt81RP655XGZPElI0PelVTZ6YwCRnPSupoFM= +github.com/klauspost/crc32 v1.3.0/go.mod h1:D7kQaZhnkX/Y0tstFGf8VUzv2UofNGqCjnC3zdHB0Hw= github.com/klauspost/reedsolomon v1.14.2 h1:SafJYwpBBQBI6amHUygcjxZjXeN2HpiENHQDwuPWCCQ= github.com/klauspost/reedsolomon v1.14.2/go.mod h1:yjqqjgMTQkBUHSG97/rm4zipffCNbCiZcB3kTqr++sQ= github.com/minio/highwayhash v1.0.4 h1:asJizugGgchQod2ja9NJlGOWq4s7KsAWr5XUc9Clgl4= github.com/minio/highwayhash v1.0.4/go.mod h1:GGYsuwP/fPD6Y9hMiXuapVvlIUEhFhMTh0rxU3ik1LQ= +github.com/miscreant/miscreant v0.3.0 h1:bCn4zQMvNeeFBE3PWrG9ePFLPZyttBPhJ/WDqyqWrLQ= +github.com/miscreant/miscreant v0.3.0/go.mod h1:ZKWeIKfbJej2zjb1OUXJaaP1DnCb4yoTtcR90O7BOD4= github.com/modern-go/gls v0.0.0-20250215024828-78308f6bb19d h1:e3xdlObtriVu9HlrOfYB8Nmy51+DuJy5Hcgsg+x7ixg= github.com/modern-go/gls v0.0.0-20250215024828-78308f6bb19d/go.mod h1:I8AX+yW//L8Hshx6+a1m3bYkwXkpsVjA2795vP4f4oQ= github.com/modern-go/reflect2 v1.0.2 h1:xBagoLtFs94CBntxluKeaWgTMpvLxC4ur3nMaC9Gz0M= github.com/modern-go/reflect2 v1.0.2/go.mod h1:yWuevngMOJpCy52FWWMvUC8ws7m/LJsjYzDa0/r8luk= github.com/mschoch/smat v0.2.0 h1:8imxQsjDm8yFEAVBe7azKmKSgzSkZXDuKkSq9374khM= github.com/mschoch/smat v0.2.0/go.mod h1:kc9mz7DoBKqDyiRL7VZN8KvXQMWeTaVnttLRXOlotKw= +github.com/phuslu/log v1.0.134 h1:FZLg0lLe7eXqyRBK57mWDn45+qNVU74QaLNHk7EyOtw= +github.com/phuslu/log v1.0.134/go.mod h1:GYElPZLxBdIMMGZkGggLHDQ33zQJjqsHdJns+flCTyE= github.com/pierrec/lz4/v4 v4.1.29 h1:CDQY6qZOLI4DW0Nx6R1vRrifrCeQHnNXkMb0hZWXFjg= github.com/pierrec/lz4/v4 v4.1.29/go.mod h1:EoQMVJgeeEOMsCqCzqFm2O0cJvljX2nGZjcRIPL34O4= github.com/pierrec/lz4/v4 v4.1.30 h1:cchX8N2DVP668WkElI9QMwVyoNabLkq1LofDHFeIrdg= @@ -67,6 +81,8 @@ golang.org/x/crypto v0.57.0 h1:3ZVCjf8Ggz7zneR/EHRVx68Ctf+2pmIMP2UFhh9cC6M= golang.org/x/crypto v0.57.0/go.mod h1:Fdz0i5U6CoizGwLda9DttjSk6qlZo25zYNtR+ycvuZA= golang.org/x/net v0.59.0 h1:5zfYln+w5XCxwrnMMJPufRgNoXEaGxl0wo5GqPXyues= golang.org/x/net v0.59.0/go.mod h1:2DA/G1UfVbCpQPeWTmMPGY7Cs2PkBkwu743bVX5PIVg= +golang.org/x/sync v0.0.0-20190227155943-e225da77a7e6 h1:bjcUS9ztw9kFmmIxJInhon/0Is3p+EHBKNgquIzo1OI= +golang.org/x/sync v0.0.0-20190227155943-e225da77a7e6/go.mod h1:RxMgew5VJxzue5/jJTE5uejpjVlOe/izrB70Jof72aM= golang.org/x/sys v0.21.0/go.mod h1:/VUhepiaJMQUp4+oa/7Zr1D23ma6VTLIYjOOTFZPUcA= golang.org/x/sys v0.36.0 h1:KVRy2GtZBrk1cBYA7MKu5bEZFxQk4NIDV6RLVcC8o0k= golang.org/x/sys v0.36.0/go.mod h1:OgkHotnGiDImocRcuBABYBEXf8A9a87e/uXjp9XT3ks= diff --git a/testdata/corpus/reported-libraries.json b/testdata/corpus/reported-libraries.json index b11dcad4..66520ffc 100644 --- a/testdata/corpus/reported-libraries.json +++ b/testdata/corpus/reported-libraries.json @@ -783,6 +783,138 @@ "packages": ["github.com/tmthrgd/go-popcount"] } } + }, + { + "id": "aead-siphash", + "origin": "ecosystem-scan", + "module": "github.com/aead/siphash", + "version": "v1.0.1", + "inventory": { + "darwin/amd64": { + "asm_files": 1, + "packages": ["github.com/aead/siphash"] + }, + "linux/386": { + "asm_files": 1, + "packages": ["github.com/aead/siphash"] + }, + "linux/amd64": { + "asm_files": 1, + "packages": ["github.com/aead/siphash"] + }, + "windows/386": { + "asm_files": 1, + "packages": ["github.com/aead/siphash"] + }, + "windows/amd64": { + "asm_files": 1, + "packages": ["github.com/aead/siphash"] + } + } + }, + { + "id": "chain-txvm", + "origin": "ecosystem-scan", + "module": "github.com/chain/txvm", + "version": "v0.0.0-20190422181059-ff6bfbe53892", + "inventory": { + "darwin/amd64": { + "asm_files": 1, + "packages": ["github.com/chain/txvm/crypto/sha3"] + }, + "linux/amd64": { + "asm_files": 1, + "packages": ["github.com/chain/txvm/crypto/sha3"] + }, + "windows/amd64": { + "asm_files": 1, + "packages": ["github.com/chain/txvm/crypto/sha3"] + } + } + }, + { + "id": "klauspost-crc32", + "origin": "ecosystem-scan", + "module": "github.com/klauspost/crc32", + "version": "v1.3.0", + "inventory": { + "darwin/amd64": { + "asm_files": 1, + "packages": ["github.com/klauspost/crc32"] + }, + "darwin/arm64": { + "asm_files": 1, + "packages": ["github.com/klauspost/crc32"] + }, + "linux/amd64": { + "asm_files": 1, + "packages": ["github.com/klauspost/crc32"] + }, + "linux/arm64": { + "asm_files": 1, + "packages": ["github.com/klauspost/crc32"] + }, + "windows/amd64": { + "asm_files": 1, + "packages": ["github.com/klauspost/crc32"] + }, + "windows/arm64": { + "asm_files": 1, + "packages": ["github.com/klauspost/crc32"] + } + } + }, + { + "id": "phuslu-log", + "origin": "ecosystem-scan", + "module": "github.com/phuslu/log", + "version": "v1.0.134", + "inventory": { + "darwin/amd64": { + "asm_files": 2, + "packages": ["github.com/phuslu/log"] + }, + "darwin/arm64": { + "asm_files": 2, + "packages": ["github.com/phuslu/log"] + }, + "linux/386": { + "asm_files": 1, + "packages": ["github.com/phuslu/log"] + }, + "linux/amd64": { + "asm_files": 3, + "packages": ["github.com/phuslu/log"] + }, + "linux/arm": { + "asm_files": 1, + "packages": ["github.com/phuslu/log"] + }, + "linux/arm64": { + "asm_files": 3, + "packages": ["github.com/phuslu/log"] + }, + "windows/386": { + "asm_files": 1, + "packages": ["github.com/phuslu/log"] + }, + "windows/amd64": { + "asm_files": 2, + "packages": ["github.com/phuslu/log"] + }, + "windows/arm64": { + "asm_files": 2, + "packages": ["github.com/phuslu/log"] + }, + "js/wasm": { + "asm_files": 1, + "packages": ["github.com/phuslu/log"] + }, + "wasip1/wasm": { + "asm_files": 1, + "packages": ["github.com/phuslu/log"] + } + } } ] } diff --git a/testdata/coverage/arm64-go-assembler-families.txt b/testdata/coverage/arm64-go-assembler-families.txt index ce14fe95..d039b511 100644 --- a/testdata/coverage/arm64-go-assembler-families.txt +++ b/testdata/coverage/arm64-go-assembler-families.txt @@ -1,6 +1,25 @@ -# ARM64 scalar opcode families completed by the issue #2552 fix. -# The Go assembler encoder tables and positive testdata define this list's -# legal operand forms; external packages are regression consumers only. +# ARM64 opcode families with complete named-form coverage. The Go assembler +# encoder tables and positive testdata define this list's legal operand forms; +# external packages are regression consumers only. Raw-encoding completeness +# is enforced by each family's decoder tests rather than inferred from this list. +AESD +AESE +AESIMC +AESMC +SHA1C +SHA1H +SHA1M +SHA1P +SHA1SU0 +SHA1SU1 +SHA256H +SHA256H2 +SHA256SU0 +SHA256SU1 +SHA512H +SHA512H2 +SHA512SU0 +SHA512SU1 BFI BFIW BFXIL @@ -38,6 +57,14 @@ REV16W REV32 ASR ASRW +RBIT +RBITW +CLZ +CLZW +CLS +CLSW +VCLS +VCLZ LSL LSLW LSR @@ -46,8 +73,26 @@ ROR RORW SUBS SUBSW +ADDS +ADDSW +BIC +BICW +BICS +BICSW TST TSTW +FCCMPS +FCCMPD +FCCMPES +FCCMPED +FCMPS +FCMPD +FCMPES +FCMPED +VFMAXV +VFMINV +VFMAXNMV +VFMINNMV FMOVQ MOVB MOVBU diff --git a/testdata/coverage/arm64-xarch-plan9-baseline.json b/testdata/coverage/arm64-xarch-plan9-baseline.json index 9a51f9d7..53b33dc6 100644 --- a/testdata/coverage/arm64-xarch-plan9-baseline.json +++ b/testdata/coverage/arm64-xarch-plan9-baseline.json @@ -6,9 +6,9 @@ "asm_files": 1, "unique_ops": 667, "unique_forms": 1108, - "supported_forms": 379, - "context_forms": 54, - "unsupported_forms": 675, + "supported_forms": 752, + "context_forms": 76, + "unsupported_forms": 280, "parse_err_count": 0, - "coverage_fingerprint": "9530b87906a6aa540bc57a6011563a79b077baadfad88980da0d53d306e96881" + "coverage_fingerprint": "0805416cf50daf0ae78b6359f3e3cc3e0f51a5c2e2d1be89509177bb44bff050" } diff --git a/testdata/coverage/go-asm-baseline.json b/testdata/coverage/go-asm-baseline.json index 12f15ea1..471ac85b 100644 --- a/testdata/coverage/go-asm-baseline.json +++ b/testdata/coverage/go-asm-baseline.json @@ -31,15 +31,15 @@ "versions": { "go1.20": { "386": { - "context_forms": 6, - "coverage_fingerprint": "c44108e67d2b8dda3d332dbd2f7cbf08c6803cae1cd67712e83dfd999cf073df", + "context_forms": 7, + "coverage_fingerprint": "9b6b29fe6743c63fc53ad9d260faee77569d04b37724aaab0ee9002f10bad129", "official_opcodes": 1598, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 41, - "unique_forms": 59, + "supported_forms": 49, + "unique_forms": 56, "unique_ops": 20, - "unsupported_forms": 12, + "unsupported_forms": 0, "encoder_opcodes": 1601, "encoder_forms": 4996, "encoder_opcodes_observed_in_corpus": 19, @@ -47,44 +47,44 @@ }, "amd64": { "context_forms": 6, - "coverage_fingerprint": "074ec6a5f92c839df7173c7c44089a854e7ced6a5b4c67b2aee2327bfccbc63a", + "coverage_fingerprint": "69be09d0611061fb5059ca52de3d06ad11cebb8e627735458a3a8f1b0c297d52", "official_opcodes": 1598, "parse_err_count": 0, - "runtime_verified_forms": 35, - "supported_forms": 767, - "unique_forms": 6740, + "runtime_verified_forms": 51, + "supported_forms": 6731, + "unique_forms": 6738, "unique_ops": 1454, - "unsupported_forms": 5967, + "unsupported_forms": 1, "encoder_opcodes": 1601, "encoder_forms": 4996, "encoder_opcodes_observed_in_corpus": 1449, "encoder_fingerprint": "e369c64457f20a446a4e5c89736a5bb4a4b63d121710809d547cc171c571bcd1" }, "arm": { - "context_forms": 34, - "coverage_fingerprint": "7bd5f9d5b63a18fcdf2695c10bae78e582b3eed7dddbd69c2339bfd63e04438a", + "context_forms": 44, + "coverage_fingerprint": "bebce6de19fef7f88d32061a16036e1d270573ea513ce66dc1c599834277e456", "official_opcodes": 179, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 310, - "unique_forms": 498, + "supported_forms": 453, + "unique_forms": 497, "unique_ops": 133, - "unsupported_forms": 154, + "unsupported_forms": 0, "encoder_opcodes": 142, "encoder_forms": 526, "encoder_opcodes_observed_in_corpus": 127, "encoder_fingerprint": "9233f86c9bec14609e5ebd1bea4750ebc130871e476fb7a7ff07721253812fd2" }, "arm64": { - "context_forms": 45, - "coverage_fingerprint": "95931d2efbda61ed77dee4878a6d81003e0cca9c8c45cf403801ffff16da9467", + "context_forms": 66, + "coverage_fingerprint": "c491779c2bdce3968db4e74dfa0fda5a58d0174b6327499ef185c692e950f917", "official_opcodes": 608, "parse_err_count": 0, "runtime_verified_forms": 62, - "supported_forms": 452, + "supported_forms": 845, "unique_forms": 911, "unique_ops": 487, - "unsupported_forms": 414, + "unsupported_forms": 0, "encoder_opcodes": 444, "encoder_forms": 1397, "encoder_opcodes_observed_in_corpus": 393, @@ -108,15 +108,15 @@ }, "go1.21": { "386": { - "context_forms": 6, - "coverage_fingerprint": "9ac7af8e6cf867ac7e4e22669af5cc2db4d74434cca25faf4177e37e55c65dff", + "context_forms": 7, + "coverage_fingerprint": "a761cab88cc51f2073bb6215c65316cdda26c801e10ca41a346f3f39b18d9b3d", "official_opcodes": 1599, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 41, - "unique_forms": 60, + "supported_forms": 50, + "unique_forms": 57, "unique_ops": 21, - "unsupported_forms": 13, + "unsupported_forms": 0, "encoder_opcodes": 1602, "encoder_forms": 4997, "encoder_opcodes_observed_in_corpus": 20, @@ -124,44 +124,44 @@ }, "amd64": { "context_forms": 6, - "coverage_fingerprint": "2a0ed5b32f1a31014e35f9476063a5fee389209d941ee1e9b181420cea962a72", + "coverage_fingerprint": "85b56b99e338a71cf80fb6e4bbffe9a2551c8c4d9edebf34de9c86d45886f6c7", "official_opcodes": 1599, "parse_err_count": 0, - "runtime_verified_forms": 35, - "supported_forms": 767, - "unique_forms": 6741, + "runtime_verified_forms": 51, + "supported_forms": 6733, + "unique_forms": 6739, "unique_ops": 1455, - "unsupported_forms": 5968, + "unsupported_forms": 0, "encoder_opcodes": 1602, "encoder_forms": 4997, "encoder_opcodes_observed_in_corpus": 1450, "encoder_fingerprint": "ed66f1e1863c5e77ffa40f546092a958697bb7dcc186d88bfa26c49b75cb40c5" }, "arm": { - "context_forms": 34, - "coverage_fingerprint": "7bd5f9d5b63a18fcdf2695c10bae78e582b3eed7dddbd69c2339bfd63e04438a", + "context_forms": 44, + "coverage_fingerprint": "bebce6de19fef7f88d32061a16036e1d270573ea513ce66dc1c599834277e456", "official_opcodes": 179, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 310, - "unique_forms": 498, + "supported_forms": 453, + "unique_forms": 497, "unique_ops": 133, - "unsupported_forms": 154, + "unsupported_forms": 0, "encoder_opcodes": 142, "encoder_forms": 526, "encoder_opcodes_observed_in_corpus": 127, "encoder_fingerprint": "9233f86c9bec14609e5ebd1bea4750ebc130871e476fb7a7ff07721253812fd2" }, "arm64": { - "context_forms": 45, - "coverage_fingerprint": "816994965e8272f2528099ddb023f6656ffb6b26d4739a4b23b56940da4f1cdd", + "context_forms": 66, + "coverage_fingerprint": "55819d509fde7bef7f19d250ac7c8c1796d0eae119f43eb7301f78cb54104f20", "official_opcodes": 604, "parse_err_count": 0, "runtime_verified_forms": 62, - "supported_forms": 454, + "supported_forms": 879, "unique_forms": 945, "unique_ops": 487, - "unsupported_forms": 446, + "unsupported_forms": 0, "encoder_opcodes": 444, "encoder_forms": 1402, "encoder_opcodes_observed_in_corpus": 393, @@ -185,15 +185,15 @@ }, "go1.22": { "386": { - "context_forms": 6, - "coverage_fingerprint": "9ac7af8e6cf867ac7e4e22669af5cc2db4d74434cca25faf4177e37e55c65dff", + "context_forms": 7, + "coverage_fingerprint": "a761cab88cc51f2073bb6215c65316cdda26c801e10ca41a346f3f39b18d9b3d", "official_opcodes": 1599, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 41, - "unique_forms": 60, + "supported_forms": 50, + "unique_forms": 57, "unique_ops": 21, - "unsupported_forms": 13, + "unsupported_forms": 0, "encoder_opcodes": 1602, "encoder_forms": 4997, "encoder_opcodes_observed_in_corpus": 20, @@ -201,44 +201,44 @@ }, "amd64": { "context_forms": 6, - "coverage_fingerprint": "2a0ed5b32f1a31014e35f9476063a5fee389209d941ee1e9b181420cea962a72", + "coverage_fingerprint": "85b56b99e338a71cf80fb6e4bbffe9a2551c8c4d9edebf34de9c86d45886f6c7", "official_opcodes": 1599, "parse_err_count": 0, - "runtime_verified_forms": 35, - "supported_forms": 767, - "unique_forms": 6741, + "runtime_verified_forms": 51, + "supported_forms": 6733, + "unique_forms": 6739, "unique_ops": 1455, - "unsupported_forms": 5968, + "unsupported_forms": 0, "encoder_opcodes": 1602, "encoder_forms": 4997, "encoder_opcodes_observed_in_corpus": 1450, "encoder_fingerprint": "ed66f1e1863c5e77ffa40f546092a958697bb7dcc186d88bfa26c49b75cb40c5" }, "arm": { - "context_forms": 34, - "coverage_fingerprint": "7bd5f9d5b63a18fcdf2695c10bae78e582b3eed7dddbd69c2339bfd63e04438a", + "context_forms": 44, + "coverage_fingerprint": "bebce6de19fef7f88d32061a16036e1d270573ea513ce66dc1c599834277e456", "official_opcodes": 179, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 310, - "unique_forms": 498, + "supported_forms": 453, + "unique_forms": 497, "unique_ops": 133, - "unsupported_forms": 154, + "unsupported_forms": 0, "encoder_opcodes": 142, "encoder_forms": 526, "encoder_opcodes_observed_in_corpus": 127, "encoder_fingerprint": "9233f86c9bec14609e5ebd1bea4750ebc130871e476fb7a7ff07721253812fd2" }, "arm64": { - "context_forms": 47, - "coverage_fingerprint": "c8291a1d518d8e1651439e445eaad77da93fef4adc9fa94ebc95625086db8d84", + "context_forms": 68, + "coverage_fingerprint": "60870a1654d457a0afc8e54aa5e3c54b871ad29a788cc9df6aeeabade9b3a804", "official_opcodes": 606, "parse_err_count": 0, "runtime_verified_forms": 62, - "supported_forms": 454, + "supported_forms": 879, "unique_forms": 947, "unique_ops": 488, - "unsupported_forms": 446, + "unsupported_forms": 0, "encoder_opcodes": 444, "encoder_forms": 1444, "encoder_opcodes_observed_in_corpus": 394, @@ -262,15 +262,15 @@ }, "go1.23": { "386": { - "context_forms": 6, - "coverage_fingerprint": "9ac7af8e6cf867ac7e4e22669af5cc2db4d74434cca25faf4177e37e55c65dff", + "context_forms": 7, + "coverage_fingerprint": "a761cab88cc51f2073bb6215c65316cdda26c801e10ca41a346f3f39b18d9b3d", "official_opcodes": 1599, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 41, - "unique_forms": 60, + "supported_forms": 50, + "unique_forms": 57, "unique_ops": 21, - "unsupported_forms": 13, + "unsupported_forms": 0, "encoder_opcodes": 1602, "encoder_forms": 4997, "encoder_opcodes_observed_in_corpus": 20, @@ -278,44 +278,44 @@ }, "amd64": { "context_forms": 6, - "coverage_fingerprint": "2a0ed5b32f1a31014e35f9476063a5fee389209d941ee1e9b181420cea962a72", + "coverage_fingerprint": "85b56b99e338a71cf80fb6e4bbffe9a2551c8c4d9edebf34de9c86d45886f6c7", "official_opcodes": 1599, "parse_err_count": 0, - "runtime_verified_forms": 35, - "supported_forms": 767, - "unique_forms": 6741, + "runtime_verified_forms": 51, + "supported_forms": 6733, + "unique_forms": 6739, "unique_ops": 1455, - "unsupported_forms": 5968, + "unsupported_forms": 0, "encoder_opcodes": 1602, "encoder_forms": 4997, "encoder_opcodes_observed_in_corpus": 1450, "encoder_fingerprint": "ed66f1e1863c5e77ffa40f546092a958697bb7dcc186d88bfa26c49b75cb40c5" }, "arm": { - "context_forms": 34, - "coverage_fingerprint": "7bd5f9d5b63a18fcdf2695c10bae78e582b3eed7dddbd69c2339bfd63e04438a", + "context_forms": 44, + "coverage_fingerprint": "bebce6de19fef7f88d32061a16036e1d270573ea513ce66dc1c599834277e456", "official_opcodes": 179, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 310, - "unique_forms": 498, + "supported_forms": 453, + "unique_forms": 497, "unique_ops": 133, - "unsupported_forms": 154, + "unsupported_forms": 0, "encoder_opcodes": 142, "encoder_forms": 526, "encoder_opcodes_observed_in_corpus": 127, "encoder_fingerprint": "9233f86c9bec14609e5ebd1bea4750ebc130871e476fb7a7ff07721253812fd2" }, "arm64": { - "context_forms": 47, - "coverage_fingerprint": "2b989fc1d29f7bf5ad0ea040759c6d90cd350c0819de472a21d8080730a18200", + "context_forms": 68, + "coverage_fingerprint": "a09a6d62c104e8b51c47eba688a5f02e661b0f2f028bb9c7910acb06ffd5c960", "official_opcodes": 606, "parse_err_count": 0, "runtime_verified_forms": 62, - "supported_forms": 455, + "supported_forms": 880, "unique_forms": 948, "unique_ops": 488, - "unsupported_forms": 446, + "unsupported_forms": 0, "encoder_opcodes": 445, "encoder_forms": 1445, "encoder_opcodes_observed_in_corpus": 394, @@ -339,15 +339,15 @@ }, "go1.24": { "386": { - "context_forms": 6, - "coverage_fingerprint": "9ac7af8e6cf867ac7e4e22669af5cc2db4d74434cca25faf4177e37e55c65dff", + "context_forms": 7, + "coverage_fingerprint": "a761cab88cc51f2073bb6215c65316cdda26c801e10ca41a346f3f39b18d9b3d", "official_opcodes": 1599, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 41, - "unique_forms": 60, + "supported_forms": 50, + "unique_forms": 57, "unique_ops": 21, - "unsupported_forms": 13, + "unsupported_forms": 0, "encoder_opcodes": 1602, "encoder_forms": 4997, "encoder_opcodes_observed_in_corpus": 20, @@ -355,44 +355,44 @@ }, "amd64": { "context_forms": 6, - "coverage_fingerprint": "2a0ed5b32f1a31014e35f9476063a5fee389209d941ee1e9b181420cea962a72", + "coverage_fingerprint": "85b56b99e338a71cf80fb6e4bbffe9a2551c8c4d9edebf34de9c86d45886f6c7", "official_opcodes": 1599, "parse_err_count": 0, - "runtime_verified_forms": 35, - "supported_forms": 767, - "unique_forms": 6741, + "runtime_verified_forms": 51, + "supported_forms": 6733, + "unique_forms": 6739, "unique_ops": 1455, - "unsupported_forms": 5968, + "unsupported_forms": 0, "encoder_opcodes": 1602, "encoder_forms": 4997, "encoder_opcodes_observed_in_corpus": 1450, "encoder_fingerprint": "ed66f1e1863c5e77ffa40f546092a958697bb7dcc186d88bfa26c49b75cb40c5" }, "arm": { - "context_forms": 34, - "coverage_fingerprint": "edb4268d064f26136ec8e070e195e38ae31e1fdb2fe31294e66b068dc57dc1eb", + "context_forms": 44, + "coverage_fingerprint": "e4b40628c50da969e06d93552884a0c27e276a361d45cb221ccfc5c82c5a11bc", "official_opcodes": 181, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 312, - "unique_forms": 500, + "supported_forms": 455, + "unique_forms": 499, "unique_ops": 135, - "unsupported_forms": 154, + "unsupported_forms": 0, "encoder_opcodes": 144, "encoder_forms": 528, "encoder_opcodes_observed_in_corpus": 129, "encoder_fingerprint": "d48a5c9ffa187d1b998e7c5b4c447c90a9798cc0b778e7eff5c14f8dd193a108" }, "arm64": { - "context_forms": 47, - "coverage_fingerprint": "2b989fc1d29f7bf5ad0ea040759c6d90cd350c0819de472a21d8080730a18200", + "context_forms": 68, + "coverage_fingerprint": "a09a6d62c104e8b51c47eba688a5f02e661b0f2f028bb9c7910acb06ffd5c960", "official_opcodes": 606, "parse_err_count": 0, "runtime_verified_forms": 62, - "supported_forms": 455, + "supported_forms": 880, "unique_forms": 948, "unique_ops": 488, - "unsupported_forms": 446, + "unsupported_forms": 0, "encoder_opcodes": 445, "encoder_forms": 1445, "encoder_opcodes_observed_in_corpus": 394, @@ -416,15 +416,15 @@ }, "go1.25": { "386": { - "context_forms": 6, - "coverage_fingerprint": "9ac7af8e6cf867ac7e4e22669af5cc2db4d74434cca25faf4177e37e55c65dff", + "context_forms": 7, + "coverage_fingerprint": "a761cab88cc51f2073bb6215c65316cdda26c801e10ca41a346f3f39b18d9b3d", "official_opcodes": 1600, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 41, - "unique_forms": 60, + "supported_forms": 50, + "unique_forms": 57, "unique_ops": 21, - "unsupported_forms": 13, + "unsupported_forms": 0, "encoder_opcodes": 1603, "encoder_forms": 4998, "encoder_opcodes_observed_in_corpus": 20, @@ -432,44 +432,44 @@ }, "amd64": { "context_forms": 6, - "coverage_fingerprint": "d858d8ff078e13d327ca4f220b2096a6a8d58ca30a28a8ee74115c13be391752", + "coverage_fingerprint": "786c884a97756aff577826e58042c0f83ed97d42e7d754eb9d0aa1731205718c", "official_opcodes": 1600, "parse_err_count": 0, - "runtime_verified_forms": 35, - "supported_forms": 767, - "unique_forms": 6742, + "runtime_verified_forms": 51, + "supported_forms": 6734, + "unique_forms": 6740, "unique_ops": 1456, - "unsupported_forms": 5969, + "unsupported_forms": 0, "encoder_opcodes": 1603, "encoder_forms": 4998, "encoder_opcodes_observed_in_corpus": 1451, "encoder_fingerprint": "b5e0b0e2b61b69a007f387082aaa2f7c38c7fdc890c8d16c3e5e00e919144d4c" }, "arm": { - "context_forms": 34, - "coverage_fingerprint": "edb4268d064f26136ec8e070e195e38ae31e1fdb2fe31294e66b068dc57dc1eb", + "context_forms": 44, + "coverage_fingerprint": "e4b40628c50da969e06d93552884a0c27e276a361d45cb221ccfc5c82c5a11bc", "official_opcodes": 181, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 312, - "unique_forms": 500, + "supported_forms": 455, + "unique_forms": 499, "unique_ops": 135, - "unsupported_forms": 154, + "unsupported_forms": 0, "encoder_opcodes": 144, "encoder_forms": 528, "encoder_opcodes_observed_in_corpus": 129, "encoder_fingerprint": "d48a5c9ffa187d1b998e7c5b4c447c90a9798cc0b778e7eff5c14f8dd193a108" }, "arm64": { - "context_forms": 47, - "coverage_fingerprint": "8d90049669c26eeda4a3671b56da2eaceb99276e11cabe6066067b41f3ef9be2", + "context_forms": 68, + "coverage_fingerprint": "c5a10dbec4b7b9179cd8f235b381898d01862be2e89dfac7a2daee2f22de1370", "official_opcodes": 607, "parse_err_count": 0, "runtime_verified_forms": 62, - "supported_forms": 455, + "supported_forms": 881, "unique_forms": 949, "unique_ops": 489, - "unsupported_forms": 447, + "unsupported_forms": 0, "encoder_opcodes": 446, "encoder_forms": 1447, "encoder_opcodes_observed_in_corpus": 395, @@ -493,15 +493,15 @@ }, "go1.26": { "386": { - "context_forms": 6, - "coverage_fingerprint": "9ac7af8e6cf867ac7e4e22669af5cc2db4d74434cca25faf4177e37e55c65dff", + "context_forms": 7, + "coverage_fingerprint": "a761cab88cc51f2073bb6215c65316cdda26c801e10ca41a346f3f39b18d9b3d", "official_opcodes": 1600, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 41, - "unique_forms": 60, + "supported_forms": 50, + "unique_forms": 57, "unique_ops": 21, - "unsupported_forms": 13, + "unsupported_forms": 0, "encoder_opcodes": 1603, "encoder_forms": 4998, "encoder_opcodes_observed_in_corpus": 20, @@ -509,44 +509,44 @@ }, "amd64": { "context_forms": 6, - "coverage_fingerprint": "d858d8ff078e13d327ca4f220b2096a6a8d58ca30a28a8ee74115c13be391752", + "coverage_fingerprint": "786c884a97756aff577826e58042c0f83ed97d42e7d754eb9d0aa1731205718c", "official_opcodes": 1600, "parse_err_count": 0, - "runtime_verified_forms": 35, - "supported_forms": 767, - "unique_forms": 6742, + "runtime_verified_forms": 51, + "supported_forms": 6734, + "unique_forms": 6740, "unique_ops": 1456, - "unsupported_forms": 5969, + "unsupported_forms": 0, "encoder_opcodes": 1603, "encoder_forms": 4998, "encoder_opcodes_observed_in_corpus": 1451, "encoder_fingerprint": "b5e0b0e2b61b69a007f387082aaa2f7c38c7fdc890c8d16c3e5e00e919144d4c" }, "arm": { - "context_forms": 34, - "coverage_fingerprint": "edb4268d064f26136ec8e070e195e38ae31e1fdb2fe31294e66b068dc57dc1eb", + "context_forms": 44, + "coverage_fingerprint": "e4b40628c50da969e06d93552884a0c27e276a361d45cb221ccfc5c82c5a11bc", "official_opcodes": 181, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 312, - "unique_forms": 500, + "supported_forms": 455, + "unique_forms": 499, "unique_ops": 135, - "unsupported_forms": 154, + "unsupported_forms": 0, "encoder_opcodes": 144, "encoder_forms": 528, "encoder_opcodes_observed_in_corpus": 129, "encoder_fingerprint": "d48a5c9ffa187d1b998e7c5b4c447c90a9798cc0b778e7eff5c14f8dd193a108" }, "arm64": { - "context_forms": 47, - "coverage_fingerprint": "53b31063476d8a0ac4302c43b05620049ff67be89c346cccd1c61ad71b71d0b1", + "context_forms": 68, + "coverage_fingerprint": "f3aef4ea39c97304679260f98ec6ee3d92d6c77c3cc3dc571175f72fef4a5963", "official_opcodes": 613, "parse_err_count": 0, "runtime_verified_forms": 62, - "supported_forms": 455, + "supported_forms": 887, "unique_forms": 955, "unique_ops": 495, - "unsupported_forms": 453, + "unsupported_forms": 0, "encoder_opcodes": 450, "encoder_forms": 1451, "encoder_opcodes_observed_in_corpus": 401, @@ -570,15 +570,15 @@ }, "go1.27": { "386": { - "context_forms": 6, - "coverage_fingerprint": "9ac7af8e6cf867ac7e4e22669af5cc2db4d74434cca25faf4177e37e55c65dff", + "context_forms": 7, + "coverage_fingerprint": "a761cab88cc51f2073bb6215c65316cdda26c801e10ca41a346f3f39b18d9b3d", "official_opcodes": 1600, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 41, - "unique_forms": 60, + "supported_forms": 50, + "unique_forms": 57, "unique_ops": 21, - "unsupported_forms": 13, + "unsupported_forms": 0, "encoder_opcodes": 1603, "encoder_forms": 4997, "encoder_opcodes_observed_in_corpus": 20, @@ -586,44 +586,44 @@ }, "amd64": { "context_forms": 6, - "coverage_fingerprint": "d858d8ff078e13d327ca4f220b2096a6a8d58ca30a28a8ee74115c13be391752", + "coverage_fingerprint": "786c884a97756aff577826e58042c0f83ed97d42e7d754eb9d0aa1731205718c", "official_opcodes": 1600, "parse_err_count": 0, - "runtime_verified_forms": 35, - "supported_forms": 767, - "unique_forms": 6742, + "runtime_verified_forms": 51, + "supported_forms": 6734, + "unique_forms": 6740, "unique_ops": 1456, - "unsupported_forms": 5969, + "unsupported_forms": 0, "encoder_opcodes": 1603, "encoder_forms": 4997, "encoder_opcodes_observed_in_corpus": 1451, "encoder_fingerprint": "4341ad3acc9a810857665d1941f5f6329b514aeeb62667ac292c46b79fcd1a81" }, "arm": { - "context_forms": 34, - "coverage_fingerprint": "edb4268d064f26136ec8e070e195e38ae31e1fdb2fe31294e66b068dc57dc1eb", + "context_forms": 44, + "coverage_fingerprint": "e4b40628c50da969e06d93552884a0c27e276a361d45cb221ccfc5c82c5a11bc", "official_opcodes": 181, "parse_err_count": 0, "runtime_verified_forms": 0, - "supported_forms": 312, - "unique_forms": 500, + "supported_forms": 455, + "unique_forms": 499, "unique_ops": 135, - "unsupported_forms": 154, + "unsupported_forms": 0, "encoder_opcodes": 144, "encoder_forms": 528, "encoder_opcodes_observed_in_corpus": 129, "encoder_fingerprint": "d48a5c9ffa187d1b998e7c5b4c447c90a9798cc0b778e7eff5c14f8dd193a108" }, "arm64": { - "context_forms": 47, - "coverage_fingerprint": "4d297d36051af801c65e07a4010d3d07a8e081f4040d46ecadf894e19adbf451", + "context_forms": 68, + "coverage_fingerprint": "375e6ad3881b96ec7b98f566f3a04060569b35687790c8700a4aec1e27bd5f25", "official_opcodes": 1417, "parse_err_count": 0, "runtime_verified_forms": 62, - "supported_forms": 457, - "unique_forms": 1980, + "supported_forms": 1980, + "unique_forms": 2048, "unique_ops": 1281, - "unsupported_forms": 1476, + "unsupported_forms": 0, "encoder_opcodes": 1253, "encoder_forms": 2964, "encoder_opcodes_observed_in_corpus": 1187, diff --git a/testdata/discovery/README.md b/testdata/discovery/README.md new file mode 100644 index 00000000..42b71c9e --- /dev/null +++ b/testdata/discovery/README.md @@ -0,0 +1,154 @@ +# Go module assembly discovery ledger + +`ledger/` is the repository-owned checkpoint for newest-to-oldest scans of the +official Go module index. The history pass stops at 2019-04-10. Within one +logical module family, `/vN` major has priority first and Go semantic version +second: discovering `/v3` replaces `/v2` even if the `/v3` index record is +older, and still older `/v2` records are then skipped. It records the selected +exact `module@latest` version, including modules without Plan 9 assembly. +Assembly matches retain every `.s` path and architecture hint for all current +Go ports, including architectures plan9asm does not support yet; failures +remain eligible for retry. + +Results are deliberately stored as uncompressed, line-oriented JSON instead +of a binary gzip blob: + +```text +ledger/ + manifest.json + records/00.jsonl ... records/ff.jsonl +``` + +`sha256(module)[0]` selects one of 256 shards, so all records for a module stay +in one stable file. Records are sorted by module, Go semantic version, and +result kind. Updating the ledger replaces obsolete exact versions; a later +success also clears the corresponding retryable failure. Repository tests +validate the layout, shard ownership, ordering, and counts, and reject +committed `.gz` discovery results. + +Continue from this checkpoint without downloading completed versions again: + +```sh +go run ./cmd/plan9asmdiscover \ + -limit 20000 \ + -workers 64 \ + -traffic-report _out/discovery-traffic.json \ + -out-dir testdata/discovery/ledger +``` + +When `-out-dir` already exists, it is validated, used as the completed +exact-version checkpoint, and updated in place. The history upper bound is +derived from the earliest `index_ranges[].since`; a new ledger starts at the +current time. Because the official index only offers an ascending `since` +API, the scanner brackets complete time windows internally and selects their +newest records. It never splits a timestamp group, so a batch may contain +slightly more than `-limit` records without making the next reverse cursor lose +entries. Every committed interval and its exact entry count is retained in +`manifest.json` under `index_ranges`. Parsed-time ordering, identical adjacent +endpoints, and aggregate entry counts are checked whenever the ledger is read +or written; gaps, overlaps, and conflicting repeats are rejected. Thus no +manual cursor copying is part of normal operation. `-seen-report` remains +available for additional legacy JSON, gzip-compressed JSON, or sharded import +sources and is repeatable. Every selected module discovered in the index is +resolved to an exact `@latest` version before ZIP inspection. A completed exact +version is reused without another ZIP request. A higher module-path major, or a +higher Go semver within the current major, crosses the family checkpoint and is +resolved; lower majors and older versions do not cause metadata or ZIP traffic. +If `@latest` resolves to a higher-priority exact version, the old family's +scanned, matched, and failure records are removed. +For a new exact version, Discovery uses HEAD and range requests to read the ZIP +directory and candidate `.s` contents; it does not materialize the complete +module. Only `matched` versions are downloaded through the Go module cache by +the later corpus translation/LLVM compilation stage. + +`-traffic-report` writes one sorted JSON entry for every module that actually +made a request. It separates `@latest`, ZIP HEAD, ZIP range, and whole-small-ZIP +traffic, including retries, and gives per-module and run totals. Bytes mean +HTTP response entity bytes read with `Accept-Encoding: identity`; HTTP headers +and TLS/IP overhead are outside this application-level measurement. Index +traffic is reported separately because it does not belong to one module. A +module absent from the report made zero proxy requests. + +List the largest modules in one batch: + +```sh +jq -r '.modules[] | [.total_body_bytes, .total_requests, .module, + .resolved_version, .outcome] | @tsv' _out/discovery-traffic.json | + sort -nr | head -20 +``` + +`outcome` is `scanned`, `matched`, `failure`, `reused_scanned`, or +`reused_matched`. Reused modules normally make only the `@latest` metadata +request; their previously inspected exact ZIP is not fetched again. GitHub +pseudo-versions at the same commit also share successful ZIP inspection across +repository-path case aliases, including aliases encountered concurrently in +one batch. Semantic tags and case-sensitive module subdirectories are never +folded. + +`-workers` parallelizes module inspection inside one Discovery process. Ledger +publication remains single-writer and is protected by a sibling writer lock; +never launch concurrent processes targeting the same `-out-dir`, and do not +rewrite a ledger while corpus shards are reading it. Corpus shards themselves +may run in parallel because the ledger is read-only and each shard has a unique +report path. + +Run an incremental head scan whenever needed; it does not depend on the history +scan having reached 2019: + +```sh +go run ./cmd/plan9asmdiscover \ + -scan-mode incremental \ + -workers 64 \ + -out-dir testdata/discovery/ledger +``` + +Incremental mode derives its lower bound from the greatest committed +`index_ranges[].before` value and scans only up to the new current-time upper +bound. It always drains that interval and ignores `-limit`, so it cannot +publish a new high-water mark while leaving an unrecorded gap. A newly +published `/v3` is therefore processed even when `/v2` is the current family +checkpoint. Empty intervals are recorded with an exact zero count so the same +head window is not fetched repeatedly. History extends the earliest range and +incremental scanning extends the latest range, preserving one continuous +coverage chain in both directions. + +Retry retained failures without rereading the module index: + +```sh +go run ./cmd/plan9asmdiscover \ + -scan-mode retry \ + -workers 64 \ + -out-dir testdata/discovery/ledger +``` + +Validate the complete ledger and print both derived endpoints plus the funnel +counts at any time without network access: + +```sh +go run ./cmd/plan9asmdiscover -status \ + -out-dir testdata/discovery/ledger +``` + +The status read checks range continuity, the sum of range entry counts, all +manifest/record counts, shard ownership, semantic ordering, and duplicates. + +After adding a new supported target, its external assembly corpus can be +replayed directly from the saved exact versions without reading the module +index or revisiting no-assembly modules: + +```sh +for shard in $(seq 0 31); do + PLAN9ASM_DISCOVERY_TARGETS=linux/riscv64 \ + scripts/check-discovered-library-corpus.sh "$shard" 32 \ + "_out/discovered-library-corpus/riscv64-shard-$shard.json" +done +``` + +The target filter uses the recorded file paths. It conservatively retains +unsuffixed and custom-suffixed files, then fetches only those matched exact +versions and applies the current Go source/build-constraint checks before +translation and LLVM 22 compilation. + +The external-library discovery and compilation corpus uses Go 1.27 only. The +Go 1.20–1.27 matrix belongs exclusively to the separate official Go +toolchain/standard-library assembly corpus. diff --git a/testdata/discovery/ledger/manifest.json b/testdata/discovery/ledger/manifest.json new file mode 100644 index 00000000..ba8fed2b --- /dev/null +++ b/testdata/discovery/ledger/manifest.json @@ -0,0 +1,85 @@ +{ + "schema_version": 2, + "format": "plan9asmdiscover-jsonl-v1", + "generated_at": "2026-09-21T22:13:56.780749Z", + "scan_direction": "bidirectional", + "index_ranges": [ + { + "since": "2026-09-13T09:56:42.949703Z", + "before": "2026-09-13T14:59:13.837766Z", + "index_entries": 20000 + }, + { + "since": "2026-09-13T14:59:13.837766Z", + "before": "2026-09-13T19:21:04.961448Z", + "index_entries": 20000 + }, + { + "since": "2026-09-13T19:21:04.961448Z", + "before": "2026-09-13T23:53:29.47859Z", + "index_entries": 20000 + }, + { + "since": "2026-09-13T23:53:29.47859Z", + "before": "2026-09-13T23:53:30.945058Z", + "index_entries": 1 + }, + { + "since": "2026-09-13T23:53:30.945058Z", + "before": "2026-09-14T04:31:55.415018Z", + "index_entries": 19939 + }, + { + "since": "2026-09-14T04:31:55.415018Z", + "before": "2026-09-14T09:18:29.828394Z", + "index_entries": 20000 + }, + { + "since": "2026-09-14T09:18:29.828394Z", + "before": "2026-09-14T13:20:48.319799Z", + "index_entries": 20000 + }, + { + "since": "2026-09-14T13:20:48.319799Z", + "before": "2026-09-14T13:45:15.249393Z", + "index_entries": 2000 + }, + { + "since": "2026-09-14T13:45:15.249393Z", + "before": "2026-09-14T14:11:32.759987Z", + "index_entries": 1999 + }, + { + "since": "2026-09-14T14:11:32.759987Z", + "before": "2026-09-14T14:39:48.505112Z", + "index_entries": 2000 + }, + { + "since": "2026-09-14T14:39:48.505112Z", + "before": "2026-09-14T15:05:37.465297Z", + "index_entries": 2000 + }, + { + "since": "2026-09-14T15:05:37.465297Z", + "before": "2026-09-14T19:02:51.341026Z", + "index_entries": 20000 + }, + { + "since": "2026-09-14T19:02:51.341026Z", + "before": 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+{"kind":"scanned","module":"golang.org/x/image","version":"v0.46.0"} +{"kind":"scanned","module":"gopkg.in/jpoehls/gophermail.v0","version":"v0.0.0-20160410235621-62941eab772c"} +{"kind":"scanned","module":"gopkg.in/loremipsum.v1","version":"v1.1.0"} +{"kind":"scanned","module":"gopkg.in/oxequa/realize.v2","version":"v2.0.2"} +{"kind":"scanned","module":"megpoid.dev/go/contact-form","version":"v0.0.0-20260911232142-b003fca17094"} +{"kind":"scanned","module":"moul.io/graphman/viz","version":"v0.0.0-20210616043755-eef9a7ac05c7"} +{"kind":"scanned","module":"seehuhn.de/go/postscript","version":"v0.7.4"} +{"kind":"scanned","module":"sigs.k8s.io/cloud-provider-azure/pkg/azclient/trace","version":"v0.24.1"} diff --git a/toolchain_test.go b/toolchain_test.go index 92af9eda..01177933 100644 --- a/toolchain_test.go +++ b/toolchain_test.go @@ -36,6 +36,17 @@ func findLLVM22Tool(name string) string { candidates = append(candidates, filepath.Join(strings.TrimSpace(string(out)), name)) } else { candidates = append(candidates, name+"-22", name) + // Homebrew keeps versioned LLVM/LLD installations outside PATH. Keep + // these explicit candidates version-checked so an unversioned LLVM 23 + // tool can never become a silent fallback for the LLVM 22 tests. + for _, prefix := range []string{ + "/opt/homebrew/opt/llvm@22/bin", + "/opt/homebrew/opt/lld@22/bin", + "/usr/local/opt/llvm@22/bin", + "/usr/local/opt/lld@22/bin", + } { + candidates = append(candidates, filepath.Join(prefix, name)) + } } for _, candidate := range candidates { path, err := exec.LookPath(candidate) diff --git a/translate.go b/translate.go index 66d8b527..3db6cc3b 100644 --- a/translate.go +++ b/translate.go @@ -78,12 +78,43 @@ type FrameSlot struct { Offset int64 Type LLVMType Index int // index into LLVM function arguments (for Params) or results tuple (for Results) + // Name is the source-level Go parameter or result name when available. + // It lets legacy assembly with a stale numeric FP offset still identify a + // unique named result without weakening validation for anonymous or + // aggregate frame slots. + Name string // Field is the index of the extracted field within the argument aggregate. // It is used for classic Go asm slots like b_base+0(FP) when the Go-level // parameter is passed as a struct (string/slice header). // // When Field < 0, the slot refers directly to %arg(Index). Field int + // Fields carries a nested extractvalue path for arrays and structs. It is + // empty for direct values and one-level aggregates, which continue to use + // Field for compatibility with existing callers. + Fields []int +} + +func frameSlotFields(slot FrameSlot) []int { + if len(slot.Fields) != 0 { + return slot.Fields + } + if slot.Field >= 0 { + return []int{slot.Field} + } + return nil +} + +func frameSlotExtractSuffix(slot FrameSlot) string { + fields := frameSlotFields(slot) + if len(fields) == 0 { + return "" + } + parts := make([]string, len(fields)) + for i, field := range fields { + parts[i] = fmt.Sprintf("%d", field) + } + return ", " + strings.Join(parts, ", ") } // X87Mode selects how explicit x87 instructions in 386 Plan 9 assembly are @@ -154,6 +185,10 @@ func translateIRText(file *File, opt Options) (string, error) { if len(file.Funcs) == 0 && len(file.Data) == 0 && len(file.Globl) == 0 { return "", fmt.Errorf("empty file") } + file, err := normalizeX86RawFile(file, opt.Goarch) + if err != nil { + return "", err + } resolve := opt.ResolveSym if resolve == nil { @@ -214,13 +249,28 @@ func translateIRText(file *File, opt Options) (string, error) { if sig.Ret == "" { return "", fmt.Errorf("missing return type for %q", name) } + if file.Arch == ArchAMD64 && fn.X86RawText != nil { + if err := emitX86AddressSensitiveRawText(&b, *fn, sig); err != nil { + return "", fmt.Errorf("%s: %w", name, err) + } + b.WriteString("\n") + continue + } if err := validateResolvedImmediates(file.Arch, *fn); err != nil { return "", fmt.Errorf("%s: %w", name, err) } + if file.Arch == ArchAMD64 { + if err := validateAMD64ScalarAddSubFunction(opt.Goarch, *fn); err != nil { + return "", fmt.Errorf("%s: %w", name, err) + } + } if sig.Attrs == "" { sig.Attrs = attrRegistry.ref(inferFuncTargetFeaturesForGOARCH(file.Arch, opt.Goarch, *fn)) } - if file.Arch == ArchARM && funcNeedsARMCFG(*fn) { + // ARM is a fully supported target. Always use its architecture-aware CFG + // lowerer so even straight-line functions receive the same operand-form + // validation; the legacy linear prototype silently accepts unknown forms. + if file.Arch == ArchARM { if err := translateFuncARM(&b, *fn, sig, resolve, opt.Sigs, opt.AnnotateSource); err != nil { return "", fmt.Errorf("%s: %w", name, err) } @@ -234,7 +284,12 @@ func translateIRText(file *File, opt Options) (string, error) { b.WriteString("\n") continue } - if file.Arch == ArchAMD64 && (opt.Goarch == "386" || (opt.Goarch == "amd64" && funcNeedsAMD64CFG(*fn))) { + // X86 is fully supported. Always use its architecture-aware CFG lowerer + // so straight-line amd64 functions receive the same memory-width and + // operand-form semantics as functions containing branches or vector ops. + // The old linear prototype could silently reinterpret wide FP-frame stores + // as numeric conversions and leave adjacent aggregate result slots unwritten. + if file.Arch == ArchAMD64 { if err := translateFuncX86(&b, *fn, sig, resolve, opt.Sigs, opt.Goarch, opt.TargetTriple, opt.X87Mode, opt.AnnotateSource); err != nil { return "", fmt.Errorf("%s: %w", name, err) } @@ -254,6 +309,9 @@ func translateIRText(file *File, opt Options) (string, error) { b.WriteString("\n") } attrRegistry.emit(&b) + if fileUsesX86NonTemporalMetadata(file) { + b.WriteString("!0 = !{i32 1}\n\n") + } return b.String(), nil } @@ -366,12 +424,16 @@ func emitExternSBGlobals(b *strings.Builder, file *File, resolve func(string) st continue } s := strings.TrimSpace(arg.Sym) + indirect := strings.HasPrefix(s, "*") + if indirect { + s = strings.TrimSpace(strings.TrimPrefix(s, "*")) + } base, off, ok := parseSBRef(s) if !ok || base == "" { continue } base = strings.TrimPrefix(base, "$") - if off == 0 { + if off == 0 && !indirect { // Bare symbol refs are usually global data addresses // (e.g. MOVQ runtime·vdsoGettimeofdaySym(SB), AX). Exclude only // control-flow ops that use symbol operands as branch/call targets. @@ -582,13 +644,6 @@ func translateFuncLinear(b *strings.Builder, arch Arch, fn Func, sig FuncSig, an b.WriteString(" {\n") b.WriteString("entry:\n") - // Fast path: permissive void lowering for marker/stub functions. - if sig.Ret == Void { - b.WriteString(" ret void\n") - b.WriteString("}\n") - return nil - } - type ssaVal struct { typ LLVMType val string // either constant ("0") or SSA ("%t1") @@ -879,10 +934,10 @@ func translateFuncLinear(b *strings.Builder, arch Arch, fn Func, sig FuncSig, an return ssaVal{typ: I64, val: "0"}, nil } arg := fmt.Sprintf("%%arg%d", idx) - if slot.Field >= 0 { + if fields := frameSlotFields(slot); len(fields) != 0 { aggTy := sig.Args[idx] name := newTmp() - fmt.Fprintf(b, " %%%s = extractvalue %s %s, %d\n", name, aggTy, arg, slot.Field) + fmt.Fprintf(b, " %%%s = extractvalue %s %s%s\n", name, aggTy, arg, frameSlotExtractSuffix(slot)) return ssaVal{typ: slot.Type, val: "%" + name}, nil } return ssaVal{typ: slot.Type, val: arg}, nil @@ -1084,9 +1139,14 @@ func translateFuncLinear(b *strings.Builder, arch Arch, fn Func, sig FuncSig, an if err != nil { return err } - rhs, err := valueOf(src) - if err != nil { - return err + var rhs ssaVal + if (ins.Op == OpADDQ || ins.Op == OpSUBQ) && src.Kind == OpImm { + rhs = ssaVal{typ: I64, val: fmt.Sprintf("%d", amd64ScalarAddSubImmediateInt64(src.Imm, 64))} + } else { + rhs, err = valueOf(src) + if err != nil { + return err + } } lhs, err = emitCast(lhs, I64) if err != nil { diff --git a/translate_module.go b/translate_module.go index b47932d1..baee8599 100644 --- a/translate_module.go +++ b/translate_module.go @@ -12,6 +12,10 @@ import ( // // Caller owns the returned module and should call Dispose when finished. func TranslateModule(file *File, opt Options) (llvm.Module, error) { + file, err := normalizeX86RawFile(file, opt.Goarch) + if err != nil { + return llvm.Module{}, err + } mod, err := translateModuleDirect(file, opt) if err == nil { return finishTranslatedModule(file, mod) diff --git a/translate_module_direct.go b/translate_module_direct.go index f9e56ab8..0117d032 100644 --- a/translate_module_direct.go +++ b/translate_module_direct.go @@ -50,6 +50,10 @@ func translateModuleDirect(file *File, opt Options) (llvm.Module, error) { for i := range file.Funcs { fn := &file.Funcs[i] + if fn.X86RawText != nil { + mod.Dispose() + return llvm.Module{}, directUnsupportedf("address-sensitive x86 raw TEXT requires textual lowering for %s", fn.Sym) + } name := resolve(fn.Sym) sig, ok := opt.Sigs[name] if !ok { @@ -71,7 +75,13 @@ func translateModuleDirect(file *File, opt Options) (llvm.Module, error) { mod.Dispose() return llvm.Module{}, directUnsupportedf("%s: %v", name, err) } - if file.Arch == ArchARM && funcNeedsARMCFG(*fn) { + if file.Arch == ArchAMD64 { + if err := validateAMD64ScalarAddSubFunction(opt.Goarch, *fn); err != nil { + mod.Dispose() + return llvm.Module{}, fmt.Errorf("%s: %w", name, err) + } + } + if file.Arch == ArchARM { mod.Dispose() return llvm.Module{}, directUnsupportedf("arm CFG lowering required for %s", name) } @@ -278,8 +288,11 @@ func translateFuncLinearModule(mod llvm.Module, arch Arch, fn Func, sig FuncSig) return directValue{}, directUnsupportedf("FP slot %s invalid arg index %d", op.String(), slot.Index) } arg := args[slot.Index] - if slot.Field >= 0 { - ev := b.CreateExtractValue(arg, slot.Field, "") + if fields := frameSlotFields(slot); len(fields) != 0 { + ev := arg + for _, field := range fields { + ev = b.CreateExtractValue(ev, field, "") + } return directValue{typ: slot.Type, val: ev}, nil } return directValue{typ: slot.Type, val: arg}, nil @@ -353,6 +366,9 @@ func translateFuncLinearModule(mod llvm.Module, arch Arch, fn Func, sig FuncSig) return directUnsupportedf("MOVL expects 2 args") } src, dst := ins.Args[0], ins.Args[1] + if dst.Kind == OpFP && (src.Kind == OpFP || src.Kind == OpMem || src.Kind == OpSym) { + return fmt.Errorf("x86 MOVL does not allow memory-to-result-memory: %q", ins.Raw) + } v, err := valueOf(src) if err != nil { return err @@ -383,9 +399,19 @@ func translateFuncLinearModule(mod llvm.Module, arch Arch, fn Func, sig FuncSig) if err != nil { return err } - rhs, err := valueOf(src) - if err != nil { - return err + var rhs directValue + if (ins.Op == OpADDQ || ins.Op == OpSUBQ) && src.Kind == OpImm { + i64Ty, typeErr := llvmTypeFromLLVMType(ctx, I64) + if typeErr != nil { + return typeErr + } + normalized := amd64ScalarAddSubImmediateInt64(src.Imm, 64) + rhs = directValue{typ: I64, val: llvm.ConstInt(i64Ty, uint64(normalized), true)} + } else { + rhs, err = valueOf(src) + if err != nil { + return err + } } lhs, err = cast(lhs, I64) if err != nil { diff --git a/translate_prelude.go b/translate_prelude.go index 57bb4ee1..b99d3ef8 100644 --- a/translate_prelude.go +++ b/translate_prelude.go @@ -1,6 +1,9 @@ package plan9asm -import "strings" +import ( + "fmt" + "strings" +) func emitArchPrelude(b *strings.Builder, file *File, resolve func(string) string, goarch string, wasmABI WASMABI) { switch file.Arch { @@ -43,15 +46,14 @@ func emitWASMPrelude(b *strings.Builder, file *File, resolve func(string) string b.WriteString("\n") } want := make(map[string]bool) + wantFloatUnary := make(map[string]bool) for _, fn := range file.Funcs { for _, ins := range fn.Instrs { - switch normalizeInstructionOpcode(ins.Op) { - case "F64FLOOR": - want["floor"] = true - case "F64CEIL": - want["ceil"] = true - case "F64TRUNC": - want["trunc"] = true + op := normalizeInstructionOpcode(ins.Op) + if spec, ok := wasmFloatUnaryOps[op]; ok && spec.intrinsic != "" { + wantFloatUnary[string(spec.typ)+"|"+spec.intrinsic] = true + } + switch op { case "MEMORYCOPY": want["memmove"] = true case "MEMORYFILL": @@ -75,12 +77,18 @@ func emitWASMPrelude(b *strings.Builder, file *File, resolve func(string) string if want["memory.grow"] { b.WriteString("declare i32 @llvm.wasm.memory.grow.i32(i32, i32)\n") } - for _, name := range []string{"floor", "ceil", "trunc"} { - if want[name] { - b.WriteString("declare double @llvm." + name + ".f64(double)\n") + for _, typ := range []LLVMType{LLVMType("float"), LLVMType("double")} { + bits := "32" + if typ == LLVMType("double") { + bits = "64" + } + for _, name := range []string{"fabs", "ceil", "floor", "trunc", "roundeven", "sqrt"} { + if wantFloatUnary[string(typ)+"|"+name] { + fmt.Fprintf(b, "declare %s @llvm.%s.f%s(%s)\n", typ, name, bits, typ) + } } } - if len(want) != 0 { + if len(want) != 0 || len(wantFloatUnary) != 0 { b.WriteString("\n") } } diff --git a/types.go b/types.go index fa36d02b..45c296f8 100644 --- a/types.go +++ b/types.go @@ -32,17 +32,35 @@ const ( SP Reg = "SP" BP Reg = "BP" PC Reg = "PC" + ES Reg = "ES" + CS Reg = "CS" + SS Reg = "SS" + DS Reg = "DS" FS Reg = "FS" GS Reg = "GS" + // TLS is the x86 thread-local-storage pseudo-register used by the Go + // assembler both as a loadable base and as a relocation-only memory index. + TLS Reg = "TLS" - AL Reg = "AL" - AH Reg = "AH" - BL Reg = "BL" - BH Reg = "BH" - CL Reg = "CL" - CH Reg = "CH" - DL Reg = "DL" - DH Reg = "DH" + AL Reg = "AL" + AH Reg = "AH" + BL Reg = "BL" + BH Reg = "BH" + CL Reg = "CL" + CH Reg = "CH" + DL Reg = "DL" + DH Reg = "DH" + BPB Reg = "BPB" + SIB Reg = "SIB" + DIB Reg = "DIB" + R8B Reg = "R8B" + R9B Reg = "R9B" + R10B Reg = "R10B" + R11B Reg = "R11B" + R12B Reg = "R12B" + R13B Reg = "R13B" + R14B Reg = "R14B" + R15B Reg = "R15B" ZR Reg = "ZR" ) @@ -88,6 +106,8 @@ func parseReg(s string) (Reg, bool) { return FS, true case "GS": return GS, true + case "TLS": + return TLS, true case "AL": return AL, true case "AH": @@ -104,6 +124,28 @@ func parseReg(s string) (Reg, bool) { return DL, true case "DH": return DH, true + case "BPB": + return BPB, true + case "SIB": + return SIB, true + case "DIB": + return DIB, true + case "R8B": + return R8B, true + case "R9B": + return R9B, true + case "R10B": + return R10B, true + case "R11B": + return R11B, true + case "R12B": + return R12B, true + case "R13B": + return R13B, true + case "R14B": + return R14B, true + case "R15B": + return R15B, true case "ZR": return ZR, true case "G": @@ -141,6 +183,18 @@ func parseReg(s string) (Reg, bool) { return Reg(ss), true } } + if strings.HasPrefix(ss, "PN") && len(ss) >= 3 { + i := 2 + for i < len(ss) && ss[i] >= '0' && ss[i] <= '9' { + i++ + } + if i > 2 { + rest := ss[i:] + if rest == "" || strings.HasPrefix(rest, ".") || strings.HasPrefix(rest, "[") { + return Reg(ss), true + } + } + } if (strings.HasPrefix(ss, "X") || strings.HasPrefix(ss, "Y") || strings.HasPrefix(ss, "Z") || strings.HasPrefix(ss, "V") || strings.HasPrefix(ss, "F") || strings.HasPrefix(ss, "P")) && len(ss) >= 2 { i := 1 for i < len(ss) && ss[i] >= '0' && ss[i] <= '9' { @@ -152,7 +206,7 @@ func parseReg(s string) (Reg, bool) { if rest == "" { return Reg(ss), true } - if strings.HasPrefix(rest, ".") { + if strings.HasPrefix(rest, ".") || strings.HasPrefix(ss, "Z") && strings.HasPrefix(rest, "[") { return Reg(ss), true } } @@ -211,10 +265,11 @@ const ( type Operand struct { Kind OperandKind - Imm int64 // OpImm - ImmRaw string // OpImm unresolved symbolic placeholder, including leading '$' - Reg Reg // OpReg - Ext ExtendOp // OpRegExtend + Imm int64 // OpImm; floating immediates hold their float64 bit pattern + ImmRaw string // OpImm unresolved symbolic placeholder, including leading '$' + ImmIsFloat bool // OpImm originated from a floating constant expression + Reg Reg // OpReg + Ext ExtendOp // OpRegExtend // OpRegShift ShiftOp ShiftOp ShiftAmount int64 @@ -235,7 +290,8 @@ type Operand struct { // (R0)(R6) Mem MemRef - RegList []Reg // OpRegList (e.g. (R4, R8)) + RegList []Reg // OpRegList (e.g. (R4, R8)) + RegListRange bool // OpRegList originated from one range (e.g. [Z4.Q-Z5.Q]) } type MemRef struct { @@ -255,6 +311,9 @@ func (o Operand) String() string { if o.ImmRaw != "" { return o.ImmRaw } + if o.ImmIsFloat { + return "$(" + strconv.FormatFloat(math.Float64frombits(uint64(o.Imm)), 'g', -1, 64) + ")" + } return fmt.Sprintf("$%d", o.Imm) case OpReg: return string(o.Reg) @@ -393,6 +452,28 @@ func parseImmExpr(v string) (uint64, bool) { return evalImmExpr(expr) } +func parseVectorLengthScaleExpr(v string) (int64, bool) { + expr := strings.ToUpper(strings.ReplaceAll(strings.TrimSpace(v), " ", "")) + for strings.HasPrefix(expr, "(") && strings.HasSuffix(expr, ")") { + expr = strings.TrimSpace(expr[1 : len(expr)-1]) + } + sign := int64(1) + if strings.HasPrefix(expr, "-") { + sign = -1 + expr = strings.TrimPrefix(expr, "-") + } else { + expr = strings.TrimPrefix(expr, "+") + } + if !strings.HasPrefix(expr, "VL*") { + return 0, false + } + multiplier, err := strconv.ParseInt(strings.TrimPrefix(expr, "VL*"), 10, 64) + if err != nil || multiplier < 0 { + return 0, false + } + return sign * multiplier, true +} + func parseImmFloatExpr(v string) (float64, bool) { exprText := strings.TrimSpace(v) if exprText == "" { @@ -473,6 +554,19 @@ func evalImmExpr(e ast.Expr) (uint64, bool) { case *ast.ParenExpr: return evalImmExpr(x.X) case *ast.BasicLit: + if x.Kind == token.CHAR { + if len(x.Value) < 2 || x.Value[0] != '\'' { + return 0, false + } + value, _, tail, err := strconv.UnquoteChar(x.Value[1:], '\'') + if err != nil { + return 0, false + } + if tail != "'" { + return 0, false + } + return uint64(value), true + } if x.Kind != token.INT { return 0, false } @@ -552,21 +646,19 @@ func evalImmExpr(e ast.Expr) (uint64, bool) { } func parseFP(s string) (name string, off int64, ok bool) { - // Minimal: name+off(FP) - // Examples: a+0(FP), b+8(FP), ret+16(FP) + // Go accepts both name(FP) and name+off(FP) (including a negative + // displacement). The omitted displacement is exactly zero; generated + // assembly uses that spelling frequently for the first result slot. s = strings.TrimSpace(s) if !strings.HasSuffix(s, "(FP)") { return "", 0, false } - base := strings.TrimSuffix(s, "(FP)") - plus := strings.LastIndexByte(base, '+') - if plus <= 0 || plus == len(base)-1 { + base := strings.TrimSpace(strings.TrimSuffix(s, "(FP)")) + if base == "" { return "", 0, false } - name = strings.TrimSpace(base[:plus]) - offStr := strings.TrimSpace(base[plus+1:]) - off, err := strconv.ParseInt(offStr, 0, 64) - if err != nil { + name, off = splitSymPlusOff(base) + if name == "" || strings.IndexAny(name, " \t,()") >= 0 { return "", 0, false } return name, off, true @@ -595,7 +687,10 @@ func parseOperand(s string) (Operand, error) { } } if imm, ok := parseImm(s); ok { - op := Operand{Kind: OpImm, Imm: imm} + expr := strings.TrimSpace(strings.TrimPrefix(s, "$")) + _, integerExpression := parseImmExpr(expr) + _, floatingExpression := parseImmFloatExpr(expr) + op := Operand{Kind: OpImm, Imm: imm, ImmIsFloat: !integerExpression && floatingExpression} if isSymbolicImmPlaceholder(s) { expr := strings.TrimSpace(strings.TrimPrefix(s, "$")) if _, resolvedInt := parseImmExpr(expr); !resolvedInt { @@ -642,7 +737,7 @@ func parseOperand(s string) (Operand, error) { } regs = append(regs, rs...) } - return Operand{Kind: OpRegList, RegList: regs}, nil + return Operand{Kind: OpRegList, RegList: regs, RegListRange: len(parts) == 1 && strings.Contains(parts[0], "-")}, nil } // Register list: (R4, R8) if strings.HasPrefix(s, "(") && strings.HasSuffix(s, ")") && strings.Contains(s, ",") { @@ -863,13 +958,15 @@ type DataStmt struct { // GloblStmt models a minimal Plan 9 GLOBL directive: // -// GLOBL sym(SB), flags, $size +// GLOBL sym(SB), $size +// GLOBL sym(SB), flags, $size // // Flags are preserved as raw text for now (e.g. "RODATA"). type GloblStmt struct { - Sym string - Flags string - Size int64 + Sym string + Flags string + Size int64 + SizeRaw string // unresolved generated go_asm.h expression; translation rejects it } func parseIdent(s string) (string, bool) { @@ -946,6 +1043,24 @@ func parseMem(s string) (MemRef, bool) { if !strings.Contains(s, "(") || !strings.Contains(s, ")") { return MemRef{}, false } + // A displacement is a Go constant expression and may itself contain + // parentheses. Split from the final base-register group before the older + // left-to-right address parser so forms such as 0+(1*16)(BP) do not mistake + // the expression's first parenthesis for the address base. + if strings.HasSuffix(s, ")") { + if open := strings.LastIndexByte(s, '('); open > 0 { + prefix := strings.TrimSpace(s[:open]) + baseText := strings.TrimSpace(s[open+1 : len(s)-1]) + if base, ok := parseReg(baseText); ok { + if offset, ok := parseImmExpr(prefix); ok { + if base == FS || base == GS { + return MemRef{Segment: base, Off: int64(offset)}, true + } + return MemRef{Base: base, Off: int64(offset)}, true + } + } + } + } parseIndexScale := func(inner string) (idx Reg, ext ExtendOp, scale int64, ok bool) { inner = strings.TrimSpace(inner) @@ -1040,8 +1155,21 @@ func parseMem(s string) (MemRef, bool) { } return MemRef{Sym: offPart + "(SB)", Index: idx, IndexExt: ext, Scale: scale}, true } + // Go's ARM64 SVE vector-offset syntax prints the vector index before the + // scalar base, for example (Z6.S.SXTW<<2)(R14). Normalize that spelling to + // the MemRef Base/Index model before parseReg accepts the arranged Z name as + // an ordinary base register. + if offPart == "" && strings.HasPrefix(strings.ToUpper(baseStr), "Z") && strings.HasPrefix(rest, "(") && strings.HasSuffix(rest, ")") { + base2 := strings.TrimSpace(strings.TrimSuffix(strings.TrimPrefix(rest, "("), ")")) + if base, baseOK := parseReg(base2); baseOK { + if index, ext, scale, indexOK := parseIndexScale(baseStr); indexOK { + return MemRef{Base: base, Index: index, IndexExt: ext, Scale: scale}, true + } + } + } var off int64 + var offRaw string if offPart != "" { if n, err := strconv.ParseInt(offPart, 0, 64); err == nil { off = n @@ -1049,8 +1177,10 @@ func parseMem(s string) (MemRef, bool) { off = int64(u) } else { // Stack slots commonly use a descriptive name before their numeric - // displacement (for example control-4(SP)). Preserve the displacement; - // only an unresolved include-derived expression degrades to zero. + // displacement (for example control-4(SP)). Preserve both the source + // spelling and displacement so architecture validators can distinguish + // named stack slots from plain register-relative memory. + offRaw = offPart _, off = splitSymPlusOff(offPart) } } @@ -1068,6 +1198,12 @@ func parseMem(s string) (MemRef, bool) { mem := MemRef{Base: br, Off: 0} if u, ok := parseImmExpr(baseStr); ok { mem.Off = int64(u) + } else if idx, ext, scale, ok := parseIndexScale(baseStr); ok { + mem.Index = idx + mem.IndexExt = ext + mem.Scale = scale + } else if _, ok := parseVectorLengthScaleExpr(baseStr); ok { + mem.OffRaw = baseStr } rem := strings.TrimSpace(rest[j2+1:]) if rem == "" { @@ -1094,6 +1230,12 @@ func parseMem(s string) (MemRef, bool) { if u, ok := parseImmExpr(baseStr); ok { return MemRef{Base: br, Off: int64(u)}, true } + if idx, ext, scale, ok := parseIndexScale(baseStr); ok { + return MemRef{Base: br, Index: idx, IndexExt: ext, Scale: scale}, true + } + if _, ok := parseVectorLengthScaleExpr(baseStr); ok { + return MemRef{Base: br, OffRaw: baseStr}, true + } // Accept (symExpr)(REG) by degrading symExpr to offset 0 when // include-derived constants are unavailable in preprocessing. return MemRef{Base: br, Off: 0}, true @@ -1107,7 +1249,7 @@ func parseMem(s string) (MemRef, bool) { return MemRef{Base: "", Off: off, Index: idx, IndexExt: ext, Scale: scale}, true } - mem := MemRef{Base: base, Off: off} + mem := MemRef{Base: base, Off: off, OffRaw: offRaw} if base == FS || base == GS { mem.Base = "" mem.Segment = base diff --git a/types_deep_test.go b/types_deep_test.go index cd45f7e8..9656ce4a 100644 --- a/types_deep_test.go +++ b/types_deep_test.go @@ -178,9 +178,11 @@ func TestTypeParserEdgeCoverage(t *testing.T) { want bool }{ {"arg+8(FP)", true}, + {"arg(FP)", true}, + {"arg-8(FP)", true}, {"arg+8(SP)", false}, {"$ret+16(FP)", true}, - {"$ret(FP)", false}, + {"$ret(FP)", true}, } { if _, _, ok := parseFP(tc.in); ok != tc.want && tc.in[0] != '$' { t.Fatalf("parseFP(%q) ok = %v, want %v", tc.in, ok, tc.want) @@ -245,6 +247,14 @@ func TestTypeParserEdgeCoverage(t *testing.T) { t.Fatalf("parseOperand(%q) = (%v, %v), want kind %v", tc.in, err, op.Kind, tc.want) } } + rangeOperand, err := parseOperand("[Z4.Q-Z5.Q]") + if err != nil || !rangeOperand.RegListRange { + t.Fatalf("parseOperand(SVE range) = (%+v, %v), want range provenance", rangeOperand, err) + } + listOperand, err := parseOperand("[Z4.Q, Z5.Q]") + if err != nil || listOperand.RegListRange { + t.Fatalf("parseOperand(SVE list) = (%+v, %v), want non-range provenance", listOperand, err) + } if reg, ext, ok := parseRegExtend("r3.sxtw"); !ok || reg != "R3" || ext != ExtendSXTW { t.Fatalf("parseRegExtend(r3.sxtw) = (%q, %q, %v)", reg, ext, ok) } diff --git a/wasm_goabi_test.go b/wasm_goabi_test.go index 03d24d40..6728a0c9 100644 --- a/wasm_goabi_test.go +++ b/wasm_goabi_test.go @@ -59,6 +59,38 @@ TEXT unwind(SB), NOSPLIT, $0-0 } } +func TestWasmGoABIResumeDispatchOmitsCallsAfterTerminatingTailReturn(t *testing.T) { + file, err := Parse(ArchWASM, `TEXT caller(SB), NOSPLIT, $0-0 + CALL first(SB) + RET tail(SB) + CALL unreachable(SB) +`) + if err != nil { + t.Fatal(err) + } + sigs := map[string]FuncSig{ + "caller": {Name: "caller", Ret: Void}, + "first": {Name: "first", Ret: Void}, + "tail": {Name: "tail", Ret: Void}, + "unreachable": {Name: "unreachable", Ret: Void}, + } + ir, err := Translate(file, Options{ + TargetTriple: "wasm32-unknown-unknown", + Sigs: sigs, + Goarch: "wasm", + WASMABI: WASMABIGo, + }) + if err != nil { + t.Fatal(err) + } + if !strings.Contains(ir, "i32 1, label %wasm_resume_1") { + t.Fatalf("reachable CALL is absent from resume dispatch:\n%s", ir) + } + if strings.Contains(ir, "wasm_resume_2") { + t.Fatalf("unreachable CALL leaked into resume dispatch:\n%s", ir) + } +} + func TestWasmRETUNWINDRequiresGoABI(t *testing.T) { file, err := Parse(ArchWASM, "TEXT unwind(SB), NOSPLIT, $0-0\nRETUNWIND\n") if err != nil { diff --git a/wasm_ops.go b/wasm_ops.go index 63fd666b..ec56717a 100644 --- a/wasm_ops.go +++ b/wasm_ops.go @@ -15,6 +15,28 @@ type wasmMemoryStoreOp struct { storeType LLVMType } +type wasmFloatUnaryOp struct { + typ LLVMType + intrinsic string +} + +var wasmFloatUnaryOps = map[string]wasmFloatUnaryOp{ + "F32ABS": {LLVMType("float"), "fabs"}, + "F32NEG": {LLVMType("float"), ""}, + "F32CEIL": {LLVMType("float"), "ceil"}, + "F32FLOOR": {LLVMType("float"), "floor"}, + "F32TRUNC": {LLVMType("float"), "trunc"}, + "F32NEAREST": {LLVMType("float"), "roundeven"}, + "F32SQRT": {LLVMType("float"), "sqrt"}, + "F64ABS": {LLVMType("double"), "fabs"}, + "F64NEG": {LLVMType("double"), ""}, + "F64CEIL": {LLVMType("double"), "ceil"}, + "F64FLOOR": {LLVMType("double"), "floor"}, + "F64TRUNC": {LLVMType("double"), "trunc"}, + "F64NEAREST": {LLVMType("double"), "roundeven"}, + "F64SQRT": {LLVMType("double"), "sqrt"}, +} + var wasmIntegerBinaryOps = map[string]wasmIntegerOp{ "I32ADD": {I32, "add"}, "I32SUB": {I32, "sub"}, diff --git a/wasm_translate.go b/wasm_translate.go index 4b318f3f..b71a7b28 100644 --- a/wasm_translate.go +++ b/wasm_translate.go @@ -28,7 +28,21 @@ type wasmControlFrame struct { // LLVM SSA. The direct ABI maps FP operands through FuncSig.Frame. The Go ABI // instead recreates the official compiler's linear-memory stack, register // globals, resumable calls, and unwind return protocol. -func translateFuncWASM(b *strings.Builder, fn Func, sig FuncSig, resolve func(string) string, sigs map[string]FuncSig, wasmABI WASMABI, annotateSource bool) error { +func translateFuncWASM(b *strings.Builder, fn Func, sig FuncSig, resolve func(string) string, sigs map[string]FuncSig, wasmABI WASMABI, annotateSource bool) (err error) { + // LLVM's WebAssembly backend cannot lower blockaddress. Keep this as a + // lowering invariant so future control-flow or code-pointer work fails here + // instead of producing IR that only breaks later in llc. + output := b + outputStart := b.Len() + defer func() { + if err != nil { + return + } + if strings.Contains(output.String()[outputStart:], "blockaddress(") { + err = fmt.Errorf("wasm lowering emitted unsupported LLVM blockaddress in %s", sig.Name) + } + }() + useGoStack := wasmABI == WASMABIGo goABI := useGoStack && !sig.WASMNative physicalRet := sig.Ret @@ -308,9 +322,9 @@ func translateFuncWASM(b *strings.Builder, fn Func, sig FuncSig, resolve func(st return wasmValue{}, fmt.Errorf("FP parameter %s has invalid argument index %d", arg, slot.Index) } value := fmt.Sprintf("%%arg%d", slot.Index) - if slot.Field >= 0 { + if fields := frameSlotFields(slot); len(fields) != 0 { name := newTmp() - fmt.Fprintf(b, " %%%s = extractvalue %s %s, %d\n", name, sig.Args[slot.Index], value, slot.Field) + fmt.Fprintf(b, " %%%s = extractvalue %s %s%s\n", name, sig.Args[slot.Index], value, frameSlotExtractSuffix(slot)) value = "%" + name } return wasmValue{typ: slot.Type, val: value}, nil @@ -1011,20 +1025,17 @@ func translateFuncWASM(b *strings.Builder, fn Func, sig FuncSig, resolve func(st case "CALL", "CALLNORESUME": pcID++ callPCs[i] = pcID - if goABI && normalizeInstructionOpcode(ins.Op) == "CALL" { - resumeLabels[i] = fmt.Sprintf("wasm_resume_%d", pcID) - } } } } + var goABIOuter *strings.Builder if goABI { - b.WriteString(" switch i32 %pc_b, label %wasm_entry_body [") - for i := range fn.Instrs { - if label := resumeLabels[i]; label != "" { - fmt.Fprintf(b, " i32 %d, label %%%s", callPCs[i], label) - } - } - b.WriteString(" ]\nwasm_entry_body:\n") + // Build the function body separately so the entry dispatch can contain + // only resume labels that were actually emitted. A terminating tail + // return can make a later lexical CALL unreachable. + goABIOuter = b + b = &strings.Builder{} + b.WriteString("wasm_entry_body:\n") if fn.FrameSize != 0 { sp, err := loadRegister(SP) if err != nil { @@ -1061,6 +1072,34 @@ func translateFuncWASM(b *strings.Builder, fn Func, sig FuncSig, resolve func(st } continue } + if spec, ok := wasmFloatUnaryOps[op]; ok { + if len(ins.Args) != 0 { + return fmt.Errorf("%s is a zero-operand WebAssembly stack instruction", ins.Op) + } + value, err := pop(op) + if err != nil { + return err + } + if value.typ != spec.typ || value.stackAddr { + wantType := "f32" + if spec.typ == LLVMType("double") { + wantType = "f64" + } + return fmt.Errorf("%s expects %s, got %s", op, wantType, value.typ) + } + name := newTmp() + if spec.intrinsic == "" { + fmt.Fprintf(b, " %%%s = fneg %s %s\n", name, spec.typ, value.val) + } else { + bits := "32" + if spec.typ == LLVMType("double") { + bits = "64" + } + fmt.Fprintf(b, " %%%s = call %s @llvm.%s.f%s(%s %s)\n", name, spec.typ, spec.intrinsic, bits, spec.typ, value.val) + } + push(wasmValue{typ: spec.typ, val: "%" + name}) + continue + } if spec, ok := wasmMemoryLoadOps[op]; ok { if len(ins.Args) != 1 { return fmt.Errorf("%s expects one operand", ins.Op) @@ -1117,7 +1156,7 @@ func translateFuncWASM(b *strings.Builder, fn Func, sig FuncSig, resolve func(st continue } switch op { - case "NOP", "NO_LOCAL_POINTERS": + case "NOP", "NO_LOCAL_POINTERS", "FUNCDATA", "PCDATA": continue case "LABEL": if len(ins.Args) != 1 { @@ -1382,18 +1421,6 @@ func translateFuncWASM(b *strings.Builder, fn Func, sig FuncSig, resolve func(st if _, err := pop(op); err != nil { return err } - case "F64FLOOR", "F64CEIL", "F64TRUNC": - v, err := pop(op) - if err != nil { - return err - } - if v.typ != LLVMType("double") || v.stackAddr { - return fmt.Errorf("%s expects f64, got %s", op, v.typ) - } - intrinsic := strings.ToLower(strings.TrimPrefix(op, "F64")) - name := newTmp() - fmt.Fprintf(b, " %%%s = call double @llvm.%s.f64(double %s)\n", name, intrinsic, v.val) - push(wasmValue{typ: LLVMType("double"), val: "%" + name}) case "F64STORE": if len(ins.Args) != 1 || ins.Args[0].Kind != OpFP { return fmt.Errorf("F64Store expects an FP slot") @@ -1520,6 +1547,9 @@ func translateFuncWASM(b *strings.Builder, fn Func, sig FuncSig, resolve func(st // Only the Go ABI entry has a PC_B resume switch. Native helpers // still use the linear Go stack for calls, but continue directly // after a normally returning callee. + if op == "CALL" && goABI { + resumeLabels[insIndex] = fmt.Sprintf("wasm_resume_%d", callPCs[insIndex]) + } if err := emitGoCall(target, callPCs[insIndex], resumeLabels[insIndex], op == "CALL" && goABI); err != nil { return err } @@ -1601,6 +1631,18 @@ func translateFuncWASM(b *strings.Builder, fn Func, sig FuncSig, resolve func(st } } b.WriteString("}\n") + if goABI { + body := b.String() + b = goABIOuter + b.WriteString(" switch i32 %pc_b, label %wasm_entry_body [") + for i := range fn.Instrs { + if label := resumeLabels[i]; label != "" { + fmt.Fprintf(b, " i32 %d, label %%%s", callPCs[i], label) + } + } + b.WriteString(" ]\n") + b.WriteString(body) + } return nil } diff --git a/wasm_translate_test.go b/wasm_translate_test.go index e7f8dac8..1e64df2d 100644 --- a/wasm_translate_test.go +++ b/wasm_translate_test.go @@ -5,6 +5,116 @@ import ( "testing" ) +func TestTranslateWasmControlFlowAvoidsLLVMBlockAddress(t *testing.T) { + file, err := Parse(ArchWASM, `TEXT noBlockAddress(SB), NOSPLIT, $0-0 + I32Const $1 + If + I32Const $2 + Drop + Else + I32Const $3 + Drop + End + RET +`) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: "wasm32-unknown-unknown", + Goarch: "wasm", + Sigs: map[string]FuncSig{ + "noBlockAddress": {Name: "noBlockAddress", Ret: Void}, + }, + }) + if err != nil { + t.Fatal(err) + } + if strings.Contains(ir, "blockaddress(") { + t.Fatalf("WebAssembly lowering emitted LLVM blockaddress:\n%s", ir) + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "wasm32-unknown-unknown", "wasm-no-blockaddress.ll", "wasm-no-blockaddress.o", ir) +} + +func TestTranslateWasmFloatUnaryFamilyCompleteGo127Forms(t *testing.T) { + file, err := Parse(ArchWASM, ` +TEXT floatunary(SB),0,$0-0 + Get F0 + F32Abs + F32Neg + F32Ceil + F32Floor + F32Trunc + F32Nearest + F32Sqrt + Drop + Get F16 + F64Abs + F64Neg + F64Ceil + F64Floor + F64Trunc + F64Nearest + F64Sqrt + Drop + FUNCDATA $0, unaryargs(SB) + PCDATA $0, $0 + RET +`) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: "wasm32-unknown-unknown", + Goarch: "wasm", + Sigs: map[string]FuncSig{"floatunary": {Name: "floatunary", Ret: Void}}, + }) + if err != nil { + t.Fatal(err) + } + for _, want := range []string{ + "call float @llvm.fabs.f32", "fneg float", "call float @llvm.ceil.f32", + "call float @llvm.floor.f32", "call float @llvm.trunc.f32", "call float @llvm.roundeven.f32", + "call float @llvm.sqrt.f32", "call double @llvm.fabs.f64", "fneg double", + "call double @llvm.ceil.f64", "call double @llvm.floor.f64", "call double @llvm.trunc.f64", + "call double @llvm.roundeven.f64", "call double @llvm.sqrt.f64", + } { + if !strings.Contains(ir, want) { + t.Fatalf("wasm floating unary family IR missing %q:\n%s", want, ir) + } + } + llc := findLLVM22Tool("llc") + if llc == "" { + t.Fatal("LLVM 22 llc not found") + } + compileLLVMToObject(t, llc, "wasm32-unknown-unknown", "wasm-float-unary.ll", "wasm-float-unary.o", ir) +} + +func TestTranslateWasmFloatUnaryFamilyRejectsFormsOutsideGo127Opcodes(t *testing.T) { + for _, body := range []string{ + "F64Sqrt $1", + "F32Abs $1", + "I64Const $1\nF64Sqrt", + "I32Const $1\nF32Nearest", + } { + file, err := Parse(ArchWASM, "TEXT bad(SB),0,$0-0\n"+body+"\nDrop\nRET\n") + if err != nil { + continue + } + if _, err := Translate(file, Options{ + TargetTriple: "wasm32-unknown-unknown", + Goarch: "wasm", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }); err == nil { + t.Fatalf("Translate accepted wasm unary form outside Go 1.27 opcode semantics:\n%s", body) + } + } +} + func TestTranslateOfficialWasmFloorFunctions(t *testing.T) { file, err := Parse(ArchWASM, ` TEXT ·archFloor(SB),NOSPLIT,$0 diff --git a/x86_32bit_test.go b/x86_32bit_test.go index f067208e..0856f11f 100644 --- a/x86_32bit_test.go +++ b/x86_32bit_test.go @@ -1,6 +1,7 @@ package plan9asm import ( + "fmt" "os" "os/exec" "path/filepath" @@ -155,8 +156,6 @@ func TestTranslate386RejectsInvalidInstructionForms(t *testing.T) { {name: "cld operand", instruction: "CLD AX", want: "CLD takes no operands"}, {name: "std operand", instruction: "STD AX", want: "STD takes no operands"}, {name: "rep operand", instruction: "REP AX", want: "REP takes no operands"}, - {name: "repne movs", instruction: "REPN; MOVSB", want: "REPN is unsupported for MOVSB"}, - {name: "rep scas", instruction: "REP; SCASB", want: "REP SCASB is not yet supported"}, {name: "movsb operand", instruction: "MOVSB AX", want: "MOVSB takes no operands"}, {name: "rdtsc operand", instruction: "RDTSC AX", want: "RDTSC takes no operands"}, {name: "rdtscp operand", instruction: "RDTSCP AX", want: "RDTSCP takes no operands"}, @@ -170,34 +169,31 @@ func TestTranslate386RejectsInvalidInstructionForms(t *testing.T) { {name: "pushal operand", instruction: "PUSHAL AX", want: "PUSHAL takes no operands"}, {name: "popal operand", instruction: "POPAL AX", want: "POPAL takes no operands"}, {name: "unmodeled direct sp write", instruction: "XORL AX, SP", want: "direct SP write is unsupported"}, - {name: "cmpxchg8b destination", instruction: "CMPXCHG8B AX", want: "CMPXCHG8B expects mem"}, - {name: "cmpxchg8b segment", instruction: "CMPXCHG8B 0(FS)", want: "does not support segment-relative memory"}, {name: "fmovd count", instruction: "FMOVD F0", want: "FMOVD expects src, dst"}, - {name: "fmovd destination", instruction: "FMOVD F0, AX", want: "unsupported x87 double destination"}, - {name: "fmovdp count", instruction: "FMOVDP F0", want: "FMOVDP expects src, dst"}, - {name: "fmovdp destination", instruction: "FMOVDP F0, AX", want: "unsupported x87 double destination"}, - {name: "fmovv count", instruction: "FMOVV AX", want: "FMOVV expects src, dst"}, - {name: "fmovv destination", instruction: "FMOVV AX, F1", want: "FMOVV expects F0 destination"}, - {name: "fmovvp count", instruction: "FMOVVP F0", want: "FMOVVP expects src, dst"}, + {name: "fmovd destination", instruction: "FMOVD F0, AX", want: "FMOVD expects memory,F0"}, + {name: "fmovdp count", instruction: "FMOVDP F0", want: "FMOVDP expects F0 source"}, + {name: "fmovdp destination", instruction: "FMOVDP F0, AX", want: "FMOVDP expects F0 source"}, + {name: "fmovv count", instruction: "FMOVV AX", want: "FMOVV expects memory source"}, + {name: "fmovv destination", instruction: "FMOVV AX, F1", want: "FMOVV expects memory source"}, + {name: "fmovvp count", instruction: "FMOVVP F0", want: "FMOVVP expects F0 source"}, {name: "fmovvp source", instruction: "FMOVVP F1, 0(SP)", want: "FMOVVP expects F0 source"}, - {name: "fmovvp destination", instruction: "FMOVVP F0, AX", want: "unsupported x87 integer destination"}, + {name: "fmovvp destination", instruction: "FMOVVP F0, AX", want: "FMOVVP expects F0 source"}, {name: "fxchd count", instruction: "FXCHD F0", want: "FXCHD expects Fsrc, Fdst"}, {name: "fxchd registers", instruction: "FXCHD AX, BX", want: "FXCHD expects x87 registers"}, {name: "fdivd count", instruction: "FDIVD F0", want: "FDIVD expects src, dst"}, - {name: "fdivd destination", instruction: "FDIVD F0, $1", want: "unsupported x87 double destination"}, + {name: "fdivd destination", instruction: "FDIVD F0, $1", want: "FDIVD expects memory,F0"}, {name: "fadddp count", instruction: "FADDDP F0", want: "FADDDP expects src, dst"}, - {name: "fadddp destination", instruction: "FADDDP F0, $1", want: "unsupported x87 double destination"}, - {name: "fstcw count", instruction: "FSTCW", want: "FSTCW expects dst"}, + {name: "fadddp destination", instruction: "FADDDP F0, $1", want: "FADDDP expects F0 source"}, + {name: "fstcw count", instruction: "FSTCW", want: "FSTCW expects memory destination"}, {name: "fstcw destination", instruction: "FSTCW ret+0(FP)", want: "unsupported x87 word destination"}, - {name: "fldcw count", instruction: "FLDCW", want: "FLDCW expects src"}, + {name: "fldcw count", instruction: "FLDCW", want: "FLDCW expects memory source"}, {name: "frndint operand", instruction: "FRNDINT AX", want: "FRNDINT takes no operands"}, {name: "fabs operand", instruction: "FABS AX", want: "FABS takes no operands"}, {name: "fucomi count", instruction: "FUCOMI F0", want: "FUCOMI expects lhs, rhs"}, {name: "ftst operand", instruction: "FTST AX", want: "FTST takes no operands"}, - {name: "fstsw count", instruction: "FSTSW", want: "FSTSW expects dst"}, + {name: "fstsw count", instruction: "FSTSW", want: "FSTSW expects memory destination"}, {name: "fstsw destination", instruction: "FSTSW ret+0(FP)", want: "unsupported x87 word destination"}, {name: "fld1 operand", instruction: "FLD1 AX", want: "FLD1 takes no operands"}, - {name: "x87 on amd64", instruction: "FLD1", want: "requires GOARCH=386", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, {name: "pushl on amd64", instruction: "PUSHL AX", want: "requires GOARCH=386", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, {name: "popl on amd64", instruction: "POPL AX", want: "requires GOARCH=386", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, {name: "pushfl on amd64", instruction: "PUSHFL", want: "requires GOARCH=386", goarch: "amd64", triple: "x86_64-unknown-linux-gnu"}, @@ -900,7 +896,7 @@ TEXT frameAddress(SB),NOSPLIT,$0-12 for _, want := range []string{ "cmpxchg ptr", "@__plan9asm_rep_stosl", - "@__plan9asm_repne_scasb", + "@__plan9asm_rep_scasb", "@__plan9asm_movsb", "@__plan9asm_movsl", `asm sideeffect "fnstcw $0"`, @@ -925,12 +921,399 @@ TEXT frameAddress(SB),NOSPLIT,$0-12 t.Fatalf("386 IR missing %q:\n%s", want, ir) } } - if strings.Contains(ir, "roundeven") { + if strings.Contains(ir, "call double @llvm.roundeven") || strings.Contains(ir, "call float @llvm.roundeven") { t.Fatalf("386 x87 lowering unexpectedly depends on external roundeven:\n%s", ir) } compile386IR(t, ir, "instruction_families") } +func TestTranslate386X87MoveFamilyCompleteForms(t *testing.T) { + file, err := Parse(ArchAMD64, ` +TEXT x87moves(SB),NOSPLIT,$0-0 + FMOVB 0(SI), F0 + FMOVBP F0, 0(DI) + FMOVD 0(SI), F0 + FMOVD $(2.928932188134524e-01), F0 + FMOVD F0, 0(DI) + FMOVD F1, F0 + FMOVD F0, F1 + FMOVDP F0, 0(DI) + FMOVDP F0, F1 + FMOVF 0(SI), F0 + FMOVF F0, 0(DI) + FMOVFP F0, 0(DI) + FMOVL 0(SI), F0 + FMOVL F0, 0(DI) + FMOVLP F0, 0(DI) + FMOVV 0(SI), F0 + FMOVVP F0, 0(DI) + FMOVW 0(SI), F0 + FMOVW F0, 0(DI) + FMOVWP F0, 0(DI) + FMOVX 0(SI), F0 + FMOVXP F0, 0(DI) + RET +`) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"x87moves": {Name: "x87moves", Ret: Void}}, + X87Mode: X87Software, + }) + if err != nil { + t.Fatalf("Translate(complete x87 move family) error = %v", err) + } + compile386IR(t, ir, "x87_move_family") +} + +func TestTranslate386X87MoveFamilyRejectsNonGoForms(t *testing.T) { + for _, test := range []struct { + instruction string + want string + }{ + {instruction: "FMOVF F1, F0", want: "FMOVF expects memory source and F0 destination"}, + {instruction: "FMOVFP F1, 0(DI)", want: "FMOVFP expects F0 source and memory destination"}, + {instruction: "FMOVL 0(SI), F1", want: "FMOVL expects memory source and F0 destination"}, + {instruction: "FMOVLP F0, F1", want: "FMOVLP expects F0 source and memory destination"}, + {instruction: "FMOVX F0, F1", want: "FMOVX expects memory source and F0 destination"}, + {instruction: "FMOVXP F1, 0(DI)", want: "FMOVXP expects F0 source and memory destination"}, + } { + t.Run(test.instruction, func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n"+test.instruction+"\nRET\n") + if err != nil { + t.Fatal(err) + } + _, err = Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + if err == nil || !strings.Contains(err.Error(), test.want) { + t.Fatalf("Translate(%q) error = %v, want %q", test.instruction, err, test.want) + } + }) + } +} + +func TestTranslate386X87ConstantUnaryAndTranscendentalFamily(t *testing.T) { + file, err := Parse(ArchAMD64, ` +TEXT x87transcendental(SB),NOSPLIT,$0-0 + FBLD 0(SI) + FBSTP 0(DI) + FLD1 + FLDL2E + FLDL2T + FLDLG2 + FLDLN2 + FLDPI + FLDZ + F2XM1 + FABS + FCHS + FCLEX + FCOS + FDECSTP + FINCSTP + FINIT + FNOP + FPATAN + FPREM + FPREM1 + FPTAN + FRNDINT + FSCALE + FSIN + FSINCOS + FSQRT + FTST + FXAM + FXTRACT + FYL2X + FYL2XP1 + RET +`) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"x87transcendental": {Name: "x87transcendental", Ret: Void}}, + X87Mode: X87Software, + }) + if err != nil { + t.Fatalf("Translate(complete x87 constant/unary/transcendental family) error = %v", err) + } + compile386IR(t, ir, "x87_transcendental_family") +} + +func TestTranslate386X87ConstantUnaryAndTranscendentalFamilyRejectsOperands(t *testing.T) { + for _, op := range []string{ + "F2XM1", "FABS", "FCHS", "FCLEX", "FCOS", "FDECSTP", "FINCSTP", "FINIT", + "FLD1", "FLDL2E", "FLDL2T", "FLDLG2", "FLDLN2", "FLDPI", "FLDZ", "FNOP", + "FPATAN", "FPREM", "FPREM1", "FPTAN", "FRNDINT", "FSCALE", "FSIN", "FSINCOS", + "FSQRT", "FTST", "FXAM", "FXTRACT", "FYL2X", "FYL2XP1", + } { + t.Run(op, func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n"+op+" AX\nRET\n") + if err != nil { + t.Fatal(err) + } + _, err = Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + if err == nil || !strings.Contains(err.Error(), "takes no operands") { + t.Fatalf("Translate(%s AX) error = %v, want no-operand rejection", op, err) + } + }) + } + for _, test := range []struct { + instruction string + want string + }{ + {instruction: "FBLD F0", want: "FBLD expects memory source"}, + {instruction: "FBSTP AX", want: "FBSTP expects memory destination"}, + } { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n"+test.instruction+"\nRET\n") + if err != nil { + t.Fatal(err) + } + _, err = Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + if err == nil || !strings.Contains(err.Error(), test.want) { + t.Fatalf("Translate(%q) error = %v, want %q", test.instruction, err, test.want) + } + } +} + +func TestTranslate386X87ArithmeticFamilyCompleteForms(t *testing.T) { + var src strings.Builder + src.WriteString("TEXT x87arithmetic(SB),NOSPLIT,$0-0\n") + for _, stem := range []string{"FADD", "FMUL", "FSUB", "FSUBR", "FDIV", "FDIVR"} { + for _, width := range []string{"W", "L", "F"} { + fmt.Fprintf(&src, "\t%s%s 0(SI), F0\n", stem, width) + } + fmt.Fprintf(&src, "\t%sD 0(SI), F0\n", stem) + fmt.Fprintf(&src, "\t%sD F1, F0\n", stem) + fmt.Fprintf(&src, "\t%sD F0, F1\n", stem) + fmt.Fprintf(&src, "\t%sDP F0, F1\n", stem) + } + src.WriteString("\tRET\n") + file, err := Parse(ArchAMD64, src.String()) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"x87arithmetic": {Name: "x87arithmetic", Ret: Void}}, + X87Mode: X87Software, + }) + if err != nil { + t.Fatalf("Translate(complete x87 arithmetic family) error = %v", err) + } + compile386IR(t, ir, "x87_arithmetic_family") +} + +func TestTranslate386X87ArithmeticFamilyRejectsNonGoForms(t *testing.T) { + for _, test := range []struct { + instruction string + want string + }{ + {instruction: "FADDW F1, F0", want: "FADDW expects memory source and F0 destination"}, + {instruction: "FMULL 0(SI), F1", want: "FMULL expects memory source and F0 destination"}, + {instruction: "FSUBF F0, 0(DI)", want: "FSUBF expects memory source and F0 destination"}, + {instruction: "FDIVD 0(SI), F1", want: "FDIVD expects memory,F0"}, + {instruction: "FSUBRDP 0(SI), F0", want: "FSUBRDP expects F0 source and x87-register destination"}, + {instruction: "FDIVRDP F1, F0", want: "FDIVRDP expects F0 source and x87-register destination"}, + } { + t.Run(test.instruction, func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n"+test.instruction+"\nRET\n") + if err != nil { + t.Fatal(err) + } + _, err = Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + if err == nil || !strings.Contains(err.Error(), test.want) { + t.Fatalf("Translate(%q) error = %v, want %q", test.instruction, err, test.want) + } + }) + } +} + +func TestTranslate386X87CompareFamilyCompleteForms(t *testing.T) { + file, err := Parse(ArchAMD64, ` +TEXT x87compare(SB),NOSPLIT,$0-0 + FCOMD 0(SI), F0 + FCOMD F1, F0 + FCOMD F0, F1 + FCOMDP 0(SI), F0 + FCOMDP F1, F0 + FCOMDP F0, F1 + FCOMDPP F0, F1 + FCOMF 0(SI), F0 + FCOMFP 0(SI), F0 + FCOML 0(SI), F0 + FCOMLP 0(SI), F0 + FCOMW 0(SI), F0 + FCOMWP 0(SI), F0 + FCOMI F1, F0 + FCOMIP F1, F0 + FUCOM F0, F1 + FUCOMP F0, F1 + FUCOMPP F0, F1 + FUCOMI F0, F1 + FUCOMIP F0, F1 + RET +`) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"x87compare": {Name: "x87compare", Ret: Void}}, + X87Mode: X87Software, + }) + if err != nil { + t.Fatalf("Translate(complete x87 compare family) error = %v", err) + } + compile386IR(t, ir, "x87_compare_family") +} + +func TestTranslate386X87CompareFamilyRejectsNonGoForms(t *testing.T) { + for _, test := range []struct { + instruction string + want string + }{ + {instruction: "FCOMF F1, F0", want: "FCOMF expects memory source and F0 destination"}, + {instruction: "FCOMD 0(SI), F1", want: "FCOMD expects memory,F0"}, + {instruction: "FCOMDPP F1, F0", want: "FCOMDPP expects F0 source and x87-register destination"}, + {instruction: "FCOMI F0, F1", want: "FCOMI expects x87-register source and F0 destination"}, + {instruction: "FUCOM F1, F0", want: "FUCOM expects F0 source and x87-register destination"}, + {instruction: "FUCOMIP 0(SI), F0", want: "FUCOMIP expects F0 source and x87-register destination"}, + } { + t.Run(test.instruction, func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n"+test.instruction+"\nRET\n") + if err != nil { + t.Fatal(err) + } + _, err = Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + if err == nil || !strings.Contains(err.Error(), test.want) { + t.Fatalf("Translate(%q) error = %v, want %q", test.instruction, err, test.want) + } + }) + } +} + +func TestTranslate386LAHFSAHFFamily(t *testing.T) { + file, err := Parse(ArchAMD64, ` +TEXT flags386(SB),NOSPLIT,$0-0 + LAHF + SAHF + RET +`) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"flags386": {Name: "flags386", Ret: Void}}, + }) + if err != nil { + t.Fatalf("Translate(LAHF/SAHF) error = %v", err) + } + compile386IR(t, ir, "lahf_sahf_family") + for _, op := range []string{"LAHF", "SAHF"} { + bad, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n"+op+" AX\nRET\n") + if err != nil { + t.Fatal(err) + } + _, err = Translate(bad, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + if err == nil || !strings.Contains(err.Error(), "takes no operands") { + t.Fatalf("Translate(%s AX) error = %v, want no-operand rejection", op, err) + } + } +} + +func TestTranslate386X87EnvironmentAndControlFamily(t *testing.T) { + file, err := Parse(ArchAMD64, ` +TEXT x87environment(SB),NOSPLIT,$0-0 + FLDCW 0(SI) + FLDENV 0(SI) + FRSTOR 0(SI) + FSAVE 0(DI) + FSTCW 0(DI) + FSTENV 0(DI) + FSTSW 0(DI) + FSTSW AX + RET +`) + if err != nil { + t.Fatal(err) + } + ir, err := Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"x87environment": {Name: "x87environment", Ret: Void}}, + X87Mode: X87Software, + }) + if err != nil { + t.Fatalf("Translate(complete x87 environment/control family) error = %v", err) + } + compile386IR(t, ir, "x87_environment_family") +} + +func TestTranslate386X87EnvironmentAndControlFamilyRejectsNonGoForms(t *testing.T) { + for _, test := range []struct { + instruction string + want string + }{ + {instruction: "FLDCW AX", want: "FLDCW expects memory source"}, + {instruction: "FLDENV F0", want: "FLDENV expects memory source"}, + {instruction: "FRSTOR AX", want: "FRSTOR expects memory source"}, + {instruction: "FSAVE AX", want: "FSAVE expects memory destination"}, + {instruction: "FSTCW AX", want: "FSTCW expects memory destination"}, + {instruction: "FSTENV F0", want: "FSTENV expects memory destination"}, + {instruction: "FSTSW BX", want: "FSTSW expects memory destination or AX"}, + } { + t.Run(test.instruction, func(t *testing.T) { + file, err := Parse(ArchAMD64, "TEXT bad(SB),NOSPLIT,$0-0\n"+test.instruction+"\nRET\n") + if err != nil { + t.Fatal(err) + } + _, err = Translate(file, Options{ + TargetTriple: "i386-unknown-linux-gnu", + Goarch: "386", + Sigs: map[string]FuncSig{"bad": {Name: "bad", Ret: Void}}, + }) + if err == nil || !strings.Contains(err.Error(), test.want) { + t.Fatalf("Translate(%q) error = %v, want %q", test.instruction, err, test.want) + } + }) + } +} + func TestTranslate386X87Modes(t *testing.T) { hardware := translate386RoundingIR(t, X87Auto) for _, want := range []string{ @@ -986,7 +1369,7 @@ func TestTranslate386X87Modes(t *testing.T) { func TestTranslate386X87Codegen(t *testing.T) { llc := findLLVM22Tool("llc") if llc == "" { - t.Skip("llc not found") + t.Fatal("llc not found") } ir := translate386RoundingIR(t, X87Hardware) dir := t.TempDir() @@ -1013,7 +1396,7 @@ func TestTranslate386X87Codegen(t *testing.T) { args = append(args, "-filetype=asm", llPath, "-o", asmPath) if output, err := exec.Command(llc, args...).CombinedOutput(); err != nil { if unsupported386Target(string(output)) { - t.Skipf("llc lacks 386 target: %s", output) + t.Fatalf("llc lacks 386 target: %s", output) } t.Fatalf("llc failed: %v\n%s", err, output) } @@ -1185,7 +1568,7 @@ func compile386IR(t *testing.T, ir, name string) { t.Helper() llc := findLLVM22Tool("llc") if llc == "" { - t.Skip("llc not found") + t.Fatal("llc not found") } tmp := t.TempDir() llPath := filepath.Join(tmp, name+".ll") @@ -1196,7 +1579,7 @@ func compile386IR(t *testing.T, ir, name string) { cmd := exec.Command(llc, "-mtriple=i386-unknown-linux-gnu", "-filetype=obj", llPath, "-o", objPath) if out, err := cmd.CombinedOutput(); err != nil { if unsupported386Target(string(out)) { - t.Skipf("llc does not support i386: %s", strings.TrimSpace(string(out))) + t.Fatalf("llc does not support i386: %s", strings.TrimSpace(string(out))) } t.Fatalf("llc failed: %v\n%s", err, out) } @@ -1209,7 +1592,7 @@ func TestRuntimeExec386Core(t *testing.T) { llc := findLLVM22Tool("llc") clang := findLLVM22Tool("clang") if llc == "" || clang == "" { - t.Skip("llc/clang not found") + t.Fatal("llc/clang not found") } file, err := Parse(ArchAMD64, ` TEXT addCarry(SB),NOSPLIT,$0-12 diff --git a/x86_probe_context_test.go b/x86_probe_context_test.go new file mode 100644 index 00000000..4ca9d63b --- /dev/null +++ b/x86_probe_context_test.go @@ -0,0 +1,26 @@ +//go:build !llgo + +package plan9asm + +import ( + "errors" + "strings" + "testing" +) + +func TestProbe386LegacyImmediateJumpRequiresLayoutContext(t *testing.T) { + const source = "TEXT legacyJump(SB),$0-0\n\tJMP $4\n" + requireX86GoAssemblerResult(t, "386", source, true) + file, err := Parse(ArchAMD64, source) + if err != nil { + t.Fatal(err) + } + instruction := file.Funcs[0].Instrs[1] + err = ProbeInstruction(ArchAMD64, "386", instruction) + if !errors.Is(err, ErrProbeNeedsContext) { + t.Fatalf("ProbeInstruction(JMP $4) error = %v, want ErrProbeNeedsContext", err) + } + if !strings.Contains(err.Error(), "JMP $4") || !strings.Contains(err.Error(), "layout") { + t.Fatalf("context error does not explain the legacy relocation: %v", err) + } +}